1 /*
   2  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
  26 #define CPU_X86_VM_VM_VERSION_X86_HPP
  27 
  28 #include "runtime/globals_extension.hpp"
  29 #include "runtime/vm_version.hpp"
  30 
  31 class VM_Version : public Abstract_VM_Version {
  32   friend class VMStructs;
  33 public:
  34   // cpuid result register layouts.  These are all unions of a uint32_t
  35   // (in case anyone wants access to the register as a whole) and a bitfield.
  36 
  37   union StdCpuid1Eax {
  38     uint32_t value;
  39     struct {
  40       uint32_t stepping   : 4,
  41                model      : 4,
  42                family     : 4,
  43                proc_type  : 2,
  44                           : 2,
  45                ext_model  : 4,
  46                ext_family : 8,
  47                           : 4;
  48     } bits;
  49   };
  50 
  51   union StdCpuid1Ebx { // example, unused
  52     uint32_t value;
  53     struct {
  54       uint32_t brand_id         : 8,
  55                clflush_size     : 8,
  56                threads_per_cpu  : 8,
  57                apic_id          : 8;
  58     } bits;
  59   };
  60 
  61   union StdCpuid1Ecx {
  62     uint32_t value;
  63     struct {
  64       uint32_t sse3     : 1,
  65                clmul    : 1,
  66                         : 1,
  67                monitor  : 1,
  68                         : 1,
  69                vmx      : 1,
  70                         : 1,
  71                est      : 1,
  72                         : 1,
  73                ssse3    : 1,
  74                cid      : 1,
  75                         : 2,
  76                cmpxchg16: 1,
  77                         : 4,
  78                dca      : 1,
  79                sse4_1   : 1,
  80                sse4_2   : 1,
  81                         : 2,
  82                popcnt   : 1,
  83                         : 1,
  84                aes      : 1,
  85                         : 1,
  86                osxsave  : 1,
  87                avx      : 1,
  88                         : 3;
  89     } bits;
  90   };
  91 
  92   union StdCpuid1Edx {
  93     uint32_t value;
  94     struct {
  95       uint32_t          : 4,
  96                tsc      : 1,
  97                         : 3,
  98                cmpxchg8 : 1,
  99                         : 6,
 100                cmov     : 1,
 101                         : 3,
 102                clflush  : 1,
 103                         : 3,
 104                mmx      : 1,
 105                fxsr     : 1,
 106                sse      : 1,
 107                sse2     : 1,
 108                         : 1,
 109                ht       : 1,
 110                         : 3;
 111     } bits;
 112   };
 113 
 114   union DcpCpuid4Eax {
 115     uint32_t value;
 116     struct {
 117       uint32_t cache_type    : 5,
 118                              : 21,
 119                cores_per_cpu : 6;
 120     } bits;
 121   };
 122 
 123   union DcpCpuid4Ebx {
 124     uint32_t value;
 125     struct {
 126       uint32_t L1_line_size  : 12,
 127                partitions    : 10,
 128                associativity : 10;
 129     } bits;
 130   };
 131 
 132   union TplCpuidBEbx {
 133     uint32_t value;
 134     struct {
 135       uint32_t logical_cpus : 16,
 136                             : 16;
 137     } bits;
 138   };
 139 
 140   union ExtCpuid1Ecx {
 141     uint32_t value;
 142     struct {
 143       uint32_t LahfSahf     : 1,
 144                CmpLegacy    : 1,
 145                             : 3,
 146                lzcnt_intel  : 1,
 147                lzcnt        : 1,
 148                sse4a        : 1,
 149                misalignsse  : 1,
 150                prefetchw    : 1,
 151                             : 22;
 152     } bits;
 153   };
 154 
 155   union ExtCpuid1Edx {
 156     uint32_t value;
 157     struct {
 158       uint32_t           : 22,
 159                mmx_amd   : 1,
 160                mmx       : 1,
 161                fxsr      : 1,
 162                          : 4,
 163                long_mode : 1,
 164                tdnow2    : 1,
 165                tdnow     : 1;
 166     } bits;
 167   };
 168 
 169   union ExtCpuid5Ex {
 170     uint32_t value;
 171     struct {
 172       uint32_t L1_line_size : 8,
 173                L1_tag_lines : 8,
 174                L1_assoc     : 8,
 175                L1_size      : 8;
 176     } bits;
 177   };
 178 
 179   union ExtCpuid7Edx {
 180     uint32_t value;
 181     struct {
 182       uint32_t               : 8,
 183               tsc_invariance : 1,
 184                              : 23;
 185     } bits;
 186   };
 187 
 188   union ExtCpuid8Ecx {
 189     uint32_t value;
 190     struct {
 191       uint32_t cores_per_cpu : 8,
 192                              : 24;
 193     } bits;
 194   };
 195 
 196   union SefCpuid7Eax {
 197     uint32_t value;
 198   };
 199 
 200   union SefCpuid7Ebx {
 201     uint32_t value;
 202     struct {
 203       uint32_t fsgsbase : 1,
 204                         : 2,
 205                    bmi1 : 1,
 206                         : 1,
 207                    avx2 : 1,
 208                         : 2,
 209                    bmi2 : 1,
 210                    erms : 1,
 211                         : 1,
 212                     rtm : 1,
 213                         : 4,
 214                 avx512f : 1,
 215                avx512dq : 1,
 216                         : 1,
 217                     adx : 1,
 218                         : 6,
 219                avx512pf : 1,
 220                avx512er : 1,
 221                avx512cd : 1,
 222                         : 1,
 223                avx512bw : 1,
 224                avx512vl : 1;
 225     } bits;
 226   };
 227 
 228   union XemXcr0Eax {
 229     uint32_t value;
 230     struct {
 231       uint32_t x87     : 1,
 232                sse     : 1,
 233                ymm     : 1,
 234                bndregs : 1,
 235                bndcsr  : 1,
 236                opmask  : 1,
 237                zmm512  : 1,
 238                zmm32   : 1,
 239                        : 24;
 240     } bits;
 241   };
 242 
 243 protected:
 244   static int _cpu;
 245   static int _model;
 246   static int _stepping;
 247   static uint64_t _cpuFeatures; // features returned by the "cpuid" instruction
 248                                 // 0 if this instruction is not available
 249   static const char* _features_str;
 250 
 251   static address   _cpuinfo_segv_addr; // address of instruction which causes SEGV
 252   static address   _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
 253 
 254   enum {
 255     CPU_CX8      = (1 << 0), // next bits are from cpuid 1 (EDX)
 256     CPU_CMOV     = (1 << 1),
 257     CPU_FXSR     = (1 << 2),
 258     CPU_HT       = (1 << 3),
 259     CPU_MMX      = (1 << 4),
 260     CPU_3DNOW_PREFETCH = (1 << 5), // Processor supports 3dnow prefetch and prefetchw instructions
 261                                    // may not necessarily support other 3dnow instructions
 262     CPU_SSE      = (1 << 6),
 263     CPU_SSE2     = (1 << 7),
 264     CPU_SSE3     = (1 << 8),  // SSE3 comes from cpuid 1 (ECX)
 265     CPU_SSSE3    = (1 << 9),
 266     CPU_SSE4A    = (1 << 10),
 267     CPU_SSE4_1   = (1 << 11),
 268     CPU_SSE4_2   = (1 << 12),
 269     CPU_POPCNT   = (1 << 13),
 270     CPU_LZCNT    = (1 << 14),
 271     CPU_TSC      = (1 << 15),
 272     CPU_TSCINV   = (1 << 16),
 273     CPU_AVX      = (1 << 17),
 274     CPU_AVX2     = (1 << 18),
 275     CPU_AES      = (1 << 19),
 276     CPU_ERMS     = (1 << 20), // enhanced 'rep movsb/stosb' instructions
 277     CPU_CLMUL    = (1 << 21), // carryless multiply for CRC
 278     CPU_BMI1     = (1 << 22),
 279     CPU_BMI2     = (1 << 23),
 280     CPU_RTM      = (1 << 24), // Restricted Transactional Memory instructions
 281     CPU_ADX      = (1 << 25),
 282     CPU_AVX512F  = (1 << 26), // AVX 512bit foundation instructions
 283     CPU_AVX512DQ = (1 << 27),
 284     CPU_AVX512PF = (1 << 28),
 285     CPU_AVX512ER = (1 << 29),
 286     CPU_AVX512CD = (1 << 30),
 287     CPU_AVX512BW = (1 << 31)
 288   } cpuFeatureFlags;
 289 
 290 #define CPU_AVX512VL UCONST64(0x100000000) // EVEX instructions with smaller vector length : enums are limited to 32bit
 291 
 292   enum {
 293     // AMD
 294     CPU_FAMILY_AMD_11H       = 0x11,
 295     // Intel
 296     CPU_FAMILY_INTEL_CORE    = 6,
 297     CPU_MODEL_NEHALEM        = 0x1e,
 298     CPU_MODEL_NEHALEM_EP     = 0x1a,
 299     CPU_MODEL_NEHALEM_EX     = 0x2e,
 300     CPU_MODEL_WESTMERE       = 0x25,
 301     CPU_MODEL_WESTMERE_EP    = 0x2c,
 302     CPU_MODEL_WESTMERE_EX    = 0x2f,
 303     CPU_MODEL_SANDYBRIDGE    = 0x2a,
 304     CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
 305     CPU_MODEL_IVYBRIDGE_EP   = 0x3a,
 306     CPU_MODEL_HASWELL_E3     = 0x3c,
 307     CPU_MODEL_HASWELL_E7     = 0x3f,
 308     CPU_MODEL_BROADWELL      = 0x3d,
 309     CPU_MODEL_SKYLAKE        = CPU_MODEL_HASWELL_E3
 310   } cpuExtendedFamily;
 311 
 312   // cpuid information block.  All info derived from executing cpuid with
 313   // various function numbers is stored here.  Intel and AMD info is
 314   // merged in this block: accessor methods disentangle it.
 315   //
 316   // The info block is laid out in subblocks of 4 dwords corresponding to
 317   // eax, ebx, ecx and edx, whether or not they contain anything useful.
 318   struct CpuidInfo {
 319     // cpuid function 0
 320     uint32_t std_max_function;
 321     uint32_t std_vendor_name_0;
 322     uint32_t std_vendor_name_1;
 323     uint32_t std_vendor_name_2;
 324 
 325     // cpuid function 1
 326     StdCpuid1Eax std_cpuid1_eax;
 327     StdCpuid1Ebx std_cpuid1_ebx;
 328     StdCpuid1Ecx std_cpuid1_ecx;
 329     StdCpuid1Edx std_cpuid1_edx;
 330 
 331     // cpuid function 4 (deterministic cache parameters)
 332     DcpCpuid4Eax dcp_cpuid4_eax;
 333     DcpCpuid4Ebx dcp_cpuid4_ebx;
 334     uint32_t     dcp_cpuid4_ecx; // unused currently
 335     uint32_t     dcp_cpuid4_edx; // unused currently
 336 
 337     // cpuid function 7 (structured extended features)
 338     SefCpuid7Eax sef_cpuid7_eax;
 339     SefCpuid7Ebx sef_cpuid7_ebx;
 340     uint32_t     sef_cpuid7_ecx; // unused currently
 341     uint32_t     sef_cpuid7_edx; // unused currently
 342 
 343     // cpuid function 0xB (processor topology)
 344     // ecx = 0
 345     uint32_t     tpl_cpuidB0_eax;
 346     TplCpuidBEbx tpl_cpuidB0_ebx;
 347     uint32_t     tpl_cpuidB0_ecx; // unused currently
 348     uint32_t     tpl_cpuidB0_edx; // unused currently
 349 
 350     // ecx = 1
 351     uint32_t     tpl_cpuidB1_eax;
 352     TplCpuidBEbx tpl_cpuidB1_ebx;
 353     uint32_t     tpl_cpuidB1_ecx; // unused currently
 354     uint32_t     tpl_cpuidB1_edx; // unused currently
 355 
 356     // ecx = 2
 357     uint32_t     tpl_cpuidB2_eax;
 358     TplCpuidBEbx tpl_cpuidB2_ebx;
 359     uint32_t     tpl_cpuidB2_ecx; // unused currently
 360     uint32_t     tpl_cpuidB2_edx; // unused currently
 361 
 362     // cpuid function 0x80000000 // example, unused
 363     uint32_t ext_max_function;
 364     uint32_t ext_vendor_name_0;
 365     uint32_t ext_vendor_name_1;
 366     uint32_t ext_vendor_name_2;
 367 
 368     // cpuid function 0x80000001
 369     uint32_t     ext_cpuid1_eax; // reserved
 370     uint32_t     ext_cpuid1_ebx; // reserved
 371     ExtCpuid1Ecx ext_cpuid1_ecx;
 372     ExtCpuid1Edx ext_cpuid1_edx;
 373 
 374     // cpuid functions 0x80000002 thru 0x80000004: example, unused
 375     uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
 376     uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
 377     uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
 378 
 379     // cpuid function 0x80000005 // AMD L1, Intel reserved
 380     uint32_t     ext_cpuid5_eax; // unused currently
 381     uint32_t     ext_cpuid5_ebx; // reserved
 382     ExtCpuid5Ex  ext_cpuid5_ecx; // L1 data cache info (AMD)
 383     ExtCpuid5Ex  ext_cpuid5_edx; // L1 instruction cache info (AMD)
 384 
 385     // cpuid function 0x80000007
 386     uint32_t     ext_cpuid7_eax; // reserved
 387     uint32_t     ext_cpuid7_ebx; // reserved
 388     uint32_t     ext_cpuid7_ecx; // reserved
 389     ExtCpuid7Edx ext_cpuid7_edx; // tscinv
 390 
 391     // cpuid function 0x80000008
 392     uint32_t     ext_cpuid8_eax; // unused currently
 393     uint32_t     ext_cpuid8_ebx; // reserved
 394     ExtCpuid8Ecx ext_cpuid8_ecx;
 395     uint32_t     ext_cpuid8_edx; // reserved
 396 
 397     // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
 398     XemXcr0Eax   xem_xcr0_eax;
 399     uint32_t     xem_xcr0_edx; // reserved
 400 
 401     // Space to save ymm registers after signal handle
 402     int          ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
 403 
 404     // Space to save zmm registers after signal handle
 405     int          zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
 406   };
 407 
 408   // The actual cpuid info block
 409   static CpuidInfo _cpuid_info;
 410 
 411   // Extractors and predicates
 412   static uint32_t extended_cpu_family() {
 413     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
 414     result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
 415     return result;
 416   }
 417 
 418   static uint32_t extended_cpu_model() {
 419     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
 420     result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
 421     return result;
 422   }
 423 
 424   static uint32_t cpu_stepping() {
 425     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
 426     return result;
 427   }
 428 
 429   static uint logical_processor_count() {
 430     uint result = threads_per_core();
 431     return result;
 432   }
 433 
 434   static uint64_t feature_flags() {
 435     uint64_t result = 0;
 436     if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
 437       result |= CPU_CX8;
 438     if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
 439       result |= CPU_CMOV;
 440     if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd() &&
 441         _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
 442       result |= CPU_FXSR;
 443     // HT flag is set for multi-core processors also.
 444     if (threads_per_core() > 1)
 445       result |= CPU_HT;
 446     if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd() &&
 447         _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
 448       result |= CPU_MMX;
 449     if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
 450       result |= CPU_SSE;
 451     if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
 452       result |= CPU_SSE2;
 453     if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
 454       result |= CPU_SSE3;
 455     if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
 456       result |= CPU_SSSE3;
 457     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
 458       result |= CPU_SSE4_1;
 459     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
 460       result |= CPU_SSE4_2;
 461     if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
 462       result |= CPU_POPCNT;
 463     if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
 464         _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
 465         _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
 466         _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
 467       result |= CPU_AVX;
 468       if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
 469         result |= CPU_AVX2;
 470       if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
 471           _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
 472           _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
 473           _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
 474         result |= CPU_AVX512F;
 475         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
 476           result |= CPU_AVX512CD;
 477         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
 478           result |= CPU_AVX512DQ;
 479         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
 480           result |= CPU_AVX512PF;
 481         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
 482           result |= CPU_AVX512ER;
 483         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
 484           result |= CPU_AVX512BW;
 485         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
 486           result |= CPU_AVX512VL;
 487       }
 488     }
 489     if(_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 490       result |= CPU_BMI1;
 491     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 492       result |= CPU_TSC;
 493     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 494       result |= CPU_TSCINV;
 495     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 496       result |= CPU_AES;
 497     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 498       result |= CPU_ERMS;
 499     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 500       result |= CPU_CLMUL;
 501     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 502       result |= CPU_RTM;
 503 
 504     // AMD features.
 505     if (is_amd()) {
 506       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 507           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 508         result |= CPU_3DNOW_PREFETCH;
 509       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 510         result |= CPU_LZCNT;
 511       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 512         result |= CPU_SSE4A;
 513     }
 514     // Intel features.
 515     if(is_intel()) {
 516       if(_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 517          result |= CPU_ADX;
 518       if(_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 519         result |= CPU_BMI2;
 520       if(_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 521         result |= CPU_LZCNT;
 522       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 523       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 524         result |= CPU_3DNOW_PREFETCH;
 525       }
 526     }
 527 
 528     return result;
 529   }
 530 
 531   static bool os_supports_avx_vectors() {
 532     bool retVal = false;
 533     if (supports_evex()) {
 534       // Verify that OS save/restore all bits of EVEX registers
 535       // during signal processing.
 536       int nreg = 2 LP64_ONLY(+2);
 537       retVal = true;
 538       for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 539         if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 540           retVal = false;
 541           break;
 542         }
 543       }
 544     } else if (supports_avx()) {
 545       // Verify that OS save/restore all bits of AVX registers
 546       // during signal processing.
 547       int nreg = 2 LP64_ONLY(+2);
 548       retVal = true;
 549       for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
 550         if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
 551           retVal = false;
 552           break;
 553         }
 554       }
 555       // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen
 556       if (retVal == false) {
 557         // Verify that OS save/restore all bits of EVEX registers
 558         // during signal processing.
 559         int nreg = 2 LP64_ONLY(+2);
 560         retVal = true;
 561         for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 562           if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 563             retVal = false;
 564             break;
 565           }
 566         }
 567       }
 568     }
 569     return retVal;
 570   }
 571 
 572   static void get_processor_features();
 573 
 574 public:
 575   // Offsets for cpuid asm stub
 576   static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
 577   static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
 578   static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
 579   static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
 580   static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
 581   static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
 582   static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
 583   static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
 584   static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
 585   static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
 586   static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
 587   static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
 588   static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
 589   static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
 590 
 591   // The value used to check ymm register after signal handle
 592   static int ymm_test_value()    { return 0xCAFEBABE; }
 593 
 594   static void get_cpu_info_wrapper();
 595   static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
 596   static bool  is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
 597   static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
 598   static address  cpuinfo_cont_addr()           { return _cpuinfo_cont_addr; }
 599 
 600   static void clean_cpuFeatures()   { _cpuFeatures = 0; }
 601   static void set_avx_cpuFeatures() { _cpuFeatures = (CPU_SSE | CPU_SSE2 | CPU_AVX); }
 602   static void set_evex_cpuFeatures() { _cpuFeatures = (CPU_AVX512F | CPU_SSE | CPU_SSE2 ); }
 603 
 604 
 605   // Initialization
 606   static void initialize();
 607 
 608   // Override Abstract_VM_Version implementation
 609   static bool use_biased_locking();
 610 
 611   // Asserts
 612   static void assert_is_initialized() {
 613     assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
 614   }
 615 
 616   //
 617   // Processor family:
 618   //       3   -  386
 619   //       4   -  486
 620   //       5   -  Pentium
 621   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
 622   //              Pentium M, Core Solo, Core Duo, Core2 Duo
 623   //    family 6 model:   9,        13,       14,        15
 624   //    0x0f   -  Pentium 4, Opteron
 625   //
 626   // Note: The cpu family should be used to select between
 627   //       instruction sequences which are valid on all Intel
 628   //       processors.  Use the feature test functions below to
 629   //       determine whether a particular instruction is supported.
 630   //
 631   static int  cpu_family()        { return _cpu;}
 632   static bool is_P6()             { return cpu_family() >= 6; }
 633   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
 634   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
 635 
 636   static bool supports_processor_topology() {
 637     return (_cpuid_info.std_max_function >= 0xB) &&
 638            // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
 639            // Some cpus have max cpuid >= 0xB but do not support processor topology.
 640            (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
 641   }
 642 
 643   static uint cores_per_cpu()  {
 644     uint result = 1;
 645     if (is_intel()) {
 646       bool supports_topology = supports_processor_topology();
 647       if (supports_topology) {
 648         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 649                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 650       }
 651       if (!supports_topology || result == 0) {
 652         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 653       }
 654     } else if (is_amd()) {
 655       result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
 656     }
 657     return result;
 658   }
 659 
 660   static uint threads_per_core()  {
 661     uint result = 1;
 662     if (is_intel() && supports_processor_topology()) {
 663       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 664     } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
 665       result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
 666                cores_per_cpu();
 667     }
 668     return result;
 669   }
 670 
 671   static intx L1_line_size()  {
 672     intx result = 0;
 673     if (is_intel()) {
 674       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 675     } else if (is_amd()) {
 676       result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
 677     }
 678     if (result < 32) // not defined ?
 679       result = 32;   // 32 bytes by default on x86 and other x64
 680     return result;
 681   }
 682 
 683   static intx prefetch_data_size()  {
 684     return L1_line_size();
 685   }
 686 
 687   //
 688   // Feature identification
 689   //
 690   static bool supports_cpuid()    { return _cpuFeatures  != 0; }
 691   static bool supports_cmpxchg8() { return (_cpuFeatures & CPU_CX8) != 0; }
 692   static bool supports_cmov()     { return (_cpuFeatures & CPU_CMOV) != 0; }
 693   static bool supports_fxsr()     { return (_cpuFeatures & CPU_FXSR) != 0; }
 694   static bool supports_ht()       { return (_cpuFeatures & CPU_HT) != 0; }
 695   static bool supports_mmx()      { return (_cpuFeatures & CPU_MMX) != 0; }
 696   static bool supports_sse()      { return (_cpuFeatures & CPU_SSE) != 0; }
 697   static bool supports_sse2()     { return (_cpuFeatures & CPU_SSE2) != 0; }
 698   static bool supports_sse3()     { return (_cpuFeatures & CPU_SSE3) != 0; }
 699   static bool supports_ssse3()    { return (_cpuFeatures & CPU_SSSE3)!= 0; }
 700   static bool supports_sse4_1()   { return (_cpuFeatures & CPU_SSE4_1) != 0; }
 701   static bool supports_sse4_2()   { return (_cpuFeatures & CPU_SSE4_2) != 0; }
 702   static bool supports_popcnt()   { return (_cpuFeatures & CPU_POPCNT) != 0; }
 703   static bool supports_avx()      { return (_cpuFeatures & CPU_AVX) != 0; }
 704   static bool supports_avx2()     { return (_cpuFeatures & CPU_AVX2) != 0; }
 705   static bool supports_tsc()      { return (_cpuFeatures & CPU_TSC)    != 0; }
 706   static bool supports_aes()      { return (_cpuFeatures & CPU_AES) != 0; }
 707   static bool supports_erms()     { return (_cpuFeatures & CPU_ERMS) != 0; }
 708   static bool supports_clmul()    { return (_cpuFeatures & CPU_CLMUL) != 0; }
 709   static bool supports_rtm()      { return (_cpuFeatures & CPU_RTM) != 0; }
 710   static bool supports_bmi1()     { return (_cpuFeatures & CPU_BMI1) != 0; }
 711   static bool supports_bmi2()     { return (_cpuFeatures & CPU_BMI2) != 0; }
 712   static bool supports_adx()      { return (_cpuFeatures & CPU_ADX) != 0; }
 713   static bool supports_evex()     { return (_cpuFeatures & CPU_AVX512F) != 0; }
 714   static bool supports_avx512dq() { return (_cpuFeatures & CPU_AVX512DQ) != 0; }
 715   static bool supports_avx512pf() { return (_cpuFeatures & CPU_AVX512PF) != 0; }
 716   static bool supports_avx512er() { return (_cpuFeatures & CPU_AVX512ER) != 0; }
 717   static bool supports_avx512cd() { return (_cpuFeatures & CPU_AVX512CD) != 0; }
 718   static bool supports_avx512bw() { return (_cpuFeatures & CPU_AVX512BW) != 0; }
 719   static bool supports_avx512vl() { return (_cpuFeatures & CPU_AVX512VL) != 0; }
 720   static bool supports_avx512vlbw() { return (supports_avx512bw() && supports_avx512vl()); }
 721   static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
 722   static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
 723   static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
 724   static bool supports_avxonly()    { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
 725   // Intel features
 726   static bool is_intel_family_core() { return is_intel() &&
 727                                        extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
 728 
 729   static bool is_intel_tsc_synched_at_init()  {
 730     if (is_intel_family_core()) {
 731       uint32_t ext_model = extended_cpu_model();
 732       if (ext_model == CPU_MODEL_NEHALEM_EP     ||
 733           ext_model == CPU_MODEL_WESTMERE_EP    ||
 734           ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
 735           ext_model == CPU_MODEL_IVYBRIDGE_EP) {
 736         // <= 2-socket invariant tsc support. EX versions are usually used
 737         // in > 2-socket systems and likely don't synchronize tscs at
 738         // initialization.
 739         // Code that uses tsc values must be prepared for them to arbitrarily
 740         // jump forward or backward.
 741         return true;
 742       }
 743     }
 744     return false;
 745   }
 746 
 747   // AMD features
 748   static bool supports_3dnow_prefetch()    { return (_cpuFeatures & CPU_3DNOW_PREFETCH) != 0; }
 749   static bool supports_mmx_ext()  { return is_amd() && _cpuid_info.ext_cpuid1_edx.bits.mmx_amd != 0; }
 750   static bool supports_lzcnt()    { return (_cpuFeatures & CPU_LZCNT) != 0; }
 751   static bool supports_sse4a()    { return (_cpuFeatures & CPU_SSE4A) != 0; }
 752 
 753   static bool is_amd_Barcelona()  { return is_amd() &&
 754                                            extended_cpu_family() == CPU_FAMILY_AMD_11H; }
 755 
 756   // Intel and AMD newer cores support fast timestamps well
 757   static bool supports_tscinv_bit() {
 758     return (_cpuFeatures & CPU_TSCINV) != 0;
 759   }
 760   static bool supports_tscinv() {
 761     return supports_tscinv_bit() &&
 762            ( (is_amd() && !is_amd_Barcelona()) ||
 763              is_intel_tsc_synched_at_init() );
 764   }
 765 
 766   // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
 767   static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
 768                                            supports_sse3() && _model != 0x1C; }
 769 
 770   static bool supports_compare_and_exchange() { return true; }
 771 
 772   static const char* cpu_features()           { return _features_str; }
 773 
 774   static intx allocate_prefetch_distance() {
 775     // This method should be called before allocate_prefetch_style().
 776     //
 777     // Hardware prefetching (distance/size in bytes):
 778     // Pentium 3 -  64 /  32
 779     // Pentium 4 - 256 / 128
 780     // Athlon    -  64 /  32 ????
 781     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
 782     // Core      - 128 /  64
 783     //
 784     // Software prefetching (distance in bytes / instruction with best score):
 785     // Pentium 3 - 128 / prefetchnta
 786     // Pentium 4 - 512 / prefetchnta
 787     // Athlon    - 128 / prefetchnta
 788     // Opteron   - 256 / prefetchnta
 789     // Core      - 256 / prefetchnta
 790     // It will be used only when AllocatePrefetchStyle > 0
 791 
 792     intx count = AllocatePrefetchDistance;
 793     if (count < 0) {   // default ?
 794       if (is_amd()) {  // AMD
 795         if (supports_sse2())
 796           count = 256; // Opteron
 797         else
 798           count = 128; // Athlon
 799       } else {         // Intel
 800         if (supports_sse2())
 801           if (cpu_family() == 6) {
 802             count = 256; // Pentium M, Core, Core2
 803           } else {
 804             count = 512; // Pentium 4
 805           }
 806         else
 807           count = 128; // Pentium 3 (and all other old CPUs)
 808       }
 809     }
 810     return count;
 811   }
 812   static intx allocate_prefetch_style() {
 813     assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
 814     // Return 0 if AllocatePrefetchDistance was not defined.
 815     return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
 816   }
 817 
 818   // Prefetch interval for gc copy/scan == 9 dcache lines.  Derived from
 819   // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
 820   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
 821   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
 822 
 823   // gc copy/scan is disabled if prefetchw isn't supported, because
 824   // Prefetch::write emits an inlined prefetchw on Linux.
 825   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
 826   // The used prefetcht0 instruction works for both amd64 and em64t.
 827   static intx prefetch_copy_interval_in_bytes() {
 828     intx interval = PrefetchCopyIntervalInBytes;
 829     return interval >= 0 ? interval : 576;
 830   }
 831   static intx prefetch_scan_interval_in_bytes() {
 832     intx interval = PrefetchScanIntervalInBytes;
 833     return interval >= 0 ? interval : 576;
 834   }
 835   static intx prefetch_fields_ahead() {
 836     intx count = PrefetchFieldsAhead;
 837     return count >= 0 ? count : 1;
 838   }
 839   static uint32_t get_xsave_header_lower_segment() {
 840     return _cpuid_info.xem_xcr0_eax.value;
 841   }
 842   static uint32_t get_xsave_header_upper_segment() {
 843     return _cpuid_info.xem_xcr0_edx;
 844   }
 845 };
 846 
 847 #endif // CPU_X86_VM_VM_VERSION_X86_HPP