src/cpu/x86/vm/assembler_x86.cpp

*** 770,779 ****
--- 770,780 ----
      case 0x2F: // comiss
      case 0x54: // andps
      case 0x55: // andnps
      case 0x56: // orps
      case 0x57: // xorps
+     case 0x58: // addpd
      case 0x59: // mulpd
      case 0x6E: // movd
      case 0x7E: // movd
      case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
        debug_only(has_disp32 = true);
*** 1888,1897 ****
--- 1889,1904 ----
    int encode = prefix_and_encode(src->encoding());
    emit_int8((unsigned char)0xF7);
    emit_int8((unsigned char)(0xF0 | encode));
  }
  
+ void Assembler::imull(Register src) {
+   int encode = prefix_and_encode(src->encoding());
+   emit_int8((unsigned char)0xF7);
+   emit_int8((unsigned char)(0xE8 | encode));
+ }
+ 
  void Assembler::imull(Register dst, Register src) {
    int encode = prefix_and_encode(dst->encoding(), src->encoding());
    emit_int8(0x0F);
    emit_int8((unsigned char)0xAF);
    emit_int8((unsigned char)(0xC0 | encode));
*** 3751,3760 ****
--- 3758,3776 ----
    NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
    (void) prefix_and_encode(dst->encoding(), true);
    emit_arith_b(0xF6, 0xC0, dst, imm8);
  }
  
+ void Assembler::testb(Address dst, int imm8) {
+   InstructionMark im(this);
+   prefix(dst);
+   emit_int8((unsigned char)0xF6);
+   emit_operand(rax, dst, 1);
+   emit_int8(imm8);
+ 
+ }
+ 
  void Assembler::testl(Register dst, int32_t imm32) {
    // not using emit_arith because test
    // doesn't support sign-extension of
    // 8bit operands
    int encode = dst->encoding();
*** 4081,4090 ****
--- 4097,4116 ----
    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
    emit_int8(0x58);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::addpd(XMMRegister dst, Address src) {
+   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
+   InstructionMark im(this);
+   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
+   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
+   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
+   emit_int8(0x58);
+   emit_operand(dst, src);
+ }
+ 
  void Assembler::addps(XMMRegister dst, XMMRegister src) {
    NOT_LP64(assert(VM_Version::supports_sse2(), ""));
    InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
    int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
    emit_int8(0x58);