755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x59: // mulpd
776 case 0x6E: // movd
777 case 0x7E: // movd
778 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
779 debug_only(has_disp32 = true);
780 break;
781
782 case 0xAD: // shrd r, a, %cl
783 case 0xAF: // imul r, a
784 case 0xBE: // movsbl r, a (movsxb)
785 case 0xBF: // movswl r, a (movsxw)
786 case 0xB6: // movzbl r, a (movzxb)
787 case 0xB7: // movzwl r, a (movzxw)
788 case REP16(0x40): // cmovl cc, r, a
789 case 0xB0: // cmpxchgb
790 case 0xB1: // cmpxchg
791 case 0xC1: // xaddl
792 case 0xC7: // cmpxchg8
793 case REP16(0x90): // setcc a
794 debug_only(has_disp32 = true);
1873 emit_int8(0x0F);
1874 emit_int8(0x77);
1875 }
1876
1877 void Assembler::hlt() {
1878 emit_int8((unsigned char)0xF4);
1879 }
1880
1881 void Assembler::idivl(Register src) {
1882 int encode = prefix_and_encode(src->encoding());
1883 emit_int8((unsigned char)0xF7);
1884 emit_int8((unsigned char)(0xF8 | encode));
1885 }
1886
1887 void Assembler::divl(Register src) { // Unsigned
1888 int encode = prefix_and_encode(src->encoding());
1889 emit_int8((unsigned char)0xF7);
1890 emit_int8((unsigned char)(0xF0 | encode));
1891 }
1892
1893 void Assembler::imull(Register dst, Register src) {
1894 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1895 emit_int8(0x0F);
1896 emit_int8((unsigned char)0xAF);
1897 emit_int8((unsigned char)(0xC0 | encode));
1898 }
1899
1900
1901 void Assembler::imull(Register dst, Register src, int value) {
1902 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1903 if (is8bit(value)) {
1904 emit_int8(0x6B);
1905 emit_int8((unsigned char)(0xC0 | encode));
1906 emit_int8(value & 0xFF);
1907 } else {
1908 emit_int8(0x69);
1909 emit_int8((unsigned char)(0xC0 | encode));
1910 emit_int32(value);
1911 }
1912 }
3736 emit_int8(0x5C);
3737 emit_int8((unsigned char)(0xC0 | encode));
3738 }
3739
3740 void Assembler::subss(XMMRegister dst, Address src) {
3741 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3742 InstructionMark im(this);
3743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3744 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3745 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3746 emit_int8(0x5C);
3747 emit_operand(dst, src);
3748 }
3749
3750 void Assembler::testb(Register dst, int imm8) {
3751 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3752 (void) prefix_and_encode(dst->encoding(), true);
3753 emit_arith_b(0xF6, 0xC0, dst, imm8);
3754 }
3755
3756 void Assembler::testl(Register dst, int32_t imm32) {
3757 // not using emit_arith because test
3758 // doesn't support sign-extension of
3759 // 8bit operands
3760 int encode = dst->encoding();
3761 if (encode == 0) {
3762 emit_int8((unsigned char)0xA9);
3763 } else {
3764 encode = prefix_and_encode(encode);
3765 emit_int8((unsigned char)0xF7);
3766 emit_int8((unsigned char)(0xC0 | encode));
3767 }
3768 emit_int32(imm32);
3769 }
3770
3771 void Assembler::testl(Register dst, Register src) {
3772 (void) prefix_and_encode(dst->encoding(), src->encoding());
3773 emit_arith(0x85, 0xC0, dst, src);
3774 }
3775
4064
4065 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4066 assert(VM_Version::supports_avx(), "");
4067 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4068 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4069 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4070 emit_int8(0x5C);
4071 emit_int8((unsigned char)(0xC0 | encode));
4072 }
4073
4074 //====================VECTOR ARITHMETIC=====================================
4075
4076 // Float-point vector arithmetic
4077
4078 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4079 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4080 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4081 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4082 emit_int8(0x58);
4083 emit_int8((unsigned char)(0xC0 | encode));
4084 }
4085
4086 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4089 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4090 emit_int8(0x58);
4091 emit_int8((unsigned char)(0xC0 | encode));
4092 }
4093
4094 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4095 assert(VM_Version::supports_avx(), "");
4096 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4097 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4098 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4099 emit_int8(0x58);
4100 emit_int8((unsigned char)(0xC0 | encode));
4101 }
4102
4103 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
|
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 debug_only(has_disp32 = true);
781 break;
782
783 case 0xAD: // shrd r, a, %cl
784 case 0xAF: // imul r, a
785 case 0xBE: // movsbl r, a (movsxb)
786 case 0xBF: // movswl r, a (movsxw)
787 case 0xB6: // movzbl r, a (movzxb)
788 case 0xB7: // movzwl r, a (movzxw)
789 case REP16(0x40): // cmovl cc, r, a
790 case 0xB0: // cmpxchgb
791 case 0xB1: // cmpxchg
792 case 0xC1: // xaddl
793 case 0xC7: // cmpxchg8
794 case REP16(0x90): // setcc a
795 debug_only(has_disp32 = true);
1874 emit_int8(0x0F);
1875 emit_int8(0x77);
1876 }
1877
1878 void Assembler::hlt() {
1879 emit_int8((unsigned char)0xF4);
1880 }
1881
1882 void Assembler::idivl(Register src) {
1883 int encode = prefix_and_encode(src->encoding());
1884 emit_int8((unsigned char)0xF7);
1885 emit_int8((unsigned char)(0xF8 | encode));
1886 }
1887
1888 void Assembler::divl(Register src) { // Unsigned
1889 int encode = prefix_and_encode(src->encoding());
1890 emit_int8((unsigned char)0xF7);
1891 emit_int8((unsigned char)(0xF0 | encode));
1892 }
1893
1894 void Assembler::imull(Register src) {
1895 int encode = prefix_and_encode(src->encoding());
1896 emit_int8((unsigned char)0xF7);
1897 emit_int8((unsigned char)(0xE8 | encode));
1898 }
1899
1900 void Assembler::imull(Register dst, Register src) {
1901 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1902 emit_int8(0x0F);
1903 emit_int8((unsigned char)0xAF);
1904 emit_int8((unsigned char)(0xC0 | encode));
1905 }
1906
1907
1908 void Assembler::imull(Register dst, Register src, int value) {
1909 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1910 if (is8bit(value)) {
1911 emit_int8(0x6B);
1912 emit_int8((unsigned char)(0xC0 | encode));
1913 emit_int8(value & 0xFF);
1914 } else {
1915 emit_int8(0x69);
1916 emit_int8((unsigned char)(0xC0 | encode));
1917 emit_int32(value);
1918 }
1919 }
3743 emit_int8(0x5C);
3744 emit_int8((unsigned char)(0xC0 | encode));
3745 }
3746
3747 void Assembler::subss(XMMRegister dst, Address src) {
3748 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3749 InstructionMark im(this);
3750 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3751 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3752 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3753 emit_int8(0x5C);
3754 emit_operand(dst, src);
3755 }
3756
3757 void Assembler::testb(Register dst, int imm8) {
3758 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3759 (void) prefix_and_encode(dst->encoding(), true);
3760 emit_arith_b(0xF6, 0xC0, dst, imm8);
3761 }
3762
3763 void Assembler::testb(Address dst, int imm8) {
3764 InstructionMark im(this);
3765 prefix(dst);
3766 emit_int8((unsigned char)0xF6);
3767 emit_operand(rax, dst, 1);
3768 emit_int8(imm8);
3769
3770 }
3771
3772 void Assembler::testl(Register dst, int32_t imm32) {
3773 // not using emit_arith because test
3774 // doesn't support sign-extension of
3775 // 8bit operands
3776 int encode = dst->encoding();
3777 if (encode == 0) {
3778 emit_int8((unsigned char)0xA9);
3779 } else {
3780 encode = prefix_and_encode(encode);
3781 emit_int8((unsigned char)0xF7);
3782 emit_int8((unsigned char)(0xC0 | encode));
3783 }
3784 emit_int32(imm32);
3785 }
3786
3787 void Assembler::testl(Register dst, Register src) {
3788 (void) prefix_and_encode(dst->encoding(), src->encoding());
3789 emit_arith(0x85, 0xC0, dst, src);
3790 }
3791
4080
4081 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4082 assert(VM_Version::supports_avx(), "");
4083 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4084 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4085 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4086 emit_int8(0x5C);
4087 emit_int8((unsigned char)(0xC0 | encode));
4088 }
4089
4090 //====================VECTOR ARITHMETIC=====================================
4091
4092 // Float-point vector arithmetic
4093
4094 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4095 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4096 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4097 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4098 emit_int8(0x58);
4099 emit_int8((unsigned char)(0xC0 | encode));
4100 }
4101
4102 void Assembler::addpd(XMMRegister dst, Address src) {
4103 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4104 InstructionMark im(this);
4105 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4106 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4107 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4108 emit_int8(0x58);
4109 emit_operand(dst, src);
4110 }
4111
4112 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4114 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4115 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4116 emit_int8(0x58);
4117 emit_int8((unsigned char)(0xC0 | encode));
4118 }
4119
4120 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4121 assert(VM_Version::supports_avx(), "");
4122 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4123 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4124 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4125 emit_int8(0x58);
4126 emit_int8((unsigned char)(0xC0 | encode));
4127 }
4128
4129 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
|