2347         {
2348           if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2349             __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2350           }
2351           __ andpd(dest->as_xmm_double_reg(),
2352                     ExternalAddress((address)double_signmask_pool));
2353         }
2354         break;
2355 
2356       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2357       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2358       default      : ShouldNotReachHere();
2359     }
2360 
2361   } else if (value->is_double_fpu()) {
2362     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2363     switch(code) {
2364       case lir_log10 : __ flog10() ; break;
2365       case lir_abs   : __ fabs() ; break;
2366       case lir_sqrt  : __ fsqrt(); break;
2367       case lir_sin   :
2368         // Should consider not saving rbx, if not necessary
2369         __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2370         break;
2371       case lir_cos :
2372         // Should consider not saving rbx, if not necessary
2373         assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2374         __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2375         break;
2376       case lir_tan :
2377         // Should consider not saving rbx, if not necessary
2378         __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2379         break;
2380       case lir_pow :
2381         __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2382         break;
2383       default      : ShouldNotReachHere();
2384     }
2385   } else {
2386     Unimplemented();
2387   }
2388 }
2389 
2390 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2391   // assert(left->destroys_register(), "check");
2392   if (left->is_single_cpu()) {
2393     Register reg = left->as_register();
2394     if (right->is_constant()) {
2395       int val = right->as_constant_ptr()->as_jint();

2347         {
2348           if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2349             __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2350           }
2351           __ andpd(dest->as_xmm_double_reg(),
2352                     ExternalAddress((address)double_signmask_pool));
2353         }
2354         break;
2355 
2356       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2357       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2358       default      : ShouldNotReachHere();
2359     }
2360 
2361   } else if (value->is_double_fpu()) {
2362     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2363     switch(code) {
2364       case lir_log10 : __ flog10() ; break;
2365       case lir_abs   : __ fabs() ; break;
2366       case lir_sqrt  : __ fsqrt(); break;









2367       case lir_tan :
2368         // Should consider not saving rbx, if not necessary
2369         __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2370         break;
2371       case lir_pow :
2372         __ pow_with_fallback(op->as_Op2()->fpu_stack_size());
2373         break;
2374       default      : ShouldNotReachHere();
2375     }
2376   } else {
2377     Unimplemented();
2378   }
2379 }
2380 
2381 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2382   // assert(left->destroys_register(), "check");
2383   if (left->is_single_cpu()) {
2384     Register reg = left->as_register();
2385     if (right->is_constant()) {
2386       int val = right->as_constant_ptr()->as_jint();