1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && (_attributes != NULL) && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 debug_only(has_disp32 = true);
781 break;
782
783 case 0xAD: // shrd r, a, %cl
784 case 0xAF: // imul r, a
785 case 0xBE: // movsbl r, a (movsxb)
786 case 0xBF: // movswl r, a (movsxw)
787 case 0xB6: // movzbl r, a (movzxb)
788 case 0xB7: // movzwl r, a (movzxw)
789 case REP16(0x40): // cmovl cc, r, a
790 case 0xB0: // cmpxchgb
791 case 0xB1: // cmpxchg
792 case 0xC1: // xaddl
793 case 0xC7: // cmpxchg8
794 case REP16(0x90): // setcc a
795 debug_only(has_disp32 = true);
796 // fall out of the switch to decode the address
797 break;
798
799 case 0xC4: // pinsrw r, a, #8
800 debug_only(has_disp32 = true);
801 case 0xC5: // pextrw r, r, #8
802 tail_size = 1; // the imm8
803 break;
804
805 case 0xAC: // shrd r, a, #8
806 debug_only(has_disp32 = true);
807 tail_size = 1; // the imm8
808 break;
809
810 case REP16(0x80): // jcc rdisp32
811 if (which == end_pc_operand) return ip + 4;
812 assert(which == call32_operand, "jcc has no disp32 or imm");
813 return ip;
814 default:
815 ShouldNotReachHere();
816 }
817 break;
818
819 case 0x81: // addl a, #32; addl r, #32
820 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
821 // on 32bit in the case of cmpl, the imm might be an oop
822 tail_size = 4;
823 debug_only(has_disp32 = true); // has both kinds of operands!
824 break;
825
826 case 0x83: // addl a, #8; addl r, #8
827 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
828 debug_only(has_disp32 = true); // has both kinds of operands!
829 tail_size = 1;
830 break;
831
832 case 0x9B:
833 switch (0xFF & *ip++) {
834 case 0xD9: // fnstcw a
835 debug_only(has_disp32 = true);
836 break;
837 default:
838 ShouldNotReachHere();
839 }
840 break;
841
842 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
843 case REP4(0x10): // adc...
844 case REP4(0x20): // and...
845 case REP4(0x30): // xor...
846 case REP4(0x08): // or...
847 case REP4(0x18): // sbb...
848 case REP4(0x28): // sub...
849 case 0xF7: // mull a
850 case 0x8D: // lea r, a
851 case 0x87: // xchg r, a
852 case REP4(0x38): // cmp...
853 case 0x85: // test r, a
854 debug_only(has_disp32 = true); // has both kinds of operands!
855 break;
856
857 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
858 case 0xC6: // movb a, #8
859 case 0x80: // cmpb a, #8
860 case 0x6B: // imul r, a, #8
861 debug_only(has_disp32 = true); // has both kinds of operands!
862 tail_size = 1; // the imm8
863 break;
864
865 case 0xC4: // VEX_3bytes
866 case 0xC5: // VEX_2bytes
867 assert((UseAVX > 0), "shouldn't have VEX prefix");
868 assert(ip == inst+1, "no prefixes allowed");
869 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
870 // but they have prefix 0x0F and processed when 0x0F processed above.
871 //
872 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
873 // instructions (these instructions are not supported in 64-bit mode).
874 // To distinguish them bits [7:6] are set in the VEX second byte since
875 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
876 // those VEX bits REX and vvvv bits are inverted.
877 //
878 // Fortunately C2 doesn't generate these instructions so we don't need
879 // to check for them in product version.
880
881 // Check second byte
882 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
883
884 int vex_opcode;
885 // First byte
886 if ((0xFF & *inst) == VEX_3bytes) {
887 vex_opcode = VEX_OPCODE_MASK & *ip;
888 ip++; // third byte
889 is_64bit = ((VEX_W & *ip) == VEX_W);
890 } else {
891 vex_opcode = VEX_OPCODE_0F;
892 }
893 ip++; // opcode
894 // To find the end of instruction (which == end_pc_operand).
895 switch (vex_opcode) {
896 case VEX_OPCODE_0F:
897 switch (0xFF & *ip) {
898 case 0x70: // pshufd r, r/a, #8
899 case 0x71: // ps[rl|ra|ll]w r, #8
900 case 0x72: // ps[rl|ra|ll]d r, #8
901 case 0x73: // ps[rl|ra|ll]q r, #8
902 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
903 case 0xC4: // pinsrw r, r, r/a, #8
904 case 0xC5: // pextrw r/a, r, #8
905 case 0xC6: // shufp[s|d] r, r, r/a, #8
906 tail_size = 1; // the imm8
907 break;
908 }
909 break;
910 case VEX_OPCODE_0F_3A:
911 tail_size = 1;
912 break;
913 }
914 ip++; // skip opcode
915 debug_only(has_disp32 = true); // has both kinds of operands!
916 break;
917
918 case 0x62: // EVEX_4bytes
919 assert((UseAVX > 0), "shouldn't have EVEX prefix");
920 assert(ip == inst+1, "no prefixes allowed");
921 // no EVEX collisions, all instructions that have 0x62 opcodes
922 // have EVEX versions and are subopcodes of 0x66
923 ip++; // skip P0 and exmaine W in P1
924 is_64bit = ((VEX_W & *ip) == VEX_W);
925 ip++; // move to P2
926 ip++; // skip P2, move to opcode
927 // To find the end of instruction (which == end_pc_operand).
928 switch (0xFF & *ip) {
929 case 0x61: // pcmpestri r, r/a, #8
930 case 0x70: // pshufd r, r/a, #8
931 case 0x73: // psrldq r, #8
932 tail_size = 1; // the imm8
933 break;
934 default:
935 break;
936 }
937 ip++; // skip opcode
938 debug_only(has_disp32 = true); // has both kinds of operands!
939 break;
940
941 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
942 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
943 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
944 case 0xDD: // fld_d a; fst_d a; fstp_d a
945 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
946 case 0xDF: // fild_d a; fistp_d a
947 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
948 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
949 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
950 debug_only(has_disp32 = true);
951 break;
952
953 case 0xE8: // call rdisp32
954 case 0xE9: // jmp rdisp32
955 if (which == end_pc_operand) return ip + 4;
956 assert(which == call32_operand, "call has no disp32 or imm");
957 return ip;
958
959 case 0xF0: // Lock
960 assert(os::is_MP(), "only on MP");
961 goto again_after_prefix;
962
963 case 0xF3: // For SSE
964 case 0xF2: // For SSE2
965 switch (0xFF & *ip++) {
966 case REX:
967 case REX_B:
968 case REX_X:
969 case REX_XB:
970 case REX_R:
971 case REX_RB:
972 case REX_RX:
973 case REX_RXB:
974 case REX_W:
975 case REX_WB:
976 case REX_WX:
977 case REX_WXB:
978 case REX_WR:
979 case REX_WRB:
980 case REX_WRX:
981 case REX_WRXB:
982 NOT_LP64(assert(false, "found 64bit prefix"));
983 ip++;
984 default:
985 ip++;
986 }
987 debug_only(has_disp32 = true); // has both kinds of operands!
988 break;
989
990 default:
991 ShouldNotReachHere();
992
993 #undef REP8
994 #undef REP16
995 }
996
997 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
998 #ifdef _LP64
999 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1000 #else
1001 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1002 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1003 #endif // LP64
1004 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1005
1006 // parse the output of emit_operand
1007 int op2 = 0xFF & *ip++;
1008 int base = op2 & 0x07;
1009 int op3 = -1;
1010 const int b100 = 4;
1011 const int b101 = 5;
1012 if (base == b100 && (op2 >> 6) != 3) {
1013 op3 = 0xFF & *ip++;
1014 base = op3 & 0x07; // refetch the base
1015 }
1016 // now ip points at the disp (if any)
1017
1018 switch (op2 >> 6) {
1019 case 0:
1020 // [00 reg 100][ss index base]
1021 // [00 reg 100][00 100 esp]
1022 // [00 reg base]
1023 // [00 reg 100][ss index 101][disp32]
1024 // [00 reg 101] [disp32]
1025
1026 if (base == b101) {
1027 if (which == disp32_operand)
1028 return ip; // caller wants the disp32
1029 ip += 4; // skip the disp32
1030 }
1031 break;
1032
1033 case 1:
1034 // [01 reg 100][ss index base][disp8]
1035 // [01 reg 100][00 100 esp][disp8]
1036 // [01 reg base] [disp8]
1037 ip += 1; // skip the disp8
1038 break;
1039
1040 case 2:
1041 // [10 reg 100][ss index base][disp32]
1042 // [10 reg 100][00 100 esp][disp32]
1043 // [10 reg base] [disp32]
1044 if (which == disp32_operand)
1045 return ip; // caller wants the disp32
1046 ip += 4; // skip the disp32
1047 break;
1048
1049 case 3:
1050 // [11 reg base] (not a memory addressing mode)
1051 break;
1052 }
1053
1054 if (which == end_pc_operand) {
1055 return ip + tail_size;
1056 }
1057
1058 #ifdef _LP64
1059 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1060 #else
1061 assert(which == imm_operand, "instruction has only an imm field");
1062 #endif // LP64
1063 return ip;
1064 }
1065
1066 address Assembler::locate_next_instruction(address inst) {
1067 // Secretly share code with locate_operand:
1068 return locate_operand(inst, end_pc_operand);
1069 }
1070
1071
1072 #ifdef ASSERT
1073 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1074 address inst = inst_mark();
1075 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1076 address opnd;
1077
1078 Relocation* r = rspec.reloc();
1079 if (r->type() == relocInfo::none) {
1080 return;
1081 } else if (r->is_call() || format == call32_operand) {
1082 // assert(format == imm32_operand, "cannot specify a nonzero format");
1083 opnd = locate_operand(inst, call32_operand);
1084 } else if (r->is_data()) {
1085 assert(format == imm_operand || format == disp32_operand
1086 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1087 opnd = locate_operand(inst, (WhichOperand)format);
1088 } else {
1089 assert(format == imm_operand, "cannot specify a format");
1090 return;
1091 }
1092 assert(opnd == pc(), "must put operand where relocs can find it");
1093 }
1094 #endif // ASSERT
1095
1096 void Assembler::emit_operand32(Register reg, Address adr) {
1097 assert(reg->encoding() < 8, "no extended registers");
1098 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1099 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1100 adr._rspec);
1101 }
1102
1103 void Assembler::emit_operand(Register reg, Address adr,
1104 int rip_relative_correction) {
1105 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1106 adr._rspec,
1107 rip_relative_correction);
1108 }
1109
1110 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1111 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1112 adr._rspec);
1113 }
1114
1115 // MMX operations
1116 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1117 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1118 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1119 }
1120
1121 // work around gcc (3.2.1-7a) bug
1122 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1123 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1124 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1125 }
1126
1127
1128 void Assembler::emit_farith(int b1, int b2, int i) {
1129 assert(isByte(b1) && isByte(b2), "wrong opcode");
1130 assert(0 <= i && i < 8, "illegal stack offset");
1131 emit_int8(b1);
1132 emit_int8(b2 + i);
1133 }
1134
1135
1136 // Now the Assembler instructions (identical for 32/64 bits)
1137
1138 void Assembler::adcl(Address dst, int32_t imm32) {
1139 InstructionMark im(this);
1140 prefix(dst);
1141 emit_arith_operand(0x81, rdx, dst, imm32);
1142 }
1143
1144 void Assembler::adcl(Address dst, Register src) {
1145 InstructionMark im(this);
1146 prefix(dst, src);
1147 emit_int8(0x11);
1148 emit_operand(src, dst);
1149 }
1150
1151 void Assembler::adcl(Register dst, int32_t imm32) {
1152 prefix(dst);
1153 emit_arith(0x81, 0xD0, dst, imm32);
1154 }
1155
1156 void Assembler::adcl(Register dst, Address src) {
1157 InstructionMark im(this);
1158 prefix(src, dst);
1159 emit_int8(0x13);
1160 emit_operand(dst, src);
1161 }
1162
1163 void Assembler::adcl(Register dst, Register src) {
1164 (void) prefix_and_encode(dst->encoding(), src->encoding());
1165 emit_arith(0x13, 0xC0, dst, src);
1166 }
1167
1168 void Assembler::addl(Address dst, int32_t imm32) {
1169 InstructionMark im(this);
1170 prefix(dst);
1171 emit_arith_operand(0x81, rax, dst, imm32);
1172 }
1173
1174 void Assembler::addl(Address dst, Register src) {
1175 InstructionMark im(this);
1176 prefix(dst, src);
1177 emit_int8(0x01);
1178 emit_operand(src, dst);
1179 }
1180
1181 void Assembler::addl(Register dst, int32_t imm32) {
1182 prefix(dst);
1183 emit_arith(0x81, 0xC0, dst, imm32);
1184 }
1185
1186 void Assembler::addl(Register dst, Address src) {
1187 InstructionMark im(this);
1188 prefix(src, dst);
1189 emit_int8(0x03);
1190 emit_operand(dst, src);
1191 }
1192
1193 void Assembler::addl(Register dst, Register src) {
1194 (void) prefix_and_encode(dst->encoding(), src->encoding());
1195 emit_arith(0x03, 0xC0, dst, src);
1196 }
1197
1198 void Assembler::addr_nop_4() {
1199 assert(UseAddressNop, "no CPU support");
1200 // 4 bytes: NOP DWORD PTR [EAX+0]
1201 emit_int8(0x0F);
1202 emit_int8(0x1F);
1203 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1204 emit_int8(0); // 8-bits offset (1 byte)
1205 }
1206
1207 void Assembler::addr_nop_5() {
1208 assert(UseAddressNop, "no CPU support");
1209 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1210 emit_int8(0x0F);
1211 emit_int8(0x1F);
1212 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1213 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1214 emit_int8(0); // 8-bits offset (1 byte)
1215 }
1216
1217 void Assembler::addr_nop_7() {
1218 assert(UseAddressNop, "no CPU support");
1219 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1220 emit_int8(0x0F);
1221 emit_int8(0x1F);
1222 emit_int8((unsigned char)0x80);
1223 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1224 emit_int32(0); // 32-bits offset (4 bytes)
1225 }
1226
1227 void Assembler::addr_nop_8() {
1228 assert(UseAddressNop, "no CPU support");
1229 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1230 emit_int8(0x0F);
1231 emit_int8(0x1F);
1232 emit_int8((unsigned char)0x84);
1233 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1234 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1235 emit_int32(0); // 32-bits offset (4 bytes)
1236 }
1237
1238 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1240 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1241 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1242 emit_int8(0x58);
1243 emit_int8((unsigned char)(0xC0 | encode));
1244 }
1245
1246 void Assembler::addsd(XMMRegister dst, Address src) {
1247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1248 InstructionMark im(this);
1249 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1250 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1251 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1252 emit_int8(0x58);
1253 emit_operand(dst, src);
1254 }
1255
1256 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1257 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1258 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1260 emit_int8(0x58);
1261 emit_int8((unsigned char)(0xC0 | encode));
1262 }
1263
1264 void Assembler::addss(XMMRegister dst, Address src) {
1265 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1266 InstructionMark im(this);
1267 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1268 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1269 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1270 emit_int8(0x58);
1271 emit_operand(dst, src);
1272 }
1273
1274 void Assembler::aesdec(XMMRegister dst, Address src) {
1275 assert(VM_Version::supports_aes(), "");
1276 InstructionMark im(this);
1277 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1278 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1279 emit_int8((unsigned char)0xDE);
1280 emit_operand(dst, src);
1281 }
1282
1283 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1284 assert(VM_Version::supports_aes(), "");
1285 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1286 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1287 emit_int8((unsigned char)0xDE);
1288 emit_int8(0xC0 | encode);
1289 }
1290
1291 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1292 assert(VM_Version::supports_aes(), "");
1293 InstructionMark im(this);
1294 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1295 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1296 emit_int8((unsigned char)0xDF);
1297 emit_operand(dst, src);
1298 }
1299
1300 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1301 assert(VM_Version::supports_aes(), "");
1302 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1303 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1304 emit_int8((unsigned char)0xDF);
1305 emit_int8((unsigned char)(0xC0 | encode));
1306 }
1307
1308 void Assembler::aesenc(XMMRegister dst, Address src) {
1309 assert(VM_Version::supports_aes(), "");
1310 InstructionMark im(this);
1311 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1312 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1313 emit_int8((unsigned char)0xDC);
1314 emit_operand(dst, src);
1315 }
1316
1317 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1318 assert(VM_Version::supports_aes(), "");
1319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1320 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1321 emit_int8((unsigned char)0xDC);
1322 emit_int8(0xC0 | encode);
1323 }
1324
1325 void Assembler::aesenclast(XMMRegister dst, Address src) {
1326 assert(VM_Version::supports_aes(), "");
1327 InstructionMark im(this);
1328 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1329 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1330 emit_int8((unsigned char)0xDD);
1331 emit_operand(dst, src);
1332 }
1333
1334 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1335 assert(VM_Version::supports_aes(), "");
1336 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1337 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1338 emit_int8((unsigned char)0xDD);
1339 emit_int8((unsigned char)(0xC0 | encode));
1340 }
1341
1342 void Assembler::andl(Address dst, int32_t imm32) {
1343 InstructionMark im(this);
1344 prefix(dst);
1345 emit_int8((unsigned char)0x81);
1346 emit_operand(rsp, dst, 4);
1347 emit_int32(imm32);
1348 }
1349
1350 void Assembler::andl(Register dst, int32_t imm32) {
1351 prefix(dst);
1352 emit_arith(0x81, 0xE0, dst, imm32);
1353 }
1354
1355 void Assembler::andl(Register dst, Address src) {
1356 InstructionMark im(this);
1357 prefix(src, dst);
1358 emit_int8(0x23);
1359 emit_operand(dst, src);
1360 }
1361
1362 void Assembler::andl(Register dst, Register src) {
1363 (void) prefix_and_encode(dst->encoding(), src->encoding());
1364 emit_arith(0x23, 0xC0, dst, src);
1365 }
1366
1367 void Assembler::andnl(Register dst, Register src1, Register src2) {
1368 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1369 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1370 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1371 emit_int8((unsigned char)0xF2);
1372 emit_int8((unsigned char)(0xC0 | encode));
1373 }
1374
1375 void Assembler::andnl(Register dst, Register src1, Address src2) {
1376 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1377 InstructionMark im(this);
1378 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1379 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1380 emit_int8((unsigned char)0xF2);
1381 emit_operand(dst, src2);
1382 }
1383
1384 void Assembler::bsfl(Register dst, Register src) {
1385 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1386 emit_int8(0x0F);
1387 emit_int8((unsigned char)0xBC);
1388 emit_int8((unsigned char)(0xC0 | encode));
1389 }
1390
1391 void Assembler::bsrl(Register dst, Register src) {
1392 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1393 emit_int8(0x0F);
1394 emit_int8((unsigned char)0xBD);
1395 emit_int8((unsigned char)(0xC0 | encode));
1396 }
1397
1398 void Assembler::bswapl(Register reg) { // bswap
1399 int encode = prefix_and_encode(reg->encoding());
1400 emit_int8(0x0F);
1401 emit_int8((unsigned char)(0xC8 | encode));
1402 }
1403
1404 void Assembler::blsil(Register dst, Register src) {
1405 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1406 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1407 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1408 emit_int8((unsigned char)0xF3);
1409 emit_int8((unsigned char)(0xC0 | encode));
1410 }
1411
1412 void Assembler::blsil(Register dst, Address src) {
1413 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1414 InstructionMark im(this);
1415 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1416 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1417 emit_int8((unsigned char)0xF3);
1418 emit_operand(rbx, src);
1419 }
1420
1421 void Assembler::blsmskl(Register dst, Register src) {
1422 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1423 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1424 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1425 emit_int8((unsigned char)0xF3);
1426 emit_int8((unsigned char)(0xC0 | encode));
1427 }
1428
1429 void Assembler::blsmskl(Register dst, Address src) {
1430 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1431 InstructionMark im(this);
1432 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1433 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1434 emit_int8((unsigned char)0xF3);
1435 emit_operand(rdx, src);
1436 }
1437
1438 void Assembler::blsrl(Register dst, Register src) {
1439 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1440 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1441 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1442 emit_int8((unsigned char)0xF3);
1443 emit_int8((unsigned char)(0xC0 | encode));
1444 }
1445
1446 void Assembler::blsrl(Register dst, Address src) {
1447 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1448 InstructionMark im(this);
1449 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1450 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1451 emit_int8((unsigned char)0xF3);
1452 emit_operand(rcx, src);
1453 }
1454
1455 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1456 // suspect disp32 is always good
1457 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1458
1459 if (L.is_bound()) {
1460 const int long_size = 5;
1461 int offs = (int)( target(L) - pc() );
1462 assert(offs <= 0, "assembler error");
1463 InstructionMark im(this);
1464 // 1110 1000 #32-bit disp
1465 emit_int8((unsigned char)0xE8);
1466 emit_data(offs - long_size, rtype, operand);
1467 } else {
1468 InstructionMark im(this);
1469 // 1110 1000 #32-bit disp
1470 L.add_patch_at(code(), locator());
1471
1472 emit_int8((unsigned char)0xE8);
1473 emit_data(int(0), rtype, operand);
1474 }
1475 }
1476
1477 void Assembler::call(Register dst) {
1478 int encode = prefix_and_encode(dst->encoding());
1479 emit_int8((unsigned char)0xFF);
1480 emit_int8((unsigned char)(0xD0 | encode));
1481 }
1482
1483
1484 void Assembler::call(Address adr) {
1485 InstructionMark im(this);
1486 prefix(adr);
1487 emit_int8((unsigned char)0xFF);
1488 emit_operand(rdx, adr);
1489 }
1490
1491 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1492 assert(entry != NULL, "call most probably wrong");
1493 InstructionMark im(this);
1494 emit_int8((unsigned char)0xE8);
1495 intptr_t disp = entry - (pc() + sizeof(int32_t));
1496 assert(is_simm32(disp), "must be 32bit offset (call2)");
1497 // Technically, should use call32_operand, but this format is
1498 // implied by the fact that we're emitting a call instruction.
1499
1500 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1501 emit_data((int) disp, rspec, operand);
1502 }
1503
1504 void Assembler::cdql() {
1505 emit_int8((unsigned char)0x99);
1506 }
1507
1508 void Assembler::cld() {
1509 emit_int8((unsigned char)0xFC);
1510 }
1511
1512 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1513 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1514 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1515 emit_int8(0x0F);
1516 emit_int8(0x40 | cc);
1517 emit_int8((unsigned char)(0xC0 | encode));
1518 }
1519
1520
1521 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1522 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1523 prefix(src, dst);
1524 emit_int8(0x0F);
1525 emit_int8(0x40 | cc);
1526 emit_operand(dst, src);
1527 }
1528
1529 void Assembler::cmpb(Address dst, int imm8) {
1530 InstructionMark im(this);
1531 prefix(dst);
1532 emit_int8((unsigned char)0x80);
1533 emit_operand(rdi, dst, 1);
1534 emit_int8(imm8);
1535 }
1536
1537 void Assembler::cmpl(Address dst, int32_t imm32) {
1538 InstructionMark im(this);
1539 prefix(dst);
1540 emit_int8((unsigned char)0x81);
1541 emit_operand(rdi, dst, 4);
1542 emit_int32(imm32);
1543 }
1544
1545 void Assembler::cmpl(Register dst, int32_t imm32) {
1546 prefix(dst);
1547 emit_arith(0x81, 0xF8, dst, imm32);
1548 }
1549
1550 void Assembler::cmpl(Register dst, Register src) {
1551 (void) prefix_and_encode(dst->encoding(), src->encoding());
1552 emit_arith(0x3B, 0xC0, dst, src);
1553 }
1554
1555 void Assembler::cmpl(Register dst, Address src) {
1556 InstructionMark im(this);
1557 prefix(src, dst);
1558 emit_int8((unsigned char)0x3B);
1559 emit_operand(dst, src);
1560 }
1561
1562 void Assembler::cmpw(Address dst, int imm16) {
1563 InstructionMark im(this);
1564 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1565 emit_int8(0x66);
1566 emit_int8((unsigned char)0x81);
1567 emit_operand(rdi, dst, 2);
1568 emit_int16(imm16);
1569 }
1570
1571 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1572 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1573 // The ZF is set if the compared values were equal, and cleared otherwise.
1574 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1575 InstructionMark im(this);
1576 prefix(adr, reg);
1577 emit_int8(0x0F);
1578 emit_int8((unsigned char)0xB1);
1579 emit_operand(reg, adr);
1580 }
1581
1582 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1583 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1584 // The ZF is set if the compared values were equal, and cleared otherwise.
1585 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1586 InstructionMark im(this);
1587 prefix(adr, reg, true);
1588 emit_int8(0x0F);
1589 emit_int8((unsigned char)0xB0);
1590 emit_operand(reg, adr);
1591 }
1592
1593 void Assembler::comisd(XMMRegister dst, Address src) {
1594 // NOTE: dbx seems to decode this as comiss even though the
1595 // 0x66 is there. Strangly ucomisd comes out correct
1596 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1597 InstructionMark im(this);
1598 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1599 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1600 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1601 emit_int8(0x2F);
1602 emit_operand(dst, src);
1603 }
1604
1605 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1606 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1607 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1608 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1609 emit_int8(0x2F);
1610 emit_int8((unsigned char)(0xC0 | encode));
1611 }
1612
1613 void Assembler::comiss(XMMRegister dst, Address src) {
1614 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1615 InstructionMark im(this);
1616 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1617 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1618 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1619 emit_int8(0x2F);
1620 emit_operand(dst, src);
1621 }
1622
1623 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1624 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1625 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1626 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1627 emit_int8(0x2F);
1628 emit_int8((unsigned char)(0xC0 | encode));
1629 }
1630
1631 void Assembler::cpuid() {
1632 emit_int8(0x0F);
1633 emit_int8((unsigned char)0xA2);
1634 }
1635
1636 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1637 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1638 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1639 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1640 //
1641 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1642 //
1643 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1644 //
1645 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1646 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1647 assert(VM_Version::supports_sse4_2(), "");
1648 int8_t w = 0x01;
1649 Prefix p = Prefix_EMPTY;
1650
1651 emit_int8((int8_t)0xF2);
1652 switch (sizeInBytes) {
1653 case 1:
1654 w = 0;
1655 break;
1656 case 2:
1657 case 4:
1658 break;
1659 LP64_ONLY(case 8:)
1660 // This instruction is not valid in 32 bits
1661 // Note:
1662 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1663 //
1664 // Page B - 72 Vol. 2C says
1665 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1666 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1667 // F0!!!
1668 // while 3 - 208 Vol. 2A
1669 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1670 //
1671 // the 0 on a last bit is reserved for a different flavor of this instruction :
1672 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1673 p = REX_W;
1674 break;
1675 default:
1676 assert(0, "Unsupported value for a sizeInBytes argument");
1677 break;
1678 }
1679 LP64_ONLY(prefix(crc, v, p);)
1680 emit_int8((int8_t)0x0F);
1681 emit_int8(0x38);
1682 emit_int8((int8_t)(0xF0 | w));
1683 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1684 }
1685
1686 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1687 assert(VM_Version::supports_sse4_2(), "");
1688 InstructionMark im(this);
1689 int8_t w = 0x01;
1690 Prefix p = Prefix_EMPTY;
1691
1692 emit_int8((int8_t)0xF2);
1693 switch (sizeInBytes) {
1694 case 1:
1695 w = 0;
1696 break;
1697 case 2:
1698 case 4:
1699 break;
1700 LP64_ONLY(case 8:)
1701 // This instruction is not valid in 32 bits
1702 p = REX_W;
1703 break;
1704 default:
1705 assert(0, "Unsupported value for a sizeInBytes argument");
1706 break;
1707 }
1708 LP64_ONLY(prefix(crc, adr, p);)
1709 emit_int8((int8_t)0x0F);
1710 emit_int8(0x38);
1711 emit_int8((int8_t)(0xF0 | w));
1712 emit_operand(crc, adr);
1713 }
1714
1715 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1717 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1718 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1719 emit_int8((unsigned char)0xE6);
1720 emit_int8((unsigned char)(0xC0 | encode));
1721 }
1722
1723 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1725 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1726 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1727 emit_int8(0x5B);
1728 emit_int8((unsigned char)(0xC0 | encode));
1729 }
1730
1731 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1732 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1733 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1734 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1735 emit_int8(0x5A);
1736 emit_int8((unsigned char)(0xC0 | encode));
1737 }
1738
1739 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1740 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1741 InstructionMark im(this);
1742 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1743 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1744 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1745 emit_int8(0x5A);
1746 emit_operand(dst, src);
1747 }
1748
1749 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1752 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1753 emit_int8(0x2A);
1754 emit_int8((unsigned char)(0xC0 | encode));
1755 }
1756
1757 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionMark im(this);
1760 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1761 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1762 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1763 emit_int8(0x2A);
1764 emit_operand(dst, src);
1765 }
1766
1767 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1768 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1769 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1770 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1771 emit_int8(0x2A);
1772 emit_int8((unsigned char)(0xC0 | encode));
1773 }
1774
1775 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1776 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1777 InstructionMark im(this);
1778 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1779 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1780 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1781 emit_int8(0x2A);
1782 emit_operand(dst, src);
1783 }
1784
1785 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1786 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1787 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1788 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1789 emit_int8(0x2A);
1790 emit_int8((unsigned char)(0xC0 | encode));
1791 }
1792
1793 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1794 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1796 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1797 emit_int8(0x5A);
1798 emit_int8((unsigned char)(0xC0 | encode));
1799 }
1800
1801 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1803 InstructionMark im(this);
1804 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1805 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1806 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1807 emit_int8(0x5A);
1808 emit_operand(dst, src);
1809 }
1810
1811
1812 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1813 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1814 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1815 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1816 emit_int8(0x2C);
1817 emit_int8((unsigned char)(0xC0 | encode));
1818 }
1819
1820 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1821 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1823 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1824 emit_int8(0x2C);
1825 emit_int8((unsigned char)(0xC0 | encode));
1826 }
1827
1828 void Assembler::decl(Address dst) {
1829 // Don't use it directly. Use MacroAssembler::decrement() instead.
1830 InstructionMark im(this);
1831 prefix(dst);
1832 emit_int8((unsigned char)0xFF);
1833 emit_operand(rcx, dst);
1834 }
1835
1836 void Assembler::divsd(XMMRegister dst, Address src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 InstructionMark im(this);
1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1840 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1841 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1842 emit_int8(0x5E);
1843 emit_operand(dst, src);
1844 }
1845
1846 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1847 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1848 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1849 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1850 emit_int8(0x5E);
1851 emit_int8((unsigned char)(0xC0 | encode));
1852 }
1853
1854 void Assembler::divss(XMMRegister dst, Address src) {
1855 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1856 InstructionMark im(this);
1857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1858 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1859 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x5E);
1861 emit_operand(dst, src);
1862 }
1863
1864 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1867 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1868 emit_int8(0x5E);
1869 emit_int8((unsigned char)(0xC0 | encode));
1870 }
1871
1872 void Assembler::emms() {
1873 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1874 emit_int8(0x0F);
1875 emit_int8(0x77);
1876 }
1877
1878 void Assembler::hlt() {
1879 emit_int8((unsigned char)0xF4);
1880 }
1881
1882 void Assembler::idivl(Register src) {
1883 int encode = prefix_and_encode(src->encoding());
1884 emit_int8((unsigned char)0xF7);
1885 emit_int8((unsigned char)(0xF8 | encode));
1886 }
1887
1888 void Assembler::divl(Register src) { // Unsigned
1889 int encode = prefix_and_encode(src->encoding());
1890 emit_int8((unsigned char)0xF7);
1891 emit_int8((unsigned char)(0xF0 | encode));
1892 }
1893
1894 void Assembler::imull(Register src) {
1895 int encode = prefix_and_encode(src->encoding());
1896 emit_int8((unsigned char)0xF7);
1897 emit_int8((unsigned char)(0xE8 | encode));
1898 }
1899
1900 void Assembler::imull(Register dst, Register src) {
1901 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1902 emit_int8(0x0F);
1903 emit_int8((unsigned char)0xAF);
1904 emit_int8((unsigned char)(0xC0 | encode));
1905 }
1906
1907
1908 void Assembler::imull(Register dst, Register src, int value) {
1909 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1910 if (is8bit(value)) {
1911 emit_int8(0x6B);
1912 emit_int8((unsigned char)(0xC0 | encode));
1913 emit_int8(value & 0xFF);
1914 } else {
1915 emit_int8(0x69);
1916 emit_int8((unsigned char)(0xC0 | encode));
1917 emit_int32(value);
1918 }
1919 }
1920
1921 void Assembler::imull(Register dst, Address src) {
1922 InstructionMark im(this);
1923 prefix(src, dst);
1924 emit_int8(0x0F);
1925 emit_int8((unsigned char) 0xAF);
1926 emit_operand(dst, src);
1927 }
1928
1929
1930 void Assembler::incl(Address dst) {
1931 // Don't use it directly. Use MacroAssembler::increment() instead.
1932 InstructionMark im(this);
1933 prefix(dst);
1934 emit_int8((unsigned char)0xFF);
1935 emit_operand(rax, dst);
1936 }
1937
1938 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1939 InstructionMark im(this);
1940 assert((0 <= cc) && (cc < 16), "illegal cc");
1941 if (L.is_bound()) {
1942 address dst = target(L);
1943 assert(dst != NULL, "jcc most probably wrong");
1944
1945 const int short_size = 2;
1946 const int long_size = 6;
1947 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1948 if (maybe_short && is8bit(offs - short_size)) {
1949 // 0111 tttn #8-bit disp
1950 emit_int8(0x70 | cc);
1951 emit_int8((offs - short_size) & 0xFF);
1952 } else {
1953 // 0000 1111 1000 tttn #32-bit disp
1954 assert(is_simm32(offs - long_size),
1955 "must be 32bit offset (call4)");
1956 emit_int8(0x0F);
1957 emit_int8((unsigned char)(0x80 | cc));
1958 emit_int32(offs - long_size);
1959 }
1960 } else {
1961 // Note: could eliminate cond. jumps to this jump if condition
1962 // is the same however, seems to be rather unlikely case.
1963 // Note: use jccb() if label to be bound is very close to get
1964 // an 8-bit displacement
1965 L.add_patch_at(code(), locator());
1966 emit_int8(0x0F);
1967 emit_int8((unsigned char)(0x80 | cc));
1968 emit_int32(0);
1969 }
1970 }
1971
1972 void Assembler::jccb(Condition cc, Label& L) {
1973 if (L.is_bound()) {
1974 const int short_size = 2;
1975 address entry = target(L);
1976 #ifdef ASSERT
1977 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1978 intptr_t delta = short_branch_delta();
1979 if (delta != 0) {
1980 dist += (dist < 0 ? (-delta) :delta);
1981 }
1982 assert(is8bit(dist), "Dispacement too large for a short jmp");
1983 #endif
1984 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1985 // 0111 tttn #8-bit disp
1986 emit_int8(0x70 | cc);
1987 emit_int8((offs - short_size) & 0xFF);
1988 } else {
1989 InstructionMark im(this);
1990 L.add_patch_at(code(), locator());
1991 emit_int8(0x70 | cc);
1992 emit_int8(0);
1993 }
1994 }
1995
1996 void Assembler::jmp(Address adr) {
1997 InstructionMark im(this);
1998 prefix(adr);
1999 emit_int8((unsigned char)0xFF);
2000 emit_operand(rsp, adr);
2001 }
2002
2003 void Assembler::jmp(Label& L, bool maybe_short) {
2004 if (L.is_bound()) {
2005 address entry = target(L);
2006 assert(entry != NULL, "jmp most probably wrong");
2007 InstructionMark im(this);
2008 const int short_size = 2;
2009 const int long_size = 5;
2010 intptr_t offs = entry - pc();
2011 if (maybe_short && is8bit(offs - short_size)) {
2012 emit_int8((unsigned char)0xEB);
2013 emit_int8((offs - short_size) & 0xFF);
2014 } else {
2015 emit_int8((unsigned char)0xE9);
2016 emit_int32(offs - long_size);
2017 }
2018 } else {
2019 // By default, forward jumps are always 32-bit displacements, since
2020 // we can't yet know where the label will be bound. If you're sure that
2021 // the forward jump will not run beyond 256 bytes, use jmpb to
2022 // force an 8-bit displacement.
2023 InstructionMark im(this);
2024 L.add_patch_at(code(), locator());
2025 emit_int8((unsigned char)0xE9);
2026 emit_int32(0);
2027 }
2028 }
2029
2030 void Assembler::jmp(Register entry) {
2031 int encode = prefix_and_encode(entry->encoding());
2032 emit_int8((unsigned char)0xFF);
2033 emit_int8((unsigned char)(0xE0 | encode));
2034 }
2035
2036 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2037 InstructionMark im(this);
2038 emit_int8((unsigned char)0xE9);
2039 assert(dest != NULL, "must have a target");
2040 intptr_t disp = dest - (pc() + sizeof(int32_t));
2041 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2042 emit_data(disp, rspec.reloc(), call32_operand);
2043 }
2044
2045 void Assembler::jmpb(Label& L) {
2046 if (L.is_bound()) {
2047 const int short_size = 2;
2048 address entry = target(L);
2049 assert(entry != NULL, "jmp most probably wrong");
2050 #ifdef ASSERT
2051 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2052 intptr_t delta = short_branch_delta();
2053 if (delta != 0) {
2054 dist += (dist < 0 ? (-delta) :delta);
2055 }
2056 assert(is8bit(dist), "Dispacement too large for a short jmp");
2057 #endif
2058 intptr_t offs = entry - pc();
2059 emit_int8((unsigned char)0xEB);
2060 emit_int8((offs - short_size) & 0xFF);
2061 } else {
2062 InstructionMark im(this);
2063 L.add_patch_at(code(), locator());
2064 emit_int8((unsigned char)0xEB);
2065 emit_int8(0);
2066 }
2067 }
2068
2069 void Assembler::ldmxcsr( Address src) {
2070 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2071 InstructionMark im(this);
2072 prefix(src);
2073 emit_int8(0x0F);
2074 emit_int8((unsigned char)0xAE);
2075 emit_operand(as_Register(2), src);
2076 }
2077
2078 void Assembler::leal(Register dst, Address src) {
2079 InstructionMark im(this);
2080 #ifdef _LP64
2081 emit_int8(0x67); // addr32
2082 prefix(src, dst);
2083 #endif // LP64
2084 emit_int8((unsigned char)0x8D);
2085 emit_operand(dst, src);
2086 }
2087
2088 void Assembler::lfence() {
2089 emit_int8(0x0F);
2090 emit_int8((unsigned char)0xAE);
2091 emit_int8((unsigned char)0xE8);
2092 }
2093
2094 void Assembler::lock() {
2095 emit_int8((unsigned char)0xF0);
2096 }
2097
2098 void Assembler::lzcntl(Register dst, Register src) {
2099 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2100 emit_int8((unsigned char)0xF3);
2101 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2102 emit_int8(0x0F);
2103 emit_int8((unsigned char)0xBD);
2104 emit_int8((unsigned char)(0xC0 | encode));
2105 }
2106
2107 // Emit mfence instruction
2108 void Assembler::mfence() {
2109 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2110 emit_int8(0x0F);
2111 emit_int8((unsigned char)0xAE);
2112 emit_int8((unsigned char)0xF0);
2113 }
2114
2115 void Assembler::mov(Register dst, Register src) {
2116 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2117 }
2118
2119 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2120 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2121 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2122 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2123 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2124 emit_int8(0x28);
2125 emit_int8((unsigned char)(0xC0 | encode));
2126 }
2127
2128 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2129 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2130 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2131 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2132 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2133 emit_int8(0x28);
2134 emit_int8((unsigned char)(0xC0 | encode));
2135 }
2136
2137 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2138 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2139 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2140 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2141 emit_int8(0x16);
2142 emit_int8((unsigned char)(0xC0 | encode));
2143 }
2144
2145 void Assembler::movb(Register dst, Address src) {
2146 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2147 InstructionMark im(this);
2148 prefix(src, dst, true);
2149 emit_int8((unsigned char)0x8A);
2150 emit_operand(dst, src);
2151 }
2152
2153 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2154 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2155 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
2156 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2157 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2158 emit_int8(0x12);
2159 emit_int8(0xC0 | encode);
2160 }
2161
2162 void Assembler::kmovql(KRegister dst, KRegister src) {
2163 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2164 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2165 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2166 emit_int8((unsigned char)0x90);
2167 emit_int8((unsigned char)(0xC0 | encode));
2168 }
2169
2170 void Assembler::kmovql(KRegister dst, Address src) {
2171 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2172 InstructionMark im(this);
2173 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2174 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2175 emit_int8((unsigned char)0x90);
2176 emit_operand((Register)dst, src);
2177 }
2178
2179 void Assembler::kmovql(Address dst, KRegister src) {
2180 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2181 InstructionMark im(this);
2182 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2183 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2184 emit_int8((unsigned char)0x90);
2185 emit_operand((Register)src, dst);
2186 }
2187
2188 void Assembler::kmovql(KRegister dst, Register src) {
2189 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2190 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2191 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_bw, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2192 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, VEX_OPCODE_0F, &attributes);
2193 emit_int8((unsigned char)0x92);
2194 emit_int8((unsigned char)(0xC0 | encode));
2195 }
2196
2197 void Assembler::kmovdl(KRegister dst, Register src) {
2198 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2199 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2200 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2201 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, VEX_OPCODE_0F, &attributes);
2202 emit_int8((unsigned char)0x92);
2203 emit_int8((unsigned char)(0xC0 | encode));
2204 }
2205
2206 void Assembler::kmovwl(KRegister dst, Register src) {
2207 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2208 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2209 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2210 emit_int8((unsigned char)0x92);
2211 emit_int8((unsigned char)(0xC0 | encode));
2212 }
2213
2214 void Assembler::movb(Address dst, int imm8) {
2215 InstructionMark im(this);
2216 prefix(dst);
2217 emit_int8((unsigned char)0xC6);
2218 emit_operand(rax, dst, 1);
2219 emit_int8(imm8);
2220 }
2221
2222
2223 void Assembler::movb(Address dst, Register src) {
2224 assert(src->has_byte_register(), "must have byte register");
2225 InstructionMark im(this);
2226 prefix(dst, src, true);
2227 emit_int8((unsigned char)0x88);
2228 emit_operand(src, dst);
2229 }
2230
2231 void Assembler::movdl(XMMRegister dst, Register src) {
2232 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2233 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2234 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2235 emit_int8(0x6E);
2236 emit_int8((unsigned char)(0xC0 | encode));
2237 }
2238
2239 void Assembler::movdl(Register dst, XMMRegister src) {
2240 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2241 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2242 // swap src/dst to get correct prefix
2243 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2244 emit_int8(0x7E);
2245 emit_int8((unsigned char)(0xC0 | encode));
2246 }
2247
2248 void Assembler::movdl(XMMRegister dst, Address src) {
2249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2250 InstructionMark im(this);
2251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2252 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2253 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2254 emit_int8(0x6E);
2255 emit_operand(dst, src);
2256 }
2257
2258 void Assembler::movdl(Address dst, XMMRegister src) {
2259 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2260 InstructionMark im(this);
2261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2262 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2263 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2264 emit_int8(0x7E);
2265 emit_operand(src, dst);
2266 }
2267
2268 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2269 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2270 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2271 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2272 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2273 emit_int8(0x6F);
2274 emit_int8((unsigned char)(0xC0 | encode));
2275 }
2276
2277 void Assembler::movdqa(XMMRegister dst, Address src) {
2278 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2279 InstructionMark im(this);
2280 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2281 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2282 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2283 emit_int8(0x6F);
2284 emit_operand(dst, src);
2285 }
2286
2287 void Assembler::movdqu(XMMRegister dst, Address src) {
2288 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2289 InstructionMark im(this);
2290 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2291 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2292 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2293 emit_int8(0x6F);
2294 emit_operand(dst, src);
2295 }
2296
2297 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2298 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2299 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2300 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2301 emit_int8(0x6F);
2302 emit_int8((unsigned char)(0xC0 | encode));
2303 }
2304
2305 void Assembler::movdqu(Address dst, XMMRegister src) {
2306 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2307 InstructionMark im(this);
2308 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2309 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2310 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2311 emit_int8(0x7F);
2312 emit_operand(src, dst);
2313 }
2314
2315 // Move Unaligned 256bit Vector
2316 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2317 assert(UseAVX > 0, "");
2318 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2319 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2320 emit_int8(0x6F);
2321 emit_int8((unsigned char)(0xC0 | encode));
2322 }
2323
2324 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2325 assert(UseAVX > 0, "");
2326 InstructionMark im(this);
2327 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2328 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2329 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2330 emit_int8(0x6F);
2331 emit_operand(dst, src);
2332 }
2333
2334 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2335 assert(UseAVX > 0, "");
2336 InstructionMark im(this);
2337 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2338 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2339 // swap src<->dst for encoding
2340 assert(src != xnoreg, "sanity");
2341 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2342 emit_int8(0x7F);
2343 emit_operand(src, dst);
2344 }
2345
2346 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2347 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2348 assert(VM_Version::supports_evex(), "");
2349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2350 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2351 emit_int8(0x6F);
2352 emit_int8((unsigned char)(0xC0 | encode));
2353 }
2354
2355 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2356 assert(VM_Version::supports_evex(), "");
2357 InstructionMark im(this);
2358 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2359 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2360 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2361 emit_int8(0x6F);
2362 emit_operand(dst, src);
2363 }
2364
2365 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2366 assert(VM_Version::supports_evex(), "");
2367 assert(src != xnoreg, "sanity");
2368 InstructionMark im(this);
2369 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2370 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2371 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2372 emit_int8(0x7F);
2373 emit_operand(src, dst);
2374 }
2375
2376 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2377 assert(VM_Version::supports_evex(), "");
2378 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2379 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2380 emit_int8(0x6F);
2381 emit_int8((unsigned char)(0xC0 | encode));
2382 }
2383
2384 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2385 assert(VM_Version::supports_evex(), "");
2386 InstructionMark im(this);
2387 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2388 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2389 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2390 emit_int8(0x6F);
2391 emit_operand(dst, src);
2392 }
2393
2394 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2395 assert(VM_Version::supports_evex(), "");
2396 assert(src != xnoreg, "sanity");
2397 InstructionMark im(this);
2398 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2399 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2400 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2401 emit_int8(0x7F);
2402 emit_operand(src, dst);
2403 }
2404
2405 // Uses zero extension on 64bit
2406
2407 void Assembler::movl(Register dst, int32_t imm32) {
2408 int encode = prefix_and_encode(dst->encoding());
2409 emit_int8((unsigned char)(0xB8 | encode));
2410 emit_int32(imm32);
2411 }
2412
2413 void Assembler::movl(Register dst, Register src) {
2414 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2415 emit_int8((unsigned char)0x8B);
2416 emit_int8((unsigned char)(0xC0 | encode));
2417 }
2418
2419 void Assembler::movl(Register dst, Address src) {
2420 InstructionMark im(this);
2421 prefix(src, dst);
2422 emit_int8((unsigned char)0x8B);
2423 emit_operand(dst, src);
2424 }
2425
2426 void Assembler::movl(Address dst, int32_t imm32) {
2427 InstructionMark im(this);
2428 prefix(dst);
2429 emit_int8((unsigned char)0xC7);
2430 emit_operand(rax, dst, 4);
2431 emit_int32(imm32);
2432 }
2433
2434 void Assembler::movl(Address dst, Register src) {
2435 InstructionMark im(this);
2436 prefix(dst, src);
2437 emit_int8((unsigned char)0x89);
2438 emit_operand(src, dst);
2439 }
2440
2441 // New cpus require to use movsd and movss to avoid partial register stall
2442 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2443 // The selection is done in MacroAssembler::movdbl() and movflt().
2444 void Assembler::movlpd(XMMRegister dst, Address src) {
2445 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2446 InstructionMark im(this);
2447 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2448 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2449 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2450 emit_int8(0x12);
2451 emit_operand(dst, src);
2452 }
2453
2454 void Assembler::movq( MMXRegister dst, Address src ) {
2455 assert( VM_Version::supports_mmx(), "" );
2456 emit_int8(0x0F);
2457 emit_int8(0x6F);
2458 emit_operand(dst, src);
2459 }
2460
2461 void Assembler::movq( Address dst, MMXRegister src ) {
2462 assert( VM_Version::supports_mmx(), "" );
2463 emit_int8(0x0F);
2464 emit_int8(0x7F);
2465 // workaround gcc (3.2.1-7a) bug
2466 // In that version of gcc with only an emit_operand(MMX, Address)
2467 // gcc will tail jump and try and reverse the parameters completely
2468 // obliterating dst in the process. By having a version available
2469 // that doesn't need to swap the args at the tail jump the bug is
2470 // avoided.
2471 emit_operand(dst, src);
2472 }
2473
2474 void Assembler::movq(XMMRegister dst, Address src) {
2475 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2476 InstructionMark im(this);
2477 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2478 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2479 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2480 emit_int8(0x7E);
2481 emit_operand(dst, src);
2482 }
2483
2484 void Assembler::movq(Address dst, XMMRegister src) {
2485 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2486 InstructionMark im(this);
2487 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2488 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2489 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2490 emit_int8((unsigned char)0xD6);
2491 emit_operand(src, dst);
2492 }
2493
2494 void Assembler::movsbl(Register dst, Address src) { // movsxb
2495 InstructionMark im(this);
2496 prefix(src, dst);
2497 emit_int8(0x0F);
2498 emit_int8((unsigned char)0xBE);
2499 emit_operand(dst, src);
2500 }
2501
2502 void Assembler::movsbl(Register dst, Register src) { // movsxb
2503 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2504 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2505 emit_int8(0x0F);
2506 emit_int8((unsigned char)0xBE);
2507 emit_int8((unsigned char)(0xC0 | encode));
2508 }
2509
2510 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2511 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2512 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2513 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2514 emit_int8(0x10);
2515 emit_int8((unsigned char)(0xC0 | encode));
2516 }
2517
2518 void Assembler::movsd(XMMRegister dst, Address src) {
2519 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2520 InstructionMark im(this);
2521 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2522 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2523 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2524 emit_int8(0x10);
2525 emit_operand(dst, src);
2526 }
2527
2528 void Assembler::movsd(Address dst, XMMRegister src) {
2529 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2530 InstructionMark im(this);
2531 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2532 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2533 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2534 emit_int8(0x11);
2535 emit_operand(src, dst);
2536 }
2537
2538 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2539 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2540 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2541 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2542 emit_int8(0x10);
2543 emit_int8((unsigned char)(0xC0 | encode));
2544 }
2545
2546 void Assembler::movss(XMMRegister dst, Address src) {
2547 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2548 InstructionMark im(this);
2549 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2550 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2551 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2552 emit_int8(0x10);
2553 emit_operand(dst, src);
2554 }
2555
2556 void Assembler::movss(Address dst, XMMRegister src) {
2557 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2558 InstructionMark im(this);
2559 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2560 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2561 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2562 emit_int8(0x11);
2563 emit_operand(src, dst);
2564 }
2565
2566 void Assembler::movswl(Register dst, Address src) { // movsxw
2567 InstructionMark im(this);
2568 prefix(src, dst);
2569 emit_int8(0x0F);
2570 emit_int8((unsigned char)0xBF);
2571 emit_operand(dst, src);
2572 }
2573
2574 void Assembler::movswl(Register dst, Register src) { // movsxw
2575 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2576 emit_int8(0x0F);
2577 emit_int8((unsigned char)0xBF);
2578 emit_int8((unsigned char)(0xC0 | encode));
2579 }
2580
2581 void Assembler::movw(Address dst, int imm16) {
2582 InstructionMark im(this);
2583
2584 emit_int8(0x66); // switch to 16-bit mode
2585 prefix(dst);
2586 emit_int8((unsigned char)0xC7);
2587 emit_operand(rax, dst, 2);
2588 emit_int16(imm16);
2589 }
2590
2591 void Assembler::movw(Register dst, Address src) {
2592 InstructionMark im(this);
2593 emit_int8(0x66);
2594 prefix(src, dst);
2595 emit_int8((unsigned char)0x8B);
2596 emit_operand(dst, src);
2597 }
2598
2599 void Assembler::movw(Address dst, Register src) {
2600 InstructionMark im(this);
2601 emit_int8(0x66);
2602 prefix(dst, src);
2603 emit_int8((unsigned char)0x89);
2604 emit_operand(src, dst);
2605 }
2606
2607 void Assembler::movzbl(Register dst, Address src) { // movzxb
2608 InstructionMark im(this);
2609 prefix(src, dst);
2610 emit_int8(0x0F);
2611 emit_int8((unsigned char)0xB6);
2612 emit_operand(dst, src);
2613 }
2614
2615 void Assembler::movzbl(Register dst, Register src) { // movzxb
2616 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2617 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2618 emit_int8(0x0F);
2619 emit_int8((unsigned char)0xB6);
2620 emit_int8(0xC0 | encode);
2621 }
2622
2623 void Assembler::movzwl(Register dst, Address src) { // movzxw
2624 InstructionMark im(this);
2625 prefix(src, dst);
2626 emit_int8(0x0F);
2627 emit_int8((unsigned char)0xB7);
2628 emit_operand(dst, src);
2629 }
2630
2631 void Assembler::movzwl(Register dst, Register src) { // movzxw
2632 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2633 emit_int8(0x0F);
2634 emit_int8((unsigned char)0xB7);
2635 emit_int8(0xC0 | encode);
2636 }
2637
2638 void Assembler::mull(Address src) {
2639 InstructionMark im(this);
2640 prefix(src);
2641 emit_int8((unsigned char)0xF7);
2642 emit_operand(rsp, src);
2643 }
2644
2645 void Assembler::mull(Register src) {
2646 int encode = prefix_and_encode(src->encoding());
2647 emit_int8((unsigned char)0xF7);
2648 emit_int8((unsigned char)(0xE0 | encode));
2649 }
2650
2651 void Assembler::mulsd(XMMRegister dst, Address src) {
2652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2653 InstructionMark im(this);
2654 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2655 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2656 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2657 emit_int8(0x59);
2658 emit_operand(dst, src);
2659 }
2660
2661 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2662 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2663 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2664 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2665 emit_int8(0x59);
2666 emit_int8((unsigned char)(0xC0 | encode));
2667 }
2668
2669 void Assembler::mulss(XMMRegister dst, Address src) {
2670 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2671 InstructionMark im(this);
2672 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2673 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2674 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2675 emit_int8(0x59);
2676 emit_operand(dst, src);
2677 }
2678
2679 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2680 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2681 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2682 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2683 emit_int8(0x59);
2684 emit_int8((unsigned char)(0xC0 | encode));
2685 }
2686
2687 void Assembler::negl(Register dst) {
2688 int encode = prefix_and_encode(dst->encoding());
2689 emit_int8((unsigned char)0xF7);
2690 emit_int8((unsigned char)(0xD8 | encode));
2691 }
2692
2693 void Assembler::nop(int i) {
2694 #ifdef ASSERT
2695 assert(i > 0, " ");
2696 // The fancy nops aren't currently recognized by debuggers making it a
2697 // pain to disassemble code while debugging. If asserts are on clearly
2698 // speed is not an issue so simply use the single byte traditional nop
2699 // to do alignment.
2700
2701 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2702 return;
2703
2704 #endif // ASSERT
2705
2706 if (UseAddressNop && VM_Version::is_intel()) {
2707 //
2708 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2709 // 1: 0x90
2710 // 2: 0x66 0x90
2711 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2712 // 4: 0x0F 0x1F 0x40 0x00
2713 // 5: 0x0F 0x1F 0x44 0x00 0x00
2714 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2715 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2716 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2717 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2718 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2719 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2720
2721 // The rest coding is Intel specific - don't use consecutive address nops
2722
2723 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2724 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2725 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2726 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2727
2728 while(i >= 15) {
2729 // For Intel don't generate consecutive addess nops (mix with regular nops)
2730 i -= 15;
2731 emit_int8(0x66); // size prefix
2732 emit_int8(0x66); // size prefix
2733 emit_int8(0x66); // size prefix
2734 addr_nop_8();
2735 emit_int8(0x66); // size prefix
2736 emit_int8(0x66); // size prefix
2737 emit_int8(0x66); // size prefix
2738 emit_int8((unsigned char)0x90);
2739 // nop
2740 }
2741 switch (i) {
2742 case 14:
2743 emit_int8(0x66); // size prefix
2744 case 13:
2745 emit_int8(0x66); // size prefix
2746 case 12:
2747 addr_nop_8();
2748 emit_int8(0x66); // size prefix
2749 emit_int8(0x66); // size prefix
2750 emit_int8(0x66); // size prefix
2751 emit_int8((unsigned char)0x90);
2752 // nop
2753 break;
2754 case 11:
2755 emit_int8(0x66); // size prefix
2756 case 10:
2757 emit_int8(0x66); // size prefix
2758 case 9:
2759 emit_int8(0x66); // size prefix
2760 case 8:
2761 addr_nop_8();
2762 break;
2763 case 7:
2764 addr_nop_7();
2765 break;
2766 case 6:
2767 emit_int8(0x66); // size prefix
2768 case 5:
2769 addr_nop_5();
2770 break;
2771 case 4:
2772 addr_nop_4();
2773 break;
2774 case 3:
2775 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2776 emit_int8(0x66); // size prefix
2777 case 2:
2778 emit_int8(0x66); // size prefix
2779 case 1:
2780 emit_int8((unsigned char)0x90);
2781 // nop
2782 break;
2783 default:
2784 assert(i == 0, " ");
2785 }
2786 return;
2787 }
2788 if (UseAddressNop && VM_Version::is_amd()) {
2789 //
2790 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2791 // 1: 0x90
2792 // 2: 0x66 0x90
2793 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2794 // 4: 0x0F 0x1F 0x40 0x00
2795 // 5: 0x0F 0x1F 0x44 0x00 0x00
2796 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2797 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2798 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2799 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2800 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2801 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2802
2803 // The rest coding is AMD specific - use consecutive address nops
2804
2805 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2806 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2807 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2808 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2809 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2810 // Size prefixes (0x66) are added for larger sizes
2811
2812 while(i >= 22) {
2813 i -= 11;
2814 emit_int8(0x66); // size prefix
2815 emit_int8(0x66); // size prefix
2816 emit_int8(0x66); // size prefix
2817 addr_nop_8();
2818 }
2819 // Generate first nop for size between 21-12
2820 switch (i) {
2821 case 21:
2822 i -= 1;
2823 emit_int8(0x66); // size prefix
2824 case 20:
2825 case 19:
2826 i -= 1;
2827 emit_int8(0x66); // size prefix
2828 case 18:
2829 case 17:
2830 i -= 1;
2831 emit_int8(0x66); // size prefix
2832 case 16:
2833 case 15:
2834 i -= 8;
2835 addr_nop_8();
2836 break;
2837 case 14:
2838 case 13:
2839 i -= 7;
2840 addr_nop_7();
2841 break;
2842 case 12:
2843 i -= 6;
2844 emit_int8(0x66); // size prefix
2845 addr_nop_5();
2846 break;
2847 default:
2848 assert(i < 12, " ");
2849 }
2850
2851 // Generate second nop for size between 11-1
2852 switch (i) {
2853 case 11:
2854 emit_int8(0x66); // size prefix
2855 case 10:
2856 emit_int8(0x66); // size prefix
2857 case 9:
2858 emit_int8(0x66); // size prefix
2859 case 8:
2860 addr_nop_8();
2861 break;
2862 case 7:
2863 addr_nop_7();
2864 break;
2865 case 6:
2866 emit_int8(0x66); // size prefix
2867 case 5:
2868 addr_nop_5();
2869 break;
2870 case 4:
2871 addr_nop_4();
2872 break;
2873 case 3:
2874 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2875 emit_int8(0x66); // size prefix
2876 case 2:
2877 emit_int8(0x66); // size prefix
2878 case 1:
2879 emit_int8((unsigned char)0x90);
2880 // nop
2881 break;
2882 default:
2883 assert(i == 0, " ");
2884 }
2885 return;
2886 }
2887
2888 // Using nops with size prefixes "0x66 0x90".
2889 // From AMD Optimization Guide:
2890 // 1: 0x90
2891 // 2: 0x66 0x90
2892 // 3: 0x66 0x66 0x90
2893 // 4: 0x66 0x66 0x66 0x90
2894 // 5: 0x66 0x66 0x90 0x66 0x90
2895 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2896 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2897 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2898 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2899 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2900 //
2901 while(i > 12) {
2902 i -= 4;
2903 emit_int8(0x66); // size prefix
2904 emit_int8(0x66);
2905 emit_int8(0x66);
2906 emit_int8((unsigned char)0x90);
2907 // nop
2908 }
2909 // 1 - 12 nops
2910 if(i > 8) {
2911 if(i > 9) {
2912 i -= 1;
2913 emit_int8(0x66);
2914 }
2915 i -= 3;
2916 emit_int8(0x66);
2917 emit_int8(0x66);
2918 emit_int8((unsigned char)0x90);
2919 }
2920 // 1 - 8 nops
2921 if(i > 4) {
2922 if(i > 6) {
2923 i -= 1;
2924 emit_int8(0x66);
2925 }
2926 i -= 3;
2927 emit_int8(0x66);
2928 emit_int8(0x66);
2929 emit_int8((unsigned char)0x90);
2930 }
2931 switch (i) {
2932 case 4:
2933 emit_int8(0x66);
2934 case 3:
2935 emit_int8(0x66);
2936 case 2:
2937 emit_int8(0x66);
2938 case 1:
2939 emit_int8((unsigned char)0x90);
2940 break;
2941 default:
2942 assert(i == 0, " ");
2943 }
2944 }
2945
2946 void Assembler::notl(Register dst) {
2947 int encode = prefix_and_encode(dst->encoding());
2948 emit_int8((unsigned char)0xF7);
2949 emit_int8((unsigned char)(0xD0 | encode));
2950 }
2951
2952 void Assembler::orl(Address dst, int32_t imm32) {
2953 InstructionMark im(this);
2954 prefix(dst);
2955 emit_arith_operand(0x81, rcx, dst, imm32);
2956 }
2957
2958 void Assembler::orl(Register dst, int32_t imm32) {
2959 prefix(dst);
2960 emit_arith(0x81, 0xC8, dst, imm32);
2961 }
2962
2963 void Assembler::orl(Register dst, Address src) {
2964 InstructionMark im(this);
2965 prefix(src, dst);
2966 emit_int8(0x0B);
2967 emit_operand(dst, src);
2968 }
2969
2970 void Assembler::orl(Register dst, Register src) {
2971 (void) prefix_and_encode(dst->encoding(), src->encoding());
2972 emit_arith(0x0B, 0xC0, dst, src);
2973 }
2974
2975 void Assembler::orl(Address dst, Register src) {
2976 InstructionMark im(this);
2977 prefix(dst, src);
2978 emit_int8(0x09);
2979 emit_operand(src, dst);
2980 }
2981
2982 void Assembler::packuswb(XMMRegister dst, Address src) {
2983 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2984 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
2985 InstructionMark im(this);
2986 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2987 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
2988 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2989 emit_int8(0x67);
2990 emit_operand(dst, src);
2991 }
2992
2993 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
2994 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2996 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2997 emit_int8(0x67);
2998 emit_int8((unsigned char)(0xC0 | encode));
2999 }
3000
3001 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3002 assert(UseAVX > 0, "some form of AVX must be enabled");
3003 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3004 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3005 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3006 emit_int8(0x67);
3007 emit_int8((unsigned char)(0xC0 | encode));
3008 }
3009
3010 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3011 assert(VM_Version::supports_avx2(), "");
3012 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3013 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3014 emit_int8(0x00);
3015 emit_int8(0xC0 | encode);
3016 emit_int8(imm8);
3017 }
3018
3019 void Assembler::pause() {
3020 emit_int8((unsigned char)0xF3);
3021 emit_int8((unsigned char)0x90);
3022 }
3023
3024 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3025 assert(VM_Version::supports_sse4_2(), "");
3026 InstructionMark im(this);
3027 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3028 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3029 emit_int8(0x61);
3030 emit_operand(dst, src);
3031 emit_int8(imm8);
3032 }
3033
3034 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3035 assert(VM_Version::supports_sse4_2(), "");
3036 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3037 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3038 emit_int8(0x61);
3039 emit_int8((unsigned char)(0xC0 | encode));
3040 emit_int8(imm8);
3041 }
3042
3043 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3045 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3046 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3047 emit_int8(0x75);
3048 emit_int8((unsigned char)(0xC0 | encode));
3049 }
3050
3051 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3052 assert(VM_Version::supports_avx(), "");
3053 assert(!VM_Version::supports_evex(), "");
3054 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3055 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3056 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3057 emit_int8(0x75);
3058 emit_int8((unsigned char)(0xC0 | encode));
3059 }
3060
3061 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3062 assert(VM_Version::supports_sse2(), "");
3063 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3064 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3065 emit_int8((unsigned char)0xD7);
3066 emit_int8((unsigned char)(0xC0 | encode));
3067 }
3068
3069 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3070 assert(VM_Version::supports_avx2(), "");
3071 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3072 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3073 emit_int8((unsigned char)0xD7);
3074 emit_int8((unsigned char)(0xC0 | encode));
3075 }
3076
3077 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3078 assert(VM_Version::supports_sse4_1(), "");
3079 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3080 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3081 emit_int8(0x16);
3082 emit_int8((unsigned char)(0xC0 | encode));
3083 emit_int8(imm8);
3084 }
3085
3086 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3087 assert(VM_Version::supports_sse4_1(), "");
3088 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3089 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3090 emit_int8(0x16);
3091 emit_int8((unsigned char)(0xC0 | encode));
3092 emit_int8(imm8);
3093 }
3094
3095 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3096 assert(VM_Version::supports_sse2(), "");
3097 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3098 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3099 emit_int8((unsigned char)0xC5);
3100 emit_int8((unsigned char)(0xC0 | encode));
3101 emit_int8(imm8);
3102 }
3103
3104 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3105 assert(VM_Version::supports_sse4_1(), "");
3106 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3107 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3108 emit_int8(0x22);
3109 emit_int8((unsigned char)(0xC0 | encode));
3110 emit_int8(imm8);
3111 }
3112
3113 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3114 assert(VM_Version::supports_sse4_1(), "");
3115 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3116 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3117 emit_int8(0x22);
3118 emit_int8((unsigned char)(0xC0 | encode));
3119 emit_int8(imm8);
3120 }
3121
3122 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3123 assert(VM_Version::supports_sse2(), "");
3124 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3125 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3126 emit_int8((unsigned char)0xC4);
3127 emit_int8((unsigned char)(0xC0 | encode));
3128 emit_int8(imm8);
3129 }
3130
3131 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3132 assert(VM_Version::supports_sse4_1(), "");
3133 InstructionMark im(this);
3134 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3135 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3136 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3137 emit_int8(0x30);
3138 emit_operand(dst, src);
3139 }
3140
3141 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3142 assert(VM_Version::supports_sse4_1(), "");
3143 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3144 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3145 emit_int8(0x30);
3146 emit_int8((unsigned char)(0xC0 | encode));
3147 }
3148
3149 void Assembler::vpmovzxbw(XMMRegister dst, Address src) {
3150 assert(VM_Version::supports_avx(), "");
3151 InstructionMark im(this);
3152 assert(dst != xnoreg, "sanity");
3153 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3154 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3155 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3156 emit_int8(0x30);
3157 emit_operand(dst, src);
3158 }
3159
3160 // generic
3161 void Assembler::pop(Register dst) {
3162 int encode = prefix_and_encode(dst->encoding());
3163 emit_int8(0x58 | encode);
3164 }
3165
3166 void Assembler::popcntl(Register dst, Address src) {
3167 assert(VM_Version::supports_popcnt(), "must support");
3168 InstructionMark im(this);
3169 emit_int8((unsigned char)0xF3);
3170 prefix(src, dst);
3171 emit_int8(0x0F);
3172 emit_int8((unsigned char)0xB8);
3173 emit_operand(dst, src);
3174 }
3175
3176 void Assembler::popcntl(Register dst, Register src) {
3177 assert(VM_Version::supports_popcnt(), "must support");
3178 emit_int8((unsigned char)0xF3);
3179 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3180 emit_int8(0x0F);
3181 emit_int8((unsigned char)0xB8);
3182 emit_int8((unsigned char)(0xC0 | encode));
3183 }
3184
3185 void Assembler::popf() {
3186 emit_int8((unsigned char)0x9D);
3187 }
3188
3189 #ifndef _LP64 // no 32bit push/pop on amd64
3190 void Assembler::popl(Address dst) {
3191 // NOTE: this will adjust stack by 8byte on 64bits
3192 InstructionMark im(this);
3193 prefix(dst);
3194 emit_int8((unsigned char)0x8F);
3195 emit_operand(rax, dst);
3196 }
3197 #endif
3198
3199 void Assembler::prefetch_prefix(Address src) {
3200 prefix(src);
3201 emit_int8(0x0F);
3202 }
3203
3204 void Assembler::prefetchnta(Address src) {
3205 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3206 InstructionMark im(this);
3207 prefetch_prefix(src);
3208 emit_int8(0x18);
3209 emit_operand(rax, src); // 0, src
3210 }
3211
3212 void Assembler::prefetchr(Address src) {
3213 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3214 InstructionMark im(this);
3215 prefetch_prefix(src);
3216 emit_int8(0x0D);
3217 emit_operand(rax, src); // 0, src
3218 }
3219
3220 void Assembler::prefetcht0(Address src) {
3221 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3222 InstructionMark im(this);
3223 prefetch_prefix(src);
3224 emit_int8(0x18);
3225 emit_operand(rcx, src); // 1, src
3226 }
3227
3228 void Assembler::prefetcht1(Address src) {
3229 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3230 InstructionMark im(this);
3231 prefetch_prefix(src);
3232 emit_int8(0x18);
3233 emit_operand(rdx, src); // 2, src
3234 }
3235
3236 void Assembler::prefetcht2(Address src) {
3237 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3238 InstructionMark im(this);
3239 prefetch_prefix(src);
3240 emit_int8(0x18);
3241 emit_operand(rbx, src); // 3, src
3242 }
3243
3244 void Assembler::prefetchw(Address src) {
3245 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3246 InstructionMark im(this);
3247 prefetch_prefix(src);
3248 emit_int8(0x0D);
3249 emit_operand(rcx, src); // 1, src
3250 }
3251
3252 void Assembler::prefix(Prefix p) {
3253 emit_int8(p);
3254 }
3255
3256 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3257 assert(VM_Version::supports_ssse3(), "");
3258 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3260 emit_int8(0x00);
3261 emit_int8((unsigned char)(0xC0 | encode));
3262 }
3263
3264 void Assembler::pshufb(XMMRegister dst, Address src) {
3265 assert(VM_Version::supports_ssse3(), "");
3266 InstructionMark im(this);
3267 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3268 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3269 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3270 emit_int8(0x00);
3271 emit_operand(dst, src);
3272 }
3273
3274 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3275 assert(isByte(mode), "invalid value");
3276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3277 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
3278 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3279 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3280 emit_int8(0x70);
3281 emit_int8((unsigned char)(0xC0 | encode));
3282 emit_int8(mode & 0xFF);
3283 }
3284
3285 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3286 assert(isByte(mode), "invalid value");
3287 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3288 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3289 InstructionMark im(this);
3290 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3291 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3292 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3293 emit_int8(0x70);
3294 emit_operand(dst, src);
3295 emit_int8(mode & 0xFF);
3296 }
3297
3298 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3299 assert(isByte(mode), "invalid value");
3300 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3301 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3302 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3303 emit_int8(0x70);
3304 emit_int8((unsigned char)(0xC0 | encode));
3305 emit_int8(mode & 0xFF);
3306 }
3307
3308 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3309 assert(isByte(mode), "invalid value");
3310 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3311 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3312 InstructionMark im(this);
3313 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3314 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3315 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3316 emit_int8(0x70);
3317 emit_operand(dst, src);
3318 emit_int8(mode & 0xFF);
3319 }
3320
3321 void Assembler::psrldq(XMMRegister dst, int shift) {
3322 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3323 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3324 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3325 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3326 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3327 emit_int8(0x73);
3328 emit_int8((unsigned char)(0xC0 | encode));
3329 emit_int8(shift);
3330 }
3331
3332 void Assembler::pslldq(XMMRegister dst, int shift) {
3333 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3336 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3337 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3338 emit_int8(0x73);
3339 emit_int8((unsigned char)(0xC0 | encode));
3340 emit_int8(shift);
3341 }
3342
3343 void Assembler::ptest(XMMRegister dst, Address src) {
3344 assert(VM_Version::supports_sse4_1(), "");
3345 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3346 InstructionMark im(this);
3347 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3348 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3349 emit_int8(0x17);
3350 emit_operand(dst, src);
3351 }
3352
3353 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3354 assert(VM_Version::supports_sse4_1(), "");
3355 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3356 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3357 emit_int8(0x17);
3358 emit_int8((unsigned char)(0xC0 | encode));
3359 }
3360
3361 void Assembler::vptest(XMMRegister dst, Address src) {
3362 assert(VM_Version::supports_avx(), "");
3363 InstructionMark im(this);
3364 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3365 assert(dst != xnoreg, "sanity");
3366 // swap src<->dst for encoding
3367 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3368 emit_int8(0x17);
3369 emit_operand(dst, src);
3370 }
3371
3372 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3373 assert(VM_Version::supports_avx(), "");
3374 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3375 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3376 emit_int8(0x17);
3377 emit_int8((unsigned char)(0xC0 | encode));
3378 }
3379
3380 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3381 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3382 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3383 InstructionMark im(this);
3384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3385 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3386 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3387 emit_int8(0x60);
3388 emit_operand(dst, src);
3389 }
3390
3391 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3392 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3394 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3395 emit_int8(0x60);
3396 emit_int8((unsigned char)(0xC0 | encode));
3397 }
3398
3399 void Assembler::punpckldq(XMMRegister dst, Address src) {
3400 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3401 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3402 InstructionMark im(this);
3403 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3404 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3405 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3406 emit_int8(0x62);
3407 emit_operand(dst, src);
3408 }
3409
3410 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3411 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3412 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3413 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3414 emit_int8(0x62);
3415 emit_int8((unsigned char)(0xC0 | encode));
3416 }
3417
3418 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3419 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3420 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3421 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3422 emit_int8(0x6C);
3423 emit_int8((unsigned char)(0xC0 | encode));
3424 }
3425
3426 void Assembler::push(int32_t imm32) {
3427 // in 64bits we push 64bits onto the stack but only
3428 // take a 32bit immediate
3429 emit_int8(0x68);
3430 emit_int32(imm32);
3431 }
3432
3433 void Assembler::push(Register src) {
3434 int encode = prefix_and_encode(src->encoding());
3435
3436 emit_int8(0x50 | encode);
3437 }
3438
3439 void Assembler::pushf() {
3440 emit_int8((unsigned char)0x9C);
3441 }
3442
3443 #ifndef _LP64 // no 32bit push/pop on amd64
3444 void Assembler::pushl(Address src) {
3445 // Note this will push 64bit on 64bit
3446 InstructionMark im(this);
3447 prefix(src);
3448 emit_int8((unsigned char)0xFF);
3449 emit_operand(rsi, src);
3450 }
3451 #endif
3452
3453 void Assembler::rcll(Register dst, int imm8) {
3454 assert(isShiftCount(imm8), "illegal shift count");
3455 int encode = prefix_and_encode(dst->encoding());
3456 if (imm8 == 1) {
3457 emit_int8((unsigned char)0xD1);
3458 emit_int8((unsigned char)(0xD0 | encode));
3459 } else {
3460 emit_int8((unsigned char)0xC1);
3461 emit_int8((unsigned char)0xD0 | encode);
3462 emit_int8(imm8);
3463 }
3464 }
3465
3466 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3467 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3468 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3469 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3470 emit_int8(0x53);
3471 emit_int8((unsigned char)(0xC0 | encode));
3472 }
3473
3474 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3475 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3477 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3478 emit_int8(0x53);
3479 emit_int8((unsigned char)(0xC0 | encode));
3480 }
3481
3482 void Assembler::rdtsc() {
3483 emit_int8((unsigned char)0x0F);
3484 emit_int8((unsigned char)0x31);
3485 }
3486
3487 // copies data from [esi] to [edi] using rcx pointer sized words
3488 // generic
3489 void Assembler::rep_mov() {
3490 emit_int8((unsigned char)0xF3);
3491 // MOVSQ
3492 LP64_ONLY(prefix(REX_W));
3493 emit_int8((unsigned char)0xA5);
3494 }
3495
3496 // sets rcx bytes with rax, value at [edi]
3497 void Assembler::rep_stosb() {
3498 emit_int8((unsigned char)0xF3); // REP
3499 LP64_ONLY(prefix(REX_W));
3500 emit_int8((unsigned char)0xAA); // STOSB
3501 }
3502
3503 // sets rcx pointer sized words with rax, value at [edi]
3504 // generic
3505 void Assembler::rep_stos() {
3506 emit_int8((unsigned char)0xF3); // REP
3507 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3508 emit_int8((unsigned char)0xAB);
3509 }
3510
3511 // scans rcx pointer sized words at [edi] for occurance of rax,
3512 // generic
3513 void Assembler::repne_scan() { // repne_scan
3514 emit_int8((unsigned char)0xF2);
3515 // SCASQ
3516 LP64_ONLY(prefix(REX_W));
3517 emit_int8((unsigned char)0xAF);
3518 }
3519
3520 #ifdef _LP64
3521 // scans rcx 4 byte words at [edi] for occurance of rax,
3522 // generic
3523 void Assembler::repne_scanl() { // repne_scan
3524 emit_int8((unsigned char)0xF2);
3525 // SCASL
3526 emit_int8((unsigned char)0xAF);
3527 }
3528 #endif
3529
3530 void Assembler::ret(int imm16) {
3531 if (imm16 == 0) {
3532 emit_int8((unsigned char)0xC3);
3533 } else {
3534 emit_int8((unsigned char)0xC2);
3535 emit_int16(imm16);
3536 }
3537 }
3538
3539 void Assembler::sahf() {
3540 #ifdef _LP64
3541 // Not supported in 64bit mode
3542 ShouldNotReachHere();
3543 #endif
3544 emit_int8((unsigned char)0x9E);
3545 }
3546
3547 void Assembler::sarl(Register dst, int imm8) {
3548 int encode = prefix_and_encode(dst->encoding());
3549 assert(isShiftCount(imm8), "illegal shift count");
3550 if (imm8 == 1) {
3551 emit_int8((unsigned char)0xD1);
3552 emit_int8((unsigned char)(0xF8 | encode));
3553 } else {
3554 emit_int8((unsigned char)0xC1);
3555 emit_int8((unsigned char)(0xF8 | encode));
3556 emit_int8(imm8);
3557 }
3558 }
3559
3560 void Assembler::sarl(Register dst) {
3561 int encode = prefix_and_encode(dst->encoding());
3562 emit_int8((unsigned char)0xD3);
3563 emit_int8((unsigned char)(0xF8 | encode));
3564 }
3565
3566 void Assembler::sbbl(Address dst, int32_t imm32) {
3567 InstructionMark im(this);
3568 prefix(dst);
3569 emit_arith_operand(0x81, rbx, dst, imm32);
3570 }
3571
3572 void Assembler::sbbl(Register dst, int32_t imm32) {
3573 prefix(dst);
3574 emit_arith(0x81, 0xD8, dst, imm32);
3575 }
3576
3577
3578 void Assembler::sbbl(Register dst, Address src) {
3579 InstructionMark im(this);
3580 prefix(src, dst);
3581 emit_int8(0x1B);
3582 emit_operand(dst, src);
3583 }
3584
3585 void Assembler::sbbl(Register dst, Register src) {
3586 (void) prefix_and_encode(dst->encoding(), src->encoding());
3587 emit_arith(0x1B, 0xC0, dst, src);
3588 }
3589
3590 void Assembler::setb(Condition cc, Register dst) {
3591 assert(0 <= cc && cc < 16, "illegal cc");
3592 int encode = prefix_and_encode(dst->encoding(), true);
3593 emit_int8(0x0F);
3594 emit_int8((unsigned char)0x90 | cc);
3595 emit_int8((unsigned char)(0xC0 | encode));
3596 }
3597
3598 void Assembler::shll(Register dst, int imm8) {
3599 assert(isShiftCount(imm8), "illegal shift count");
3600 int encode = prefix_and_encode(dst->encoding());
3601 if (imm8 == 1 ) {
3602 emit_int8((unsigned char)0xD1);
3603 emit_int8((unsigned char)(0xE0 | encode));
3604 } else {
3605 emit_int8((unsigned char)0xC1);
3606 emit_int8((unsigned char)(0xE0 | encode));
3607 emit_int8(imm8);
3608 }
3609 }
3610
3611 void Assembler::shll(Register dst) {
3612 int encode = prefix_and_encode(dst->encoding());
3613 emit_int8((unsigned char)0xD3);
3614 emit_int8((unsigned char)(0xE0 | encode));
3615 }
3616
3617 void Assembler::shrl(Register dst, int imm8) {
3618 assert(isShiftCount(imm8), "illegal shift count");
3619 int encode = prefix_and_encode(dst->encoding());
3620 emit_int8((unsigned char)0xC1);
3621 emit_int8((unsigned char)(0xE8 | encode));
3622 emit_int8(imm8);
3623 }
3624
3625 void Assembler::shrl(Register dst) {
3626 int encode = prefix_and_encode(dst->encoding());
3627 emit_int8((unsigned char)0xD3);
3628 emit_int8((unsigned char)(0xE8 | encode));
3629 }
3630
3631 // copies a single word from [esi] to [edi]
3632 void Assembler::smovl() {
3633 emit_int8((unsigned char)0xA5);
3634 }
3635
3636 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3637 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3638 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3639 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3640 emit_int8(0x51);
3641 emit_int8((unsigned char)(0xC0 | encode));
3642 }
3643
3644 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3645 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3646 InstructionMark im(this);
3647 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3648 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3649 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3650 emit_int8(0x51);
3651 emit_operand(dst, src);
3652 }
3653
3654 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3655 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3656 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3657 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3658 emit_int8(0x51);
3659 emit_int8((unsigned char)(0xC0 | encode));
3660 }
3661
3662 void Assembler::std() {
3663 emit_int8((unsigned char)0xFD);
3664 }
3665
3666 void Assembler::sqrtss(XMMRegister dst, Address src) {
3667 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3668 InstructionMark im(this);
3669 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3670 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3671 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3672 emit_int8(0x51);
3673 emit_operand(dst, src);
3674 }
3675
3676 void Assembler::stmxcsr( Address dst) {
3677 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3678 InstructionMark im(this);
3679 prefix(dst);
3680 emit_int8(0x0F);
3681 emit_int8((unsigned char)0xAE);
3682 emit_operand(as_Register(3), dst);
3683 }
3684
3685 void Assembler::subl(Address dst, int32_t imm32) {
3686 InstructionMark im(this);
3687 prefix(dst);
3688 emit_arith_operand(0x81, rbp, dst, imm32);
3689 }
3690
3691 void Assembler::subl(Address dst, Register src) {
3692 InstructionMark im(this);
3693 prefix(dst, src);
3694 emit_int8(0x29);
3695 emit_operand(src, dst);
3696 }
3697
3698 void Assembler::subl(Register dst, int32_t imm32) {
3699 prefix(dst);
3700 emit_arith(0x81, 0xE8, dst, imm32);
3701 }
3702
3703 // Force generation of a 4 byte immediate value even if it fits into 8bit
3704 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3705 prefix(dst);
3706 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3707 }
3708
3709 void Assembler::subl(Register dst, Address src) {
3710 InstructionMark im(this);
3711 prefix(src, dst);
3712 emit_int8(0x2B);
3713 emit_operand(dst, src);
3714 }
3715
3716 void Assembler::subl(Register dst, Register src) {
3717 (void) prefix_and_encode(dst->encoding(), src->encoding());
3718 emit_arith(0x2B, 0xC0, dst, src);
3719 }
3720
3721 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3723 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3724 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3725 emit_int8(0x5C);
3726 emit_int8((unsigned char)(0xC0 | encode));
3727 }
3728
3729 void Assembler::subsd(XMMRegister dst, Address src) {
3730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3731 InstructionMark im(this);
3732 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3733 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3734 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3735 emit_int8(0x5C);
3736 emit_operand(dst, src);
3737 }
3738
3739 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3740 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3741 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3742 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3743 emit_int8(0x5C);
3744 emit_int8((unsigned char)(0xC0 | encode));
3745 }
3746
3747 void Assembler::subss(XMMRegister dst, Address src) {
3748 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3749 InstructionMark im(this);
3750 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3751 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3752 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3753 emit_int8(0x5C);
3754 emit_operand(dst, src);
3755 }
3756
3757 void Assembler::testb(Register dst, int imm8) {
3758 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3759 (void) prefix_and_encode(dst->encoding(), true);
3760 emit_arith_b(0xF6, 0xC0, dst, imm8);
3761 }
3762
3763 void Assembler::testb(Address dst, int imm8) {
3764 InstructionMark im(this);
3765 prefix(dst);
3766 emit_int8((unsigned char)0xF6);
3767 emit_operand(rax, dst, 1);
3768 emit_int8(imm8);
3769
3770 }
3771
3772 void Assembler::testl(Register dst, int32_t imm32) {
3773 // not using emit_arith because test
3774 // doesn't support sign-extension of
3775 // 8bit operands
3776 int encode = dst->encoding();
3777 if (encode == 0) {
3778 emit_int8((unsigned char)0xA9);
3779 } else {
3780 encode = prefix_and_encode(encode);
3781 emit_int8((unsigned char)0xF7);
3782 emit_int8((unsigned char)(0xC0 | encode));
3783 }
3784 emit_int32(imm32);
3785 }
3786
3787 void Assembler::testl(Register dst, Register src) {
3788 (void) prefix_and_encode(dst->encoding(), src->encoding());
3789 emit_arith(0x85, 0xC0, dst, src);
3790 }
3791
3792 void Assembler::testl(Register dst, Address src) {
3793 InstructionMark im(this);
3794 prefix(src, dst);
3795 emit_int8((unsigned char)0x85);
3796 emit_operand(dst, src);
3797 }
3798
3799 void Assembler::tzcntl(Register dst, Register src) {
3800 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3801 emit_int8((unsigned char)0xF3);
3802 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3803 emit_int8(0x0F);
3804 emit_int8((unsigned char)0xBC);
3805 emit_int8((unsigned char)0xC0 | encode);
3806 }
3807
3808 void Assembler::tzcntq(Register dst, Register src) {
3809 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3810 emit_int8((unsigned char)0xF3);
3811 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
3812 emit_int8(0x0F);
3813 emit_int8((unsigned char)0xBC);
3814 emit_int8((unsigned char)(0xC0 | encode));
3815 }
3816
3817 void Assembler::ucomisd(XMMRegister dst, Address src) {
3818 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3819 InstructionMark im(this);
3820 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3821 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3822 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3823 emit_int8(0x2E);
3824 emit_operand(dst, src);
3825 }
3826
3827 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
3828 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3829 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3830 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3831 emit_int8(0x2E);
3832 emit_int8((unsigned char)(0xC0 | encode));
3833 }
3834
3835 void Assembler::ucomiss(XMMRegister dst, Address src) {
3836 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3837 InstructionMark im(this);
3838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3840 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3841 emit_int8(0x2E);
3842 emit_operand(dst, src);
3843 }
3844
3845 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
3846 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3847 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3848 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3849 emit_int8(0x2E);
3850 emit_int8((unsigned char)(0xC0 | encode));
3851 }
3852
3853 void Assembler::xabort(int8_t imm8) {
3854 emit_int8((unsigned char)0xC6);
3855 emit_int8((unsigned char)0xF8);
3856 emit_int8((unsigned char)(imm8 & 0xFF));
3857 }
3858
3859 void Assembler::xaddl(Address dst, Register src) {
3860 InstructionMark im(this);
3861 prefix(dst, src);
3862 emit_int8(0x0F);
3863 emit_int8((unsigned char)0xC1);
3864 emit_operand(src, dst);
3865 }
3866
3867 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
3868 InstructionMark im(this);
3869 relocate(rtype);
3870 if (abort.is_bound()) {
3871 address entry = target(abort);
3872 assert(entry != NULL, "abort entry NULL");
3873 intptr_t offset = entry - pc();
3874 emit_int8((unsigned char)0xC7);
3875 emit_int8((unsigned char)0xF8);
3876 emit_int32(offset - 6); // 2 opcode + 4 address
3877 } else {
3878 abort.add_patch_at(code(), locator());
3879 emit_int8((unsigned char)0xC7);
3880 emit_int8((unsigned char)0xF8);
3881 emit_int32(0);
3882 }
3883 }
3884
3885 void Assembler::xchgl(Register dst, Address src) { // xchg
3886 InstructionMark im(this);
3887 prefix(src, dst);
3888 emit_int8((unsigned char)0x87);
3889 emit_operand(dst, src);
3890 }
3891
3892 void Assembler::xchgl(Register dst, Register src) {
3893 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3894 emit_int8((unsigned char)0x87);
3895 emit_int8((unsigned char)(0xC0 | encode));
3896 }
3897
3898 void Assembler::xend() {
3899 emit_int8((unsigned char)0x0F);
3900 emit_int8((unsigned char)0x01);
3901 emit_int8((unsigned char)0xD5);
3902 }
3903
3904 void Assembler::xgetbv() {
3905 emit_int8(0x0F);
3906 emit_int8(0x01);
3907 emit_int8((unsigned char)0xD0);
3908 }
3909
3910 void Assembler::xorl(Register dst, int32_t imm32) {
3911 prefix(dst);
3912 emit_arith(0x81, 0xF0, dst, imm32);
3913 }
3914
3915 void Assembler::xorl(Register dst, Address src) {
3916 InstructionMark im(this);
3917 prefix(src, dst);
3918 emit_int8(0x33);
3919 emit_operand(dst, src);
3920 }
3921
3922 void Assembler::xorl(Register dst, Register src) {
3923 (void) prefix_and_encode(dst->encoding(), src->encoding());
3924 emit_arith(0x33, 0xC0, dst, src);
3925 }
3926
3927
3928 // AVX 3-operands scalar float-point arithmetic instructions
3929
3930 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
3931 assert(VM_Version::supports_avx(), "");
3932 InstructionMark im(this);
3933 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3934 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3935 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3936 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3937 emit_int8(0x58);
3938 emit_operand(dst, src);
3939 }
3940
3941 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3942 assert(VM_Version::supports_avx(), "");
3943 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3944 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3945 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3946 emit_int8(0x58);
3947 emit_int8((unsigned char)(0xC0 | encode));
3948 }
3949
3950 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
3951 assert(VM_Version::supports_avx(), "");
3952 InstructionMark im(this);
3953 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3954 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3955 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3956 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3957 emit_int8(0x58);
3958 emit_operand(dst, src);
3959 }
3960
3961 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3962 assert(VM_Version::supports_avx(), "");
3963 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3964 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3965 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3966 emit_int8(0x58);
3967 emit_int8((unsigned char)(0xC0 | encode));
3968 }
3969
3970 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
3971 assert(VM_Version::supports_avx(), "");
3972 InstructionMark im(this);
3973 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3974 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3975 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3976 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3977 emit_int8(0x5E);
3978 emit_operand(dst, src);
3979 }
3980
3981 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3982 assert(VM_Version::supports_avx(), "");
3983 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3984 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3985 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3986 emit_int8(0x5E);
3987 emit_int8((unsigned char)(0xC0 | encode));
3988 }
3989
3990 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
3991 assert(VM_Version::supports_avx(), "");
3992 InstructionMark im(this);
3993 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3994 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3995 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3996 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3997 emit_int8(0x5E);
3998 emit_operand(dst, src);
3999 }
4000
4001 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4002 assert(VM_Version::supports_avx(), "");
4003 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4004 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4005 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4006 emit_int8(0x5E);
4007 emit_int8((unsigned char)(0xC0 | encode));
4008 }
4009
4010 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4011 assert(VM_Version::supports_avx(), "");
4012 InstructionMark im(this);
4013 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4014 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4015 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4016 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4017 emit_int8(0x59);
4018 emit_operand(dst, src);
4019 }
4020
4021 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4022 assert(VM_Version::supports_avx(), "");
4023 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4024 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4025 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4026 emit_int8(0x59);
4027 emit_int8((unsigned char)(0xC0 | encode));
4028 }
4029
4030 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4031 assert(VM_Version::supports_avx(), "");
4032 InstructionMark im(this);
4033 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4034 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4035 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4036 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4037 emit_int8(0x59);
4038 emit_operand(dst, src);
4039 }
4040
4041 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4042 assert(VM_Version::supports_avx(), "");
4043 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4044 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4045 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4046 emit_int8(0x59);
4047 emit_int8((unsigned char)(0xC0 | encode));
4048 }
4049
4050 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4051 assert(VM_Version::supports_avx(), "");
4052 InstructionMark im(this);
4053 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4054 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4055 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4056 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4057 emit_int8(0x5C);
4058 emit_operand(dst, src);
4059 }
4060
4061 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4062 assert(VM_Version::supports_avx(), "");
4063 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4064 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4065 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4066 emit_int8(0x5C);
4067 emit_int8((unsigned char)(0xC0 | encode));
4068 }
4069
4070 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4071 assert(VM_Version::supports_avx(), "");
4072 InstructionMark im(this);
4073 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4074 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4075 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4076 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4077 emit_int8(0x5C);
4078 emit_operand(dst, src);
4079 }
4080
4081 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4082 assert(VM_Version::supports_avx(), "");
4083 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4084 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4085 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4086 emit_int8(0x5C);
4087 emit_int8((unsigned char)(0xC0 | encode));
4088 }
4089
4090 //====================VECTOR ARITHMETIC=====================================
4091
4092 // Float-point vector arithmetic
4093
4094 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4095 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4096 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4097 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4098 emit_int8(0x58);
4099 emit_int8((unsigned char)(0xC0 | encode));
4100 }
4101
4102 void Assembler::addpd(XMMRegister dst, Address src) {
4103 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4104 InstructionMark im(this);
4105 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4106 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4107 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4108 emit_int8(0x58);
4109 emit_operand(dst, src);
4110 }
4111
4112 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4114 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4115 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4116 emit_int8(0x58);
4117 emit_int8((unsigned char)(0xC0 | encode));
4118 }
4119
4120 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4121 assert(VM_Version::supports_avx(), "");
4122 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4123 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4124 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4125 emit_int8(0x58);
4126 emit_int8((unsigned char)(0xC0 | encode));
4127 }
4128
4129 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4130 assert(VM_Version::supports_avx(), "");
4131 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4132 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4133 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4134 emit_int8(0x58);
4135 emit_int8((unsigned char)(0xC0 | encode));
4136 }
4137
4138 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4139 assert(VM_Version::supports_avx(), "");
4140 InstructionMark im(this);
4141 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4142 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4143 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4144 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4145 emit_int8(0x58);
4146 emit_operand(dst, src);
4147 }
4148
4149 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4150 assert(VM_Version::supports_avx(), "");
4151 InstructionMark im(this);
4152 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4153 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4154 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4155 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4156 emit_int8(0x58);
4157 emit_operand(dst, src);
4158 }
4159
4160 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4162 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4163 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4164 emit_int8(0x5C);
4165 emit_int8((unsigned char)(0xC0 | encode));
4166 }
4167
4168 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4169 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4170 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4171 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4172 emit_int8(0x5C);
4173 emit_int8((unsigned char)(0xC0 | encode));
4174 }
4175
4176 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4177 assert(VM_Version::supports_avx(), "");
4178 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4179 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4180 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4181 emit_int8(0x5C);
4182 emit_int8((unsigned char)(0xC0 | encode));
4183 }
4184
4185 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4186 assert(VM_Version::supports_avx(), "");
4187 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4188 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4189 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4190 emit_int8(0x5C);
4191 emit_int8((unsigned char)(0xC0 | encode));
4192 }
4193
4194 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4195 assert(VM_Version::supports_avx(), "");
4196 InstructionMark im(this);
4197 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4198 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4199 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4200 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4201 emit_int8(0x5C);
4202 emit_operand(dst, src);
4203 }
4204
4205 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4206 assert(VM_Version::supports_avx(), "");
4207 InstructionMark im(this);
4208 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4209 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4210 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4211 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4212 emit_int8(0x5C);
4213 emit_operand(dst, src);
4214 }
4215
4216 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4217 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4218 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4219 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4220 emit_int8(0x59);
4221 emit_int8((unsigned char)(0xC0 | encode));
4222 }
4223
4224 void Assembler::mulpd(XMMRegister dst, Address src) {
4225 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4226 InstructionMark im(this);
4227 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4228 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4229 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4230 emit_int8(0x59);
4231 emit_operand(dst, src);
4232 }
4233
4234 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4235 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4236 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4237 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4238 emit_int8(0x59);
4239 emit_int8((unsigned char)(0xC0 | encode));
4240 }
4241
4242 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4243 assert(VM_Version::supports_avx(), "");
4244 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4245 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4246 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4247 emit_int8(0x59);
4248 emit_int8((unsigned char)(0xC0 | encode));
4249 }
4250
4251 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4252 assert(VM_Version::supports_avx(), "");
4253 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4254 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4255 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4256 emit_int8(0x59);
4257 emit_int8((unsigned char)(0xC0 | encode));
4258 }
4259
4260 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4261 assert(VM_Version::supports_avx(), "");
4262 InstructionMark im(this);
4263 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4264 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4265 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4266 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4267 emit_int8(0x59);
4268 emit_operand(dst, src);
4269 }
4270
4271 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4272 assert(VM_Version::supports_avx(), "");
4273 InstructionMark im(this);
4274 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4275 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4276 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4277 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4278 emit_int8(0x59);
4279 emit_operand(dst, src);
4280 }
4281
4282 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4284 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4285 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4286 emit_int8(0x5E);
4287 emit_int8((unsigned char)(0xC0 | encode));
4288 }
4289
4290 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4292 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4294 emit_int8(0x5E);
4295 emit_int8((unsigned char)(0xC0 | encode));
4296 }
4297
4298 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4299 assert(VM_Version::supports_avx(), "");
4300 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4301 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4302 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4303 emit_int8(0x5E);
4304 emit_int8((unsigned char)(0xC0 | encode));
4305 }
4306
4307 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4308 assert(VM_Version::supports_avx(), "");
4309 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4310 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4311 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4312 emit_int8(0x5E);
4313 emit_int8((unsigned char)(0xC0 | encode));
4314 }
4315
4316 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4317 assert(VM_Version::supports_avx(), "");
4318 InstructionMark im(this);
4319 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4320 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4321 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4322 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4323 emit_int8(0x5E);
4324 emit_operand(dst, src);
4325 }
4326
4327 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4328 assert(VM_Version::supports_avx(), "");
4329 InstructionMark im(this);
4330 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4331 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4332 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4333 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4334 emit_int8(0x5E);
4335 emit_operand(dst, src);
4336 }
4337
4338 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4339 assert(VM_Version::supports_avx(), "");
4340 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4341 int nds_enc = 0;
4342 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4343 emit_int8(0x51);
4344 emit_int8((unsigned char)(0xC0 | encode));
4345 }
4346
4347 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4348 assert(VM_Version::supports_avx(), "");
4349 InstructionMark im(this);
4350 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4351 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4352 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4353 emit_int8(0x51);
4354 emit_operand(dst, src);
4355 }
4356
4357 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4358 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4359 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4360 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4361 emit_int8(0x54);
4362 emit_int8((unsigned char)(0xC0 | encode));
4363 }
4364
4365 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4366 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4368 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4369 emit_int8(0x54);
4370 emit_int8((unsigned char)(0xC0 | encode));
4371 }
4372
4373 void Assembler::andps(XMMRegister dst, Address src) {
4374 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4375 InstructionMark im(this);
4376 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4377 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4378 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4379 emit_int8(0x54);
4380 emit_operand(dst, src);
4381 }
4382
4383 void Assembler::andpd(XMMRegister dst, Address src) {
4384 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4385 InstructionMark im(this);
4386 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4387 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4388 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4389 emit_int8(0x54);
4390 emit_operand(dst, src);
4391 }
4392
4393 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4394 assert(VM_Version::supports_avx(), "");
4395 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4396 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4397 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4398 emit_int8(0x54);
4399 emit_int8((unsigned char)(0xC0 | encode));
4400 }
4401
4402 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4403 assert(VM_Version::supports_avx(), "");
4404 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4405 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4406 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4407 emit_int8(0x54);
4408 emit_int8((unsigned char)(0xC0 | encode));
4409 }
4410
4411 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4412 assert(VM_Version::supports_avx(), "");
4413 InstructionMark im(this);
4414 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4415 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4416 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4417 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4418 emit_int8(0x54);
4419 emit_operand(dst, src);
4420 }
4421
4422 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4423 assert(VM_Version::supports_avx(), "");
4424 InstructionMark im(this);
4425 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4426 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4427 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4428 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4429 emit_int8(0x54);
4430 emit_operand(dst, src);
4431 }
4432
4433 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4434 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4435 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4436 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4437 emit_int8(0x15);
4438 emit_int8((unsigned char)(0xC0 | encode));
4439 }
4440
4441 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4442 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4443 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4444 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4445 emit_int8(0x14);
4446 emit_int8((unsigned char)(0xC0 | encode));
4447 }
4448
4449 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4450 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4451 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4452 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4453 emit_int8(0x57);
4454 emit_int8((unsigned char)(0xC0 | encode));
4455 }
4456
4457 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4458 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4459 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4460 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4461 emit_int8(0x57);
4462 emit_int8((unsigned char)(0xC0 | encode));
4463 }
4464
4465 void Assembler::xorpd(XMMRegister dst, Address src) {
4466 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4467 InstructionMark im(this);
4468 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4469 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4470 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4471 emit_int8(0x57);
4472 emit_operand(dst, src);
4473 }
4474
4475 void Assembler::xorps(XMMRegister dst, Address src) {
4476 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4477 InstructionMark im(this);
4478 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4479 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4480 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4481 emit_int8(0x57);
4482 emit_operand(dst, src);
4483 }
4484
4485 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4486 assert(VM_Version::supports_avx(), "");
4487 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4488 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4489 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4490 emit_int8(0x57);
4491 emit_int8((unsigned char)(0xC0 | encode));
4492 }
4493
4494 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4495 assert(VM_Version::supports_avx(), "");
4496 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4497 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4498 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4499 emit_int8(0x57);
4500 emit_int8((unsigned char)(0xC0 | encode));
4501 }
4502
4503 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4504 assert(VM_Version::supports_avx(), "");
4505 InstructionMark im(this);
4506 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4507 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4508 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4509 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4510 emit_int8(0x57);
4511 emit_operand(dst, src);
4512 }
4513
4514 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4515 assert(VM_Version::supports_avx(), "");
4516 InstructionMark im(this);
4517 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4518 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4519 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4520 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4521 emit_int8(0x57);
4522 emit_operand(dst, src);
4523 }
4524
4525 // Integer vector arithmetic
4526 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4527 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4528 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4529 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4530 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4531 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4532 emit_int8(0x01);
4533 emit_int8((unsigned char)(0xC0 | encode));
4534 }
4535
4536 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4537 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4538 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4539 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4540 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4541 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4542 emit_int8(0x02);
4543 emit_int8((unsigned char)(0xC0 | encode));
4544 }
4545
4546 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4547 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4548 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4549 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4550 emit_int8((unsigned char)0xFC);
4551 emit_int8((unsigned char)(0xC0 | encode));
4552 }
4553
4554 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4555 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4556 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4557 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4558 emit_int8((unsigned char)0xFD);
4559 emit_int8((unsigned char)(0xC0 | encode));
4560 }
4561
4562 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4563 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4564 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4565 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4566 emit_int8((unsigned char)0xFE);
4567 emit_int8((unsigned char)(0xC0 | encode));
4568 }
4569
4570 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4571 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4572 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4573 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4574 emit_int8((unsigned char)0xD4);
4575 emit_int8((unsigned char)(0xC0 | encode));
4576 }
4577
4578 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4579 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4580 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4581 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4582 emit_int8(0x01);
4583 emit_int8((unsigned char)(0xC0 | encode));
4584 }
4585
4586 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4587 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4588 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4589 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4590 emit_int8(0x02);
4591 emit_int8((unsigned char)(0xC0 | encode));
4592 }
4593
4594 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4595 assert(UseAVX > 0, "requires some form of AVX");
4596 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4597 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4598 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4599 emit_int8((unsigned char)0xFC);
4600 emit_int8((unsigned char)(0xC0 | encode));
4601 }
4602
4603 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4604 assert(UseAVX > 0, "requires some form of AVX");
4605 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4606 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4607 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4608 emit_int8((unsigned char)0xFD);
4609 emit_int8((unsigned char)(0xC0 | encode));
4610 }
4611
4612 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4613 assert(UseAVX > 0, "requires some form of AVX");
4614 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4615 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4616 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4617 emit_int8((unsigned char)0xFE);
4618 emit_int8((unsigned char)(0xC0 | encode));
4619 }
4620
4621 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4622 assert(UseAVX > 0, "requires some form of AVX");
4623 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4624 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4625 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4626 emit_int8((unsigned char)0xD4);
4627 emit_int8((unsigned char)(0xC0 | encode));
4628 }
4629
4630 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4631 assert(UseAVX > 0, "requires some form of AVX");
4632 InstructionMark im(this);
4633 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4634 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4635 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4636 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4637 emit_int8((unsigned char)0xFC);
4638 emit_operand(dst, src);
4639 }
4640
4641 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4642 assert(UseAVX > 0, "requires some form of AVX");
4643 InstructionMark im(this);
4644 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4645 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4646 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4647 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4648 emit_int8((unsigned char)0xFD);
4649 emit_operand(dst, src);
4650 }
4651
4652 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4653 assert(UseAVX > 0, "requires some form of AVX");
4654 InstructionMark im(this);
4655 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4656 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4657 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4658 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4659 emit_int8((unsigned char)0xFE);
4660 emit_operand(dst, src);
4661 }
4662
4663 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4664 assert(UseAVX > 0, "requires some form of AVX");
4665 InstructionMark im(this);
4666 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4667 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4668 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4669 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4670 emit_int8((unsigned char)0xD4);
4671 emit_operand(dst, src);
4672 }
4673
4674 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4675 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4676 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4677 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4678 emit_int8((unsigned char)0xF8);
4679 emit_int8((unsigned char)(0xC0 | encode));
4680 }
4681
4682 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4683 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4684 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4685 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4686 emit_int8((unsigned char)0xF9);
4687 emit_int8((unsigned char)(0xC0 | encode));
4688 }
4689
4690 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4691 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4692 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4693 emit_int8((unsigned char)0xFA);
4694 emit_int8((unsigned char)(0xC0 | encode));
4695 }
4696
4697 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4698 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4699 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4700 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4701 emit_int8((unsigned char)0xFB);
4702 emit_int8((unsigned char)(0xC0 | encode));
4703 }
4704
4705 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4706 assert(UseAVX > 0, "requires some form of AVX");
4707 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4708 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4709 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4710 emit_int8((unsigned char)0xF8);
4711 emit_int8((unsigned char)(0xC0 | encode));
4712 }
4713
4714 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4715 assert(UseAVX > 0, "requires some form of AVX");
4716 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4717 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4718 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4719 emit_int8((unsigned char)0xF9);
4720 emit_int8((unsigned char)(0xC0 | encode));
4721 }
4722
4723 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4724 assert(UseAVX > 0, "requires some form of AVX");
4725 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4726 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4727 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4728 emit_int8((unsigned char)0xFA);
4729 emit_int8((unsigned char)(0xC0 | encode));
4730 }
4731
4732 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4733 assert(UseAVX > 0, "requires some form of AVX");
4734 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4735 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4736 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4737 emit_int8((unsigned char)0xFB);
4738 emit_int8((unsigned char)(0xC0 | encode));
4739 }
4740
4741 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4742 assert(UseAVX > 0, "requires some form of AVX");
4743 InstructionMark im(this);
4744 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4745 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4746 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4747 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4748 emit_int8((unsigned char)0xF8);
4749 emit_operand(dst, src);
4750 }
4751
4752 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4753 assert(UseAVX > 0, "requires some form of AVX");
4754 InstructionMark im(this);
4755 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4756 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4757 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4758 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4759 emit_int8((unsigned char)0xF9);
4760 emit_operand(dst, src);
4761 }
4762
4763 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4764 assert(UseAVX > 0, "requires some form of AVX");
4765 InstructionMark im(this);
4766 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4767 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4768 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4769 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4770 emit_int8((unsigned char)0xFA);
4771 emit_operand(dst, src);
4772 }
4773
4774 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4775 assert(UseAVX > 0, "requires some form of AVX");
4776 InstructionMark im(this);
4777 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4778 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4779 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4780 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4781 emit_int8((unsigned char)0xFB);
4782 emit_operand(dst, src);
4783 }
4784
4785 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4786 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4787 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4788 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4789 emit_int8((unsigned char)0xD5);
4790 emit_int8((unsigned char)(0xC0 | encode));
4791 }
4792
4793 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4794 assert(VM_Version::supports_sse4_1(), "");
4795 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4796 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4797 emit_int8(0x40);
4798 emit_int8((unsigned char)(0xC0 | encode));
4799 }
4800
4801 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4802 assert(UseAVX > 0, "requires some form of AVX");
4803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4804 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4805 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4806 emit_int8((unsigned char)0xD5);
4807 emit_int8((unsigned char)(0xC0 | encode));
4808 }
4809
4810 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4811 assert(UseAVX > 0, "requires some form of AVX");
4812 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4813 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4814 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4815 emit_int8(0x40);
4816 emit_int8((unsigned char)(0xC0 | encode));
4817 }
4818
4819 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4820 assert(UseAVX > 2, "requires some form of AVX");
4821 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4822 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4823 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4824 emit_int8(0x40);
4825 emit_int8((unsigned char)(0xC0 | encode));
4826 }
4827
4828 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4829 assert(UseAVX > 0, "requires some form of AVX");
4830 InstructionMark im(this);
4831 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4832 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4833 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4834 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4835 emit_int8((unsigned char)0xD5);
4836 emit_operand(dst, src);
4837 }
4838
4839 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4840 assert(UseAVX > 0, "requires some form of AVX");
4841 InstructionMark im(this);
4842 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4843 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4844 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4845 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4846 emit_int8(0x40);
4847 emit_operand(dst, src);
4848 }
4849
4850 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4851 assert(UseAVX > 0, "requires some form of AVX");
4852 InstructionMark im(this);
4853 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4854 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4855 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4856 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4857 emit_int8(0x40);
4858 emit_operand(dst, src);
4859 }
4860
4861 // Shift packed integers left by specified number of bits.
4862 void Assembler::psllw(XMMRegister dst, int shift) {
4863 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4864 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4865 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4866 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4867 emit_int8(0x71);
4868 emit_int8((unsigned char)(0xC0 | encode));
4869 emit_int8(shift & 0xFF);
4870 }
4871
4872 void Assembler::pslld(XMMRegister dst, int shift) {
4873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4874 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4875 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4876 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4877 emit_int8(0x72);
4878 emit_int8((unsigned char)(0xC0 | encode));
4879 emit_int8(shift & 0xFF);
4880 }
4881
4882 void Assembler::psllq(XMMRegister dst, int shift) {
4883 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4884 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4885 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4886 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4887 emit_int8(0x73);
4888 emit_int8((unsigned char)(0xC0 | encode));
4889 emit_int8(shift & 0xFF);
4890 }
4891
4892 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
4893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4894 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4895 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4896 emit_int8((unsigned char)0xF1);
4897 emit_int8((unsigned char)(0xC0 | encode));
4898 }
4899
4900 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
4901 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4903 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4904 emit_int8((unsigned char)0xF2);
4905 emit_int8((unsigned char)(0xC0 | encode));
4906 }
4907
4908 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
4909 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4910 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4911 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4912 emit_int8((unsigned char)0xF3);
4913 emit_int8((unsigned char)(0xC0 | encode));
4914 }
4915
4916 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4917 assert(UseAVX > 0, "requires some form of AVX");
4918 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4919 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
4920 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4921 emit_int8(0x71);
4922 emit_int8((unsigned char)(0xC0 | encode));
4923 emit_int8(shift & 0xFF);
4924 }
4925
4926 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4927 assert(UseAVX > 0, "requires some form of AVX");
4928 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4929 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4930 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
4931 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4932 emit_int8(0x72);
4933 emit_int8((unsigned char)(0xC0 | encode));
4934 emit_int8(shift & 0xFF);
4935 }
4936
4937 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
4938 assert(UseAVX > 0, "requires some form of AVX");
4939 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4940 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
4941 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4942 emit_int8(0x73);
4943 emit_int8((unsigned char)(0xC0 | encode));
4944 emit_int8(shift & 0xFF);
4945 }
4946
4947 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4948 assert(UseAVX > 0, "requires some form of AVX");
4949 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4950 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4951 emit_int8((unsigned char)0xF1);
4952 emit_int8((unsigned char)(0xC0 | encode));
4953 }
4954
4955 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4956 assert(UseAVX > 0, "requires some form of AVX");
4957 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4958 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4959 emit_int8((unsigned char)0xF2);
4960 emit_int8((unsigned char)(0xC0 | encode));
4961 }
4962
4963 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
4964 assert(UseAVX > 0, "requires some form of AVX");
4965 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4966 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4967 emit_int8((unsigned char)0xF3);
4968 emit_int8((unsigned char)(0xC0 | encode));
4969 }
4970
4971 // Shift packed integers logically right by specified number of bits.
4972 void Assembler::psrlw(XMMRegister dst, int shift) {
4973 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4974 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4975 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
4976 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4977 emit_int8(0x71);
4978 emit_int8((unsigned char)(0xC0 | encode));
4979 emit_int8(shift & 0xFF);
4980 }
4981
4982 void Assembler::psrld(XMMRegister dst, int shift) {
4983 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4984 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4985 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
4986 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4987 emit_int8(0x72);
4988 emit_int8((unsigned char)(0xC0 | encode));
4989 emit_int8(shift & 0xFF);
4990 }
4991
4992 void Assembler::psrlq(XMMRegister dst, int shift) {
4993 // Do not confuse it with psrldq SSE2 instruction which
4994 // shifts 128 bit value in xmm register by number of bytes.
4995 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4996 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4997 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
4998 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4999 emit_int8(0x73);
5000 emit_int8((unsigned char)(0xC0 | encode));
5001 emit_int8(shift & 0xFF);
5002 }
5003
5004 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5005 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5006 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5007 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5008 emit_int8((unsigned char)0xD1);
5009 emit_int8((unsigned char)(0xC0 | encode));
5010 }
5011
5012 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5013 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5014 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5015 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5016 emit_int8((unsigned char)0xD2);
5017 emit_int8((unsigned char)(0xC0 | encode));
5018 }
5019
5020 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5021 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5022 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5023 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5024 emit_int8((unsigned char)0xD3);
5025 emit_int8((unsigned char)(0xC0 | encode));
5026 }
5027
5028 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5029 assert(UseAVX > 0, "requires some form of AVX");
5030 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5031 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5032 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5033 emit_int8(0x71);
5034 emit_int8((unsigned char)(0xC0 | encode));
5035 emit_int8(shift & 0xFF);
5036 }
5037
5038 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5039 assert(UseAVX > 0, "requires some form of AVX");
5040 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5041 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5042 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5043 emit_int8(0x72);
5044 emit_int8((unsigned char)(0xC0 | encode));
5045 emit_int8(shift & 0xFF);
5046 }
5047
5048 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5049 assert(UseAVX > 0, "requires some form of AVX");
5050 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5051 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5052 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5053 emit_int8(0x73);
5054 emit_int8((unsigned char)(0xC0 | encode));
5055 emit_int8(shift & 0xFF);
5056 }
5057
5058 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5059 assert(UseAVX > 0, "requires some form of AVX");
5060 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5061 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5062 emit_int8((unsigned char)0xD1);
5063 emit_int8((unsigned char)(0xC0 | encode));
5064 }
5065
5066 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5067 assert(UseAVX > 0, "requires some form of AVX");
5068 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5069 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5070 emit_int8((unsigned char)0xD2);
5071 emit_int8((unsigned char)(0xC0 | encode));
5072 }
5073
5074 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5075 assert(UseAVX > 0, "requires some form of AVX");
5076 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5077 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5078 emit_int8((unsigned char)0xD3);
5079 emit_int8((unsigned char)(0xC0 | encode));
5080 }
5081
5082 // Shift packed integers arithmetically right by specified number of bits.
5083 void Assembler::psraw(XMMRegister dst, int shift) {
5084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5085 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5086 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5087 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5088 emit_int8(0x71);
5089 emit_int8((unsigned char)(0xC0 | encode));
5090 emit_int8(shift & 0xFF);
5091 }
5092
5093 void Assembler::psrad(XMMRegister dst, int shift) {
5094 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5095 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5096 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5097 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5098 emit_int8(0x72);
5099 emit_int8((unsigned char)(0xC0 | encode));
5100 emit_int8(shift & 0xFF);
5101 }
5102
5103 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5104 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5105 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5106 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5107 emit_int8((unsigned char)0xE1);
5108 emit_int8((unsigned char)(0xC0 | encode));
5109 }
5110
5111 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5112 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5113 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5114 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5115 emit_int8((unsigned char)0xE2);
5116 emit_int8((unsigned char)(0xC0 | encode));
5117 }
5118
5119 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5120 assert(UseAVX > 0, "requires some form of AVX");
5121 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5122 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5123 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5124 emit_int8(0x71);
5125 emit_int8((unsigned char)(0xC0 | encode));
5126 emit_int8(shift & 0xFF);
5127 }
5128
5129 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5130 assert(UseAVX > 0, "requires some form of AVX");
5131 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5132 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5133 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5134 emit_int8(0x72);
5135 emit_int8((unsigned char)(0xC0 | encode));
5136 emit_int8(shift & 0xFF);
5137 }
5138
5139 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5140 assert(UseAVX > 0, "requires some form of AVX");
5141 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5142 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5143 emit_int8((unsigned char)0xE1);
5144 emit_int8((unsigned char)(0xC0 | encode));
5145 }
5146
5147 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5148 assert(UseAVX > 0, "requires some form of AVX");
5149 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5150 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5151 emit_int8((unsigned char)0xE2);
5152 emit_int8((unsigned char)(0xC0 | encode));
5153 }
5154
5155
5156 // logical operations packed integers
5157 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5158 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5159 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5160 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5161 emit_int8((unsigned char)0xDB);
5162 emit_int8((unsigned char)(0xC0 | encode));
5163 }
5164
5165 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5166 assert(UseAVX > 0, "requires some form of AVX");
5167 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5168 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5169 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5170 emit_int8((unsigned char)0xDB);
5171 emit_int8((unsigned char)(0xC0 | encode));
5172 }
5173
5174 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5175 assert(UseAVX > 0, "requires some form of AVX");
5176 InstructionMark im(this);
5177 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5178 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5179 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5180 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5181 emit_int8((unsigned char)0xDB);
5182 emit_operand(dst, src);
5183 }
5184
5185 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5186 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5187 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5188 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5189 emit_int8((unsigned char)0xDF);
5190 emit_int8((unsigned char)(0xC0 | encode));
5191 }
5192
5193 void Assembler::por(XMMRegister dst, XMMRegister src) {
5194 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5195 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5196 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5197 emit_int8((unsigned char)0xEB);
5198 emit_int8((unsigned char)(0xC0 | encode));
5199 }
5200
5201 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5202 assert(UseAVX > 0, "requires some form of AVX");
5203 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5204 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5205 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5206 emit_int8((unsigned char)0xEB);
5207 emit_int8((unsigned char)(0xC0 | encode));
5208 }
5209
5210 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5211 assert(UseAVX > 0, "requires some form of AVX");
5212 InstructionMark im(this);
5213 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5214 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5215 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5216 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5217 emit_int8((unsigned char)0xEB);
5218 emit_operand(dst, src);
5219 }
5220
5221 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5222 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5223 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5224 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5225 emit_int8((unsigned char)0xEF);
5226 emit_int8((unsigned char)(0xC0 | encode));
5227 }
5228
5229 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5230 assert(UseAVX > 0, "requires some form of AVX");
5231 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5232 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5233 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5234 emit_int8((unsigned char)0xEF);
5235 emit_int8((unsigned char)(0xC0 | encode));
5236 }
5237
5238 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5239 assert(UseAVX > 0, "requires some form of AVX");
5240 InstructionMark im(this);
5241 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5242 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5243 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5244 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5245 emit_int8((unsigned char)0xEF);
5246 emit_operand(dst, src);
5247 }
5248
5249
5250 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5251 assert(VM_Version::supports_avx(), "");
5252 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5253 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5254 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5255 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5256 emit_int8(0x18);
5257 emit_int8((unsigned char)(0xC0 | encode));
5258 // 0x00 - insert into lower 128 bits
5259 // 0x01 - insert into upper 128 bits
5260 emit_int8(0x01);
5261 }
5262
5263 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5264 assert(VM_Version::supports_evex(), "");
5265 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5266 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5267 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5268 emit_int8(0x1A);
5269 emit_int8((unsigned char)(0xC0 | encode));
5270 // 0x00 - insert into lower 256 bits
5271 // 0x01 - insert into upper 256 bits
5272 emit_int8(value & 0x01);
5273 }
5274
5275 void Assembler::vinsertf64x4h(XMMRegister dst, Address src, int value) {
5276 assert(VM_Version::supports_evex(), "");
5277 assert(dst != xnoreg, "sanity");
5278 InstructionMark im(this);
5279 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5280 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5281 // swap src<->dst for encoding
5282 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5283 emit_int8(0x1A);
5284 emit_operand(dst, src);
5285 // 0x00 - insert into lower 256 bits
5286 // 0x01 - insert into upper 128 bits
5287 emit_int8(value & 0x01);
5288 }
5289
5290 void Assembler::vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5291 assert(VM_Version::supports_evex(), "");
5292 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5293 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5294 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5295 emit_int8(0x18);
5296 emit_int8((unsigned char)(0xC0 | encode));
5297 // 0x00 - insert into q0 128 bits (0..127)
5298 // 0x01 - insert into q1 128 bits (128..255)
5299 // 0x02 - insert into q2 128 bits (256..383)
5300 // 0x03 - insert into q3 128 bits (384..511)
5301 emit_int8(value & 0x3);
5302 }
5303
5304 void Assembler::vinsertf32x4h(XMMRegister dst, Address src, int value) {
5305 assert(VM_Version::supports_avx(), "");
5306 assert(dst != xnoreg, "sanity");
5307 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5308 InstructionMark im(this);
5309 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5310 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5311 // swap src<->dst for encoding
5312 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5313 emit_int8(0x18);
5314 emit_operand(dst, src);
5315 // 0x00 - insert into q0 128 bits (0..127)
5316 // 0x01 - insert into q1 128 bits (128..255)
5317 // 0x02 - insert into q2 128 bits (256..383)
5318 // 0x03 - insert into q3 128 bits (384..511)
5319 emit_int8(value & 0x3);
5320 }
5321
5322 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
5323 assert(VM_Version::supports_avx(), "");
5324 assert(dst != xnoreg, "sanity");
5325 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5326 InstructionMark im(this);
5327 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5328 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5329 // swap src<->dst for encoding
5330 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5331 emit_int8(0x18);
5332 emit_operand(dst, src);
5333 // 0x01 - insert into upper 128 bits
5334 emit_int8(0x01);
5335 }
5336
5337 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
5338 assert(VM_Version::supports_avx(), "");
5339 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5340 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5341 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5342 emit_int8(0x19);
5343 emit_int8((unsigned char)(0xC0 | encode));
5344 // 0x00 - insert into lower 128 bits
5345 // 0x01 - insert into upper 128 bits
5346 emit_int8(0x01);
5347 }
5348
5349 void Assembler::vextractf128h(Address dst, XMMRegister src) {
5350 assert(VM_Version::supports_avx(), "");
5351 assert(src != xnoreg, "sanity");
5352 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5353 InstructionMark im(this);
5354 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5355 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5356 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5357 emit_int8(0x19);
5358 emit_operand(src, dst);
5359 // 0x01 - extract from upper 128 bits
5360 emit_int8(0x01);
5361 }
5362
5363 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5364 assert(VM_Version::supports_avx2(), "");
5365 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5366 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5367 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5368 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5369 emit_int8(0x38);
5370 emit_int8((unsigned char)(0xC0 | encode));
5371 // 0x00 - insert into lower 128 bits
5372 // 0x01 - insert into upper 128 bits
5373 emit_int8(0x01);
5374 }
5375
5376 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5377 assert(VM_Version::supports_evex(), "");
5378 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5379 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5380 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5381 emit_int8(0x38);
5382 emit_int8((unsigned char)(0xC0 | encode));
5383 // 0x00 - insert into lower 256 bits
5384 // 0x01 - insert into upper 256 bits
5385 emit_int8(value & 0x01);
5386 }
5387
5388 void Assembler::vinserti128h(XMMRegister dst, Address src) {
5389 assert(VM_Version::supports_avx2(), "");
5390 assert(dst != xnoreg, "sanity");
5391 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5392 InstructionMark im(this);
5393 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5394 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5395 // swap src<->dst for encoding
5396 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5397 emit_int8(0x38);
5398 emit_operand(dst, src);
5399 // 0x01 - insert into upper 128 bits
5400 emit_int8(0x01);
5401 }
5402
5403 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
5404 assert(VM_Version::supports_avx(), "");
5405 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5406 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5407 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5408 emit_int8(0x39);
5409 emit_int8((unsigned char)(0xC0 | encode));
5410 // 0x00 - insert into lower 128 bits
5411 // 0x01 - insert into upper 128 bits
5412 emit_int8(0x01);
5413 }
5414
5415 void Assembler::vextracti128h(Address dst, XMMRegister src) {
5416 assert(VM_Version::supports_avx2(), "");
5417 assert(src != xnoreg, "sanity");
5418 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5419 InstructionMark im(this);
5420 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5421 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5422 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5423 emit_int8(0x39);
5424 emit_operand(src, dst);
5425 // 0x01 - extract from upper 128 bits
5426 emit_int8(0x01);
5427 }
5428
5429 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src, int value) {
5430 assert(VM_Version::supports_evex(), "");
5431 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5432 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5433 emit_int8(0x3B);
5434 emit_int8((unsigned char)(0xC0 | encode));
5435 // 0x00 - extract from lower 256 bits
5436 // 0x01 - extract from upper 256 bits
5437 emit_int8(value & 0x01);
5438 }
5439
5440 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
5441 assert(VM_Version::supports_evex(), "");
5442 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5443 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5444 emit_int8(0x39);
5445 emit_int8((unsigned char)(0xC0 | encode));
5446 // 0x01 - extract from bits 255:128
5447 // 0x02 - extract from bits 383:256
5448 // 0x03 - extract from bits 511:384
5449 emit_int8(value & 0x3);
5450 }
5451
5452 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src, int value) {
5453 assert(VM_Version::supports_evex(), "");
5454 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5455 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5456 emit_int8(0x1B);
5457 emit_int8((unsigned char)(0xC0 | encode));
5458 // 0x00 - extract from lower 256 bits
5459 // 0x01 - extract from upper 256 bits
5460 emit_int8(value & 0x1);
5461 }
5462
5463 void Assembler::vextractf64x4h(Address dst, XMMRegister src, int value) {
5464 assert(VM_Version::supports_evex(), "");
5465 assert(src != xnoreg, "sanity");
5466 InstructionMark im(this);
5467 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5468 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
5469 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5470 emit_int8(0x1B);
5471 emit_operand(src, dst);
5472 // 0x00 - extract from lower 256 bits
5473 // 0x01 - extract from upper 256 bits
5474 emit_int8(value & 0x01);
5475 }
5476
5477 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
5478 assert(VM_Version::supports_avx(), "");
5479 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5480 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5481 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5482 emit_int8(0x19);
5483 emit_int8((unsigned char)(0xC0 | encode));
5484 // 0x00 - extract from bits 127:0
5485 // 0x01 - extract from bits 255:128
5486 // 0x02 - extract from bits 383:256
5487 // 0x03 - extract from bits 511:384
5488 emit_int8(value & 0x3);
5489 }
5490
5491 void Assembler::vextractf32x4h(Address dst, XMMRegister src, int value) {
5492 assert(VM_Version::supports_evex(), "");
5493 assert(src != xnoreg, "sanity");
5494 InstructionMark im(this);
5495 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5496 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5497 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5498 emit_int8(0x19);
5499 emit_operand(src, dst);
5500 // 0x00 - extract from bits 127:0
5501 // 0x01 - extract from bits 255:128
5502 // 0x02 - extract from bits 383:256
5503 // 0x03 - extract from bits 511:384
5504 emit_int8(value & 0x3);
5505 }
5506
5507 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
5508 assert(VM_Version::supports_evex(), "");
5509 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5510 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5511 emit_int8(0x19);
5512 emit_int8((unsigned char)(0xC0 | encode));
5513 // 0x01 - extract from bits 255:128
5514 // 0x02 - extract from bits 383:256
5515 // 0x03 - extract from bits 511:384
5516 emit_int8(value & 0x3);
5517 }
5518
5519 // duplicate 4-bytes integer data from src into 8 locations in dest
5520 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5521 assert(VM_Version::supports_avx2(), "");
5522 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5523 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5524 emit_int8(0x58);
5525 emit_int8((unsigned char)(0xC0 | encode));
5526 }
5527
5528 // duplicate 2-bytes integer data from src into 16 locations in dest
5529 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
5530 assert(VM_Version::supports_avx2(), "");
5531 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5532 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5533 emit_int8(0x79);
5534 emit_int8((unsigned char)(0xC0 | encode));
5535 }
5536
5537 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5538 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5539 assert(VM_Version::supports_evex(), "");
5540 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5541 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5542 emit_int8(0x78);
5543 emit_int8((unsigned char)(0xC0 | encode));
5544 }
5545
5546 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5547 assert(VM_Version::supports_evex(), "");
5548 assert(dst != xnoreg, "sanity");
5549 InstructionMark im(this);
5550 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5551 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
5552 // swap src<->dst for encoding
5553 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5554 emit_int8(0x78);
5555 emit_operand(dst, src);
5556 }
5557
5558 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5559 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5560 assert(VM_Version::supports_evex(), "");
5561 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5562 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5563 emit_int8(0x79);
5564 emit_int8((unsigned char)(0xC0 | encode));
5565 }
5566
5567 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5568 assert(VM_Version::supports_evex(), "");
5569 assert(dst != xnoreg, "sanity");
5570 InstructionMark im(this);
5571 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5572 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
5573 // swap src<->dst for encoding
5574 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5575 emit_int8(0x79);
5576 emit_operand(dst, src);
5577 }
5578
5579 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5580 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5581 assert(VM_Version::supports_evex(), "");
5582 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5583 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5584 emit_int8(0x58);
5585 emit_int8((unsigned char)(0xC0 | encode));
5586 }
5587
5588 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5589 assert(VM_Version::supports_evex(), "");
5590 assert(dst != xnoreg, "sanity");
5591 InstructionMark im(this);
5592 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5593 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5594 // swap src<->dst for encoding
5595 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5596 emit_int8(0x58);
5597 emit_operand(dst, src);
5598 }
5599
5600 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5601 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5602 assert(VM_Version::supports_evex(), "");
5603 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5604 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5605 emit_int8(0x59);
5606 emit_int8((unsigned char)(0xC0 | encode));
5607 }
5608
5609 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5610 assert(VM_Version::supports_evex(), "");
5611 assert(dst != xnoreg, "sanity");
5612 InstructionMark im(this);
5613 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5614 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5615 // swap src<->dst for encoding
5616 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5617 emit_int8(0x59);
5618 emit_operand(dst, src);
5619 }
5620
5621 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5622 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5623 assert(VM_Version::supports_evex(), "");
5624 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5625 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5626 emit_int8(0x18);
5627 emit_int8((unsigned char)(0xC0 | encode));
5628 }
5629
5630 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5631 assert(VM_Version::supports_evex(), "");
5632 assert(dst != xnoreg, "sanity");
5633 InstructionMark im(this);
5634 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5635 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5636 // swap src<->dst for encoding
5637 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5638 emit_int8(0x18);
5639 emit_operand(dst, src);
5640 }
5641
5642 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5643 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5644 assert(VM_Version::supports_evex(), "");
5645 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5646 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5647 emit_int8(0x19);
5648 emit_int8((unsigned char)(0xC0 | encode));
5649 }
5650
5651 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5652 assert(VM_Version::supports_evex(), "");
5653 assert(dst != xnoreg, "sanity");
5654 InstructionMark im(this);
5655 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5656 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5657 // swap src<->dst for encoding
5658 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5659 emit_int8(0x19);
5660 emit_operand(dst, src);
5661 }
5662
5663 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5664 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5665 assert(VM_Version::supports_evex(), "");
5666 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5667 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5668 emit_int8(0x7A);
5669 emit_int8((unsigned char)(0xC0 | encode));
5670 }
5671
5672 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5673 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5674 assert(VM_Version::supports_evex(), "");
5675 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5676 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5677 emit_int8(0x7B);
5678 emit_int8((unsigned char)(0xC0 | encode));
5679 }
5680
5681 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5682 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5683 assert(VM_Version::supports_evex(), "");
5684 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5685 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5686 emit_int8(0x7C);
5687 emit_int8((unsigned char)(0xC0 | encode));
5688 }
5689
5690 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5691 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5692 assert(VM_Version::supports_evex(), "");
5693 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5694 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5695 emit_int8(0x7C);
5696 emit_int8((unsigned char)(0xC0 | encode));
5697 }
5698
5699 // Carry-Less Multiplication Quadword
5700 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5701 assert(VM_Version::supports_clmul(), "");
5702 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5703 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5704 emit_int8(0x44);
5705 emit_int8((unsigned char)(0xC0 | encode));
5706 emit_int8((unsigned char)mask);
5707 }
5708
5709 // Carry-Less Multiplication Quadword
5710 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5711 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5712 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5713 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5714 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5715 emit_int8(0x44);
5716 emit_int8((unsigned char)(0xC0 | encode));
5717 emit_int8((unsigned char)mask);
5718 }
5719
5720 void Assembler::vzeroupper() {
5721 assert(VM_Version::supports_avx(), "");
5722 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5723 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5724 emit_int8(0x77);
5725 }
5726
5727
5728 #ifndef _LP64
5729 // 32bit only pieces of the assembler
5730
5731 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5732 // NO PREFIX AS NEVER 64BIT
5733 InstructionMark im(this);
5734 emit_int8((unsigned char)0x81);
5735 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5736 emit_data(imm32, rspec, 0);
5737 }
5738
5739 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5740 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5741 InstructionMark im(this);
5742 emit_int8((unsigned char)0x81);
5743 emit_operand(rdi, src1);
5744 emit_data(imm32, rspec, 0);
5745 }
5746
5747 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5748 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5749 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5750 void Assembler::cmpxchg8(Address adr) {
5751 InstructionMark im(this);
5752 emit_int8(0x0F);
5753 emit_int8((unsigned char)0xC7);
5754 emit_operand(rcx, adr);
5755 }
5756
5757 void Assembler::decl(Register dst) {
5758 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5759 emit_int8(0x48 | dst->encoding());
5760 }
5761
5762 #endif // _LP64
5763
5764 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5765
5766 void Assembler::fabs() {
5767 emit_int8((unsigned char)0xD9);
5768 emit_int8((unsigned char)0xE1);
5769 }
5770
5771 void Assembler::fadd(int i) {
5772 emit_farith(0xD8, 0xC0, i);
5773 }
5774
5775 void Assembler::fadd_d(Address src) {
5776 InstructionMark im(this);
5777 emit_int8((unsigned char)0xDC);
5778 emit_operand32(rax, src);
5779 }
5780
5781 void Assembler::fadd_s(Address src) {
5782 InstructionMark im(this);
5783 emit_int8((unsigned char)0xD8);
5784 emit_operand32(rax, src);
5785 }
5786
5787 void Assembler::fadda(int i) {
5788 emit_farith(0xDC, 0xC0, i);
5789 }
5790
5791 void Assembler::faddp(int i) {
5792 emit_farith(0xDE, 0xC0, i);
5793 }
5794
5795 void Assembler::fchs() {
5796 emit_int8((unsigned char)0xD9);
5797 emit_int8((unsigned char)0xE0);
5798 }
5799
5800 void Assembler::fcom(int i) {
5801 emit_farith(0xD8, 0xD0, i);
5802 }
5803
5804 void Assembler::fcomp(int i) {
5805 emit_farith(0xD8, 0xD8, i);
5806 }
5807
5808 void Assembler::fcomp_d(Address src) {
5809 InstructionMark im(this);
5810 emit_int8((unsigned char)0xDC);
5811 emit_operand32(rbx, src);
5812 }
5813
5814 void Assembler::fcomp_s(Address src) {
5815 InstructionMark im(this);
5816 emit_int8((unsigned char)0xD8);
5817 emit_operand32(rbx, src);
5818 }
5819
5820 void Assembler::fcompp() {
5821 emit_int8((unsigned char)0xDE);
5822 emit_int8((unsigned char)0xD9);
5823 }
5824
5825 void Assembler::fcos() {
5826 emit_int8((unsigned char)0xD9);
5827 emit_int8((unsigned char)0xFF);
5828 }
5829
5830 void Assembler::fdecstp() {
5831 emit_int8((unsigned char)0xD9);
5832 emit_int8((unsigned char)0xF6);
5833 }
5834
5835 void Assembler::fdiv(int i) {
5836 emit_farith(0xD8, 0xF0, i);
5837 }
5838
5839 void Assembler::fdiv_d(Address src) {
5840 InstructionMark im(this);
5841 emit_int8((unsigned char)0xDC);
5842 emit_operand32(rsi, src);
5843 }
5844
5845 void Assembler::fdiv_s(Address src) {
5846 InstructionMark im(this);
5847 emit_int8((unsigned char)0xD8);
5848 emit_operand32(rsi, src);
5849 }
5850
5851 void Assembler::fdiva(int i) {
5852 emit_farith(0xDC, 0xF8, i);
5853 }
5854
5855 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
5856 // is erroneous for some of the floating-point instructions below.
5857
5858 void Assembler::fdivp(int i) {
5859 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
5860 }
5861
5862 void Assembler::fdivr(int i) {
5863 emit_farith(0xD8, 0xF8, i);
5864 }
5865
5866 void Assembler::fdivr_d(Address src) {
5867 InstructionMark im(this);
5868 emit_int8((unsigned char)0xDC);
5869 emit_operand32(rdi, src);
5870 }
5871
5872 void Assembler::fdivr_s(Address src) {
5873 InstructionMark im(this);
5874 emit_int8((unsigned char)0xD8);
5875 emit_operand32(rdi, src);
5876 }
5877
5878 void Assembler::fdivra(int i) {
5879 emit_farith(0xDC, 0xF0, i);
5880 }
5881
5882 void Assembler::fdivrp(int i) {
5883 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
5884 }
5885
5886 void Assembler::ffree(int i) {
5887 emit_farith(0xDD, 0xC0, i);
5888 }
5889
5890 void Assembler::fild_d(Address adr) {
5891 InstructionMark im(this);
5892 emit_int8((unsigned char)0xDF);
5893 emit_operand32(rbp, adr);
5894 }
5895
5896 void Assembler::fild_s(Address adr) {
5897 InstructionMark im(this);
5898 emit_int8((unsigned char)0xDB);
5899 emit_operand32(rax, adr);
5900 }
5901
5902 void Assembler::fincstp() {
5903 emit_int8((unsigned char)0xD9);
5904 emit_int8((unsigned char)0xF7);
5905 }
5906
5907 void Assembler::finit() {
5908 emit_int8((unsigned char)0x9B);
5909 emit_int8((unsigned char)0xDB);
5910 emit_int8((unsigned char)0xE3);
5911 }
5912
5913 void Assembler::fist_s(Address adr) {
5914 InstructionMark im(this);
5915 emit_int8((unsigned char)0xDB);
5916 emit_operand32(rdx, adr);
5917 }
5918
5919 void Assembler::fistp_d(Address adr) {
5920 InstructionMark im(this);
5921 emit_int8((unsigned char)0xDF);
5922 emit_operand32(rdi, adr);
5923 }
5924
5925 void Assembler::fistp_s(Address adr) {
5926 InstructionMark im(this);
5927 emit_int8((unsigned char)0xDB);
5928 emit_operand32(rbx, adr);
5929 }
5930
5931 void Assembler::fld1() {
5932 emit_int8((unsigned char)0xD9);
5933 emit_int8((unsigned char)0xE8);
5934 }
5935
5936 void Assembler::fld_d(Address adr) {
5937 InstructionMark im(this);
5938 emit_int8((unsigned char)0xDD);
5939 emit_operand32(rax, adr);
5940 }
5941
5942 void Assembler::fld_s(Address adr) {
5943 InstructionMark im(this);
5944 emit_int8((unsigned char)0xD9);
5945 emit_operand32(rax, adr);
5946 }
5947
5948
5949 void Assembler::fld_s(int index) {
5950 emit_farith(0xD9, 0xC0, index);
5951 }
5952
5953 void Assembler::fld_x(Address adr) {
5954 InstructionMark im(this);
5955 emit_int8((unsigned char)0xDB);
5956 emit_operand32(rbp, adr);
5957 }
5958
5959 void Assembler::fldcw(Address src) {
5960 InstructionMark im(this);
5961 emit_int8((unsigned char)0xD9);
5962 emit_operand32(rbp, src);
5963 }
5964
5965 void Assembler::fldenv(Address src) {
5966 InstructionMark im(this);
5967 emit_int8((unsigned char)0xD9);
5968 emit_operand32(rsp, src);
5969 }
5970
5971 void Assembler::fldlg2() {
5972 emit_int8((unsigned char)0xD9);
5973 emit_int8((unsigned char)0xEC);
5974 }
5975
5976 void Assembler::fldln2() {
5977 emit_int8((unsigned char)0xD9);
5978 emit_int8((unsigned char)0xED);
5979 }
5980
5981 void Assembler::fldz() {
5982 emit_int8((unsigned char)0xD9);
5983 emit_int8((unsigned char)0xEE);
5984 }
5985
5986 void Assembler::flog() {
5987 fldln2();
5988 fxch();
5989 fyl2x();
5990 }
5991
5992 void Assembler::flog10() {
5993 fldlg2();
5994 fxch();
5995 fyl2x();
5996 }
5997
5998 void Assembler::fmul(int i) {
5999 emit_farith(0xD8, 0xC8, i);
6000 }
6001
6002 void Assembler::fmul_d(Address src) {
6003 InstructionMark im(this);
6004 emit_int8((unsigned char)0xDC);
6005 emit_operand32(rcx, src);
6006 }
6007
6008 void Assembler::fmul_s(Address src) {
6009 InstructionMark im(this);
6010 emit_int8((unsigned char)0xD8);
6011 emit_operand32(rcx, src);
6012 }
6013
6014 void Assembler::fmula(int i) {
6015 emit_farith(0xDC, 0xC8, i);
6016 }
6017
6018 void Assembler::fmulp(int i) {
6019 emit_farith(0xDE, 0xC8, i);
6020 }
6021
6022 void Assembler::fnsave(Address dst) {
6023 InstructionMark im(this);
6024 emit_int8((unsigned char)0xDD);
6025 emit_operand32(rsi, dst);
6026 }
6027
6028 void Assembler::fnstcw(Address src) {
6029 InstructionMark im(this);
6030 emit_int8((unsigned char)0x9B);
6031 emit_int8((unsigned char)0xD9);
6032 emit_operand32(rdi, src);
6033 }
6034
6035 void Assembler::fnstsw_ax() {
6036 emit_int8((unsigned char)0xDF);
6037 emit_int8((unsigned char)0xE0);
6038 }
6039
6040 void Assembler::fprem() {
6041 emit_int8((unsigned char)0xD9);
6042 emit_int8((unsigned char)0xF8);
6043 }
6044
6045 void Assembler::fprem1() {
6046 emit_int8((unsigned char)0xD9);
6047 emit_int8((unsigned char)0xF5);
6048 }
6049
6050 void Assembler::frstor(Address src) {
6051 InstructionMark im(this);
6052 emit_int8((unsigned char)0xDD);
6053 emit_operand32(rsp, src);
6054 }
6055
6056 void Assembler::fsin() {
6057 emit_int8((unsigned char)0xD9);
6058 emit_int8((unsigned char)0xFE);
6059 }
6060
6061 void Assembler::fsqrt() {
6062 emit_int8((unsigned char)0xD9);
6063 emit_int8((unsigned char)0xFA);
6064 }
6065
6066 void Assembler::fst_d(Address adr) {
6067 InstructionMark im(this);
6068 emit_int8((unsigned char)0xDD);
6069 emit_operand32(rdx, adr);
6070 }
6071
6072 void Assembler::fst_s(Address adr) {
6073 InstructionMark im(this);
6074 emit_int8((unsigned char)0xD9);
6075 emit_operand32(rdx, adr);
6076 }
6077
6078 void Assembler::fstp_d(Address adr) {
6079 InstructionMark im(this);
6080 emit_int8((unsigned char)0xDD);
6081 emit_operand32(rbx, adr);
6082 }
6083
6084 void Assembler::fstp_d(int index) {
6085 emit_farith(0xDD, 0xD8, index);
6086 }
6087
6088 void Assembler::fstp_s(Address adr) {
6089 InstructionMark im(this);
6090 emit_int8((unsigned char)0xD9);
6091 emit_operand32(rbx, adr);
6092 }
6093
6094 void Assembler::fstp_x(Address adr) {
6095 InstructionMark im(this);
6096 emit_int8((unsigned char)0xDB);
6097 emit_operand32(rdi, adr);
6098 }
6099
6100 void Assembler::fsub(int i) {
6101 emit_farith(0xD8, 0xE0, i);
6102 }
6103
6104 void Assembler::fsub_d(Address src) {
6105 InstructionMark im(this);
6106 emit_int8((unsigned char)0xDC);
6107 emit_operand32(rsp, src);
6108 }
6109
6110 void Assembler::fsub_s(Address src) {
6111 InstructionMark im(this);
6112 emit_int8((unsigned char)0xD8);
6113 emit_operand32(rsp, src);
6114 }
6115
6116 void Assembler::fsuba(int i) {
6117 emit_farith(0xDC, 0xE8, i);
6118 }
6119
6120 void Assembler::fsubp(int i) {
6121 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6122 }
6123
6124 void Assembler::fsubr(int i) {
6125 emit_farith(0xD8, 0xE8, i);
6126 }
6127
6128 void Assembler::fsubr_d(Address src) {
6129 InstructionMark im(this);
6130 emit_int8((unsigned char)0xDC);
6131 emit_operand32(rbp, src);
6132 }
6133
6134 void Assembler::fsubr_s(Address src) {
6135 InstructionMark im(this);
6136 emit_int8((unsigned char)0xD8);
6137 emit_operand32(rbp, src);
6138 }
6139
6140 void Assembler::fsubra(int i) {
6141 emit_farith(0xDC, 0xE0, i);
6142 }
6143
6144 void Assembler::fsubrp(int i) {
6145 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6146 }
6147
6148 void Assembler::ftan() {
6149 emit_int8((unsigned char)0xD9);
6150 emit_int8((unsigned char)0xF2);
6151 emit_int8((unsigned char)0xDD);
6152 emit_int8((unsigned char)0xD8);
6153 }
6154
6155 void Assembler::ftst() {
6156 emit_int8((unsigned char)0xD9);
6157 emit_int8((unsigned char)0xE4);
6158 }
6159
6160 void Assembler::fucomi(int i) {
6161 // make sure the instruction is supported (introduced for P6, together with cmov)
6162 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6163 emit_farith(0xDB, 0xE8, i);
6164 }
6165
6166 void Assembler::fucomip(int i) {
6167 // make sure the instruction is supported (introduced for P6, together with cmov)
6168 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6169 emit_farith(0xDF, 0xE8, i);
6170 }
6171
6172 void Assembler::fwait() {
6173 emit_int8((unsigned char)0x9B);
6174 }
6175
6176 void Assembler::fxch(int i) {
6177 emit_farith(0xD9, 0xC8, i);
6178 }
6179
6180 void Assembler::fyl2x() {
6181 emit_int8((unsigned char)0xD9);
6182 emit_int8((unsigned char)0xF1);
6183 }
6184
6185 void Assembler::frndint() {
6186 emit_int8((unsigned char)0xD9);
6187 emit_int8((unsigned char)0xFC);
6188 }
6189
6190 void Assembler::f2xm1() {
6191 emit_int8((unsigned char)0xD9);
6192 emit_int8((unsigned char)0xF0);
6193 }
6194
6195 void Assembler::fldl2e() {
6196 emit_int8((unsigned char)0xD9);
6197 emit_int8((unsigned char)0xEA);
6198 }
6199
6200 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6201 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6202 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6203 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6204
6205 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6206 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6207 if (pre > 0) {
6208 emit_int8(simd_pre[pre]);
6209 }
6210 if (rex_w) {
6211 prefixq(adr, xreg);
6212 } else {
6213 prefix(adr, xreg);
6214 }
6215 if (opc > 0) {
6216 emit_int8(0x0F);
6217 int opc2 = simd_opc[opc];
6218 if (opc2 > 0) {
6219 emit_int8(opc2);
6220 }
6221 }
6222 }
6223
6224 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6225 if (pre > 0) {
6226 emit_int8(simd_pre[pre]);
6227 }
6228 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6229 if (opc > 0) {
6230 emit_int8(0x0F);
6231 int opc2 = simd_opc[opc];
6232 if (opc2 > 0) {
6233 emit_int8(opc2);
6234 }
6235 }
6236 return encode;
6237 }
6238
6239
6240 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6241 int vector_len = _attributes->get_vector_len();
6242 bool vex_w = _attributes->is_rex_vex_w();
6243 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6244 prefix(VEX_3bytes);
6245
6246 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6247 byte1 = (~byte1) & 0xE0;
6248 byte1 |= opc;
6249 emit_int8(byte1);
6250
6251 int byte2 = ((~nds_enc) & 0xf) << 3;
6252 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6253 emit_int8(byte2);
6254 } else {
6255 prefix(VEX_2bytes);
6256
6257 int byte1 = vex_r ? VEX_R : 0;
6258 byte1 = (~byte1) & 0x80;
6259 byte1 |= ((~nds_enc) & 0xf) << 3;
6260 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6261 emit_int8(byte1);
6262 }
6263 }
6264
6265 // This is a 4 byte encoding
6266 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6267 // EVEX 0x62 prefix
6268 prefix(EVEX_4bytes);
6269 bool vex_w = _attributes->is_rex_vex_w();
6270 int evex_encoding = (vex_w ? VEX_W : 0);
6271 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6272 _attributes->set_evex_encoding(evex_encoding);
6273
6274 // P0: byte 2, initialized to RXBR`00mm
6275 // instead of not'd
6276 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6277 byte2 = (~byte2) & 0xF0;
6278 // confine opc opcode extensions in mm bits to lower two bits
6279 // of form {0F, 0F_38, 0F_3A}
6280 byte2 |= opc;
6281 emit_int8(byte2);
6282
6283 // P1: byte 3 as Wvvvv1pp
6284 int byte3 = ((~nds_enc) & 0xf) << 3;
6285 // p[10] is always 1
6286 byte3 |= EVEX_F;
6287 byte3 |= (vex_w & 1) << 7;
6288 // confine pre opcode extensions in pp bits to lower two bits
6289 // of form {66, F3, F2}
6290 byte3 |= pre;
6291 emit_int8(byte3);
6292
6293 // P2: byte 4 as zL'Lbv'aaa
6294 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6295 // EVEX.v` for extending EVEX.vvvv or VIDX
6296 byte4 |= (evex_v ? 0: EVEX_V);
6297 // third EXEC.b for broadcast actions
6298 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6299 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6300 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6301 // last is EVEX.z for zero/merge actions
6302 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6303 emit_int8(byte4);
6304 }
6305
6306 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6307 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6308 bool vex_b = adr.base_needs_rex();
6309 bool vex_x = adr.index_needs_rex();
6310 set_attributes(attributes);
6311 attributes->set_current_assembler(this);
6312
6313 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6314 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6315 switch (attributes->get_vector_len()) {
6316 case AVX_128bit:
6317 case AVX_256bit:
6318 attributes->set_is_legacy_mode();
6319 break;
6320 }
6321 }
6322
6323 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6324 {
6325 bool evex_r = (xreg_enc >= 16);
6326 bool evex_v = (nds_enc >= 16);
6327 attributes->set_is_evex_instruction();
6328 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6329 } else {
6330 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6331 }
6332 }
6333
6334 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6335 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6336 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6337 bool vex_x = false;
6338 set_attributes(attributes);
6339 attributes->set_current_assembler(this);
6340
6341 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6342 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6343 switch (attributes->get_vector_len()) {
6344 case AVX_128bit:
6345 case AVX_256bit:
6346 if ((dst_enc >= 16) | (nds_enc >= 16) | (src_enc >= 16)) {
6347 // up propagate arithmetic instructions to meet RA requirements
6348 attributes->set_vector_len(AVX_512bit);
6349 } else {
6350 attributes->set_is_legacy_mode();
6351 }
6352 break;
6353 }
6354 }
6355
6356 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6357 {
6358 bool evex_r = (dst_enc >= 16);
6359 bool evex_v = (nds_enc >= 16);
6360 // can use vex_x as bank extender on rm encoding
6361 vex_x = (src_enc >= 16);
6362 attributes->set_is_evex_instruction();
6363 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6364 } else {
6365 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6366 }
6367
6368 // return modrm byte components for operands
6369 return (((dst_enc & 7) << 3) | (src_enc & 7));
6370 }
6371
6372
6373 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6374 VexOpcode opc, InstructionAttr *attributes) {
6375 if (UseAVX > 0) {
6376 int xreg_enc = xreg->encoding();
6377 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6378 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6379 } else {
6380 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6381 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6382 }
6383 }
6384
6385 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6386 VexOpcode opc, InstructionAttr *attributes) {
6387 int dst_enc = dst->encoding();
6388 int src_enc = src->encoding();
6389 if (UseAVX > 0) {
6390 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6391 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6392 } else {
6393 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6394 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6395 }
6396 }
6397
6398 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
6399 VexOpcode opc, InstructionAttr *attributes) {
6400 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6401 return vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), pre, opc, attributes);
6402 }
6403
6404 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
6405 VexOpcode opc, InstructionAttr *attributes) {
6406 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6407 return vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), pre, opc, attributes);
6408 }
6409
6410 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6411 assert(VM_Version::supports_avx(), "");
6412 assert(!VM_Version::supports_evex(), "");
6413 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6414 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6415 emit_int8((unsigned char)0xC2);
6416 emit_int8((unsigned char)(0xC0 | encode));
6417 emit_int8((unsigned char)(0xF & cop));
6418 }
6419
6420 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6421 assert(VM_Version::supports_avx(), "");
6422 assert(!VM_Version::supports_evex(), "");
6423 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6424 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6425 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6426 emit_int8((unsigned char)0x4B);
6427 emit_int8((unsigned char)(0xC0 | encode));
6428 int src2_enc = src2->encoding();
6429 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6430 }
6431
6432
6433 #ifndef _LP64
6434
6435 void Assembler::incl(Register dst) {
6436 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6437 emit_int8(0x40 | dst->encoding());
6438 }
6439
6440 void Assembler::lea(Register dst, Address src) {
6441 leal(dst, src);
6442 }
6443
6444 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6445 InstructionMark im(this);
6446 emit_int8((unsigned char)0xC7);
6447 emit_operand(rax, dst);
6448 emit_data((int)imm32, rspec, 0);
6449 }
6450
6451 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6452 InstructionMark im(this);
6453 int encode = prefix_and_encode(dst->encoding());
6454 emit_int8((unsigned char)(0xB8 | encode));
6455 emit_data((int)imm32, rspec, 0);
6456 }
6457
6458 void Assembler::popa() { // 32bit
6459 emit_int8(0x61);
6460 }
6461
6462 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
6463 InstructionMark im(this);
6464 emit_int8(0x68);
6465 emit_data(imm32, rspec, 0);
6466 }
6467
6468 void Assembler::pusha() { // 32bit
6469 emit_int8(0x60);
6470 }
6471
6472 void Assembler::set_byte_if_not_zero(Register dst) {
6473 emit_int8(0x0F);
6474 emit_int8((unsigned char)0x95);
6475 emit_int8((unsigned char)(0xE0 | dst->encoding()));
6476 }
6477
6478 void Assembler::shldl(Register dst, Register src) {
6479 emit_int8(0x0F);
6480 emit_int8((unsigned char)0xA5);
6481 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6482 }
6483
6484 // 0F A4 / r ib
6485 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6486 emit_int8(0x0F);
6487 emit_int8((unsigned char)0xA4);
6488 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6489 emit_int8(imm8);
6490 }
6491
6492 void Assembler::shrdl(Register dst, Register src) {
6493 emit_int8(0x0F);
6494 emit_int8((unsigned char)0xAD);
6495 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6496 }
6497
6498 #else // LP64
6499
6500 void Assembler::set_byte_if_not_zero(Register dst) {
6501 int enc = prefix_and_encode(dst->encoding(), true);
6502 emit_int8(0x0F);
6503 emit_int8((unsigned char)0x95);
6504 emit_int8((unsigned char)(0xE0 | enc));
6505 }
6506
6507 // 64bit only pieces of the assembler
6508 // This should only be used by 64bit instructions that can use rip-relative
6509 // it cannot be used by instructions that want an immediate value.
6510
6511 bool Assembler::reachable(AddressLiteral adr) {
6512 int64_t disp;
6513 // None will force a 64bit literal to the code stream. Likely a placeholder
6514 // for something that will be patched later and we need to certain it will
6515 // always be reachable.
6516 if (adr.reloc() == relocInfo::none) {
6517 return false;
6518 }
6519 if (adr.reloc() == relocInfo::internal_word_type) {
6520 // This should be rip relative and easily reachable.
6521 return true;
6522 }
6523 if (adr.reloc() == relocInfo::virtual_call_type ||
6524 adr.reloc() == relocInfo::opt_virtual_call_type ||
6525 adr.reloc() == relocInfo::static_call_type ||
6526 adr.reloc() == relocInfo::static_stub_type ) {
6527 // This should be rip relative within the code cache and easily
6528 // reachable until we get huge code caches. (At which point
6529 // ic code is going to have issues).
6530 return true;
6531 }
6532 if (adr.reloc() != relocInfo::external_word_type &&
6533 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
6534 adr.reloc() != relocInfo::poll_type && // relocs to identify them
6535 adr.reloc() != relocInfo::runtime_call_type ) {
6536 return false;
6537 }
6538
6539 // Stress the correction code
6540 if (ForceUnreachable) {
6541 // Must be runtimecall reloc, see if it is in the codecache
6542 // Flipping stuff in the codecache to be unreachable causes issues
6543 // with things like inline caches where the additional instructions
6544 // are not handled.
6545 if (CodeCache::find_blob(adr._target) == NULL) {
6546 return false;
6547 }
6548 }
6549 // For external_word_type/runtime_call_type if it is reachable from where we
6550 // are now (possibly a temp buffer) and where we might end up
6551 // anywhere in the codeCache then we are always reachable.
6552 // This would have to change if we ever save/restore shared code
6553 // to be more pessimistic.
6554 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
6555 if (!is_simm32(disp)) return false;
6556 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
6557 if (!is_simm32(disp)) return false;
6558
6559 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
6560
6561 // Because rip relative is a disp + address_of_next_instruction and we
6562 // don't know the value of address_of_next_instruction we apply a fudge factor
6563 // to make sure we will be ok no matter the size of the instruction we get placed into.
6564 // We don't have to fudge the checks above here because they are already worst case.
6565
6566 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
6567 // + 4 because better safe than sorry.
6568 const int fudge = 12 + 4;
6569 if (disp < 0) {
6570 disp -= fudge;
6571 } else {
6572 disp += fudge;
6573 }
6574 return is_simm32(disp);
6575 }
6576
6577 // Check if the polling page is not reachable from the code cache using rip-relative
6578 // addressing.
6579 bool Assembler::is_polling_page_far() {
6580 intptr_t addr = (intptr_t)os::get_polling_page();
6581 return ForceUnreachable ||
6582 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
6583 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
6584 }
6585
6586 void Assembler::emit_data64(jlong data,
6587 relocInfo::relocType rtype,
6588 int format) {
6589 if (rtype == relocInfo::none) {
6590 emit_int64(data);
6591 } else {
6592 emit_data64(data, Relocation::spec_simple(rtype), format);
6593 }
6594 }
6595
6596 void Assembler::emit_data64(jlong data,
6597 RelocationHolder const& rspec,
6598 int format) {
6599 assert(imm_operand == 0, "default format must be immediate in this file");
6600 assert(imm_operand == format, "must be immediate");
6601 assert(inst_mark() != NULL, "must be inside InstructionMark");
6602 // Do not use AbstractAssembler::relocate, which is not intended for
6603 // embedded words. Instead, relocate to the enclosing instruction.
6604 code_section()->relocate(inst_mark(), rspec, format);
6605 #ifdef ASSERT
6606 check_relocation(rspec, format);
6607 #endif
6608 emit_int64(data);
6609 }
6610
6611 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6612 if (reg_enc >= 8) {
6613 prefix(REX_B);
6614 reg_enc -= 8;
6615 } else if (byteinst && reg_enc >= 4) {
6616 prefix(REX);
6617 }
6618 return reg_enc;
6619 }
6620
6621 int Assembler::prefixq_and_encode(int reg_enc) {
6622 if (reg_enc < 8) {
6623 prefix(REX_W);
6624 } else {
6625 prefix(REX_WB);
6626 reg_enc -= 8;
6627 }
6628 return reg_enc;
6629 }
6630
6631 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
6632 if (dst_enc < 8) {
6633 if (src_enc >= 8) {
6634 prefix(REX_B);
6635 src_enc -= 8;
6636 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
6637 prefix(REX);
6638 }
6639 } else {
6640 if (src_enc < 8) {
6641 prefix(REX_R);
6642 } else {
6643 prefix(REX_RB);
6644 src_enc -= 8;
6645 }
6646 dst_enc -= 8;
6647 }
6648 return dst_enc << 3 | src_enc;
6649 }
6650
6651 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6652 if (dst_enc < 8) {
6653 if (src_enc < 8) {
6654 prefix(REX_W);
6655 } else {
6656 prefix(REX_WB);
6657 src_enc -= 8;
6658 }
6659 } else {
6660 if (src_enc < 8) {
6661 prefix(REX_WR);
6662 } else {
6663 prefix(REX_WRB);
6664 src_enc -= 8;
6665 }
6666 dst_enc -= 8;
6667 }
6668 return dst_enc << 3 | src_enc;
6669 }
6670
6671 void Assembler::prefix(Register reg) {
6672 if (reg->encoding() >= 8) {
6673 prefix(REX_B);
6674 }
6675 }
6676
6677 void Assembler::prefix(Register dst, Register src, Prefix p) {
6678 if (src->encoding() >= 8) {
6679 p = (Prefix)(p | REX_B);
6680 }
6681 if (dst->encoding() >= 8) {
6682 p = (Prefix)( p | REX_R);
6683 }
6684 if (p != Prefix_EMPTY) {
6685 // do not generate an empty prefix
6686 prefix(p);
6687 }
6688 }
6689
6690 void Assembler::prefix(Register dst, Address adr, Prefix p) {
6691 if (adr.base_needs_rex()) {
6692 if (adr.index_needs_rex()) {
6693 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6694 } else {
6695 prefix(REX_B);
6696 }
6697 } else {
6698 if (adr.index_needs_rex()) {
6699 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6700 }
6701 }
6702 if (dst->encoding() >= 8) {
6703 p = (Prefix)(p | REX_R);
6704 }
6705 if (p != Prefix_EMPTY) {
6706 // do not generate an empty prefix
6707 prefix(p);
6708 }
6709 }
6710
6711 void Assembler::prefix(Address adr) {
6712 if (adr.base_needs_rex()) {
6713 if (adr.index_needs_rex()) {
6714 prefix(REX_XB);
6715 } else {
6716 prefix(REX_B);
6717 }
6718 } else {
6719 if (adr.index_needs_rex()) {
6720 prefix(REX_X);
6721 }
6722 }
6723 }
6724
6725 void Assembler::prefixq(Address adr) {
6726 if (adr.base_needs_rex()) {
6727 if (adr.index_needs_rex()) {
6728 prefix(REX_WXB);
6729 } else {
6730 prefix(REX_WB);
6731 }
6732 } else {
6733 if (adr.index_needs_rex()) {
6734 prefix(REX_WX);
6735 } else {
6736 prefix(REX_W);
6737 }
6738 }
6739 }
6740
6741
6742 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6743 if (reg->encoding() < 8) {
6744 if (adr.base_needs_rex()) {
6745 if (adr.index_needs_rex()) {
6746 prefix(REX_XB);
6747 } else {
6748 prefix(REX_B);
6749 }
6750 } else {
6751 if (adr.index_needs_rex()) {
6752 prefix(REX_X);
6753 } else if (byteinst && reg->encoding() >= 4 ) {
6754 prefix(REX);
6755 }
6756 }
6757 } else {
6758 if (adr.base_needs_rex()) {
6759 if (adr.index_needs_rex()) {
6760 prefix(REX_RXB);
6761 } else {
6762 prefix(REX_RB);
6763 }
6764 } else {
6765 if (adr.index_needs_rex()) {
6766 prefix(REX_RX);
6767 } else {
6768 prefix(REX_R);
6769 }
6770 }
6771 }
6772 }
6773
6774 void Assembler::prefixq(Address adr, Register src) {
6775 if (src->encoding() < 8) {
6776 if (adr.base_needs_rex()) {
6777 if (adr.index_needs_rex()) {
6778 prefix(REX_WXB);
6779 } else {
6780 prefix(REX_WB);
6781 }
6782 } else {
6783 if (adr.index_needs_rex()) {
6784 prefix(REX_WX);
6785 } else {
6786 prefix(REX_W);
6787 }
6788 }
6789 } else {
6790 if (adr.base_needs_rex()) {
6791 if (adr.index_needs_rex()) {
6792 prefix(REX_WRXB);
6793 } else {
6794 prefix(REX_WRB);
6795 }
6796 } else {
6797 if (adr.index_needs_rex()) {
6798 prefix(REX_WRX);
6799 } else {
6800 prefix(REX_WR);
6801 }
6802 }
6803 }
6804 }
6805
6806 void Assembler::prefix(Address adr, XMMRegister reg) {
6807 if (reg->encoding() < 8) {
6808 if (adr.base_needs_rex()) {
6809 if (adr.index_needs_rex()) {
6810 prefix(REX_XB);
6811 } else {
6812 prefix(REX_B);
6813 }
6814 } else {
6815 if (adr.index_needs_rex()) {
6816 prefix(REX_X);
6817 }
6818 }
6819 } else {
6820 if (adr.base_needs_rex()) {
6821 if (adr.index_needs_rex()) {
6822 prefix(REX_RXB);
6823 } else {
6824 prefix(REX_RB);
6825 }
6826 } else {
6827 if (adr.index_needs_rex()) {
6828 prefix(REX_RX);
6829 } else {
6830 prefix(REX_R);
6831 }
6832 }
6833 }
6834 }
6835
6836 void Assembler::prefixq(Address adr, XMMRegister src) {
6837 if (src->encoding() < 8) {
6838 if (adr.base_needs_rex()) {
6839 if (adr.index_needs_rex()) {
6840 prefix(REX_WXB);
6841 } else {
6842 prefix(REX_WB);
6843 }
6844 } else {
6845 if (adr.index_needs_rex()) {
6846 prefix(REX_WX);
6847 } else {
6848 prefix(REX_W);
6849 }
6850 }
6851 } else {
6852 if (adr.base_needs_rex()) {
6853 if (adr.index_needs_rex()) {
6854 prefix(REX_WRXB);
6855 } else {
6856 prefix(REX_WRB);
6857 }
6858 } else {
6859 if (adr.index_needs_rex()) {
6860 prefix(REX_WRX);
6861 } else {
6862 prefix(REX_WR);
6863 }
6864 }
6865 }
6866 }
6867
6868 void Assembler::adcq(Register dst, int32_t imm32) {
6869 (void) prefixq_and_encode(dst->encoding());
6870 emit_arith(0x81, 0xD0, dst, imm32);
6871 }
6872
6873 void Assembler::adcq(Register dst, Address src) {
6874 InstructionMark im(this);
6875 prefixq(src, dst);
6876 emit_int8(0x13);
6877 emit_operand(dst, src);
6878 }
6879
6880 void Assembler::adcq(Register dst, Register src) {
6881 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6882 emit_arith(0x13, 0xC0, dst, src);
6883 }
6884
6885 void Assembler::addq(Address dst, int32_t imm32) {
6886 InstructionMark im(this);
6887 prefixq(dst);
6888 emit_arith_operand(0x81, rax, dst,imm32);
6889 }
6890
6891 void Assembler::addq(Address dst, Register src) {
6892 InstructionMark im(this);
6893 prefixq(dst, src);
6894 emit_int8(0x01);
6895 emit_operand(src, dst);
6896 }
6897
6898 void Assembler::addq(Register dst, int32_t imm32) {
6899 (void) prefixq_and_encode(dst->encoding());
6900 emit_arith(0x81, 0xC0, dst, imm32);
6901 }
6902
6903 void Assembler::addq(Register dst, Address src) {
6904 InstructionMark im(this);
6905 prefixq(src, dst);
6906 emit_int8(0x03);
6907 emit_operand(dst, src);
6908 }
6909
6910 void Assembler::addq(Register dst, Register src) {
6911 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6912 emit_arith(0x03, 0xC0, dst, src);
6913 }
6914
6915 void Assembler::adcxq(Register dst, Register src) {
6916 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6917 emit_int8((unsigned char)0x66);
6918 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6919 emit_int8(0x0F);
6920 emit_int8(0x38);
6921 emit_int8((unsigned char)0xF6);
6922 emit_int8((unsigned char)(0xC0 | encode));
6923 }
6924
6925 void Assembler::adoxq(Register dst, Register src) {
6926 //assert(VM_Version::supports_adx(), "adx instructions not supported");
6927 emit_int8((unsigned char)0xF3);
6928 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6929 emit_int8(0x0F);
6930 emit_int8(0x38);
6931 emit_int8((unsigned char)0xF6);
6932 emit_int8((unsigned char)(0xC0 | encode));
6933 }
6934
6935 void Assembler::andq(Address dst, int32_t imm32) {
6936 InstructionMark im(this);
6937 prefixq(dst);
6938 emit_int8((unsigned char)0x81);
6939 emit_operand(rsp, dst, 4);
6940 emit_int32(imm32);
6941 }
6942
6943 void Assembler::andq(Register dst, int32_t imm32) {
6944 (void) prefixq_and_encode(dst->encoding());
6945 emit_arith(0x81, 0xE0, dst, imm32);
6946 }
6947
6948 void Assembler::andq(Register dst, Address src) {
6949 InstructionMark im(this);
6950 prefixq(src, dst);
6951 emit_int8(0x23);
6952 emit_operand(dst, src);
6953 }
6954
6955 void Assembler::andq(Register dst, Register src) {
6956 (void) prefixq_and_encode(dst->encoding(), src->encoding());
6957 emit_arith(0x23, 0xC0, dst, src);
6958 }
6959
6960 void Assembler::andnq(Register dst, Register src1, Register src2) {
6961 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6962 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6963 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6964 emit_int8((unsigned char)0xF2);
6965 emit_int8((unsigned char)(0xC0 | encode));
6966 }
6967
6968 void Assembler::andnq(Register dst, Register src1, Address src2) {
6969 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6970 InstructionMark im(this);
6971 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6972 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
6973 emit_int8((unsigned char)0xF2);
6974 emit_operand(dst, src2);
6975 }
6976
6977 void Assembler::bsfq(Register dst, Register src) {
6978 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6979 emit_int8(0x0F);
6980 emit_int8((unsigned char)0xBC);
6981 emit_int8((unsigned char)(0xC0 | encode));
6982 }
6983
6984 void Assembler::bsrq(Register dst, Register src) {
6985 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6986 emit_int8(0x0F);
6987 emit_int8((unsigned char)0xBD);
6988 emit_int8((unsigned char)(0xC0 | encode));
6989 }
6990
6991 void Assembler::bswapq(Register reg) {
6992 int encode = prefixq_and_encode(reg->encoding());
6993 emit_int8(0x0F);
6994 emit_int8((unsigned char)(0xC8 | encode));
6995 }
6996
6997 void Assembler::blsiq(Register dst, Register src) {
6998 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
6999 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7000 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7001 emit_int8((unsigned char)0xF3);
7002 emit_int8((unsigned char)(0xC0 | encode));
7003 }
7004
7005 void Assembler::blsiq(Register dst, Address src) {
7006 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7007 InstructionMark im(this);
7008 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7009 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7010 emit_int8((unsigned char)0xF3);
7011 emit_operand(rbx, src);
7012 }
7013
7014 void Assembler::blsmskq(Register dst, Register src) {
7015 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7016 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7017 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7018 emit_int8((unsigned char)0xF3);
7019 emit_int8((unsigned char)(0xC0 | encode));
7020 }
7021
7022 void Assembler::blsmskq(Register dst, Address src) {
7023 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7024 InstructionMark im(this);
7025 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7026 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7027 emit_int8((unsigned char)0xF3);
7028 emit_operand(rdx, src);
7029 }
7030
7031 void Assembler::blsrq(Register dst, Register src) {
7032 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7033 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7034 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7035 emit_int8((unsigned char)0xF3);
7036 emit_int8((unsigned char)(0xC0 | encode));
7037 }
7038
7039 void Assembler::blsrq(Register dst, Address src) {
7040 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7041 InstructionMark im(this);
7042 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7043 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7044 emit_int8((unsigned char)0xF3);
7045 emit_operand(rcx, src);
7046 }
7047
7048 void Assembler::cdqq() {
7049 prefix(REX_W);
7050 emit_int8((unsigned char)0x99);
7051 }
7052
7053 void Assembler::clflush(Address adr) {
7054 prefix(adr);
7055 emit_int8(0x0F);
7056 emit_int8((unsigned char)0xAE);
7057 emit_operand(rdi, adr);
7058 }
7059
7060 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7061 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7062 emit_int8(0x0F);
7063 emit_int8(0x40 | cc);
7064 emit_int8((unsigned char)(0xC0 | encode));
7065 }
7066
7067 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7068 InstructionMark im(this);
7069 prefixq(src, dst);
7070 emit_int8(0x0F);
7071 emit_int8(0x40 | cc);
7072 emit_operand(dst, src);
7073 }
7074
7075 void Assembler::cmpq(Address dst, int32_t imm32) {
7076 InstructionMark im(this);
7077 prefixq(dst);
7078 emit_int8((unsigned char)0x81);
7079 emit_operand(rdi, dst, 4);
7080 emit_int32(imm32);
7081 }
7082
7083 void Assembler::cmpq(Register dst, int32_t imm32) {
7084 (void) prefixq_and_encode(dst->encoding());
7085 emit_arith(0x81, 0xF8, dst, imm32);
7086 }
7087
7088 void Assembler::cmpq(Address dst, Register src) {
7089 InstructionMark im(this);
7090 prefixq(dst, src);
7091 emit_int8(0x3B);
7092 emit_operand(src, dst);
7093 }
7094
7095 void Assembler::cmpq(Register dst, Register src) {
7096 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7097 emit_arith(0x3B, 0xC0, dst, src);
7098 }
7099
7100 void Assembler::cmpq(Register dst, Address src) {
7101 InstructionMark im(this);
7102 prefixq(src, dst);
7103 emit_int8(0x3B);
7104 emit_operand(dst, src);
7105 }
7106
7107 void Assembler::cmpxchgq(Register reg, Address adr) {
7108 InstructionMark im(this);
7109 prefixq(adr, reg);
7110 emit_int8(0x0F);
7111 emit_int8((unsigned char)0xB1);
7112 emit_operand(reg, adr);
7113 }
7114
7115 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7116 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7117 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7118 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7119 emit_int8(0x2A);
7120 emit_int8((unsigned char)(0xC0 | encode));
7121 }
7122
7123 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7124 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7125 InstructionMark im(this);
7126 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7127 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7128 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7129 emit_int8(0x2A);
7130 emit_operand(dst, src);
7131 }
7132
7133 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7134 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7135 InstructionMark im(this);
7136 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7137 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7138 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7139 emit_int8(0x2A);
7140 emit_operand(dst, src);
7141 }
7142
7143 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7144 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7145 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7146 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7147 emit_int8(0x2C);
7148 emit_int8((unsigned char)(0xC0 | encode));
7149 }
7150
7151 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7152 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7153 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7154 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7155 emit_int8(0x2C);
7156 emit_int8((unsigned char)(0xC0 | encode));
7157 }
7158
7159 void Assembler::decl(Register dst) {
7160 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7161 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7162 int encode = prefix_and_encode(dst->encoding());
7163 emit_int8((unsigned char)0xFF);
7164 emit_int8((unsigned char)(0xC8 | encode));
7165 }
7166
7167 void Assembler::decq(Register dst) {
7168 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7169 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7170 int encode = prefixq_and_encode(dst->encoding());
7171 emit_int8((unsigned char)0xFF);
7172 emit_int8(0xC8 | encode);
7173 }
7174
7175 void Assembler::decq(Address dst) {
7176 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7177 InstructionMark im(this);
7178 prefixq(dst);
7179 emit_int8((unsigned char)0xFF);
7180 emit_operand(rcx, dst);
7181 }
7182
7183 void Assembler::fxrstor(Address src) {
7184 prefixq(src);
7185 emit_int8(0x0F);
7186 emit_int8((unsigned char)0xAE);
7187 emit_operand(as_Register(1), src);
7188 }
7189
7190 void Assembler::xrstor(Address src) {
7191 prefixq(src);
7192 emit_int8(0x0F);
7193 emit_int8((unsigned char)0xAE);
7194 emit_operand(as_Register(5), src);
7195 }
7196
7197 void Assembler::fxsave(Address dst) {
7198 prefixq(dst);
7199 emit_int8(0x0F);
7200 emit_int8((unsigned char)0xAE);
7201 emit_operand(as_Register(0), dst);
7202 }
7203
7204 void Assembler::xsave(Address dst) {
7205 prefixq(dst);
7206 emit_int8(0x0F);
7207 emit_int8((unsigned char)0xAE);
7208 emit_operand(as_Register(4), dst);
7209 }
7210
7211 void Assembler::idivq(Register src) {
7212 int encode = prefixq_and_encode(src->encoding());
7213 emit_int8((unsigned char)0xF7);
7214 emit_int8((unsigned char)(0xF8 | encode));
7215 }
7216
7217 void Assembler::imulq(Register dst, Register src) {
7218 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7219 emit_int8(0x0F);
7220 emit_int8((unsigned char)0xAF);
7221 emit_int8((unsigned char)(0xC0 | encode));
7222 }
7223
7224 void Assembler::imulq(Register dst, Register src, int value) {
7225 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7226 if (is8bit(value)) {
7227 emit_int8(0x6B);
7228 emit_int8((unsigned char)(0xC0 | encode));
7229 emit_int8(value & 0xFF);
7230 } else {
7231 emit_int8(0x69);
7232 emit_int8((unsigned char)(0xC0 | encode));
7233 emit_int32(value);
7234 }
7235 }
7236
7237 void Assembler::imulq(Register dst, Address src) {
7238 InstructionMark im(this);
7239 prefixq(src, dst);
7240 emit_int8(0x0F);
7241 emit_int8((unsigned char) 0xAF);
7242 emit_operand(dst, src);
7243 }
7244
7245 void Assembler::incl(Register dst) {
7246 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7247 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7248 int encode = prefix_and_encode(dst->encoding());
7249 emit_int8((unsigned char)0xFF);
7250 emit_int8((unsigned char)(0xC0 | encode));
7251 }
7252
7253 void Assembler::incq(Register dst) {
7254 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7255 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7256 int encode = prefixq_and_encode(dst->encoding());
7257 emit_int8((unsigned char)0xFF);
7258 emit_int8((unsigned char)(0xC0 | encode));
7259 }
7260
7261 void Assembler::incq(Address dst) {
7262 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7263 InstructionMark im(this);
7264 prefixq(dst);
7265 emit_int8((unsigned char)0xFF);
7266 emit_operand(rax, dst);
7267 }
7268
7269 void Assembler::lea(Register dst, Address src) {
7270 leaq(dst, src);
7271 }
7272
7273 void Assembler::leaq(Register dst, Address src) {
7274 InstructionMark im(this);
7275 prefixq(src, dst);
7276 emit_int8((unsigned char)0x8D);
7277 emit_operand(dst, src);
7278 }
7279
7280 void Assembler::mov64(Register dst, int64_t imm64) {
7281 InstructionMark im(this);
7282 int encode = prefixq_and_encode(dst->encoding());
7283 emit_int8((unsigned char)(0xB8 | encode));
7284 emit_int64(imm64);
7285 }
7286
7287 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7288 InstructionMark im(this);
7289 int encode = prefixq_and_encode(dst->encoding());
7290 emit_int8(0xB8 | encode);
7291 emit_data64(imm64, rspec);
7292 }
7293
7294 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7295 InstructionMark im(this);
7296 int encode = prefix_and_encode(dst->encoding());
7297 emit_int8((unsigned char)(0xB8 | encode));
7298 emit_data((int)imm32, rspec, narrow_oop_operand);
7299 }
7300
7301 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7302 InstructionMark im(this);
7303 prefix(dst);
7304 emit_int8((unsigned char)0xC7);
7305 emit_operand(rax, dst, 4);
7306 emit_data((int)imm32, rspec, narrow_oop_operand);
7307 }
7308
7309 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7310 InstructionMark im(this);
7311 int encode = prefix_and_encode(src1->encoding());
7312 emit_int8((unsigned char)0x81);
7313 emit_int8((unsigned char)(0xF8 | encode));
7314 emit_data((int)imm32, rspec, narrow_oop_operand);
7315 }
7316
7317 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7318 InstructionMark im(this);
7319 prefix(src1);
7320 emit_int8((unsigned char)0x81);
7321 emit_operand(rax, src1, 4);
7322 emit_data((int)imm32, rspec, narrow_oop_operand);
7323 }
7324
7325 void Assembler::lzcntq(Register dst, Register src) {
7326 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7327 emit_int8((unsigned char)0xF3);
7328 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7329 emit_int8(0x0F);
7330 emit_int8((unsigned char)0xBD);
7331 emit_int8((unsigned char)(0xC0 | encode));
7332 }
7333
7334 void Assembler::movdq(XMMRegister dst, Register src) {
7335 // table D-1 says MMX/SSE2
7336 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7338 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7339 emit_int8(0x6E);
7340 emit_int8((unsigned char)(0xC0 | encode));
7341 }
7342
7343 void Assembler::movdq(Register dst, XMMRegister src) {
7344 // table D-1 says MMX/SSE2
7345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7346 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7347 // swap src/dst to get correct prefix
7348 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7349 emit_int8(0x7E);
7350 emit_int8((unsigned char)(0xC0 | encode));
7351 }
7352
7353 void Assembler::movq(Register dst, Register src) {
7354 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7355 emit_int8((unsigned char)0x8B);
7356 emit_int8((unsigned char)(0xC0 | encode));
7357 }
7358
7359 void Assembler::movq(Register dst, Address src) {
7360 InstructionMark im(this);
7361 prefixq(src, dst);
7362 emit_int8((unsigned char)0x8B);
7363 emit_operand(dst, src);
7364 }
7365
7366 void Assembler::movq(Address dst, Register src) {
7367 InstructionMark im(this);
7368 prefixq(dst, src);
7369 emit_int8((unsigned char)0x89);
7370 emit_operand(src, dst);
7371 }
7372
7373 void Assembler::movsbq(Register dst, Address src) {
7374 InstructionMark im(this);
7375 prefixq(src, dst);
7376 emit_int8(0x0F);
7377 emit_int8((unsigned char)0xBE);
7378 emit_operand(dst, src);
7379 }
7380
7381 void Assembler::movsbq(Register dst, Register src) {
7382 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7383 emit_int8(0x0F);
7384 emit_int8((unsigned char)0xBE);
7385 emit_int8((unsigned char)(0xC0 | encode));
7386 }
7387
7388 void Assembler::movslq(Register dst, int32_t imm32) {
7389 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
7390 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
7391 // as a result we shouldn't use until tested at runtime...
7392 ShouldNotReachHere();
7393 InstructionMark im(this);
7394 int encode = prefixq_and_encode(dst->encoding());
7395 emit_int8((unsigned char)(0xC7 | encode));
7396 emit_int32(imm32);
7397 }
7398
7399 void Assembler::movslq(Address dst, int32_t imm32) {
7400 assert(is_simm32(imm32), "lost bits");
7401 InstructionMark im(this);
7402 prefixq(dst);
7403 emit_int8((unsigned char)0xC7);
7404 emit_operand(rax, dst, 4);
7405 emit_int32(imm32);
7406 }
7407
7408 void Assembler::movslq(Register dst, Address src) {
7409 InstructionMark im(this);
7410 prefixq(src, dst);
7411 emit_int8(0x63);
7412 emit_operand(dst, src);
7413 }
7414
7415 void Assembler::movslq(Register dst, Register src) {
7416 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7417 emit_int8(0x63);
7418 emit_int8((unsigned char)(0xC0 | encode));
7419 }
7420
7421 void Assembler::movswq(Register dst, Address src) {
7422 InstructionMark im(this);
7423 prefixq(src, dst);
7424 emit_int8(0x0F);
7425 emit_int8((unsigned char)0xBF);
7426 emit_operand(dst, src);
7427 }
7428
7429 void Assembler::movswq(Register dst, Register src) {
7430 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7431 emit_int8((unsigned char)0x0F);
7432 emit_int8((unsigned char)0xBF);
7433 emit_int8((unsigned char)(0xC0 | encode));
7434 }
7435
7436 void Assembler::movzbq(Register dst, Address src) {
7437 InstructionMark im(this);
7438 prefixq(src, dst);
7439 emit_int8((unsigned char)0x0F);
7440 emit_int8((unsigned char)0xB6);
7441 emit_operand(dst, src);
7442 }
7443
7444 void Assembler::movzbq(Register dst, Register src) {
7445 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7446 emit_int8(0x0F);
7447 emit_int8((unsigned char)0xB6);
7448 emit_int8(0xC0 | encode);
7449 }
7450
7451 void Assembler::movzwq(Register dst, Address src) {
7452 InstructionMark im(this);
7453 prefixq(src, dst);
7454 emit_int8((unsigned char)0x0F);
7455 emit_int8((unsigned char)0xB7);
7456 emit_operand(dst, src);
7457 }
7458
7459 void Assembler::movzwq(Register dst, Register src) {
7460 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7461 emit_int8((unsigned char)0x0F);
7462 emit_int8((unsigned char)0xB7);
7463 emit_int8((unsigned char)(0xC0 | encode));
7464 }
7465
7466 void Assembler::mulq(Address src) {
7467 InstructionMark im(this);
7468 prefixq(src);
7469 emit_int8((unsigned char)0xF7);
7470 emit_operand(rsp, src);
7471 }
7472
7473 void Assembler::mulq(Register src) {
7474 int encode = prefixq_and_encode(src->encoding());
7475 emit_int8((unsigned char)0xF7);
7476 emit_int8((unsigned char)(0xE0 | encode));
7477 }
7478
7479 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7480 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7481 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7482 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
7483 emit_int8((unsigned char)0xF6);
7484 emit_int8((unsigned char)(0xC0 | encode));
7485 }
7486
7487 void Assembler::negq(Register dst) {
7488 int encode = prefixq_and_encode(dst->encoding());
7489 emit_int8((unsigned char)0xF7);
7490 emit_int8((unsigned char)(0xD8 | encode));
7491 }
7492
7493 void Assembler::notq(Register dst) {
7494 int encode = prefixq_and_encode(dst->encoding());
7495 emit_int8((unsigned char)0xF7);
7496 emit_int8((unsigned char)(0xD0 | encode));
7497 }
7498
7499 void Assembler::orq(Address dst, int32_t imm32) {
7500 InstructionMark im(this);
7501 prefixq(dst);
7502 emit_int8((unsigned char)0x81);
7503 emit_operand(rcx, dst, 4);
7504 emit_int32(imm32);
7505 }
7506
7507 void Assembler::orq(Register dst, int32_t imm32) {
7508 (void) prefixq_and_encode(dst->encoding());
7509 emit_arith(0x81, 0xC8, dst, imm32);
7510 }
7511
7512 void Assembler::orq(Register dst, Address src) {
7513 InstructionMark im(this);
7514 prefixq(src, dst);
7515 emit_int8(0x0B);
7516 emit_operand(dst, src);
7517 }
7518
7519 void Assembler::orq(Register dst, Register src) {
7520 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7521 emit_arith(0x0B, 0xC0, dst, src);
7522 }
7523
7524 void Assembler::popa() { // 64bit
7525 movq(r15, Address(rsp, 0));
7526 movq(r14, Address(rsp, wordSize));
7527 movq(r13, Address(rsp, 2 * wordSize));
7528 movq(r12, Address(rsp, 3 * wordSize));
7529 movq(r11, Address(rsp, 4 * wordSize));
7530 movq(r10, Address(rsp, 5 * wordSize));
7531 movq(r9, Address(rsp, 6 * wordSize));
7532 movq(r8, Address(rsp, 7 * wordSize));
7533 movq(rdi, Address(rsp, 8 * wordSize));
7534 movq(rsi, Address(rsp, 9 * wordSize));
7535 movq(rbp, Address(rsp, 10 * wordSize));
7536 // skip rsp
7537 movq(rbx, Address(rsp, 12 * wordSize));
7538 movq(rdx, Address(rsp, 13 * wordSize));
7539 movq(rcx, Address(rsp, 14 * wordSize));
7540 movq(rax, Address(rsp, 15 * wordSize));
7541
7542 addq(rsp, 16 * wordSize);
7543 }
7544
7545 void Assembler::popcntq(Register dst, Address src) {
7546 assert(VM_Version::supports_popcnt(), "must support");
7547 InstructionMark im(this);
7548 emit_int8((unsigned char)0xF3);
7549 prefixq(src, dst);
7550 emit_int8((unsigned char)0x0F);
7551 emit_int8((unsigned char)0xB8);
7552 emit_operand(dst, src);
7553 }
7554
7555 void Assembler::popcntq(Register dst, Register src) {
7556 assert(VM_Version::supports_popcnt(), "must support");
7557 emit_int8((unsigned char)0xF3);
7558 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7559 emit_int8((unsigned char)0x0F);
7560 emit_int8((unsigned char)0xB8);
7561 emit_int8((unsigned char)(0xC0 | encode));
7562 }
7563
7564 void Assembler::popq(Address dst) {
7565 InstructionMark im(this);
7566 prefixq(dst);
7567 emit_int8((unsigned char)0x8F);
7568 emit_operand(rax, dst);
7569 }
7570
7571 void Assembler::pusha() { // 64bit
7572 // we have to store original rsp. ABI says that 128 bytes
7573 // below rsp are local scratch.
7574 movq(Address(rsp, -5 * wordSize), rsp);
7575
7576 subq(rsp, 16 * wordSize);
7577
7578 movq(Address(rsp, 15 * wordSize), rax);
7579 movq(Address(rsp, 14 * wordSize), rcx);
7580 movq(Address(rsp, 13 * wordSize), rdx);
7581 movq(Address(rsp, 12 * wordSize), rbx);
7582 // skip rsp
7583 movq(Address(rsp, 10 * wordSize), rbp);
7584 movq(Address(rsp, 9 * wordSize), rsi);
7585 movq(Address(rsp, 8 * wordSize), rdi);
7586 movq(Address(rsp, 7 * wordSize), r8);
7587 movq(Address(rsp, 6 * wordSize), r9);
7588 movq(Address(rsp, 5 * wordSize), r10);
7589 movq(Address(rsp, 4 * wordSize), r11);
7590 movq(Address(rsp, 3 * wordSize), r12);
7591 movq(Address(rsp, 2 * wordSize), r13);
7592 movq(Address(rsp, wordSize), r14);
7593 movq(Address(rsp, 0), r15);
7594 }
7595
7596 void Assembler::pushq(Address src) {
7597 InstructionMark im(this);
7598 prefixq(src);
7599 emit_int8((unsigned char)0xFF);
7600 emit_operand(rsi, src);
7601 }
7602
7603 void Assembler::rclq(Register dst, int imm8) {
7604 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7605 int encode = prefixq_and_encode(dst->encoding());
7606 if (imm8 == 1) {
7607 emit_int8((unsigned char)0xD1);
7608 emit_int8((unsigned char)(0xD0 | encode));
7609 } else {
7610 emit_int8((unsigned char)0xC1);
7611 emit_int8((unsigned char)(0xD0 | encode));
7612 emit_int8(imm8);
7613 }
7614 }
7615
7616 void Assembler::rcrq(Register dst, int imm8) {
7617 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7618 int encode = prefixq_and_encode(dst->encoding());
7619 if (imm8 == 1) {
7620 emit_int8((unsigned char)0xD1);
7621 emit_int8((unsigned char)(0xD8 | encode));
7622 } else {
7623 emit_int8((unsigned char)0xC1);
7624 emit_int8((unsigned char)(0xD8 | encode));
7625 emit_int8(imm8);
7626 }
7627 }
7628
7629 void Assembler::rorq(Register dst, int imm8) {
7630 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7631 int encode = prefixq_and_encode(dst->encoding());
7632 if (imm8 == 1) {
7633 emit_int8((unsigned char)0xD1);
7634 emit_int8((unsigned char)(0xC8 | encode));
7635 } else {
7636 emit_int8((unsigned char)0xC1);
7637 emit_int8((unsigned char)(0xc8 | encode));
7638 emit_int8(imm8);
7639 }
7640 }
7641
7642 void Assembler::rorxq(Register dst, Register src, int imm8) {
7643 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7644 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7645 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
7646 emit_int8((unsigned char)0xF0);
7647 emit_int8((unsigned char)(0xC0 | encode));
7648 emit_int8(imm8);
7649 }
7650
7651 void Assembler::sarq(Register dst, int imm8) {
7652 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7653 int encode = prefixq_and_encode(dst->encoding());
7654 if (imm8 == 1) {
7655 emit_int8((unsigned char)0xD1);
7656 emit_int8((unsigned char)(0xF8 | encode));
7657 } else {
7658 emit_int8((unsigned char)0xC1);
7659 emit_int8((unsigned char)(0xF8 | encode));
7660 emit_int8(imm8);
7661 }
7662 }
7663
7664 void Assembler::sarq(Register dst) {
7665 int encode = prefixq_and_encode(dst->encoding());
7666 emit_int8((unsigned char)0xD3);
7667 emit_int8((unsigned char)(0xF8 | encode));
7668 }
7669
7670 void Assembler::sbbq(Address dst, int32_t imm32) {
7671 InstructionMark im(this);
7672 prefixq(dst);
7673 emit_arith_operand(0x81, rbx, dst, imm32);
7674 }
7675
7676 void Assembler::sbbq(Register dst, int32_t imm32) {
7677 (void) prefixq_and_encode(dst->encoding());
7678 emit_arith(0x81, 0xD8, dst, imm32);
7679 }
7680
7681 void Assembler::sbbq(Register dst, Address src) {
7682 InstructionMark im(this);
7683 prefixq(src, dst);
7684 emit_int8(0x1B);
7685 emit_operand(dst, src);
7686 }
7687
7688 void Assembler::sbbq(Register dst, Register src) {
7689 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7690 emit_arith(0x1B, 0xC0, dst, src);
7691 }
7692
7693 void Assembler::shlq(Register dst, int imm8) {
7694 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7695 int encode = prefixq_and_encode(dst->encoding());
7696 if (imm8 == 1) {
7697 emit_int8((unsigned char)0xD1);
7698 emit_int8((unsigned char)(0xE0 | encode));
7699 } else {
7700 emit_int8((unsigned char)0xC1);
7701 emit_int8((unsigned char)(0xE0 | encode));
7702 emit_int8(imm8);
7703 }
7704 }
7705
7706 void Assembler::shlq(Register dst) {
7707 int encode = prefixq_and_encode(dst->encoding());
7708 emit_int8((unsigned char)0xD3);
7709 emit_int8((unsigned char)(0xE0 | encode));
7710 }
7711
7712 void Assembler::shrq(Register dst, int imm8) {
7713 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7714 int encode = prefixq_and_encode(dst->encoding());
7715 emit_int8((unsigned char)0xC1);
7716 emit_int8((unsigned char)(0xE8 | encode));
7717 emit_int8(imm8);
7718 }
7719
7720 void Assembler::shrq(Register dst) {
7721 int encode = prefixq_and_encode(dst->encoding());
7722 emit_int8((unsigned char)0xD3);
7723 emit_int8(0xE8 | encode);
7724 }
7725
7726 void Assembler::subq(Address dst, int32_t imm32) {
7727 InstructionMark im(this);
7728 prefixq(dst);
7729 emit_arith_operand(0x81, rbp, dst, imm32);
7730 }
7731
7732 void Assembler::subq(Address dst, Register src) {
7733 InstructionMark im(this);
7734 prefixq(dst, src);
7735 emit_int8(0x29);
7736 emit_operand(src, dst);
7737 }
7738
7739 void Assembler::subq(Register dst, int32_t imm32) {
7740 (void) prefixq_and_encode(dst->encoding());
7741 emit_arith(0x81, 0xE8, dst, imm32);
7742 }
7743
7744 // Force generation of a 4 byte immediate value even if it fits into 8bit
7745 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7746 (void) prefixq_and_encode(dst->encoding());
7747 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7748 }
7749
7750 void Assembler::subq(Register dst, Address src) {
7751 InstructionMark im(this);
7752 prefixq(src, dst);
7753 emit_int8(0x2B);
7754 emit_operand(dst, src);
7755 }
7756
7757 void Assembler::subq(Register dst, Register src) {
7758 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7759 emit_arith(0x2B, 0xC0, dst, src);
7760 }
7761
7762 void Assembler::testq(Register dst, int32_t imm32) {
7763 // not using emit_arith because test
7764 // doesn't support sign-extension of
7765 // 8bit operands
7766 int encode = dst->encoding();
7767 if (encode == 0) {
7768 prefix(REX_W);
7769 emit_int8((unsigned char)0xA9);
7770 } else {
7771 encode = prefixq_and_encode(encode);
7772 emit_int8((unsigned char)0xF7);
7773 emit_int8((unsigned char)(0xC0 | encode));
7774 }
7775 emit_int32(imm32);
7776 }
7777
7778 void Assembler::testq(Register dst, Register src) {
7779 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7780 emit_arith(0x85, 0xC0, dst, src);
7781 }
7782
7783 void Assembler::xaddq(Address dst, Register src) {
7784 InstructionMark im(this);
7785 prefixq(dst, src);
7786 emit_int8(0x0F);
7787 emit_int8((unsigned char)0xC1);
7788 emit_operand(src, dst);
7789 }
7790
7791 void Assembler::xchgq(Register dst, Address src) {
7792 InstructionMark im(this);
7793 prefixq(src, dst);
7794 emit_int8((unsigned char)0x87);
7795 emit_operand(dst, src);
7796 }
7797
7798 void Assembler::xchgq(Register dst, Register src) {
7799 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7800 emit_int8((unsigned char)0x87);
7801 emit_int8((unsigned char)(0xc0 | encode));
7802 }
7803
7804 void Assembler::xorq(Register dst, Register src) {
7805 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7806 emit_arith(0x33, 0xC0, dst, src);
7807 }
7808
7809 void Assembler::xorq(Register dst, Address src) {
7810 InstructionMark im(this);
7811 prefixq(src, dst);
7812 emit_int8(0x33);
7813 emit_operand(dst, src);
7814 }
7815
7816 #endif // !LP64