1 /*
2 * Copyright (c) 2000, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_InstructionPrinter.hpp"
27 #include "c1/c1_LIR.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_ValueStack.hpp"
30 #include "ci/ciInstance.hpp"
31 #include "runtime/sharedRuntime.hpp"
32
33 Register LIR_OprDesc::as_register() const {
34 return FrameMap::cpu_rnr2reg(cpu_regnr());
35 }
36
37 Register LIR_OprDesc::as_register_lo() const {
38 return FrameMap::cpu_rnr2reg(cpu_regnrLo());
39 }
40
41 Register LIR_OprDesc::as_register_hi() const {
42 return FrameMap::cpu_rnr2reg(cpu_regnrHi());
43 }
44
45 #if defined(X86)
46
47 XMMRegister LIR_OprDesc::as_xmm_float_reg() const {
48 return FrameMap::nr2xmmreg(xmm_regnr());
49 }
50
51 XMMRegister LIR_OprDesc::as_xmm_double_reg() const {
52 assert(xmm_regnrLo() == xmm_regnrHi(), "assumed in calculation");
53 return FrameMap::nr2xmmreg(xmm_regnrLo());
54 }
55
56 #endif // X86
57
58 #if defined(SPARC) || defined(PPC)
59
60 FloatRegister LIR_OprDesc::as_float_reg() const {
61 return FrameMap::nr2floatreg(fpu_regnr());
62 }
63
64 FloatRegister LIR_OprDesc::as_double_reg() const {
65 return FrameMap::nr2floatreg(fpu_regnrHi());
66 }
67
68 #endif
69
70 #if defined(ARM) || defined (AARCH64)
71
72 FloatRegister LIR_OprDesc::as_float_reg() const {
73 return as_FloatRegister(fpu_regnr());
74 }
75
76 FloatRegister LIR_OprDesc::as_double_reg() const {
77 return as_FloatRegister(fpu_regnrLo());
78 }
79
80 #endif
81
82
83 LIR_Opr LIR_OprFact::illegalOpr = LIR_OprFact::illegal();
84
85 LIR_Opr LIR_OprFact::value_type(ValueType* type) {
86 ValueTag tag = type->tag();
87 switch (tag) {
88 case metaDataTag : {
89 ClassConstant* c = type->as_ClassConstant();
90 if (c != NULL && !c->value()->is_loaded()) {
91 return LIR_OprFact::metadataConst(NULL);
92 } else if (c != NULL) {
93 return LIR_OprFact::metadataConst(c->value()->constant_encoding());
94 } else {
95 MethodConstant* m = type->as_MethodConstant();
96 assert (m != NULL, "not a class or a method?");
97 return LIR_OprFact::metadataConst(m->value()->constant_encoding());
98 }
99 }
100 case objectTag : {
101 return LIR_OprFact::oopConst(type->as_ObjectType()->encoding());
102 }
103 case addressTag: return LIR_OprFact::addressConst(type->as_AddressConstant()->value());
104 case intTag : return LIR_OprFact::intConst(type->as_IntConstant()->value());
105 case floatTag : return LIR_OprFact::floatConst(type->as_FloatConstant()->value());
106 case longTag : return LIR_OprFact::longConst(type->as_LongConstant()->value());
107 case doubleTag : return LIR_OprFact::doubleConst(type->as_DoubleConstant()->value());
108 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
109 }
110 }
111
112
113 LIR_Opr LIR_OprFact::dummy_value_type(ValueType* type) {
114 switch (type->tag()) {
115 case objectTag: return LIR_OprFact::oopConst(NULL);
116 case addressTag:return LIR_OprFact::addressConst(0);
117 case intTag: return LIR_OprFact::intConst(0);
118 case floatTag: return LIR_OprFact::floatConst(0.0);
119 case longTag: return LIR_OprFact::longConst(0);
120 case doubleTag: return LIR_OprFact::doubleConst(0.0);
121 default: ShouldNotReachHere(); return LIR_OprFact::intConst(-1);
122 }
123 return illegalOpr;
124 }
125
126
127
128 //---------------------------------------------------
129
130
131 LIR_Address::Scale LIR_Address::scale(BasicType type) {
132 int elem_size = type2aelembytes(type);
133 switch (elem_size) {
134 case 1: return LIR_Address::times_1;
135 case 2: return LIR_Address::times_2;
136 case 4: return LIR_Address::times_4;
137 case 8: return LIR_Address::times_8;
138 }
139 ShouldNotReachHere();
140 return LIR_Address::times_1;
141 }
142
143
144 #ifndef PRODUCT
145 void LIR_Address::verify0() const {
146 #if defined(SPARC) || defined(PPC)
147 assert(scale() == times_1, "Scaled addressing mode not available on SPARC/PPC and should not be used");
148 assert(disp() == 0 || index()->is_illegal(), "can't have both");
149 #endif
150 #ifdef _LP64
151 assert(base()->is_cpu_register(), "wrong base operand");
152 #ifndef AARCH64
153 assert(index()->is_illegal() || index()->is_double_cpu(), "wrong index operand");
154 #else
155 assert(index()->is_illegal() || index()->is_double_cpu() || index()->is_single_cpu(), "wrong index operand");
156 #endif
157 assert(base()->type() == T_OBJECT || base()->type() == T_LONG || base()->type() == T_METADATA,
158 "wrong type for addresses");
159 #else
160 assert(base()->is_single_cpu(), "wrong base operand");
161 assert(index()->is_illegal() || index()->is_single_cpu(), "wrong index operand");
162 assert(base()->type() == T_OBJECT || base()->type() == T_INT || base()->type() == T_METADATA,
163 "wrong type for addresses");
164 #endif
165 }
166 #endif
167
168
169 //---------------------------------------------------
170
171 char LIR_OprDesc::type_char(BasicType t) {
172 switch (t) {
173 case T_ARRAY:
174 t = T_OBJECT;
175 case T_BOOLEAN:
176 case T_CHAR:
177 case T_FLOAT:
178 case T_DOUBLE:
179 case T_BYTE:
180 case T_SHORT:
181 case T_INT:
182 case T_LONG:
183 case T_OBJECT:
184 case T_ADDRESS:
185 case T_VOID:
186 return ::type2char(t);
187 case T_METADATA:
188 return 'M';
189 case T_ILLEGAL:
190 return '?';
191
192 default:
193 ShouldNotReachHere();
194 return '?';
195 }
196 }
197
198 #ifndef PRODUCT
199 void LIR_OprDesc::validate_type() const {
200
201 #ifdef ASSERT
202 if (!is_pointer() && !is_illegal()) {
203 OprKind kindfield = kind_field(); // Factored out because of compiler bug, see 8002160
204 switch (as_BasicType(type_field())) {
205 case T_LONG:
206 assert((kindfield == cpu_register || kindfield == stack_value) &&
207 size_field() == double_size, "must match");
208 break;
209 case T_FLOAT:
210 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
211 assert((kindfield == fpu_register || kindfield == stack_value
212 ARM_ONLY(|| kindfield == cpu_register)
213 PPC_ONLY(|| kindfield == cpu_register) ) &&
214 size_field() == single_size, "must match");
215 break;
216 case T_DOUBLE:
217 // FP return values can be also in CPU registers on ARM and PPC (softfp ABI)
218 assert((kindfield == fpu_register || kindfield == stack_value
219 ARM_ONLY(|| kindfield == cpu_register)
220 PPC_ONLY(|| kindfield == cpu_register) ) &&
221 size_field() == double_size, "must match");
222 break;
223 case T_BOOLEAN:
224 case T_CHAR:
225 case T_BYTE:
226 case T_SHORT:
227 case T_INT:
228 case T_ADDRESS:
229 case T_OBJECT:
230 case T_METADATA:
231 case T_ARRAY:
232 assert((kindfield == cpu_register || kindfield == stack_value) &&
233 size_field() == single_size, "must match");
234 break;
235
236 case T_ILLEGAL:
237 // XXX TKR also means unknown right now
238 // assert(is_illegal(), "must match");
239 break;
240
241 default:
242 ShouldNotReachHere();
243 }
244 }
245 #endif
246
247 }
248 #endif // PRODUCT
249
250
251 bool LIR_OprDesc::is_oop() const {
252 if (is_pointer()) {
253 return pointer()->is_oop_pointer();
254 } else {
255 OprType t= type_field();
256 assert(t != unknown_type, "not set");
257 return t == object_type;
258 }
259 }
260
261
262
263 void LIR_Op2::verify() const {
264 #ifdef ASSERT
265 switch (code()) {
266 case lir_cmove:
267 case lir_xchg:
268 break;
269
270 default:
271 assert(!result_opr()->is_register() || !result_opr()->is_oop_register(),
272 "can't produce oops from arith");
273 }
274
275 if (TwoOperandLIRForm) {
276 switch (code()) {
277 case lir_add:
278 case lir_sub:
279 case lir_mul:
280 case lir_mul_strictfp:
281 case lir_div:
282 case lir_div_strictfp:
283 case lir_rem:
284 case lir_logic_and:
285 case lir_logic_or:
286 case lir_logic_xor:
287 case lir_shl:
288 case lir_shr:
289 assert(in_opr1() == result_opr(), "opr1 and result must match");
290 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
291 break;
292
293 // special handling for lir_ushr because of write barriers
294 case lir_ushr:
295 assert(in_opr1() == result_opr() || in_opr2()->is_constant(), "opr1 and result must match or shift count is constant");
296 assert(in_opr1()->is_valid() && in_opr2()->is_valid(), "must be valid");
297 break;
298
299 }
300 }
301 #endif
302 }
303
304
305 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block)
306 : LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
307 , _cond(cond)
308 , _type(type)
309 , _label(block->label())
310 , _block(block)
311 , _ublock(NULL)
312 , _stub(NULL) {
313 }
314
315 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, CodeStub* stub) :
316 LIR_Op(lir_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
317 , _cond(cond)
318 , _type(type)
319 , _label(stub->entry())
320 , _block(NULL)
321 , _ublock(NULL)
322 , _stub(stub) {
323 }
324
325 LIR_OpBranch::LIR_OpBranch(LIR_Condition cond, BasicType type, BlockBegin* block, BlockBegin* ublock)
326 : LIR_Op(lir_cond_float_branch, LIR_OprFact::illegalOpr, (CodeEmitInfo*)NULL)
327 , _cond(cond)
328 , _type(type)
329 , _label(block->label())
330 , _block(block)
331 , _ublock(ublock)
332 , _stub(NULL)
333 {
334 }
335
336 void LIR_OpBranch::change_block(BlockBegin* b) {
337 assert(_block != NULL, "must have old block");
338 assert(_block->label() == label(), "must be equal");
339
340 _block = b;
341 _label = b->label();
342 }
343
344 void LIR_OpBranch::change_ublock(BlockBegin* b) {
345 assert(_ublock != NULL, "must have old block");
346 _ublock = b;
347 }
348
349 void LIR_OpBranch::negate_cond() {
350 switch (_cond) {
351 case lir_cond_equal: _cond = lir_cond_notEqual; break;
352 case lir_cond_notEqual: _cond = lir_cond_equal; break;
353 case lir_cond_less: _cond = lir_cond_greaterEqual; break;
354 case lir_cond_lessEqual: _cond = lir_cond_greater; break;
355 case lir_cond_greaterEqual: _cond = lir_cond_less; break;
356 case lir_cond_greater: _cond = lir_cond_lessEqual; break;
357 default: ShouldNotReachHere();
358 }
359 }
360
361
362 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr result, LIR_Opr object, ciKlass* klass,
363 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
364 bool fast_check, CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch,
365 CodeStub* stub)
366
367 : LIR_Op(code, result, NULL)
368 , _object(object)
369 , _array(LIR_OprFact::illegalOpr)
370 , _klass(klass)
371 , _tmp1(tmp1)
372 , _tmp2(tmp2)
373 , _tmp3(tmp3)
374 , _fast_check(fast_check)
375 , _stub(stub)
376 , _info_for_patch(info_for_patch)
377 , _info_for_exception(info_for_exception)
378 , _profiled_method(NULL)
379 , _profiled_bci(-1)
380 , _should_profile(false)
381 {
382 if (code == lir_checkcast) {
383 assert(info_for_exception != NULL, "checkcast throws exceptions");
384 } else if (code == lir_instanceof) {
385 assert(info_for_exception == NULL, "instanceof throws no exceptions");
386 } else {
387 ShouldNotReachHere();
388 }
389 }
390
391
392
393 LIR_OpTypeCheck::LIR_OpTypeCheck(LIR_Code code, LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, CodeEmitInfo* info_for_exception)
394 : LIR_Op(code, LIR_OprFact::illegalOpr, NULL)
395 , _object(object)
396 , _array(array)
397 , _klass(NULL)
398 , _tmp1(tmp1)
399 , _tmp2(tmp2)
400 , _tmp3(tmp3)
401 , _fast_check(false)
402 , _stub(NULL)
403 , _info_for_patch(NULL)
404 , _info_for_exception(info_for_exception)
405 , _profiled_method(NULL)
406 , _profiled_bci(-1)
407 , _should_profile(false)
408 {
409 if (code == lir_store_check) {
410 _stub = new ArrayStoreExceptionStub(object, info_for_exception);
411 assert(info_for_exception != NULL, "store_check throws exceptions");
412 } else {
413 ShouldNotReachHere();
414 }
415 }
416
417
418 LIR_OpArrayCopy::LIR_OpArrayCopy(LIR_Opr src, LIR_Opr src_pos, LIR_Opr dst, LIR_Opr dst_pos, LIR_Opr length,
419 LIR_Opr tmp, ciArrayKlass* expected_type, int flags, CodeEmitInfo* info)
420 : LIR_Op(lir_arraycopy, LIR_OprFact::illegalOpr, info)
421 , _tmp(tmp)
422 , _src(src)
423 , _src_pos(src_pos)
424 , _dst(dst)
425 , _dst_pos(dst_pos)
426 , _flags(flags)
427 , _expected_type(expected_type)
428 , _length(length) {
429 _stub = new ArrayCopyStub(this);
430 }
431
432 LIR_OpUpdateCRC32::LIR_OpUpdateCRC32(LIR_Opr crc, LIR_Opr val, LIR_Opr res)
433 : LIR_Op(lir_updatecrc32, res, NULL)
434 , _crc(crc)
435 , _val(val) {
436 }
437
438 //-------------------verify--------------------------
439
440 void LIR_Op1::verify() const {
441 switch(code()) {
442 case lir_move:
443 assert(in_opr()->is_valid() && result_opr()->is_valid(), "must be");
444 break;
445 case lir_null_check:
446 assert(in_opr()->is_register(), "must be");
447 break;
448 case lir_return:
449 assert(in_opr()->is_register() || in_opr()->is_illegal(), "must be");
450 break;
451 }
452 }
453
454 void LIR_OpRTCall::verify() const {
455 assert(strcmp(Runtime1::name_for_address(addr()), "<unknown function>") != 0, "unknown function");
456 }
457
458 //-------------------visits--------------------------
459
460 // complete rework of LIR instruction visitor.
461 // The virtual call for each instruction type is replaced by a big
462 // switch that adds the operands for each instruction
463
464 void LIR_OpVisitState::visit(LIR_Op* op) {
465 // copy information from the LIR_Op
466 reset();
467 set_op(op);
468
469 switch (op->code()) {
470
471 // LIR_Op0
472 case lir_word_align: // result and info always invalid
473 case lir_backwardbranch_target: // result and info always invalid
474 case lir_build_frame: // result and info always invalid
475 case lir_fpop_raw: // result and info always invalid
476 case lir_24bit_FPU: // result and info always invalid
477 case lir_reset_FPU: // result and info always invalid
478 case lir_breakpoint: // result and info always invalid
479 case lir_membar: // result and info always invalid
480 case lir_membar_acquire: // result and info always invalid
481 case lir_membar_release: // result and info always invalid
482 case lir_membar_loadload: // result and info always invalid
483 case lir_membar_storestore: // result and info always invalid
484 case lir_membar_loadstore: // result and info always invalid
485 case lir_membar_storeload: // result and info always invalid
486 {
487 assert(op->as_Op0() != NULL, "must be");
488 assert(op->_info == NULL, "info not used by this instruction");
489 assert(op->_result->is_illegal(), "not used");
490 break;
491 }
492
493 case lir_nop: // may have info, result always invalid
494 case lir_std_entry: // may have result, info always invalid
495 case lir_osr_entry: // may have result, info always invalid
496 case lir_get_thread: // may have result, info always invalid
497 {
498 assert(op->as_Op0() != NULL, "must be");
499 if (op->_info != NULL) do_info(op->_info);
500 if (op->_result->is_valid()) do_output(op->_result);
501 break;
502 }
503
504
505 // LIR_OpLabel
506 case lir_label: // result and info always invalid
507 {
508 assert(op->as_OpLabel() != NULL, "must be");
509 assert(op->_info == NULL, "info not used by this instruction");
510 assert(op->_result->is_illegal(), "not used");
511 break;
512 }
513
514
515 // LIR_Op1
516 case lir_fxch: // input always valid, result and info always invalid
517 case lir_fld: // input always valid, result and info always invalid
518 case lir_ffree: // input always valid, result and info always invalid
519 case lir_push: // input always valid, result and info always invalid
520 case lir_pop: // input always valid, result and info always invalid
521 case lir_return: // input always valid, result and info always invalid
522 case lir_leal: // input and result always valid, info always invalid
523 case lir_neg: // input and result always valid, info always invalid
524 case lir_monaddr: // input and result always valid, info always invalid
525 case lir_null_check: // input and info always valid, result always invalid
526 case lir_move: // input and result always valid, may have info
527 case lir_pack64: // input and result always valid
528 case lir_unpack64: // input and result always valid
529 {
530 assert(op->as_Op1() != NULL, "must be");
531 LIR_Op1* op1 = (LIR_Op1*)op;
532
533 if (op1->_info) do_info(op1->_info);
534 if (op1->_opr->is_valid()) do_input(op1->_opr);
535 if (op1->_result->is_valid()) do_output(op1->_result);
536
537 break;
538 }
539
540 case lir_safepoint:
541 {
542 assert(op->as_Op1() != NULL, "must be");
543 LIR_Op1* op1 = (LIR_Op1*)op;
544
545 assert(op1->_info != NULL, ""); do_info(op1->_info);
546 if (op1->_opr->is_valid()) do_temp(op1->_opr); // safepoints on SPARC need temporary register
547 assert(op1->_result->is_illegal(), "safepoint does not produce value");
548
549 break;
550 }
551
552 // LIR_OpConvert;
553 case lir_convert: // input and result always valid, info always invalid
554 {
555 assert(op->as_OpConvert() != NULL, "must be");
556 LIR_OpConvert* opConvert = (LIR_OpConvert*)op;
557
558 assert(opConvert->_info == NULL, "must be");
559 if (opConvert->_opr->is_valid()) do_input(opConvert->_opr);
560 if (opConvert->_result->is_valid()) do_output(opConvert->_result);
561 #ifdef PPC
562 if (opConvert->_tmp1->is_valid()) do_temp(opConvert->_tmp1);
563 if (opConvert->_tmp2->is_valid()) do_temp(opConvert->_tmp2);
564 #endif
565 do_stub(opConvert->_stub);
566
567 break;
568 }
569
570 // LIR_OpBranch;
571 case lir_branch: // may have info, input and result register always invalid
572 case lir_cond_float_branch: // may have info, input and result register always invalid
573 {
574 assert(op->as_OpBranch() != NULL, "must be");
575 LIR_OpBranch* opBranch = (LIR_OpBranch*)op;
576
577 if (opBranch->_info != NULL) do_info(opBranch->_info);
578 assert(opBranch->_result->is_illegal(), "not used");
579 if (opBranch->_stub != NULL) opBranch->stub()->visit(this);
580
581 break;
582 }
583
584
585 // LIR_OpAllocObj
586 case lir_alloc_object:
587 {
588 assert(op->as_OpAllocObj() != NULL, "must be");
589 LIR_OpAllocObj* opAllocObj = (LIR_OpAllocObj*)op;
590
591 if (opAllocObj->_info) do_info(opAllocObj->_info);
592 if (opAllocObj->_opr->is_valid()) { do_input(opAllocObj->_opr);
593 do_temp(opAllocObj->_opr);
594 }
595 if (opAllocObj->_tmp1->is_valid()) do_temp(opAllocObj->_tmp1);
596 if (opAllocObj->_tmp2->is_valid()) do_temp(opAllocObj->_tmp2);
597 if (opAllocObj->_tmp3->is_valid()) do_temp(opAllocObj->_tmp3);
598 if (opAllocObj->_tmp4->is_valid()) do_temp(opAllocObj->_tmp4);
599 if (opAllocObj->_result->is_valid()) do_output(opAllocObj->_result);
600 do_stub(opAllocObj->_stub);
601 break;
602 }
603
604
605 // LIR_OpRoundFP;
606 case lir_roundfp: {
607 assert(op->as_OpRoundFP() != NULL, "must be");
608 LIR_OpRoundFP* opRoundFP = (LIR_OpRoundFP*)op;
609
610 assert(op->_info == NULL, "info not used by this instruction");
611 assert(opRoundFP->_tmp->is_illegal(), "not used");
612 do_input(opRoundFP->_opr);
613 do_output(opRoundFP->_result);
614
615 break;
616 }
617
618
619 // LIR_Op2
620 case lir_cmp:
621 case lir_cmp_l2i:
622 case lir_ucmp_fd2i:
623 case lir_cmp_fd2i:
624 case lir_add:
625 case lir_sub:
626 case lir_mul:
627 case lir_div:
628 case lir_rem:
629 case lir_sqrt:
630 case lir_abs:
631 case lir_logic_and:
632 case lir_logic_or:
633 case lir_logic_xor:
634 case lir_shl:
635 case lir_shr:
636 case lir_ushr:
637 case lir_xadd:
638 case lir_xchg:
639 case lir_assert:
640 {
641 assert(op->as_Op2() != NULL, "must be");
642 LIR_Op2* op2 = (LIR_Op2*)op;
643 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
644 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
645
646 if (op2->_info) do_info(op2->_info);
647 if (op2->_opr1->is_valid()) do_input(op2->_opr1);
648 if (op2->_opr2->is_valid()) do_input(op2->_opr2);
649 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
650 if (op2->_result->is_valid()) do_output(op2->_result);
651 if (op->code() == lir_xchg || op->code() == lir_xadd) {
652 // on ARM and PPC, return value is loaded first so could
653 // destroy inputs. On other platforms that implement those
654 // (x86, sparc), the extra constrainsts are harmless.
655 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
656 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
657 }
658
659 break;
660 }
661
662 // special handling for cmove: right input operand must not be equal
663 // to the result operand, otherwise the backend fails
664 case lir_cmove:
665 {
666 assert(op->as_Op2() != NULL, "must be");
667 LIR_Op2* op2 = (LIR_Op2*)op;
668
669 assert(op2->_info == NULL && op2->_tmp1->is_illegal() && op2->_tmp2->is_illegal() &&
670 op2->_tmp3->is_illegal() && op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
671 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid() && op2->_result->is_valid(), "used");
672
673 do_input(op2->_opr1);
674 do_input(op2->_opr2);
675 do_temp(op2->_opr2);
676 do_output(op2->_result);
677
678 break;
679 }
680
681 // vspecial handling for strict operations: register input operands
682 // as temp to guarantee that they do not overlap with other
683 // registers
684 case lir_mul_strictfp:
685 case lir_div_strictfp:
686 {
687 assert(op->as_Op2() != NULL, "must be");
688 LIR_Op2* op2 = (LIR_Op2*)op;
689
690 assert(op2->_info == NULL, "not used");
691 assert(op2->_opr1->is_valid(), "used");
692 assert(op2->_opr2->is_valid(), "used");
693 assert(op2->_result->is_valid(), "used");
694 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
695 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
696
697 do_input(op2->_opr1); do_temp(op2->_opr1);
698 do_input(op2->_opr2); do_temp(op2->_opr2);
699 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
700 do_output(op2->_result);
701
702 break;
703 }
704
705 case lir_throw: {
706 assert(op->as_Op2() != NULL, "must be");
707 LIR_Op2* op2 = (LIR_Op2*)op;
708
709 if (op2->_info) do_info(op2->_info);
710 if (op2->_opr1->is_valid()) do_temp(op2->_opr1);
711 if (op2->_opr2->is_valid()) do_input(op2->_opr2); // exception object is input parameter
712 assert(op2->_result->is_illegal(), "no result");
713 assert(op2->_tmp2->is_illegal() && op2->_tmp3->is_illegal() &&
714 op2->_tmp4->is_illegal() && op2->_tmp5->is_illegal(), "not used");
715
716 break;
717 }
718
719 case lir_unwind: {
720 assert(op->as_Op1() != NULL, "must be");
721 LIR_Op1* op1 = (LIR_Op1*)op;
722
723 assert(op1->_info == NULL, "no info");
724 assert(op1->_opr->is_valid(), "exception oop"); do_input(op1->_opr);
725 assert(op1->_result->is_illegal(), "no result");
726
727 break;
728 }
729
730
731 case lir_tan:
732 case lir_log10: {
733 assert(op->as_Op2() != NULL, "must be");
734 LIR_Op2* op2 = (LIR_Op2*)op;
735
736 // On x86 tan/sin/cos need two temporary fpu stack slots and
737 // log/log10 need one so handle opr2 and tmp as temp inputs.
738 // Register input operand as temp to guarantee that it doesn't
739 // overlap with the input.
740 assert(op2->_info == NULL, "not used");
741 assert(op2->_tmp5->is_illegal(), "not used");
742 assert(op2->_opr1->is_valid(), "used");
743 do_input(op2->_opr1); do_temp(op2->_opr1);
744
745 if (op2->_opr2->is_valid()) do_temp(op2->_opr2);
746 if (op2->_tmp1->is_valid()) do_temp(op2->_tmp1);
747 if (op2->_tmp2->is_valid()) do_temp(op2->_tmp2);
748 if (op2->_tmp3->is_valid()) do_temp(op2->_tmp3);
749 if (op2->_tmp4->is_valid()) do_temp(op2->_tmp4);
750 if (op2->_result->is_valid()) do_output(op2->_result);
751
752 break;
753 }
754
755 case lir_pow: {
756 assert(op->as_Op2() != NULL, "must be");
757 LIR_Op2* op2 = (LIR_Op2*)op;
758
759 // On x86 pow needs two temporary fpu stack slots: tmp1 and
760 // tmp2. Register input operands as temps to guarantee that it
761 // doesn't overlap with the temporary slots.
762 assert(op2->_info == NULL, "not used");
763 assert(op2->_opr1->is_valid() && op2->_opr2->is_valid(), "used");
764 assert(op2->_tmp1->is_valid() && op2->_tmp2->is_valid() && op2->_tmp3->is_valid()
765 && op2->_tmp4->is_valid() && op2->_tmp5->is_valid(), "used");
766 assert(op2->_result->is_valid(), "used");
767
768 do_input(op2->_opr1); do_temp(op2->_opr1);
769 do_input(op2->_opr2); do_temp(op2->_opr2);
770 do_temp(op2->_tmp1);
771 do_temp(op2->_tmp2);
772 do_temp(op2->_tmp3);
773 do_temp(op2->_tmp4);
774 do_temp(op2->_tmp5);
775 do_output(op2->_result);
776
777 break;
778 }
779
780 // LIR_Op3
781 case lir_idiv:
782 case lir_irem: {
783 assert(op->as_Op3() != NULL, "must be");
784 LIR_Op3* op3= (LIR_Op3*)op;
785
786 if (op3->_info) do_info(op3->_info);
787 if (op3->_opr1->is_valid()) do_input(op3->_opr1);
788
789 // second operand is input and temp, so ensure that second operand
790 // and third operand get not the same register
791 if (op3->_opr2->is_valid()) do_input(op3->_opr2);
792 if (op3->_opr2->is_valid()) do_temp(op3->_opr2);
793 if (op3->_opr3->is_valid()) do_temp(op3->_opr3);
794
795 if (op3->_result->is_valid()) do_output(op3->_result);
796
797 break;
798 }
799
800
801 // LIR_OpJavaCall
802 case lir_static_call:
803 case lir_optvirtual_call:
804 case lir_icvirtual_call:
805 case lir_virtual_call:
806 case lir_dynamic_call: {
807 LIR_OpJavaCall* opJavaCall = op->as_OpJavaCall();
808 assert(opJavaCall != NULL, "must be");
809
810 if (opJavaCall->_receiver->is_valid()) do_input(opJavaCall->_receiver);
811
812 // only visit register parameters
813 int n = opJavaCall->_arguments->length();
814 for (int i = opJavaCall->_receiver->is_valid() ? 1 : 0; i < n; i++) {
815 if (!opJavaCall->_arguments->at(i)->is_pointer()) {
816 do_input(*opJavaCall->_arguments->adr_at(i));
817 }
818 }
819
820 if (opJavaCall->_info) do_info(opJavaCall->_info);
821 if (FrameMap::method_handle_invoke_SP_save_opr() != LIR_OprFact::illegalOpr &&
822 opJavaCall->is_method_handle_invoke()) {
823 opJavaCall->_method_handle_invoke_SP_save_opr = FrameMap::method_handle_invoke_SP_save_opr();
824 do_temp(opJavaCall->_method_handle_invoke_SP_save_opr);
825 }
826 do_call();
827 if (opJavaCall->_result->is_valid()) do_output(opJavaCall->_result);
828
829 break;
830 }
831
832
833 // LIR_OpRTCall
834 case lir_rtcall: {
835 assert(op->as_OpRTCall() != NULL, "must be");
836 LIR_OpRTCall* opRTCall = (LIR_OpRTCall*)op;
837
838 // only visit register parameters
839 int n = opRTCall->_arguments->length();
840 for (int i = 0; i < n; i++) {
841 if (!opRTCall->_arguments->at(i)->is_pointer()) {
842 do_input(*opRTCall->_arguments->adr_at(i));
843 }
844 }
845 if (opRTCall->_info) do_info(opRTCall->_info);
846 if (opRTCall->_tmp->is_valid()) do_temp(opRTCall->_tmp);
847 do_call();
848 if (opRTCall->_result->is_valid()) do_output(opRTCall->_result);
849
850 break;
851 }
852
853
854 // LIR_OpArrayCopy
855 case lir_arraycopy: {
856 assert(op->as_OpArrayCopy() != NULL, "must be");
857 LIR_OpArrayCopy* opArrayCopy = (LIR_OpArrayCopy*)op;
858
859 assert(opArrayCopy->_result->is_illegal(), "unused");
860 assert(opArrayCopy->_src->is_valid(), "used"); do_input(opArrayCopy->_src); do_temp(opArrayCopy->_src);
861 assert(opArrayCopy->_src_pos->is_valid(), "used"); do_input(opArrayCopy->_src_pos); do_temp(opArrayCopy->_src_pos);
862 assert(opArrayCopy->_dst->is_valid(), "used"); do_input(opArrayCopy->_dst); do_temp(opArrayCopy->_dst);
863 assert(opArrayCopy->_dst_pos->is_valid(), "used"); do_input(opArrayCopy->_dst_pos); do_temp(opArrayCopy->_dst_pos);
864 assert(opArrayCopy->_length->is_valid(), "used"); do_input(opArrayCopy->_length); do_temp(opArrayCopy->_length);
865 assert(opArrayCopy->_tmp->is_valid(), "used"); do_temp(opArrayCopy->_tmp);
866 if (opArrayCopy->_info) do_info(opArrayCopy->_info);
867
868 // the implementation of arraycopy always has a call into the runtime
869 do_call();
870
871 break;
872 }
873
874
875 // LIR_OpUpdateCRC32
876 case lir_updatecrc32: {
877 assert(op->as_OpUpdateCRC32() != NULL, "must be");
878 LIR_OpUpdateCRC32* opUp = (LIR_OpUpdateCRC32*)op;
879
880 assert(opUp->_crc->is_valid(), "used"); do_input(opUp->_crc); do_temp(opUp->_crc);
881 assert(opUp->_val->is_valid(), "used"); do_input(opUp->_val); do_temp(opUp->_val);
882 assert(opUp->_result->is_valid(), "used"); do_output(opUp->_result);
883 assert(opUp->_info == NULL, "no info for LIR_OpUpdateCRC32");
884
885 break;
886 }
887
888
889 // LIR_OpLock
890 case lir_lock:
891 case lir_unlock: {
892 assert(op->as_OpLock() != NULL, "must be");
893 LIR_OpLock* opLock = (LIR_OpLock*)op;
894
895 if (opLock->_info) do_info(opLock->_info);
896
897 // TODO: check if these operands really have to be temp
898 // (or if input is sufficient). This may have influence on the oop map!
899 assert(opLock->_lock->is_valid(), "used"); do_temp(opLock->_lock);
900 assert(opLock->_hdr->is_valid(), "used"); do_temp(opLock->_hdr);
901 assert(opLock->_obj->is_valid(), "used"); do_temp(opLock->_obj);
902
903 if (opLock->_scratch->is_valid()) do_temp(opLock->_scratch);
904 assert(opLock->_result->is_illegal(), "unused");
905
906 do_stub(opLock->_stub);
907
908 break;
909 }
910
911
912 // LIR_OpDelay
913 case lir_delay_slot: {
914 assert(op->as_OpDelay() != NULL, "must be");
915 LIR_OpDelay* opDelay = (LIR_OpDelay*)op;
916
917 visit(opDelay->delay_op());
918 break;
919 }
920
921 // LIR_OpTypeCheck
922 case lir_instanceof:
923 case lir_checkcast:
924 case lir_store_check: {
925 assert(op->as_OpTypeCheck() != NULL, "must be");
926 LIR_OpTypeCheck* opTypeCheck = (LIR_OpTypeCheck*)op;
927
928 if (opTypeCheck->_info_for_exception) do_info(opTypeCheck->_info_for_exception);
929 if (opTypeCheck->_info_for_patch) do_info(opTypeCheck->_info_for_patch);
930 if (opTypeCheck->_object->is_valid()) do_input(opTypeCheck->_object);
931 if (op->code() == lir_store_check && opTypeCheck->_object->is_valid()) {
932 do_temp(opTypeCheck->_object);
933 }
934 if (opTypeCheck->_array->is_valid()) do_input(opTypeCheck->_array);
935 if (opTypeCheck->_tmp1->is_valid()) do_temp(opTypeCheck->_tmp1);
936 if (opTypeCheck->_tmp2->is_valid()) do_temp(opTypeCheck->_tmp2);
937 if (opTypeCheck->_tmp3->is_valid()) do_temp(opTypeCheck->_tmp3);
938 if (opTypeCheck->_result->is_valid()) do_output(opTypeCheck->_result);
939 do_stub(opTypeCheck->_stub);
940 break;
941 }
942
943 // LIR_OpCompareAndSwap
944 case lir_cas_long:
945 case lir_cas_obj:
946 case lir_cas_int: {
947 assert(op->as_OpCompareAndSwap() != NULL, "must be");
948 LIR_OpCompareAndSwap* opCompareAndSwap = (LIR_OpCompareAndSwap*)op;
949
950 assert(opCompareAndSwap->_addr->is_valid(), "used");
951 assert(opCompareAndSwap->_cmp_value->is_valid(), "used");
952 assert(opCompareAndSwap->_new_value->is_valid(), "used");
953 if (opCompareAndSwap->_info) do_info(opCompareAndSwap->_info);
954 do_input(opCompareAndSwap->_addr);
955 do_temp(opCompareAndSwap->_addr);
956 do_input(opCompareAndSwap->_cmp_value);
957 do_temp(opCompareAndSwap->_cmp_value);
958 do_input(opCompareAndSwap->_new_value);
959 do_temp(opCompareAndSwap->_new_value);
960 if (opCompareAndSwap->_tmp1->is_valid()) do_temp(opCompareAndSwap->_tmp1);
961 if (opCompareAndSwap->_tmp2->is_valid()) do_temp(opCompareAndSwap->_tmp2);
962 if (opCompareAndSwap->_result->is_valid()) do_output(opCompareAndSwap->_result);
963
964 break;
965 }
966
967
968 // LIR_OpAllocArray;
969 case lir_alloc_array: {
970 assert(op->as_OpAllocArray() != NULL, "must be");
971 LIR_OpAllocArray* opAllocArray = (LIR_OpAllocArray*)op;
972
973 if (opAllocArray->_info) do_info(opAllocArray->_info);
974 if (opAllocArray->_klass->is_valid()) do_input(opAllocArray->_klass); do_temp(opAllocArray->_klass);
975 if (opAllocArray->_len->is_valid()) do_input(opAllocArray->_len); do_temp(opAllocArray->_len);
976 if (opAllocArray->_tmp1->is_valid()) do_temp(opAllocArray->_tmp1);
977 if (opAllocArray->_tmp2->is_valid()) do_temp(opAllocArray->_tmp2);
978 if (opAllocArray->_tmp3->is_valid()) do_temp(opAllocArray->_tmp3);
979 if (opAllocArray->_tmp4->is_valid()) do_temp(opAllocArray->_tmp4);
980 if (opAllocArray->_result->is_valid()) do_output(opAllocArray->_result);
981 do_stub(opAllocArray->_stub);
982 break;
983 }
984
985 // LIR_OpProfileCall:
986 case lir_profile_call: {
987 assert(op->as_OpProfileCall() != NULL, "must be");
988 LIR_OpProfileCall* opProfileCall = (LIR_OpProfileCall*)op;
989
990 if (opProfileCall->_recv->is_valid()) do_temp(opProfileCall->_recv);
991 assert(opProfileCall->_mdo->is_valid(), "used"); do_temp(opProfileCall->_mdo);
992 assert(opProfileCall->_tmp1->is_valid(), "used"); do_temp(opProfileCall->_tmp1);
993 break;
994 }
995
996 // LIR_OpProfileType:
997 case lir_profile_type: {
998 assert(op->as_OpProfileType() != NULL, "must be");
999 LIR_OpProfileType* opProfileType = (LIR_OpProfileType*)op;
1000
1001 do_input(opProfileType->_mdp); do_temp(opProfileType->_mdp);
1002 do_input(opProfileType->_obj);
1003 do_temp(opProfileType->_tmp);
1004 break;
1005 }
1006 default:
1007 ShouldNotReachHere();
1008 }
1009 }
1010
1011
1012 void LIR_OpVisitState::do_stub(CodeStub* stub) {
1013 if (stub != NULL) {
1014 stub->visit(this);
1015 }
1016 }
1017
1018 XHandlers* LIR_OpVisitState::all_xhandler() {
1019 XHandlers* result = NULL;
1020
1021 int i;
1022 for (i = 0; i < info_count(); i++) {
1023 if (info_at(i)->exception_handlers() != NULL) {
1024 result = info_at(i)->exception_handlers();
1025 break;
1026 }
1027 }
1028
1029 #ifdef ASSERT
1030 for (i = 0; i < info_count(); i++) {
1031 assert(info_at(i)->exception_handlers() == NULL ||
1032 info_at(i)->exception_handlers() == result,
1033 "only one xhandler list allowed per LIR-operation");
1034 }
1035 #endif
1036
1037 if (result != NULL) {
1038 return result;
1039 } else {
1040 return new XHandlers();
1041 }
1042
1043 return result;
1044 }
1045
1046
1047 #ifdef ASSERT
1048 bool LIR_OpVisitState::no_operands(LIR_Op* op) {
1049 visit(op);
1050
1051 return opr_count(inputMode) == 0 &&
1052 opr_count(outputMode) == 0 &&
1053 opr_count(tempMode) == 0 &&
1054 info_count() == 0 &&
1055 !has_call() &&
1056 !has_slow_case();
1057 }
1058 #endif
1059
1060 //---------------------------------------------------
1061
1062
1063 void LIR_OpJavaCall::emit_code(LIR_Assembler* masm) {
1064 masm->emit_call(this);
1065 }
1066
1067 void LIR_OpRTCall::emit_code(LIR_Assembler* masm) {
1068 masm->emit_rtcall(this);
1069 }
1070
1071 void LIR_OpLabel::emit_code(LIR_Assembler* masm) {
1072 masm->emit_opLabel(this);
1073 }
1074
1075 void LIR_OpArrayCopy::emit_code(LIR_Assembler* masm) {
1076 masm->emit_arraycopy(this);
1077 masm->append_code_stub(stub());
1078 }
1079
1080 void LIR_OpUpdateCRC32::emit_code(LIR_Assembler* masm) {
1081 masm->emit_updatecrc32(this);
1082 }
1083
1084 void LIR_Op0::emit_code(LIR_Assembler* masm) {
1085 masm->emit_op0(this);
1086 }
1087
1088 void LIR_Op1::emit_code(LIR_Assembler* masm) {
1089 masm->emit_op1(this);
1090 }
1091
1092 void LIR_OpAllocObj::emit_code(LIR_Assembler* masm) {
1093 masm->emit_alloc_obj(this);
1094 masm->append_code_stub(stub());
1095 }
1096
1097 void LIR_OpBranch::emit_code(LIR_Assembler* masm) {
1098 masm->emit_opBranch(this);
1099 if (stub()) {
1100 masm->append_code_stub(stub());
1101 }
1102 }
1103
1104 void LIR_OpConvert::emit_code(LIR_Assembler* masm) {
1105 masm->emit_opConvert(this);
1106 if (stub() != NULL) {
1107 masm->append_code_stub(stub());
1108 }
1109 }
1110
1111 void LIR_Op2::emit_code(LIR_Assembler* masm) {
1112 masm->emit_op2(this);
1113 }
1114
1115 void LIR_OpAllocArray::emit_code(LIR_Assembler* masm) {
1116 masm->emit_alloc_array(this);
1117 masm->append_code_stub(stub());
1118 }
1119
1120 void LIR_OpTypeCheck::emit_code(LIR_Assembler* masm) {
1121 masm->emit_opTypeCheck(this);
1122 if (stub()) {
1123 masm->append_code_stub(stub());
1124 }
1125 }
1126
1127 void LIR_OpCompareAndSwap::emit_code(LIR_Assembler* masm) {
1128 masm->emit_compare_and_swap(this);
1129 }
1130
1131 void LIR_Op3::emit_code(LIR_Assembler* masm) {
1132 masm->emit_op3(this);
1133 }
1134
1135 void LIR_OpLock::emit_code(LIR_Assembler* masm) {
1136 masm->emit_lock(this);
1137 if (stub()) {
1138 masm->append_code_stub(stub());
1139 }
1140 }
1141
1142 #ifdef ASSERT
1143 void LIR_OpAssert::emit_code(LIR_Assembler* masm) {
1144 masm->emit_assert(this);
1145 }
1146 #endif
1147
1148 void LIR_OpDelay::emit_code(LIR_Assembler* masm) {
1149 masm->emit_delay(this);
1150 }
1151
1152 void LIR_OpProfileCall::emit_code(LIR_Assembler* masm) {
1153 masm->emit_profile_call(this);
1154 }
1155
1156 void LIR_OpProfileType::emit_code(LIR_Assembler* masm) {
1157 masm->emit_profile_type(this);
1158 }
1159
1160 // LIR_List
1161 LIR_List::LIR_List(Compilation* compilation, BlockBegin* block)
1162 : _operations(8)
1163 , _compilation(compilation)
1164 #ifndef PRODUCT
1165 , _block(block)
1166 #endif
1167 #ifdef ASSERT
1168 , _file(NULL)
1169 , _line(0)
1170 #endif
1171 { }
1172
1173
1174 #ifdef ASSERT
1175 void LIR_List::set_file_and_line(const char * file, int line) {
1176 const char * f = strrchr(file, '/');
1177 if (f == NULL) f = strrchr(file, '\\');
1178 if (f == NULL) {
1179 f = file;
1180 } else {
1181 f++;
1182 }
1183 _file = f;
1184 _line = line;
1185 }
1186 #endif
1187
1188
1189 void LIR_List::append(LIR_InsertionBuffer* buffer) {
1190 assert(this == buffer->lir_list(), "wrong lir list");
1191 const int n = _operations.length();
1192
1193 if (buffer->number_of_ops() > 0) {
1194 // increase size of instructions list
1195 _operations.at_grow(n + buffer->number_of_ops() - 1, NULL);
1196 // insert ops from buffer into instructions list
1197 int op_index = buffer->number_of_ops() - 1;
1198 int ip_index = buffer->number_of_insertion_points() - 1;
1199 int from_index = n - 1;
1200 int to_index = _operations.length() - 1;
1201 for (; ip_index >= 0; ip_index --) {
1202 int index = buffer->index_at(ip_index);
1203 // make room after insertion point
1204 while (index < from_index) {
1205 _operations.at_put(to_index --, _operations.at(from_index --));
1206 }
1207 // insert ops from buffer
1208 for (int i = buffer->count_at(ip_index); i > 0; i --) {
1209 _operations.at_put(to_index --, buffer->op_at(op_index --));
1210 }
1211 }
1212 }
1213
1214 buffer->finish();
1215 }
1216
1217
1218 void LIR_List::oop2reg_patch(jobject o, LIR_Opr reg, CodeEmitInfo* info) {
1219 assert(reg->type() == T_OBJECT, "bad reg");
1220 append(new LIR_Op1(lir_move, LIR_OprFact::oopConst(o), reg, T_OBJECT, lir_patch_normal, info));
1221 }
1222
1223 void LIR_List::klass2reg_patch(Metadata* o, LIR_Opr reg, CodeEmitInfo* info) {
1224 assert(reg->type() == T_METADATA, "bad reg");
1225 append(new LIR_Op1(lir_move, LIR_OprFact::metadataConst(o), reg, T_METADATA, lir_patch_normal, info));
1226 }
1227
1228 void LIR_List::load(LIR_Address* addr, LIR_Opr src, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1229 append(new LIR_Op1(
1230 lir_move,
1231 LIR_OprFact::address(addr),
1232 src,
1233 addr->type(),
1234 patch_code,
1235 info));
1236 }
1237
1238
1239 void LIR_List::volatile_load_mem_reg(LIR_Address* address, LIR_Opr dst, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1240 append(new LIR_Op1(
1241 lir_move,
1242 LIR_OprFact::address(address),
1243 dst,
1244 address->type(),
1245 patch_code,
1246 info, lir_move_volatile));
1247 }
1248
1249 void LIR_List::volatile_load_unsafe_reg(LIR_Opr base, LIR_Opr offset, LIR_Opr dst, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1250 append(new LIR_Op1(
1251 lir_move,
1252 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1253 dst,
1254 type,
1255 patch_code,
1256 info, lir_move_volatile));
1257 }
1258
1259
1260 void LIR_List::store_mem_int(jint v, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1261 append(new LIR_Op1(
1262 lir_move,
1263 LIR_OprFact::intConst(v),
1264 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1265 type,
1266 patch_code,
1267 info));
1268 }
1269
1270
1271 void LIR_List::store_mem_oop(jobject o, LIR_Opr base, int offset_in_bytes, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1272 append(new LIR_Op1(
1273 lir_move,
1274 LIR_OprFact::oopConst(o),
1275 LIR_OprFact::address(new LIR_Address(base, offset_in_bytes, type)),
1276 type,
1277 patch_code,
1278 info));
1279 }
1280
1281
1282 void LIR_List::store(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1283 append(new LIR_Op1(
1284 lir_move,
1285 src,
1286 LIR_OprFact::address(addr),
1287 addr->type(),
1288 patch_code,
1289 info));
1290 }
1291
1292
1293 void LIR_List::volatile_store_mem_reg(LIR_Opr src, LIR_Address* addr, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1294 append(new LIR_Op1(
1295 lir_move,
1296 src,
1297 LIR_OprFact::address(addr),
1298 addr->type(),
1299 patch_code,
1300 info,
1301 lir_move_volatile));
1302 }
1303
1304 void LIR_List::volatile_store_unsafe_reg(LIR_Opr src, LIR_Opr base, LIR_Opr offset, BasicType type, CodeEmitInfo* info, LIR_PatchCode patch_code) {
1305 append(new LIR_Op1(
1306 lir_move,
1307 src,
1308 LIR_OprFact::address(new LIR_Address(base, offset, type)),
1309 type,
1310 patch_code,
1311 info, lir_move_volatile));
1312 }
1313
1314
1315 void LIR_List::idiv(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1316 append(new LIR_Op3(
1317 lir_idiv,
1318 left,
1319 right,
1320 tmp,
1321 res,
1322 info));
1323 }
1324
1325
1326 void LIR_List::idiv(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1327 append(new LIR_Op3(
1328 lir_idiv,
1329 left,
1330 LIR_OprFact::intConst(right),
1331 tmp,
1332 res,
1333 info));
1334 }
1335
1336
1337 void LIR_List::irem(LIR_Opr left, LIR_Opr right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1338 append(new LIR_Op3(
1339 lir_irem,
1340 left,
1341 right,
1342 tmp,
1343 res,
1344 info));
1345 }
1346
1347
1348 void LIR_List::irem(LIR_Opr left, int right, LIR_Opr res, LIR_Opr tmp, CodeEmitInfo* info) {
1349 append(new LIR_Op3(
1350 lir_irem,
1351 left,
1352 LIR_OprFact::intConst(right),
1353 tmp,
1354 res,
1355 info));
1356 }
1357
1358
1359 void LIR_List::cmp_mem_int(LIR_Condition condition, LIR_Opr base, int disp, int c, CodeEmitInfo* info) {
1360 append(new LIR_Op2(
1361 lir_cmp,
1362 condition,
1363 LIR_OprFact::address(new LIR_Address(base, disp, T_INT)),
1364 LIR_OprFact::intConst(c),
1365 info));
1366 }
1367
1368
1369 void LIR_List::cmp_reg_mem(LIR_Condition condition, LIR_Opr reg, LIR_Address* addr, CodeEmitInfo* info) {
1370 append(new LIR_Op2(
1371 lir_cmp,
1372 condition,
1373 reg,
1374 LIR_OprFact::address(addr),
1375 info));
1376 }
1377
1378 void LIR_List::allocate_object(LIR_Opr dst, LIR_Opr t1, LIR_Opr t2, LIR_Opr t3, LIR_Opr t4,
1379 int header_size, int object_size, LIR_Opr klass, bool init_check, CodeStub* stub) {
1380 append(new LIR_OpAllocObj(
1381 klass,
1382 dst,
1383 t1,
1384 t2,
1385 t3,
1386 t4,
1387 header_size,
1388 object_size,
1389 init_check,
1390 stub));
1391 }
1392
1393 void LIR_List::allocate_array(LIR_Opr dst, LIR_Opr len, LIR_Opr t1,LIR_Opr t2, LIR_Opr t3,LIR_Opr t4, BasicType type, LIR_Opr klass, CodeStub* stub) {
1394 append(new LIR_OpAllocArray(
1395 klass,
1396 len,
1397 dst,
1398 t1,
1399 t2,
1400 t3,
1401 t4,
1402 type,
1403 stub));
1404 }
1405
1406 void LIR_List::shift_left(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1407 append(new LIR_Op2(
1408 lir_shl,
1409 value,
1410 count,
1411 dst,
1412 tmp));
1413 }
1414
1415 void LIR_List::shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1416 append(new LIR_Op2(
1417 lir_shr,
1418 value,
1419 count,
1420 dst,
1421 tmp));
1422 }
1423
1424
1425 void LIR_List::unsigned_shift_right(LIR_Opr value, LIR_Opr count, LIR_Opr dst, LIR_Opr tmp) {
1426 append(new LIR_Op2(
1427 lir_ushr,
1428 value,
1429 count,
1430 dst,
1431 tmp));
1432 }
1433
1434 void LIR_List::fcmp2int(LIR_Opr left, LIR_Opr right, LIR_Opr dst, bool is_unordered_less) {
1435 append(new LIR_Op2(is_unordered_less ? lir_ucmp_fd2i : lir_cmp_fd2i,
1436 left,
1437 right,
1438 dst));
1439 }
1440
1441 void LIR_List::lock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub, CodeEmitInfo* info) {
1442 append(new LIR_OpLock(
1443 lir_lock,
1444 hdr,
1445 obj,
1446 lock,
1447 scratch,
1448 stub,
1449 info));
1450 }
1451
1452 void LIR_List::unlock_object(LIR_Opr hdr, LIR_Opr obj, LIR_Opr lock, LIR_Opr scratch, CodeStub* stub) {
1453 append(new LIR_OpLock(
1454 lir_unlock,
1455 hdr,
1456 obj,
1457 lock,
1458 scratch,
1459 stub,
1460 NULL));
1461 }
1462
1463
1464 void check_LIR() {
1465 // cannot do the proper checking as PRODUCT and other modes return different results
1466 // guarantee(sizeof(LIR_OprDesc) == wordSize, "may not have a v-table");
1467 }
1468
1469
1470
1471 void LIR_List::checkcast (LIR_Opr result, LIR_Opr object, ciKlass* klass,
1472 LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check,
1473 CodeEmitInfo* info_for_exception, CodeEmitInfo* info_for_patch, CodeStub* stub,
1474 ciMethod* profiled_method, int profiled_bci) {
1475 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_checkcast, result, object, klass,
1476 tmp1, tmp2, tmp3, fast_check, info_for_exception, info_for_patch, stub);
1477 if (profiled_method != NULL) {
1478 c->set_profiled_method(profiled_method);
1479 c->set_profiled_bci(profiled_bci);
1480 c->set_should_profile(true);
1481 }
1482 append(c);
1483 }
1484
1485 void LIR_List::instanceof(LIR_Opr result, LIR_Opr object, ciKlass* klass, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3, bool fast_check, CodeEmitInfo* info_for_patch, ciMethod* profiled_method, int profiled_bci) {
1486 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_instanceof, result, object, klass, tmp1, tmp2, tmp3, fast_check, NULL, info_for_patch, NULL);
1487 if (profiled_method != NULL) {
1488 c->set_profiled_method(profiled_method);
1489 c->set_profiled_bci(profiled_bci);
1490 c->set_should_profile(true);
1491 }
1492 append(c);
1493 }
1494
1495
1496 void LIR_List::store_check(LIR_Opr object, LIR_Opr array, LIR_Opr tmp1, LIR_Opr tmp2, LIR_Opr tmp3,
1497 CodeEmitInfo* info_for_exception, ciMethod* profiled_method, int profiled_bci) {
1498 LIR_OpTypeCheck* c = new LIR_OpTypeCheck(lir_store_check, object, array, tmp1, tmp2, tmp3, info_for_exception);
1499 if (profiled_method != NULL) {
1500 c->set_profiled_method(profiled_method);
1501 c->set_profiled_bci(profiled_bci);
1502 c->set_should_profile(true);
1503 }
1504 append(c);
1505 }
1506
1507
1508 void LIR_List::cas_long(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1509 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1510 append(new LIR_OpCompareAndSwap(lir_cas_long, addr, cmp_value, new_value, t1, t2, result));
1511 }
1512
1513 void LIR_List::cas_obj(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1514 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1515 append(new LIR_OpCompareAndSwap(lir_cas_obj, addr, cmp_value, new_value, t1, t2, result));
1516 }
1517
1518 void LIR_List::cas_int(LIR_Opr addr, LIR_Opr cmp_value, LIR_Opr new_value,
1519 LIR_Opr t1, LIR_Opr t2, LIR_Opr result) {
1520 append(new LIR_OpCompareAndSwap(lir_cas_int, addr, cmp_value, new_value, t1, t2, result));
1521 }
1522
1523
1524 #ifdef PRODUCT
1525
1526 void print_LIR(BlockList* blocks) {
1527 }
1528
1529 #else
1530 // LIR_OprDesc
1531 void LIR_OprDesc::print() const {
1532 print(tty);
1533 }
1534
1535 void LIR_OprDesc::print(outputStream* out) const {
1536 if (is_illegal()) {
1537 return;
1538 }
1539
1540 out->print("[");
1541 if (is_pointer()) {
1542 pointer()->print_value_on(out);
1543 } else if (is_single_stack()) {
1544 out->print("stack:%d", single_stack_ix());
1545 } else if (is_double_stack()) {
1546 out->print("dbl_stack:%d",double_stack_ix());
1547 } else if (is_virtual()) {
1548 out->print("R%d", vreg_number());
1549 } else if (is_single_cpu()) {
1550 out->print("%s", as_register()->name());
1551 } else if (is_double_cpu()) {
1552 out->print("%s", as_register_hi()->name());
1553 out->print("%s", as_register_lo()->name());
1554 #if defined(X86)
1555 } else if (is_single_xmm()) {
1556 out->print("%s", as_xmm_float_reg()->name());
1557 } else if (is_double_xmm()) {
1558 out->print("%s", as_xmm_double_reg()->name());
1559 } else if (is_single_fpu()) {
1560 out->print("fpu%d", fpu_regnr());
1561 } else if (is_double_fpu()) {
1562 out->print("fpu%d", fpu_regnrLo());
1563 #elif defined(AARCH64)
1564 } else if (is_single_fpu()) {
1565 out->print("fpu%d", fpu_regnr());
1566 } else if (is_double_fpu()) {
1567 out->print("fpu%d", fpu_regnrLo());
1568 #elif defined(ARM)
1569 } else if (is_single_fpu()) {
1570 out->print("s%d", fpu_regnr());
1571 } else if (is_double_fpu()) {
1572 out->print("d%d", fpu_regnrLo() >> 1);
1573 #else
1574 } else if (is_single_fpu()) {
1575 out->print("%s", as_float_reg()->name());
1576 } else if (is_double_fpu()) {
1577 out->print("%s", as_double_reg()->name());
1578 #endif
1579
1580 } else if (is_illegal()) {
1581 out->print("-");
1582 } else {
1583 out->print("Unknown Operand");
1584 }
1585 if (!is_illegal()) {
1586 out->print("|%c", type_char());
1587 }
1588 if (is_register() && is_last_use()) {
1589 out->print("(last_use)");
1590 }
1591 out->print("]");
1592 }
1593
1594
1595 // LIR_Address
1596 void LIR_Const::print_value_on(outputStream* out) const {
1597 switch (type()) {
1598 case T_ADDRESS:out->print("address:%d",as_jint()); break;
1599 case T_INT: out->print("int:%d", as_jint()); break;
1600 case T_LONG: out->print("lng:" JLONG_FORMAT, as_jlong()); break;
1601 case T_FLOAT: out->print("flt:%f", as_jfloat()); break;
1602 case T_DOUBLE: out->print("dbl:%f", as_jdouble()); break;
1603 case T_OBJECT: out->print("obj:" INTPTR_FORMAT, p2i(as_jobject())); break;
1604 case T_METADATA: out->print("metadata:" INTPTR_FORMAT, p2i(as_metadata()));break;
1605 default: out->print("%3d:0x" UINT64_FORMAT_X, type(), (uint64_t)as_jlong()); break;
1606 }
1607 }
1608
1609 // LIR_Address
1610 void LIR_Address::print_value_on(outputStream* out) const {
1611 out->print("Base:"); _base->print(out);
1612 if (!_index->is_illegal()) {
1613 out->print(" Index:"); _index->print(out);
1614 switch (scale()) {
1615 case times_1: break;
1616 case times_2: out->print(" * 2"); break;
1617 case times_4: out->print(" * 4"); break;
1618 case times_8: out->print(" * 8"); break;
1619 }
1620 }
1621 out->print(" Disp: " INTX_FORMAT, _disp);
1622 }
1623
1624 // debug output of block header without InstructionPrinter
1625 // (because phi functions are not necessary for LIR)
1626 static void print_block(BlockBegin* x) {
1627 // print block id
1628 BlockEnd* end = x->end();
1629 tty->print("B%d ", x->block_id());
1630
1631 // print flags
1632 if (x->is_set(BlockBegin::std_entry_flag)) tty->print("std ");
1633 if (x->is_set(BlockBegin::osr_entry_flag)) tty->print("osr ");
1634 if (x->is_set(BlockBegin::exception_entry_flag)) tty->print("ex ");
1635 if (x->is_set(BlockBegin::subroutine_entry_flag)) tty->print("jsr ");
1636 if (x->is_set(BlockBegin::backward_branch_target_flag)) tty->print("bb ");
1637 if (x->is_set(BlockBegin::linear_scan_loop_header_flag)) tty->print("lh ");
1638 if (x->is_set(BlockBegin::linear_scan_loop_end_flag)) tty->print("le ");
1639
1640 // print block bci range
1641 tty->print("[%d, %d] ", x->bci(), (end == NULL ? -1 : end->printable_bci()));
1642
1643 // print predecessors and successors
1644 if (x->number_of_preds() > 0) {
1645 tty->print("preds: ");
1646 for (int i = 0; i < x->number_of_preds(); i ++) {
1647 tty->print("B%d ", x->pred_at(i)->block_id());
1648 }
1649 }
1650
1651 if (x->number_of_sux() > 0) {
1652 tty->print("sux: ");
1653 for (int i = 0; i < x->number_of_sux(); i ++) {
1654 tty->print("B%d ", x->sux_at(i)->block_id());
1655 }
1656 }
1657
1658 // print exception handlers
1659 if (x->number_of_exception_handlers() > 0) {
1660 tty->print("xhandler: ");
1661 for (int i = 0; i < x->number_of_exception_handlers(); i++) {
1662 tty->print("B%d ", x->exception_handler_at(i)->block_id());
1663 }
1664 }
1665
1666 tty->cr();
1667 }
1668
1669 void print_LIR(BlockList* blocks) {
1670 tty->print_cr("LIR:");
1671 int i;
1672 for (i = 0; i < blocks->length(); i++) {
1673 BlockBegin* bb = blocks->at(i);
1674 print_block(bb);
1675 tty->print("__id_Instruction___________________________________________"); tty->cr();
1676 bb->lir()->print_instructions();
1677 }
1678 }
1679
1680 void LIR_List::print_instructions() {
1681 for (int i = 0; i < _operations.length(); i++) {
1682 _operations.at(i)->print(); tty->cr();
1683 }
1684 tty->cr();
1685 }
1686
1687 // LIR_Ops printing routines
1688 // LIR_Op
1689 void LIR_Op::print_on(outputStream* out) const {
1690 if (id() != -1 || PrintCFGToFile) {
1691 out->print("%4d ", id());
1692 } else {
1693 out->print(" ");
1694 }
1695 out->print("%s ", name());
1696 print_instr(out);
1697 if (info() != NULL) out->print(" [bci:%d]", info()->stack()->bci());
1698 #ifdef ASSERT
1699 if (Verbose && _file != NULL) {
1700 out->print(" (%s:%d)", _file, _line);
1701 }
1702 #endif
1703 }
1704
1705 const char * LIR_Op::name() const {
1706 const char* s = NULL;
1707 switch(code()) {
1708 // LIR_Op0
1709 case lir_membar: s = "membar"; break;
1710 case lir_membar_acquire: s = "membar_acquire"; break;
1711 case lir_membar_release: s = "membar_release"; break;
1712 case lir_membar_loadload: s = "membar_loadload"; break;
1713 case lir_membar_storestore: s = "membar_storestore"; break;
1714 case lir_membar_loadstore: s = "membar_loadstore"; break;
1715 case lir_membar_storeload: s = "membar_storeload"; break;
1716 case lir_word_align: s = "word_align"; break;
1717 case lir_label: s = "label"; break;
1718 case lir_nop: s = "nop"; break;
1719 case lir_backwardbranch_target: s = "backbranch"; break;
1720 case lir_std_entry: s = "std_entry"; break;
1721 case lir_osr_entry: s = "osr_entry"; break;
1722 case lir_build_frame: s = "build_frm"; break;
1723 case lir_fpop_raw: s = "fpop_raw"; break;
1724 case lir_24bit_FPU: s = "24bit_FPU"; break;
1725 case lir_reset_FPU: s = "reset_FPU"; break;
1726 case lir_breakpoint: s = "breakpoint"; break;
1727 case lir_get_thread: s = "get_thread"; break;
1728 // LIR_Op1
1729 case lir_fxch: s = "fxch"; break;
1730 case lir_fld: s = "fld"; break;
1731 case lir_ffree: s = "ffree"; break;
1732 case lir_push: s = "push"; break;
1733 case lir_pop: s = "pop"; break;
1734 case lir_null_check: s = "null_check"; break;
1735 case lir_return: s = "return"; break;
1736 case lir_safepoint: s = "safepoint"; break;
1737 case lir_neg: s = "neg"; break;
1738 case lir_leal: s = "leal"; break;
1739 case lir_branch: s = "branch"; break;
1740 case lir_cond_float_branch: s = "flt_cond_br"; break;
1741 case lir_move: s = "move"; break;
1742 case lir_roundfp: s = "roundfp"; break;
1743 case lir_rtcall: s = "rtcall"; break;
1744 case lir_throw: s = "throw"; break;
1745 case lir_unwind: s = "unwind"; break;
1746 case lir_convert: s = "convert"; break;
1747 case lir_alloc_object: s = "alloc_obj"; break;
1748 case lir_monaddr: s = "mon_addr"; break;
1749 case lir_pack64: s = "pack64"; break;
1750 case lir_unpack64: s = "unpack64"; break;
1751 // LIR_Op2
1752 case lir_cmp: s = "cmp"; break;
1753 case lir_cmp_l2i: s = "cmp_l2i"; break;
1754 case lir_ucmp_fd2i: s = "ucomp_fd2i"; break;
1755 case lir_cmp_fd2i: s = "comp_fd2i"; break;
1756 case lir_cmove: s = "cmove"; break;
1757 case lir_add: s = "add"; break;
1758 case lir_sub: s = "sub"; break;
1759 case lir_mul: s = "mul"; break;
1760 case lir_mul_strictfp: s = "mul_strictfp"; break;
1761 case lir_div: s = "div"; break;
1762 case lir_div_strictfp: s = "div_strictfp"; break;
1763 case lir_rem: s = "rem"; break;
1764 case lir_abs: s = "abs"; break;
1765 case lir_sqrt: s = "sqrt"; break;
1766 case lir_tan: s = "tan"; break;
1767 case lir_log10: s = "log10"; break;
1768 case lir_pow: s = "pow"; break;
1769 case lir_logic_and: s = "logic_and"; break;
1770 case lir_logic_or: s = "logic_or"; break;
1771 case lir_logic_xor: s = "logic_xor"; break;
1772 case lir_shl: s = "shift_left"; break;
1773 case lir_shr: s = "shift_right"; break;
1774 case lir_ushr: s = "ushift_right"; break;
1775 case lir_alloc_array: s = "alloc_array"; break;
1776 case lir_xadd: s = "xadd"; break;
1777 case lir_xchg: s = "xchg"; break;
1778 // LIR_Op3
1779 case lir_idiv: s = "idiv"; break;
1780 case lir_irem: s = "irem"; break;
1781 // LIR_OpJavaCall
1782 case lir_static_call: s = "static"; break;
1783 case lir_optvirtual_call: s = "optvirtual"; break;
1784 case lir_icvirtual_call: s = "icvirtual"; break;
1785 case lir_virtual_call: s = "virtual"; break;
1786 case lir_dynamic_call: s = "dynamic"; break;
1787 // LIR_OpArrayCopy
1788 case lir_arraycopy: s = "arraycopy"; break;
1789 // LIR_OpUpdateCRC32
1790 case lir_updatecrc32: s = "updatecrc32"; break;
1791 // LIR_OpLock
1792 case lir_lock: s = "lock"; break;
1793 case lir_unlock: s = "unlock"; break;
1794 // LIR_OpDelay
1795 case lir_delay_slot: s = "delay"; break;
1796 // LIR_OpTypeCheck
1797 case lir_instanceof: s = "instanceof"; break;
1798 case lir_checkcast: s = "checkcast"; break;
1799 case lir_store_check: s = "store_check"; break;
1800 // LIR_OpCompareAndSwap
1801 case lir_cas_long: s = "cas_long"; break;
1802 case lir_cas_obj: s = "cas_obj"; break;
1803 case lir_cas_int: s = "cas_int"; break;
1804 // LIR_OpProfileCall
1805 case lir_profile_call: s = "profile_call"; break;
1806 // LIR_OpProfileType
1807 case lir_profile_type: s = "profile_type"; break;
1808 // LIR_OpAssert
1809 #ifdef ASSERT
1810 case lir_assert: s = "assert"; break;
1811 #endif
1812 case lir_none: ShouldNotReachHere();break;
1813 default: s = "illegal_op"; break;
1814 }
1815 return s;
1816 }
1817
1818 // LIR_OpJavaCall
1819 void LIR_OpJavaCall::print_instr(outputStream* out) const {
1820 out->print("call: ");
1821 out->print("[addr: " INTPTR_FORMAT "]", p2i(address()));
1822 if (receiver()->is_valid()) {
1823 out->print(" [recv: "); receiver()->print(out); out->print("]");
1824 }
1825 if (result_opr()->is_valid()) {
1826 out->print(" [result: "); result_opr()->print(out); out->print("]");
1827 }
1828 }
1829
1830 // LIR_OpLabel
1831 void LIR_OpLabel::print_instr(outputStream* out) const {
1832 out->print("[label:" INTPTR_FORMAT "]", p2i(_label));
1833 }
1834
1835 // LIR_OpArrayCopy
1836 void LIR_OpArrayCopy::print_instr(outputStream* out) const {
1837 src()->print(out); out->print(" ");
1838 src_pos()->print(out); out->print(" ");
1839 dst()->print(out); out->print(" ");
1840 dst_pos()->print(out); out->print(" ");
1841 length()->print(out); out->print(" ");
1842 tmp()->print(out); out->print(" ");
1843 }
1844
1845 // LIR_OpUpdateCRC32
1846 void LIR_OpUpdateCRC32::print_instr(outputStream* out) const {
1847 crc()->print(out); out->print(" ");
1848 val()->print(out); out->print(" ");
1849 result_opr()->print(out); out->print(" ");
1850 }
1851
1852 // LIR_OpCompareAndSwap
1853 void LIR_OpCompareAndSwap::print_instr(outputStream* out) const {
1854 addr()->print(out); out->print(" ");
1855 cmp_value()->print(out); out->print(" ");
1856 new_value()->print(out); out->print(" ");
1857 tmp1()->print(out); out->print(" ");
1858 tmp2()->print(out); out->print(" ");
1859
1860 }
1861
1862 // LIR_Op0
1863 void LIR_Op0::print_instr(outputStream* out) const {
1864 result_opr()->print(out);
1865 }
1866
1867 // LIR_Op1
1868 const char * LIR_Op1::name() const {
1869 if (code() == lir_move) {
1870 switch (move_kind()) {
1871 case lir_move_normal:
1872 return "move";
1873 case lir_move_unaligned:
1874 return "unaligned move";
1875 case lir_move_volatile:
1876 return "volatile_move";
1877 case lir_move_wide:
1878 return "wide_move";
1879 default:
1880 ShouldNotReachHere();
1881 return "illegal_op";
1882 }
1883 } else {
1884 return LIR_Op::name();
1885 }
1886 }
1887
1888
1889 void LIR_Op1::print_instr(outputStream* out) const {
1890 _opr->print(out); out->print(" ");
1891 result_opr()->print(out); out->print(" ");
1892 print_patch_code(out, patch_code());
1893 }
1894
1895
1896 // LIR_Op1
1897 void LIR_OpRTCall::print_instr(outputStream* out) const {
1898 intx a = (intx)addr();
1899 out->print("%s", Runtime1::name_for_address(addr()));
1900 out->print(" ");
1901 tmp()->print(out);
1902 }
1903
1904 void LIR_Op1::print_patch_code(outputStream* out, LIR_PatchCode code) {
1905 switch(code) {
1906 case lir_patch_none: break;
1907 case lir_patch_low: out->print("[patch_low]"); break;
1908 case lir_patch_high: out->print("[patch_high]"); break;
1909 case lir_patch_normal: out->print("[patch_normal]"); break;
1910 default: ShouldNotReachHere();
1911 }
1912 }
1913
1914 // LIR_OpBranch
1915 void LIR_OpBranch::print_instr(outputStream* out) const {
1916 print_condition(out, cond()); out->print(" ");
1917 if (block() != NULL) {
1918 out->print("[B%d] ", block()->block_id());
1919 } else if (stub() != NULL) {
1920 out->print("[");
1921 stub()->print_name(out);
1922 out->print(": " INTPTR_FORMAT "]", p2i(stub()));
1923 if (stub()->info() != NULL) out->print(" [bci:%d]", stub()->info()->stack()->bci());
1924 } else {
1925 out->print("[label:" INTPTR_FORMAT "] ", p2i(label()));
1926 }
1927 if (ublock() != NULL) {
1928 out->print("unordered: [B%d] ", ublock()->block_id());
1929 }
1930 }
1931
1932 void LIR_Op::print_condition(outputStream* out, LIR_Condition cond) {
1933 switch(cond) {
1934 case lir_cond_equal: out->print("[EQ]"); break;
1935 case lir_cond_notEqual: out->print("[NE]"); break;
1936 case lir_cond_less: out->print("[LT]"); break;
1937 case lir_cond_lessEqual: out->print("[LE]"); break;
1938 case lir_cond_greaterEqual: out->print("[GE]"); break;
1939 case lir_cond_greater: out->print("[GT]"); break;
1940 case lir_cond_belowEqual: out->print("[BE]"); break;
1941 case lir_cond_aboveEqual: out->print("[AE]"); break;
1942 case lir_cond_always: out->print("[AL]"); break;
1943 default: out->print("[%d]",cond); break;
1944 }
1945 }
1946
1947 // LIR_OpConvert
1948 void LIR_OpConvert::print_instr(outputStream* out) const {
1949 print_bytecode(out, bytecode());
1950 in_opr()->print(out); out->print(" ");
1951 result_opr()->print(out); out->print(" ");
1952 #ifdef PPC
1953 if(tmp1()->is_valid()) {
1954 tmp1()->print(out); out->print(" ");
1955 tmp2()->print(out); out->print(" ");
1956 }
1957 #endif
1958 }
1959
1960 void LIR_OpConvert::print_bytecode(outputStream* out, Bytecodes::Code code) {
1961 switch(code) {
1962 case Bytecodes::_d2f: out->print("[d2f] "); break;
1963 case Bytecodes::_d2i: out->print("[d2i] "); break;
1964 case Bytecodes::_d2l: out->print("[d2l] "); break;
1965 case Bytecodes::_f2d: out->print("[f2d] "); break;
1966 case Bytecodes::_f2i: out->print("[f2i] "); break;
1967 case Bytecodes::_f2l: out->print("[f2l] "); break;
1968 case Bytecodes::_i2b: out->print("[i2b] "); break;
1969 case Bytecodes::_i2c: out->print("[i2c] "); break;
1970 case Bytecodes::_i2d: out->print("[i2d] "); break;
1971 case Bytecodes::_i2f: out->print("[i2f] "); break;
1972 case Bytecodes::_i2l: out->print("[i2l] "); break;
1973 case Bytecodes::_i2s: out->print("[i2s] "); break;
1974 case Bytecodes::_l2i: out->print("[l2i] "); break;
1975 case Bytecodes::_l2f: out->print("[l2f] "); break;
1976 case Bytecodes::_l2d: out->print("[l2d] "); break;
1977 default:
1978 out->print("[?%d]",code);
1979 break;
1980 }
1981 }
1982
1983 void LIR_OpAllocObj::print_instr(outputStream* out) const {
1984 klass()->print(out); out->print(" ");
1985 obj()->print(out); out->print(" ");
1986 tmp1()->print(out); out->print(" ");
1987 tmp2()->print(out); out->print(" ");
1988 tmp3()->print(out); out->print(" ");
1989 tmp4()->print(out); out->print(" ");
1990 out->print("[hdr:%d]", header_size()); out->print(" ");
1991 out->print("[obj:%d]", object_size()); out->print(" ");
1992 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
1993 }
1994
1995 void LIR_OpRoundFP::print_instr(outputStream* out) const {
1996 _opr->print(out); out->print(" ");
1997 tmp()->print(out); out->print(" ");
1998 result_opr()->print(out); out->print(" ");
1999 }
2000
2001 // LIR_Op2
2002 void LIR_Op2::print_instr(outputStream* out) const {
2003 if (code() == lir_cmove || code() == lir_cmp) {
2004 print_condition(out, condition()); out->print(" ");
2005 }
2006 in_opr1()->print(out); out->print(" ");
2007 in_opr2()->print(out); out->print(" ");
2008 if (tmp1_opr()->is_valid()) { tmp1_opr()->print(out); out->print(" "); }
2009 if (tmp2_opr()->is_valid()) { tmp2_opr()->print(out); out->print(" "); }
2010 if (tmp3_opr()->is_valid()) { tmp3_opr()->print(out); out->print(" "); }
2011 if (tmp4_opr()->is_valid()) { tmp4_opr()->print(out); out->print(" "); }
2012 if (tmp5_opr()->is_valid()) { tmp5_opr()->print(out); out->print(" "); }
2013 result_opr()->print(out);
2014 }
2015
2016 void LIR_OpAllocArray::print_instr(outputStream* out) const {
2017 klass()->print(out); out->print(" ");
2018 len()->print(out); out->print(" ");
2019 obj()->print(out); out->print(" ");
2020 tmp1()->print(out); out->print(" ");
2021 tmp2()->print(out); out->print(" ");
2022 tmp3()->print(out); out->print(" ");
2023 tmp4()->print(out); out->print(" ");
2024 out->print("[type:0x%x]", type()); out->print(" ");
2025 out->print("[label:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2026 }
2027
2028
2029 void LIR_OpTypeCheck::print_instr(outputStream* out) const {
2030 object()->print(out); out->print(" ");
2031 if (code() == lir_store_check) {
2032 array()->print(out); out->print(" ");
2033 }
2034 if (code() != lir_store_check) {
2035 klass()->print_name_on(out); out->print(" ");
2036 if (fast_check()) out->print("fast_check ");
2037 }
2038 tmp1()->print(out); out->print(" ");
2039 tmp2()->print(out); out->print(" ");
2040 tmp3()->print(out); out->print(" ");
2041 result_opr()->print(out); out->print(" ");
2042 if (info_for_exception() != NULL) out->print(" [bci:%d]", info_for_exception()->stack()->bci());
2043 }
2044
2045
2046 // LIR_Op3
2047 void LIR_Op3::print_instr(outputStream* out) const {
2048 in_opr1()->print(out); out->print(" ");
2049 in_opr2()->print(out); out->print(" ");
2050 in_opr3()->print(out); out->print(" ");
2051 result_opr()->print(out);
2052 }
2053
2054
2055 void LIR_OpLock::print_instr(outputStream* out) const {
2056 hdr_opr()->print(out); out->print(" ");
2057 obj_opr()->print(out); out->print(" ");
2058 lock_opr()->print(out); out->print(" ");
2059 if (_scratch->is_valid()) {
2060 _scratch->print(out); out->print(" ");
2061 }
2062 out->print("[lbl:" INTPTR_FORMAT "]", p2i(stub()->entry()));
2063 }
2064
2065 #ifdef ASSERT
2066 void LIR_OpAssert::print_instr(outputStream* out) const {
2067 print_condition(out, condition()); out->print(" ");
2068 in_opr1()->print(out); out->print(" ");
2069 in_opr2()->print(out); out->print(", \"");
2070 out->print("%s", msg()); out->print("\"");
2071 }
2072 #endif
2073
2074
2075 void LIR_OpDelay::print_instr(outputStream* out) const {
2076 _op->print_on(out);
2077 }
2078
2079
2080 // LIR_OpProfileCall
2081 void LIR_OpProfileCall::print_instr(outputStream* out) const {
2082 profiled_method()->name()->print_symbol_on(out);
2083 out->print(".");
2084 profiled_method()->holder()->name()->print_symbol_on(out);
2085 out->print(" @ %d ", profiled_bci());
2086 mdo()->print(out); out->print(" ");
2087 recv()->print(out); out->print(" ");
2088 tmp1()->print(out); out->print(" ");
2089 }
2090
2091 // LIR_OpProfileType
2092 void LIR_OpProfileType::print_instr(outputStream* out) const {
2093 out->print("exact = ");
2094 if (exact_klass() == NULL) {
2095 out->print("unknown");
2096 } else {
2097 exact_klass()->print_name_on(out);
2098 }
2099 out->print(" current = "); ciTypeEntries::print_ciklass(out, current_klass());
2100 out->print(" ");
2101 mdp()->print(out); out->print(" ");
2102 obj()->print(out); out->print(" ");
2103 tmp()->print(out); out->print(" ");
2104 }
2105
2106 #endif // PRODUCT
2107
2108 // Implementation of LIR_InsertionBuffer
2109
2110 void LIR_InsertionBuffer::append(int index, LIR_Op* op) {
2111 assert(_index_and_count.length() % 2 == 0, "must have a count for each index");
2112
2113 int i = number_of_insertion_points() - 1;
2114 if (i < 0 || index_at(i) < index) {
2115 append_new(index, 1);
2116 } else {
2117 assert(index_at(i) == index, "can append LIR_Ops in ascending order only");
2118 assert(count_at(i) > 0, "check");
2119 set_count_at(i, count_at(i) + 1);
2120 }
2121 _ops.push(op);
2122
2123 DEBUG_ONLY(verify());
2124 }
2125
2126 #ifdef ASSERT
2127 void LIR_InsertionBuffer::verify() {
2128 int sum = 0;
2129 int prev_idx = -1;
2130
2131 for (int i = 0; i < number_of_insertion_points(); i++) {
2132 assert(prev_idx < index_at(i), "index must be ordered ascending");
2133 sum += count_at(i);
2134 }
2135 assert(sum == number_of_ops(), "wrong total sum");
2136 }
2137 #endif