1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && (_attributes != NULL) && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x59: // mulpd
776 case 0x6E: // movd
777 case 0x7E: // movd
778 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
779 debug_only(has_disp32 = true);
780 break;
781
782 case 0xAD: // shrd r, a, %cl
783 case 0xAF: // imul r, a
784 case 0xBE: // movsbl r, a (movsxb)
785 case 0xBF: // movswl r, a (movsxw)
786 case 0xB6: // movzbl r, a (movzxb)
787 case 0xB7: // movzwl r, a (movzxw)
788 case REP16(0x40): // cmovl cc, r, a
789 case 0xB0: // cmpxchgb
790 case 0xB1: // cmpxchg
791 case 0xC1: // xaddl
792 case 0xC7: // cmpxchg8
793 case REP16(0x90): // setcc a
794 debug_only(has_disp32 = true);
795 // fall out of the switch to decode the address
796 break;
797
798 case 0xC4: // pinsrw r, a, #8
799 debug_only(has_disp32 = true);
800 case 0xC5: // pextrw r, r, #8
801 tail_size = 1; // the imm8
802 break;
803
804 case 0xAC: // shrd r, a, #8
805 debug_only(has_disp32 = true);
806 tail_size = 1; // the imm8
807 break;
808
809 case REP16(0x80): // jcc rdisp32
810 if (which == end_pc_operand) return ip + 4;
811 assert(which == call32_operand, "jcc has no disp32 or imm");
812 return ip;
813 default:
814 ShouldNotReachHere();
815 }
816 break;
817
818 case 0x81: // addl a, #32; addl r, #32
819 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
820 // on 32bit in the case of cmpl, the imm might be an oop
821 tail_size = 4;
822 debug_only(has_disp32 = true); // has both kinds of operands!
823 break;
824
825 case 0x83: // addl a, #8; addl r, #8
826 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
827 debug_only(has_disp32 = true); // has both kinds of operands!
828 tail_size = 1;
829 break;
830
831 case 0x9B:
832 switch (0xFF & *ip++) {
833 case 0xD9: // fnstcw a
834 debug_only(has_disp32 = true);
835 break;
836 default:
837 ShouldNotReachHere();
838 }
839 break;
840
841 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
842 case REP4(0x10): // adc...
843 case REP4(0x20): // and...
844 case REP4(0x30): // xor...
845 case REP4(0x08): // or...
846 case REP4(0x18): // sbb...
847 case REP4(0x28): // sub...
848 case 0xF7: // mull a
849 case 0x8D: // lea r, a
850 case 0x87: // xchg r, a
851 case REP4(0x38): // cmp...
852 case 0x85: // test r, a
853 debug_only(has_disp32 = true); // has both kinds of operands!
854 break;
855
856 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
857 case 0xC6: // movb a, #8
858 case 0x80: // cmpb a, #8
859 case 0x6B: // imul r, a, #8
860 debug_only(has_disp32 = true); // has both kinds of operands!
861 tail_size = 1; // the imm8
862 break;
863
864 case 0xC4: // VEX_3bytes
865 case 0xC5: // VEX_2bytes
866 assert((UseAVX > 0), "shouldn't have VEX prefix");
867 assert(ip == inst+1, "no prefixes allowed");
868 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
869 // but they have prefix 0x0F and processed when 0x0F processed above.
870 //
871 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
872 // instructions (these instructions are not supported in 64-bit mode).
873 // To distinguish them bits [7:6] are set in the VEX second byte since
874 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
875 // those VEX bits REX and vvvv bits are inverted.
876 //
877 // Fortunately C2 doesn't generate these instructions so we don't need
878 // to check for them in product version.
879
880 // Check second byte
881 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
882
883 int vex_opcode;
884 // First byte
885 if ((0xFF & *inst) == VEX_3bytes) {
886 vex_opcode = VEX_OPCODE_MASK & *ip;
887 ip++; // third byte
888 is_64bit = ((VEX_W & *ip) == VEX_W);
889 } else {
890 vex_opcode = VEX_OPCODE_0F;
891 }
892 ip++; // opcode
893 // To find the end of instruction (which == end_pc_operand).
894 switch (vex_opcode) {
895 case VEX_OPCODE_0F:
896 switch (0xFF & *ip) {
897 case 0x70: // pshufd r, r/a, #8
898 case 0x71: // ps[rl|ra|ll]w r, #8
899 case 0x72: // ps[rl|ra|ll]d r, #8
900 case 0x73: // ps[rl|ra|ll]q r, #8
901 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
902 case 0xC4: // pinsrw r, r, r/a, #8
903 case 0xC5: // pextrw r/a, r, #8
904 case 0xC6: // shufp[s|d] r, r, r/a, #8
905 tail_size = 1; // the imm8
906 break;
907 }
908 break;
909 case VEX_OPCODE_0F_3A:
910 tail_size = 1;
911 break;
912 }
913 ip++; // skip opcode
914 debug_only(has_disp32 = true); // has both kinds of operands!
915 break;
916
917 case 0x62: // EVEX_4bytes
918 assert((UseAVX > 0), "shouldn't have EVEX prefix");
919 assert(ip == inst+1, "no prefixes allowed");
920 // no EVEX collisions, all instructions that have 0x62 opcodes
921 // have EVEX versions and are subopcodes of 0x66
922 ip++; // skip P0 and exmaine W in P1
923 is_64bit = ((VEX_W & *ip) == VEX_W);
924 ip++; // move to P2
925 ip++; // skip P2, move to opcode
926 // To find the end of instruction (which == end_pc_operand).
927 switch (0xFF & *ip) {
928 case 0x61: // pcmpestri r, r/a, #8
929 case 0x70: // pshufd r, r/a, #8
930 case 0x73: // psrldq r, #8
931 tail_size = 1; // the imm8
932 break;
933 default:
934 break;
935 }
936 ip++; // skip opcode
937 debug_only(has_disp32 = true); // has both kinds of operands!
938 break;
939
940 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
941 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
942 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
943 case 0xDD: // fld_d a; fst_d a; fstp_d a
944 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
945 case 0xDF: // fild_d a; fistp_d a
946 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
947 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
948 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
949 debug_only(has_disp32 = true);
950 break;
951
952 case 0xE8: // call rdisp32
953 case 0xE9: // jmp rdisp32
954 if (which == end_pc_operand) return ip + 4;
955 assert(which == call32_operand, "call has no disp32 or imm");
956 return ip;
957
958 case 0xF0: // Lock
959 assert(os::is_MP(), "only on MP");
960 goto again_after_prefix;
961
962 case 0xF3: // For SSE
963 case 0xF2: // For SSE2
964 switch (0xFF & *ip++) {
965 case REX:
966 case REX_B:
967 case REX_X:
968 case REX_XB:
969 case REX_R:
970 case REX_RB:
971 case REX_RX:
972 case REX_RXB:
973 case REX_W:
974 case REX_WB:
975 case REX_WX:
976 case REX_WXB:
977 case REX_WR:
978 case REX_WRB:
979 case REX_WRX:
980 case REX_WRXB:
981 NOT_LP64(assert(false, "found 64bit prefix"));
982 ip++;
983 default:
984 ip++;
985 }
986 debug_only(has_disp32 = true); // has both kinds of operands!
987 break;
988
989 default:
990 ShouldNotReachHere();
991
992 #undef REP8
993 #undef REP16
994 }
995
996 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
997 #ifdef _LP64
998 assert(which != imm_operand, "instruction is not a movq reg, imm64");
999 #else
1000 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1001 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1002 #endif // LP64
1003 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1004
1005 // parse the output of emit_operand
1006 int op2 = 0xFF & *ip++;
1007 int base = op2 & 0x07;
1008 int op3 = -1;
1009 const int b100 = 4;
1010 const int b101 = 5;
1011 if (base == b100 && (op2 >> 6) != 3) {
1012 op3 = 0xFF & *ip++;
1013 base = op3 & 0x07; // refetch the base
1014 }
1015 // now ip points at the disp (if any)
1016
1017 switch (op2 >> 6) {
1018 case 0:
1019 // [00 reg 100][ss index base]
1020 // [00 reg 100][00 100 esp]
1021 // [00 reg base]
1022 // [00 reg 100][ss index 101][disp32]
1023 // [00 reg 101] [disp32]
1024
1025 if (base == b101) {
1026 if (which == disp32_operand)
1027 return ip; // caller wants the disp32
1028 ip += 4; // skip the disp32
1029 }
1030 break;
1031
1032 case 1:
1033 // [01 reg 100][ss index base][disp8]
1034 // [01 reg 100][00 100 esp][disp8]
1035 // [01 reg base] [disp8]
1036 ip += 1; // skip the disp8
1037 break;
1038
1039 case 2:
1040 // [10 reg 100][ss index base][disp32]
1041 // [10 reg 100][00 100 esp][disp32]
1042 // [10 reg base] [disp32]
1043 if (which == disp32_operand)
1044 return ip; // caller wants the disp32
1045 ip += 4; // skip the disp32
1046 break;
1047
1048 case 3:
1049 // [11 reg base] (not a memory addressing mode)
1050 break;
1051 }
1052
1053 if (which == end_pc_operand) {
1054 return ip + tail_size;
1055 }
1056
1057 #ifdef _LP64
1058 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1059 #else
1060 assert(which == imm_operand, "instruction has only an imm field");
1061 #endif // LP64
1062 return ip;
1063 }
1064
1065 address Assembler::locate_next_instruction(address inst) {
1066 // Secretly share code with locate_operand:
1067 return locate_operand(inst, end_pc_operand);
1068 }
1069
1070
1071 #ifdef ASSERT
1072 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1073 address inst = inst_mark();
1074 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1075 address opnd;
1076
1077 Relocation* r = rspec.reloc();
1078 if (r->type() == relocInfo::none) {
1079 return;
1080 } else if (r->is_call() || format == call32_operand) {
1081 // assert(format == imm32_operand, "cannot specify a nonzero format");
1082 opnd = locate_operand(inst, call32_operand);
1083 } else if (r->is_data()) {
1084 assert(format == imm_operand || format == disp32_operand
1085 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1086 opnd = locate_operand(inst, (WhichOperand)format);
1087 } else {
1088 assert(format == imm_operand, "cannot specify a format");
1089 return;
1090 }
1091 assert(opnd == pc(), "must put operand where relocs can find it");
1092 }
1093 #endif // ASSERT
1094
1095 void Assembler::emit_operand32(Register reg, Address adr) {
1096 assert(reg->encoding() < 8, "no extended registers");
1097 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1098 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1099 adr._rspec);
1100 }
1101
1102 void Assembler::emit_operand(Register reg, Address adr,
1103 int rip_relative_correction) {
1104 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1105 adr._rspec,
1106 rip_relative_correction);
1107 }
1108
1109 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1110 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1111 adr._rspec);
1112 }
1113
1114 // MMX operations
1115 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1116 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1117 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1118 }
1119
1120 // work around gcc (3.2.1-7a) bug
1121 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1122 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1123 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1124 }
1125
1126
1127 void Assembler::emit_farith(int b1, int b2, int i) {
1128 assert(isByte(b1) && isByte(b2), "wrong opcode");
1129 assert(0 <= i && i < 8, "illegal stack offset");
1130 emit_int8(b1);
1131 emit_int8(b2 + i);
1132 }
1133
1134
1135 // Now the Assembler instructions (identical for 32/64 bits)
1136
1137 void Assembler::adcl(Address dst, int32_t imm32) {
1138 InstructionMark im(this);
1139 prefix(dst);
1140 emit_arith_operand(0x81, rdx, dst, imm32);
1141 }
1142
1143 void Assembler::adcl(Address dst, Register src) {
1144 InstructionMark im(this);
1145 prefix(dst, src);
1146 emit_int8(0x11);
1147 emit_operand(src, dst);
1148 }
1149
1150 void Assembler::adcl(Register dst, int32_t imm32) {
1151 prefix(dst);
1152 emit_arith(0x81, 0xD0, dst, imm32);
1153 }
1154
1155 void Assembler::adcl(Register dst, Address src) {
1156 InstructionMark im(this);
1157 prefix(src, dst);
1158 emit_int8(0x13);
1159 emit_operand(dst, src);
1160 }
1161
1162 void Assembler::adcl(Register dst, Register src) {
1163 (void) prefix_and_encode(dst->encoding(), src->encoding());
1164 emit_arith(0x13, 0xC0, dst, src);
1165 }
1166
1167 void Assembler::addl(Address dst, int32_t imm32) {
1168 InstructionMark im(this);
1169 prefix(dst);
1170 emit_arith_operand(0x81, rax, dst, imm32);
1171 }
1172
1173 void Assembler::addl(Address dst, Register src) {
1174 InstructionMark im(this);
1175 prefix(dst, src);
1176 emit_int8(0x01);
1177 emit_operand(src, dst);
1178 }
1179
1180 void Assembler::addl(Register dst, int32_t imm32) {
1181 prefix(dst);
1182 emit_arith(0x81, 0xC0, dst, imm32);
1183 }
1184
1185 void Assembler::addl(Register dst, Address src) {
1186 InstructionMark im(this);
1187 prefix(src, dst);
1188 emit_int8(0x03);
1189 emit_operand(dst, src);
1190 }
1191
1192 void Assembler::addl(Register dst, Register src) {
1193 (void) prefix_and_encode(dst->encoding(), src->encoding());
1194 emit_arith(0x03, 0xC0, dst, src);
1195 }
1196
1197 void Assembler::addr_nop_4() {
1198 assert(UseAddressNop, "no CPU support");
1199 // 4 bytes: NOP DWORD PTR [EAX+0]
1200 emit_int8(0x0F);
1201 emit_int8(0x1F);
1202 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1203 emit_int8(0); // 8-bits offset (1 byte)
1204 }
1205
1206 void Assembler::addr_nop_5() {
1207 assert(UseAddressNop, "no CPU support");
1208 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1209 emit_int8(0x0F);
1210 emit_int8(0x1F);
1211 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1212 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1213 emit_int8(0); // 8-bits offset (1 byte)
1214 }
1215
1216 void Assembler::addr_nop_7() {
1217 assert(UseAddressNop, "no CPU support");
1218 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1219 emit_int8(0x0F);
1220 emit_int8(0x1F);
1221 emit_int8((unsigned char)0x80);
1222 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1223 emit_int32(0); // 32-bits offset (4 bytes)
1224 }
1225
1226 void Assembler::addr_nop_8() {
1227 assert(UseAddressNop, "no CPU support");
1228 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1229 emit_int8(0x0F);
1230 emit_int8(0x1F);
1231 emit_int8((unsigned char)0x84);
1232 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1233 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1234 emit_int32(0); // 32-bits offset (4 bytes)
1235 }
1236
1237 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1238 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1239 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1240 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1241 emit_int8(0x58);
1242 emit_int8((unsigned char)(0xC0 | encode));
1243 }
1244
1245 void Assembler::addsd(XMMRegister dst, Address src) {
1246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1247 InstructionMark im(this);
1248 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1249 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1250 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1251 emit_int8(0x58);
1252 emit_operand(dst, src);
1253 }
1254
1255 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1256 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1257 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1258 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1259 emit_int8(0x58);
1260 emit_int8((unsigned char)(0xC0 | encode));
1261 }
1262
1263 void Assembler::addss(XMMRegister dst, Address src) {
1264 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1265 InstructionMark im(this);
1266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1267 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1268 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1269 emit_int8(0x58);
1270 emit_operand(dst, src);
1271 }
1272
1273 void Assembler::aesdec(XMMRegister dst, Address src) {
1274 assert(VM_Version::supports_aes(), "");
1275 InstructionMark im(this);
1276 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1277 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1278 emit_int8((unsigned char)0xDE);
1279 emit_operand(dst, src);
1280 }
1281
1282 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1283 assert(VM_Version::supports_aes(), "");
1284 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1285 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1286 emit_int8((unsigned char)0xDE);
1287 emit_int8(0xC0 | encode);
1288 }
1289
1290 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1291 assert(VM_Version::supports_aes(), "");
1292 InstructionMark im(this);
1293 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1294 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1295 emit_int8((unsigned char)0xDF);
1296 emit_operand(dst, src);
1297 }
1298
1299 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1300 assert(VM_Version::supports_aes(), "");
1301 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1302 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1303 emit_int8((unsigned char)0xDF);
1304 emit_int8((unsigned char)(0xC0 | encode));
1305 }
1306
1307 void Assembler::aesenc(XMMRegister dst, Address src) {
1308 assert(VM_Version::supports_aes(), "");
1309 InstructionMark im(this);
1310 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1311 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1312 emit_int8((unsigned char)0xDC);
1313 emit_operand(dst, src);
1314 }
1315
1316 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1317 assert(VM_Version::supports_aes(), "");
1318 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1319 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1320 emit_int8((unsigned char)0xDC);
1321 emit_int8(0xC0 | encode);
1322 }
1323
1324 void Assembler::aesenclast(XMMRegister dst, Address src) {
1325 assert(VM_Version::supports_aes(), "");
1326 InstructionMark im(this);
1327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1328 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1329 emit_int8((unsigned char)0xDD);
1330 emit_operand(dst, src);
1331 }
1332
1333 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1334 assert(VM_Version::supports_aes(), "");
1335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1336 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1337 emit_int8((unsigned char)0xDD);
1338 emit_int8((unsigned char)(0xC0 | encode));
1339 }
1340
1341 void Assembler::andl(Address dst, int32_t imm32) {
1342 InstructionMark im(this);
1343 prefix(dst);
1344 emit_int8((unsigned char)0x81);
1345 emit_operand(rsp, dst, 4);
1346 emit_int32(imm32);
1347 }
1348
1349 void Assembler::andl(Register dst, int32_t imm32) {
1350 prefix(dst);
1351 emit_arith(0x81, 0xE0, dst, imm32);
1352 }
1353
1354 void Assembler::andl(Register dst, Address src) {
1355 InstructionMark im(this);
1356 prefix(src, dst);
1357 emit_int8(0x23);
1358 emit_operand(dst, src);
1359 }
1360
1361 void Assembler::andl(Register dst, Register src) {
1362 (void) prefix_and_encode(dst->encoding(), src->encoding());
1363 emit_arith(0x23, 0xC0, dst, src);
1364 }
1365
1366 void Assembler::andnl(Register dst, Register src1, Register src2) {
1367 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1368 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1369 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1370 emit_int8((unsigned char)0xF2);
1371 emit_int8((unsigned char)(0xC0 | encode));
1372 }
1373
1374 void Assembler::andnl(Register dst, Register src1, Address src2) {
1375 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1376 InstructionMark im(this);
1377 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1378 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1379 emit_int8((unsigned char)0xF2);
1380 emit_operand(dst, src2);
1381 }
1382
1383 void Assembler::bsfl(Register dst, Register src) {
1384 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1385 emit_int8(0x0F);
1386 emit_int8((unsigned char)0xBC);
1387 emit_int8((unsigned char)(0xC0 | encode));
1388 }
1389
1390 void Assembler::bsrl(Register dst, Register src) {
1391 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1392 emit_int8(0x0F);
1393 emit_int8((unsigned char)0xBD);
1394 emit_int8((unsigned char)(0xC0 | encode));
1395 }
1396
1397 void Assembler::bswapl(Register reg) { // bswap
1398 int encode = prefix_and_encode(reg->encoding());
1399 emit_int8(0x0F);
1400 emit_int8((unsigned char)(0xC8 | encode));
1401 }
1402
1403 void Assembler::blsil(Register dst, Register src) {
1404 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1405 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1406 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1407 emit_int8((unsigned char)0xF3);
1408 emit_int8((unsigned char)(0xC0 | encode));
1409 }
1410
1411 void Assembler::blsil(Register dst, Address src) {
1412 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1413 InstructionMark im(this);
1414 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1415 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1416 emit_int8((unsigned char)0xF3);
1417 emit_operand(rbx, src);
1418 }
1419
1420 void Assembler::blsmskl(Register dst, Register src) {
1421 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1422 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1423 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1424 emit_int8((unsigned char)0xF3);
1425 emit_int8((unsigned char)(0xC0 | encode));
1426 }
1427
1428 void Assembler::blsmskl(Register dst, Address src) {
1429 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1430 InstructionMark im(this);
1431 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1432 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1433 emit_int8((unsigned char)0xF3);
1434 emit_operand(rdx, src);
1435 }
1436
1437 void Assembler::blsrl(Register dst, Register src) {
1438 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1439 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1440 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1441 emit_int8((unsigned char)0xF3);
1442 emit_int8((unsigned char)(0xC0 | encode));
1443 }
1444
1445 void Assembler::blsrl(Register dst, Address src) {
1446 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1447 InstructionMark im(this);
1448 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1449 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1450 emit_int8((unsigned char)0xF3);
1451 emit_operand(rcx, src);
1452 }
1453
1454 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1455 // suspect disp32 is always good
1456 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1457
1458 if (L.is_bound()) {
1459 const int long_size = 5;
1460 int offs = (int)( target(L) - pc() );
1461 assert(offs <= 0, "assembler error");
1462 InstructionMark im(this);
1463 // 1110 1000 #32-bit disp
1464 emit_int8((unsigned char)0xE8);
1465 emit_data(offs - long_size, rtype, operand);
1466 } else {
1467 InstructionMark im(this);
1468 // 1110 1000 #32-bit disp
1469 L.add_patch_at(code(), locator());
1470
1471 emit_int8((unsigned char)0xE8);
1472 emit_data(int(0), rtype, operand);
1473 }
1474 }
1475
1476 void Assembler::call(Register dst) {
1477 int encode = prefix_and_encode(dst->encoding());
1478 emit_int8((unsigned char)0xFF);
1479 emit_int8((unsigned char)(0xD0 | encode));
1480 }
1481
1482
1483 void Assembler::call(Address adr) {
1484 InstructionMark im(this);
1485 prefix(adr);
1486 emit_int8((unsigned char)0xFF);
1487 emit_operand(rdx, adr);
1488 }
1489
1490 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1491 assert(entry != NULL, "call most probably wrong");
1492 InstructionMark im(this);
1493 emit_int8((unsigned char)0xE8);
1494 intptr_t disp = entry - (pc() + sizeof(int32_t));
1495 assert(is_simm32(disp), "must be 32bit offset (call2)");
1496 // Technically, should use call32_operand, but this format is
1497 // implied by the fact that we're emitting a call instruction.
1498
1499 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1500 emit_data((int) disp, rspec, operand);
1501 }
1502
1503 void Assembler::cdql() {
1504 emit_int8((unsigned char)0x99);
1505 }
1506
1507 void Assembler::cld() {
1508 emit_int8((unsigned char)0xFC);
1509 }
1510
1511 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1512 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1513 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1514 emit_int8(0x0F);
1515 emit_int8(0x40 | cc);
1516 emit_int8((unsigned char)(0xC0 | encode));
1517 }
1518
1519
1520 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1521 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1522 prefix(src, dst);
1523 emit_int8(0x0F);
1524 emit_int8(0x40 | cc);
1525 emit_operand(dst, src);
1526 }
1527
1528 void Assembler::cmpb(Address dst, int imm8) {
1529 InstructionMark im(this);
1530 prefix(dst);
1531 emit_int8((unsigned char)0x80);
1532 emit_operand(rdi, dst, 1);
1533 emit_int8(imm8);
1534 }
1535
1536 void Assembler::cmpl(Address dst, int32_t imm32) {
1537 InstructionMark im(this);
1538 prefix(dst);
1539 emit_int8((unsigned char)0x81);
1540 emit_operand(rdi, dst, 4);
1541 emit_int32(imm32);
1542 }
1543
1544 void Assembler::cmpl(Register dst, int32_t imm32) {
1545 prefix(dst);
1546 emit_arith(0x81, 0xF8, dst, imm32);
1547 }
1548
1549 void Assembler::cmpl(Register dst, Register src) {
1550 (void) prefix_and_encode(dst->encoding(), src->encoding());
1551 emit_arith(0x3B, 0xC0, dst, src);
1552 }
1553
1554 void Assembler::cmpl(Register dst, Address src) {
1555 InstructionMark im(this);
1556 prefix(src, dst);
1557 emit_int8((unsigned char)0x3B);
1558 emit_operand(dst, src);
1559 }
1560
1561 void Assembler::cmpw(Address dst, int imm16) {
1562 InstructionMark im(this);
1563 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1564 emit_int8(0x66);
1565 emit_int8((unsigned char)0x81);
1566 emit_operand(rdi, dst, 2);
1567 emit_int16(imm16);
1568 }
1569
1570 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1571 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1572 // The ZF is set if the compared values were equal, and cleared otherwise.
1573 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1574 InstructionMark im(this);
1575 prefix(adr, reg);
1576 emit_int8(0x0F);
1577 emit_int8((unsigned char)0xB1);
1578 emit_operand(reg, adr);
1579 }
1580
1581 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1582 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1583 // The ZF is set if the compared values were equal, and cleared otherwise.
1584 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1585 InstructionMark im(this);
1586 prefix(adr, reg, true);
1587 emit_int8(0x0F);
1588 emit_int8((unsigned char)0xB0);
1589 emit_operand(reg, adr);
1590 }
1591
1592 void Assembler::comisd(XMMRegister dst, Address src) {
1593 // NOTE: dbx seems to decode this as comiss even though the
1594 // 0x66 is there. Strangly ucomisd comes out correct
1595 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1596 InstructionMark im(this);
1597 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1598 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1599 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1600 emit_int8(0x2F);
1601 emit_operand(dst, src);
1602 }
1603
1604 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1606 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1607 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1608 emit_int8(0x2F);
1609 emit_int8((unsigned char)(0xC0 | encode));
1610 }
1611
1612 void Assembler::comiss(XMMRegister dst, Address src) {
1613 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1614 InstructionMark im(this);
1615 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1616 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1617 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1618 emit_int8(0x2F);
1619 emit_operand(dst, src);
1620 }
1621
1622 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1623 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1624 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1625 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1626 emit_int8(0x2F);
1627 emit_int8((unsigned char)(0xC0 | encode));
1628 }
1629
1630 void Assembler::cpuid() {
1631 emit_int8(0x0F);
1632 emit_int8((unsigned char)0xA2);
1633 }
1634
1635 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1636 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1637 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1638 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1639 //
1640 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1641 //
1642 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1643 //
1644 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1645 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1646 assert(VM_Version::supports_sse4_2(), "");
1647 int8_t w = 0x01;
1648 Prefix p = Prefix_EMPTY;
1649
1650 emit_int8((int8_t)0xF2);
1651 switch (sizeInBytes) {
1652 case 1:
1653 w = 0;
1654 break;
1655 case 2:
1656 case 4:
1657 break;
1658 LP64_ONLY(case 8:)
1659 // This instruction is not valid in 32 bits
1660 // Note:
1661 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1662 //
1663 // Page B - 72 Vol. 2C says
1664 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1665 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1666 // F0!!!
1667 // while 3 - 208 Vol. 2A
1668 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1669 //
1670 // the 0 on a last bit is reserved for a different flavor of this instruction :
1671 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1672 p = REX_W;
1673 break;
1674 default:
1675 assert(0, "Unsupported value for a sizeInBytes argument");
1676 break;
1677 }
1678 LP64_ONLY(prefix(crc, v, p);)
1679 emit_int8((int8_t)0x0F);
1680 emit_int8(0x38);
1681 emit_int8((int8_t)(0xF0 | w));
1682 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1683 }
1684
1685 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1686 assert(VM_Version::supports_sse4_2(), "");
1687 InstructionMark im(this);
1688 int8_t w = 0x01;
1689 Prefix p = Prefix_EMPTY;
1690
1691 emit_int8((int8_t)0xF2);
1692 switch (sizeInBytes) {
1693 case 1:
1694 w = 0;
1695 break;
1696 case 2:
1697 case 4:
1698 break;
1699 LP64_ONLY(case 8:)
1700 // This instruction is not valid in 32 bits
1701 p = REX_W;
1702 break;
1703 default:
1704 assert(0, "Unsupported value for a sizeInBytes argument");
1705 break;
1706 }
1707 LP64_ONLY(prefix(crc, adr, p);)
1708 emit_int8((int8_t)0x0F);
1709 emit_int8(0x38);
1710 emit_int8((int8_t)(0xF0 | w));
1711 emit_operand(crc, adr);
1712 }
1713
1714 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1715 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1717 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1718 emit_int8((unsigned char)0xE6);
1719 emit_int8((unsigned char)(0xC0 | encode));
1720 }
1721
1722 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1723 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1724 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1725 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1726 emit_int8(0x5B);
1727 emit_int8((unsigned char)(0xC0 | encode));
1728 }
1729
1730 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1731 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1732 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1733 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1734 emit_int8(0x5A);
1735 emit_int8((unsigned char)(0xC0 | encode));
1736 }
1737
1738 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1739 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1740 InstructionMark im(this);
1741 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1742 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1743 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1744 emit_int8(0x5A);
1745 emit_operand(dst, src);
1746 }
1747
1748 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1750 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1751 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1752 emit_int8(0x2A);
1753 emit_int8((unsigned char)(0xC0 | encode));
1754 }
1755
1756 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1758 InstructionMark im(this);
1759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1760 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1761 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1762 emit_int8(0x2A);
1763 emit_operand(dst, src);
1764 }
1765
1766 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1767 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1768 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1769 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1770 emit_int8(0x2A);
1771 emit_int8((unsigned char)(0xC0 | encode));
1772 }
1773
1774 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1775 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1776 InstructionMark im(this);
1777 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1778 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1779 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1780 emit_int8(0x2A);
1781 emit_operand(dst, src);
1782 }
1783
1784 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1785 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1786 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1787 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1788 emit_int8(0x2A);
1789 emit_int8((unsigned char)(0xC0 | encode));
1790 }
1791
1792 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1793 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1795 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1796 emit_int8(0x5A);
1797 emit_int8((unsigned char)(0xC0 | encode));
1798 }
1799
1800 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1801 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1802 InstructionMark im(this);
1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1806 emit_int8(0x5A);
1807 emit_operand(dst, src);
1808 }
1809
1810
1811 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1812 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1813 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1814 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1815 emit_int8(0x2C);
1816 emit_int8((unsigned char)(0xC0 | encode));
1817 }
1818
1819 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1820 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1822 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1823 emit_int8(0x2C);
1824 emit_int8((unsigned char)(0xC0 | encode));
1825 }
1826
1827 void Assembler::decl(Address dst) {
1828 // Don't use it directly. Use MacroAssembler::decrement() instead.
1829 InstructionMark im(this);
1830 prefix(dst);
1831 emit_int8((unsigned char)0xFF);
1832 emit_operand(rcx, dst);
1833 }
1834
1835 void Assembler::divsd(XMMRegister dst, Address src) {
1836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1837 InstructionMark im(this);
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1840 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1841 emit_int8(0x5E);
1842 emit_operand(dst, src);
1843 }
1844
1845 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1846 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1848 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1849 emit_int8(0x5E);
1850 emit_int8((unsigned char)(0xC0 | encode));
1851 }
1852
1853 void Assembler::divss(XMMRegister dst, Address src) {
1854 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1855 InstructionMark im(this);
1856 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1857 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1858 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1859 emit_int8(0x5E);
1860 emit_operand(dst, src);
1861 }
1862
1863 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1864 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1865 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1866 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1867 emit_int8(0x5E);
1868 emit_int8((unsigned char)(0xC0 | encode));
1869 }
1870
1871 void Assembler::emms() {
1872 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1873 emit_int8(0x0F);
1874 emit_int8(0x77);
1875 }
1876
1877 void Assembler::hlt() {
1878 emit_int8((unsigned char)0xF4);
1879 }
1880
1881 void Assembler::idivl(Register src) {
1882 int encode = prefix_and_encode(src->encoding());
1883 emit_int8((unsigned char)0xF7);
1884 emit_int8((unsigned char)(0xF8 | encode));
1885 }
1886
1887 void Assembler::divl(Register src) { // Unsigned
1888 int encode = prefix_and_encode(src->encoding());
1889 emit_int8((unsigned char)0xF7);
1890 emit_int8((unsigned char)(0xF0 | encode));
1891 }
1892
1893 void Assembler::imull(Register dst, Register src) {
1894 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1895 emit_int8(0x0F);
1896 emit_int8((unsigned char)0xAF);
1897 emit_int8((unsigned char)(0xC0 | encode));
1898 }
1899
1900
1901 void Assembler::imull(Register dst, Register src, int value) {
1902 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1903 if (is8bit(value)) {
1904 emit_int8(0x6B);
1905 emit_int8((unsigned char)(0xC0 | encode));
1906 emit_int8(value & 0xFF);
1907 } else {
1908 emit_int8(0x69);
1909 emit_int8((unsigned char)(0xC0 | encode));
1910 emit_int32(value);
1911 }
1912 }
1913
1914 void Assembler::imull(Register dst, Address src) {
1915 InstructionMark im(this);
1916 prefix(src, dst);
1917 emit_int8(0x0F);
1918 emit_int8((unsigned char) 0xAF);
1919 emit_operand(dst, src);
1920 }
1921
1922
1923 void Assembler::incl(Address dst) {
1924 // Don't use it directly. Use MacroAssembler::increment() instead.
1925 InstructionMark im(this);
1926 prefix(dst);
1927 emit_int8((unsigned char)0xFF);
1928 emit_operand(rax, dst);
1929 }
1930
1931 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1932 InstructionMark im(this);
1933 assert((0 <= cc) && (cc < 16), "illegal cc");
1934 if (L.is_bound()) {
1935 address dst = target(L);
1936 assert(dst != NULL, "jcc most probably wrong");
1937
1938 const int short_size = 2;
1939 const int long_size = 6;
1940 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1941 if (maybe_short && is8bit(offs - short_size)) {
1942 // 0111 tttn #8-bit disp
1943 emit_int8(0x70 | cc);
1944 emit_int8((offs - short_size) & 0xFF);
1945 } else {
1946 // 0000 1111 1000 tttn #32-bit disp
1947 assert(is_simm32(offs - long_size),
1948 "must be 32bit offset (call4)");
1949 emit_int8(0x0F);
1950 emit_int8((unsigned char)(0x80 | cc));
1951 emit_int32(offs - long_size);
1952 }
1953 } else {
1954 // Note: could eliminate cond. jumps to this jump if condition
1955 // is the same however, seems to be rather unlikely case.
1956 // Note: use jccb() if label to be bound is very close to get
1957 // an 8-bit displacement
1958 L.add_patch_at(code(), locator());
1959 emit_int8(0x0F);
1960 emit_int8((unsigned char)(0x80 | cc));
1961 emit_int32(0);
1962 }
1963 }
1964
1965 void Assembler::jccb(Condition cc, Label& L) {
1966 if (L.is_bound()) {
1967 const int short_size = 2;
1968 address entry = target(L);
1969 #ifdef ASSERT
1970 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1971 intptr_t delta = short_branch_delta();
1972 if (delta != 0) {
1973 dist += (dist < 0 ? (-delta) :delta);
1974 }
1975 assert(is8bit(dist), "Dispacement too large for a short jmp");
1976 #endif
1977 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1978 // 0111 tttn #8-bit disp
1979 emit_int8(0x70 | cc);
1980 emit_int8((offs - short_size) & 0xFF);
1981 } else {
1982 InstructionMark im(this);
1983 L.add_patch_at(code(), locator());
1984 emit_int8(0x70 | cc);
1985 emit_int8(0);
1986 }
1987 }
1988
1989 void Assembler::jmp(Address adr) {
1990 InstructionMark im(this);
1991 prefix(adr);
1992 emit_int8((unsigned char)0xFF);
1993 emit_operand(rsp, adr);
1994 }
1995
1996 void Assembler::jmp(Label& L, bool maybe_short) {
1997 if (L.is_bound()) {
1998 address entry = target(L);
1999 assert(entry != NULL, "jmp most probably wrong");
2000 InstructionMark im(this);
2001 const int short_size = 2;
2002 const int long_size = 5;
2003 intptr_t offs = entry - pc();
2004 if (maybe_short && is8bit(offs - short_size)) {
2005 emit_int8((unsigned char)0xEB);
2006 emit_int8((offs - short_size) & 0xFF);
2007 } else {
2008 emit_int8((unsigned char)0xE9);
2009 emit_int32(offs - long_size);
2010 }
2011 } else {
2012 // By default, forward jumps are always 32-bit displacements, since
2013 // we can't yet know where the label will be bound. If you're sure that
2014 // the forward jump will not run beyond 256 bytes, use jmpb to
2015 // force an 8-bit displacement.
2016 InstructionMark im(this);
2017 L.add_patch_at(code(), locator());
2018 emit_int8((unsigned char)0xE9);
2019 emit_int32(0);
2020 }
2021 }
2022
2023 void Assembler::jmp(Register entry) {
2024 int encode = prefix_and_encode(entry->encoding());
2025 emit_int8((unsigned char)0xFF);
2026 emit_int8((unsigned char)(0xE0 | encode));
2027 }
2028
2029 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2030 InstructionMark im(this);
2031 emit_int8((unsigned char)0xE9);
2032 assert(dest != NULL, "must have a target");
2033 intptr_t disp = dest - (pc() + sizeof(int32_t));
2034 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2035 emit_data(disp, rspec.reloc(), call32_operand);
2036 }
2037
2038 void Assembler::jmpb(Label& L) {
2039 if (L.is_bound()) {
2040 const int short_size = 2;
2041 address entry = target(L);
2042 assert(entry != NULL, "jmp most probably wrong");
2043 #ifdef ASSERT
2044 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2045 intptr_t delta = short_branch_delta();
2046 if (delta != 0) {
2047 dist += (dist < 0 ? (-delta) :delta);
2048 }
2049 assert(is8bit(dist), "Dispacement too large for a short jmp");
2050 #endif
2051 intptr_t offs = entry - pc();
2052 emit_int8((unsigned char)0xEB);
2053 emit_int8((offs - short_size) & 0xFF);
2054 } else {
2055 InstructionMark im(this);
2056 L.add_patch_at(code(), locator());
2057 emit_int8((unsigned char)0xEB);
2058 emit_int8(0);
2059 }
2060 }
2061
2062 void Assembler::ldmxcsr( Address src) {
2063 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2064 InstructionMark im(this);
2065 prefix(src);
2066 emit_int8(0x0F);
2067 emit_int8((unsigned char)0xAE);
2068 emit_operand(as_Register(2), src);
2069 }
2070
2071 void Assembler::leal(Register dst, Address src) {
2072 InstructionMark im(this);
2073 #ifdef _LP64
2074 emit_int8(0x67); // addr32
2075 prefix(src, dst);
2076 #endif // LP64
2077 emit_int8((unsigned char)0x8D);
2078 emit_operand(dst, src);
2079 }
2080
2081 void Assembler::lfence() {
2082 emit_int8(0x0F);
2083 emit_int8((unsigned char)0xAE);
2084 emit_int8((unsigned char)0xE8);
2085 }
2086
2087 void Assembler::lock() {
2088 emit_int8((unsigned char)0xF0);
2089 }
2090
2091 void Assembler::lzcntl(Register dst, Register src) {
2092 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2093 emit_int8((unsigned char)0xF3);
2094 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2095 emit_int8(0x0F);
2096 emit_int8((unsigned char)0xBD);
2097 emit_int8((unsigned char)(0xC0 | encode));
2098 }
2099
2100 // Emit mfence instruction
2101 void Assembler::mfence() {
2102 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2103 emit_int8(0x0F);
2104 emit_int8((unsigned char)0xAE);
2105 emit_int8((unsigned char)0xF0);
2106 }
2107
2108 void Assembler::mov(Register dst, Register src) {
2109 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2110 }
2111
2112 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2114 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2115 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2116 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2117 emit_int8(0x28);
2118 emit_int8((unsigned char)(0xC0 | encode));
2119 }
2120
2121 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2123 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2124 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2125 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2126 emit_int8(0x28);
2127 emit_int8((unsigned char)(0xC0 | encode));
2128 }
2129
2130 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2131 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2132 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2133 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2134 emit_int8(0x16);
2135 emit_int8((unsigned char)(0xC0 | encode));
2136 }
2137
2138 void Assembler::movb(Register dst, Address src) {
2139 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2140 InstructionMark im(this);
2141 prefix(src, dst, true);
2142 emit_int8((unsigned char)0x8A);
2143 emit_operand(dst, src);
2144 }
2145
2146 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2147 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2148 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
2149 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2150 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2151 emit_int8(0x12);
2152 emit_int8(0xC0 | encode);
2153 }
2154
2155 void Assembler::kmovwl(KRegister dst, Register src) {
2156 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2157 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2158 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2159 emit_int8((unsigned char)0x92);
2160 emit_int8((unsigned char)(0xC0 | encode));
2161 }
2162
2163 void Assembler::kmovdl(KRegister dst, Register src) {
2164 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2165 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2166 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2167 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, VEX_OPCODE_0F, &attributes);
2168 emit_int8((unsigned char)0x92);
2169 emit_int8((unsigned char)(0xC0 | encode));
2170 }
2171
2172 void Assembler::kmovql(KRegister dst, KRegister src) {
2173 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2174 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2175 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2176 emit_int8((unsigned char)0x90);
2177 emit_int8((unsigned char)(0xC0 | encode));
2178 }
2179
2180 void Assembler::kmovql(KRegister dst, Address src) {
2181 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2182 InstructionMark im(this);
2183 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2184 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2185 emit_int8((unsigned char)0x90);
2186 emit_operand((Register)dst, src);
2187 }
2188
2189 void Assembler::kmovql(Address dst, KRegister src) {
2190 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2191 InstructionMark im(this);
2192 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2193 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2194 emit_int8((unsigned char)0x90);
2195 emit_operand((Register)src, dst);
2196 }
2197
2198 void Assembler::kmovql(KRegister dst, Register src) {
2199 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2200 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2201 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_bw, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2202 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, VEX_OPCODE_0F, &attributes);
2203 emit_int8((unsigned char)0x92);
2204 emit_int8((unsigned char)(0xC0 | encode));
2205 }
2206
2207 // This instruction produces ZF or CF flags
2208 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2209 NOT_LP64(assert(VM_Version::supports_avx512dq(), ""));
2210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2211 int encode = kreg_prefix_and_encode(src1, knoreg, src2, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2212 emit_int8((unsigned char)0x98);
2213 emit_int8((unsigned char)(0xC0 | encode));
2214 }
2215
2216 // This instruction produces ZF or CF flags
2217 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2218 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2219 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2220 int encode = kreg_prefix_and_encode(src1, knoreg, src2, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2221 emit_int8((unsigned char)0x98);
2222 emit_int8((unsigned char)(0xC0 | encode));
2223 }
2224
2225 // This instruction produces ZF or CF flags
2226 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2227 NOT_LP64(assert(VM_Version::supports_avx512bw(), ""));
2228 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2229 int encode = kreg_prefix_and_encode(src1, knoreg, src2, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2230 emit_int8((unsigned char)0x98);
2231 emit_int8((unsigned char)(0xC0 | encode));
2232 }
2233
2234 // This instruction produces ZF or CF flags
2235 void Assembler::kortestql(KRegister src1, KRegister src2) {
2236 NOT_LP64(assert(VM_Version::supports_avx512bw(), ""));
2237 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2238 int encode = kreg_prefix_and_encode(src1, knoreg, src2, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2239 emit_int8((unsigned char)0x98);
2240 emit_int8((unsigned char)(0xC0 | encode));
2241 }
2242
2243 void Assembler::movb(Address dst, int imm8) {
2244 InstructionMark im(this);
2245 prefix(dst);
2246 emit_int8((unsigned char)0xC6);
2247 emit_operand(rax, dst, 1);
2248 emit_int8(imm8);
2249 }
2250
2251
2252 void Assembler::movb(Address dst, Register src) {
2253 assert(src->has_byte_register(), "must have byte register");
2254 InstructionMark im(this);
2255 prefix(dst, src, true);
2256 emit_int8((unsigned char)0x88);
2257 emit_operand(src, dst);
2258 }
2259
2260 void Assembler::movdl(XMMRegister dst, Register src) {
2261 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2263 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2264 emit_int8(0x6E);
2265 emit_int8((unsigned char)(0xC0 | encode));
2266 }
2267
2268 void Assembler::movdl(Register dst, XMMRegister src) {
2269 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2270 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2271 // swap src/dst to get correct prefix
2272 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2273 emit_int8(0x7E);
2274 emit_int8((unsigned char)(0xC0 | encode));
2275 }
2276
2277 void Assembler::movdl(XMMRegister dst, Address src) {
2278 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2279 InstructionMark im(this);
2280 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2281 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2282 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2283 emit_int8(0x6E);
2284 emit_operand(dst, src);
2285 }
2286
2287 void Assembler::movdl(Address dst, XMMRegister src) {
2288 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2289 InstructionMark im(this);
2290 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2291 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2292 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2293 emit_int8(0x7E);
2294 emit_operand(src, dst);
2295 }
2296
2297 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2298 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2299 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2300 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2301 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2302 emit_int8(0x6F);
2303 emit_int8((unsigned char)(0xC0 | encode));
2304 }
2305
2306 void Assembler::movdqa(XMMRegister dst, Address src) {
2307 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2308 InstructionMark im(this);
2309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2310 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2311 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2312 emit_int8(0x6F);
2313 emit_operand(dst, src);
2314 }
2315
2316 void Assembler::movdqu(XMMRegister dst, Address src) {
2317 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2318 InstructionMark im(this);
2319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2320 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2321 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2322 emit_int8(0x6F);
2323 emit_operand(dst, src);
2324 }
2325
2326 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2327 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2328 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2329 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2330 emit_int8(0x6F);
2331 emit_int8((unsigned char)(0xC0 | encode));
2332 }
2333
2334 void Assembler::movdqu(Address dst, XMMRegister src) {
2335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2336 InstructionMark im(this);
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2338 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2339 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2340 emit_int8(0x7F);
2341 emit_operand(src, dst);
2342 }
2343
2344 // Move Unaligned 256bit Vector
2345 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2346 assert(UseAVX > 0, "");
2347 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2348 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2349 emit_int8(0x6F);
2350 emit_int8((unsigned char)(0xC0 | encode));
2351 }
2352
2353 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2354 assert(UseAVX > 0, "");
2355 InstructionMark im(this);
2356 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2357 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2358 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2359 emit_int8(0x6F);
2360 emit_operand(dst, src);
2361 }
2362
2363 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2364 assert(UseAVX > 0, "");
2365 InstructionMark im(this);
2366 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2367 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2368 // swap src<->dst for encoding
2369 assert(src != xnoreg, "sanity");
2370 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2371 emit_int8(0x7F);
2372 emit_operand(src, dst);
2373 }
2374
2375 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2376 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2377 assert(VM_Version::supports_evex(), "");
2378 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2379 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2380 emit_int8(0x6F);
2381 emit_int8((unsigned char)(0xC0 | encode));
2382 }
2383
2384 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2385 assert(VM_Version::supports_evex(), "");
2386 InstructionMark im(this);
2387 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2388 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2389 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2390 emit_int8(0x6F);
2391 emit_operand(dst, src);
2392 }
2393
2394 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2395 assert(VM_Version::supports_evex(), "");
2396 assert(src != xnoreg, "sanity");
2397 InstructionMark im(this);
2398 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2399 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2400 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2401 emit_int8(0x7F);
2402 emit_operand(src, dst);
2403 }
2404
2405 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2406 assert(VM_Version::supports_evex(), "");
2407 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2408 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2409 emit_int8(0x6F);
2410 emit_int8((unsigned char)(0xC0 | encode));
2411 }
2412
2413 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2414 assert(VM_Version::supports_evex(), "");
2415 InstructionMark im(this);
2416 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2417 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2418 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2419 emit_int8(0x6F);
2420 emit_operand(dst, src);
2421 }
2422
2423 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2424 assert(VM_Version::supports_evex(), "");
2425 assert(src != xnoreg, "sanity");
2426 InstructionMark im(this);
2427 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2428 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2429 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2430 emit_int8(0x7F);
2431 emit_operand(src, dst);
2432 }
2433 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2434 assert(VM_Version::supports_evex(), "");
2435 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2436 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2437 emit_int8(0x6F);
2438 emit_int8((unsigned char)(0xC0 | encode));
2439 }
2440
2441 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2442 assert(VM_Version::supports_evex(), "");
2443 InstructionMark im(this);
2444 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2445 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2446 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2447 emit_int8(0x6F);
2448 emit_operand(dst, src);
2449 }
2450
2451 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2452 assert(VM_Version::supports_evex(), "");
2453 assert(src != xnoreg, "sanity");
2454 InstructionMark im(this);
2455 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2456 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2457 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2458 emit_int8(0x7F);
2459 emit_operand(src, dst);
2460 }
2461
2462 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2463 assert(VM_Version::supports_evex(), "");
2464 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2465 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2466 emit_int8(0x6F);
2467 emit_int8((unsigned char)(0xC0 | encode));
2468 }
2469
2470 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2471 assert(VM_Version::supports_evex(), "");
2472 InstructionMark im(this);
2473 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2474 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2475 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2476 emit_int8(0x6F);
2477 emit_operand(dst, src);
2478 }
2479
2480 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2481 assert(VM_Version::supports_evex(), "");
2482 assert(src != xnoreg, "sanity");
2483 InstructionMark im(this);
2484 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2485 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2486 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2487 emit_int8(0x7F);
2488 emit_operand(src, dst);
2489 }
2490
2491 // Uses zero extension on 64bit
2492
2493 void Assembler::movl(Register dst, int32_t imm32) {
2494 int encode = prefix_and_encode(dst->encoding());
2495 emit_int8((unsigned char)(0xB8 | encode));
2496 emit_int32(imm32);
2497 }
2498
2499 void Assembler::movl(Register dst, Register src) {
2500 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2501 emit_int8((unsigned char)0x8B);
2502 emit_int8((unsigned char)(0xC0 | encode));
2503 }
2504
2505 void Assembler::movl(Register dst, Address src) {
2506 InstructionMark im(this);
2507 prefix(src, dst);
2508 emit_int8((unsigned char)0x8B);
2509 emit_operand(dst, src);
2510 }
2511
2512 void Assembler::movl(Address dst, int32_t imm32) {
2513 InstructionMark im(this);
2514 prefix(dst);
2515 emit_int8((unsigned char)0xC7);
2516 emit_operand(rax, dst, 4);
2517 emit_int32(imm32);
2518 }
2519
2520 void Assembler::movl(Address dst, Register src) {
2521 InstructionMark im(this);
2522 prefix(dst, src);
2523 emit_int8((unsigned char)0x89);
2524 emit_operand(src, dst);
2525 }
2526
2527 // New cpus require to use movsd and movss to avoid partial register stall
2528 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2529 // The selection is done in MacroAssembler::movdbl() and movflt().
2530 void Assembler::movlpd(XMMRegister dst, Address src) {
2531 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2532 InstructionMark im(this);
2533 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2534 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2535 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2536 emit_int8(0x12);
2537 emit_operand(dst, src);
2538 }
2539
2540 void Assembler::movq( MMXRegister dst, Address src ) {
2541 assert( VM_Version::supports_mmx(), "" );
2542 emit_int8(0x0F);
2543 emit_int8(0x6F);
2544 emit_operand(dst, src);
2545 }
2546
2547 void Assembler::movq( Address dst, MMXRegister src ) {
2548 assert( VM_Version::supports_mmx(), "" );
2549 emit_int8(0x0F);
2550 emit_int8(0x7F);
2551 // workaround gcc (3.2.1-7a) bug
2552 // In that version of gcc with only an emit_operand(MMX, Address)
2553 // gcc will tail jump and try and reverse the parameters completely
2554 // obliterating dst in the process. By having a version available
2555 // that doesn't need to swap the args at the tail jump the bug is
2556 // avoided.
2557 emit_operand(dst, src);
2558 }
2559
2560 void Assembler::movq(XMMRegister dst, Address src) {
2561 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2562 InstructionMark im(this);
2563 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2564 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2565 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2566 emit_int8(0x7E);
2567 emit_operand(dst, src);
2568 }
2569
2570 void Assembler::movq(Address dst, XMMRegister src) {
2571 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2572 InstructionMark im(this);
2573 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2574 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2575 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2576 emit_int8((unsigned char)0xD6);
2577 emit_operand(src, dst);
2578 }
2579
2580 void Assembler::movsbl(Register dst, Address src) { // movsxb
2581 InstructionMark im(this);
2582 prefix(src, dst);
2583 emit_int8(0x0F);
2584 emit_int8((unsigned char)0xBE);
2585 emit_operand(dst, src);
2586 }
2587
2588 void Assembler::movsbl(Register dst, Register src) { // movsxb
2589 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2590 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2591 emit_int8(0x0F);
2592 emit_int8((unsigned char)0xBE);
2593 emit_int8((unsigned char)(0xC0 | encode));
2594 }
2595
2596 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2597 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2598 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2599 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2600 emit_int8(0x10);
2601 emit_int8((unsigned char)(0xC0 | encode));
2602 }
2603
2604 void Assembler::movsd(XMMRegister dst, Address src) {
2605 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2606 InstructionMark im(this);
2607 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2608 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2609 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2610 emit_int8(0x10);
2611 emit_operand(dst, src);
2612 }
2613
2614 void Assembler::movsd(Address dst, XMMRegister src) {
2615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2616 InstructionMark im(this);
2617 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2618 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2619 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2620 emit_int8(0x11);
2621 emit_operand(src, dst);
2622 }
2623
2624 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2625 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2626 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2627 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2628 emit_int8(0x10);
2629 emit_int8((unsigned char)(0xC0 | encode));
2630 }
2631
2632 void Assembler::movss(XMMRegister dst, Address src) {
2633 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2634 InstructionMark im(this);
2635 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2636 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2637 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2638 emit_int8(0x10);
2639 emit_operand(dst, src);
2640 }
2641
2642 void Assembler::movss(Address dst, XMMRegister src) {
2643 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2644 InstructionMark im(this);
2645 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2646 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2647 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2648 emit_int8(0x11);
2649 emit_operand(src, dst);
2650 }
2651
2652 void Assembler::movswl(Register dst, Address src) { // movsxw
2653 InstructionMark im(this);
2654 prefix(src, dst);
2655 emit_int8(0x0F);
2656 emit_int8((unsigned char)0xBF);
2657 emit_operand(dst, src);
2658 }
2659
2660 void Assembler::movswl(Register dst, Register src) { // movsxw
2661 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2662 emit_int8(0x0F);
2663 emit_int8((unsigned char)0xBF);
2664 emit_int8((unsigned char)(0xC0 | encode));
2665 }
2666
2667 void Assembler::movw(Address dst, int imm16) {
2668 InstructionMark im(this);
2669
2670 emit_int8(0x66); // switch to 16-bit mode
2671 prefix(dst);
2672 emit_int8((unsigned char)0xC7);
2673 emit_operand(rax, dst, 2);
2674 emit_int16(imm16);
2675 }
2676
2677 void Assembler::movw(Register dst, Address src) {
2678 InstructionMark im(this);
2679 emit_int8(0x66);
2680 prefix(src, dst);
2681 emit_int8((unsigned char)0x8B);
2682 emit_operand(dst, src);
2683 }
2684
2685 void Assembler::movw(Address dst, Register src) {
2686 InstructionMark im(this);
2687 emit_int8(0x66);
2688 prefix(dst, src);
2689 emit_int8((unsigned char)0x89);
2690 emit_operand(src, dst);
2691 }
2692
2693 void Assembler::movzbl(Register dst, Address src) { // movzxb
2694 InstructionMark im(this);
2695 prefix(src, dst);
2696 emit_int8(0x0F);
2697 emit_int8((unsigned char)0xB6);
2698 emit_operand(dst, src);
2699 }
2700
2701 void Assembler::movzbl(Register dst, Register src) { // movzxb
2702 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2703 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2704 emit_int8(0x0F);
2705 emit_int8((unsigned char)0xB6);
2706 emit_int8(0xC0 | encode);
2707 }
2708
2709 void Assembler::movzwl(Register dst, Address src) { // movzxw
2710 InstructionMark im(this);
2711 prefix(src, dst);
2712 emit_int8(0x0F);
2713 emit_int8((unsigned char)0xB7);
2714 emit_operand(dst, src);
2715 }
2716
2717 void Assembler::movzwl(Register dst, Register src) { // movzxw
2718 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2719 emit_int8(0x0F);
2720 emit_int8((unsigned char)0xB7);
2721 emit_int8(0xC0 | encode);
2722 }
2723
2724 void Assembler::mull(Address src) {
2725 InstructionMark im(this);
2726 prefix(src);
2727 emit_int8((unsigned char)0xF7);
2728 emit_operand(rsp, src);
2729 }
2730
2731 void Assembler::mull(Register src) {
2732 int encode = prefix_and_encode(src->encoding());
2733 emit_int8((unsigned char)0xF7);
2734 emit_int8((unsigned char)(0xE0 | encode));
2735 }
2736
2737 void Assembler::mulsd(XMMRegister dst, Address src) {
2738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2739 InstructionMark im(this);
2740 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2741 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2742 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2743 emit_int8(0x59);
2744 emit_operand(dst, src);
2745 }
2746
2747 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2748 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2749 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2750 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2751 emit_int8(0x59);
2752 emit_int8((unsigned char)(0xC0 | encode));
2753 }
2754
2755 void Assembler::mulss(XMMRegister dst, Address src) {
2756 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2757 InstructionMark im(this);
2758 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2759 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2760 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2761 emit_int8(0x59);
2762 emit_operand(dst, src);
2763 }
2764
2765 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2766 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2767 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2768 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2769 emit_int8(0x59);
2770 emit_int8((unsigned char)(0xC0 | encode));
2771 }
2772
2773 void Assembler::negl(Register dst) {
2774 int encode = prefix_and_encode(dst->encoding());
2775 emit_int8((unsigned char)0xF7);
2776 emit_int8((unsigned char)(0xD8 | encode));
2777 }
2778
2779 void Assembler::nop(int i) {
2780 #ifdef ASSERT
2781 assert(i > 0, " ");
2782 // The fancy nops aren't currently recognized by debuggers making it a
2783 // pain to disassemble code while debugging. If asserts are on clearly
2784 // speed is not an issue so simply use the single byte traditional nop
2785 // to do alignment.
2786
2787 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2788 return;
2789
2790 #endif // ASSERT
2791
2792 if (UseAddressNop && VM_Version::is_intel()) {
2793 //
2794 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2795 // 1: 0x90
2796 // 2: 0x66 0x90
2797 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2798 // 4: 0x0F 0x1F 0x40 0x00
2799 // 5: 0x0F 0x1F 0x44 0x00 0x00
2800 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2801 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2802 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2803 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2804 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2805 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2806
2807 // The rest coding is Intel specific - don't use consecutive address nops
2808
2809 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2810 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2811 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2812 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2813
2814 while(i >= 15) {
2815 // For Intel don't generate consecutive addess nops (mix with regular nops)
2816 i -= 15;
2817 emit_int8(0x66); // size prefix
2818 emit_int8(0x66); // size prefix
2819 emit_int8(0x66); // size prefix
2820 addr_nop_8();
2821 emit_int8(0x66); // size prefix
2822 emit_int8(0x66); // size prefix
2823 emit_int8(0x66); // size prefix
2824 emit_int8((unsigned char)0x90);
2825 // nop
2826 }
2827 switch (i) {
2828 case 14:
2829 emit_int8(0x66); // size prefix
2830 case 13:
2831 emit_int8(0x66); // size prefix
2832 case 12:
2833 addr_nop_8();
2834 emit_int8(0x66); // size prefix
2835 emit_int8(0x66); // size prefix
2836 emit_int8(0x66); // size prefix
2837 emit_int8((unsigned char)0x90);
2838 // nop
2839 break;
2840 case 11:
2841 emit_int8(0x66); // size prefix
2842 case 10:
2843 emit_int8(0x66); // size prefix
2844 case 9:
2845 emit_int8(0x66); // size prefix
2846 case 8:
2847 addr_nop_8();
2848 break;
2849 case 7:
2850 addr_nop_7();
2851 break;
2852 case 6:
2853 emit_int8(0x66); // size prefix
2854 case 5:
2855 addr_nop_5();
2856 break;
2857 case 4:
2858 addr_nop_4();
2859 break;
2860 case 3:
2861 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2862 emit_int8(0x66); // size prefix
2863 case 2:
2864 emit_int8(0x66); // size prefix
2865 case 1:
2866 emit_int8((unsigned char)0x90);
2867 // nop
2868 break;
2869 default:
2870 assert(i == 0, " ");
2871 }
2872 return;
2873 }
2874 if (UseAddressNop && VM_Version::is_amd()) {
2875 //
2876 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2877 // 1: 0x90
2878 // 2: 0x66 0x90
2879 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2880 // 4: 0x0F 0x1F 0x40 0x00
2881 // 5: 0x0F 0x1F 0x44 0x00 0x00
2882 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2883 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2884 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2885 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2886 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2887 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2888
2889 // The rest coding is AMD specific - use consecutive address nops
2890
2891 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2892 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2893 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2894 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2895 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2896 // Size prefixes (0x66) are added for larger sizes
2897
2898 while(i >= 22) {
2899 i -= 11;
2900 emit_int8(0x66); // size prefix
2901 emit_int8(0x66); // size prefix
2902 emit_int8(0x66); // size prefix
2903 addr_nop_8();
2904 }
2905 // Generate first nop for size between 21-12
2906 switch (i) {
2907 case 21:
2908 i -= 1;
2909 emit_int8(0x66); // size prefix
2910 case 20:
2911 case 19:
2912 i -= 1;
2913 emit_int8(0x66); // size prefix
2914 case 18:
2915 case 17:
2916 i -= 1;
2917 emit_int8(0x66); // size prefix
2918 case 16:
2919 case 15:
2920 i -= 8;
2921 addr_nop_8();
2922 break;
2923 case 14:
2924 case 13:
2925 i -= 7;
2926 addr_nop_7();
2927 break;
2928 case 12:
2929 i -= 6;
2930 emit_int8(0x66); // size prefix
2931 addr_nop_5();
2932 break;
2933 default:
2934 assert(i < 12, " ");
2935 }
2936
2937 // Generate second nop for size between 11-1
2938 switch (i) {
2939 case 11:
2940 emit_int8(0x66); // size prefix
2941 case 10:
2942 emit_int8(0x66); // size prefix
2943 case 9:
2944 emit_int8(0x66); // size prefix
2945 case 8:
2946 addr_nop_8();
2947 break;
2948 case 7:
2949 addr_nop_7();
2950 break;
2951 case 6:
2952 emit_int8(0x66); // size prefix
2953 case 5:
2954 addr_nop_5();
2955 break;
2956 case 4:
2957 addr_nop_4();
2958 break;
2959 case 3:
2960 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2961 emit_int8(0x66); // size prefix
2962 case 2:
2963 emit_int8(0x66); // size prefix
2964 case 1:
2965 emit_int8((unsigned char)0x90);
2966 // nop
2967 break;
2968 default:
2969 assert(i == 0, " ");
2970 }
2971 return;
2972 }
2973
2974 // Using nops with size prefixes "0x66 0x90".
2975 // From AMD Optimization Guide:
2976 // 1: 0x90
2977 // 2: 0x66 0x90
2978 // 3: 0x66 0x66 0x90
2979 // 4: 0x66 0x66 0x66 0x90
2980 // 5: 0x66 0x66 0x90 0x66 0x90
2981 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2982 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2983 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2984 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2985 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2986 //
2987 while(i > 12) {
2988 i -= 4;
2989 emit_int8(0x66); // size prefix
2990 emit_int8(0x66);
2991 emit_int8(0x66);
2992 emit_int8((unsigned char)0x90);
2993 // nop
2994 }
2995 // 1 - 12 nops
2996 if(i > 8) {
2997 if(i > 9) {
2998 i -= 1;
2999 emit_int8(0x66);
3000 }
3001 i -= 3;
3002 emit_int8(0x66);
3003 emit_int8(0x66);
3004 emit_int8((unsigned char)0x90);
3005 }
3006 // 1 - 8 nops
3007 if(i > 4) {
3008 if(i > 6) {
3009 i -= 1;
3010 emit_int8(0x66);
3011 }
3012 i -= 3;
3013 emit_int8(0x66);
3014 emit_int8(0x66);
3015 emit_int8((unsigned char)0x90);
3016 }
3017 switch (i) {
3018 case 4:
3019 emit_int8(0x66);
3020 case 3:
3021 emit_int8(0x66);
3022 case 2:
3023 emit_int8(0x66);
3024 case 1:
3025 emit_int8((unsigned char)0x90);
3026 break;
3027 default:
3028 assert(i == 0, " ");
3029 }
3030 }
3031
3032 void Assembler::notl(Register dst) {
3033 int encode = prefix_and_encode(dst->encoding());
3034 emit_int8((unsigned char)0xF7);
3035 emit_int8((unsigned char)(0xD0 | encode));
3036 }
3037
3038 void Assembler::orl(Address dst, int32_t imm32) {
3039 InstructionMark im(this);
3040 prefix(dst);
3041 emit_arith_operand(0x81, rcx, dst, imm32);
3042 }
3043
3044 void Assembler::orl(Register dst, int32_t imm32) {
3045 prefix(dst);
3046 emit_arith(0x81, 0xC8, dst, imm32);
3047 }
3048
3049 void Assembler::orl(Register dst, Address src) {
3050 InstructionMark im(this);
3051 prefix(src, dst);
3052 emit_int8(0x0B);
3053 emit_operand(dst, src);
3054 }
3055
3056 void Assembler::orl(Register dst, Register src) {
3057 (void) prefix_and_encode(dst->encoding(), src->encoding());
3058 emit_arith(0x0B, 0xC0, dst, src);
3059 }
3060
3061 void Assembler::orl(Address dst, Register src) {
3062 InstructionMark im(this);
3063 prefix(dst, src);
3064 emit_int8(0x09);
3065 emit_operand(src, dst);
3066 }
3067
3068 void Assembler::packuswb(XMMRegister dst, Address src) {
3069 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3070 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3071 InstructionMark im(this);
3072 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3073 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3074 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3075 emit_int8(0x67);
3076 emit_operand(dst, src);
3077 }
3078
3079 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3080 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3081 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3082 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3083 emit_int8(0x67);
3084 emit_int8((unsigned char)(0xC0 | encode));
3085 }
3086
3087 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3088 assert(UseAVX > 0, "some form of AVX must be enabled");
3089 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3090 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3091 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3092 emit_int8(0x67);
3093 emit_int8((unsigned char)(0xC0 | encode));
3094 }
3095
3096 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3097 assert(VM_Version::supports_avx2(), "");
3098 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3099 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3100 emit_int8(0x00);
3101 emit_int8(0xC0 | encode);
3102 emit_int8(imm8);
3103 }
3104
3105 void Assembler::pause() {
3106 emit_int8((unsigned char)0xF3);
3107 emit_int8((unsigned char)0x90);
3108 }
3109
3110 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3111 assert(VM_Version::supports_sse4_2(), "");
3112 InstructionMark im(this);
3113 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3114 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3115 emit_int8(0x61);
3116 emit_operand(dst, src);
3117 emit_int8(imm8);
3118 }
3119
3120 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3121 assert(VM_Version::supports_sse4_2(), "");
3122 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3123 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3124 emit_int8(0x61);
3125 emit_int8((unsigned char)(0xC0 | encode));
3126 emit_int8(imm8);
3127 }
3128
3129 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3130 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3131 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3132 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3133 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3134 emit_int8(0x74);
3135 emit_int8((unsigned char)(0xC0 | encode));
3136 }
3137
3138 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3139 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3140 assert(VM_Version::supports_avx(), "");
3141 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3142 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3143 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3144 emit_int8(0x74);
3145 emit_int8((unsigned char)(0xC0 | encode));
3146 }
3147
3148 // In this context, kdst is written the mask used to process the equal components
3149 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3150 assert(VM_Version::supports_avx512bw(), "");
3151 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3152 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3153 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3154 emit_int8(0x74);
3155 emit_int8((unsigned char)(0xC0 | encode));
3156 }
3157
3158 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3159 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3160 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3161 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3162 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3163 emit_int8(0x75);
3164 emit_int8((unsigned char)(0xC0 | encode));
3165 }
3166
3167 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3168 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3169 assert(VM_Version::supports_avx(), "");
3170 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3171 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3172 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3173 emit_int8(0x75);
3174 emit_int8((unsigned char)(0xC0 | encode));
3175 }
3176
3177 // In this context, kdst is written the mask used to process the equal components
3178 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3179 assert(VM_Version::supports_avx512bw(), "");
3180 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3181 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3182 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3183 emit_int8(0x75);
3184 emit_int8((unsigned char)(0xC0 | encode));
3185 }
3186
3187 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3188 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3189 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3190 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3191 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3192 emit_int8(0x76);
3193 emit_int8((unsigned char)(0xC0 | encode));
3194 }
3195
3196 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3197 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3198 assert(VM_Version::supports_avx(), "");
3199 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3200 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3201 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3202 emit_int8(0x76);
3203 emit_int8((unsigned char)(0xC0 | encode));
3204 }
3205
3206 // In this context, kdst is written the mask used to process the equal components
3207 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3208 assert(VM_Version::supports_evex(), "");
3209 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3210 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3211 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3212 emit_int8(0x76);
3213 emit_int8((unsigned char)(0xC0 | encode));
3214 }
3215
3216 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3217 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3218 NOT_LP64(assert(VM_Version::supports_sse4_1(), ""));
3219 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3220 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3221 emit_int8(0x29);
3222 emit_int8((unsigned char)(0xC0 | encode));
3223 }
3224
3225 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3226 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3227 assert(VM_Version::supports_avx(), "");
3228 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3229 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3230 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3231 emit_int8(0x29);
3232 emit_int8((unsigned char)(0xC0 | encode));
3233 }
3234
3235 // In this context, kdst is written the mask used to process the equal components
3236 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3237 assert(VM_Version::supports_evex(), "");
3238 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3239 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3240 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3241 emit_int8(0x29);
3242 emit_int8((unsigned char)(0xC0 | encode));
3243 }
3244
3245 // In this context, kdst is written the mask used to process the equal components
3246 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3247 assert(VM_Version::supports_evex(), "");
3248 InstructionMark im(this);
3249 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3250 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3251 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3252 int dst_enc = kdst->encoding();
3253 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3254 emit_int8(0x29);
3255 emit_operand(as_Register(dst_enc), src);
3256 }
3257
3258 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3259 assert(VM_Version::supports_sse2(), "");
3260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3261 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3262 emit_int8((unsigned char)0xD7);
3263 emit_int8((unsigned char)(0xC0 | encode));
3264 }
3265
3266 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3267 assert(VM_Version::supports_avx2(), "");
3268 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3269 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3270 emit_int8((unsigned char)0xD7);
3271 emit_int8((unsigned char)(0xC0 | encode));
3272 }
3273
3274 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3275 assert(VM_Version::supports_sse4_1(), "");
3276 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3277 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3278 emit_int8(0x16);
3279 emit_int8((unsigned char)(0xC0 | encode));
3280 emit_int8(imm8);
3281 }
3282
3283 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3284 assert(VM_Version::supports_sse4_1(), "");
3285 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3286 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3287 emit_int8(0x16);
3288 emit_int8((unsigned char)(0xC0 | encode));
3289 emit_int8(imm8);
3290 }
3291
3292 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3293 assert(VM_Version::supports_sse2(), "");
3294 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3295 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3296 emit_int8((unsigned char)0xC5);
3297 emit_int8((unsigned char)(0xC0 | encode));
3298 emit_int8(imm8);
3299 }
3300
3301 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3302 assert(VM_Version::supports_sse4_1(), "");
3303 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3304 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3305 emit_int8(0x22);
3306 emit_int8((unsigned char)(0xC0 | encode));
3307 emit_int8(imm8);
3308 }
3309
3310 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3311 assert(VM_Version::supports_sse4_1(), "");
3312 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3313 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3314 emit_int8(0x22);
3315 emit_int8((unsigned char)(0xC0 | encode));
3316 emit_int8(imm8);
3317 }
3318
3319 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3320 assert(VM_Version::supports_sse2(), "");
3321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3322 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3323 emit_int8((unsigned char)0xC4);
3324 emit_int8((unsigned char)(0xC0 | encode));
3325 emit_int8(imm8);
3326 }
3327
3328 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3329 assert(VM_Version::supports_sse4_1(), "");
3330 InstructionMark im(this);
3331 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3332 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3333 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3334 emit_int8(0x30);
3335 emit_operand(dst, src);
3336 }
3337
3338 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3339 assert(VM_Version::supports_sse4_1(), "");
3340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3341 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3342 emit_int8(0x30);
3343 emit_int8((unsigned char)(0xC0 | encode));
3344 }
3345
3346 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3347 assert(VM_Version::supports_avx(), "");
3348 InstructionMark im(this);
3349 assert(dst != xnoreg, "sanity");
3350 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3351 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3352 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3353 emit_int8(0x30);
3354 emit_operand(dst, src);
3355 }
3356
3357 // generic
3358 void Assembler::pop(Register dst) {
3359 int encode = prefix_and_encode(dst->encoding());
3360 emit_int8(0x58 | encode);
3361 }
3362
3363 void Assembler::popcntl(Register dst, Address src) {
3364 assert(VM_Version::supports_popcnt(), "must support");
3365 InstructionMark im(this);
3366 emit_int8((unsigned char)0xF3);
3367 prefix(src, dst);
3368 emit_int8(0x0F);
3369 emit_int8((unsigned char)0xB8);
3370 emit_operand(dst, src);
3371 }
3372
3373 void Assembler::popcntl(Register dst, Register src) {
3374 assert(VM_Version::supports_popcnt(), "must support");
3375 emit_int8((unsigned char)0xF3);
3376 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3377 emit_int8(0x0F);
3378 emit_int8((unsigned char)0xB8);
3379 emit_int8((unsigned char)(0xC0 | encode));
3380 }
3381
3382 void Assembler::popf() {
3383 emit_int8((unsigned char)0x9D);
3384 }
3385
3386 #ifndef _LP64 // no 32bit push/pop on amd64
3387 void Assembler::popl(Address dst) {
3388 // NOTE: this will adjust stack by 8byte on 64bits
3389 InstructionMark im(this);
3390 prefix(dst);
3391 emit_int8((unsigned char)0x8F);
3392 emit_operand(rax, dst);
3393 }
3394 #endif
3395
3396 void Assembler::prefetch_prefix(Address src) {
3397 prefix(src);
3398 emit_int8(0x0F);
3399 }
3400
3401 void Assembler::prefetchnta(Address src) {
3402 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3403 InstructionMark im(this);
3404 prefetch_prefix(src);
3405 emit_int8(0x18);
3406 emit_operand(rax, src); // 0, src
3407 }
3408
3409 void Assembler::prefetchr(Address src) {
3410 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3411 InstructionMark im(this);
3412 prefetch_prefix(src);
3413 emit_int8(0x0D);
3414 emit_operand(rax, src); // 0, src
3415 }
3416
3417 void Assembler::prefetcht0(Address src) {
3418 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3419 InstructionMark im(this);
3420 prefetch_prefix(src);
3421 emit_int8(0x18);
3422 emit_operand(rcx, src); // 1, src
3423 }
3424
3425 void Assembler::prefetcht1(Address src) {
3426 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3427 InstructionMark im(this);
3428 prefetch_prefix(src);
3429 emit_int8(0x18);
3430 emit_operand(rdx, src); // 2, src
3431 }
3432
3433 void Assembler::prefetcht2(Address src) {
3434 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3435 InstructionMark im(this);
3436 prefetch_prefix(src);
3437 emit_int8(0x18);
3438 emit_operand(rbx, src); // 3, src
3439 }
3440
3441 void Assembler::prefetchw(Address src) {
3442 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3443 InstructionMark im(this);
3444 prefetch_prefix(src);
3445 emit_int8(0x0D);
3446 emit_operand(rcx, src); // 1, src
3447 }
3448
3449 void Assembler::prefix(Prefix p) {
3450 emit_int8(p);
3451 }
3452
3453 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3454 assert(VM_Version::supports_ssse3(), "");
3455 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3456 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3457 emit_int8(0x00);
3458 emit_int8((unsigned char)(0xC0 | encode));
3459 }
3460
3461 void Assembler::pshufb(XMMRegister dst, Address src) {
3462 assert(VM_Version::supports_ssse3(), "");
3463 InstructionMark im(this);
3464 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3465 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3466 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3467 emit_int8(0x00);
3468 emit_operand(dst, src);
3469 }
3470
3471 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3472 assert(isByte(mode), "invalid value");
3473 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3474 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
3475 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3476 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3477 emit_int8(0x70);
3478 emit_int8((unsigned char)(0xC0 | encode));
3479 emit_int8(mode & 0xFF);
3480 }
3481
3482 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3483 assert(isByte(mode), "invalid value");
3484 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3485 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3486 InstructionMark im(this);
3487 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3488 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3489 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3490 emit_int8(0x70);
3491 emit_operand(dst, src);
3492 emit_int8(mode & 0xFF);
3493 }
3494
3495 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3496 assert(isByte(mode), "invalid value");
3497 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3498 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3499 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3500 emit_int8(0x70);
3501 emit_int8((unsigned char)(0xC0 | encode));
3502 emit_int8(mode & 0xFF);
3503 }
3504
3505 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3506 assert(isByte(mode), "invalid value");
3507 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3508 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3509 InstructionMark im(this);
3510 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3511 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3512 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3513 emit_int8(0x70);
3514 emit_operand(dst, src);
3515 emit_int8(mode & 0xFF);
3516 }
3517
3518 void Assembler::psrldq(XMMRegister dst, int shift) {
3519 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3520 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3521 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3522 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3523 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3524 emit_int8(0x73);
3525 emit_int8((unsigned char)(0xC0 | encode));
3526 emit_int8(shift);
3527 }
3528
3529 void Assembler::pslldq(XMMRegister dst, int shift) {
3530 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3531 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3532 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3533 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3534 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3535 emit_int8(0x73);
3536 emit_int8((unsigned char)(0xC0 | encode));
3537 emit_int8(shift);
3538 }
3539
3540 void Assembler::ptest(XMMRegister dst, Address src) {
3541 assert(VM_Version::supports_sse4_1(), "");
3542 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3543 InstructionMark im(this);
3544 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3545 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3546 emit_int8(0x17);
3547 emit_operand(dst, src);
3548 }
3549
3550 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3551 assert(VM_Version::supports_sse4_1(), "");
3552 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3553 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3554 emit_int8(0x17);
3555 emit_int8((unsigned char)(0xC0 | encode));
3556 }
3557
3558 void Assembler::vptest(XMMRegister dst, Address src) {
3559 assert(VM_Version::supports_avx(), "");
3560 InstructionMark im(this);
3561 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3562 assert(dst != xnoreg, "sanity");
3563 // swap src<->dst for encoding
3564 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3565 emit_int8(0x17);
3566 emit_operand(dst, src);
3567 }
3568
3569 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3570 assert(VM_Version::supports_avx(), "");
3571 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3572 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3573 emit_int8(0x17);
3574 emit_int8((unsigned char)(0xC0 | encode));
3575 }
3576
3577 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3578 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3579 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3580 InstructionMark im(this);
3581 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3582 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3583 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3584 emit_int8(0x60);
3585 emit_operand(dst, src);
3586 }
3587
3588 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3589 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3590 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3591 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3592 emit_int8(0x60);
3593 emit_int8((unsigned char)(0xC0 | encode));
3594 }
3595
3596 void Assembler::punpckldq(XMMRegister dst, Address src) {
3597 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3598 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3599 InstructionMark im(this);
3600 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3601 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3602 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3603 emit_int8(0x62);
3604 emit_operand(dst, src);
3605 }
3606
3607 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3609 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3610 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3611 emit_int8(0x62);
3612 emit_int8((unsigned char)(0xC0 | encode));
3613 }
3614
3615 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3616 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3617 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3618 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3619 emit_int8(0x6C);
3620 emit_int8((unsigned char)(0xC0 | encode));
3621 }
3622
3623 void Assembler::push(int32_t imm32) {
3624 // in 64bits we push 64bits onto the stack but only
3625 // take a 32bit immediate
3626 emit_int8(0x68);
3627 emit_int32(imm32);
3628 }
3629
3630 void Assembler::push(Register src) {
3631 int encode = prefix_and_encode(src->encoding());
3632
3633 emit_int8(0x50 | encode);
3634 }
3635
3636 void Assembler::pushf() {
3637 emit_int8((unsigned char)0x9C);
3638 }
3639
3640 #ifndef _LP64 // no 32bit push/pop on amd64
3641 void Assembler::pushl(Address src) {
3642 // Note this will push 64bit on 64bit
3643 InstructionMark im(this);
3644 prefix(src);
3645 emit_int8((unsigned char)0xFF);
3646 emit_operand(rsi, src);
3647 }
3648 #endif
3649
3650 void Assembler::rcll(Register dst, int imm8) {
3651 assert(isShiftCount(imm8), "illegal shift count");
3652 int encode = prefix_and_encode(dst->encoding());
3653 if (imm8 == 1) {
3654 emit_int8((unsigned char)0xD1);
3655 emit_int8((unsigned char)(0xD0 | encode));
3656 } else {
3657 emit_int8((unsigned char)0xC1);
3658 emit_int8((unsigned char)0xD0 | encode);
3659 emit_int8(imm8);
3660 }
3661 }
3662
3663 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3664 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3665 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3666 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3667 emit_int8(0x53);
3668 emit_int8((unsigned char)(0xC0 | encode));
3669 }
3670
3671 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3672 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3673 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3674 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3675 emit_int8(0x53);
3676 emit_int8((unsigned char)(0xC0 | encode));
3677 }
3678
3679 void Assembler::rdtsc() {
3680 emit_int8((unsigned char)0x0F);
3681 emit_int8((unsigned char)0x31);
3682 }
3683
3684 // copies data from [esi] to [edi] using rcx pointer sized words
3685 // generic
3686 void Assembler::rep_mov() {
3687 emit_int8((unsigned char)0xF3);
3688 // MOVSQ
3689 LP64_ONLY(prefix(REX_W));
3690 emit_int8((unsigned char)0xA5);
3691 }
3692
3693 // sets rcx bytes with rax, value at [edi]
3694 void Assembler::rep_stosb() {
3695 emit_int8((unsigned char)0xF3); // REP
3696 LP64_ONLY(prefix(REX_W));
3697 emit_int8((unsigned char)0xAA); // STOSB
3698 }
3699
3700 // sets rcx pointer sized words with rax, value at [edi]
3701 // generic
3702 void Assembler::rep_stos() {
3703 emit_int8((unsigned char)0xF3); // REP
3704 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3705 emit_int8((unsigned char)0xAB);
3706 }
3707
3708 // scans rcx pointer sized words at [edi] for occurance of rax,
3709 // generic
3710 void Assembler::repne_scan() { // repne_scan
3711 emit_int8((unsigned char)0xF2);
3712 // SCASQ
3713 LP64_ONLY(prefix(REX_W));
3714 emit_int8((unsigned char)0xAF);
3715 }
3716
3717 #ifdef _LP64
3718 // scans rcx 4 byte words at [edi] for occurance of rax,
3719 // generic
3720 void Assembler::repne_scanl() { // repne_scan
3721 emit_int8((unsigned char)0xF2);
3722 // SCASL
3723 emit_int8((unsigned char)0xAF);
3724 }
3725 #endif
3726
3727 void Assembler::ret(int imm16) {
3728 if (imm16 == 0) {
3729 emit_int8((unsigned char)0xC3);
3730 } else {
3731 emit_int8((unsigned char)0xC2);
3732 emit_int16(imm16);
3733 }
3734 }
3735
3736 void Assembler::sahf() {
3737 #ifdef _LP64
3738 // Not supported in 64bit mode
3739 ShouldNotReachHere();
3740 #endif
3741 emit_int8((unsigned char)0x9E);
3742 }
3743
3744 void Assembler::sarl(Register dst, int imm8) {
3745 int encode = prefix_and_encode(dst->encoding());
3746 assert(isShiftCount(imm8), "illegal shift count");
3747 if (imm8 == 1) {
3748 emit_int8((unsigned char)0xD1);
3749 emit_int8((unsigned char)(0xF8 | encode));
3750 } else {
3751 emit_int8((unsigned char)0xC1);
3752 emit_int8((unsigned char)(0xF8 | encode));
3753 emit_int8(imm8);
3754 }
3755 }
3756
3757 void Assembler::sarl(Register dst) {
3758 int encode = prefix_and_encode(dst->encoding());
3759 emit_int8((unsigned char)0xD3);
3760 emit_int8((unsigned char)(0xF8 | encode));
3761 }
3762
3763 void Assembler::sbbl(Address dst, int32_t imm32) {
3764 InstructionMark im(this);
3765 prefix(dst);
3766 emit_arith_operand(0x81, rbx, dst, imm32);
3767 }
3768
3769 void Assembler::sbbl(Register dst, int32_t imm32) {
3770 prefix(dst);
3771 emit_arith(0x81, 0xD8, dst, imm32);
3772 }
3773
3774
3775 void Assembler::sbbl(Register dst, Address src) {
3776 InstructionMark im(this);
3777 prefix(src, dst);
3778 emit_int8(0x1B);
3779 emit_operand(dst, src);
3780 }
3781
3782 void Assembler::sbbl(Register dst, Register src) {
3783 (void) prefix_and_encode(dst->encoding(), src->encoding());
3784 emit_arith(0x1B, 0xC0, dst, src);
3785 }
3786
3787 void Assembler::setb(Condition cc, Register dst) {
3788 assert(0 <= cc && cc < 16, "illegal cc");
3789 int encode = prefix_and_encode(dst->encoding(), true);
3790 emit_int8(0x0F);
3791 emit_int8((unsigned char)0x90 | cc);
3792 emit_int8((unsigned char)(0xC0 | encode));
3793 }
3794
3795 void Assembler::shll(Register dst, int imm8) {
3796 assert(isShiftCount(imm8), "illegal shift count");
3797 int encode = prefix_and_encode(dst->encoding());
3798 if (imm8 == 1 ) {
3799 emit_int8((unsigned char)0xD1);
3800 emit_int8((unsigned char)(0xE0 | encode));
3801 } else {
3802 emit_int8((unsigned char)0xC1);
3803 emit_int8((unsigned char)(0xE0 | encode));
3804 emit_int8(imm8);
3805 }
3806 }
3807
3808 void Assembler::shll(Register dst) {
3809 int encode = prefix_and_encode(dst->encoding());
3810 emit_int8((unsigned char)0xD3);
3811 emit_int8((unsigned char)(0xE0 | encode));
3812 }
3813
3814 void Assembler::shrl(Register dst, int imm8) {
3815 assert(isShiftCount(imm8), "illegal shift count");
3816 int encode = prefix_and_encode(dst->encoding());
3817 emit_int8((unsigned char)0xC1);
3818 emit_int8((unsigned char)(0xE8 | encode));
3819 emit_int8(imm8);
3820 }
3821
3822 void Assembler::shrl(Register dst) {
3823 int encode = prefix_and_encode(dst->encoding());
3824 emit_int8((unsigned char)0xD3);
3825 emit_int8((unsigned char)(0xE8 | encode));
3826 }
3827
3828 // copies a single word from [esi] to [edi]
3829 void Assembler::smovl() {
3830 emit_int8((unsigned char)0xA5);
3831 }
3832
3833 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3834 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3835 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3836 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3837 emit_int8(0x51);
3838 emit_int8((unsigned char)(0xC0 | encode));
3839 }
3840
3841 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3842 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3843 InstructionMark im(this);
3844 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3845 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3846 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3847 emit_int8(0x51);
3848 emit_operand(dst, src);
3849 }
3850
3851 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3852 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3853 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3854 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3855 emit_int8(0x51);
3856 emit_int8((unsigned char)(0xC0 | encode));
3857 }
3858
3859 void Assembler::std() {
3860 emit_int8((unsigned char)0xFD);
3861 }
3862
3863 void Assembler::sqrtss(XMMRegister dst, Address src) {
3864 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3865 InstructionMark im(this);
3866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3867 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3868 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3869 emit_int8(0x51);
3870 emit_operand(dst, src);
3871 }
3872
3873 void Assembler::stmxcsr( Address dst) {
3874 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3875 InstructionMark im(this);
3876 prefix(dst);
3877 emit_int8(0x0F);
3878 emit_int8((unsigned char)0xAE);
3879 emit_operand(as_Register(3), dst);
3880 }
3881
3882 void Assembler::subl(Address dst, int32_t imm32) {
3883 InstructionMark im(this);
3884 prefix(dst);
3885 emit_arith_operand(0x81, rbp, dst, imm32);
3886 }
3887
3888 void Assembler::subl(Address dst, Register src) {
3889 InstructionMark im(this);
3890 prefix(dst, src);
3891 emit_int8(0x29);
3892 emit_operand(src, dst);
3893 }
3894
3895 void Assembler::subl(Register dst, int32_t imm32) {
3896 prefix(dst);
3897 emit_arith(0x81, 0xE8, dst, imm32);
3898 }
3899
3900 // Force generation of a 4 byte immediate value even if it fits into 8bit
3901 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3902 prefix(dst);
3903 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3904 }
3905
3906 void Assembler::subl(Register dst, Address src) {
3907 InstructionMark im(this);
3908 prefix(src, dst);
3909 emit_int8(0x2B);
3910 emit_operand(dst, src);
3911 }
3912
3913 void Assembler::subl(Register dst, Register src) {
3914 (void) prefix_and_encode(dst->encoding(), src->encoding());
3915 emit_arith(0x2B, 0xC0, dst, src);
3916 }
3917
3918 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3919 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3920 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3921 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3922 emit_int8(0x5C);
3923 emit_int8((unsigned char)(0xC0 | encode));
3924 }
3925
3926 void Assembler::subsd(XMMRegister dst, Address src) {
3927 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3928 InstructionMark im(this);
3929 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3930 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3931 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3932 emit_int8(0x5C);
3933 emit_operand(dst, src);
3934 }
3935
3936 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3937 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3938 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3939 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3940 emit_int8(0x5C);
3941 emit_int8((unsigned char)(0xC0 | encode));
3942 }
3943
3944 void Assembler::subss(XMMRegister dst, Address src) {
3945 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3946 InstructionMark im(this);
3947 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3948 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3949 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3950 emit_int8(0x5C);
3951 emit_operand(dst, src);
3952 }
3953
3954 void Assembler::testb(Register dst, int imm8) {
3955 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3956 (void) prefix_and_encode(dst->encoding(), true);
3957 emit_arith_b(0xF6, 0xC0, dst, imm8);
3958 }
3959
3960 void Assembler::testl(Register dst, int32_t imm32) {
3961 // not using emit_arith because test
3962 // doesn't support sign-extension of
3963 // 8bit operands
3964 int encode = dst->encoding();
3965 if (encode == 0) {
3966 emit_int8((unsigned char)0xA9);
3967 } else {
3968 encode = prefix_and_encode(encode);
3969 emit_int8((unsigned char)0xF7);
3970 emit_int8((unsigned char)(0xC0 | encode));
3971 }
3972 emit_int32(imm32);
3973 }
3974
3975 void Assembler::testl(Register dst, Register src) {
3976 (void) prefix_and_encode(dst->encoding(), src->encoding());
3977 emit_arith(0x85, 0xC0, dst, src);
3978 }
3979
3980 void Assembler::testl(Register dst, Address src) {
3981 InstructionMark im(this);
3982 prefix(src, dst);
3983 emit_int8((unsigned char)0x85);
3984 emit_operand(dst, src);
3985 }
3986
3987 void Assembler::tzcntl(Register dst, Register src) {
3988 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3989 emit_int8((unsigned char)0xF3);
3990 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3991 emit_int8(0x0F);
3992 emit_int8((unsigned char)0xBC);
3993 emit_int8((unsigned char)0xC0 | encode);
3994 }
3995
3996 void Assembler::tzcntq(Register dst, Register src) {
3997 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
3998 emit_int8((unsigned char)0xF3);
3999 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4000 emit_int8(0x0F);
4001 emit_int8((unsigned char)0xBC);
4002 emit_int8((unsigned char)(0xC0 | encode));
4003 }
4004
4005 void Assembler::ucomisd(XMMRegister dst, Address src) {
4006 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4007 InstructionMark im(this);
4008 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4009 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4010 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4011 emit_int8(0x2E);
4012 emit_operand(dst, src);
4013 }
4014
4015 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4016 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4017 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4018 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4019 emit_int8(0x2E);
4020 emit_int8((unsigned char)(0xC0 | encode));
4021 }
4022
4023 void Assembler::ucomiss(XMMRegister dst, Address src) {
4024 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4025 InstructionMark im(this);
4026 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4027 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4028 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4029 emit_int8(0x2E);
4030 emit_operand(dst, src);
4031 }
4032
4033 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4034 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4035 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4036 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4037 emit_int8(0x2E);
4038 emit_int8((unsigned char)(0xC0 | encode));
4039 }
4040
4041 void Assembler::xabort(int8_t imm8) {
4042 emit_int8((unsigned char)0xC6);
4043 emit_int8((unsigned char)0xF8);
4044 emit_int8((unsigned char)(imm8 & 0xFF));
4045 }
4046
4047 void Assembler::xaddl(Address dst, Register src) {
4048 InstructionMark im(this);
4049 prefix(dst, src);
4050 emit_int8(0x0F);
4051 emit_int8((unsigned char)0xC1);
4052 emit_operand(src, dst);
4053 }
4054
4055 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4056 InstructionMark im(this);
4057 relocate(rtype);
4058 if (abort.is_bound()) {
4059 address entry = target(abort);
4060 assert(entry != NULL, "abort entry NULL");
4061 intptr_t offset = entry - pc();
4062 emit_int8((unsigned char)0xC7);
4063 emit_int8((unsigned char)0xF8);
4064 emit_int32(offset - 6); // 2 opcode + 4 address
4065 } else {
4066 abort.add_patch_at(code(), locator());
4067 emit_int8((unsigned char)0xC7);
4068 emit_int8((unsigned char)0xF8);
4069 emit_int32(0);
4070 }
4071 }
4072
4073 void Assembler::xchgl(Register dst, Address src) { // xchg
4074 InstructionMark im(this);
4075 prefix(src, dst);
4076 emit_int8((unsigned char)0x87);
4077 emit_operand(dst, src);
4078 }
4079
4080 void Assembler::xchgl(Register dst, Register src) {
4081 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4082 emit_int8((unsigned char)0x87);
4083 emit_int8((unsigned char)(0xC0 | encode));
4084 }
4085
4086 void Assembler::xend() {
4087 emit_int8((unsigned char)0x0F);
4088 emit_int8((unsigned char)0x01);
4089 emit_int8((unsigned char)0xD5);
4090 }
4091
4092 void Assembler::xgetbv() {
4093 emit_int8(0x0F);
4094 emit_int8(0x01);
4095 emit_int8((unsigned char)0xD0);
4096 }
4097
4098 void Assembler::xorl(Register dst, int32_t imm32) {
4099 prefix(dst);
4100 emit_arith(0x81, 0xF0, dst, imm32);
4101 }
4102
4103 void Assembler::xorl(Register dst, Address src) {
4104 InstructionMark im(this);
4105 prefix(src, dst);
4106 emit_int8(0x33);
4107 emit_operand(dst, src);
4108 }
4109
4110 void Assembler::xorl(Register dst, Register src) {
4111 (void) prefix_and_encode(dst->encoding(), src->encoding());
4112 emit_arith(0x33, 0xC0, dst, src);
4113 }
4114
4115
4116 // AVX 3-operands scalar float-point arithmetic instructions
4117
4118 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4119 assert(VM_Version::supports_avx(), "");
4120 InstructionMark im(this);
4121 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4122 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4123 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4124 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4125 emit_int8(0x58);
4126 emit_operand(dst, src);
4127 }
4128
4129 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4130 assert(VM_Version::supports_avx(), "");
4131 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4132 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4133 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4134 emit_int8(0x58);
4135 emit_int8((unsigned char)(0xC0 | encode));
4136 }
4137
4138 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4139 assert(VM_Version::supports_avx(), "");
4140 InstructionMark im(this);
4141 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4142 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4143 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4144 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4145 emit_int8(0x58);
4146 emit_operand(dst, src);
4147 }
4148
4149 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4150 assert(VM_Version::supports_avx(), "");
4151 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4152 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4153 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4154 emit_int8(0x58);
4155 emit_int8((unsigned char)(0xC0 | encode));
4156 }
4157
4158 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4159 assert(VM_Version::supports_avx(), "");
4160 InstructionMark im(this);
4161 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4162 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4163 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4164 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4165 emit_int8(0x5E);
4166 emit_operand(dst, src);
4167 }
4168
4169 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4170 assert(VM_Version::supports_avx(), "");
4171 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4172 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4173 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4174 emit_int8(0x5E);
4175 emit_int8((unsigned char)(0xC0 | encode));
4176 }
4177
4178 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4179 assert(VM_Version::supports_avx(), "");
4180 InstructionMark im(this);
4181 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4182 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4183 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4184 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4185 emit_int8(0x5E);
4186 emit_operand(dst, src);
4187 }
4188
4189 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4190 assert(VM_Version::supports_avx(), "");
4191 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4192 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4193 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4194 emit_int8(0x5E);
4195 emit_int8((unsigned char)(0xC0 | encode));
4196 }
4197
4198 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4199 assert(VM_Version::supports_avx(), "");
4200 InstructionMark im(this);
4201 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4202 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4203 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4204 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4205 emit_int8(0x59);
4206 emit_operand(dst, src);
4207 }
4208
4209 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4210 assert(VM_Version::supports_avx(), "");
4211 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4212 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4213 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4214 emit_int8(0x59);
4215 emit_int8((unsigned char)(0xC0 | encode));
4216 }
4217
4218 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4219 assert(VM_Version::supports_avx(), "");
4220 InstructionMark im(this);
4221 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4222 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4223 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4224 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4225 emit_int8(0x59);
4226 emit_operand(dst, src);
4227 }
4228
4229 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4230 assert(VM_Version::supports_avx(), "");
4231 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4232 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4233 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4234 emit_int8(0x59);
4235 emit_int8((unsigned char)(0xC0 | encode));
4236 }
4237
4238 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4239 assert(VM_Version::supports_avx(), "");
4240 InstructionMark im(this);
4241 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4242 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4243 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4244 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4245 emit_int8(0x5C);
4246 emit_operand(dst, src);
4247 }
4248
4249 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4250 assert(VM_Version::supports_avx(), "");
4251 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4252 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4253 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4254 emit_int8(0x5C);
4255 emit_int8((unsigned char)(0xC0 | encode));
4256 }
4257
4258 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4259 assert(VM_Version::supports_avx(), "");
4260 InstructionMark im(this);
4261 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4262 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4263 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4264 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4265 emit_int8(0x5C);
4266 emit_operand(dst, src);
4267 }
4268
4269 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4270 assert(VM_Version::supports_avx(), "");
4271 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4272 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4273 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4274 emit_int8(0x5C);
4275 emit_int8((unsigned char)(0xC0 | encode));
4276 }
4277
4278 //====================VECTOR ARITHMETIC=====================================
4279
4280 // Float-point vector arithmetic
4281
4282 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4284 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4285 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4286 emit_int8(0x58);
4287 emit_int8((unsigned char)(0xC0 | encode));
4288 }
4289
4290 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4292 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4294 emit_int8(0x58);
4295 emit_int8((unsigned char)(0xC0 | encode));
4296 }
4297
4298 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4299 assert(VM_Version::supports_avx(), "");
4300 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4301 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4302 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4303 emit_int8(0x58);
4304 emit_int8((unsigned char)(0xC0 | encode));
4305 }
4306
4307 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4308 assert(VM_Version::supports_avx(), "");
4309 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4310 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4311 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4312 emit_int8(0x58);
4313 emit_int8((unsigned char)(0xC0 | encode));
4314 }
4315
4316 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4317 assert(VM_Version::supports_avx(), "");
4318 InstructionMark im(this);
4319 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4320 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4321 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4322 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4323 emit_int8(0x58);
4324 emit_operand(dst, src);
4325 }
4326
4327 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4328 assert(VM_Version::supports_avx(), "");
4329 InstructionMark im(this);
4330 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4331 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4332 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4333 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4334 emit_int8(0x58);
4335 emit_operand(dst, src);
4336 }
4337
4338 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4340 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4342 emit_int8(0x5C);
4343 emit_int8((unsigned char)(0xC0 | encode));
4344 }
4345
4346 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4347 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4348 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4350 emit_int8(0x5C);
4351 emit_int8((unsigned char)(0xC0 | encode));
4352 }
4353
4354 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4355 assert(VM_Version::supports_avx(), "");
4356 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4357 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4358 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4359 emit_int8(0x5C);
4360 emit_int8((unsigned char)(0xC0 | encode));
4361 }
4362
4363 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4364 assert(VM_Version::supports_avx(), "");
4365 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4366 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4367 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4368 emit_int8(0x5C);
4369 emit_int8((unsigned char)(0xC0 | encode));
4370 }
4371
4372 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4373 assert(VM_Version::supports_avx(), "");
4374 InstructionMark im(this);
4375 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4376 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4377 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4378 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4379 emit_int8(0x5C);
4380 emit_operand(dst, src);
4381 }
4382
4383 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4384 assert(VM_Version::supports_avx(), "");
4385 InstructionMark im(this);
4386 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4387 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4388 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4389 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4390 emit_int8(0x5C);
4391 emit_operand(dst, src);
4392 }
4393
4394 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4395 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4396 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4397 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4398 emit_int8(0x59);
4399 emit_int8((unsigned char)(0xC0 | encode));
4400 }
4401
4402 void Assembler::mulpd(XMMRegister dst, Address src) {
4403 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4404 InstructionMark im(this);
4405 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4406 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4407 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4408 emit_int8(0x59);
4409 emit_operand(dst, src);
4410 }
4411
4412 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4413 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4414 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4415 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4416 emit_int8(0x59);
4417 emit_int8((unsigned char)(0xC0 | encode));
4418 }
4419
4420 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4421 assert(VM_Version::supports_avx(), "");
4422 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4423 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4424 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4425 emit_int8(0x59);
4426 emit_int8((unsigned char)(0xC0 | encode));
4427 }
4428
4429 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4430 assert(VM_Version::supports_avx(), "");
4431 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4432 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4433 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4434 emit_int8(0x59);
4435 emit_int8((unsigned char)(0xC0 | encode));
4436 }
4437
4438 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4439 assert(VM_Version::supports_avx(), "");
4440 InstructionMark im(this);
4441 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4442 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4443 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4444 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4445 emit_int8(0x59);
4446 emit_operand(dst, src);
4447 }
4448
4449 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4450 assert(VM_Version::supports_avx(), "");
4451 InstructionMark im(this);
4452 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4453 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4454 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4455 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4456 emit_int8(0x59);
4457 emit_operand(dst, src);
4458 }
4459
4460 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4461 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4462 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4463 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4464 emit_int8(0x5E);
4465 emit_int8((unsigned char)(0xC0 | encode));
4466 }
4467
4468 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4469 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4470 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4471 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4472 emit_int8(0x5E);
4473 emit_int8((unsigned char)(0xC0 | encode));
4474 }
4475
4476 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4477 assert(VM_Version::supports_avx(), "");
4478 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4479 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4480 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4481 emit_int8(0x5E);
4482 emit_int8((unsigned char)(0xC0 | encode));
4483 }
4484
4485 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4486 assert(VM_Version::supports_avx(), "");
4487 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4488 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4489 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4490 emit_int8(0x5E);
4491 emit_int8((unsigned char)(0xC0 | encode));
4492 }
4493
4494 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4495 assert(VM_Version::supports_avx(), "");
4496 InstructionMark im(this);
4497 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4498 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4499 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4500 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4501 emit_int8(0x5E);
4502 emit_operand(dst, src);
4503 }
4504
4505 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4506 assert(VM_Version::supports_avx(), "");
4507 InstructionMark im(this);
4508 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4509 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4510 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4511 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4512 emit_int8(0x5E);
4513 emit_operand(dst, src);
4514 }
4515
4516 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4517 assert(VM_Version::supports_avx(), "");
4518 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4519 int nds_enc = 0;
4520 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4521 emit_int8(0x51);
4522 emit_int8((unsigned char)(0xC0 | encode));
4523 }
4524
4525 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4526 assert(VM_Version::supports_avx(), "");
4527 InstructionMark im(this);
4528 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4529 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4530 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4531 emit_int8(0x51);
4532 emit_operand(dst, src);
4533 }
4534
4535 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4536 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4537 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4538 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4539 emit_int8(0x54);
4540 emit_int8((unsigned char)(0xC0 | encode));
4541 }
4542
4543 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4544 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4545 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4546 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4547 emit_int8(0x54);
4548 emit_int8((unsigned char)(0xC0 | encode));
4549 }
4550
4551 void Assembler::andps(XMMRegister dst, Address src) {
4552 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4553 InstructionMark im(this);
4554 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4555 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4556 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4557 emit_int8(0x54);
4558 emit_operand(dst, src);
4559 }
4560
4561 void Assembler::andpd(XMMRegister dst, Address src) {
4562 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4563 InstructionMark im(this);
4564 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4565 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4566 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4567 emit_int8(0x54);
4568 emit_operand(dst, src);
4569 }
4570
4571 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4572 assert(VM_Version::supports_avx(), "");
4573 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4574 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4575 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4576 emit_int8(0x54);
4577 emit_int8((unsigned char)(0xC0 | encode));
4578 }
4579
4580 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4581 assert(VM_Version::supports_avx(), "");
4582 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4583 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4584 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4585 emit_int8(0x54);
4586 emit_int8((unsigned char)(0xC0 | encode));
4587 }
4588
4589 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4590 assert(VM_Version::supports_avx(), "");
4591 InstructionMark im(this);
4592 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4593 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4594 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4595 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4596 emit_int8(0x54);
4597 emit_operand(dst, src);
4598 }
4599
4600 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4601 assert(VM_Version::supports_avx(), "");
4602 InstructionMark im(this);
4603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4604 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4605 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4606 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4607 emit_int8(0x54);
4608 emit_operand(dst, src);
4609 }
4610
4611 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4612 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4613 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4614 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4615 emit_int8(0x15);
4616 emit_int8((unsigned char)(0xC0 | encode));
4617 }
4618
4619 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4621 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4622 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4623 emit_int8(0x14);
4624 emit_int8((unsigned char)(0xC0 | encode));
4625 }
4626
4627 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4628 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4629 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4630 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4631 emit_int8(0x57);
4632 emit_int8((unsigned char)(0xC0 | encode));
4633 }
4634
4635 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4636 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4637 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4638 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4639 emit_int8(0x57);
4640 emit_int8((unsigned char)(0xC0 | encode));
4641 }
4642
4643 void Assembler::xorpd(XMMRegister dst, Address src) {
4644 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4645 InstructionMark im(this);
4646 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4647 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4648 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4649 emit_int8(0x57);
4650 emit_operand(dst, src);
4651 }
4652
4653 void Assembler::xorps(XMMRegister dst, Address src) {
4654 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4655 InstructionMark im(this);
4656 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4657 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4658 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4659 emit_int8(0x57);
4660 emit_operand(dst, src);
4661 }
4662
4663 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4664 assert(VM_Version::supports_avx(), "");
4665 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4666 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4667 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4668 emit_int8(0x57);
4669 emit_int8((unsigned char)(0xC0 | encode));
4670 }
4671
4672 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4673 assert(VM_Version::supports_avx(), "");
4674 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4675 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4676 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4677 emit_int8(0x57);
4678 emit_int8((unsigned char)(0xC0 | encode));
4679 }
4680
4681 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4682 assert(VM_Version::supports_avx(), "");
4683 InstructionMark im(this);
4684 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4685 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4686 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4687 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4688 emit_int8(0x57);
4689 emit_operand(dst, src);
4690 }
4691
4692 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4693 assert(VM_Version::supports_avx(), "");
4694 InstructionMark im(this);
4695 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4696 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4697 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4698 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4699 emit_int8(0x57);
4700 emit_operand(dst, src);
4701 }
4702
4703 // Integer vector arithmetic
4704 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4705 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4706 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4707 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4708 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4709 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4710 emit_int8(0x01);
4711 emit_int8((unsigned char)(0xC0 | encode));
4712 }
4713
4714 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4715 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4716 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4717 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4718 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4719 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4720 emit_int8(0x02);
4721 emit_int8((unsigned char)(0xC0 | encode));
4722 }
4723
4724 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4725 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4726 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4727 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4728 emit_int8((unsigned char)0xFC);
4729 emit_int8((unsigned char)(0xC0 | encode));
4730 }
4731
4732 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4733 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4734 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4735 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4736 emit_int8((unsigned char)0xFD);
4737 emit_int8((unsigned char)(0xC0 | encode));
4738 }
4739
4740 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4742 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4743 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4744 emit_int8((unsigned char)0xFE);
4745 emit_int8((unsigned char)(0xC0 | encode));
4746 }
4747
4748 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4750 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4751 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4752 emit_int8((unsigned char)0xD4);
4753 emit_int8((unsigned char)(0xC0 | encode));
4754 }
4755
4756 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4757 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4758 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4759 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4760 emit_int8(0x01);
4761 emit_int8((unsigned char)(0xC0 | encode));
4762 }
4763
4764 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4765 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4766 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4767 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4768 emit_int8(0x02);
4769 emit_int8((unsigned char)(0xC0 | encode));
4770 }
4771
4772 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4773 assert(UseAVX > 0, "requires some form of AVX");
4774 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4775 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4776 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4777 emit_int8((unsigned char)0xFC);
4778 emit_int8((unsigned char)(0xC0 | encode));
4779 }
4780
4781 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4782 assert(UseAVX > 0, "requires some form of AVX");
4783 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4784 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4785 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4786 emit_int8((unsigned char)0xFD);
4787 emit_int8((unsigned char)(0xC0 | encode));
4788 }
4789
4790 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4791 assert(UseAVX > 0, "requires some form of AVX");
4792 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4793 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4794 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4795 emit_int8((unsigned char)0xFE);
4796 emit_int8((unsigned char)(0xC0 | encode));
4797 }
4798
4799 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4800 assert(UseAVX > 0, "requires some form of AVX");
4801 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4802 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4803 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4804 emit_int8((unsigned char)0xD4);
4805 emit_int8((unsigned char)(0xC0 | encode));
4806 }
4807
4808 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4809 assert(UseAVX > 0, "requires some form of AVX");
4810 InstructionMark im(this);
4811 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4812 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4813 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4814 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4815 emit_int8((unsigned char)0xFC);
4816 emit_operand(dst, src);
4817 }
4818
4819 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4820 assert(UseAVX > 0, "requires some form of AVX");
4821 InstructionMark im(this);
4822 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4823 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4824 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4825 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4826 emit_int8((unsigned char)0xFD);
4827 emit_operand(dst, src);
4828 }
4829
4830 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4831 assert(UseAVX > 0, "requires some form of AVX");
4832 InstructionMark im(this);
4833 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4834 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4835 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4836 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4837 emit_int8((unsigned char)0xFE);
4838 emit_operand(dst, src);
4839 }
4840
4841 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4842 assert(UseAVX > 0, "requires some form of AVX");
4843 InstructionMark im(this);
4844 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4845 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4846 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4847 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4848 emit_int8((unsigned char)0xD4);
4849 emit_operand(dst, src);
4850 }
4851
4852 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4853 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4854 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4855 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4856 emit_int8((unsigned char)0xF8);
4857 emit_int8((unsigned char)(0xC0 | encode));
4858 }
4859
4860 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4861 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4862 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4863 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4864 emit_int8((unsigned char)0xF9);
4865 emit_int8((unsigned char)(0xC0 | encode));
4866 }
4867
4868 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4869 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4870 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4871 emit_int8((unsigned char)0xFA);
4872 emit_int8((unsigned char)(0xC0 | encode));
4873 }
4874
4875 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4876 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4877 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4878 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4879 emit_int8((unsigned char)0xFB);
4880 emit_int8((unsigned char)(0xC0 | encode));
4881 }
4882
4883 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4884 assert(UseAVX > 0, "requires some form of AVX");
4885 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4886 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4887 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4888 emit_int8((unsigned char)0xF8);
4889 emit_int8((unsigned char)(0xC0 | encode));
4890 }
4891
4892 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4893 assert(UseAVX > 0, "requires some form of AVX");
4894 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4895 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4896 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4897 emit_int8((unsigned char)0xF9);
4898 emit_int8((unsigned char)(0xC0 | encode));
4899 }
4900
4901 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4902 assert(UseAVX > 0, "requires some form of AVX");
4903 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4904 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4905 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4906 emit_int8((unsigned char)0xFA);
4907 emit_int8((unsigned char)(0xC0 | encode));
4908 }
4909
4910 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4911 assert(UseAVX > 0, "requires some form of AVX");
4912 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4913 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4914 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4915 emit_int8((unsigned char)0xFB);
4916 emit_int8((unsigned char)(0xC0 | encode));
4917 }
4918
4919 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4920 assert(UseAVX > 0, "requires some form of AVX");
4921 InstructionMark im(this);
4922 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4923 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4924 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4925 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4926 emit_int8((unsigned char)0xF8);
4927 emit_operand(dst, src);
4928 }
4929
4930 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4931 assert(UseAVX > 0, "requires some form of AVX");
4932 InstructionMark im(this);
4933 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4934 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4935 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4936 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4937 emit_int8((unsigned char)0xF9);
4938 emit_operand(dst, src);
4939 }
4940
4941 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4942 assert(UseAVX > 0, "requires some form of AVX");
4943 InstructionMark im(this);
4944 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4945 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4946 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4947 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4948 emit_int8((unsigned char)0xFA);
4949 emit_operand(dst, src);
4950 }
4951
4952 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4953 assert(UseAVX > 0, "requires some form of AVX");
4954 InstructionMark im(this);
4955 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4956 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4957 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4958 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4959 emit_int8((unsigned char)0xFB);
4960 emit_operand(dst, src);
4961 }
4962
4963 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4964 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4965 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4966 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4967 emit_int8((unsigned char)0xD5);
4968 emit_int8((unsigned char)(0xC0 | encode));
4969 }
4970
4971 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4972 assert(VM_Version::supports_sse4_1(), "");
4973 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4974 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4975 emit_int8(0x40);
4976 emit_int8((unsigned char)(0xC0 | encode));
4977 }
4978
4979 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4980 assert(UseAVX > 0, "requires some form of AVX");
4981 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4982 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4983 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4984 emit_int8((unsigned char)0xD5);
4985 emit_int8((unsigned char)(0xC0 | encode));
4986 }
4987
4988 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4989 assert(UseAVX > 0, "requires some form of AVX");
4990 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4991 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4992 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4993 emit_int8(0x40);
4994 emit_int8((unsigned char)(0xC0 | encode));
4995 }
4996
4997 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4998 assert(UseAVX > 2, "requires some form of AVX");
4999 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5000 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5001 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5002 emit_int8(0x40);
5003 emit_int8((unsigned char)(0xC0 | encode));
5004 }
5005
5006 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5007 assert(UseAVX > 0, "requires some form of AVX");
5008 InstructionMark im(this);
5009 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5010 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5011 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5012 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5013 emit_int8((unsigned char)0xD5);
5014 emit_operand(dst, src);
5015 }
5016
5017 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5018 assert(UseAVX > 0, "requires some form of AVX");
5019 InstructionMark im(this);
5020 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5021 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5022 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5023 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5024 emit_int8(0x40);
5025 emit_operand(dst, src);
5026 }
5027
5028 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5029 assert(UseAVX > 0, "requires some form of AVX");
5030 InstructionMark im(this);
5031 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5032 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5033 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5034 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5035 emit_int8(0x40);
5036 emit_operand(dst, src);
5037 }
5038
5039 // Shift packed integers left by specified number of bits.
5040 void Assembler::psllw(XMMRegister dst, int shift) {
5041 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5042 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5043 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5044 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5045 emit_int8(0x71);
5046 emit_int8((unsigned char)(0xC0 | encode));
5047 emit_int8(shift & 0xFF);
5048 }
5049
5050 void Assembler::pslld(XMMRegister dst, int shift) {
5051 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5052 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5053 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5054 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5055 emit_int8(0x72);
5056 emit_int8((unsigned char)(0xC0 | encode));
5057 emit_int8(shift & 0xFF);
5058 }
5059
5060 void Assembler::psllq(XMMRegister dst, int shift) {
5061 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5062 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5063 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5064 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5065 emit_int8(0x73);
5066 emit_int8((unsigned char)(0xC0 | encode));
5067 emit_int8(shift & 0xFF);
5068 }
5069
5070 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5071 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5072 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5073 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5074 emit_int8((unsigned char)0xF1);
5075 emit_int8((unsigned char)(0xC0 | encode));
5076 }
5077
5078 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5079 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5080 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5081 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5082 emit_int8((unsigned char)0xF2);
5083 emit_int8((unsigned char)(0xC0 | encode));
5084 }
5085
5086 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5088 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5089 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5090 emit_int8((unsigned char)0xF3);
5091 emit_int8((unsigned char)(0xC0 | encode));
5092 }
5093
5094 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5095 assert(UseAVX > 0, "requires some form of AVX");
5096 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5097 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5098 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5099 emit_int8(0x71);
5100 emit_int8((unsigned char)(0xC0 | encode));
5101 emit_int8(shift & 0xFF);
5102 }
5103
5104 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5105 assert(UseAVX > 0, "requires some form of AVX");
5106 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5107 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5108 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5109 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5110 emit_int8(0x72);
5111 emit_int8((unsigned char)(0xC0 | encode));
5112 emit_int8(shift & 0xFF);
5113 }
5114
5115 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5116 assert(UseAVX > 0, "requires some form of AVX");
5117 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5118 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5119 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5120 emit_int8(0x73);
5121 emit_int8((unsigned char)(0xC0 | encode));
5122 emit_int8(shift & 0xFF);
5123 }
5124
5125 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5126 assert(UseAVX > 0, "requires some form of AVX");
5127 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5128 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5129 emit_int8((unsigned char)0xF1);
5130 emit_int8((unsigned char)(0xC0 | encode));
5131 }
5132
5133 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5134 assert(UseAVX > 0, "requires some form of AVX");
5135 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5136 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5137 emit_int8((unsigned char)0xF2);
5138 emit_int8((unsigned char)(0xC0 | encode));
5139 }
5140
5141 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5142 assert(UseAVX > 0, "requires some form of AVX");
5143 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5144 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5145 emit_int8((unsigned char)0xF3);
5146 emit_int8((unsigned char)(0xC0 | encode));
5147 }
5148
5149 // Shift packed integers logically right by specified number of bits.
5150 void Assembler::psrlw(XMMRegister dst, int shift) {
5151 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5152 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5153 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5154 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5155 emit_int8(0x71);
5156 emit_int8((unsigned char)(0xC0 | encode));
5157 emit_int8(shift & 0xFF);
5158 }
5159
5160 void Assembler::psrld(XMMRegister dst, int shift) {
5161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5162 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5163 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5164 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5165 emit_int8(0x72);
5166 emit_int8((unsigned char)(0xC0 | encode));
5167 emit_int8(shift & 0xFF);
5168 }
5169
5170 void Assembler::psrlq(XMMRegister dst, int shift) {
5171 // Do not confuse it with psrldq SSE2 instruction which
5172 // shifts 128 bit value in xmm register by number of bytes.
5173 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5174 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5175 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5176 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5177 emit_int8(0x73);
5178 emit_int8((unsigned char)(0xC0 | encode));
5179 emit_int8(shift & 0xFF);
5180 }
5181
5182 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5183 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5184 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5185 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5186 emit_int8((unsigned char)0xD1);
5187 emit_int8((unsigned char)(0xC0 | encode));
5188 }
5189
5190 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5191 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5192 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5193 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5194 emit_int8((unsigned char)0xD2);
5195 emit_int8((unsigned char)(0xC0 | encode));
5196 }
5197
5198 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5200 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5201 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5202 emit_int8((unsigned char)0xD3);
5203 emit_int8((unsigned char)(0xC0 | encode));
5204 }
5205
5206 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5207 assert(UseAVX > 0, "requires some form of AVX");
5208 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5209 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5210 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5211 emit_int8(0x71);
5212 emit_int8((unsigned char)(0xC0 | encode));
5213 emit_int8(shift & 0xFF);
5214 }
5215
5216 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5217 assert(UseAVX > 0, "requires some form of AVX");
5218 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5219 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5220 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5221 emit_int8(0x72);
5222 emit_int8((unsigned char)(0xC0 | encode));
5223 emit_int8(shift & 0xFF);
5224 }
5225
5226 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5227 assert(UseAVX > 0, "requires some form of AVX");
5228 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5229 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5230 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5231 emit_int8(0x73);
5232 emit_int8((unsigned char)(0xC0 | encode));
5233 emit_int8(shift & 0xFF);
5234 }
5235
5236 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5237 assert(UseAVX > 0, "requires some form of AVX");
5238 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5239 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5240 emit_int8((unsigned char)0xD1);
5241 emit_int8((unsigned char)(0xC0 | encode));
5242 }
5243
5244 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5245 assert(UseAVX > 0, "requires some form of AVX");
5246 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5247 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5248 emit_int8((unsigned char)0xD2);
5249 emit_int8((unsigned char)(0xC0 | encode));
5250 }
5251
5252 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5253 assert(UseAVX > 0, "requires some form of AVX");
5254 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5255 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5256 emit_int8((unsigned char)0xD3);
5257 emit_int8((unsigned char)(0xC0 | encode));
5258 }
5259
5260 // Shift packed integers arithmetically right by specified number of bits.
5261 void Assembler::psraw(XMMRegister dst, int shift) {
5262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5263 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5264 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5265 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5266 emit_int8(0x71);
5267 emit_int8((unsigned char)(0xC0 | encode));
5268 emit_int8(shift & 0xFF);
5269 }
5270
5271 void Assembler::psrad(XMMRegister dst, int shift) {
5272 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5273 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5274 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5275 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5276 emit_int8(0x72);
5277 emit_int8((unsigned char)(0xC0 | encode));
5278 emit_int8(shift & 0xFF);
5279 }
5280
5281 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5282 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5283 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5284 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5285 emit_int8((unsigned char)0xE1);
5286 emit_int8((unsigned char)(0xC0 | encode));
5287 }
5288
5289 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5290 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5291 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5292 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5293 emit_int8((unsigned char)0xE2);
5294 emit_int8((unsigned char)(0xC0 | encode));
5295 }
5296
5297 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5298 assert(UseAVX > 0, "requires some form of AVX");
5299 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5300 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5301 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5302 emit_int8(0x71);
5303 emit_int8((unsigned char)(0xC0 | encode));
5304 emit_int8(shift & 0xFF);
5305 }
5306
5307 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5308 assert(UseAVX > 0, "requires some form of AVX");
5309 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5310 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5311 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5312 emit_int8(0x72);
5313 emit_int8((unsigned char)(0xC0 | encode));
5314 emit_int8(shift & 0xFF);
5315 }
5316
5317 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5318 assert(UseAVX > 0, "requires some form of AVX");
5319 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5320 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5321 emit_int8((unsigned char)0xE1);
5322 emit_int8((unsigned char)(0xC0 | encode));
5323 }
5324
5325 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5326 assert(UseAVX > 0, "requires some form of AVX");
5327 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5328 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5329 emit_int8((unsigned char)0xE2);
5330 emit_int8((unsigned char)(0xC0 | encode));
5331 }
5332
5333
5334 // logical operations packed integers
5335 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5336 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5337 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5338 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5339 emit_int8((unsigned char)0xDB);
5340 emit_int8((unsigned char)(0xC0 | encode));
5341 }
5342
5343 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5344 assert(UseAVX > 0, "requires some form of AVX");
5345 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5346 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5347 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5348 emit_int8((unsigned char)0xDB);
5349 emit_int8((unsigned char)(0xC0 | encode));
5350 }
5351
5352 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5353 assert(UseAVX > 0, "requires some form of AVX");
5354 InstructionMark im(this);
5355 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5356 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5357 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5358 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5359 emit_int8((unsigned char)0xDB);
5360 emit_operand(dst, src);
5361 }
5362
5363 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5365 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5366 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5367 emit_int8((unsigned char)0xDF);
5368 emit_int8((unsigned char)(0xC0 | encode));
5369 }
5370
5371 void Assembler::por(XMMRegister dst, XMMRegister src) {
5372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5373 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5374 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5375 emit_int8((unsigned char)0xEB);
5376 emit_int8((unsigned char)(0xC0 | encode));
5377 }
5378
5379 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5380 assert(UseAVX > 0, "requires some form of AVX");
5381 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5382 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5383 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5384 emit_int8((unsigned char)0xEB);
5385 emit_int8((unsigned char)(0xC0 | encode));
5386 }
5387
5388 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5389 assert(UseAVX > 0, "requires some form of AVX");
5390 InstructionMark im(this);
5391 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5392 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5393 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5394 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5395 emit_int8((unsigned char)0xEB);
5396 emit_operand(dst, src);
5397 }
5398
5399 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5400 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5401 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5402 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5403 emit_int8((unsigned char)0xEF);
5404 emit_int8((unsigned char)(0xC0 | encode));
5405 }
5406
5407 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5408 assert(UseAVX > 0, "requires some form of AVX");
5409 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5410 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5411 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5412 emit_int8((unsigned char)0xEF);
5413 emit_int8((unsigned char)(0xC0 | encode));
5414 }
5415
5416 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5417 assert(UseAVX > 0, "requires some form of AVX");
5418 InstructionMark im(this);
5419 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5420 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5421 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5422 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5423 emit_int8((unsigned char)0xEF);
5424 emit_operand(dst, src);
5425 }
5426
5427
5428 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5429 assert(VM_Version::supports_avx(), "");
5430 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5431 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5432 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5433 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5434 emit_int8(0x18);
5435 emit_int8((unsigned char)(0xC0 | encode));
5436 // 0x00 - insert into lower 128 bits
5437 // 0x01 - insert into upper 128 bits
5438 emit_int8(0x01);
5439 }
5440
5441 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5442 assert(VM_Version::supports_evex(), "");
5443 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5444 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5445 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5446 emit_int8(0x1A);
5447 emit_int8((unsigned char)(0xC0 | encode));
5448 // 0x00 - insert into lower 256 bits
5449 // 0x01 - insert into upper 256 bits
5450 emit_int8(value & 0x01);
5451 }
5452
5453 void Assembler::vinsertf64x4h(XMMRegister dst, Address src, int value) {
5454 assert(VM_Version::supports_evex(), "");
5455 assert(dst != xnoreg, "sanity");
5456 InstructionMark im(this);
5457 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5458 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5459 // swap src<->dst for encoding
5460 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5461 emit_int8(0x1A);
5462 emit_operand(dst, src);
5463 // 0x00 - insert into lower 256 bits
5464 // 0x01 - insert into upper 128 bits
5465 emit_int8(value & 0x01);
5466 }
5467
5468 void Assembler::vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5469 assert(VM_Version::supports_evex(), "");
5470 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5471 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5472 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5473 emit_int8(0x18);
5474 emit_int8((unsigned char)(0xC0 | encode));
5475 // 0x00 - insert into q0 128 bits (0..127)
5476 // 0x01 - insert into q1 128 bits (128..255)
5477 // 0x02 - insert into q2 128 bits (256..383)
5478 // 0x03 - insert into q3 128 bits (384..511)
5479 emit_int8(value & 0x3);
5480 }
5481
5482 void Assembler::vinsertf32x4h(XMMRegister dst, Address src, int value) {
5483 assert(VM_Version::supports_avx(), "");
5484 assert(dst != xnoreg, "sanity");
5485 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5486 InstructionMark im(this);
5487 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5488 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5489 // swap src<->dst for encoding
5490 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5491 emit_int8(0x18);
5492 emit_operand(dst, src);
5493 // 0x00 - insert into q0 128 bits (0..127)
5494 // 0x01 - insert into q1 128 bits (128..255)
5495 // 0x02 - insert into q2 128 bits (256..383)
5496 // 0x03 - insert into q3 128 bits (384..511)
5497 emit_int8(value & 0x3);
5498 }
5499
5500 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
5501 assert(VM_Version::supports_avx(), "");
5502 assert(dst != xnoreg, "sanity");
5503 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5504 InstructionMark im(this);
5505 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5506 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5507 // swap src<->dst for encoding
5508 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5509 emit_int8(0x18);
5510 emit_operand(dst, src);
5511 // 0x01 - insert into upper 128 bits
5512 emit_int8(0x01);
5513 }
5514
5515 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
5516 assert(VM_Version::supports_avx(), "");
5517 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5518 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5519 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5520 emit_int8(0x19);
5521 emit_int8((unsigned char)(0xC0 | encode));
5522 // 0x00 - insert into lower 128 bits
5523 // 0x01 - insert into upper 128 bits
5524 emit_int8(0x01);
5525 }
5526
5527 void Assembler::vextractf128h(Address dst, XMMRegister src) {
5528 assert(VM_Version::supports_avx(), "");
5529 assert(src != xnoreg, "sanity");
5530 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5531 InstructionMark im(this);
5532 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5533 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5534 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5535 emit_int8(0x19);
5536 emit_operand(src, dst);
5537 // 0x01 - extract from upper 128 bits
5538 emit_int8(0x01);
5539 }
5540
5541 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5542 assert(VM_Version::supports_avx2(), "");
5543 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5544 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5545 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5546 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5547 emit_int8(0x38);
5548 emit_int8((unsigned char)(0xC0 | encode));
5549 // 0x00 - insert into lower 128 bits
5550 // 0x01 - insert into upper 128 bits
5551 emit_int8(0x01);
5552 }
5553
5554 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5555 assert(VM_Version::supports_evex(), "");
5556 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5557 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5558 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5559 emit_int8(0x38);
5560 emit_int8((unsigned char)(0xC0 | encode));
5561 // 0x00 - insert into lower 256 bits
5562 // 0x01 - insert into upper 256 bits
5563 emit_int8(value & 0x01);
5564 }
5565
5566 void Assembler::vinserti128h(XMMRegister dst, Address src) {
5567 assert(VM_Version::supports_avx2(), "");
5568 assert(dst != xnoreg, "sanity");
5569 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5570 InstructionMark im(this);
5571 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5572 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5573 // swap src<->dst for encoding
5574 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5575 emit_int8(0x38);
5576 emit_operand(dst, src);
5577 // 0x01 - insert into upper 128 bits
5578 emit_int8(0x01);
5579 }
5580
5581 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
5582 assert(VM_Version::supports_avx(), "");
5583 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5585 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5586 emit_int8(0x39);
5587 emit_int8((unsigned char)(0xC0 | encode));
5588 // 0x00 - insert into lower 128 bits
5589 // 0x01 - insert into upper 128 bits
5590 emit_int8(0x01);
5591 }
5592
5593 void Assembler::vextracti128h(Address dst, XMMRegister src) {
5594 assert(VM_Version::supports_avx2(), "");
5595 assert(src != xnoreg, "sanity");
5596 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5597 InstructionMark im(this);
5598 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5599 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5600 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5601 emit_int8(0x39);
5602 emit_operand(src, dst);
5603 // 0x01 - extract from upper 128 bits
5604 emit_int8(0x01);
5605 }
5606
5607 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src, int value) {
5608 assert(VM_Version::supports_evex(), "");
5609 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5610 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5611 emit_int8(0x3B);
5612 emit_int8((unsigned char)(0xC0 | encode));
5613 // 0x00 - extract from lower 256 bits
5614 // 0x01 - extract from upper 256 bits
5615 emit_int8(value & 0x01);
5616 }
5617
5618 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
5619 assert(VM_Version::supports_evex(), "");
5620 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5621 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5622 emit_int8(0x39);
5623 emit_int8((unsigned char)(0xC0 | encode));
5624 // 0x01 - extract from bits 255:128
5625 // 0x02 - extract from bits 383:256
5626 // 0x03 - extract from bits 511:384
5627 emit_int8(value & 0x3);
5628 }
5629
5630 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src, int value) {
5631 assert(VM_Version::supports_evex(), "");
5632 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5633 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5634 emit_int8(0x1B);
5635 emit_int8((unsigned char)(0xC0 | encode));
5636 // 0x00 - extract from lower 256 bits
5637 // 0x01 - extract from upper 256 bits
5638 emit_int8(value & 0x1);
5639 }
5640
5641 void Assembler::vextractf64x4h(Address dst, XMMRegister src, int value) {
5642 assert(VM_Version::supports_evex(), "");
5643 assert(src != xnoreg, "sanity");
5644 InstructionMark im(this);
5645 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5646 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
5647 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5648 emit_int8(0x1B);
5649 emit_operand(src, dst);
5650 // 0x00 - extract from lower 256 bits
5651 // 0x01 - extract from upper 256 bits
5652 emit_int8(value & 0x01);
5653 }
5654
5655 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
5656 assert(VM_Version::supports_avx(), "");
5657 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5658 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5659 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5660 emit_int8(0x19);
5661 emit_int8((unsigned char)(0xC0 | encode));
5662 // 0x00 - extract from bits 127:0
5663 // 0x01 - extract from bits 255:128
5664 // 0x02 - extract from bits 383:256
5665 // 0x03 - extract from bits 511:384
5666 emit_int8(value & 0x3);
5667 }
5668
5669 void Assembler::vextractf32x4h(Address dst, XMMRegister src, int value) {
5670 assert(VM_Version::supports_evex(), "");
5671 assert(src != xnoreg, "sanity");
5672 InstructionMark im(this);
5673 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5674 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5675 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5676 emit_int8(0x19);
5677 emit_operand(src, dst);
5678 // 0x00 - extract from bits 127:0
5679 // 0x01 - extract from bits 255:128
5680 // 0x02 - extract from bits 383:256
5681 // 0x03 - extract from bits 511:384
5682 emit_int8(value & 0x3);
5683 }
5684
5685 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
5686 assert(VM_Version::supports_evex(), "");
5687 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5688 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5689 emit_int8(0x19);
5690 emit_int8((unsigned char)(0xC0 | encode));
5691 // 0x01 - extract from bits 255:128
5692 // 0x02 - extract from bits 383:256
5693 // 0x03 - extract from bits 511:384
5694 emit_int8(value & 0x3);
5695 }
5696
5697 // duplicate 4-bytes integer data from src into 8 locations in dest
5698 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5699 assert(VM_Version::supports_avx2(), "");
5700 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5701 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5702 emit_int8(0x58);
5703 emit_int8((unsigned char)(0xC0 | encode));
5704 }
5705
5706 // duplicate 2-bytes integer data from src into 16 locations in dest
5707 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
5708 assert(VM_Version::supports_avx2(), "");
5709 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5710 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5711 emit_int8(0x79);
5712 emit_int8((unsigned char)(0xC0 | encode));
5713 }
5714
5715 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5716 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5717 assert(VM_Version::supports_evex(), "");
5718 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5719 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5720 emit_int8(0x78);
5721 emit_int8((unsigned char)(0xC0 | encode));
5722 }
5723
5724 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5725 assert(VM_Version::supports_evex(), "");
5726 assert(dst != xnoreg, "sanity");
5727 InstructionMark im(this);
5728 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5729 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
5730 // swap src<->dst for encoding
5731 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5732 emit_int8(0x78);
5733 emit_operand(dst, src);
5734 }
5735
5736 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5737 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5738 assert(VM_Version::supports_evex(), "");
5739 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5740 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5741 emit_int8(0x79);
5742 emit_int8((unsigned char)(0xC0 | encode));
5743 }
5744
5745 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5746 assert(VM_Version::supports_evex(), "");
5747 assert(dst != xnoreg, "sanity");
5748 InstructionMark im(this);
5749 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5750 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
5751 // swap src<->dst for encoding
5752 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5753 emit_int8(0x79);
5754 emit_operand(dst, src);
5755 }
5756
5757 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5758 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5759 assert(VM_Version::supports_evex(), "");
5760 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5761 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5762 emit_int8(0x58);
5763 emit_int8((unsigned char)(0xC0 | encode));
5764 }
5765
5766 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5767 assert(VM_Version::supports_evex(), "");
5768 assert(dst != xnoreg, "sanity");
5769 InstructionMark im(this);
5770 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5771 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5772 // swap src<->dst for encoding
5773 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5774 emit_int8(0x58);
5775 emit_operand(dst, src);
5776 }
5777
5778 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5779 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5780 assert(VM_Version::supports_evex(), "");
5781 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5782 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5783 emit_int8(0x59);
5784 emit_int8((unsigned char)(0xC0 | encode));
5785 }
5786
5787 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5788 assert(VM_Version::supports_evex(), "");
5789 assert(dst != xnoreg, "sanity");
5790 InstructionMark im(this);
5791 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5792 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5793 // swap src<->dst for encoding
5794 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5795 emit_int8(0x59);
5796 emit_operand(dst, src);
5797 }
5798
5799 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5800 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5801 assert(VM_Version::supports_evex(), "");
5802 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5803 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5804 emit_int8(0x18);
5805 emit_int8((unsigned char)(0xC0 | encode));
5806 }
5807
5808 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5809 assert(VM_Version::supports_evex(), "");
5810 assert(dst != xnoreg, "sanity");
5811 InstructionMark im(this);
5812 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5813 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5814 // swap src<->dst for encoding
5815 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5816 emit_int8(0x18);
5817 emit_operand(dst, src);
5818 }
5819
5820 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5821 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5822 assert(VM_Version::supports_evex(), "");
5823 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5824 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5825 emit_int8(0x19);
5826 emit_int8((unsigned char)(0xC0 | encode));
5827 }
5828
5829 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5830 assert(VM_Version::supports_evex(), "");
5831 assert(dst != xnoreg, "sanity");
5832 InstructionMark im(this);
5833 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5834 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5835 // swap src<->dst for encoding
5836 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5837 emit_int8(0x19);
5838 emit_operand(dst, src);
5839 }
5840
5841 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5842 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5843 assert(VM_Version::supports_evex(), "");
5844 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5845 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5846 emit_int8(0x7A);
5847 emit_int8((unsigned char)(0xC0 | encode));
5848 }
5849
5850 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5851 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5852 assert(VM_Version::supports_evex(), "");
5853 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5854 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5855 emit_int8(0x7B);
5856 emit_int8((unsigned char)(0xC0 | encode));
5857 }
5858
5859 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5860 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5861 assert(VM_Version::supports_evex(), "");
5862 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5863 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5864 emit_int8(0x7C);
5865 emit_int8((unsigned char)(0xC0 | encode));
5866 }
5867
5868 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5869 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5870 assert(VM_Version::supports_evex(), "");
5871 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5872 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5873 emit_int8(0x7C);
5874 emit_int8((unsigned char)(0xC0 | encode));
5875 }
5876
5877 // Carry-Less Multiplication Quadword
5878 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5879 assert(VM_Version::supports_clmul(), "");
5880 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5881 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5882 emit_int8(0x44);
5883 emit_int8((unsigned char)(0xC0 | encode));
5884 emit_int8((unsigned char)mask);
5885 }
5886
5887 // Carry-Less Multiplication Quadword
5888 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5889 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5890 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5891 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5892 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5893 emit_int8(0x44);
5894 emit_int8((unsigned char)(0xC0 | encode));
5895 emit_int8((unsigned char)mask);
5896 }
5897
5898 void Assembler::vzeroupper() {
5899 assert(VM_Version::supports_avx(), "");
5900 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5901 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5902 emit_int8(0x77);
5903 }
5904
5905
5906 #ifndef _LP64
5907 // 32bit only pieces of the assembler
5908
5909 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5910 // NO PREFIX AS NEVER 64BIT
5911 InstructionMark im(this);
5912 emit_int8((unsigned char)0x81);
5913 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5914 emit_data(imm32, rspec, 0);
5915 }
5916
5917 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5918 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5919 InstructionMark im(this);
5920 emit_int8((unsigned char)0x81);
5921 emit_operand(rdi, src1);
5922 emit_data(imm32, rspec, 0);
5923 }
5924
5925 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5926 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5927 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5928 void Assembler::cmpxchg8(Address adr) {
5929 InstructionMark im(this);
5930 emit_int8(0x0F);
5931 emit_int8((unsigned char)0xC7);
5932 emit_operand(rcx, adr);
5933 }
5934
5935 void Assembler::decl(Register dst) {
5936 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5937 emit_int8(0x48 | dst->encoding());
5938 }
5939
5940 #endif // _LP64
5941
5942 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5943
5944 void Assembler::fabs() {
5945 emit_int8((unsigned char)0xD9);
5946 emit_int8((unsigned char)0xE1);
5947 }
5948
5949 void Assembler::fadd(int i) {
5950 emit_farith(0xD8, 0xC0, i);
5951 }
5952
5953 void Assembler::fadd_d(Address src) {
5954 InstructionMark im(this);
5955 emit_int8((unsigned char)0xDC);
5956 emit_operand32(rax, src);
5957 }
5958
5959 void Assembler::fadd_s(Address src) {
5960 InstructionMark im(this);
5961 emit_int8((unsigned char)0xD8);
5962 emit_operand32(rax, src);
5963 }
5964
5965 void Assembler::fadda(int i) {
5966 emit_farith(0xDC, 0xC0, i);
5967 }
5968
5969 void Assembler::faddp(int i) {
5970 emit_farith(0xDE, 0xC0, i);
5971 }
5972
5973 void Assembler::fchs() {
5974 emit_int8((unsigned char)0xD9);
5975 emit_int8((unsigned char)0xE0);
5976 }
5977
5978 void Assembler::fcom(int i) {
5979 emit_farith(0xD8, 0xD0, i);
5980 }
5981
5982 void Assembler::fcomp(int i) {
5983 emit_farith(0xD8, 0xD8, i);
5984 }
5985
5986 void Assembler::fcomp_d(Address src) {
5987 InstructionMark im(this);
5988 emit_int8((unsigned char)0xDC);
5989 emit_operand32(rbx, src);
5990 }
5991
5992 void Assembler::fcomp_s(Address src) {
5993 InstructionMark im(this);
5994 emit_int8((unsigned char)0xD8);
5995 emit_operand32(rbx, src);
5996 }
5997
5998 void Assembler::fcompp() {
5999 emit_int8((unsigned char)0xDE);
6000 emit_int8((unsigned char)0xD9);
6001 }
6002
6003 void Assembler::fcos() {
6004 emit_int8((unsigned char)0xD9);
6005 emit_int8((unsigned char)0xFF);
6006 }
6007
6008 void Assembler::fdecstp() {
6009 emit_int8((unsigned char)0xD9);
6010 emit_int8((unsigned char)0xF6);
6011 }
6012
6013 void Assembler::fdiv(int i) {
6014 emit_farith(0xD8, 0xF0, i);
6015 }
6016
6017 void Assembler::fdiv_d(Address src) {
6018 InstructionMark im(this);
6019 emit_int8((unsigned char)0xDC);
6020 emit_operand32(rsi, src);
6021 }
6022
6023 void Assembler::fdiv_s(Address src) {
6024 InstructionMark im(this);
6025 emit_int8((unsigned char)0xD8);
6026 emit_operand32(rsi, src);
6027 }
6028
6029 void Assembler::fdiva(int i) {
6030 emit_farith(0xDC, 0xF8, i);
6031 }
6032
6033 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6034 // is erroneous for some of the floating-point instructions below.
6035
6036 void Assembler::fdivp(int i) {
6037 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6038 }
6039
6040 void Assembler::fdivr(int i) {
6041 emit_farith(0xD8, 0xF8, i);
6042 }
6043
6044 void Assembler::fdivr_d(Address src) {
6045 InstructionMark im(this);
6046 emit_int8((unsigned char)0xDC);
6047 emit_operand32(rdi, src);
6048 }
6049
6050 void Assembler::fdivr_s(Address src) {
6051 InstructionMark im(this);
6052 emit_int8((unsigned char)0xD8);
6053 emit_operand32(rdi, src);
6054 }
6055
6056 void Assembler::fdivra(int i) {
6057 emit_farith(0xDC, 0xF0, i);
6058 }
6059
6060 void Assembler::fdivrp(int i) {
6061 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6062 }
6063
6064 void Assembler::ffree(int i) {
6065 emit_farith(0xDD, 0xC0, i);
6066 }
6067
6068 void Assembler::fild_d(Address adr) {
6069 InstructionMark im(this);
6070 emit_int8((unsigned char)0xDF);
6071 emit_operand32(rbp, adr);
6072 }
6073
6074 void Assembler::fild_s(Address adr) {
6075 InstructionMark im(this);
6076 emit_int8((unsigned char)0xDB);
6077 emit_operand32(rax, adr);
6078 }
6079
6080 void Assembler::fincstp() {
6081 emit_int8((unsigned char)0xD9);
6082 emit_int8((unsigned char)0xF7);
6083 }
6084
6085 void Assembler::finit() {
6086 emit_int8((unsigned char)0x9B);
6087 emit_int8((unsigned char)0xDB);
6088 emit_int8((unsigned char)0xE3);
6089 }
6090
6091 void Assembler::fist_s(Address adr) {
6092 InstructionMark im(this);
6093 emit_int8((unsigned char)0xDB);
6094 emit_operand32(rdx, adr);
6095 }
6096
6097 void Assembler::fistp_d(Address adr) {
6098 InstructionMark im(this);
6099 emit_int8((unsigned char)0xDF);
6100 emit_operand32(rdi, adr);
6101 }
6102
6103 void Assembler::fistp_s(Address adr) {
6104 InstructionMark im(this);
6105 emit_int8((unsigned char)0xDB);
6106 emit_operand32(rbx, adr);
6107 }
6108
6109 void Assembler::fld1() {
6110 emit_int8((unsigned char)0xD9);
6111 emit_int8((unsigned char)0xE8);
6112 }
6113
6114 void Assembler::fld_d(Address adr) {
6115 InstructionMark im(this);
6116 emit_int8((unsigned char)0xDD);
6117 emit_operand32(rax, adr);
6118 }
6119
6120 void Assembler::fld_s(Address adr) {
6121 InstructionMark im(this);
6122 emit_int8((unsigned char)0xD9);
6123 emit_operand32(rax, adr);
6124 }
6125
6126
6127 void Assembler::fld_s(int index) {
6128 emit_farith(0xD9, 0xC0, index);
6129 }
6130
6131 void Assembler::fld_x(Address adr) {
6132 InstructionMark im(this);
6133 emit_int8((unsigned char)0xDB);
6134 emit_operand32(rbp, adr);
6135 }
6136
6137 void Assembler::fldcw(Address src) {
6138 InstructionMark im(this);
6139 emit_int8((unsigned char)0xD9);
6140 emit_operand32(rbp, src);
6141 }
6142
6143 void Assembler::fldenv(Address src) {
6144 InstructionMark im(this);
6145 emit_int8((unsigned char)0xD9);
6146 emit_operand32(rsp, src);
6147 }
6148
6149 void Assembler::fldlg2() {
6150 emit_int8((unsigned char)0xD9);
6151 emit_int8((unsigned char)0xEC);
6152 }
6153
6154 void Assembler::fldln2() {
6155 emit_int8((unsigned char)0xD9);
6156 emit_int8((unsigned char)0xED);
6157 }
6158
6159 void Assembler::fldz() {
6160 emit_int8((unsigned char)0xD9);
6161 emit_int8((unsigned char)0xEE);
6162 }
6163
6164 void Assembler::flog() {
6165 fldln2();
6166 fxch();
6167 fyl2x();
6168 }
6169
6170 void Assembler::flog10() {
6171 fldlg2();
6172 fxch();
6173 fyl2x();
6174 }
6175
6176 void Assembler::fmul(int i) {
6177 emit_farith(0xD8, 0xC8, i);
6178 }
6179
6180 void Assembler::fmul_d(Address src) {
6181 InstructionMark im(this);
6182 emit_int8((unsigned char)0xDC);
6183 emit_operand32(rcx, src);
6184 }
6185
6186 void Assembler::fmul_s(Address src) {
6187 InstructionMark im(this);
6188 emit_int8((unsigned char)0xD8);
6189 emit_operand32(rcx, src);
6190 }
6191
6192 void Assembler::fmula(int i) {
6193 emit_farith(0xDC, 0xC8, i);
6194 }
6195
6196 void Assembler::fmulp(int i) {
6197 emit_farith(0xDE, 0xC8, i);
6198 }
6199
6200 void Assembler::fnsave(Address dst) {
6201 InstructionMark im(this);
6202 emit_int8((unsigned char)0xDD);
6203 emit_operand32(rsi, dst);
6204 }
6205
6206 void Assembler::fnstcw(Address src) {
6207 InstructionMark im(this);
6208 emit_int8((unsigned char)0x9B);
6209 emit_int8((unsigned char)0xD9);
6210 emit_operand32(rdi, src);
6211 }
6212
6213 void Assembler::fnstsw_ax() {
6214 emit_int8((unsigned char)0xDF);
6215 emit_int8((unsigned char)0xE0);
6216 }
6217
6218 void Assembler::fprem() {
6219 emit_int8((unsigned char)0xD9);
6220 emit_int8((unsigned char)0xF8);
6221 }
6222
6223 void Assembler::fprem1() {
6224 emit_int8((unsigned char)0xD9);
6225 emit_int8((unsigned char)0xF5);
6226 }
6227
6228 void Assembler::frstor(Address src) {
6229 InstructionMark im(this);
6230 emit_int8((unsigned char)0xDD);
6231 emit_operand32(rsp, src);
6232 }
6233
6234 void Assembler::fsin() {
6235 emit_int8((unsigned char)0xD9);
6236 emit_int8((unsigned char)0xFE);
6237 }
6238
6239 void Assembler::fsqrt() {
6240 emit_int8((unsigned char)0xD9);
6241 emit_int8((unsigned char)0xFA);
6242 }
6243
6244 void Assembler::fst_d(Address adr) {
6245 InstructionMark im(this);
6246 emit_int8((unsigned char)0xDD);
6247 emit_operand32(rdx, adr);
6248 }
6249
6250 void Assembler::fst_s(Address adr) {
6251 InstructionMark im(this);
6252 emit_int8((unsigned char)0xD9);
6253 emit_operand32(rdx, adr);
6254 }
6255
6256 void Assembler::fstp_d(Address adr) {
6257 InstructionMark im(this);
6258 emit_int8((unsigned char)0xDD);
6259 emit_operand32(rbx, adr);
6260 }
6261
6262 void Assembler::fstp_d(int index) {
6263 emit_farith(0xDD, 0xD8, index);
6264 }
6265
6266 void Assembler::fstp_s(Address adr) {
6267 InstructionMark im(this);
6268 emit_int8((unsigned char)0xD9);
6269 emit_operand32(rbx, adr);
6270 }
6271
6272 void Assembler::fstp_x(Address adr) {
6273 InstructionMark im(this);
6274 emit_int8((unsigned char)0xDB);
6275 emit_operand32(rdi, adr);
6276 }
6277
6278 void Assembler::fsub(int i) {
6279 emit_farith(0xD8, 0xE0, i);
6280 }
6281
6282 void Assembler::fsub_d(Address src) {
6283 InstructionMark im(this);
6284 emit_int8((unsigned char)0xDC);
6285 emit_operand32(rsp, src);
6286 }
6287
6288 void Assembler::fsub_s(Address src) {
6289 InstructionMark im(this);
6290 emit_int8((unsigned char)0xD8);
6291 emit_operand32(rsp, src);
6292 }
6293
6294 void Assembler::fsuba(int i) {
6295 emit_farith(0xDC, 0xE8, i);
6296 }
6297
6298 void Assembler::fsubp(int i) {
6299 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6300 }
6301
6302 void Assembler::fsubr(int i) {
6303 emit_farith(0xD8, 0xE8, i);
6304 }
6305
6306 void Assembler::fsubr_d(Address src) {
6307 InstructionMark im(this);
6308 emit_int8((unsigned char)0xDC);
6309 emit_operand32(rbp, src);
6310 }
6311
6312 void Assembler::fsubr_s(Address src) {
6313 InstructionMark im(this);
6314 emit_int8((unsigned char)0xD8);
6315 emit_operand32(rbp, src);
6316 }
6317
6318 void Assembler::fsubra(int i) {
6319 emit_farith(0xDC, 0xE0, i);
6320 }
6321
6322 void Assembler::fsubrp(int i) {
6323 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6324 }
6325
6326 void Assembler::ftan() {
6327 emit_int8((unsigned char)0xD9);
6328 emit_int8((unsigned char)0xF2);
6329 emit_int8((unsigned char)0xDD);
6330 emit_int8((unsigned char)0xD8);
6331 }
6332
6333 void Assembler::ftst() {
6334 emit_int8((unsigned char)0xD9);
6335 emit_int8((unsigned char)0xE4);
6336 }
6337
6338 void Assembler::fucomi(int i) {
6339 // make sure the instruction is supported (introduced for P6, together with cmov)
6340 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6341 emit_farith(0xDB, 0xE8, i);
6342 }
6343
6344 void Assembler::fucomip(int i) {
6345 // make sure the instruction is supported (introduced for P6, together with cmov)
6346 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6347 emit_farith(0xDF, 0xE8, i);
6348 }
6349
6350 void Assembler::fwait() {
6351 emit_int8((unsigned char)0x9B);
6352 }
6353
6354 void Assembler::fxch(int i) {
6355 emit_farith(0xD9, 0xC8, i);
6356 }
6357
6358 void Assembler::fyl2x() {
6359 emit_int8((unsigned char)0xD9);
6360 emit_int8((unsigned char)0xF1);
6361 }
6362
6363 void Assembler::frndint() {
6364 emit_int8((unsigned char)0xD9);
6365 emit_int8((unsigned char)0xFC);
6366 }
6367
6368 void Assembler::f2xm1() {
6369 emit_int8((unsigned char)0xD9);
6370 emit_int8((unsigned char)0xF0);
6371 }
6372
6373 void Assembler::fldl2e() {
6374 emit_int8((unsigned char)0xD9);
6375 emit_int8((unsigned char)0xEA);
6376 }
6377
6378 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6379 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6380 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6381 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6382
6383 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6384 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6385 if (pre > 0) {
6386 emit_int8(simd_pre[pre]);
6387 }
6388 if (rex_w) {
6389 prefixq(adr, xreg);
6390 } else {
6391 prefix(adr, xreg);
6392 }
6393 if (opc > 0) {
6394 emit_int8(0x0F);
6395 int opc2 = simd_opc[opc];
6396 if (opc2 > 0) {
6397 emit_int8(opc2);
6398 }
6399 }
6400 }
6401
6402 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6403 if (pre > 0) {
6404 emit_int8(simd_pre[pre]);
6405 }
6406 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6407 if (opc > 0) {
6408 emit_int8(0x0F);
6409 int opc2 = simd_opc[opc];
6410 if (opc2 > 0) {
6411 emit_int8(opc2);
6412 }
6413 }
6414 return encode;
6415 }
6416
6417
6418 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6419 int vector_len = _attributes->get_vector_len();
6420 bool vex_w = _attributes->is_rex_vex_w();
6421 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6422 prefix(VEX_3bytes);
6423
6424 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6425 byte1 = (~byte1) & 0xE0;
6426 byte1 |= opc;
6427 emit_int8(byte1);
6428
6429 int byte2 = ((~nds_enc) & 0xf) << 3;
6430 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6431 emit_int8(byte2);
6432 } else {
6433 prefix(VEX_2bytes);
6434
6435 int byte1 = vex_r ? VEX_R : 0;
6436 byte1 = (~byte1) & 0x80;
6437 byte1 |= ((~nds_enc) & 0xf) << 3;
6438 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6439 emit_int8(byte1);
6440 }
6441 }
6442
6443 // This is a 4 byte encoding
6444 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6445 // EVEX 0x62 prefix
6446 prefix(EVEX_4bytes);
6447 bool vex_w = _attributes->is_rex_vex_w();
6448 int evex_encoding = (vex_w ? VEX_W : 0);
6449 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6450 _attributes->set_evex_encoding(evex_encoding);
6451
6452 // P0: byte 2, initialized to RXBR`00mm
6453 // instead of not'd
6454 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6455 byte2 = (~byte2) & 0xF0;
6456 // confine opc opcode extensions in mm bits to lower two bits
6457 // of form {0F, 0F_38, 0F_3A}
6458 byte2 |= opc;
6459 emit_int8(byte2);
6460
6461 // P1: byte 3 as Wvvvv1pp
6462 int byte3 = ((~nds_enc) & 0xf) << 3;
6463 // p[10] is always 1
6464 byte3 |= EVEX_F;
6465 byte3 |= (vex_w & 1) << 7;
6466 // confine pre opcode extensions in pp bits to lower two bits
6467 // of form {66, F3, F2}
6468 byte3 |= pre;
6469 emit_int8(byte3);
6470
6471 // P2: byte 4 as zL'Lbv'aaa
6472 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6473 // EVEX.v` for extending EVEX.vvvv or VIDX
6474 byte4 |= (evex_v ? 0: EVEX_V);
6475 // third EXEC.b for broadcast actions
6476 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6477 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6478 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6479 // last is EVEX.z for zero/merge actions
6480 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6481 emit_int8(byte4);
6482 }
6483
6484 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6485 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6486 bool vex_b = adr.base_needs_rex();
6487 bool vex_x = adr.index_needs_rex();
6488 set_attributes(attributes);
6489 attributes->set_current_assembler(this);
6490
6491 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6492 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6493 switch (attributes->get_vector_len()) {
6494 case AVX_128bit:
6495 case AVX_256bit:
6496 attributes->set_is_legacy_mode();
6497 break;
6498 }
6499 }
6500
6501 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6502 {
6503 bool evex_r = (xreg_enc >= 16);
6504 bool evex_v = (nds_enc >= 16);
6505 attributes->set_is_evex_instruction();
6506 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6507 } else {
6508 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6509 }
6510 }
6511
6512 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6513 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6514 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6515 bool vex_x = false;
6516 set_attributes(attributes);
6517 attributes->set_current_assembler(this);
6518
6519 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6520 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6521 switch (attributes->get_vector_len()) {
6522 case AVX_128bit:
6523 case AVX_256bit:
6524 if ((dst_enc >= 16) | (nds_enc >= 16) | (src_enc >= 16)) {
6525 // up propagate arithmetic instructions to meet RA requirements
6526 attributes->set_vector_len(AVX_512bit);
6527 } else {
6528 attributes->set_is_legacy_mode();
6529 }
6530 break;
6531 }
6532 }
6533
6534 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6535 {
6536 bool evex_r = (dst_enc >= 16);
6537 bool evex_v = (nds_enc >= 16);
6538 // can use vex_x as bank extender on rm encoding
6539 vex_x = (src_enc >= 16);
6540 attributes->set_is_evex_instruction();
6541 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6542 } else {
6543 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6544 }
6545
6546 // return modrm byte components for operands
6547 return (((dst_enc & 7) << 3) | (src_enc & 7));
6548 }
6549
6550
6551 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6552 VexOpcode opc, InstructionAttr *attributes) {
6553 if (UseAVX > 0) {
6554 int xreg_enc = xreg->encoding();
6555 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6556 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6557 } else {
6558 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6559 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6560 }
6561 }
6562
6563 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6564 VexOpcode opc, InstructionAttr *attributes) {
6565 int dst_enc = dst->encoding();
6566 int src_enc = src->encoding();
6567 if (UseAVX > 0) {
6568 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6569 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6570 } else {
6571 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6572 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6573 }
6574 }
6575
6576 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
6577 VexOpcode opc, InstructionAttr *attributes) {
6578 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6579 return vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), pre, opc, attributes);
6580 }
6581
6582 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
6583 VexOpcode opc, InstructionAttr *attributes) {
6584 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6585 return vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), pre, opc, attributes);
6586 }
6587
6588 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6589 assert(VM_Version::supports_avx(), "");
6590 assert(!VM_Version::supports_evex(), "");
6591 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6592 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6593 emit_int8((unsigned char)0xC2);
6594 emit_int8((unsigned char)(0xC0 | encode));
6595 emit_int8((unsigned char)(0xF & cop));
6596 }
6597
6598 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6599 assert(VM_Version::supports_avx(), "");
6600 assert(!VM_Version::supports_evex(), "");
6601 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6602 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6603 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6604 emit_int8((unsigned char)0x4B);
6605 emit_int8((unsigned char)(0xC0 | encode));
6606 int src2_enc = src2->encoding();
6607 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6608 }
6609
6610
6611 #ifndef _LP64
6612
6613 void Assembler::incl(Register dst) {
6614 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6615 emit_int8(0x40 | dst->encoding());
6616 }
6617
6618 void Assembler::lea(Register dst, Address src) {
6619 leal(dst, src);
6620 }
6621
6622 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6623 InstructionMark im(this);
6624 emit_int8((unsigned char)0xC7);
6625 emit_operand(rax, dst);
6626 emit_data((int)imm32, rspec, 0);
6627 }
6628
6629 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6630 InstructionMark im(this);
6631 int encode = prefix_and_encode(dst->encoding());
6632 emit_int8((unsigned char)(0xB8 | encode));
6633 emit_data((int)imm32, rspec, 0);
6634 }
6635
6636 void Assembler::popa() { // 32bit
6637 emit_int8(0x61);
6638 }
6639
6640 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
6641 InstructionMark im(this);
6642 emit_int8(0x68);
6643 emit_data(imm32, rspec, 0);
6644 }
6645
6646 void Assembler::pusha() { // 32bit
6647 emit_int8(0x60);
6648 }
6649
6650 void Assembler::set_byte_if_not_zero(Register dst) {
6651 emit_int8(0x0F);
6652 emit_int8((unsigned char)0x95);
6653 emit_int8((unsigned char)(0xE0 | dst->encoding()));
6654 }
6655
6656 void Assembler::shldl(Register dst, Register src) {
6657 emit_int8(0x0F);
6658 emit_int8((unsigned char)0xA5);
6659 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6660 }
6661
6662 // 0F A4 / r ib
6663 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6664 emit_int8(0x0F);
6665 emit_int8((unsigned char)0xA4);
6666 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6667 emit_int8(imm8);
6668 }
6669
6670 void Assembler::shrdl(Register dst, Register src) {
6671 emit_int8(0x0F);
6672 emit_int8((unsigned char)0xAD);
6673 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6674 }
6675
6676 #else // LP64
6677
6678 void Assembler::set_byte_if_not_zero(Register dst) {
6679 int enc = prefix_and_encode(dst->encoding(), true);
6680 emit_int8(0x0F);
6681 emit_int8((unsigned char)0x95);
6682 emit_int8((unsigned char)(0xE0 | enc));
6683 }
6684
6685 // 64bit only pieces of the assembler
6686 // This should only be used by 64bit instructions that can use rip-relative
6687 // it cannot be used by instructions that want an immediate value.
6688
6689 bool Assembler::reachable(AddressLiteral adr) {
6690 int64_t disp;
6691 // None will force a 64bit literal to the code stream. Likely a placeholder
6692 // for something that will be patched later and we need to certain it will
6693 // always be reachable.
6694 if (adr.reloc() == relocInfo::none) {
6695 return false;
6696 }
6697 if (adr.reloc() == relocInfo::internal_word_type) {
6698 // This should be rip relative and easily reachable.
6699 return true;
6700 }
6701 if (adr.reloc() == relocInfo::virtual_call_type ||
6702 adr.reloc() == relocInfo::opt_virtual_call_type ||
6703 adr.reloc() == relocInfo::static_call_type ||
6704 adr.reloc() == relocInfo::static_stub_type ) {
6705 // This should be rip relative within the code cache and easily
6706 // reachable until we get huge code caches. (At which point
6707 // ic code is going to have issues).
6708 return true;
6709 }
6710 if (adr.reloc() != relocInfo::external_word_type &&
6711 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
6712 adr.reloc() != relocInfo::poll_type && // relocs to identify them
6713 adr.reloc() != relocInfo::runtime_call_type ) {
6714 return false;
6715 }
6716
6717 // Stress the correction code
6718 if (ForceUnreachable) {
6719 // Must be runtimecall reloc, see if it is in the codecache
6720 // Flipping stuff in the codecache to be unreachable causes issues
6721 // with things like inline caches where the additional instructions
6722 // are not handled.
6723 if (CodeCache::find_blob(adr._target) == NULL) {
6724 return false;
6725 }
6726 }
6727 // For external_word_type/runtime_call_type if it is reachable from where we
6728 // are now (possibly a temp buffer) and where we might end up
6729 // anywhere in the codeCache then we are always reachable.
6730 // This would have to change if we ever save/restore shared code
6731 // to be more pessimistic.
6732 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
6733 if (!is_simm32(disp)) return false;
6734 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
6735 if (!is_simm32(disp)) return false;
6736
6737 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
6738
6739 // Because rip relative is a disp + address_of_next_instruction and we
6740 // don't know the value of address_of_next_instruction we apply a fudge factor
6741 // to make sure we will be ok no matter the size of the instruction we get placed into.
6742 // We don't have to fudge the checks above here because they are already worst case.
6743
6744 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
6745 // + 4 because better safe than sorry.
6746 const int fudge = 12 + 4;
6747 if (disp < 0) {
6748 disp -= fudge;
6749 } else {
6750 disp += fudge;
6751 }
6752 return is_simm32(disp);
6753 }
6754
6755 // Check if the polling page is not reachable from the code cache using rip-relative
6756 // addressing.
6757 bool Assembler::is_polling_page_far() {
6758 intptr_t addr = (intptr_t)os::get_polling_page();
6759 return ForceUnreachable ||
6760 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
6761 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
6762 }
6763
6764 void Assembler::emit_data64(jlong data,
6765 relocInfo::relocType rtype,
6766 int format) {
6767 if (rtype == relocInfo::none) {
6768 emit_int64(data);
6769 } else {
6770 emit_data64(data, Relocation::spec_simple(rtype), format);
6771 }
6772 }
6773
6774 void Assembler::emit_data64(jlong data,
6775 RelocationHolder const& rspec,
6776 int format) {
6777 assert(imm_operand == 0, "default format must be immediate in this file");
6778 assert(imm_operand == format, "must be immediate");
6779 assert(inst_mark() != NULL, "must be inside InstructionMark");
6780 // Do not use AbstractAssembler::relocate, which is not intended for
6781 // embedded words. Instead, relocate to the enclosing instruction.
6782 code_section()->relocate(inst_mark(), rspec, format);
6783 #ifdef ASSERT
6784 check_relocation(rspec, format);
6785 #endif
6786 emit_int64(data);
6787 }
6788
6789 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6790 if (reg_enc >= 8) {
6791 prefix(REX_B);
6792 reg_enc -= 8;
6793 } else if (byteinst && reg_enc >= 4) {
6794 prefix(REX);
6795 }
6796 return reg_enc;
6797 }
6798
6799 int Assembler::prefixq_and_encode(int reg_enc) {
6800 if (reg_enc < 8) {
6801 prefix(REX_W);
6802 } else {
6803 prefix(REX_WB);
6804 reg_enc -= 8;
6805 }
6806 return reg_enc;
6807 }
6808
6809 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
6810 if (dst_enc < 8) {
6811 if (src_enc >= 8) {
6812 prefix(REX_B);
6813 src_enc -= 8;
6814 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
6815 prefix(REX);
6816 }
6817 } else {
6818 if (src_enc < 8) {
6819 prefix(REX_R);
6820 } else {
6821 prefix(REX_RB);
6822 src_enc -= 8;
6823 }
6824 dst_enc -= 8;
6825 }
6826 return dst_enc << 3 | src_enc;
6827 }
6828
6829 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6830 if (dst_enc < 8) {
6831 if (src_enc < 8) {
6832 prefix(REX_W);
6833 } else {
6834 prefix(REX_WB);
6835 src_enc -= 8;
6836 }
6837 } else {
6838 if (src_enc < 8) {
6839 prefix(REX_WR);
6840 } else {
6841 prefix(REX_WRB);
6842 src_enc -= 8;
6843 }
6844 dst_enc -= 8;
6845 }
6846 return dst_enc << 3 | src_enc;
6847 }
6848
6849 void Assembler::prefix(Register reg) {
6850 if (reg->encoding() >= 8) {
6851 prefix(REX_B);
6852 }
6853 }
6854
6855 void Assembler::prefix(Register dst, Register src, Prefix p) {
6856 if (src->encoding() >= 8) {
6857 p = (Prefix)(p | REX_B);
6858 }
6859 if (dst->encoding() >= 8) {
6860 p = (Prefix)( p | REX_R);
6861 }
6862 if (p != Prefix_EMPTY) {
6863 // do not generate an empty prefix
6864 prefix(p);
6865 }
6866 }
6867
6868 void Assembler::prefix(Register dst, Address adr, Prefix p) {
6869 if (adr.base_needs_rex()) {
6870 if (adr.index_needs_rex()) {
6871 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6872 } else {
6873 prefix(REX_B);
6874 }
6875 } else {
6876 if (adr.index_needs_rex()) {
6877 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6878 }
6879 }
6880 if (dst->encoding() >= 8) {
6881 p = (Prefix)(p | REX_R);
6882 }
6883 if (p != Prefix_EMPTY) {
6884 // do not generate an empty prefix
6885 prefix(p);
6886 }
6887 }
6888
6889 void Assembler::prefix(Address adr) {
6890 if (adr.base_needs_rex()) {
6891 if (adr.index_needs_rex()) {
6892 prefix(REX_XB);
6893 } else {
6894 prefix(REX_B);
6895 }
6896 } else {
6897 if (adr.index_needs_rex()) {
6898 prefix(REX_X);
6899 }
6900 }
6901 }
6902
6903 void Assembler::prefixq(Address adr) {
6904 if (adr.base_needs_rex()) {
6905 if (adr.index_needs_rex()) {
6906 prefix(REX_WXB);
6907 } else {
6908 prefix(REX_WB);
6909 }
6910 } else {
6911 if (adr.index_needs_rex()) {
6912 prefix(REX_WX);
6913 } else {
6914 prefix(REX_W);
6915 }
6916 }
6917 }
6918
6919
6920 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6921 if (reg->encoding() < 8) {
6922 if (adr.base_needs_rex()) {
6923 if (adr.index_needs_rex()) {
6924 prefix(REX_XB);
6925 } else {
6926 prefix(REX_B);
6927 }
6928 } else {
6929 if (adr.index_needs_rex()) {
6930 prefix(REX_X);
6931 } else if (byteinst && reg->encoding() >= 4 ) {
6932 prefix(REX);
6933 }
6934 }
6935 } else {
6936 if (adr.base_needs_rex()) {
6937 if (adr.index_needs_rex()) {
6938 prefix(REX_RXB);
6939 } else {
6940 prefix(REX_RB);
6941 }
6942 } else {
6943 if (adr.index_needs_rex()) {
6944 prefix(REX_RX);
6945 } else {
6946 prefix(REX_R);
6947 }
6948 }
6949 }
6950 }
6951
6952 void Assembler::prefixq(Address adr, Register src) {
6953 if (src->encoding() < 8) {
6954 if (adr.base_needs_rex()) {
6955 if (adr.index_needs_rex()) {
6956 prefix(REX_WXB);
6957 } else {
6958 prefix(REX_WB);
6959 }
6960 } else {
6961 if (adr.index_needs_rex()) {
6962 prefix(REX_WX);
6963 } else {
6964 prefix(REX_W);
6965 }
6966 }
6967 } else {
6968 if (adr.base_needs_rex()) {
6969 if (adr.index_needs_rex()) {
6970 prefix(REX_WRXB);
6971 } else {
6972 prefix(REX_WRB);
6973 }
6974 } else {
6975 if (adr.index_needs_rex()) {
6976 prefix(REX_WRX);
6977 } else {
6978 prefix(REX_WR);
6979 }
6980 }
6981 }
6982 }
6983
6984 void Assembler::prefix(Address adr, XMMRegister reg) {
6985 if (reg->encoding() < 8) {
6986 if (adr.base_needs_rex()) {
6987 if (adr.index_needs_rex()) {
6988 prefix(REX_XB);
6989 } else {
6990 prefix(REX_B);
6991 }
6992 } else {
6993 if (adr.index_needs_rex()) {
6994 prefix(REX_X);
6995 }
6996 }
6997 } else {
6998 if (adr.base_needs_rex()) {
6999 if (adr.index_needs_rex()) {
7000 prefix(REX_RXB);
7001 } else {
7002 prefix(REX_RB);
7003 }
7004 } else {
7005 if (adr.index_needs_rex()) {
7006 prefix(REX_RX);
7007 } else {
7008 prefix(REX_R);
7009 }
7010 }
7011 }
7012 }
7013
7014 void Assembler::prefixq(Address adr, XMMRegister src) {
7015 if (src->encoding() < 8) {
7016 if (adr.base_needs_rex()) {
7017 if (adr.index_needs_rex()) {
7018 prefix(REX_WXB);
7019 } else {
7020 prefix(REX_WB);
7021 }
7022 } else {
7023 if (adr.index_needs_rex()) {
7024 prefix(REX_WX);
7025 } else {
7026 prefix(REX_W);
7027 }
7028 }
7029 } else {
7030 if (adr.base_needs_rex()) {
7031 if (adr.index_needs_rex()) {
7032 prefix(REX_WRXB);
7033 } else {
7034 prefix(REX_WRB);
7035 }
7036 } else {
7037 if (adr.index_needs_rex()) {
7038 prefix(REX_WRX);
7039 } else {
7040 prefix(REX_WR);
7041 }
7042 }
7043 }
7044 }
7045
7046 void Assembler::adcq(Register dst, int32_t imm32) {
7047 (void) prefixq_and_encode(dst->encoding());
7048 emit_arith(0x81, 0xD0, dst, imm32);
7049 }
7050
7051 void Assembler::adcq(Register dst, Address src) {
7052 InstructionMark im(this);
7053 prefixq(src, dst);
7054 emit_int8(0x13);
7055 emit_operand(dst, src);
7056 }
7057
7058 void Assembler::adcq(Register dst, Register src) {
7059 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7060 emit_arith(0x13, 0xC0, dst, src);
7061 }
7062
7063 void Assembler::addq(Address dst, int32_t imm32) {
7064 InstructionMark im(this);
7065 prefixq(dst);
7066 emit_arith_operand(0x81, rax, dst,imm32);
7067 }
7068
7069 void Assembler::addq(Address dst, Register src) {
7070 InstructionMark im(this);
7071 prefixq(dst, src);
7072 emit_int8(0x01);
7073 emit_operand(src, dst);
7074 }
7075
7076 void Assembler::addq(Register dst, int32_t imm32) {
7077 (void) prefixq_and_encode(dst->encoding());
7078 emit_arith(0x81, 0xC0, dst, imm32);
7079 }
7080
7081 void Assembler::addq(Register dst, Address src) {
7082 InstructionMark im(this);
7083 prefixq(src, dst);
7084 emit_int8(0x03);
7085 emit_operand(dst, src);
7086 }
7087
7088 void Assembler::addq(Register dst, Register src) {
7089 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7090 emit_arith(0x03, 0xC0, dst, src);
7091 }
7092
7093 void Assembler::adcxq(Register dst, Register src) {
7094 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7095 emit_int8((unsigned char)0x66);
7096 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7097 emit_int8(0x0F);
7098 emit_int8(0x38);
7099 emit_int8((unsigned char)0xF6);
7100 emit_int8((unsigned char)(0xC0 | encode));
7101 }
7102
7103 void Assembler::adoxq(Register dst, Register src) {
7104 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7105 emit_int8((unsigned char)0xF3);
7106 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7107 emit_int8(0x0F);
7108 emit_int8(0x38);
7109 emit_int8((unsigned char)0xF6);
7110 emit_int8((unsigned char)(0xC0 | encode));
7111 }
7112
7113 void Assembler::andq(Address dst, int32_t imm32) {
7114 InstructionMark im(this);
7115 prefixq(dst);
7116 emit_int8((unsigned char)0x81);
7117 emit_operand(rsp, dst, 4);
7118 emit_int32(imm32);
7119 }
7120
7121 void Assembler::andq(Register dst, int32_t imm32) {
7122 (void) prefixq_and_encode(dst->encoding());
7123 emit_arith(0x81, 0xE0, dst, imm32);
7124 }
7125
7126 void Assembler::andq(Register dst, Address src) {
7127 InstructionMark im(this);
7128 prefixq(src, dst);
7129 emit_int8(0x23);
7130 emit_operand(dst, src);
7131 }
7132
7133 void Assembler::andq(Register dst, Register src) {
7134 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7135 emit_arith(0x23, 0xC0, dst, src);
7136 }
7137
7138 void Assembler::andnq(Register dst, Register src1, Register src2) {
7139 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7140 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7141 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7142 emit_int8((unsigned char)0xF2);
7143 emit_int8((unsigned char)(0xC0 | encode));
7144 }
7145
7146 void Assembler::andnq(Register dst, Register src1, Address src2) {
7147 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7148 InstructionMark im(this);
7149 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7150 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7151 emit_int8((unsigned char)0xF2);
7152 emit_operand(dst, src2);
7153 }
7154
7155 void Assembler::bsfq(Register dst, Register src) {
7156 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7157 emit_int8(0x0F);
7158 emit_int8((unsigned char)0xBC);
7159 emit_int8((unsigned char)(0xC0 | encode));
7160 }
7161
7162 void Assembler::bsrq(Register dst, Register src) {
7163 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7164 emit_int8(0x0F);
7165 emit_int8((unsigned char)0xBD);
7166 emit_int8((unsigned char)(0xC0 | encode));
7167 }
7168
7169 void Assembler::bswapq(Register reg) {
7170 int encode = prefixq_and_encode(reg->encoding());
7171 emit_int8(0x0F);
7172 emit_int8((unsigned char)(0xC8 | encode));
7173 }
7174
7175 void Assembler::blsiq(Register dst, Register src) {
7176 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7177 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7178 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7179 emit_int8((unsigned char)0xF3);
7180 emit_int8((unsigned char)(0xC0 | encode));
7181 }
7182
7183 void Assembler::blsiq(Register dst, Address src) {
7184 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7185 InstructionMark im(this);
7186 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7187 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7188 emit_int8((unsigned char)0xF3);
7189 emit_operand(rbx, src);
7190 }
7191
7192 void Assembler::blsmskq(Register dst, Register src) {
7193 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7194 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7195 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7196 emit_int8((unsigned char)0xF3);
7197 emit_int8((unsigned char)(0xC0 | encode));
7198 }
7199
7200 void Assembler::blsmskq(Register dst, Address src) {
7201 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7202 InstructionMark im(this);
7203 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7204 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7205 emit_int8((unsigned char)0xF3);
7206 emit_operand(rdx, src);
7207 }
7208
7209 void Assembler::blsrq(Register dst, Register src) {
7210 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7211 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7212 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7213 emit_int8((unsigned char)0xF3);
7214 emit_int8((unsigned char)(0xC0 | encode));
7215 }
7216
7217 void Assembler::blsrq(Register dst, Address src) {
7218 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7219 InstructionMark im(this);
7220 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7221 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7222 emit_int8((unsigned char)0xF3);
7223 emit_operand(rcx, src);
7224 }
7225
7226 void Assembler::cdqq() {
7227 prefix(REX_W);
7228 emit_int8((unsigned char)0x99);
7229 }
7230
7231 void Assembler::clflush(Address adr) {
7232 prefix(adr);
7233 emit_int8(0x0F);
7234 emit_int8((unsigned char)0xAE);
7235 emit_operand(rdi, adr);
7236 }
7237
7238 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7239 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7240 emit_int8(0x0F);
7241 emit_int8(0x40 | cc);
7242 emit_int8((unsigned char)(0xC0 | encode));
7243 }
7244
7245 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7246 InstructionMark im(this);
7247 prefixq(src, dst);
7248 emit_int8(0x0F);
7249 emit_int8(0x40 | cc);
7250 emit_operand(dst, src);
7251 }
7252
7253 void Assembler::cmpq(Address dst, int32_t imm32) {
7254 InstructionMark im(this);
7255 prefixq(dst);
7256 emit_int8((unsigned char)0x81);
7257 emit_operand(rdi, dst, 4);
7258 emit_int32(imm32);
7259 }
7260
7261 void Assembler::cmpq(Register dst, int32_t imm32) {
7262 (void) prefixq_and_encode(dst->encoding());
7263 emit_arith(0x81, 0xF8, dst, imm32);
7264 }
7265
7266 void Assembler::cmpq(Address dst, Register src) {
7267 InstructionMark im(this);
7268 prefixq(dst, src);
7269 emit_int8(0x3B);
7270 emit_operand(src, dst);
7271 }
7272
7273 void Assembler::cmpq(Register dst, Register src) {
7274 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7275 emit_arith(0x3B, 0xC0, dst, src);
7276 }
7277
7278 void Assembler::cmpq(Register dst, Address src) {
7279 InstructionMark im(this);
7280 prefixq(src, dst);
7281 emit_int8(0x3B);
7282 emit_operand(dst, src);
7283 }
7284
7285 void Assembler::cmpxchgq(Register reg, Address adr) {
7286 InstructionMark im(this);
7287 prefixq(adr, reg);
7288 emit_int8(0x0F);
7289 emit_int8((unsigned char)0xB1);
7290 emit_operand(reg, adr);
7291 }
7292
7293 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7294 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7295 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7296 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7297 emit_int8(0x2A);
7298 emit_int8((unsigned char)(0xC0 | encode));
7299 }
7300
7301 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7302 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7303 InstructionMark im(this);
7304 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7305 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7306 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7307 emit_int8(0x2A);
7308 emit_operand(dst, src);
7309 }
7310
7311 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7312 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7313 InstructionMark im(this);
7314 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7315 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7316 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7317 emit_int8(0x2A);
7318 emit_operand(dst, src);
7319 }
7320
7321 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7322 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7323 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7324 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7325 emit_int8(0x2C);
7326 emit_int8((unsigned char)(0xC0 | encode));
7327 }
7328
7329 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7330 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7331 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7332 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7333 emit_int8(0x2C);
7334 emit_int8((unsigned char)(0xC0 | encode));
7335 }
7336
7337 void Assembler::decl(Register dst) {
7338 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7339 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7340 int encode = prefix_and_encode(dst->encoding());
7341 emit_int8((unsigned char)0xFF);
7342 emit_int8((unsigned char)(0xC8 | encode));
7343 }
7344
7345 void Assembler::decq(Register dst) {
7346 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7347 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7348 int encode = prefixq_and_encode(dst->encoding());
7349 emit_int8((unsigned char)0xFF);
7350 emit_int8(0xC8 | encode);
7351 }
7352
7353 void Assembler::decq(Address dst) {
7354 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7355 InstructionMark im(this);
7356 prefixq(dst);
7357 emit_int8((unsigned char)0xFF);
7358 emit_operand(rcx, dst);
7359 }
7360
7361 void Assembler::fxrstor(Address src) {
7362 prefixq(src);
7363 emit_int8(0x0F);
7364 emit_int8((unsigned char)0xAE);
7365 emit_operand(as_Register(1), src);
7366 }
7367
7368 void Assembler::xrstor(Address src) {
7369 prefixq(src);
7370 emit_int8(0x0F);
7371 emit_int8((unsigned char)0xAE);
7372 emit_operand(as_Register(5), src);
7373 }
7374
7375 void Assembler::fxsave(Address dst) {
7376 prefixq(dst);
7377 emit_int8(0x0F);
7378 emit_int8((unsigned char)0xAE);
7379 emit_operand(as_Register(0), dst);
7380 }
7381
7382 void Assembler::xsave(Address dst) {
7383 prefixq(dst);
7384 emit_int8(0x0F);
7385 emit_int8((unsigned char)0xAE);
7386 emit_operand(as_Register(4), dst);
7387 }
7388
7389 void Assembler::idivq(Register src) {
7390 int encode = prefixq_and_encode(src->encoding());
7391 emit_int8((unsigned char)0xF7);
7392 emit_int8((unsigned char)(0xF8 | encode));
7393 }
7394
7395 void Assembler::imulq(Register dst, Register src) {
7396 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7397 emit_int8(0x0F);
7398 emit_int8((unsigned char)0xAF);
7399 emit_int8((unsigned char)(0xC0 | encode));
7400 }
7401
7402 void Assembler::imulq(Register dst, Register src, int value) {
7403 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7404 if (is8bit(value)) {
7405 emit_int8(0x6B);
7406 emit_int8((unsigned char)(0xC0 | encode));
7407 emit_int8(value & 0xFF);
7408 } else {
7409 emit_int8(0x69);
7410 emit_int8((unsigned char)(0xC0 | encode));
7411 emit_int32(value);
7412 }
7413 }
7414
7415 void Assembler::imulq(Register dst, Address src) {
7416 InstructionMark im(this);
7417 prefixq(src, dst);
7418 emit_int8(0x0F);
7419 emit_int8((unsigned char) 0xAF);
7420 emit_operand(dst, src);
7421 }
7422
7423 void Assembler::incl(Register dst) {
7424 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7425 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7426 int encode = prefix_and_encode(dst->encoding());
7427 emit_int8((unsigned char)0xFF);
7428 emit_int8((unsigned char)(0xC0 | encode));
7429 }
7430
7431 void Assembler::incq(Register dst) {
7432 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7433 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7434 int encode = prefixq_and_encode(dst->encoding());
7435 emit_int8((unsigned char)0xFF);
7436 emit_int8((unsigned char)(0xC0 | encode));
7437 }
7438
7439 void Assembler::incq(Address dst) {
7440 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7441 InstructionMark im(this);
7442 prefixq(dst);
7443 emit_int8((unsigned char)0xFF);
7444 emit_operand(rax, dst);
7445 }
7446
7447 void Assembler::lea(Register dst, Address src) {
7448 leaq(dst, src);
7449 }
7450
7451 void Assembler::leaq(Register dst, Address src) {
7452 InstructionMark im(this);
7453 prefixq(src, dst);
7454 emit_int8((unsigned char)0x8D);
7455 emit_operand(dst, src);
7456 }
7457
7458 void Assembler::mov64(Register dst, int64_t imm64) {
7459 InstructionMark im(this);
7460 int encode = prefixq_and_encode(dst->encoding());
7461 emit_int8((unsigned char)(0xB8 | encode));
7462 emit_int64(imm64);
7463 }
7464
7465 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7466 InstructionMark im(this);
7467 int encode = prefixq_and_encode(dst->encoding());
7468 emit_int8(0xB8 | encode);
7469 emit_data64(imm64, rspec);
7470 }
7471
7472 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7473 InstructionMark im(this);
7474 int encode = prefix_and_encode(dst->encoding());
7475 emit_int8((unsigned char)(0xB8 | encode));
7476 emit_data((int)imm32, rspec, narrow_oop_operand);
7477 }
7478
7479 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7480 InstructionMark im(this);
7481 prefix(dst);
7482 emit_int8((unsigned char)0xC7);
7483 emit_operand(rax, dst, 4);
7484 emit_data((int)imm32, rspec, narrow_oop_operand);
7485 }
7486
7487 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7488 InstructionMark im(this);
7489 int encode = prefix_and_encode(src1->encoding());
7490 emit_int8((unsigned char)0x81);
7491 emit_int8((unsigned char)(0xF8 | encode));
7492 emit_data((int)imm32, rspec, narrow_oop_operand);
7493 }
7494
7495 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7496 InstructionMark im(this);
7497 prefix(src1);
7498 emit_int8((unsigned char)0x81);
7499 emit_operand(rax, src1, 4);
7500 emit_data((int)imm32, rspec, narrow_oop_operand);
7501 }
7502
7503 void Assembler::lzcntq(Register dst, Register src) {
7504 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7505 emit_int8((unsigned char)0xF3);
7506 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7507 emit_int8(0x0F);
7508 emit_int8((unsigned char)0xBD);
7509 emit_int8((unsigned char)(0xC0 | encode));
7510 }
7511
7512 void Assembler::movdq(XMMRegister dst, Register src) {
7513 // table D-1 says MMX/SSE2
7514 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7515 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7516 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7517 emit_int8(0x6E);
7518 emit_int8((unsigned char)(0xC0 | encode));
7519 }
7520
7521 void Assembler::movdq(Register dst, XMMRegister src) {
7522 // table D-1 says MMX/SSE2
7523 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7524 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7525 // swap src/dst to get correct prefix
7526 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7527 emit_int8(0x7E);
7528 emit_int8((unsigned char)(0xC0 | encode));
7529 }
7530
7531 void Assembler::movq(Register dst, Register src) {
7532 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7533 emit_int8((unsigned char)0x8B);
7534 emit_int8((unsigned char)(0xC0 | encode));
7535 }
7536
7537 void Assembler::movq(Register dst, Address src) {
7538 InstructionMark im(this);
7539 prefixq(src, dst);
7540 emit_int8((unsigned char)0x8B);
7541 emit_operand(dst, src);
7542 }
7543
7544 void Assembler::movq(Address dst, Register src) {
7545 InstructionMark im(this);
7546 prefixq(dst, src);
7547 emit_int8((unsigned char)0x89);
7548 emit_operand(src, dst);
7549 }
7550
7551 void Assembler::movsbq(Register dst, Address src) {
7552 InstructionMark im(this);
7553 prefixq(src, dst);
7554 emit_int8(0x0F);
7555 emit_int8((unsigned char)0xBE);
7556 emit_operand(dst, src);
7557 }
7558
7559 void Assembler::movsbq(Register dst, Register src) {
7560 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7561 emit_int8(0x0F);
7562 emit_int8((unsigned char)0xBE);
7563 emit_int8((unsigned char)(0xC0 | encode));
7564 }
7565
7566 void Assembler::movslq(Register dst, int32_t imm32) {
7567 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
7568 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
7569 // as a result we shouldn't use until tested at runtime...
7570 ShouldNotReachHere();
7571 InstructionMark im(this);
7572 int encode = prefixq_and_encode(dst->encoding());
7573 emit_int8((unsigned char)(0xC7 | encode));
7574 emit_int32(imm32);
7575 }
7576
7577 void Assembler::movslq(Address dst, int32_t imm32) {
7578 assert(is_simm32(imm32), "lost bits");
7579 InstructionMark im(this);
7580 prefixq(dst);
7581 emit_int8((unsigned char)0xC7);
7582 emit_operand(rax, dst, 4);
7583 emit_int32(imm32);
7584 }
7585
7586 void Assembler::movslq(Register dst, Address src) {
7587 InstructionMark im(this);
7588 prefixq(src, dst);
7589 emit_int8(0x63);
7590 emit_operand(dst, src);
7591 }
7592
7593 void Assembler::movslq(Register dst, Register src) {
7594 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7595 emit_int8(0x63);
7596 emit_int8((unsigned char)(0xC0 | encode));
7597 }
7598
7599 void Assembler::movswq(Register dst, Address src) {
7600 InstructionMark im(this);
7601 prefixq(src, dst);
7602 emit_int8(0x0F);
7603 emit_int8((unsigned char)0xBF);
7604 emit_operand(dst, src);
7605 }
7606
7607 void Assembler::movswq(Register dst, Register src) {
7608 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7609 emit_int8((unsigned char)0x0F);
7610 emit_int8((unsigned char)0xBF);
7611 emit_int8((unsigned char)(0xC0 | encode));
7612 }
7613
7614 void Assembler::movzbq(Register dst, Address src) {
7615 InstructionMark im(this);
7616 prefixq(src, dst);
7617 emit_int8((unsigned char)0x0F);
7618 emit_int8((unsigned char)0xB6);
7619 emit_operand(dst, src);
7620 }
7621
7622 void Assembler::movzbq(Register dst, Register src) {
7623 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7624 emit_int8(0x0F);
7625 emit_int8((unsigned char)0xB6);
7626 emit_int8(0xC0 | encode);
7627 }
7628
7629 void Assembler::movzwq(Register dst, Address src) {
7630 InstructionMark im(this);
7631 prefixq(src, dst);
7632 emit_int8((unsigned char)0x0F);
7633 emit_int8((unsigned char)0xB7);
7634 emit_operand(dst, src);
7635 }
7636
7637 void Assembler::movzwq(Register dst, Register src) {
7638 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7639 emit_int8((unsigned char)0x0F);
7640 emit_int8((unsigned char)0xB7);
7641 emit_int8((unsigned char)(0xC0 | encode));
7642 }
7643
7644 void Assembler::mulq(Address src) {
7645 InstructionMark im(this);
7646 prefixq(src);
7647 emit_int8((unsigned char)0xF7);
7648 emit_operand(rsp, src);
7649 }
7650
7651 void Assembler::mulq(Register src) {
7652 int encode = prefixq_and_encode(src->encoding());
7653 emit_int8((unsigned char)0xF7);
7654 emit_int8((unsigned char)(0xE0 | encode));
7655 }
7656
7657 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7658 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7659 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7660 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
7661 emit_int8((unsigned char)0xF6);
7662 emit_int8((unsigned char)(0xC0 | encode));
7663 }
7664
7665 void Assembler::negq(Register dst) {
7666 int encode = prefixq_and_encode(dst->encoding());
7667 emit_int8((unsigned char)0xF7);
7668 emit_int8((unsigned char)(0xD8 | encode));
7669 }
7670
7671 void Assembler::notq(Register dst) {
7672 int encode = prefixq_and_encode(dst->encoding());
7673 emit_int8((unsigned char)0xF7);
7674 emit_int8((unsigned char)(0xD0 | encode));
7675 }
7676
7677 void Assembler::orq(Address dst, int32_t imm32) {
7678 InstructionMark im(this);
7679 prefixq(dst);
7680 emit_int8((unsigned char)0x81);
7681 emit_operand(rcx, dst, 4);
7682 emit_int32(imm32);
7683 }
7684
7685 void Assembler::orq(Register dst, int32_t imm32) {
7686 (void) prefixq_and_encode(dst->encoding());
7687 emit_arith(0x81, 0xC8, dst, imm32);
7688 }
7689
7690 void Assembler::orq(Register dst, Address src) {
7691 InstructionMark im(this);
7692 prefixq(src, dst);
7693 emit_int8(0x0B);
7694 emit_operand(dst, src);
7695 }
7696
7697 void Assembler::orq(Register dst, Register src) {
7698 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7699 emit_arith(0x0B, 0xC0, dst, src);
7700 }
7701
7702 void Assembler::popa() { // 64bit
7703 movq(r15, Address(rsp, 0));
7704 movq(r14, Address(rsp, wordSize));
7705 movq(r13, Address(rsp, 2 * wordSize));
7706 movq(r12, Address(rsp, 3 * wordSize));
7707 movq(r11, Address(rsp, 4 * wordSize));
7708 movq(r10, Address(rsp, 5 * wordSize));
7709 movq(r9, Address(rsp, 6 * wordSize));
7710 movq(r8, Address(rsp, 7 * wordSize));
7711 movq(rdi, Address(rsp, 8 * wordSize));
7712 movq(rsi, Address(rsp, 9 * wordSize));
7713 movq(rbp, Address(rsp, 10 * wordSize));
7714 // skip rsp
7715 movq(rbx, Address(rsp, 12 * wordSize));
7716 movq(rdx, Address(rsp, 13 * wordSize));
7717 movq(rcx, Address(rsp, 14 * wordSize));
7718 movq(rax, Address(rsp, 15 * wordSize));
7719
7720 addq(rsp, 16 * wordSize);
7721 }
7722
7723 void Assembler::popcntq(Register dst, Address src) {
7724 assert(VM_Version::supports_popcnt(), "must support");
7725 InstructionMark im(this);
7726 emit_int8((unsigned char)0xF3);
7727 prefixq(src, dst);
7728 emit_int8((unsigned char)0x0F);
7729 emit_int8((unsigned char)0xB8);
7730 emit_operand(dst, src);
7731 }
7732
7733 void Assembler::popcntq(Register dst, Register src) {
7734 assert(VM_Version::supports_popcnt(), "must support");
7735 emit_int8((unsigned char)0xF3);
7736 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7737 emit_int8((unsigned char)0x0F);
7738 emit_int8((unsigned char)0xB8);
7739 emit_int8((unsigned char)(0xC0 | encode));
7740 }
7741
7742 void Assembler::popq(Address dst) {
7743 InstructionMark im(this);
7744 prefixq(dst);
7745 emit_int8((unsigned char)0x8F);
7746 emit_operand(rax, dst);
7747 }
7748
7749 void Assembler::pusha() { // 64bit
7750 // we have to store original rsp. ABI says that 128 bytes
7751 // below rsp are local scratch.
7752 movq(Address(rsp, -5 * wordSize), rsp);
7753
7754 subq(rsp, 16 * wordSize);
7755
7756 movq(Address(rsp, 15 * wordSize), rax);
7757 movq(Address(rsp, 14 * wordSize), rcx);
7758 movq(Address(rsp, 13 * wordSize), rdx);
7759 movq(Address(rsp, 12 * wordSize), rbx);
7760 // skip rsp
7761 movq(Address(rsp, 10 * wordSize), rbp);
7762 movq(Address(rsp, 9 * wordSize), rsi);
7763 movq(Address(rsp, 8 * wordSize), rdi);
7764 movq(Address(rsp, 7 * wordSize), r8);
7765 movq(Address(rsp, 6 * wordSize), r9);
7766 movq(Address(rsp, 5 * wordSize), r10);
7767 movq(Address(rsp, 4 * wordSize), r11);
7768 movq(Address(rsp, 3 * wordSize), r12);
7769 movq(Address(rsp, 2 * wordSize), r13);
7770 movq(Address(rsp, wordSize), r14);
7771 movq(Address(rsp, 0), r15);
7772 }
7773
7774 void Assembler::pushq(Address src) {
7775 InstructionMark im(this);
7776 prefixq(src);
7777 emit_int8((unsigned char)0xFF);
7778 emit_operand(rsi, src);
7779 }
7780
7781 void Assembler::rclq(Register dst, int imm8) {
7782 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7783 int encode = prefixq_and_encode(dst->encoding());
7784 if (imm8 == 1) {
7785 emit_int8((unsigned char)0xD1);
7786 emit_int8((unsigned char)(0xD0 | encode));
7787 } else {
7788 emit_int8((unsigned char)0xC1);
7789 emit_int8((unsigned char)(0xD0 | encode));
7790 emit_int8(imm8);
7791 }
7792 }
7793
7794 void Assembler::rcrq(Register dst, int imm8) {
7795 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7796 int encode = prefixq_and_encode(dst->encoding());
7797 if (imm8 == 1) {
7798 emit_int8((unsigned char)0xD1);
7799 emit_int8((unsigned char)(0xD8 | encode));
7800 } else {
7801 emit_int8((unsigned char)0xC1);
7802 emit_int8((unsigned char)(0xD8 | encode));
7803 emit_int8(imm8);
7804 }
7805 }
7806
7807 void Assembler::rorq(Register dst, int imm8) {
7808 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7809 int encode = prefixq_and_encode(dst->encoding());
7810 if (imm8 == 1) {
7811 emit_int8((unsigned char)0xD1);
7812 emit_int8((unsigned char)(0xC8 | encode));
7813 } else {
7814 emit_int8((unsigned char)0xC1);
7815 emit_int8((unsigned char)(0xc8 | encode));
7816 emit_int8(imm8);
7817 }
7818 }
7819
7820 void Assembler::rorxq(Register dst, Register src, int imm8) {
7821 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7822 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7823 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
7824 emit_int8((unsigned char)0xF0);
7825 emit_int8((unsigned char)(0xC0 | encode));
7826 emit_int8(imm8);
7827 }
7828
7829 void Assembler::sarq(Register dst, int imm8) {
7830 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7831 int encode = prefixq_and_encode(dst->encoding());
7832 if (imm8 == 1) {
7833 emit_int8((unsigned char)0xD1);
7834 emit_int8((unsigned char)(0xF8 | encode));
7835 } else {
7836 emit_int8((unsigned char)0xC1);
7837 emit_int8((unsigned char)(0xF8 | encode));
7838 emit_int8(imm8);
7839 }
7840 }
7841
7842 void Assembler::sarq(Register dst) {
7843 int encode = prefixq_and_encode(dst->encoding());
7844 emit_int8((unsigned char)0xD3);
7845 emit_int8((unsigned char)(0xF8 | encode));
7846 }
7847
7848 void Assembler::sbbq(Address dst, int32_t imm32) {
7849 InstructionMark im(this);
7850 prefixq(dst);
7851 emit_arith_operand(0x81, rbx, dst, imm32);
7852 }
7853
7854 void Assembler::sbbq(Register dst, int32_t imm32) {
7855 (void) prefixq_and_encode(dst->encoding());
7856 emit_arith(0x81, 0xD8, dst, imm32);
7857 }
7858
7859 void Assembler::sbbq(Register dst, Address src) {
7860 InstructionMark im(this);
7861 prefixq(src, dst);
7862 emit_int8(0x1B);
7863 emit_operand(dst, src);
7864 }
7865
7866 void Assembler::sbbq(Register dst, Register src) {
7867 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7868 emit_arith(0x1B, 0xC0, dst, src);
7869 }
7870
7871 void Assembler::shlq(Register dst, int imm8) {
7872 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7873 int encode = prefixq_and_encode(dst->encoding());
7874 if (imm8 == 1) {
7875 emit_int8((unsigned char)0xD1);
7876 emit_int8((unsigned char)(0xE0 | encode));
7877 } else {
7878 emit_int8((unsigned char)0xC1);
7879 emit_int8((unsigned char)(0xE0 | encode));
7880 emit_int8(imm8);
7881 }
7882 }
7883
7884 void Assembler::shlq(Register dst) {
7885 int encode = prefixq_and_encode(dst->encoding());
7886 emit_int8((unsigned char)0xD3);
7887 emit_int8((unsigned char)(0xE0 | encode));
7888 }
7889
7890 void Assembler::shrq(Register dst, int imm8) {
7891 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7892 int encode = prefixq_and_encode(dst->encoding());
7893 emit_int8((unsigned char)0xC1);
7894 emit_int8((unsigned char)(0xE8 | encode));
7895 emit_int8(imm8);
7896 }
7897
7898 void Assembler::shrq(Register dst) {
7899 int encode = prefixq_and_encode(dst->encoding());
7900 emit_int8((unsigned char)0xD3);
7901 emit_int8(0xE8 | encode);
7902 }
7903
7904 void Assembler::subq(Address dst, int32_t imm32) {
7905 InstructionMark im(this);
7906 prefixq(dst);
7907 emit_arith_operand(0x81, rbp, dst, imm32);
7908 }
7909
7910 void Assembler::subq(Address dst, Register src) {
7911 InstructionMark im(this);
7912 prefixq(dst, src);
7913 emit_int8(0x29);
7914 emit_operand(src, dst);
7915 }
7916
7917 void Assembler::subq(Register dst, int32_t imm32) {
7918 (void) prefixq_and_encode(dst->encoding());
7919 emit_arith(0x81, 0xE8, dst, imm32);
7920 }
7921
7922 // Force generation of a 4 byte immediate value even if it fits into 8bit
7923 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7924 (void) prefixq_and_encode(dst->encoding());
7925 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7926 }
7927
7928 void Assembler::subq(Register dst, Address src) {
7929 InstructionMark im(this);
7930 prefixq(src, dst);
7931 emit_int8(0x2B);
7932 emit_operand(dst, src);
7933 }
7934
7935 void Assembler::subq(Register dst, Register src) {
7936 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7937 emit_arith(0x2B, 0xC0, dst, src);
7938 }
7939
7940 void Assembler::testq(Register dst, int32_t imm32) {
7941 // not using emit_arith because test
7942 // doesn't support sign-extension of
7943 // 8bit operands
7944 int encode = dst->encoding();
7945 if (encode == 0) {
7946 prefix(REX_W);
7947 emit_int8((unsigned char)0xA9);
7948 } else {
7949 encode = prefixq_and_encode(encode);
7950 emit_int8((unsigned char)0xF7);
7951 emit_int8((unsigned char)(0xC0 | encode));
7952 }
7953 emit_int32(imm32);
7954 }
7955
7956 void Assembler::testq(Register dst, Register src) {
7957 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7958 emit_arith(0x85, 0xC0, dst, src);
7959 }
7960
7961 void Assembler::xaddq(Address dst, Register src) {
7962 InstructionMark im(this);
7963 prefixq(dst, src);
7964 emit_int8(0x0F);
7965 emit_int8((unsigned char)0xC1);
7966 emit_operand(src, dst);
7967 }
7968
7969 void Assembler::xchgq(Register dst, Address src) {
7970 InstructionMark im(this);
7971 prefixq(src, dst);
7972 emit_int8((unsigned char)0x87);
7973 emit_operand(dst, src);
7974 }
7975
7976 void Assembler::xchgq(Register dst, Register src) {
7977 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7978 emit_int8((unsigned char)0x87);
7979 emit_int8((unsigned char)(0xc0 | encode));
7980 }
7981
7982 void Assembler::xorq(Register dst, Register src) {
7983 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7984 emit_arith(0x33, 0xC0, dst, src);
7985 }
7986
7987 void Assembler::xorq(Register dst, Address src) {
7988 InstructionMark im(this);
7989 prefixq(src, dst);
7990 emit_int8(0x33);
7991 emit_operand(dst, src);
7992 }
7993
7994 #endif // !LP64