1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && (_attributes != NULL) && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 debug_only(has_disp32 = true);
781 break;
782
783 case 0xAD: // shrd r, a, %cl
784 case 0xAF: // imul r, a
785 case 0xBE: // movsbl r, a (movsxb)
786 case 0xBF: // movswl r, a (movsxw)
787 case 0xB6: // movzbl r, a (movzxb)
788 case 0xB7: // movzwl r, a (movzxw)
789 case REP16(0x40): // cmovl cc, r, a
790 case 0xB0: // cmpxchgb
791 case 0xB1: // cmpxchg
792 case 0xC1: // xaddl
793 case 0xC7: // cmpxchg8
794 case REP16(0x90): // setcc a
795 debug_only(has_disp32 = true);
796 // fall out of the switch to decode the address
797 break;
798
799 case 0xC4: // pinsrw r, a, #8
800 debug_only(has_disp32 = true);
801 case 0xC5: // pextrw r, r, #8
802 tail_size = 1; // the imm8
803 break;
804
805 case 0xAC: // shrd r, a, #8
806 debug_only(has_disp32 = true);
807 tail_size = 1; // the imm8
808 break;
809
810 case REP16(0x80): // jcc rdisp32
811 if (which == end_pc_operand) return ip + 4;
812 assert(which == call32_operand, "jcc has no disp32 or imm");
813 return ip;
814 default:
815 ShouldNotReachHere();
816 }
817 break;
818
819 case 0x81: // addl a, #32; addl r, #32
820 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
821 // on 32bit in the case of cmpl, the imm might be an oop
822 tail_size = 4;
823 debug_only(has_disp32 = true); // has both kinds of operands!
824 break;
825
826 case 0x83: // addl a, #8; addl r, #8
827 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
828 debug_only(has_disp32 = true); // has both kinds of operands!
829 tail_size = 1;
830 break;
831
832 case 0x9B:
833 switch (0xFF & *ip++) {
834 case 0xD9: // fnstcw a
835 debug_only(has_disp32 = true);
836 break;
837 default:
838 ShouldNotReachHere();
839 }
840 break;
841
842 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
843 case REP4(0x10): // adc...
844 case REP4(0x20): // and...
845 case REP4(0x30): // xor...
846 case REP4(0x08): // or...
847 case REP4(0x18): // sbb...
848 case REP4(0x28): // sub...
849 case 0xF7: // mull a
850 case 0x8D: // lea r, a
851 case 0x87: // xchg r, a
852 case REP4(0x38): // cmp...
853 case 0x85: // test r, a
854 debug_only(has_disp32 = true); // has both kinds of operands!
855 break;
856
857 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
858 case 0xC6: // movb a, #8
859 case 0x80: // cmpb a, #8
860 case 0x6B: // imul r, a, #8
861 debug_only(has_disp32 = true); // has both kinds of operands!
862 tail_size = 1; // the imm8
863 break;
864
865 case 0xC4: // VEX_3bytes
866 case 0xC5: // VEX_2bytes
867 assert((UseAVX > 0), "shouldn't have VEX prefix");
868 assert(ip == inst+1, "no prefixes allowed");
869 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
870 // but they have prefix 0x0F and processed when 0x0F processed above.
871 //
872 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
873 // instructions (these instructions are not supported in 64-bit mode).
874 // To distinguish them bits [7:6] are set in the VEX second byte since
875 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
876 // those VEX bits REX and vvvv bits are inverted.
877 //
878 // Fortunately C2 doesn't generate these instructions so we don't need
879 // to check for them in product version.
880
881 // Check second byte
882 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
883
884 int vex_opcode;
885 // First byte
886 if ((0xFF & *inst) == VEX_3bytes) {
887 vex_opcode = VEX_OPCODE_MASK & *ip;
888 ip++; // third byte
889 is_64bit = ((VEX_W & *ip) == VEX_W);
890 } else {
891 vex_opcode = VEX_OPCODE_0F;
892 }
893 ip++; // opcode
894 // To find the end of instruction (which == end_pc_operand).
895 switch (vex_opcode) {
896 case VEX_OPCODE_0F:
897 switch (0xFF & *ip) {
898 case 0x70: // pshufd r, r/a, #8
899 case 0x71: // ps[rl|ra|ll]w r, #8
900 case 0x72: // ps[rl|ra|ll]d r, #8
901 case 0x73: // ps[rl|ra|ll]q r, #8
902 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
903 case 0xC4: // pinsrw r, r, r/a, #8
904 case 0xC5: // pextrw r/a, r, #8
905 case 0xC6: // shufp[s|d] r, r, r/a, #8
906 tail_size = 1; // the imm8
907 break;
908 }
909 break;
910 case VEX_OPCODE_0F_3A:
911 tail_size = 1;
912 break;
913 }
914 ip++; // skip opcode
915 debug_only(has_disp32 = true); // has both kinds of operands!
916 break;
917
918 case 0x62: // EVEX_4bytes
919 assert((UseAVX > 0), "shouldn't have EVEX prefix");
920 assert(ip == inst+1, "no prefixes allowed");
921 // no EVEX collisions, all instructions that have 0x62 opcodes
922 // have EVEX versions and are subopcodes of 0x66
923 ip++; // skip P0 and exmaine W in P1
924 is_64bit = ((VEX_W & *ip) == VEX_W);
925 ip++; // move to P2
926 ip++; // skip P2, move to opcode
927 // To find the end of instruction (which == end_pc_operand).
928 switch (0xFF & *ip) {
929 case 0x61: // pcmpestri r, r/a, #8
930 case 0x70: // pshufd r, r/a, #8
931 case 0x73: // psrldq r, #8
932 tail_size = 1; // the imm8
933 break;
934 default:
935 break;
936 }
937 ip++; // skip opcode
938 debug_only(has_disp32 = true); // has both kinds of operands!
939 break;
940
941 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
942 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
943 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
944 case 0xDD: // fld_d a; fst_d a; fstp_d a
945 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
946 case 0xDF: // fild_d a; fistp_d a
947 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
948 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
949 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
950 debug_only(has_disp32 = true);
951 break;
952
953 case 0xE8: // call rdisp32
954 case 0xE9: // jmp rdisp32
955 if (which == end_pc_operand) return ip + 4;
956 assert(which == call32_operand, "call has no disp32 or imm");
957 return ip;
958
959 case 0xF0: // Lock
960 assert(os::is_MP(), "only on MP");
961 goto again_after_prefix;
962
963 case 0xF3: // For SSE
964 case 0xF2: // For SSE2
965 switch (0xFF & *ip++) {
966 case REX:
967 case REX_B:
968 case REX_X:
969 case REX_XB:
970 case REX_R:
971 case REX_RB:
972 case REX_RX:
973 case REX_RXB:
974 case REX_W:
975 case REX_WB:
976 case REX_WX:
977 case REX_WXB:
978 case REX_WR:
979 case REX_WRB:
980 case REX_WRX:
981 case REX_WRXB:
982 NOT_LP64(assert(false, "found 64bit prefix"));
983 ip++;
984 default:
985 ip++;
986 }
987 debug_only(has_disp32 = true); // has both kinds of operands!
988 break;
989
990 default:
991 ShouldNotReachHere();
992
993 #undef REP8
994 #undef REP16
995 }
996
997 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
998 #ifdef _LP64
999 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1000 #else
1001 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1002 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1003 #endif // LP64
1004 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1005
1006 // parse the output of emit_operand
1007 int op2 = 0xFF & *ip++;
1008 int base = op2 & 0x07;
1009 int op3 = -1;
1010 const int b100 = 4;
1011 const int b101 = 5;
1012 if (base == b100 && (op2 >> 6) != 3) {
1013 op3 = 0xFF & *ip++;
1014 base = op3 & 0x07; // refetch the base
1015 }
1016 // now ip points at the disp (if any)
1017
1018 switch (op2 >> 6) {
1019 case 0:
1020 // [00 reg 100][ss index base]
1021 // [00 reg 100][00 100 esp]
1022 // [00 reg base]
1023 // [00 reg 100][ss index 101][disp32]
1024 // [00 reg 101] [disp32]
1025
1026 if (base == b101) {
1027 if (which == disp32_operand)
1028 return ip; // caller wants the disp32
1029 ip += 4; // skip the disp32
1030 }
1031 break;
1032
1033 case 1:
1034 // [01 reg 100][ss index base][disp8]
1035 // [01 reg 100][00 100 esp][disp8]
1036 // [01 reg base] [disp8]
1037 ip += 1; // skip the disp8
1038 break;
1039
1040 case 2:
1041 // [10 reg 100][ss index base][disp32]
1042 // [10 reg 100][00 100 esp][disp32]
1043 // [10 reg base] [disp32]
1044 if (which == disp32_operand)
1045 return ip; // caller wants the disp32
1046 ip += 4; // skip the disp32
1047 break;
1048
1049 case 3:
1050 // [11 reg base] (not a memory addressing mode)
1051 break;
1052 }
1053
1054 if (which == end_pc_operand) {
1055 return ip + tail_size;
1056 }
1057
1058 #ifdef _LP64
1059 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1060 #else
1061 assert(which == imm_operand, "instruction has only an imm field");
1062 #endif // LP64
1063 return ip;
1064 }
1065
1066 address Assembler::locate_next_instruction(address inst) {
1067 // Secretly share code with locate_operand:
1068 return locate_operand(inst, end_pc_operand);
1069 }
1070
1071
1072 #ifdef ASSERT
1073 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1074 address inst = inst_mark();
1075 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1076 address opnd;
1077
1078 Relocation* r = rspec.reloc();
1079 if (r->type() == relocInfo::none) {
1080 return;
1081 } else if (r->is_call() || format == call32_operand) {
1082 // assert(format == imm32_operand, "cannot specify a nonzero format");
1083 opnd = locate_operand(inst, call32_operand);
1084 } else if (r->is_data()) {
1085 assert(format == imm_operand || format == disp32_operand
1086 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1087 opnd = locate_operand(inst, (WhichOperand)format);
1088 } else {
1089 assert(format == imm_operand, "cannot specify a format");
1090 return;
1091 }
1092 assert(opnd == pc(), "must put operand where relocs can find it");
1093 }
1094 #endif // ASSERT
1095
1096 void Assembler::emit_operand32(Register reg, Address adr) {
1097 assert(reg->encoding() < 8, "no extended registers");
1098 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1099 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1100 adr._rspec);
1101 }
1102
1103 void Assembler::emit_operand(Register reg, Address adr,
1104 int rip_relative_correction) {
1105 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1106 adr._rspec,
1107 rip_relative_correction);
1108 }
1109
1110 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1111 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1112 adr._rspec);
1113 }
1114
1115 // MMX operations
1116 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1117 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1118 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1119 }
1120
1121 // work around gcc (3.2.1-7a) bug
1122 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1123 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1124 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1125 }
1126
1127
1128 void Assembler::emit_farith(int b1, int b2, int i) {
1129 assert(isByte(b1) && isByte(b2), "wrong opcode");
1130 assert(0 <= i && i < 8, "illegal stack offset");
1131 emit_int8(b1);
1132 emit_int8(b2 + i);
1133 }
1134
1135
1136 // Now the Assembler instructions (identical for 32/64 bits)
1137
1138 void Assembler::adcl(Address dst, int32_t imm32) {
1139 InstructionMark im(this);
1140 prefix(dst);
1141 emit_arith_operand(0x81, rdx, dst, imm32);
1142 }
1143
1144 void Assembler::adcl(Address dst, Register src) {
1145 InstructionMark im(this);
1146 prefix(dst, src);
1147 emit_int8(0x11);
1148 emit_operand(src, dst);
1149 }
1150
1151 void Assembler::adcl(Register dst, int32_t imm32) {
1152 prefix(dst);
1153 emit_arith(0x81, 0xD0, dst, imm32);
1154 }
1155
1156 void Assembler::adcl(Register dst, Address src) {
1157 InstructionMark im(this);
1158 prefix(src, dst);
1159 emit_int8(0x13);
1160 emit_operand(dst, src);
1161 }
1162
1163 void Assembler::adcl(Register dst, Register src) {
1164 (void) prefix_and_encode(dst->encoding(), src->encoding());
1165 emit_arith(0x13, 0xC0, dst, src);
1166 }
1167
1168 void Assembler::addl(Address dst, int32_t imm32) {
1169 InstructionMark im(this);
1170 prefix(dst);
1171 emit_arith_operand(0x81, rax, dst, imm32);
1172 }
1173
1174 void Assembler::addl(Address dst, Register src) {
1175 InstructionMark im(this);
1176 prefix(dst, src);
1177 emit_int8(0x01);
1178 emit_operand(src, dst);
1179 }
1180
1181 void Assembler::addl(Register dst, int32_t imm32) {
1182 prefix(dst);
1183 emit_arith(0x81, 0xC0, dst, imm32);
1184 }
1185
1186 void Assembler::addl(Register dst, Address src) {
1187 InstructionMark im(this);
1188 prefix(src, dst);
1189 emit_int8(0x03);
1190 emit_operand(dst, src);
1191 }
1192
1193 void Assembler::addl(Register dst, Register src) {
1194 (void) prefix_and_encode(dst->encoding(), src->encoding());
1195 emit_arith(0x03, 0xC0, dst, src);
1196 }
1197
1198 void Assembler::addr_nop_4() {
1199 assert(UseAddressNop, "no CPU support");
1200 // 4 bytes: NOP DWORD PTR [EAX+0]
1201 emit_int8(0x0F);
1202 emit_int8(0x1F);
1203 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1204 emit_int8(0); // 8-bits offset (1 byte)
1205 }
1206
1207 void Assembler::addr_nop_5() {
1208 assert(UseAddressNop, "no CPU support");
1209 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1210 emit_int8(0x0F);
1211 emit_int8(0x1F);
1212 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1213 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1214 emit_int8(0); // 8-bits offset (1 byte)
1215 }
1216
1217 void Assembler::addr_nop_7() {
1218 assert(UseAddressNop, "no CPU support");
1219 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1220 emit_int8(0x0F);
1221 emit_int8(0x1F);
1222 emit_int8((unsigned char)0x80);
1223 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1224 emit_int32(0); // 32-bits offset (4 bytes)
1225 }
1226
1227 void Assembler::addr_nop_8() {
1228 assert(UseAddressNop, "no CPU support");
1229 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1230 emit_int8(0x0F);
1231 emit_int8(0x1F);
1232 emit_int8((unsigned char)0x84);
1233 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1234 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1235 emit_int32(0); // 32-bits offset (4 bytes)
1236 }
1237
1238 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1240 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1241 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1242 emit_int8(0x58);
1243 emit_int8((unsigned char)(0xC0 | encode));
1244 }
1245
1246 void Assembler::addsd(XMMRegister dst, Address src) {
1247 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1248 InstructionMark im(this);
1249 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1250 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1251 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1252 emit_int8(0x58);
1253 emit_operand(dst, src);
1254 }
1255
1256 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1257 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1258 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1260 emit_int8(0x58);
1261 emit_int8((unsigned char)(0xC0 | encode));
1262 }
1263
1264 void Assembler::addss(XMMRegister dst, Address src) {
1265 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1266 InstructionMark im(this);
1267 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1268 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1269 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1270 emit_int8(0x58);
1271 emit_operand(dst, src);
1272 }
1273
1274 void Assembler::aesdec(XMMRegister dst, Address src) {
1275 assert(VM_Version::supports_aes(), "");
1276 InstructionMark im(this);
1277 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1278 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1279 emit_int8((unsigned char)0xDE);
1280 emit_operand(dst, src);
1281 }
1282
1283 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1284 assert(VM_Version::supports_aes(), "");
1285 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1286 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1287 emit_int8((unsigned char)0xDE);
1288 emit_int8(0xC0 | encode);
1289 }
1290
1291 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1292 assert(VM_Version::supports_aes(), "");
1293 InstructionMark im(this);
1294 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1295 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1296 emit_int8((unsigned char)0xDF);
1297 emit_operand(dst, src);
1298 }
1299
1300 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1301 assert(VM_Version::supports_aes(), "");
1302 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1303 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1304 emit_int8((unsigned char)0xDF);
1305 emit_int8((unsigned char)(0xC0 | encode));
1306 }
1307
1308 void Assembler::aesenc(XMMRegister dst, Address src) {
1309 assert(VM_Version::supports_aes(), "");
1310 InstructionMark im(this);
1311 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1312 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1313 emit_int8((unsigned char)0xDC);
1314 emit_operand(dst, src);
1315 }
1316
1317 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1318 assert(VM_Version::supports_aes(), "");
1319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1320 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1321 emit_int8((unsigned char)0xDC);
1322 emit_int8(0xC0 | encode);
1323 }
1324
1325 void Assembler::aesenclast(XMMRegister dst, Address src) {
1326 assert(VM_Version::supports_aes(), "");
1327 InstructionMark im(this);
1328 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1329 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1330 emit_int8((unsigned char)0xDD);
1331 emit_operand(dst, src);
1332 }
1333
1334 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1335 assert(VM_Version::supports_aes(), "");
1336 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1337 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1338 emit_int8((unsigned char)0xDD);
1339 emit_int8((unsigned char)(0xC0 | encode));
1340 }
1341
1342 void Assembler::andl(Address dst, int32_t imm32) {
1343 InstructionMark im(this);
1344 prefix(dst);
1345 emit_int8((unsigned char)0x81);
1346 emit_operand(rsp, dst, 4);
1347 emit_int32(imm32);
1348 }
1349
1350 void Assembler::andl(Register dst, int32_t imm32) {
1351 prefix(dst);
1352 emit_arith(0x81, 0xE0, dst, imm32);
1353 }
1354
1355 void Assembler::andl(Register dst, Address src) {
1356 InstructionMark im(this);
1357 prefix(src, dst);
1358 emit_int8(0x23);
1359 emit_operand(dst, src);
1360 }
1361
1362 void Assembler::andl(Register dst, Register src) {
1363 (void) prefix_and_encode(dst->encoding(), src->encoding());
1364 emit_arith(0x23, 0xC0, dst, src);
1365 }
1366
1367 void Assembler::andnl(Register dst, Register src1, Register src2) {
1368 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1369 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1370 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1371 emit_int8((unsigned char)0xF2);
1372 emit_int8((unsigned char)(0xC0 | encode));
1373 }
1374
1375 void Assembler::andnl(Register dst, Register src1, Address src2) {
1376 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1377 InstructionMark im(this);
1378 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1379 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1380 emit_int8((unsigned char)0xF2);
1381 emit_operand(dst, src2);
1382 }
1383
1384 void Assembler::bsfl(Register dst, Register src) {
1385 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1386 emit_int8(0x0F);
1387 emit_int8((unsigned char)0xBC);
1388 emit_int8((unsigned char)(0xC0 | encode));
1389 }
1390
1391 void Assembler::bsrl(Register dst, Register src) {
1392 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1393 emit_int8(0x0F);
1394 emit_int8((unsigned char)0xBD);
1395 emit_int8((unsigned char)(0xC0 | encode));
1396 }
1397
1398 void Assembler::bswapl(Register reg) { // bswap
1399 int encode = prefix_and_encode(reg->encoding());
1400 emit_int8(0x0F);
1401 emit_int8((unsigned char)(0xC8 | encode));
1402 }
1403
1404 void Assembler::blsil(Register dst, Register src) {
1405 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1406 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1407 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1408 emit_int8((unsigned char)0xF3);
1409 emit_int8((unsigned char)(0xC0 | encode));
1410 }
1411
1412 void Assembler::blsil(Register dst, Address src) {
1413 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1414 InstructionMark im(this);
1415 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1416 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1417 emit_int8((unsigned char)0xF3);
1418 emit_operand(rbx, src);
1419 }
1420
1421 void Assembler::blsmskl(Register dst, Register src) {
1422 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1423 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1424 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1425 emit_int8((unsigned char)0xF3);
1426 emit_int8((unsigned char)(0xC0 | encode));
1427 }
1428
1429 void Assembler::blsmskl(Register dst, Address src) {
1430 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1431 InstructionMark im(this);
1432 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1433 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1434 emit_int8((unsigned char)0xF3);
1435 emit_operand(rdx, src);
1436 }
1437
1438 void Assembler::blsrl(Register dst, Register src) {
1439 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1440 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1441 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1442 emit_int8((unsigned char)0xF3);
1443 emit_int8((unsigned char)(0xC0 | encode));
1444 }
1445
1446 void Assembler::blsrl(Register dst, Address src) {
1447 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1448 InstructionMark im(this);
1449 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1450 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1451 emit_int8((unsigned char)0xF3);
1452 emit_operand(rcx, src);
1453 }
1454
1455 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1456 // suspect disp32 is always good
1457 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1458
1459 if (L.is_bound()) {
1460 const int long_size = 5;
1461 int offs = (int)( target(L) - pc() );
1462 assert(offs <= 0, "assembler error");
1463 InstructionMark im(this);
1464 // 1110 1000 #32-bit disp
1465 emit_int8((unsigned char)0xE8);
1466 emit_data(offs - long_size, rtype, operand);
1467 } else {
1468 InstructionMark im(this);
1469 // 1110 1000 #32-bit disp
1470 L.add_patch_at(code(), locator());
1471
1472 emit_int8((unsigned char)0xE8);
1473 emit_data(int(0), rtype, operand);
1474 }
1475 }
1476
1477 void Assembler::call(Register dst) {
1478 int encode = prefix_and_encode(dst->encoding());
1479 emit_int8((unsigned char)0xFF);
1480 emit_int8((unsigned char)(0xD0 | encode));
1481 }
1482
1483
1484 void Assembler::call(Address adr) {
1485 InstructionMark im(this);
1486 prefix(adr);
1487 emit_int8((unsigned char)0xFF);
1488 emit_operand(rdx, adr);
1489 }
1490
1491 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1492 assert(entry != NULL, "call most probably wrong");
1493 InstructionMark im(this);
1494 emit_int8((unsigned char)0xE8);
1495 intptr_t disp = entry - (pc() + sizeof(int32_t));
1496 assert(is_simm32(disp), "must be 32bit offset (call2)");
1497 // Technically, should use call32_operand, but this format is
1498 // implied by the fact that we're emitting a call instruction.
1499
1500 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1501 emit_data((int) disp, rspec, operand);
1502 }
1503
1504 void Assembler::cdql() {
1505 emit_int8((unsigned char)0x99);
1506 }
1507
1508 void Assembler::cld() {
1509 emit_int8((unsigned char)0xFC);
1510 }
1511
1512 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1513 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1514 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1515 emit_int8(0x0F);
1516 emit_int8(0x40 | cc);
1517 emit_int8((unsigned char)(0xC0 | encode));
1518 }
1519
1520
1521 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1522 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1523 prefix(src, dst);
1524 emit_int8(0x0F);
1525 emit_int8(0x40 | cc);
1526 emit_operand(dst, src);
1527 }
1528
1529 void Assembler::cmpb(Address dst, int imm8) {
1530 InstructionMark im(this);
1531 prefix(dst);
1532 emit_int8((unsigned char)0x80);
1533 emit_operand(rdi, dst, 1);
1534 emit_int8(imm8);
1535 }
1536
1537 void Assembler::cmpl(Address dst, int32_t imm32) {
1538 InstructionMark im(this);
1539 prefix(dst);
1540 emit_int8((unsigned char)0x81);
1541 emit_operand(rdi, dst, 4);
1542 emit_int32(imm32);
1543 }
1544
1545 void Assembler::cmpl(Register dst, int32_t imm32) {
1546 prefix(dst);
1547 emit_arith(0x81, 0xF8, dst, imm32);
1548 }
1549
1550 void Assembler::cmpl(Register dst, Register src) {
1551 (void) prefix_and_encode(dst->encoding(), src->encoding());
1552 emit_arith(0x3B, 0xC0, dst, src);
1553 }
1554
1555 void Assembler::cmpl(Register dst, Address src) {
1556 InstructionMark im(this);
1557 prefix(src, dst);
1558 emit_int8((unsigned char)0x3B);
1559 emit_operand(dst, src);
1560 }
1561
1562 void Assembler::cmpw(Address dst, int imm16) {
1563 InstructionMark im(this);
1564 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1565 emit_int8(0x66);
1566 emit_int8((unsigned char)0x81);
1567 emit_operand(rdi, dst, 2);
1568 emit_int16(imm16);
1569 }
1570
1571 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1572 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1573 // The ZF is set if the compared values were equal, and cleared otherwise.
1574 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1575 InstructionMark im(this);
1576 prefix(adr, reg);
1577 emit_int8(0x0F);
1578 emit_int8((unsigned char)0xB1);
1579 emit_operand(reg, adr);
1580 }
1581
1582 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1583 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1584 // The ZF is set if the compared values were equal, and cleared otherwise.
1585 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1586 InstructionMark im(this);
1587 prefix(adr, reg, true);
1588 emit_int8(0x0F);
1589 emit_int8((unsigned char)0xB0);
1590 emit_operand(reg, adr);
1591 }
1592
1593 void Assembler::comisd(XMMRegister dst, Address src) {
1594 // NOTE: dbx seems to decode this as comiss even though the
1595 // 0x66 is there. Strangly ucomisd comes out correct
1596 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1597 InstructionMark im(this);
1598 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1599 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1600 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1601 emit_int8(0x2F);
1602 emit_operand(dst, src);
1603 }
1604
1605 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1606 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1607 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1608 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1609 emit_int8(0x2F);
1610 emit_int8((unsigned char)(0xC0 | encode));
1611 }
1612
1613 void Assembler::comiss(XMMRegister dst, Address src) {
1614 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1615 InstructionMark im(this);
1616 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1617 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1618 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1619 emit_int8(0x2F);
1620 emit_operand(dst, src);
1621 }
1622
1623 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1624 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1625 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1626 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1627 emit_int8(0x2F);
1628 emit_int8((unsigned char)(0xC0 | encode));
1629 }
1630
1631 void Assembler::cpuid() {
1632 emit_int8(0x0F);
1633 emit_int8((unsigned char)0xA2);
1634 }
1635
1636 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1637 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1638 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1639 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1640 //
1641 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1642 //
1643 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1644 //
1645 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1646 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1647 assert(VM_Version::supports_sse4_2(), "");
1648 int8_t w = 0x01;
1649 Prefix p = Prefix_EMPTY;
1650
1651 emit_int8((int8_t)0xF2);
1652 switch (sizeInBytes) {
1653 case 1:
1654 w = 0;
1655 break;
1656 case 2:
1657 case 4:
1658 break;
1659 LP64_ONLY(case 8:)
1660 // This instruction is not valid in 32 bits
1661 // Note:
1662 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1663 //
1664 // Page B - 72 Vol. 2C says
1665 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1666 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1667 // F0!!!
1668 // while 3 - 208 Vol. 2A
1669 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1670 //
1671 // the 0 on a last bit is reserved for a different flavor of this instruction :
1672 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1673 p = REX_W;
1674 break;
1675 default:
1676 assert(0, "Unsupported value for a sizeInBytes argument");
1677 break;
1678 }
1679 LP64_ONLY(prefix(crc, v, p);)
1680 emit_int8((int8_t)0x0F);
1681 emit_int8(0x38);
1682 emit_int8((int8_t)(0xF0 | w));
1683 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1684 }
1685
1686 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1687 assert(VM_Version::supports_sse4_2(), "");
1688 InstructionMark im(this);
1689 int8_t w = 0x01;
1690 Prefix p = Prefix_EMPTY;
1691
1692 emit_int8((int8_t)0xF2);
1693 switch (sizeInBytes) {
1694 case 1:
1695 w = 0;
1696 break;
1697 case 2:
1698 case 4:
1699 break;
1700 LP64_ONLY(case 8:)
1701 // This instruction is not valid in 32 bits
1702 p = REX_W;
1703 break;
1704 default:
1705 assert(0, "Unsupported value for a sizeInBytes argument");
1706 break;
1707 }
1708 LP64_ONLY(prefix(crc, adr, p);)
1709 emit_int8((int8_t)0x0F);
1710 emit_int8(0x38);
1711 emit_int8((int8_t)(0xF0 | w));
1712 emit_operand(crc, adr);
1713 }
1714
1715 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1717 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1718 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1719 emit_int8((unsigned char)0xE6);
1720 emit_int8((unsigned char)(0xC0 | encode));
1721 }
1722
1723 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1724 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1725 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1726 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1727 emit_int8(0x5B);
1728 emit_int8((unsigned char)(0xC0 | encode));
1729 }
1730
1731 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1732 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1733 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1734 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1735 emit_int8(0x5A);
1736 emit_int8((unsigned char)(0xC0 | encode));
1737 }
1738
1739 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1740 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1741 InstructionMark im(this);
1742 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1743 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1744 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1745 emit_int8(0x5A);
1746 emit_operand(dst, src);
1747 }
1748
1749 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1752 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1753 emit_int8(0x2A);
1754 emit_int8((unsigned char)(0xC0 | encode));
1755 }
1756
1757 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionMark im(this);
1760 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1761 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1762 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1763 emit_int8(0x2A);
1764 emit_operand(dst, src);
1765 }
1766
1767 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1768 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1769 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1770 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1771 emit_int8(0x2A);
1772 emit_int8((unsigned char)(0xC0 | encode));
1773 }
1774
1775 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1776 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1777 InstructionMark im(this);
1778 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1779 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1780 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1781 emit_int8(0x2A);
1782 emit_operand(dst, src);
1783 }
1784
1785 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1786 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1787 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1788 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1789 emit_int8(0x2A);
1790 emit_int8((unsigned char)(0xC0 | encode));
1791 }
1792
1793 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1794 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1796 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1797 emit_int8(0x5A);
1798 emit_int8((unsigned char)(0xC0 | encode));
1799 }
1800
1801 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1803 InstructionMark im(this);
1804 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1805 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1806 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1807 emit_int8(0x5A);
1808 emit_operand(dst, src);
1809 }
1810
1811
1812 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1813 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1814 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1815 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1816 emit_int8(0x2C);
1817 emit_int8((unsigned char)(0xC0 | encode));
1818 }
1819
1820 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1821 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1823 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1824 emit_int8(0x2C);
1825 emit_int8((unsigned char)(0xC0 | encode));
1826 }
1827
1828 void Assembler::decl(Address dst) {
1829 // Don't use it directly. Use MacroAssembler::decrement() instead.
1830 InstructionMark im(this);
1831 prefix(dst);
1832 emit_int8((unsigned char)0xFF);
1833 emit_operand(rcx, dst);
1834 }
1835
1836 void Assembler::divsd(XMMRegister dst, Address src) {
1837 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1838 InstructionMark im(this);
1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1840 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1841 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1842 emit_int8(0x5E);
1843 emit_operand(dst, src);
1844 }
1845
1846 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1847 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1848 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1849 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1850 emit_int8(0x5E);
1851 emit_int8((unsigned char)(0xC0 | encode));
1852 }
1853
1854 void Assembler::divss(XMMRegister dst, Address src) {
1855 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1856 InstructionMark im(this);
1857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1858 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1859 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x5E);
1861 emit_operand(dst, src);
1862 }
1863
1864 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1867 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1868 emit_int8(0x5E);
1869 emit_int8((unsigned char)(0xC0 | encode));
1870 }
1871
1872 void Assembler::emms() {
1873 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1874 emit_int8(0x0F);
1875 emit_int8(0x77);
1876 }
1877
1878 void Assembler::hlt() {
1879 emit_int8((unsigned char)0xF4);
1880 }
1881
1882 void Assembler::idivl(Register src) {
1883 int encode = prefix_and_encode(src->encoding());
1884 emit_int8((unsigned char)0xF7);
1885 emit_int8((unsigned char)(0xF8 | encode));
1886 }
1887
1888 void Assembler::divl(Register src) { // Unsigned
1889 int encode = prefix_and_encode(src->encoding());
1890 emit_int8((unsigned char)0xF7);
1891 emit_int8((unsigned char)(0xF0 | encode));
1892 }
1893
1894 void Assembler::imull(Register src) {
1895 int encode = prefix_and_encode(src->encoding());
1896 emit_int8((unsigned char)0xF7);
1897 emit_int8((unsigned char)(0xE8 | encode));
1898 }
1899
1900 void Assembler::imull(Register dst, Register src) {
1901 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1902 emit_int8(0x0F);
1903 emit_int8((unsigned char)0xAF);
1904 emit_int8((unsigned char)(0xC0 | encode));
1905 }
1906
1907
1908 void Assembler::imull(Register dst, Register src, int value) {
1909 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1910 if (is8bit(value)) {
1911 emit_int8(0x6B);
1912 emit_int8((unsigned char)(0xC0 | encode));
1913 emit_int8(value & 0xFF);
1914 } else {
1915 emit_int8(0x69);
1916 emit_int8((unsigned char)(0xC0 | encode));
1917 emit_int32(value);
1918 }
1919 }
1920
1921 void Assembler::imull(Register dst, Address src) {
1922 InstructionMark im(this);
1923 prefix(src, dst);
1924 emit_int8(0x0F);
1925 emit_int8((unsigned char) 0xAF);
1926 emit_operand(dst, src);
1927 }
1928
1929
1930 void Assembler::incl(Address dst) {
1931 // Don't use it directly. Use MacroAssembler::increment() instead.
1932 InstructionMark im(this);
1933 prefix(dst);
1934 emit_int8((unsigned char)0xFF);
1935 emit_operand(rax, dst);
1936 }
1937
1938 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1939 InstructionMark im(this);
1940 assert((0 <= cc) && (cc < 16), "illegal cc");
1941 if (L.is_bound()) {
1942 address dst = target(L);
1943 assert(dst != NULL, "jcc most probably wrong");
1944
1945 const int short_size = 2;
1946 const int long_size = 6;
1947 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1948 if (maybe_short && is8bit(offs - short_size)) {
1949 // 0111 tttn #8-bit disp
1950 emit_int8(0x70 | cc);
1951 emit_int8((offs - short_size) & 0xFF);
1952 } else {
1953 // 0000 1111 1000 tttn #32-bit disp
1954 assert(is_simm32(offs - long_size),
1955 "must be 32bit offset (call4)");
1956 emit_int8(0x0F);
1957 emit_int8((unsigned char)(0x80 | cc));
1958 emit_int32(offs - long_size);
1959 }
1960 } else {
1961 // Note: could eliminate cond. jumps to this jump if condition
1962 // is the same however, seems to be rather unlikely case.
1963 // Note: use jccb() if label to be bound is very close to get
1964 // an 8-bit displacement
1965 L.add_patch_at(code(), locator());
1966 emit_int8(0x0F);
1967 emit_int8((unsigned char)(0x80 | cc));
1968 emit_int32(0);
1969 }
1970 }
1971
1972 void Assembler::jccb(Condition cc, Label& L) {
1973 if (L.is_bound()) {
1974 const int short_size = 2;
1975 address entry = target(L);
1976 #ifdef ASSERT
1977 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1978 intptr_t delta = short_branch_delta();
1979 if (delta != 0) {
1980 dist += (dist < 0 ? (-delta) :delta);
1981 }
1982 assert(is8bit(dist), "Dispacement too large for a short jmp");
1983 #endif
1984 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1985 // 0111 tttn #8-bit disp
1986 emit_int8(0x70 | cc);
1987 emit_int8((offs - short_size) & 0xFF);
1988 } else {
1989 InstructionMark im(this);
1990 L.add_patch_at(code(), locator());
1991 emit_int8(0x70 | cc);
1992 emit_int8(0);
1993 }
1994 }
1995
1996 void Assembler::jmp(Address adr) {
1997 InstructionMark im(this);
1998 prefix(adr);
1999 emit_int8((unsigned char)0xFF);
2000 emit_operand(rsp, adr);
2001 }
2002
2003 void Assembler::jmp(Label& L, bool maybe_short) {
2004 if (L.is_bound()) {
2005 address entry = target(L);
2006 assert(entry != NULL, "jmp most probably wrong");
2007 InstructionMark im(this);
2008 const int short_size = 2;
2009 const int long_size = 5;
2010 intptr_t offs = entry - pc();
2011 if (maybe_short && is8bit(offs - short_size)) {
2012 emit_int8((unsigned char)0xEB);
2013 emit_int8((offs - short_size) & 0xFF);
2014 } else {
2015 emit_int8((unsigned char)0xE9);
2016 emit_int32(offs - long_size);
2017 }
2018 } else {
2019 // By default, forward jumps are always 32-bit displacements, since
2020 // we can't yet know where the label will be bound. If you're sure that
2021 // the forward jump will not run beyond 256 bytes, use jmpb to
2022 // force an 8-bit displacement.
2023 InstructionMark im(this);
2024 L.add_patch_at(code(), locator());
2025 emit_int8((unsigned char)0xE9);
2026 emit_int32(0);
2027 }
2028 }
2029
2030 void Assembler::jmp(Register entry) {
2031 int encode = prefix_and_encode(entry->encoding());
2032 emit_int8((unsigned char)0xFF);
2033 emit_int8((unsigned char)(0xE0 | encode));
2034 }
2035
2036 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2037 InstructionMark im(this);
2038 emit_int8((unsigned char)0xE9);
2039 assert(dest != NULL, "must have a target");
2040 intptr_t disp = dest - (pc() + sizeof(int32_t));
2041 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2042 emit_data(disp, rspec.reloc(), call32_operand);
2043 }
2044
2045 void Assembler::jmpb(Label& L) {
2046 if (L.is_bound()) {
2047 const int short_size = 2;
2048 address entry = target(L);
2049 assert(entry != NULL, "jmp most probably wrong");
2050 #ifdef ASSERT
2051 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2052 intptr_t delta = short_branch_delta();
2053 if (delta != 0) {
2054 dist += (dist < 0 ? (-delta) :delta);
2055 }
2056 assert(is8bit(dist), "Dispacement too large for a short jmp");
2057 #endif
2058 intptr_t offs = entry - pc();
2059 emit_int8((unsigned char)0xEB);
2060 emit_int8((offs - short_size) & 0xFF);
2061 } else {
2062 InstructionMark im(this);
2063 L.add_patch_at(code(), locator());
2064 emit_int8((unsigned char)0xEB);
2065 emit_int8(0);
2066 }
2067 }
2068
2069 void Assembler::ldmxcsr( Address src) {
2070 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2071 InstructionMark im(this);
2072 prefix(src);
2073 emit_int8(0x0F);
2074 emit_int8((unsigned char)0xAE);
2075 emit_operand(as_Register(2), src);
2076 }
2077
2078 void Assembler::leal(Register dst, Address src) {
2079 InstructionMark im(this);
2080 #ifdef _LP64
2081 emit_int8(0x67); // addr32
2082 prefix(src, dst);
2083 #endif // LP64
2084 emit_int8((unsigned char)0x8D);
2085 emit_operand(dst, src);
2086 }
2087
2088 void Assembler::lfence() {
2089 emit_int8(0x0F);
2090 emit_int8((unsigned char)0xAE);
2091 emit_int8((unsigned char)0xE8);
2092 }
2093
2094 void Assembler::lock() {
2095 emit_int8((unsigned char)0xF0);
2096 }
2097
2098 void Assembler::lzcntl(Register dst, Register src) {
2099 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2100 emit_int8((unsigned char)0xF3);
2101 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2102 emit_int8(0x0F);
2103 emit_int8((unsigned char)0xBD);
2104 emit_int8((unsigned char)(0xC0 | encode));
2105 }
2106
2107 // Emit mfence instruction
2108 void Assembler::mfence() {
2109 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2110 emit_int8(0x0F);
2111 emit_int8((unsigned char)0xAE);
2112 emit_int8((unsigned char)0xF0);
2113 }
2114
2115 void Assembler::mov(Register dst, Register src) {
2116 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2117 }
2118
2119 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2120 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2121 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2122 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2123 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2124 emit_int8(0x28);
2125 emit_int8((unsigned char)(0xC0 | encode));
2126 }
2127
2128 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2129 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2130 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2131 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2132 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2133 emit_int8(0x28);
2134 emit_int8((unsigned char)(0xC0 | encode));
2135 }
2136
2137 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2138 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2139 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2140 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2141 emit_int8(0x16);
2142 emit_int8((unsigned char)(0xC0 | encode));
2143 }
2144
2145 void Assembler::movb(Register dst, Address src) {
2146 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2147 InstructionMark im(this);
2148 prefix(src, dst, true);
2149 emit_int8((unsigned char)0x8A);
2150 emit_operand(dst, src);
2151 }
2152
2153 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2154 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2155 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
2156 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2157 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2158 emit_int8(0x12);
2159 emit_int8(0xC0 | encode);
2160 }
2161
2162 void Assembler::kmovwl(KRegister dst, Register src) {
2163 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2164 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2165 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2166 emit_int8((unsigned char)0x92);
2167 emit_int8((unsigned char)(0xC0 | encode));
2168 }
2169
2170 void Assembler::kmovdl(KRegister dst, Register src) {
2171 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2172 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2173 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2174 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, VEX_OPCODE_0F, &attributes);
2175 emit_int8((unsigned char)0x92);
2176 emit_int8((unsigned char)(0xC0 | encode));
2177 }
2178
2179 void Assembler::kmovql(KRegister dst, KRegister src) {
2180 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2181 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2182 int encode = kreg_prefix_and_encode(dst, knoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2183 emit_int8((unsigned char)0x90);
2184 emit_int8((unsigned char)(0xC0 | encode));
2185 }
2186
2187 void Assembler::kmovql(KRegister dst, Address src) {
2188 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2189 InstructionMark im(this);
2190 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2191 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2192 emit_int8((unsigned char)0x90);
2193 emit_operand((Register)dst, src);
2194 }
2195
2196 void Assembler::kmovql(Address dst, KRegister src) {
2197 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2198 InstructionMark im(this);
2199 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2200 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2201 emit_int8((unsigned char)0x90);
2202 emit_operand((Register)src, dst);
2203 }
2204
2205 void Assembler::kmovql(KRegister dst, Register src) {
2206 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2207 VexSimdPrefix pre = !_legacy_mode_bw ? VEX_SIMD_F2 : VEX_SIMD_NONE;
2208 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_bw, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2209 int encode = kreg_prefix_and_encode(dst, knoreg, src, pre, VEX_OPCODE_0F, &attributes);
2210 emit_int8((unsigned char)0x92);
2211 emit_int8((unsigned char)(0xC0 | encode));
2212 }
2213
2214 // This instruction produces ZF or CF flags
2215 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2216 NOT_LP64(assert(VM_Version::supports_avx512dq(), ""));
2217 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2218 int encode = kreg_prefix_and_encode(src1, knoreg, src2, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2219 emit_int8((unsigned char)0x98);
2220 emit_int8((unsigned char)(0xC0 | encode));
2221 }
2222
2223 // This instruction produces ZF or CF flags
2224 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2225 NOT_LP64(assert(VM_Version::supports_evex(), ""));
2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2227 int encode = kreg_prefix_and_encode(src1, knoreg, src2, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2228 emit_int8((unsigned char)0x98);
2229 emit_int8((unsigned char)(0xC0 | encode));
2230 }
2231
2232 // This instruction produces ZF or CF flags
2233 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2234 NOT_LP64(assert(VM_Version::supports_avx512bw(), ""));
2235 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2236 int encode = kreg_prefix_and_encode(src1, knoreg, src2, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2237 emit_int8((unsigned char)0x98);
2238 emit_int8((unsigned char)(0xC0 | encode));
2239 }
2240
2241 // This instruction produces ZF or CF flags
2242 void Assembler::kortestql(KRegister src1, KRegister src2) {
2243 NOT_LP64(assert(VM_Version::supports_avx512bw(), ""));
2244 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2245 int encode = kreg_prefix_and_encode(src1, knoreg, src2, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2246 emit_int8((unsigned char)0x98);
2247 emit_int8((unsigned char)(0xC0 | encode));
2248 }
2249
2250 void Assembler::movb(Address dst, int imm8) {
2251 InstructionMark im(this);
2252 prefix(dst);
2253 emit_int8((unsigned char)0xC6);
2254 emit_operand(rax, dst, 1);
2255 emit_int8(imm8);
2256 }
2257
2258
2259 void Assembler::movb(Address dst, Register src) {
2260 assert(src->has_byte_register(), "must have byte register");
2261 InstructionMark im(this);
2262 prefix(dst, src, true);
2263 emit_int8((unsigned char)0x88);
2264 emit_operand(src, dst);
2265 }
2266
2267 void Assembler::movdl(XMMRegister dst, Register src) {
2268 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2270 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2271 emit_int8(0x6E);
2272 emit_int8((unsigned char)(0xC0 | encode));
2273 }
2274
2275 void Assembler::movdl(Register dst, XMMRegister src) {
2276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2277 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2278 // swap src/dst to get correct prefix
2279 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2280 emit_int8(0x7E);
2281 emit_int8((unsigned char)(0xC0 | encode));
2282 }
2283
2284 void Assembler::movdl(XMMRegister dst, Address src) {
2285 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2286 InstructionMark im(this);
2287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2288 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2289 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2290 emit_int8(0x6E);
2291 emit_operand(dst, src);
2292 }
2293
2294 void Assembler::movdl(Address dst, XMMRegister src) {
2295 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2296 InstructionMark im(this);
2297 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2298 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2299 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2300 emit_int8(0x7E);
2301 emit_operand(src, dst);
2302 }
2303
2304 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2305 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2306 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2307 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2308 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2309 emit_int8(0x6F);
2310 emit_int8((unsigned char)(0xC0 | encode));
2311 }
2312
2313 void Assembler::movdqa(XMMRegister dst, Address src) {
2314 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2315 InstructionMark im(this);
2316 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2317 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2318 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2319 emit_int8(0x6F);
2320 emit_operand(dst, src);
2321 }
2322
2323 void Assembler::movdqu(XMMRegister dst, Address src) {
2324 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2325 InstructionMark im(this);
2326 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2327 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2328 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2329 emit_int8(0x6F);
2330 emit_operand(dst, src);
2331 }
2332
2333 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2336 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2337 emit_int8(0x6F);
2338 emit_int8((unsigned char)(0xC0 | encode));
2339 }
2340
2341 void Assembler::movdqu(Address dst, XMMRegister src) {
2342 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2343 InstructionMark im(this);
2344 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2345 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2346 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2347 emit_int8(0x7F);
2348 emit_operand(src, dst);
2349 }
2350
2351 // Move Unaligned 256bit Vector
2352 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2353 assert(UseAVX > 0, "");
2354 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2355 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2356 emit_int8(0x6F);
2357 emit_int8((unsigned char)(0xC0 | encode));
2358 }
2359
2360 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2361 assert(UseAVX > 0, "");
2362 InstructionMark im(this);
2363 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2364 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2365 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2366 emit_int8(0x6F);
2367 emit_operand(dst, src);
2368 }
2369
2370 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2371 assert(UseAVX > 0, "");
2372 InstructionMark im(this);
2373 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2374 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2375 // swap src<->dst for encoding
2376 assert(src != xnoreg, "sanity");
2377 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2378 emit_int8(0x7F);
2379 emit_operand(src, dst);
2380 }
2381
2382 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2383 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2384 assert(VM_Version::supports_evex(), "");
2385 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2386 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2387 emit_int8(0x6F);
2388 emit_int8((unsigned char)(0xC0 | encode));
2389 }
2390
2391 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2392 assert(VM_Version::supports_evex(), "");
2393 InstructionMark im(this);
2394 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2395 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2396 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2397 emit_int8(0x6F);
2398 emit_operand(dst, src);
2399 }
2400
2401 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2402 assert(VM_Version::supports_evex(), "");
2403 assert(src != xnoreg, "sanity");
2404 InstructionMark im(this);
2405 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2406 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2407 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2408 emit_int8(0x7F);
2409 emit_operand(src, dst);
2410 }
2411
2412 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2413 assert(VM_Version::supports_evex(), "");
2414 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2415 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2416 emit_int8(0x6F);
2417 emit_int8((unsigned char)(0xC0 | encode));
2418 }
2419
2420 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2421 assert(VM_Version::supports_evex(), "");
2422 InstructionMark im(this);
2423 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2424 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2425 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2426 emit_int8(0x6F);
2427 emit_operand(dst, src);
2428 }
2429
2430 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2431 assert(VM_Version::supports_evex(), "");
2432 assert(src != xnoreg, "sanity");
2433 InstructionMark im(this);
2434 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2435 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2436 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2437 emit_int8(0x7F);
2438 emit_operand(src, dst);
2439 }
2440 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2441 assert(VM_Version::supports_evex(), "");
2442 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2443 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2444 emit_int8(0x6F);
2445 emit_int8((unsigned char)(0xC0 | encode));
2446 }
2447
2448 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2449 assert(VM_Version::supports_evex(), "");
2450 InstructionMark im(this);
2451 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2452 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2453 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2454 emit_int8(0x6F);
2455 emit_operand(dst, src);
2456 }
2457
2458 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2459 assert(VM_Version::supports_evex(), "");
2460 assert(src != xnoreg, "sanity");
2461 InstructionMark im(this);
2462 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2463 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2464 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2465 emit_int8(0x7F);
2466 emit_operand(src, dst);
2467 }
2468
2469 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2470 assert(VM_Version::supports_evex(), "");
2471 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2472 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2473 emit_int8(0x6F);
2474 emit_int8((unsigned char)(0xC0 | encode));
2475 }
2476
2477 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2478 assert(VM_Version::supports_evex(), "");
2479 InstructionMark im(this);
2480 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2481 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2482 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2483 emit_int8(0x6F);
2484 emit_operand(dst, src);
2485 }
2486
2487 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2488 assert(VM_Version::supports_evex(), "");
2489 assert(src != xnoreg, "sanity");
2490 InstructionMark im(this);
2491 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2492 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2493 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2494 emit_int8(0x7F);
2495 emit_operand(src, dst);
2496 }
2497
2498 // Uses zero extension on 64bit
2499
2500 void Assembler::movl(Register dst, int32_t imm32) {
2501 int encode = prefix_and_encode(dst->encoding());
2502 emit_int8((unsigned char)(0xB8 | encode));
2503 emit_int32(imm32);
2504 }
2505
2506 void Assembler::movl(Register dst, Register src) {
2507 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2508 emit_int8((unsigned char)0x8B);
2509 emit_int8((unsigned char)(0xC0 | encode));
2510 }
2511
2512 void Assembler::movl(Register dst, Address src) {
2513 InstructionMark im(this);
2514 prefix(src, dst);
2515 emit_int8((unsigned char)0x8B);
2516 emit_operand(dst, src);
2517 }
2518
2519 void Assembler::movl(Address dst, int32_t imm32) {
2520 InstructionMark im(this);
2521 prefix(dst);
2522 emit_int8((unsigned char)0xC7);
2523 emit_operand(rax, dst, 4);
2524 emit_int32(imm32);
2525 }
2526
2527 void Assembler::movl(Address dst, Register src) {
2528 InstructionMark im(this);
2529 prefix(dst, src);
2530 emit_int8((unsigned char)0x89);
2531 emit_operand(src, dst);
2532 }
2533
2534 // New cpus require to use movsd and movss to avoid partial register stall
2535 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2536 // The selection is done in MacroAssembler::movdbl() and movflt().
2537 void Assembler::movlpd(XMMRegister dst, Address src) {
2538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2539 InstructionMark im(this);
2540 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2541 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2542 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2543 emit_int8(0x12);
2544 emit_operand(dst, src);
2545 }
2546
2547 void Assembler::movq( MMXRegister dst, Address src ) {
2548 assert( VM_Version::supports_mmx(), "" );
2549 emit_int8(0x0F);
2550 emit_int8(0x6F);
2551 emit_operand(dst, src);
2552 }
2553
2554 void Assembler::movq( Address dst, MMXRegister src ) {
2555 assert( VM_Version::supports_mmx(), "" );
2556 emit_int8(0x0F);
2557 emit_int8(0x7F);
2558 // workaround gcc (3.2.1-7a) bug
2559 // In that version of gcc with only an emit_operand(MMX, Address)
2560 // gcc will tail jump and try and reverse the parameters completely
2561 // obliterating dst in the process. By having a version available
2562 // that doesn't need to swap the args at the tail jump the bug is
2563 // avoided.
2564 emit_operand(dst, src);
2565 }
2566
2567 void Assembler::movq(XMMRegister dst, Address src) {
2568 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2569 InstructionMark im(this);
2570 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2571 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2572 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2573 emit_int8(0x7E);
2574 emit_operand(dst, src);
2575 }
2576
2577 void Assembler::movq(Address dst, XMMRegister src) {
2578 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2579 InstructionMark im(this);
2580 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2581 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2582 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2583 emit_int8((unsigned char)0xD6);
2584 emit_operand(src, dst);
2585 }
2586
2587 void Assembler::movsbl(Register dst, Address src) { // movsxb
2588 InstructionMark im(this);
2589 prefix(src, dst);
2590 emit_int8(0x0F);
2591 emit_int8((unsigned char)0xBE);
2592 emit_operand(dst, src);
2593 }
2594
2595 void Assembler::movsbl(Register dst, Register src) { // movsxb
2596 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2597 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2598 emit_int8(0x0F);
2599 emit_int8((unsigned char)0xBE);
2600 emit_int8((unsigned char)(0xC0 | encode));
2601 }
2602
2603 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2604 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2605 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2606 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2607 emit_int8(0x10);
2608 emit_int8((unsigned char)(0xC0 | encode));
2609 }
2610
2611 void Assembler::movsd(XMMRegister dst, Address src) {
2612 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2613 InstructionMark im(this);
2614 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2615 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2616 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2617 emit_int8(0x10);
2618 emit_operand(dst, src);
2619 }
2620
2621 void Assembler::movsd(Address dst, XMMRegister src) {
2622 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2623 InstructionMark im(this);
2624 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2625 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2626 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2627 emit_int8(0x11);
2628 emit_operand(src, dst);
2629 }
2630
2631 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2632 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2633 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2634 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2635 emit_int8(0x10);
2636 emit_int8((unsigned char)(0xC0 | encode));
2637 }
2638
2639 void Assembler::movss(XMMRegister dst, Address src) {
2640 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2641 InstructionMark im(this);
2642 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2643 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2644 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2645 emit_int8(0x10);
2646 emit_operand(dst, src);
2647 }
2648
2649 void Assembler::movss(Address dst, XMMRegister src) {
2650 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2651 InstructionMark im(this);
2652 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2653 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2654 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2655 emit_int8(0x11);
2656 emit_operand(src, dst);
2657 }
2658
2659 void Assembler::movswl(Register dst, Address src) { // movsxw
2660 InstructionMark im(this);
2661 prefix(src, dst);
2662 emit_int8(0x0F);
2663 emit_int8((unsigned char)0xBF);
2664 emit_operand(dst, src);
2665 }
2666
2667 void Assembler::movswl(Register dst, Register src) { // movsxw
2668 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2669 emit_int8(0x0F);
2670 emit_int8((unsigned char)0xBF);
2671 emit_int8((unsigned char)(0xC0 | encode));
2672 }
2673
2674 void Assembler::movw(Address dst, int imm16) {
2675 InstructionMark im(this);
2676
2677 emit_int8(0x66); // switch to 16-bit mode
2678 prefix(dst);
2679 emit_int8((unsigned char)0xC7);
2680 emit_operand(rax, dst, 2);
2681 emit_int16(imm16);
2682 }
2683
2684 void Assembler::movw(Register dst, Address src) {
2685 InstructionMark im(this);
2686 emit_int8(0x66);
2687 prefix(src, dst);
2688 emit_int8((unsigned char)0x8B);
2689 emit_operand(dst, src);
2690 }
2691
2692 void Assembler::movw(Address dst, Register src) {
2693 InstructionMark im(this);
2694 emit_int8(0x66);
2695 prefix(dst, src);
2696 emit_int8((unsigned char)0x89);
2697 emit_operand(src, dst);
2698 }
2699
2700 void Assembler::movzbl(Register dst, Address src) { // movzxb
2701 InstructionMark im(this);
2702 prefix(src, dst);
2703 emit_int8(0x0F);
2704 emit_int8((unsigned char)0xB6);
2705 emit_operand(dst, src);
2706 }
2707
2708 void Assembler::movzbl(Register dst, Register src) { // movzxb
2709 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2710 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2711 emit_int8(0x0F);
2712 emit_int8((unsigned char)0xB6);
2713 emit_int8(0xC0 | encode);
2714 }
2715
2716 void Assembler::movzwl(Register dst, Address src) { // movzxw
2717 InstructionMark im(this);
2718 prefix(src, dst);
2719 emit_int8(0x0F);
2720 emit_int8((unsigned char)0xB7);
2721 emit_operand(dst, src);
2722 }
2723
2724 void Assembler::movzwl(Register dst, Register src) { // movzxw
2725 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2726 emit_int8(0x0F);
2727 emit_int8((unsigned char)0xB7);
2728 emit_int8(0xC0 | encode);
2729 }
2730
2731 void Assembler::mull(Address src) {
2732 InstructionMark im(this);
2733 prefix(src);
2734 emit_int8((unsigned char)0xF7);
2735 emit_operand(rsp, src);
2736 }
2737
2738 void Assembler::mull(Register src) {
2739 int encode = prefix_and_encode(src->encoding());
2740 emit_int8((unsigned char)0xF7);
2741 emit_int8((unsigned char)(0xE0 | encode));
2742 }
2743
2744 void Assembler::mulsd(XMMRegister dst, Address src) {
2745 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2746 InstructionMark im(this);
2747 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2748 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2749 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2750 emit_int8(0x59);
2751 emit_operand(dst, src);
2752 }
2753
2754 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2755 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2756 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2757 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2758 emit_int8(0x59);
2759 emit_int8((unsigned char)(0xC0 | encode));
2760 }
2761
2762 void Assembler::mulss(XMMRegister dst, Address src) {
2763 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2764 InstructionMark im(this);
2765 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2766 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2767 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2768 emit_int8(0x59);
2769 emit_operand(dst, src);
2770 }
2771
2772 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2773 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2774 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2775 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2776 emit_int8(0x59);
2777 emit_int8((unsigned char)(0xC0 | encode));
2778 }
2779
2780 void Assembler::negl(Register dst) {
2781 int encode = prefix_and_encode(dst->encoding());
2782 emit_int8((unsigned char)0xF7);
2783 emit_int8((unsigned char)(0xD8 | encode));
2784 }
2785
2786 void Assembler::nop(int i) {
2787 #ifdef ASSERT
2788 assert(i > 0, " ");
2789 // The fancy nops aren't currently recognized by debuggers making it a
2790 // pain to disassemble code while debugging. If asserts are on clearly
2791 // speed is not an issue so simply use the single byte traditional nop
2792 // to do alignment.
2793
2794 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2795 return;
2796
2797 #endif // ASSERT
2798
2799 if (UseAddressNop && VM_Version::is_intel()) {
2800 //
2801 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2802 // 1: 0x90
2803 // 2: 0x66 0x90
2804 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2805 // 4: 0x0F 0x1F 0x40 0x00
2806 // 5: 0x0F 0x1F 0x44 0x00 0x00
2807 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2808 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2809 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2810 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2811 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2812 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2813
2814 // The rest coding is Intel specific - don't use consecutive address nops
2815
2816 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2817 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2818 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2819 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2820
2821 while(i >= 15) {
2822 // For Intel don't generate consecutive addess nops (mix with regular nops)
2823 i -= 15;
2824 emit_int8(0x66); // size prefix
2825 emit_int8(0x66); // size prefix
2826 emit_int8(0x66); // size prefix
2827 addr_nop_8();
2828 emit_int8(0x66); // size prefix
2829 emit_int8(0x66); // size prefix
2830 emit_int8(0x66); // size prefix
2831 emit_int8((unsigned char)0x90);
2832 // nop
2833 }
2834 switch (i) {
2835 case 14:
2836 emit_int8(0x66); // size prefix
2837 case 13:
2838 emit_int8(0x66); // size prefix
2839 case 12:
2840 addr_nop_8();
2841 emit_int8(0x66); // size prefix
2842 emit_int8(0x66); // size prefix
2843 emit_int8(0x66); // size prefix
2844 emit_int8((unsigned char)0x90);
2845 // nop
2846 break;
2847 case 11:
2848 emit_int8(0x66); // size prefix
2849 case 10:
2850 emit_int8(0x66); // size prefix
2851 case 9:
2852 emit_int8(0x66); // size prefix
2853 case 8:
2854 addr_nop_8();
2855 break;
2856 case 7:
2857 addr_nop_7();
2858 break;
2859 case 6:
2860 emit_int8(0x66); // size prefix
2861 case 5:
2862 addr_nop_5();
2863 break;
2864 case 4:
2865 addr_nop_4();
2866 break;
2867 case 3:
2868 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2869 emit_int8(0x66); // size prefix
2870 case 2:
2871 emit_int8(0x66); // size prefix
2872 case 1:
2873 emit_int8((unsigned char)0x90);
2874 // nop
2875 break;
2876 default:
2877 assert(i == 0, " ");
2878 }
2879 return;
2880 }
2881 if (UseAddressNop && VM_Version::is_amd()) {
2882 //
2883 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2884 // 1: 0x90
2885 // 2: 0x66 0x90
2886 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2887 // 4: 0x0F 0x1F 0x40 0x00
2888 // 5: 0x0F 0x1F 0x44 0x00 0x00
2889 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2890 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2891 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2892 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2893 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2894 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2895
2896 // The rest coding is AMD specific - use consecutive address nops
2897
2898 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2899 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2900 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2901 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2902 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2903 // Size prefixes (0x66) are added for larger sizes
2904
2905 while(i >= 22) {
2906 i -= 11;
2907 emit_int8(0x66); // size prefix
2908 emit_int8(0x66); // size prefix
2909 emit_int8(0x66); // size prefix
2910 addr_nop_8();
2911 }
2912 // Generate first nop for size between 21-12
2913 switch (i) {
2914 case 21:
2915 i -= 1;
2916 emit_int8(0x66); // size prefix
2917 case 20:
2918 case 19:
2919 i -= 1;
2920 emit_int8(0x66); // size prefix
2921 case 18:
2922 case 17:
2923 i -= 1;
2924 emit_int8(0x66); // size prefix
2925 case 16:
2926 case 15:
2927 i -= 8;
2928 addr_nop_8();
2929 break;
2930 case 14:
2931 case 13:
2932 i -= 7;
2933 addr_nop_7();
2934 break;
2935 case 12:
2936 i -= 6;
2937 emit_int8(0x66); // size prefix
2938 addr_nop_5();
2939 break;
2940 default:
2941 assert(i < 12, " ");
2942 }
2943
2944 // Generate second nop for size between 11-1
2945 switch (i) {
2946 case 11:
2947 emit_int8(0x66); // size prefix
2948 case 10:
2949 emit_int8(0x66); // size prefix
2950 case 9:
2951 emit_int8(0x66); // size prefix
2952 case 8:
2953 addr_nop_8();
2954 break;
2955 case 7:
2956 addr_nop_7();
2957 break;
2958 case 6:
2959 emit_int8(0x66); // size prefix
2960 case 5:
2961 addr_nop_5();
2962 break;
2963 case 4:
2964 addr_nop_4();
2965 break;
2966 case 3:
2967 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2968 emit_int8(0x66); // size prefix
2969 case 2:
2970 emit_int8(0x66); // size prefix
2971 case 1:
2972 emit_int8((unsigned char)0x90);
2973 // nop
2974 break;
2975 default:
2976 assert(i == 0, " ");
2977 }
2978 return;
2979 }
2980
2981 // Using nops with size prefixes "0x66 0x90".
2982 // From AMD Optimization Guide:
2983 // 1: 0x90
2984 // 2: 0x66 0x90
2985 // 3: 0x66 0x66 0x90
2986 // 4: 0x66 0x66 0x66 0x90
2987 // 5: 0x66 0x66 0x90 0x66 0x90
2988 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
2989 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
2990 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
2991 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2992 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
2993 //
2994 while(i > 12) {
2995 i -= 4;
2996 emit_int8(0x66); // size prefix
2997 emit_int8(0x66);
2998 emit_int8(0x66);
2999 emit_int8((unsigned char)0x90);
3000 // nop
3001 }
3002 // 1 - 12 nops
3003 if(i > 8) {
3004 if(i > 9) {
3005 i -= 1;
3006 emit_int8(0x66);
3007 }
3008 i -= 3;
3009 emit_int8(0x66);
3010 emit_int8(0x66);
3011 emit_int8((unsigned char)0x90);
3012 }
3013 // 1 - 8 nops
3014 if(i > 4) {
3015 if(i > 6) {
3016 i -= 1;
3017 emit_int8(0x66);
3018 }
3019 i -= 3;
3020 emit_int8(0x66);
3021 emit_int8(0x66);
3022 emit_int8((unsigned char)0x90);
3023 }
3024 switch (i) {
3025 case 4:
3026 emit_int8(0x66);
3027 case 3:
3028 emit_int8(0x66);
3029 case 2:
3030 emit_int8(0x66);
3031 case 1:
3032 emit_int8((unsigned char)0x90);
3033 break;
3034 default:
3035 assert(i == 0, " ");
3036 }
3037 }
3038
3039 void Assembler::notl(Register dst) {
3040 int encode = prefix_and_encode(dst->encoding());
3041 emit_int8((unsigned char)0xF7);
3042 emit_int8((unsigned char)(0xD0 | encode));
3043 }
3044
3045 void Assembler::orl(Address dst, int32_t imm32) {
3046 InstructionMark im(this);
3047 prefix(dst);
3048 emit_arith_operand(0x81, rcx, dst, imm32);
3049 }
3050
3051 void Assembler::orl(Register dst, int32_t imm32) {
3052 prefix(dst);
3053 emit_arith(0x81, 0xC8, dst, imm32);
3054 }
3055
3056 void Assembler::orl(Register dst, Address src) {
3057 InstructionMark im(this);
3058 prefix(src, dst);
3059 emit_int8(0x0B);
3060 emit_operand(dst, src);
3061 }
3062
3063 void Assembler::orl(Register dst, Register src) {
3064 (void) prefix_and_encode(dst->encoding(), src->encoding());
3065 emit_arith(0x0B, 0xC0, dst, src);
3066 }
3067
3068 void Assembler::orl(Address dst, Register src) {
3069 InstructionMark im(this);
3070 prefix(dst, src);
3071 emit_int8(0x09);
3072 emit_operand(src, dst);
3073 }
3074
3075 void Assembler::packuswb(XMMRegister dst, Address src) {
3076 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3077 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3078 InstructionMark im(this);
3079 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3080 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3081 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3082 emit_int8(0x67);
3083 emit_operand(dst, src);
3084 }
3085
3086 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3089 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3090 emit_int8(0x67);
3091 emit_int8((unsigned char)(0xC0 | encode));
3092 }
3093
3094 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3095 assert(UseAVX > 0, "some form of AVX must be enabled");
3096 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3097 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3098 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3099 emit_int8(0x67);
3100 emit_int8((unsigned char)(0xC0 | encode));
3101 }
3102
3103 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3104 assert(VM_Version::supports_avx2(), "");
3105 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3106 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3107 emit_int8(0x00);
3108 emit_int8(0xC0 | encode);
3109 emit_int8(imm8);
3110 }
3111
3112 void Assembler::pause() {
3113 emit_int8((unsigned char)0xF3);
3114 emit_int8((unsigned char)0x90);
3115 }
3116
3117 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3118 assert(VM_Version::supports_sse4_2(), "");
3119 InstructionMark im(this);
3120 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3121 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3122 emit_int8(0x61);
3123 emit_operand(dst, src);
3124 emit_int8(imm8);
3125 }
3126
3127 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3128 assert(VM_Version::supports_sse4_2(), "");
3129 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3130 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3131 emit_int8(0x61);
3132 emit_int8((unsigned char)(0xC0 | encode));
3133 emit_int8(imm8);
3134 }
3135
3136 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3137 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3138 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3139 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3140 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3141 emit_int8(0x74);
3142 emit_int8((unsigned char)(0xC0 | encode));
3143 }
3144
3145 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3146 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3147 assert(VM_Version::supports_avx(), "");
3148 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3149 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3150 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3151 emit_int8(0x74);
3152 emit_int8((unsigned char)(0xC0 | encode));
3153 }
3154
3155 // In this context, kdst is written the mask used to process the equal components
3156 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3157 assert(VM_Version::supports_avx512bw(), "");
3158 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3159 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3160 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3161 emit_int8(0x74);
3162 emit_int8((unsigned char)(0xC0 | encode));
3163 }
3164
3165 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3166 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3167 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3168 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3169 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3170 emit_int8(0x75);
3171 emit_int8((unsigned char)(0xC0 | encode));
3172 }
3173
3174 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3175 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3176 assert(VM_Version::supports_avx(), "");
3177 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3178 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3179 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3180 emit_int8(0x75);
3181 emit_int8((unsigned char)(0xC0 | encode));
3182 }
3183
3184 // In this context, kdst is written the mask used to process the equal components
3185 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3186 assert(VM_Version::supports_avx512bw(), "");
3187 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3188 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3189 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3190 emit_int8(0x75);
3191 emit_int8((unsigned char)(0xC0 | encode));
3192 }
3193
3194 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3195 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3196 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3197 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3198 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3199 emit_int8(0x76);
3200 emit_int8((unsigned char)(0xC0 | encode));
3201 }
3202
3203 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3204 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3205 assert(VM_Version::supports_avx(), "");
3206 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3207 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3208 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3209 emit_int8(0x76);
3210 emit_int8((unsigned char)(0xC0 | encode));
3211 }
3212
3213 // In this context, kdst is written the mask used to process the equal components
3214 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3215 assert(VM_Version::supports_evex(), "");
3216 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3217 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3218 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3219 emit_int8(0x76);
3220 emit_int8((unsigned char)(0xC0 | encode));
3221 }
3222
3223 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3224 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3225 NOT_LP64(assert(VM_Version::supports_sse4_1(), ""));
3226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3227 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3228 emit_int8(0x29);
3229 emit_int8((unsigned char)(0xC0 | encode));
3230 }
3231
3232 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3233 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3234 assert(VM_Version::supports_avx(), "");
3235 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3236 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3237 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3238 emit_int8(0x29);
3239 emit_int8((unsigned char)(0xC0 | encode));
3240 }
3241
3242 // In this context, kdst is written the mask used to process the equal components
3243 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3244 assert(VM_Version::supports_evex(), "");
3245 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3246 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3247 int encode = vex_prefix_and_encode(kdst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3248 emit_int8(0x29);
3249 emit_int8((unsigned char)(0xC0 | encode));
3250 }
3251
3252 // In this context, kdst is written the mask used to process the equal components
3253 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3254 assert(VM_Version::supports_evex(), "");
3255 InstructionMark im(this);
3256 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3257 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3258 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
3259 int dst_enc = kdst->encoding();
3260 vex_prefix(src, nds_enc, dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3261 emit_int8(0x29);
3262 emit_operand(as_Register(dst_enc), src);
3263 }
3264
3265 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3266 assert(VM_Version::supports_sse2(), "");
3267 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3268 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3269 emit_int8((unsigned char)0xD7);
3270 emit_int8((unsigned char)(0xC0 | encode));
3271 }
3272
3273 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3274 assert(VM_Version::supports_avx2(), "");
3275 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3276 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3277 emit_int8((unsigned char)0xD7);
3278 emit_int8((unsigned char)(0xC0 | encode));
3279 }
3280
3281 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3282 assert(VM_Version::supports_sse4_1(), "");
3283 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3284 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3285 emit_int8(0x16);
3286 emit_int8((unsigned char)(0xC0 | encode));
3287 emit_int8(imm8);
3288 }
3289
3290 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3291 assert(VM_Version::supports_sse4_1(), "");
3292 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3293 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3294 emit_int8(0x16);
3295 emit_int8((unsigned char)(0xC0 | encode));
3296 emit_int8(imm8);
3297 }
3298
3299 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3300 assert(VM_Version::supports_sse2(), "");
3301 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3302 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3303 emit_int8((unsigned char)0xC5);
3304 emit_int8((unsigned char)(0xC0 | encode));
3305 emit_int8(imm8);
3306 }
3307
3308 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3309 assert(VM_Version::supports_sse4_1(), "");
3310 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3311 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3312 emit_int8(0x22);
3313 emit_int8((unsigned char)(0xC0 | encode));
3314 emit_int8(imm8);
3315 }
3316
3317 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3318 assert(VM_Version::supports_sse4_1(), "");
3319 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3320 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3321 emit_int8(0x22);
3322 emit_int8((unsigned char)(0xC0 | encode));
3323 emit_int8(imm8);
3324 }
3325
3326 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3327 assert(VM_Version::supports_sse2(), "");
3328 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3329 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3330 emit_int8((unsigned char)0xC4);
3331 emit_int8((unsigned char)(0xC0 | encode));
3332 emit_int8(imm8);
3333 }
3334
3335 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3336 assert(VM_Version::supports_sse4_1(), "");
3337 InstructionMark im(this);
3338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3339 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3340 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3341 emit_int8(0x30);
3342 emit_operand(dst, src);
3343 }
3344
3345 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3346 assert(VM_Version::supports_sse4_1(), "");
3347 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3348 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3349 emit_int8(0x30);
3350 emit_int8((unsigned char)(0xC0 | encode));
3351 }
3352
3353 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3354 assert(VM_Version::supports_avx(), "");
3355 InstructionMark im(this);
3356 assert(dst != xnoreg, "sanity");
3357 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3358 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3359 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3360 emit_int8(0x30);
3361 emit_operand(dst, src);
3362 }
3363
3364 // generic
3365 void Assembler::pop(Register dst) {
3366 int encode = prefix_and_encode(dst->encoding());
3367 emit_int8(0x58 | encode);
3368 }
3369
3370 void Assembler::popcntl(Register dst, Address src) {
3371 assert(VM_Version::supports_popcnt(), "must support");
3372 InstructionMark im(this);
3373 emit_int8((unsigned char)0xF3);
3374 prefix(src, dst);
3375 emit_int8(0x0F);
3376 emit_int8((unsigned char)0xB8);
3377 emit_operand(dst, src);
3378 }
3379
3380 void Assembler::popcntl(Register dst, Register src) {
3381 assert(VM_Version::supports_popcnt(), "must support");
3382 emit_int8((unsigned char)0xF3);
3383 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3384 emit_int8(0x0F);
3385 emit_int8((unsigned char)0xB8);
3386 emit_int8((unsigned char)(0xC0 | encode));
3387 }
3388
3389 void Assembler::popf() {
3390 emit_int8((unsigned char)0x9D);
3391 }
3392
3393 #ifndef _LP64 // no 32bit push/pop on amd64
3394 void Assembler::popl(Address dst) {
3395 // NOTE: this will adjust stack by 8byte on 64bits
3396 InstructionMark im(this);
3397 prefix(dst);
3398 emit_int8((unsigned char)0x8F);
3399 emit_operand(rax, dst);
3400 }
3401 #endif
3402
3403 void Assembler::prefetch_prefix(Address src) {
3404 prefix(src);
3405 emit_int8(0x0F);
3406 }
3407
3408 void Assembler::prefetchnta(Address src) {
3409 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3410 InstructionMark im(this);
3411 prefetch_prefix(src);
3412 emit_int8(0x18);
3413 emit_operand(rax, src); // 0, src
3414 }
3415
3416 void Assembler::prefetchr(Address src) {
3417 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3418 InstructionMark im(this);
3419 prefetch_prefix(src);
3420 emit_int8(0x0D);
3421 emit_operand(rax, src); // 0, src
3422 }
3423
3424 void Assembler::prefetcht0(Address src) {
3425 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3426 InstructionMark im(this);
3427 prefetch_prefix(src);
3428 emit_int8(0x18);
3429 emit_operand(rcx, src); // 1, src
3430 }
3431
3432 void Assembler::prefetcht1(Address src) {
3433 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3434 InstructionMark im(this);
3435 prefetch_prefix(src);
3436 emit_int8(0x18);
3437 emit_operand(rdx, src); // 2, src
3438 }
3439
3440 void Assembler::prefetcht2(Address src) {
3441 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3442 InstructionMark im(this);
3443 prefetch_prefix(src);
3444 emit_int8(0x18);
3445 emit_operand(rbx, src); // 3, src
3446 }
3447
3448 void Assembler::prefetchw(Address src) {
3449 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3450 InstructionMark im(this);
3451 prefetch_prefix(src);
3452 emit_int8(0x0D);
3453 emit_operand(rcx, src); // 1, src
3454 }
3455
3456 void Assembler::prefix(Prefix p) {
3457 emit_int8(p);
3458 }
3459
3460 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3461 assert(VM_Version::supports_ssse3(), "");
3462 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3463 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3464 emit_int8(0x00);
3465 emit_int8((unsigned char)(0xC0 | encode));
3466 }
3467
3468 void Assembler::pshufb(XMMRegister dst, Address src) {
3469 assert(VM_Version::supports_ssse3(), "");
3470 InstructionMark im(this);
3471 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3472 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3473 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3474 emit_int8(0x00);
3475 emit_operand(dst, src);
3476 }
3477
3478 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3479 assert(isByte(mode), "invalid value");
3480 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3481 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_128bit;
3482 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3483 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3484 emit_int8(0x70);
3485 emit_int8((unsigned char)(0xC0 | encode));
3486 emit_int8(mode & 0xFF);
3487 }
3488
3489 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3490 assert(isByte(mode), "invalid value");
3491 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3492 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3493 InstructionMark im(this);
3494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3495 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3496 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3497 emit_int8(0x70);
3498 emit_operand(dst, src);
3499 emit_int8(mode & 0xFF);
3500 }
3501
3502 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3503 assert(isByte(mode), "invalid value");
3504 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3505 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3506 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3507 emit_int8(0x70);
3508 emit_int8((unsigned char)(0xC0 | encode));
3509 emit_int8(mode & 0xFF);
3510 }
3511
3512 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3513 assert(isByte(mode), "invalid value");
3514 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3515 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3516 InstructionMark im(this);
3517 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3518 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3519 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3520 emit_int8(0x70);
3521 emit_operand(dst, src);
3522 emit_int8(mode & 0xFF);
3523 }
3524
3525 void Assembler::psrldq(XMMRegister dst, int shift) {
3526 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3528 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3529 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3530 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3531 emit_int8(0x73);
3532 emit_int8((unsigned char)(0xC0 | encode));
3533 emit_int8(shift);
3534 }
3535
3536 void Assembler::pslldq(XMMRegister dst, int shift) {
3537 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3540 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3541 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3542 emit_int8(0x73);
3543 emit_int8((unsigned char)(0xC0 | encode));
3544 emit_int8(shift);
3545 }
3546
3547 void Assembler::ptest(XMMRegister dst, Address src) {
3548 assert(VM_Version::supports_sse4_1(), "");
3549 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3550 InstructionMark im(this);
3551 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3552 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3553 emit_int8(0x17);
3554 emit_operand(dst, src);
3555 }
3556
3557 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3558 assert(VM_Version::supports_sse4_1(), "");
3559 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3560 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3561 emit_int8(0x17);
3562 emit_int8((unsigned char)(0xC0 | encode));
3563 }
3564
3565 void Assembler::vptest(XMMRegister dst, Address src) {
3566 assert(VM_Version::supports_avx(), "");
3567 InstructionMark im(this);
3568 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3569 assert(dst != xnoreg, "sanity");
3570 // swap src<->dst for encoding
3571 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3572 emit_int8(0x17);
3573 emit_operand(dst, src);
3574 }
3575
3576 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3577 assert(VM_Version::supports_avx(), "");
3578 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3579 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3580 emit_int8(0x17);
3581 emit_int8((unsigned char)(0xC0 | encode));
3582 }
3583
3584 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3585 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3586 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3587 InstructionMark im(this);
3588 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3589 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3590 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3591 emit_int8(0x60);
3592 emit_operand(dst, src);
3593 }
3594
3595 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3596 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3597 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3598 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3599 emit_int8(0x60);
3600 emit_int8((unsigned char)(0xC0 | encode));
3601 }
3602
3603 void Assembler::punpckldq(XMMRegister dst, Address src) {
3604 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3605 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3606 InstructionMark im(this);
3607 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3608 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3609 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3610 emit_int8(0x62);
3611 emit_operand(dst, src);
3612 }
3613
3614 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3615 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3616 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3617 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3618 emit_int8(0x62);
3619 emit_int8((unsigned char)(0xC0 | encode));
3620 }
3621
3622 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3623 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3624 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3625 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3626 emit_int8(0x6C);
3627 emit_int8((unsigned char)(0xC0 | encode));
3628 }
3629
3630 void Assembler::push(int32_t imm32) {
3631 // in 64bits we push 64bits onto the stack but only
3632 // take a 32bit immediate
3633 emit_int8(0x68);
3634 emit_int32(imm32);
3635 }
3636
3637 void Assembler::push(Register src) {
3638 int encode = prefix_and_encode(src->encoding());
3639
3640 emit_int8(0x50 | encode);
3641 }
3642
3643 void Assembler::pushf() {
3644 emit_int8((unsigned char)0x9C);
3645 }
3646
3647 #ifndef _LP64 // no 32bit push/pop on amd64
3648 void Assembler::pushl(Address src) {
3649 // Note this will push 64bit on 64bit
3650 InstructionMark im(this);
3651 prefix(src);
3652 emit_int8((unsigned char)0xFF);
3653 emit_operand(rsi, src);
3654 }
3655 #endif
3656
3657 void Assembler::rcll(Register dst, int imm8) {
3658 assert(isShiftCount(imm8), "illegal shift count");
3659 int encode = prefix_and_encode(dst->encoding());
3660 if (imm8 == 1) {
3661 emit_int8((unsigned char)0xD1);
3662 emit_int8((unsigned char)(0xD0 | encode));
3663 } else {
3664 emit_int8((unsigned char)0xC1);
3665 emit_int8((unsigned char)0xD0 | encode);
3666 emit_int8(imm8);
3667 }
3668 }
3669
3670 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3671 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3672 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3673 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3674 emit_int8(0x53);
3675 emit_int8((unsigned char)(0xC0 | encode));
3676 }
3677
3678 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3679 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3680 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3681 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3682 emit_int8(0x53);
3683 emit_int8((unsigned char)(0xC0 | encode));
3684 }
3685
3686 void Assembler::rdtsc() {
3687 emit_int8((unsigned char)0x0F);
3688 emit_int8((unsigned char)0x31);
3689 }
3690
3691 // copies data from [esi] to [edi] using rcx pointer sized words
3692 // generic
3693 void Assembler::rep_mov() {
3694 emit_int8((unsigned char)0xF3);
3695 // MOVSQ
3696 LP64_ONLY(prefix(REX_W));
3697 emit_int8((unsigned char)0xA5);
3698 }
3699
3700 // sets rcx bytes with rax, value at [edi]
3701 void Assembler::rep_stosb() {
3702 emit_int8((unsigned char)0xF3); // REP
3703 LP64_ONLY(prefix(REX_W));
3704 emit_int8((unsigned char)0xAA); // STOSB
3705 }
3706
3707 // sets rcx pointer sized words with rax, value at [edi]
3708 // generic
3709 void Assembler::rep_stos() {
3710 emit_int8((unsigned char)0xF3); // REP
3711 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3712 emit_int8((unsigned char)0xAB);
3713 }
3714
3715 // scans rcx pointer sized words at [edi] for occurance of rax,
3716 // generic
3717 void Assembler::repne_scan() { // repne_scan
3718 emit_int8((unsigned char)0xF2);
3719 // SCASQ
3720 LP64_ONLY(prefix(REX_W));
3721 emit_int8((unsigned char)0xAF);
3722 }
3723
3724 #ifdef _LP64
3725 // scans rcx 4 byte words at [edi] for occurance of rax,
3726 // generic
3727 void Assembler::repne_scanl() { // repne_scan
3728 emit_int8((unsigned char)0xF2);
3729 // SCASL
3730 emit_int8((unsigned char)0xAF);
3731 }
3732 #endif
3733
3734 void Assembler::ret(int imm16) {
3735 if (imm16 == 0) {
3736 emit_int8((unsigned char)0xC3);
3737 } else {
3738 emit_int8((unsigned char)0xC2);
3739 emit_int16(imm16);
3740 }
3741 }
3742
3743 void Assembler::sahf() {
3744 #ifdef _LP64
3745 // Not supported in 64bit mode
3746 ShouldNotReachHere();
3747 #endif
3748 emit_int8((unsigned char)0x9E);
3749 }
3750
3751 void Assembler::sarl(Register dst, int imm8) {
3752 int encode = prefix_and_encode(dst->encoding());
3753 assert(isShiftCount(imm8), "illegal shift count");
3754 if (imm8 == 1) {
3755 emit_int8((unsigned char)0xD1);
3756 emit_int8((unsigned char)(0xF8 | encode));
3757 } else {
3758 emit_int8((unsigned char)0xC1);
3759 emit_int8((unsigned char)(0xF8 | encode));
3760 emit_int8(imm8);
3761 }
3762 }
3763
3764 void Assembler::sarl(Register dst) {
3765 int encode = prefix_and_encode(dst->encoding());
3766 emit_int8((unsigned char)0xD3);
3767 emit_int8((unsigned char)(0xF8 | encode));
3768 }
3769
3770 void Assembler::sbbl(Address dst, int32_t imm32) {
3771 InstructionMark im(this);
3772 prefix(dst);
3773 emit_arith_operand(0x81, rbx, dst, imm32);
3774 }
3775
3776 void Assembler::sbbl(Register dst, int32_t imm32) {
3777 prefix(dst);
3778 emit_arith(0x81, 0xD8, dst, imm32);
3779 }
3780
3781
3782 void Assembler::sbbl(Register dst, Address src) {
3783 InstructionMark im(this);
3784 prefix(src, dst);
3785 emit_int8(0x1B);
3786 emit_operand(dst, src);
3787 }
3788
3789 void Assembler::sbbl(Register dst, Register src) {
3790 (void) prefix_and_encode(dst->encoding(), src->encoding());
3791 emit_arith(0x1B, 0xC0, dst, src);
3792 }
3793
3794 void Assembler::setb(Condition cc, Register dst) {
3795 assert(0 <= cc && cc < 16, "illegal cc");
3796 int encode = prefix_and_encode(dst->encoding(), true);
3797 emit_int8(0x0F);
3798 emit_int8((unsigned char)0x90 | cc);
3799 emit_int8((unsigned char)(0xC0 | encode));
3800 }
3801
3802 void Assembler::shll(Register dst, int imm8) {
3803 assert(isShiftCount(imm8), "illegal shift count");
3804 int encode = prefix_and_encode(dst->encoding());
3805 if (imm8 == 1 ) {
3806 emit_int8((unsigned char)0xD1);
3807 emit_int8((unsigned char)(0xE0 | encode));
3808 } else {
3809 emit_int8((unsigned char)0xC1);
3810 emit_int8((unsigned char)(0xE0 | encode));
3811 emit_int8(imm8);
3812 }
3813 }
3814
3815 void Assembler::shll(Register dst) {
3816 int encode = prefix_and_encode(dst->encoding());
3817 emit_int8((unsigned char)0xD3);
3818 emit_int8((unsigned char)(0xE0 | encode));
3819 }
3820
3821 void Assembler::shrl(Register dst, int imm8) {
3822 assert(isShiftCount(imm8), "illegal shift count");
3823 int encode = prefix_and_encode(dst->encoding());
3824 emit_int8((unsigned char)0xC1);
3825 emit_int8((unsigned char)(0xE8 | encode));
3826 emit_int8(imm8);
3827 }
3828
3829 void Assembler::shrl(Register dst) {
3830 int encode = prefix_and_encode(dst->encoding());
3831 emit_int8((unsigned char)0xD3);
3832 emit_int8((unsigned char)(0xE8 | encode));
3833 }
3834
3835 // copies a single word from [esi] to [edi]
3836 void Assembler::smovl() {
3837 emit_int8((unsigned char)0xA5);
3838 }
3839
3840 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3841 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3842 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3843 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3844 emit_int8(0x51);
3845 emit_int8((unsigned char)(0xC0 | encode));
3846 }
3847
3848 void Assembler::sqrtsd(XMMRegister dst, Address src) {
3849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3850 InstructionMark im(this);
3851 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3852 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3853 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3854 emit_int8(0x51);
3855 emit_operand(dst, src);
3856 }
3857
3858 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
3859 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3860 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3861 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3862 emit_int8(0x51);
3863 emit_int8((unsigned char)(0xC0 | encode));
3864 }
3865
3866 void Assembler::std() {
3867 emit_int8((unsigned char)0xFD);
3868 }
3869
3870 void Assembler::sqrtss(XMMRegister dst, Address src) {
3871 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3872 InstructionMark im(this);
3873 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3875 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3876 emit_int8(0x51);
3877 emit_operand(dst, src);
3878 }
3879
3880 void Assembler::stmxcsr( Address dst) {
3881 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3882 InstructionMark im(this);
3883 prefix(dst);
3884 emit_int8(0x0F);
3885 emit_int8((unsigned char)0xAE);
3886 emit_operand(as_Register(3), dst);
3887 }
3888
3889 void Assembler::subl(Address dst, int32_t imm32) {
3890 InstructionMark im(this);
3891 prefix(dst);
3892 emit_arith_operand(0x81, rbp, dst, imm32);
3893 }
3894
3895 void Assembler::subl(Address dst, Register src) {
3896 InstructionMark im(this);
3897 prefix(dst, src);
3898 emit_int8(0x29);
3899 emit_operand(src, dst);
3900 }
3901
3902 void Assembler::subl(Register dst, int32_t imm32) {
3903 prefix(dst);
3904 emit_arith(0x81, 0xE8, dst, imm32);
3905 }
3906
3907 // Force generation of a 4 byte immediate value even if it fits into 8bit
3908 void Assembler::subl_imm32(Register dst, int32_t imm32) {
3909 prefix(dst);
3910 emit_arith_imm32(0x81, 0xE8, dst, imm32);
3911 }
3912
3913 void Assembler::subl(Register dst, Address src) {
3914 InstructionMark im(this);
3915 prefix(src, dst);
3916 emit_int8(0x2B);
3917 emit_operand(dst, src);
3918 }
3919
3920 void Assembler::subl(Register dst, Register src) {
3921 (void) prefix_and_encode(dst->encoding(), src->encoding());
3922 emit_arith(0x2B, 0xC0, dst, src);
3923 }
3924
3925 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
3926 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3927 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3928 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3929 emit_int8(0x5C);
3930 emit_int8((unsigned char)(0xC0 | encode));
3931 }
3932
3933 void Assembler::subsd(XMMRegister dst, Address src) {
3934 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3935 InstructionMark im(this);
3936 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3937 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3938 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3939 emit_int8(0x5C);
3940 emit_operand(dst, src);
3941 }
3942
3943 void Assembler::subss(XMMRegister dst, XMMRegister src) {
3944 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3945 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3946 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3947 emit_int8(0x5C);
3948 emit_int8((unsigned char)(0xC0 | encode));
3949 }
3950
3951 void Assembler::subss(XMMRegister dst, Address src) {
3952 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3953 InstructionMark im(this);
3954 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3955 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3956 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3957 emit_int8(0x5C);
3958 emit_operand(dst, src);
3959 }
3960
3961 void Assembler::testb(Register dst, int imm8) {
3962 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3963 (void) prefix_and_encode(dst->encoding(), true);
3964 emit_arith_b(0xF6, 0xC0, dst, imm8);
3965 }
3966
3967 void Assembler::testb(Address dst, int imm8) {
3968 InstructionMark im(this);
3969 prefix(dst);
3970 emit_int8((unsigned char)0xF6);
3971 emit_operand(rax, dst, 1);
3972 emit_int8(imm8);
3973
3974 }
3975
3976 void Assembler::testl(Register dst, int32_t imm32) {
3977 // not using emit_arith because test
3978 // doesn't support sign-extension of
3979 // 8bit operands
3980 int encode = dst->encoding();
3981 if (encode == 0) {
3982 emit_int8((unsigned char)0xA9);
3983 } else {
3984 encode = prefix_and_encode(encode);
3985 emit_int8((unsigned char)0xF7);
3986 emit_int8((unsigned char)(0xC0 | encode));
3987 }
3988 emit_int32(imm32);
3989 }
3990
3991 void Assembler::testl(Register dst, Register src) {
3992 (void) prefix_and_encode(dst->encoding(), src->encoding());
3993 emit_arith(0x85, 0xC0, dst, src);
3994 }
3995
3996 void Assembler::testl(Register dst, Address src) {
3997 InstructionMark im(this);
3998 prefix(src, dst);
3999 emit_int8((unsigned char)0x85);
4000 emit_operand(dst, src);
4001 }
4002
4003 void Assembler::tzcntl(Register dst, Register src) {
4004 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4005 emit_int8((unsigned char)0xF3);
4006 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4007 emit_int8(0x0F);
4008 emit_int8((unsigned char)0xBC);
4009 emit_int8((unsigned char)0xC0 | encode);
4010 }
4011
4012 void Assembler::tzcntq(Register dst, Register src) {
4013 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4014 emit_int8((unsigned char)0xF3);
4015 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4016 emit_int8(0x0F);
4017 emit_int8((unsigned char)0xBC);
4018 emit_int8((unsigned char)(0xC0 | encode));
4019 }
4020
4021 void Assembler::ucomisd(XMMRegister dst, Address src) {
4022 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4023 InstructionMark im(this);
4024 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4025 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4026 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4027 emit_int8(0x2E);
4028 emit_operand(dst, src);
4029 }
4030
4031 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4032 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4033 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4034 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4035 emit_int8(0x2E);
4036 emit_int8((unsigned char)(0xC0 | encode));
4037 }
4038
4039 void Assembler::ucomiss(XMMRegister dst, Address src) {
4040 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4041 InstructionMark im(this);
4042 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4043 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4044 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4045 emit_int8(0x2E);
4046 emit_operand(dst, src);
4047 }
4048
4049 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4050 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4051 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4052 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4053 emit_int8(0x2E);
4054 emit_int8((unsigned char)(0xC0 | encode));
4055 }
4056
4057 void Assembler::xabort(int8_t imm8) {
4058 emit_int8((unsigned char)0xC6);
4059 emit_int8((unsigned char)0xF8);
4060 emit_int8((unsigned char)(imm8 & 0xFF));
4061 }
4062
4063 void Assembler::xaddl(Address dst, Register src) {
4064 InstructionMark im(this);
4065 prefix(dst, src);
4066 emit_int8(0x0F);
4067 emit_int8((unsigned char)0xC1);
4068 emit_operand(src, dst);
4069 }
4070
4071 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4072 InstructionMark im(this);
4073 relocate(rtype);
4074 if (abort.is_bound()) {
4075 address entry = target(abort);
4076 assert(entry != NULL, "abort entry NULL");
4077 intptr_t offset = entry - pc();
4078 emit_int8((unsigned char)0xC7);
4079 emit_int8((unsigned char)0xF8);
4080 emit_int32(offset - 6); // 2 opcode + 4 address
4081 } else {
4082 abort.add_patch_at(code(), locator());
4083 emit_int8((unsigned char)0xC7);
4084 emit_int8((unsigned char)0xF8);
4085 emit_int32(0);
4086 }
4087 }
4088
4089 void Assembler::xchgl(Register dst, Address src) { // xchg
4090 InstructionMark im(this);
4091 prefix(src, dst);
4092 emit_int8((unsigned char)0x87);
4093 emit_operand(dst, src);
4094 }
4095
4096 void Assembler::xchgl(Register dst, Register src) {
4097 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4098 emit_int8((unsigned char)0x87);
4099 emit_int8((unsigned char)(0xC0 | encode));
4100 }
4101
4102 void Assembler::xend() {
4103 emit_int8((unsigned char)0x0F);
4104 emit_int8((unsigned char)0x01);
4105 emit_int8((unsigned char)0xD5);
4106 }
4107
4108 void Assembler::xgetbv() {
4109 emit_int8(0x0F);
4110 emit_int8(0x01);
4111 emit_int8((unsigned char)0xD0);
4112 }
4113
4114 void Assembler::xorl(Register dst, int32_t imm32) {
4115 prefix(dst);
4116 emit_arith(0x81, 0xF0, dst, imm32);
4117 }
4118
4119 void Assembler::xorl(Register dst, Address src) {
4120 InstructionMark im(this);
4121 prefix(src, dst);
4122 emit_int8(0x33);
4123 emit_operand(dst, src);
4124 }
4125
4126 void Assembler::xorl(Register dst, Register src) {
4127 (void) prefix_and_encode(dst->encoding(), src->encoding());
4128 emit_arith(0x33, 0xC0, dst, src);
4129 }
4130
4131
4132 // AVX 3-operands scalar float-point arithmetic instructions
4133
4134 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4135 assert(VM_Version::supports_avx(), "");
4136 InstructionMark im(this);
4137 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4138 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4139 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4140 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4141 emit_int8(0x58);
4142 emit_operand(dst, src);
4143 }
4144
4145 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4146 assert(VM_Version::supports_avx(), "");
4147 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4148 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4149 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4150 emit_int8(0x58);
4151 emit_int8((unsigned char)(0xC0 | encode));
4152 }
4153
4154 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4155 assert(VM_Version::supports_avx(), "");
4156 InstructionMark im(this);
4157 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4158 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4159 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4160 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4161 emit_int8(0x58);
4162 emit_operand(dst, src);
4163 }
4164
4165 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4166 assert(VM_Version::supports_avx(), "");
4167 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4168 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4169 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4170 emit_int8(0x58);
4171 emit_int8((unsigned char)(0xC0 | encode));
4172 }
4173
4174 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4175 assert(VM_Version::supports_avx(), "");
4176 InstructionMark im(this);
4177 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4178 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4179 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4180 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4181 emit_int8(0x5E);
4182 emit_operand(dst, src);
4183 }
4184
4185 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4186 assert(VM_Version::supports_avx(), "");
4187 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4188 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4189 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4190 emit_int8(0x5E);
4191 emit_int8((unsigned char)(0xC0 | encode));
4192 }
4193
4194 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4195 assert(VM_Version::supports_avx(), "");
4196 InstructionMark im(this);
4197 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4198 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4199 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4200 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4201 emit_int8(0x5E);
4202 emit_operand(dst, src);
4203 }
4204
4205 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4206 assert(VM_Version::supports_avx(), "");
4207 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4208 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4209 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4210 emit_int8(0x5E);
4211 emit_int8((unsigned char)(0xC0 | encode));
4212 }
4213
4214 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4215 assert(VM_Version::supports_avx(), "");
4216 InstructionMark im(this);
4217 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4218 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4219 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4220 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4221 emit_int8(0x59);
4222 emit_operand(dst, src);
4223 }
4224
4225 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4226 assert(VM_Version::supports_avx(), "");
4227 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4228 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4229 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4230 emit_int8(0x59);
4231 emit_int8((unsigned char)(0xC0 | encode));
4232 }
4233
4234 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4235 assert(VM_Version::supports_avx(), "");
4236 InstructionMark im(this);
4237 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4238 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4239 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4240 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4241 emit_int8(0x59);
4242 emit_operand(dst, src);
4243 }
4244
4245 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4246 assert(VM_Version::supports_avx(), "");
4247 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4248 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4249 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4250 emit_int8(0x59);
4251 emit_int8((unsigned char)(0xC0 | encode));
4252 }
4253
4254 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4255 assert(VM_Version::supports_avx(), "");
4256 InstructionMark im(this);
4257 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4258 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4259 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4260 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4261 emit_int8(0x5C);
4262 emit_operand(dst, src);
4263 }
4264
4265 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4266 assert(VM_Version::supports_avx(), "");
4267 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4268 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4269 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4270 emit_int8(0x5C);
4271 emit_int8((unsigned char)(0xC0 | encode));
4272 }
4273
4274 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4275 assert(VM_Version::supports_avx(), "");
4276 InstructionMark im(this);
4277 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4278 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4279 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4280 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4281 emit_int8(0x5C);
4282 emit_operand(dst, src);
4283 }
4284
4285 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4286 assert(VM_Version::supports_avx(), "");
4287 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4288 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4289 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4290 emit_int8(0x5C);
4291 emit_int8((unsigned char)(0xC0 | encode));
4292 }
4293
4294 //====================VECTOR ARITHMETIC=====================================
4295
4296 // Float-point vector arithmetic
4297
4298 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4299 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4300 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4301 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4302 emit_int8(0x58);
4303 emit_int8((unsigned char)(0xC0 | encode));
4304 }
4305
4306 void Assembler::addpd(XMMRegister dst, Address src) {
4307 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4308 InstructionMark im(this);
4309 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4310 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4311 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4312 emit_int8(0x58);
4313 emit_operand(dst, src);
4314 }
4315
4316 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4317 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4318 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4319 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4320 emit_int8(0x58);
4321 emit_int8((unsigned char)(0xC0 | encode));
4322 }
4323
4324 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4325 assert(VM_Version::supports_avx(), "");
4326 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4327 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4328 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4329 emit_int8(0x58);
4330 emit_int8((unsigned char)(0xC0 | encode));
4331 }
4332
4333 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4334 assert(VM_Version::supports_avx(), "");
4335 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4336 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4337 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4338 emit_int8(0x58);
4339 emit_int8((unsigned char)(0xC0 | encode));
4340 }
4341
4342 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4343 assert(VM_Version::supports_avx(), "");
4344 InstructionMark im(this);
4345 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4346 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4347 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4348 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4349 emit_int8(0x58);
4350 emit_operand(dst, src);
4351 }
4352
4353 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4354 assert(VM_Version::supports_avx(), "");
4355 InstructionMark im(this);
4356 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4357 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4358 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4359 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4360 emit_int8(0x58);
4361 emit_operand(dst, src);
4362 }
4363
4364 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4365 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4366 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4367 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4368 emit_int8(0x5C);
4369 emit_int8((unsigned char)(0xC0 | encode));
4370 }
4371
4372 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4374 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4375 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4376 emit_int8(0x5C);
4377 emit_int8((unsigned char)(0xC0 | encode));
4378 }
4379
4380 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4381 assert(VM_Version::supports_avx(), "");
4382 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4383 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4384 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4385 emit_int8(0x5C);
4386 emit_int8((unsigned char)(0xC0 | encode));
4387 }
4388
4389 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4390 assert(VM_Version::supports_avx(), "");
4391 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4392 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4393 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4394 emit_int8(0x5C);
4395 emit_int8((unsigned char)(0xC0 | encode));
4396 }
4397
4398 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4399 assert(VM_Version::supports_avx(), "");
4400 InstructionMark im(this);
4401 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4402 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4403 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4404 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4405 emit_int8(0x5C);
4406 emit_operand(dst, src);
4407 }
4408
4409 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4410 assert(VM_Version::supports_avx(), "");
4411 InstructionMark im(this);
4412 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4413 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4414 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4415 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4416 emit_int8(0x5C);
4417 emit_operand(dst, src);
4418 }
4419
4420 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4421 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4422 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4423 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4424 emit_int8(0x59);
4425 emit_int8((unsigned char)(0xC0 | encode));
4426 }
4427
4428 void Assembler::mulpd(XMMRegister dst, Address src) {
4429 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4430 InstructionMark im(this);
4431 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4432 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4433 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4434 emit_int8(0x59);
4435 emit_operand(dst, src);
4436 }
4437
4438 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4440 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4441 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4442 emit_int8(0x59);
4443 emit_int8((unsigned char)(0xC0 | encode));
4444 }
4445
4446 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4447 assert(VM_Version::supports_avx(), "");
4448 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4449 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4450 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4451 emit_int8(0x59);
4452 emit_int8((unsigned char)(0xC0 | encode));
4453 }
4454
4455 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4456 assert(VM_Version::supports_avx(), "");
4457 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4458 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4459 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4460 emit_int8(0x59);
4461 emit_int8((unsigned char)(0xC0 | encode));
4462 }
4463
4464 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4465 assert(VM_Version::supports_avx(), "");
4466 InstructionMark im(this);
4467 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4468 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4469 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4470 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4471 emit_int8(0x59);
4472 emit_operand(dst, src);
4473 }
4474
4475 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4476 assert(VM_Version::supports_avx(), "");
4477 InstructionMark im(this);
4478 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4479 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4480 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4481 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4482 emit_int8(0x59);
4483 emit_operand(dst, src);
4484 }
4485
4486 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4487 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4488 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4489 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4490 emit_int8(0x5E);
4491 emit_int8((unsigned char)(0xC0 | encode));
4492 }
4493
4494 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4495 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4496 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4497 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4498 emit_int8(0x5E);
4499 emit_int8((unsigned char)(0xC0 | encode));
4500 }
4501
4502 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4503 assert(VM_Version::supports_avx(), "");
4504 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4505 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4506 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4507 emit_int8(0x5E);
4508 emit_int8((unsigned char)(0xC0 | encode));
4509 }
4510
4511 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4512 assert(VM_Version::supports_avx(), "");
4513 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4514 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4515 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4516 emit_int8(0x5E);
4517 emit_int8((unsigned char)(0xC0 | encode));
4518 }
4519
4520 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4521 assert(VM_Version::supports_avx(), "");
4522 InstructionMark im(this);
4523 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4524 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4525 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4526 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4527 emit_int8(0x5E);
4528 emit_operand(dst, src);
4529 }
4530
4531 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4532 assert(VM_Version::supports_avx(), "");
4533 InstructionMark im(this);
4534 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4535 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4536 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4537 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4538 emit_int8(0x5E);
4539 emit_operand(dst, src);
4540 }
4541
4542 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4543 assert(VM_Version::supports_avx(), "");
4544 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4545 int nds_enc = 0;
4546 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4547 emit_int8(0x51);
4548 emit_int8((unsigned char)(0xC0 | encode));
4549 }
4550
4551 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4552 assert(VM_Version::supports_avx(), "");
4553 InstructionMark im(this);
4554 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4555 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4556 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4557 emit_int8(0x51);
4558 emit_operand(dst, src);
4559 }
4560
4561 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4562 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4563 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4564 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4565 emit_int8(0x54);
4566 emit_int8((unsigned char)(0xC0 | encode));
4567 }
4568
4569 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4570 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4571 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4572 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4573 emit_int8(0x54);
4574 emit_int8((unsigned char)(0xC0 | encode));
4575 }
4576
4577 void Assembler::andps(XMMRegister dst, Address src) {
4578 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4579 InstructionMark im(this);
4580 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4581 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4582 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4583 emit_int8(0x54);
4584 emit_operand(dst, src);
4585 }
4586
4587 void Assembler::andpd(XMMRegister dst, Address src) {
4588 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4589 InstructionMark im(this);
4590 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4591 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4592 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4593 emit_int8(0x54);
4594 emit_operand(dst, src);
4595 }
4596
4597 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4598 assert(VM_Version::supports_avx(), "");
4599 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4600 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4601 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4602 emit_int8(0x54);
4603 emit_int8((unsigned char)(0xC0 | encode));
4604 }
4605
4606 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4607 assert(VM_Version::supports_avx(), "");
4608 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4609 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4610 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4611 emit_int8(0x54);
4612 emit_int8((unsigned char)(0xC0 | encode));
4613 }
4614
4615 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4616 assert(VM_Version::supports_avx(), "");
4617 InstructionMark im(this);
4618 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4619 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4620 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4621 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4622 emit_int8(0x54);
4623 emit_operand(dst, src);
4624 }
4625
4626 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4627 assert(VM_Version::supports_avx(), "");
4628 InstructionMark im(this);
4629 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4630 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4631 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4632 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4633 emit_int8(0x54);
4634 emit_operand(dst, src);
4635 }
4636
4637 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4638 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4639 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4640 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4641 emit_int8(0x15);
4642 emit_int8((unsigned char)(0xC0 | encode));
4643 }
4644
4645 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4646 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4647 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4648 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4649 emit_int8(0x14);
4650 emit_int8((unsigned char)(0xC0 | encode));
4651 }
4652
4653 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4654 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4655 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4656 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4657 emit_int8(0x57);
4658 emit_int8((unsigned char)(0xC0 | encode));
4659 }
4660
4661 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4662 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4663 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4664 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4665 emit_int8(0x57);
4666 emit_int8((unsigned char)(0xC0 | encode));
4667 }
4668
4669 void Assembler::xorpd(XMMRegister dst, Address src) {
4670 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4671 InstructionMark im(this);
4672 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4673 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4674 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4675 emit_int8(0x57);
4676 emit_operand(dst, src);
4677 }
4678
4679 void Assembler::xorps(XMMRegister dst, Address src) {
4680 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4681 InstructionMark im(this);
4682 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4683 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4684 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4685 emit_int8(0x57);
4686 emit_operand(dst, src);
4687 }
4688
4689 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4690 assert(VM_Version::supports_avx(), "");
4691 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4692 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4693 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4694 emit_int8(0x57);
4695 emit_int8((unsigned char)(0xC0 | encode));
4696 }
4697
4698 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4699 assert(VM_Version::supports_avx(), "");
4700 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4701 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4702 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4703 emit_int8(0x57);
4704 emit_int8((unsigned char)(0xC0 | encode));
4705 }
4706
4707 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4708 assert(VM_Version::supports_avx(), "");
4709 InstructionMark im(this);
4710 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4711 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4712 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4713 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4714 emit_int8(0x57);
4715 emit_operand(dst, src);
4716 }
4717
4718 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4719 assert(VM_Version::supports_avx(), "");
4720 InstructionMark im(this);
4721 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4722 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4723 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4724 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4725 emit_int8(0x57);
4726 emit_operand(dst, src);
4727 }
4728
4729 // Integer vector arithmetic
4730 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4731 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4732 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4733 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4734 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4735 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4736 emit_int8(0x01);
4737 emit_int8((unsigned char)(0xC0 | encode));
4738 }
4739
4740 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4741 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4742 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4743 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4744 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4745 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4746 emit_int8(0x02);
4747 emit_int8((unsigned char)(0xC0 | encode));
4748 }
4749
4750 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4751 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4752 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4753 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4754 emit_int8((unsigned char)0xFC);
4755 emit_int8((unsigned char)(0xC0 | encode));
4756 }
4757
4758 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4759 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4760 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4761 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4762 emit_int8((unsigned char)0xFD);
4763 emit_int8((unsigned char)(0xC0 | encode));
4764 }
4765
4766 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4767 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4768 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4769 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4770 emit_int8((unsigned char)0xFE);
4771 emit_int8((unsigned char)(0xC0 | encode));
4772 }
4773
4774 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4775 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4776 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4777 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4778 emit_int8((unsigned char)0xD4);
4779 emit_int8((unsigned char)(0xC0 | encode));
4780 }
4781
4782 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4783 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4784 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4785 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4786 emit_int8(0x01);
4787 emit_int8((unsigned char)(0xC0 | encode));
4788 }
4789
4790 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
4791 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4792 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4793 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4794 emit_int8(0x02);
4795 emit_int8((unsigned char)(0xC0 | encode));
4796 }
4797
4798 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4799 assert(UseAVX > 0, "requires some form of AVX");
4800 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4801 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4802 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4803 emit_int8((unsigned char)0xFC);
4804 emit_int8((unsigned char)(0xC0 | encode));
4805 }
4806
4807 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4808 assert(UseAVX > 0, "requires some form of AVX");
4809 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4810 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4811 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4812 emit_int8((unsigned char)0xFD);
4813 emit_int8((unsigned char)(0xC0 | encode));
4814 }
4815
4816 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4817 assert(UseAVX > 0, "requires some form of AVX");
4818 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4819 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4820 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4821 emit_int8((unsigned char)0xFE);
4822 emit_int8((unsigned char)(0xC0 | encode));
4823 }
4824
4825 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4826 assert(UseAVX > 0, "requires some form of AVX");
4827 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4828 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4829 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4830 emit_int8((unsigned char)0xD4);
4831 emit_int8((unsigned char)(0xC0 | encode));
4832 }
4833
4834 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4835 assert(UseAVX > 0, "requires some form of AVX");
4836 InstructionMark im(this);
4837 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4838 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4839 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4840 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4841 emit_int8((unsigned char)0xFC);
4842 emit_operand(dst, src);
4843 }
4844
4845 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4846 assert(UseAVX > 0, "requires some form of AVX");
4847 InstructionMark im(this);
4848 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4849 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4850 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4851 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4852 emit_int8((unsigned char)0xFD);
4853 emit_operand(dst, src);
4854 }
4855
4856 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4857 assert(UseAVX > 0, "requires some form of AVX");
4858 InstructionMark im(this);
4859 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4860 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4861 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4862 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4863 emit_int8((unsigned char)0xFE);
4864 emit_operand(dst, src);
4865 }
4866
4867 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4868 assert(UseAVX > 0, "requires some form of AVX");
4869 InstructionMark im(this);
4870 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4871 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4872 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4873 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4874 emit_int8((unsigned char)0xD4);
4875 emit_operand(dst, src);
4876 }
4877
4878 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
4879 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4880 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4881 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4882 emit_int8((unsigned char)0xF8);
4883 emit_int8((unsigned char)(0xC0 | encode));
4884 }
4885
4886 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
4887 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4888 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4889 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4890 emit_int8((unsigned char)0xF9);
4891 emit_int8((unsigned char)(0xC0 | encode));
4892 }
4893
4894 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
4895 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4896 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4897 emit_int8((unsigned char)0xFA);
4898 emit_int8((unsigned char)(0xC0 | encode));
4899 }
4900
4901 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
4902 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4903 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4904 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4905 emit_int8((unsigned char)0xFB);
4906 emit_int8((unsigned char)(0xC0 | encode));
4907 }
4908
4909 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4910 assert(UseAVX > 0, "requires some form of AVX");
4911 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4912 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4913 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4914 emit_int8((unsigned char)0xF8);
4915 emit_int8((unsigned char)(0xC0 | encode));
4916 }
4917
4918 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4919 assert(UseAVX > 0, "requires some form of AVX");
4920 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4921 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4922 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4923 emit_int8((unsigned char)0xF9);
4924 emit_int8((unsigned char)(0xC0 | encode));
4925 }
4926
4927 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4928 assert(UseAVX > 0, "requires some form of AVX");
4929 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4930 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4931 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4932 emit_int8((unsigned char)0xFA);
4933 emit_int8((unsigned char)(0xC0 | encode));
4934 }
4935
4936 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4937 assert(UseAVX > 0, "requires some form of AVX");
4938 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4939 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4940 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4941 emit_int8((unsigned char)0xFB);
4942 emit_int8((unsigned char)(0xC0 | encode));
4943 }
4944
4945 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4946 assert(UseAVX > 0, "requires some form of AVX");
4947 InstructionMark im(this);
4948 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4949 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4950 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4951 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4952 emit_int8((unsigned char)0xF8);
4953 emit_operand(dst, src);
4954 }
4955
4956 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4957 assert(UseAVX > 0, "requires some form of AVX");
4958 InstructionMark im(this);
4959 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4960 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4961 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4962 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4963 emit_int8((unsigned char)0xF9);
4964 emit_operand(dst, src);
4965 }
4966
4967 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4968 assert(UseAVX > 0, "requires some form of AVX");
4969 InstructionMark im(this);
4970 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4971 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4972 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4973 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4974 emit_int8((unsigned char)0xFA);
4975 emit_operand(dst, src);
4976 }
4977
4978 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4979 assert(UseAVX > 0, "requires some form of AVX");
4980 InstructionMark im(this);
4981 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4982 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4983 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4984 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4985 emit_int8((unsigned char)0xFB);
4986 emit_operand(dst, src);
4987 }
4988
4989 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
4990 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4991 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4993 emit_int8((unsigned char)0xD5);
4994 emit_int8((unsigned char)(0xC0 | encode));
4995 }
4996
4997 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
4998 assert(VM_Version::supports_sse4_1(), "");
4999 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5000 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5001 emit_int8(0x40);
5002 emit_int8((unsigned char)(0xC0 | encode));
5003 }
5004
5005 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5006 assert(UseAVX > 0, "requires some form of AVX");
5007 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5008 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5009 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5010 emit_int8((unsigned char)0xD5);
5011 emit_int8((unsigned char)(0xC0 | encode));
5012 }
5013
5014 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5015 assert(UseAVX > 0, "requires some form of AVX");
5016 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5017 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5018 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5019 emit_int8(0x40);
5020 emit_int8((unsigned char)(0xC0 | encode));
5021 }
5022
5023 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5024 assert(UseAVX > 2, "requires some form of AVX");
5025 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5026 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5027 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5028 emit_int8(0x40);
5029 emit_int8((unsigned char)(0xC0 | encode));
5030 }
5031
5032 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5033 assert(UseAVX > 0, "requires some form of AVX");
5034 InstructionMark im(this);
5035 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5036 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5037 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5038 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5039 emit_int8((unsigned char)0xD5);
5040 emit_operand(dst, src);
5041 }
5042
5043 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5044 assert(UseAVX > 0, "requires some form of AVX");
5045 InstructionMark im(this);
5046 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5047 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5048 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5049 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5050 emit_int8(0x40);
5051 emit_operand(dst, src);
5052 }
5053
5054 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5055 assert(UseAVX > 0, "requires some form of AVX");
5056 InstructionMark im(this);
5057 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5058 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5059 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5060 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5061 emit_int8(0x40);
5062 emit_operand(dst, src);
5063 }
5064
5065 // Shift packed integers left by specified number of bits.
5066 void Assembler::psllw(XMMRegister dst, int shift) {
5067 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5068 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5069 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5070 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5071 emit_int8(0x71);
5072 emit_int8((unsigned char)(0xC0 | encode));
5073 emit_int8(shift & 0xFF);
5074 }
5075
5076 void Assembler::pslld(XMMRegister dst, int shift) {
5077 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5078 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5079 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5080 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5081 emit_int8(0x72);
5082 emit_int8((unsigned char)(0xC0 | encode));
5083 emit_int8(shift & 0xFF);
5084 }
5085
5086 void Assembler::psllq(XMMRegister dst, int shift) {
5087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5088 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5089 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5090 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5091 emit_int8(0x73);
5092 emit_int8((unsigned char)(0xC0 | encode));
5093 emit_int8(shift & 0xFF);
5094 }
5095
5096 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5098 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5099 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5100 emit_int8((unsigned char)0xF1);
5101 emit_int8((unsigned char)(0xC0 | encode));
5102 }
5103
5104 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5105 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5106 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5107 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5108 emit_int8((unsigned char)0xF2);
5109 emit_int8((unsigned char)(0xC0 | encode));
5110 }
5111
5112 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5114 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5115 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5116 emit_int8((unsigned char)0xF3);
5117 emit_int8((unsigned char)(0xC0 | encode));
5118 }
5119
5120 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5121 assert(UseAVX > 0, "requires some form of AVX");
5122 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5123 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5124 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5125 emit_int8(0x71);
5126 emit_int8((unsigned char)(0xC0 | encode));
5127 emit_int8(shift & 0xFF);
5128 }
5129
5130 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5131 assert(UseAVX > 0, "requires some form of AVX");
5132 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5133 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5134 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5135 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5136 emit_int8(0x72);
5137 emit_int8((unsigned char)(0xC0 | encode));
5138 emit_int8(shift & 0xFF);
5139 }
5140
5141 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5142 assert(UseAVX > 0, "requires some form of AVX");
5143 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5144 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5145 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5146 emit_int8(0x73);
5147 emit_int8((unsigned char)(0xC0 | encode));
5148 emit_int8(shift & 0xFF);
5149 }
5150
5151 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5152 assert(UseAVX > 0, "requires some form of AVX");
5153 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5154 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5155 emit_int8((unsigned char)0xF1);
5156 emit_int8((unsigned char)(0xC0 | encode));
5157 }
5158
5159 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5160 assert(UseAVX > 0, "requires some form of AVX");
5161 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5162 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5163 emit_int8((unsigned char)0xF2);
5164 emit_int8((unsigned char)(0xC0 | encode));
5165 }
5166
5167 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5168 assert(UseAVX > 0, "requires some form of AVX");
5169 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5170 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5171 emit_int8((unsigned char)0xF3);
5172 emit_int8((unsigned char)(0xC0 | encode));
5173 }
5174
5175 // Shift packed integers logically right by specified number of bits.
5176 void Assembler::psrlw(XMMRegister dst, int shift) {
5177 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5178 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5179 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5180 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5181 emit_int8(0x71);
5182 emit_int8((unsigned char)(0xC0 | encode));
5183 emit_int8(shift & 0xFF);
5184 }
5185
5186 void Assembler::psrld(XMMRegister dst, int shift) {
5187 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5188 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5189 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5190 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5191 emit_int8(0x72);
5192 emit_int8((unsigned char)(0xC0 | encode));
5193 emit_int8(shift & 0xFF);
5194 }
5195
5196 void Assembler::psrlq(XMMRegister dst, int shift) {
5197 // Do not confuse it with psrldq SSE2 instruction which
5198 // shifts 128 bit value in xmm register by number of bytes.
5199 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5200 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5201 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5202 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5203 emit_int8(0x73);
5204 emit_int8((unsigned char)(0xC0 | encode));
5205 emit_int8(shift & 0xFF);
5206 }
5207
5208 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5209 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5211 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5212 emit_int8((unsigned char)0xD1);
5213 emit_int8((unsigned char)(0xC0 | encode));
5214 }
5215
5216 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5217 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5218 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5219 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5220 emit_int8((unsigned char)0xD2);
5221 emit_int8((unsigned char)(0xC0 | encode));
5222 }
5223
5224 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5225 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5226 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5227 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5228 emit_int8((unsigned char)0xD3);
5229 emit_int8((unsigned char)(0xC0 | encode));
5230 }
5231
5232 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5233 assert(UseAVX > 0, "requires some form of AVX");
5234 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5235 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5236 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5237 emit_int8(0x71);
5238 emit_int8((unsigned char)(0xC0 | encode));
5239 emit_int8(shift & 0xFF);
5240 }
5241
5242 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5243 assert(UseAVX > 0, "requires some form of AVX");
5244 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5245 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5246 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5247 emit_int8(0x72);
5248 emit_int8((unsigned char)(0xC0 | encode));
5249 emit_int8(shift & 0xFF);
5250 }
5251
5252 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5253 assert(UseAVX > 0, "requires some form of AVX");
5254 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5255 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5256 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5257 emit_int8(0x73);
5258 emit_int8((unsigned char)(0xC0 | encode));
5259 emit_int8(shift & 0xFF);
5260 }
5261
5262 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5263 assert(UseAVX > 0, "requires some form of AVX");
5264 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5265 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5266 emit_int8((unsigned char)0xD1);
5267 emit_int8((unsigned char)(0xC0 | encode));
5268 }
5269
5270 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5271 assert(UseAVX > 0, "requires some form of AVX");
5272 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5273 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5274 emit_int8((unsigned char)0xD2);
5275 emit_int8((unsigned char)(0xC0 | encode));
5276 }
5277
5278 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5279 assert(UseAVX > 0, "requires some form of AVX");
5280 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5281 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5282 emit_int8((unsigned char)0xD3);
5283 emit_int8((unsigned char)(0xC0 | encode));
5284 }
5285
5286 // Shift packed integers arithmetically right by specified number of bits.
5287 void Assembler::psraw(XMMRegister dst, int shift) {
5288 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5290 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5291 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5292 emit_int8(0x71);
5293 emit_int8((unsigned char)(0xC0 | encode));
5294 emit_int8(shift & 0xFF);
5295 }
5296
5297 void Assembler::psrad(XMMRegister dst, int shift) {
5298 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5299 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5300 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5301 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5302 emit_int8(0x72);
5303 emit_int8((unsigned char)(0xC0 | encode));
5304 emit_int8(shift & 0xFF);
5305 }
5306
5307 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5310 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5311 emit_int8((unsigned char)0xE1);
5312 emit_int8((unsigned char)(0xC0 | encode));
5313 }
5314
5315 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5316 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5317 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5318 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5319 emit_int8((unsigned char)0xE2);
5320 emit_int8((unsigned char)(0xC0 | encode));
5321 }
5322
5323 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5324 assert(UseAVX > 0, "requires some form of AVX");
5325 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5326 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5327 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5328 emit_int8(0x71);
5329 emit_int8((unsigned char)(0xC0 | encode));
5330 emit_int8(shift & 0xFF);
5331 }
5332
5333 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5334 assert(UseAVX > 0, "requires some form of AVX");
5335 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5336 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5337 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5338 emit_int8(0x72);
5339 emit_int8((unsigned char)(0xC0 | encode));
5340 emit_int8(shift & 0xFF);
5341 }
5342
5343 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5344 assert(UseAVX > 0, "requires some form of AVX");
5345 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5346 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5347 emit_int8((unsigned char)0xE1);
5348 emit_int8((unsigned char)(0xC0 | encode));
5349 }
5350
5351 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5352 assert(UseAVX > 0, "requires some form of AVX");
5353 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5354 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5355 emit_int8((unsigned char)0xE2);
5356 emit_int8((unsigned char)(0xC0 | encode));
5357 }
5358
5359
5360 // logical operations packed integers
5361 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5364 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5365 emit_int8((unsigned char)0xDB);
5366 emit_int8((unsigned char)(0xC0 | encode));
5367 }
5368
5369 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5370 assert(UseAVX > 0, "requires some form of AVX");
5371 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5372 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5373 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5374 emit_int8((unsigned char)0xDB);
5375 emit_int8((unsigned char)(0xC0 | encode));
5376 }
5377
5378 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5379 assert(UseAVX > 0, "requires some form of AVX");
5380 InstructionMark im(this);
5381 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5382 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5383 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5384 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5385 emit_int8((unsigned char)0xDB);
5386 emit_operand(dst, src);
5387 }
5388
5389 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5391 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5392 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5393 emit_int8((unsigned char)0xDF);
5394 emit_int8((unsigned char)(0xC0 | encode));
5395 }
5396
5397 void Assembler::por(XMMRegister dst, XMMRegister src) {
5398 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5399 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5400 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5401 emit_int8((unsigned char)0xEB);
5402 emit_int8((unsigned char)(0xC0 | encode));
5403 }
5404
5405 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5406 assert(UseAVX > 0, "requires some form of AVX");
5407 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5408 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5409 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5410 emit_int8((unsigned char)0xEB);
5411 emit_int8((unsigned char)(0xC0 | encode));
5412 }
5413
5414 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5415 assert(UseAVX > 0, "requires some form of AVX");
5416 InstructionMark im(this);
5417 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5418 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5419 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5420 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5421 emit_int8((unsigned char)0xEB);
5422 emit_operand(dst, src);
5423 }
5424
5425 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5426 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5427 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5428 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5429 emit_int8((unsigned char)0xEF);
5430 emit_int8((unsigned char)(0xC0 | encode));
5431 }
5432
5433 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5434 assert(UseAVX > 0, "requires some form of AVX");
5435 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5436 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5437 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5438 emit_int8((unsigned char)0xEF);
5439 emit_int8((unsigned char)(0xC0 | encode));
5440 }
5441
5442 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5443 assert(UseAVX > 0, "requires some form of AVX");
5444 InstructionMark im(this);
5445 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5446 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5447 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5448 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5449 emit_int8((unsigned char)0xEF);
5450 emit_operand(dst, src);
5451 }
5452
5453
5454 void Assembler::vinsertf128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5455 assert(VM_Version::supports_avx(), "");
5456 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5457 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5458 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5459 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5460 emit_int8(0x18);
5461 emit_int8((unsigned char)(0xC0 | encode));
5462 // 0x00 - insert into lower 128 bits
5463 // 0x01 - insert into upper 128 bits
5464 emit_int8(0x01);
5465 }
5466
5467 void Assembler::vinsertf64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5468 assert(VM_Version::supports_evex(), "");
5469 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5470 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5471 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5472 emit_int8(0x1A);
5473 emit_int8((unsigned char)(0xC0 | encode));
5474 // 0x00 - insert into lower 256 bits
5475 // 0x01 - insert into upper 256 bits
5476 emit_int8(value & 0x01);
5477 }
5478
5479 void Assembler::vinsertf64x4h(XMMRegister dst, Address src, int value) {
5480 assert(VM_Version::supports_evex(), "");
5481 assert(dst != xnoreg, "sanity");
5482 InstructionMark im(this);
5483 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5484 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5485 // swap src<->dst for encoding
5486 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5487 emit_int8(0x1A);
5488 emit_operand(dst, src);
5489 // 0x00 - insert into lower 256 bits
5490 // 0x01 - insert into upper 128 bits
5491 emit_int8(value & 0x01);
5492 }
5493
5494 void Assembler::vinsertf32x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5495 assert(VM_Version::supports_evex(), "");
5496 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5497 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5498 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5499 emit_int8(0x18);
5500 emit_int8((unsigned char)(0xC0 | encode));
5501 // 0x00 - insert into q0 128 bits (0..127)
5502 // 0x01 - insert into q1 128 bits (128..255)
5503 // 0x02 - insert into q2 128 bits (256..383)
5504 // 0x03 - insert into q3 128 bits (384..511)
5505 emit_int8(value & 0x3);
5506 }
5507
5508 void Assembler::vinsertf32x4h(XMMRegister dst, Address src, int value) {
5509 assert(VM_Version::supports_avx(), "");
5510 assert(dst != xnoreg, "sanity");
5511 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5512 InstructionMark im(this);
5513 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5514 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5515 // swap src<->dst for encoding
5516 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5517 emit_int8(0x18);
5518 emit_operand(dst, src);
5519 // 0x00 - insert into q0 128 bits (0..127)
5520 // 0x01 - insert into q1 128 bits (128..255)
5521 // 0x02 - insert into q2 128 bits (256..383)
5522 // 0x03 - insert into q3 128 bits (384..511)
5523 emit_int8(value & 0x3);
5524 }
5525
5526 void Assembler::vinsertf128h(XMMRegister dst, Address src) {
5527 assert(VM_Version::supports_avx(), "");
5528 assert(dst != xnoreg, "sanity");
5529 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5530 InstructionMark im(this);
5531 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5532 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5533 // swap src<->dst for encoding
5534 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5535 emit_int8(0x18);
5536 emit_operand(dst, src);
5537 // 0x01 - insert into upper 128 bits
5538 emit_int8(0x01);
5539 }
5540
5541 void Assembler::vextractf128h(XMMRegister dst, XMMRegister src) {
5542 assert(VM_Version::supports_avx(), "");
5543 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5544 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5545 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5546 emit_int8(0x19);
5547 emit_int8((unsigned char)(0xC0 | encode));
5548 // 0x00 - insert into lower 128 bits
5549 // 0x01 - insert into upper 128 bits
5550 emit_int8(0x01);
5551 }
5552
5553 void Assembler::vextractf128h(Address dst, XMMRegister src) {
5554 assert(VM_Version::supports_avx(), "");
5555 assert(src != xnoreg, "sanity");
5556 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5557 InstructionMark im(this);
5558 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5559 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5560 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5561 emit_int8(0x19);
5562 emit_operand(src, dst);
5563 // 0x01 - extract from upper 128 bits
5564 emit_int8(0x01);
5565 }
5566
5567 void Assembler::vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5568 assert(VM_Version::supports_avx2(), "");
5569 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5570 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5571 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5572 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5573 emit_int8(0x38);
5574 emit_int8((unsigned char)(0xC0 | encode));
5575 // 0x00 - insert into lower 128 bits
5576 // 0x01 - insert into upper 128 bits
5577 emit_int8(0x01);
5578 }
5579
5580 void Assembler::vinserti64x4h(XMMRegister dst, XMMRegister nds, XMMRegister src, int value) {
5581 assert(VM_Version::supports_evex(), "");
5582 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5583 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5584 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5585 emit_int8(0x38);
5586 emit_int8((unsigned char)(0xC0 | encode));
5587 // 0x00 - insert into lower 256 bits
5588 // 0x01 - insert into upper 256 bits
5589 emit_int8(value & 0x01);
5590 }
5591
5592 void Assembler::vinserti128h(XMMRegister dst, Address src) {
5593 assert(VM_Version::supports_avx2(), "");
5594 assert(dst != xnoreg, "sanity");
5595 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5596 InstructionMark im(this);
5597 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5598 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5599 // swap src<->dst for encoding
5600 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5601 emit_int8(0x38);
5602 emit_operand(dst, src);
5603 // 0x01 - insert into upper 128 bits
5604 emit_int8(0x01);
5605 }
5606
5607 void Assembler::vextracti128h(XMMRegister dst, XMMRegister src) {
5608 assert(VM_Version::supports_avx(), "");
5609 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5610 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5611 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5612 emit_int8(0x39);
5613 emit_int8((unsigned char)(0xC0 | encode));
5614 // 0x00 - insert into lower 128 bits
5615 // 0x01 - insert into upper 128 bits
5616 emit_int8(0x01);
5617 }
5618
5619 void Assembler::vextracti128h(Address dst, XMMRegister src) {
5620 assert(VM_Version::supports_avx2(), "");
5621 assert(src != xnoreg, "sanity");
5622 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5623 InstructionMark im(this);
5624 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5625 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5626 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5627 emit_int8(0x39);
5628 emit_operand(src, dst);
5629 // 0x01 - extract from upper 128 bits
5630 emit_int8(0x01);
5631 }
5632
5633 void Assembler::vextracti64x4h(XMMRegister dst, XMMRegister src, int value) {
5634 assert(VM_Version::supports_evex(), "");
5635 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5636 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5637 emit_int8(0x3B);
5638 emit_int8((unsigned char)(0xC0 | encode));
5639 // 0x00 - extract from lower 256 bits
5640 // 0x01 - extract from upper 256 bits
5641 emit_int8(value & 0x01);
5642 }
5643
5644 void Assembler::vextracti64x2h(XMMRegister dst, XMMRegister src, int value) {
5645 assert(VM_Version::supports_evex(), "");
5646 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5647 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5648 emit_int8(0x39);
5649 emit_int8((unsigned char)(0xC0 | encode));
5650 // 0x01 - extract from bits 255:128
5651 // 0x02 - extract from bits 383:256
5652 // 0x03 - extract from bits 511:384
5653 emit_int8(value & 0x3);
5654 }
5655
5656 void Assembler::vextractf64x4h(XMMRegister dst, XMMRegister src, int value) {
5657 assert(VM_Version::supports_evex(), "");
5658 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5659 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5660 emit_int8(0x1B);
5661 emit_int8((unsigned char)(0xC0 | encode));
5662 // 0x00 - extract from lower 256 bits
5663 // 0x01 - extract from upper 256 bits
5664 emit_int8(value & 0x1);
5665 }
5666
5667 void Assembler::vextractf64x4h(Address dst, XMMRegister src, int value) {
5668 assert(VM_Version::supports_evex(), "");
5669 assert(src != xnoreg, "sanity");
5670 InstructionMark im(this);
5671 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5672 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
5673 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5674 emit_int8(0x1B);
5675 emit_operand(src, dst);
5676 // 0x00 - extract from lower 256 bits
5677 // 0x01 - extract from upper 256 bits
5678 emit_int8(value & 0x01);
5679 }
5680
5681 void Assembler::vextractf32x4h(XMMRegister dst, XMMRegister src, int value) {
5682 assert(VM_Version::supports_avx(), "");
5683 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5684 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5685 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5686 emit_int8(0x19);
5687 emit_int8((unsigned char)(0xC0 | encode));
5688 // 0x00 - extract from bits 127:0
5689 // 0x01 - extract from bits 255:128
5690 // 0x02 - extract from bits 383:256
5691 // 0x03 - extract from bits 511:384
5692 emit_int8(value & 0x3);
5693 }
5694
5695 void Assembler::vextractf32x4h(Address dst, XMMRegister src, int value) {
5696 assert(VM_Version::supports_evex(), "");
5697 assert(src != xnoreg, "sanity");
5698 InstructionMark im(this);
5699 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5700 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5701 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5702 emit_int8(0x19);
5703 emit_operand(src, dst);
5704 // 0x00 - extract from bits 127:0
5705 // 0x01 - extract from bits 255:128
5706 // 0x02 - extract from bits 383:256
5707 // 0x03 - extract from bits 511:384
5708 emit_int8(value & 0x3);
5709 }
5710
5711 void Assembler::vextractf64x2h(XMMRegister dst, XMMRegister src, int value) {
5712 assert(VM_Version::supports_evex(), "");
5713 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5714 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5715 emit_int8(0x19);
5716 emit_int8((unsigned char)(0xC0 | encode));
5717 // 0x01 - extract from bits 255:128
5718 // 0x02 - extract from bits 383:256
5719 // 0x03 - extract from bits 511:384
5720 emit_int8(value & 0x3);
5721 }
5722
5723 // duplicate 4-bytes integer data from src into 8 locations in dest
5724 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5725 assert(VM_Version::supports_avx2(), "");
5726 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5727 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5728 emit_int8(0x58);
5729 emit_int8((unsigned char)(0xC0 | encode));
5730 }
5731
5732 // duplicate 2-bytes integer data from src into 16 locations in dest
5733 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
5734 assert(VM_Version::supports_avx2(), "");
5735 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
5736 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5737 emit_int8(0x79);
5738 emit_int8((unsigned char)(0xC0 | encode));
5739 }
5740
5741 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5742 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5743 assert(VM_Version::supports_evex(), "");
5744 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5745 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5746 emit_int8(0x78);
5747 emit_int8((unsigned char)(0xC0 | encode));
5748 }
5749
5750 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5751 assert(VM_Version::supports_evex(), "");
5752 assert(dst != xnoreg, "sanity");
5753 InstructionMark im(this);
5754 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5755 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
5756 // swap src<->dst for encoding
5757 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5758 emit_int8(0x78);
5759 emit_operand(dst, src);
5760 }
5761
5762 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5763 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5764 assert(VM_Version::supports_evex(), "");
5765 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5766 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5767 emit_int8(0x79);
5768 emit_int8((unsigned char)(0xC0 | encode));
5769 }
5770
5771 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5772 assert(VM_Version::supports_evex(), "");
5773 assert(dst != xnoreg, "sanity");
5774 InstructionMark im(this);
5775 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5776 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
5777 // swap src<->dst for encoding
5778 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5779 emit_int8(0x79);
5780 emit_operand(dst, src);
5781 }
5782
5783 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5784 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5785 assert(VM_Version::supports_evex(), "");
5786 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5787 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5788 emit_int8(0x58);
5789 emit_int8((unsigned char)(0xC0 | encode));
5790 }
5791
5792 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5793 assert(VM_Version::supports_evex(), "");
5794 assert(dst != xnoreg, "sanity");
5795 InstructionMark im(this);
5796 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5797 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5798 // swap src<->dst for encoding
5799 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5800 emit_int8(0x58);
5801 emit_operand(dst, src);
5802 }
5803
5804 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5805 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
5806 assert(VM_Version::supports_evex(), "");
5807 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5808 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5809 emit_int8(0x59);
5810 emit_int8((unsigned char)(0xC0 | encode));
5811 }
5812
5813 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
5814 assert(VM_Version::supports_evex(), "");
5815 assert(dst != xnoreg, "sanity");
5816 InstructionMark im(this);
5817 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5818 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5819 // swap src<->dst for encoding
5820 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5821 emit_int8(0x59);
5822 emit_operand(dst, src);
5823 }
5824
5825 // duplicate single precision fp from src into 4|8|16 locations in dest : requires AVX512VL
5826 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
5827 assert(VM_Version::supports_evex(), "");
5828 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5829 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5830 emit_int8(0x18);
5831 emit_int8((unsigned char)(0xC0 | encode));
5832 }
5833
5834 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
5835 assert(VM_Version::supports_evex(), "");
5836 assert(dst != xnoreg, "sanity");
5837 InstructionMark im(this);
5838 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5840 // swap src<->dst for encoding
5841 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5842 emit_int8(0x18);
5843 emit_operand(dst, src);
5844 }
5845
5846 // duplicate double precision fp from src into 2|4|8 locations in dest : requires AVX512VL
5847 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
5848 assert(VM_Version::supports_evex(), "");
5849 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5850 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5851 emit_int8(0x19);
5852 emit_int8((unsigned char)(0xC0 | encode));
5853 }
5854
5855 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
5856 assert(VM_Version::supports_evex(), "");
5857 assert(dst != xnoreg, "sanity");
5858 InstructionMark im(this);
5859 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5860 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5861 // swap src<->dst for encoding
5862 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5863 emit_int8(0x19);
5864 emit_operand(dst, src);
5865 }
5866
5867 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5868 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
5869 assert(VM_Version::supports_evex(), "");
5870 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5871 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5872 emit_int8(0x7A);
5873 emit_int8((unsigned char)(0xC0 | encode));
5874 }
5875
5876 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5877 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
5878 assert(VM_Version::supports_evex(), "");
5879 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5880 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5881 emit_int8(0x7B);
5882 emit_int8((unsigned char)(0xC0 | encode));
5883 }
5884
5885 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5886 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
5887 assert(VM_Version::supports_evex(), "");
5888 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5889 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5890 emit_int8(0x7C);
5891 emit_int8((unsigned char)(0xC0 | encode));
5892 }
5893
5894 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5895 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
5896 assert(VM_Version::supports_evex(), "");
5897 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5898 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5899 emit_int8(0x7C);
5900 emit_int8((unsigned char)(0xC0 | encode));
5901 }
5902
5903 // Carry-Less Multiplication Quadword
5904 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
5905 assert(VM_Version::supports_clmul(), "");
5906 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5907 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5908 emit_int8(0x44);
5909 emit_int8((unsigned char)(0xC0 | encode));
5910 emit_int8((unsigned char)mask);
5911 }
5912
5913 // Carry-Less Multiplication Quadword
5914 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
5915 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
5916 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5917 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
5918 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5919 emit_int8(0x44);
5920 emit_int8((unsigned char)(0xC0 | encode));
5921 emit_int8((unsigned char)mask);
5922 }
5923
5924 void Assembler::vzeroupper() {
5925 assert(VM_Version::supports_avx(), "");
5926 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5927 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5928 emit_int8(0x77);
5929 }
5930
5931
5932 #ifndef _LP64
5933 // 32bit only pieces of the assembler
5934
5935 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
5936 // NO PREFIX AS NEVER 64BIT
5937 InstructionMark im(this);
5938 emit_int8((unsigned char)0x81);
5939 emit_int8((unsigned char)(0xF8 | src1->encoding()));
5940 emit_data(imm32, rspec, 0);
5941 }
5942
5943 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
5944 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
5945 InstructionMark im(this);
5946 emit_int8((unsigned char)0x81);
5947 emit_operand(rdi, src1);
5948 emit_data(imm32, rspec, 0);
5949 }
5950
5951 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
5952 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
5953 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
5954 void Assembler::cmpxchg8(Address adr) {
5955 InstructionMark im(this);
5956 emit_int8(0x0F);
5957 emit_int8((unsigned char)0xC7);
5958 emit_operand(rcx, adr);
5959 }
5960
5961 void Assembler::decl(Register dst) {
5962 // Don't use it directly. Use MacroAssembler::decrementl() instead.
5963 emit_int8(0x48 | dst->encoding());
5964 }
5965
5966 #endif // _LP64
5967
5968 // 64bit typically doesn't use the x87 but needs to for the trig funcs
5969
5970 void Assembler::fabs() {
5971 emit_int8((unsigned char)0xD9);
5972 emit_int8((unsigned char)0xE1);
5973 }
5974
5975 void Assembler::fadd(int i) {
5976 emit_farith(0xD8, 0xC0, i);
5977 }
5978
5979 void Assembler::fadd_d(Address src) {
5980 InstructionMark im(this);
5981 emit_int8((unsigned char)0xDC);
5982 emit_operand32(rax, src);
5983 }
5984
5985 void Assembler::fadd_s(Address src) {
5986 InstructionMark im(this);
5987 emit_int8((unsigned char)0xD8);
5988 emit_operand32(rax, src);
5989 }
5990
5991 void Assembler::fadda(int i) {
5992 emit_farith(0xDC, 0xC0, i);
5993 }
5994
5995 void Assembler::faddp(int i) {
5996 emit_farith(0xDE, 0xC0, i);
5997 }
5998
5999 void Assembler::fchs() {
6000 emit_int8((unsigned char)0xD9);
6001 emit_int8((unsigned char)0xE0);
6002 }
6003
6004 void Assembler::fcom(int i) {
6005 emit_farith(0xD8, 0xD0, i);
6006 }
6007
6008 void Assembler::fcomp(int i) {
6009 emit_farith(0xD8, 0xD8, i);
6010 }
6011
6012 void Assembler::fcomp_d(Address src) {
6013 InstructionMark im(this);
6014 emit_int8((unsigned char)0xDC);
6015 emit_operand32(rbx, src);
6016 }
6017
6018 void Assembler::fcomp_s(Address src) {
6019 InstructionMark im(this);
6020 emit_int8((unsigned char)0xD8);
6021 emit_operand32(rbx, src);
6022 }
6023
6024 void Assembler::fcompp() {
6025 emit_int8((unsigned char)0xDE);
6026 emit_int8((unsigned char)0xD9);
6027 }
6028
6029 void Assembler::fcos() {
6030 emit_int8((unsigned char)0xD9);
6031 emit_int8((unsigned char)0xFF);
6032 }
6033
6034 void Assembler::fdecstp() {
6035 emit_int8((unsigned char)0xD9);
6036 emit_int8((unsigned char)0xF6);
6037 }
6038
6039 void Assembler::fdiv(int i) {
6040 emit_farith(0xD8, 0xF0, i);
6041 }
6042
6043 void Assembler::fdiv_d(Address src) {
6044 InstructionMark im(this);
6045 emit_int8((unsigned char)0xDC);
6046 emit_operand32(rsi, src);
6047 }
6048
6049 void Assembler::fdiv_s(Address src) {
6050 InstructionMark im(this);
6051 emit_int8((unsigned char)0xD8);
6052 emit_operand32(rsi, src);
6053 }
6054
6055 void Assembler::fdiva(int i) {
6056 emit_farith(0xDC, 0xF8, i);
6057 }
6058
6059 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6060 // is erroneous for some of the floating-point instructions below.
6061
6062 void Assembler::fdivp(int i) {
6063 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6064 }
6065
6066 void Assembler::fdivr(int i) {
6067 emit_farith(0xD8, 0xF8, i);
6068 }
6069
6070 void Assembler::fdivr_d(Address src) {
6071 InstructionMark im(this);
6072 emit_int8((unsigned char)0xDC);
6073 emit_operand32(rdi, src);
6074 }
6075
6076 void Assembler::fdivr_s(Address src) {
6077 InstructionMark im(this);
6078 emit_int8((unsigned char)0xD8);
6079 emit_operand32(rdi, src);
6080 }
6081
6082 void Assembler::fdivra(int i) {
6083 emit_farith(0xDC, 0xF0, i);
6084 }
6085
6086 void Assembler::fdivrp(int i) {
6087 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6088 }
6089
6090 void Assembler::ffree(int i) {
6091 emit_farith(0xDD, 0xC0, i);
6092 }
6093
6094 void Assembler::fild_d(Address adr) {
6095 InstructionMark im(this);
6096 emit_int8((unsigned char)0xDF);
6097 emit_operand32(rbp, adr);
6098 }
6099
6100 void Assembler::fild_s(Address adr) {
6101 InstructionMark im(this);
6102 emit_int8((unsigned char)0xDB);
6103 emit_operand32(rax, adr);
6104 }
6105
6106 void Assembler::fincstp() {
6107 emit_int8((unsigned char)0xD9);
6108 emit_int8((unsigned char)0xF7);
6109 }
6110
6111 void Assembler::finit() {
6112 emit_int8((unsigned char)0x9B);
6113 emit_int8((unsigned char)0xDB);
6114 emit_int8((unsigned char)0xE3);
6115 }
6116
6117 void Assembler::fist_s(Address adr) {
6118 InstructionMark im(this);
6119 emit_int8((unsigned char)0xDB);
6120 emit_operand32(rdx, adr);
6121 }
6122
6123 void Assembler::fistp_d(Address adr) {
6124 InstructionMark im(this);
6125 emit_int8((unsigned char)0xDF);
6126 emit_operand32(rdi, adr);
6127 }
6128
6129 void Assembler::fistp_s(Address adr) {
6130 InstructionMark im(this);
6131 emit_int8((unsigned char)0xDB);
6132 emit_operand32(rbx, adr);
6133 }
6134
6135 void Assembler::fld1() {
6136 emit_int8((unsigned char)0xD9);
6137 emit_int8((unsigned char)0xE8);
6138 }
6139
6140 void Assembler::fld_d(Address adr) {
6141 InstructionMark im(this);
6142 emit_int8((unsigned char)0xDD);
6143 emit_operand32(rax, adr);
6144 }
6145
6146 void Assembler::fld_s(Address adr) {
6147 InstructionMark im(this);
6148 emit_int8((unsigned char)0xD9);
6149 emit_operand32(rax, adr);
6150 }
6151
6152
6153 void Assembler::fld_s(int index) {
6154 emit_farith(0xD9, 0xC0, index);
6155 }
6156
6157 void Assembler::fld_x(Address adr) {
6158 InstructionMark im(this);
6159 emit_int8((unsigned char)0xDB);
6160 emit_operand32(rbp, adr);
6161 }
6162
6163 void Assembler::fldcw(Address src) {
6164 InstructionMark im(this);
6165 emit_int8((unsigned char)0xD9);
6166 emit_operand32(rbp, src);
6167 }
6168
6169 void Assembler::fldenv(Address src) {
6170 InstructionMark im(this);
6171 emit_int8((unsigned char)0xD9);
6172 emit_operand32(rsp, src);
6173 }
6174
6175 void Assembler::fldlg2() {
6176 emit_int8((unsigned char)0xD9);
6177 emit_int8((unsigned char)0xEC);
6178 }
6179
6180 void Assembler::fldln2() {
6181 emit_int8((unsigned char)0xD9);
6182 emit_int8((unsigned char)0xED);
6183 }
6184
6185 void Assembler::fldz() {
6186 emit_int8((unsigned char)0xD9);
6187 emit_int8((unsigned char)0xEE);
6188 }
6189
6190 void Assembler::flog() {
6191 fldln2();
6192 fxch();
6193 fyl2x();
6194 }
6195
6196 void Assembler::flog10() {
6197 fldlg2();
6198 fxch();
6199 fyl2x();
6200 }
6201
6202 void Assembler::fmul(int i) {
6203 emit_farith(0xD8, 0xC8, i);
6204 }
6205
6206 void Assembler::fmul_d(Address src) {
6207 InstructionMark im(this);
6208 emit_int8((unsigned char)0xDC);
6209 emit_operand32(rcx, src);
6210 }
6211
6212 void Assembler::fmul_s(Address src) {
6213 InstructionMark im(this);
6214 emit_int8((unsigned char)0xD8);
6215 emit_operand32(rcx, src);
6216 }
6217
6218 void Assembler::fmula(int i) {
6219 emit_farith(0xDC, 0xC8, i);
6220 }
6221
6222 void Assembler::fmulp(int i) {
6223 emit_farith(0xDE, 0xC8, i);
6224 }
6225
6226 void Assembler::fnsave(Address dst) {
6227 InstructionMark im(this);
6228 emit_int8((unsigned char)0xDD);
6229 emit_operand32(rsi, dst);
6230 }
6231
6232 void Assembler::fnstcw(Address src) {
6233 InstructionMark im(this);
6234 emit_int8((unsigned char)0x9B);
6235 emit_int8((unsigned char)0xD9);
6236 emit_operand32(rdi, src);
6237 }
6238
6239 void Assembler::fnstsw_ax() {
6240 emit_int8((unsigned char)0xDF);
6241 emit_int8((unsigned char)0xE0);
6242 }
6243
6244 void Assembler::fprem() {
6245 emit_int8((unsigned char)0xD9);
6246 emit_int8((unsigned char)0xF8);
6247 }
6248
6249 void Assembler::fprem1() {
6250 emit_int8((unsigned char)0xD9);
6251 emit_int8((unsigned char)0xF5);
6252 }
6253
6254 void Assembler::frstor(Address src) {
6255 InstructionMark im(this);
6256 emit_int8((unsigned char)0xDD);
6257 emit_operand32(rsp, src);
6258 }
6259
6260 void Assembler::fsin() {
6261 emit_int8((unsigned char)0xD9);
6262 emit_int8((unsigned char)0xFE);
6263 }
6264
6265 void Assembler::fsqrt() {
6266 emit_int8((unsigned char)0xD9);
6267 emit_int8((unsigned char)0xFA);
6268 }
6269
6270 void Assembler::fst_d(Address adr) {
6271 InstructionMark im(this);
6272 emit_int8((unsigned char)0xDD);
6273 emit_operand32(rdx, adr);
6274 }
6275
6276 void Assembler::fst_s(Address adr) {
6277 InstructionMark im(this);
6278 emit_int8((unsigned char)0xD9);
6279 emit_operand32(rdx, adr);
6280 }
6281
6282 void Assembler::fstp_d(Address adr) {
6283 InstructionMark im(this);
6284 emit_int8((unsigned char)0xDD);
6285 emit_operand32(rbx, adr);
6286 }
6287
6288 void Assembler::fstp_d(int index) {
6289 emit_farith(0xDD, 0xD8, index);
6290 }
6291
6292 void Assembler::fstp_s(Address adr) {
6293 InstructionMark im(this);
6294 emit_int8((unsigned char)0xD9);
6295 emit_operand32(rbx, adr);
6296 }
6297
6298 void Assembler::fstp_x(Address adr) {
6299 InstructionMark im(this);
6300 emit_int8((unsigned char)0xDB);
6301 emit_operand32(rdi, adr);
6302 }
6303
6304 void Assembler::fsub(int i) {
6305 emit_farith(0xD8, 0xE0, i);
6306 }
6307
6308 void Assembler::fsub_d(Address src) {
6309 InstructionMark im(this);
6310 emit_int8((unsigned char)0xDC);
6311 emit_operand32(rsp, src);
6312 }
6313
6314 void Assembler::fsub_s(Address src) {
6315 InstructionMark im(this);
6316 emit_int8((unsigned char)0xD8);
6317 emit_operand32(rsp, src);
6318 }
6319
6320 void Assembler::fsuba(int i) {
6321 emit_farith(0xDC, 0xE8, i);
6322 }
6323
6324 void Assembler::fsubp(int i) {
6325 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6326 }
6327
6328 void Assembler::fsubr(int i) {
6329 emit_farith(0xD8, 0xE8, i);
6330 }
6331
6332 void Assembler::fsubr_d(Address src) {
6333 InstructionMark im(this);
6334 emit_int8((unsigned char)0xDC);
6335 emit_operand32(rbp, src);
6336 }
6337
6338 void Assembler::fsubr_s(Address src) {
6339 InstructionMark im(this);
6340 emit_int8((unsigned char)0xD8);
6341 emit_operand32(rbp, src);
6342 }
6343
6344 void Assembler::fsubra(int i) {
6345 emit_farith(0xDC, 0xE0, i);
6346 }
6347
6348 void Assembler::fsubrp(int i) {
6349 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6350 }
6351
6352 void Assembler::ftan() {
6353 emit_int8((unsigned char)0xD9);
6354 emit_int8((unsigned char)0xF2);
6355 emit_int8((unsigned char)0xDD);
6356 emit_int8((unsigned char)0xD8);
6357 }
6358
6359 void Assembler::ftst() {
6360 emit_int8((unsigned char)0xD9);
6361 emit_int8((unsigned char)0xE4);
6362 }
6363
6364 void Assembler::fucomi(int i) {
6365 // make sure the instruction is supported (introduced for P6, together with cmov)
6366 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6367 emit_farith(0xDB, 0xE8, i);
6368 }
6369
6370 void Assembler::fucomip(int i) {
6371 // make sure the instruction is supported (introduced for P6, together with cmov)
6372 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6373 emit_farith(0xDF, 0xE8, i);
6374 }
6375
6376 void Assembler::fwait() {
6377 emit_int8((unsigned char)0x9B);
6378 }
6379
6380 void Assembler::fxch(int i) {
6381 emit_farith(0xD9, 0xC8, i);
6382 }
6383
6384 void Assembler::fyl2x() {
6385 emit_int8((unsigned char)0xD9);
6386 emit_int8((unsigned char)0xF1);
6387 }
6388
6389 void Assembler::frndint() {
6390 emit_int8((unsigned char)0xD9);
6391 emit_int8((unsigned char)0xFC);
6392 }
6393
6394 void Assembler::f2xm1() {
6395 emit_int8((unsigned char)0xD9);
6396 emit_int8((unsigned char)0xF0);
6397 }
6398
6399 void Assembler::fldl2e() {
6400 emit_int8((unsigned char)0xD9);
6401 emit_int8((unsigned char)0xEA);
6402 }
6403
6404 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6405 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6406 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6407 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6408
6409 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6410 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6411 if (pre > 0) {
6412 emit_int8(simd_pre[pre]);
6413 }
6414 if (rex_w) {
6415 prefixq(adr, xreg);
6416 } else {
6417 prefix(adr, xreg);
6418 }
6419 if (opc > 0) {
6420 emit_int8(0x0F);
6421 int opc2 = simd_opc[opc];
6422 if (opc2 > 0) {
6423 emit_int8(opc2);
6424 }
6425 }
6426 }
6427
6428 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6429 if (pre > 0) {
6430 emit_int8(simd_pre[pre]);
6431 }
6432 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6433 if (opc > 0) {
6434 emit_int8(0x0F);
6435 int opc2 = simd_opc[opc];
6436 if (opc2 > 0) {
6437 emit_int8(opc2);
6438 }
6439 }
6440 return encode;
6441 }
6442
6443
6444 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6445 int vector_len = _attributes->get_vector_len();
6446 bool vex_w = _attributes->is_rex_vex_w();
6447 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6448 prefix(VEX_3bytes);
6449
6450 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6451 byte1 = (~byte1) & 0xE0;
6452 byte1 |= opc;
6453 emit_int8(byte1);
6454
6455 int byte2 = ((~nds_enc) & 0xf) << 3;
6456 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6457 emit_int8(byte2);
6458 } else {
6459 prefix(VEX_2bytes);
6460
6461 int byte1 = vex_r ? VEX_R : 0;
6462 byte1 = (~byte1) & 0x80;
6463 byte1 |= ((~nds_enc) & 0xf) << 3;
6464 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6465 emit_int8(byte1);
6466 }
6467 }
6468
6469 // This is a 4 byte encoding
6470 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6471 // EVEX 0x62 prefix
6472 prefix(EVEX_4bytes);
6473 bool vex_w = _attributes->is_rex_vex_w();
6474 int evex_encoding = (vex_w ? VEX_W : 0);
6475 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6476 _attributes->set_evex_encoding(evex_encoding);
6477
6478 // P0: byte 2, initialized to RXBR`00mm
6479 // instead of not'd
6480 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6481 byte2 = (~byte2) & 0xF0;
6482 // confine opc opcode extensions in mm bits to lower two bits
6483 // of form {0F, 0F_38, 0F_3A}
6484 byte2 |= opc;
6485 emit_int8(byte2);
6486
6487 // P1: byte 3 as Wvvvv1pp
6488 int byte3 = ((~nds_enc) & 0xf) << 3;
6489 // p[10] is always 1
6490 byte3 |= EVEX_F;
6491 byte3 |= (vex_w & 1) << 7;
6492 // confine pre opcode extensions in pp bits to lower two bits
6493 // of form {66, F3, F2}
6494 byte3 |= pre;
6495 emit_int8(byte3);
6496
6497 // P2: byte 4 as zL'Lbv'aaa
6498 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6499 // EVEX.v` for extending EVEX.vvvv or VIDX
6500 byte4 |= (evex_v ? 0: EVEX_V);
6501 // third EXEC.b for broadcast actions
6502 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6503 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6504 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6505 // last is EVEX.z for zero/merge actions
6506 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6507 emit_int8(byte4);
6508 }
6509
6510 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6511 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6512 bool vex_b = adr.base_needs_rex();
6513 bool vex_x = adr.index_needs_rex();
6514 set_attributes(attributes);
6515 attributes->set_current_assembler(this);
6516
6517 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6518 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6519 switch (attributes->get_vector_len()) {
6520 case AVX_128bit:
6521 case AVX_256bit:
6522 attributes->set_is_legacy_mode();
6523 break;
6524 }
6525 }
6526
6527 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6528 {
6529 bool evex_r = (xreg_enc >= 16);
6530 bool evex_v = (nds_enc >= 16);
6531 attributes->set_is_evex_instruction();
6532 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6533 } else {
6534 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6535 }
6536 }
6537
6538 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6539 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6540 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6541 bool vex_x = false;
6542 set_attributes(attributes);
6543 attributes->set_current_assembler(this);
6544
6545 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6546 if ((UseAVX > 2) && _legacy_mode_vl && attributes->uses_vl()) {
6547 switch (attributes->get_vector_len()) {
6548 case AVX_128bit:
6549 case AVX_256bit:
6550 if ((dst_enc >= 16) | (nds_enc >= 16) | (src_enc >= 16)) {
6551 // up propagate arithmetic instructions to meet RA requirements
6552 attributes->set_vector_len(AVX_512bit);
6553 } else {
6554 attributes->set_is_legacy_mode();
6555 }
6556 break;
6557 }
6558 }
6559
6560 if ((UseAVX > 2) && !attributes->is_legacy_mode())
6561 {
6562 bool evex_r = (dst_enc >= 16);
6563 bool evex_v = (nds_enc >= 16);
6564 // can use vex_x as bank extender on rm encoding
6565 vex_x = (src_enc >= 16);
6566 attributes->set_is_evex_instruction();
6567 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6568 } else {
6569 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6570 }
6571
6572 // return modrm byte components for operands
6573 return (((dst_enc & 7) << 3) | (src_enc & 7));
6574 }
6575
6576
6577 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6578 VexOpcode opc, InstructionAttr *attributes) {
6579 if (UseAVX > 0) {
6580 int xreg_enc = xreg->encoding();
6581 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6582 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6583 } else {
6584 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6585 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6586 }
6587 }
6588
6589 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6590 VexOpcode opc, InstructionAttr *attributes) {
6591 int dst_enc = dst->encoding();
6592 int src_enc = src->encoding();
6593 if (UseAVX > 0) {
6594 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6595 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6596 } else {
6597 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6598 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6599 }
6600 }
6601
6602 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, KRegister src, VexSimdPrefix pre,
6603 VexOpcode opc, InstructionAttr *attributes) {
6604 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6605 return vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), pre, opc, attributes);
6606 }
6607
6608 int Assembler::kreg_prefix_and_encode(KRegister dst, KRegister nds, Register src, VexSimdPrefix pre,
6609 VexOpcode opc, InstructionAttr *attributes) {
6610 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6611 return vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), pre, opc, attributes);
6612 }
6613
6614 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6615 assert(VM_Version::supports_avx(), "");
6616 assert(!VM_Version::supports_evex(), "");
6617 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6618 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6619 emit_int8((unsigned char)0xC2);
6620 emit_int8((unsigned char)(0xC0 | encode));
6621 emit_int8((unsigned char)(0xF & cop));
6622 }
6623
6624 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6625 assert(VM_Version::supports_avx(), "");
6626 assert(!VM_Version::supports_evex(), "");
6627 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6628 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6629 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6630 emit_int8((unsigned char)0x4B);
6631 emit_int8((unsigned char)(0xC0 | encode));
6632 int src2_enc = src2->encoding();
6633 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6634 }
6635
6636
6637 #ifndef _LP64
6638
6639 void Assembler::incl(Register dst) {
6640 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6641 emit_int8(0x40 | dst->encoding());
6642 }
6643
6644 void Assembler::lea(Register dst, Address src) {
6645 leal(dst, src);
6646 }
6647
6648 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6649 InstructionMark im(this);
6650 emit_int8((unsigned char)0xC7);
6651 emit_operand(rax, dst);
6652 emit_data((int)imm32, rspec, 0);
6653 }
6654
6655 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6656 InstructionMark im(this);
6657 int encode = prefix_and_encode(dst->encoding());
6658 emit_int8((unsigned char)(0xB8 | encode));
6659 emit_data((int)imm32, rspec, 0);
6660 }
6661
6662 void Assembler::popa() { // 32bit
6663 emit_int8(0x61);
6664 }
6665
6666 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
6667 InstructionMark im(this);
6668 emit_int8(0x68);
6669 emit_data(imm32, rspec, 0);
6670 }
6671
6672 void Assembler::pusha() { // 32bit
6673 emit_int8(0x60);
6674 }
6675
6676 void Assembler::set_byte_if_not_zero(Register dst) {
6677 emit_int8(0x0F);
6678 emit_int8((unsigned char)0x95);
6679 emit_int8((unsigned char)(0xE0 | dst->encoding()));
6680 }
6681
6682 void Assembler::shldl(Register dst, Register src) {
6683 emit_int8(0x0F);
6684 emit_int8((unsigned char)0xA5);
6685 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6686 }
6687
6688 // 0F A4 / r ib
6689 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6690 emit_int8(0x0F);
6691 emit_int8((unsigned char)0xA4);
6692 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6693 emit_int8(imm8);
6694 }
6695
6696 void Assembler::shrdl(Register dst, Register src) {
6697 emit_int8(0x0F);
6698 emit_int8((unsigned char)0xAD);
6699 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
6700 }
6701
6702 #else // LP64
6703
6704 void Assembler::set_byte_if_not_zero(Register dst) {
6705 int enc = prefix_and_encode(dst->encoding(), true);
6706 emit_int8(0x0F);
6707 emit_int8((unsigned char)0x95);
6708 emit_int8((unsigned char)(0xE0 | enc));
6709 }
6710
6711 // 64bit only pieces of the assembler
6712 // This should only be used by 64bit instructions that can use rip-relative
6713 // it cannot be used by instructions that want an immediate value.
6714
6715 bool Assembler::reachable(AddressLiteral adr) {
6716 int64_t disp;
6717 // None will force a 64bit literal to the code stream. Likely a placeholder
6718 // for something that will be patched later and we need to certain it will
6719 // always be reachable.
6720 if (adr.reloc() == relocInfo::none) {
6721 return false;
6722 }
6723 if (adr.reloc() == relocInfo::internal_word_type) {
6724 // This should be rip relative and easily reachable.
6725 return true;
6726 }
6727 if (adr.reloc() == relocInfo::virtual_call_type ||
6728 adr.reloc() == relocInfo::opt_virtual_call_type ||
6729 adr.reloc() == relocInfo::static_call_type ||
6730 adr.reloc() == relocInfo::static_stub_type ) {
6731 // This should be rip relative within the code cache and easily
6732 // reachable until we get huge code caches. (At which point
6733 // ic code is going to have issues).
6734 return true;
6735 }
6736 if (adr.reloc() != relocInfo::external_word_type &&
6737 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
6738 adr.reloc() != relocInfo::poll_type && // relocs to identify them
6739 adr.reloc() != relocInfo::runtime_call_type ) {
6740 return false;
6741 }
6742
6743 // Stress the correction code
6744 if (ForceUnreachable) {
6745 // Must be runtimecall reloc, see if it is in the codecache
6746 // Flipping stuff in the codecache to be unreachable causes issues
6747 // with things like inline caches where the additional instructions
6748 // are not handled.
6749 if (CodeCache::find_blob(adr._target) == NULL) {
6750 return false;
6751 }
6752 }
6753 // For external_word_type/runtime_call_type if it is reachable from where we
6754 // are now (possibly a temp buffer) and where we might end up
6755 // anywhere in the codeCache then we are always reachable.
6756 // This would have to change if we ever save/restore shared code
6757 // to be more pessimistic.
6758 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
6759 if (!is_simm32(disp)) return false;
6760 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
6761 if (!is_simm32(disp)) return false;
6762
6763 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
6764
6765 // Because rip relative is a disp + address_of_next_instruction and we
6766 // don't know the value of address_of_next_instruction we apply a fudge factor
6767 // to make sure we will be ok no matter the size of the instruction we get placed into.
6768 // We don't have to fudge the checks above here because they are already worst case.
6769
6770 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
6771 // + 4 because better safe than sorry.
6772 const int fudge = 12 + 4;
6773 if (disp < 0) {
6774 disp -= fudge;
6775 } else {
6776 disp += fudge;
6777 }
6778 return is_simm32(disp);
6779 }
6780
6781 // Check if the polling page is not reachable from the code cache using rip-relative
6782 // addressing.
6783 bool Assembler::is_polling_page_far() {
6784 intptr_t addr = (intptr_t)os::get_polling_page();
6785 return ForceUnreachable ||
6786 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
6787 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
6788 }
6789
6790 void Assembler::emit_data64(jlong data,
6791 relocInfo::relocType rtype,
6792 int format) {
6793 if (rtype == relocInfo::none) {
6794 emit_int64(data);
6795 } else {
6796 emit_data64(data, Relocation::spec_simple(rtype), format);
6797 }
6798 }
6799
6800 void Assembler::emit_data64(jlong data,
6801 RelocationHolder const& rspec,
6802 int format) {
6803 assert(imm_operand == 0, "default format must be immediate in this file");
6804 assert(imm_operand == format, "must be immediate");
6805 assert(inst_mark() != NULL, "must be inside InstructionMark");
6806 // Do not use AbstractAssembler::relocate, which is not intended for
6807 // embedded words. Instead, relocate to the enclosing instruction.
6808 code_section()->relocate(inst_mark(), rspec, format);
6809 #ifdef ASSERT
6810 check_relocation(rspec, format);
6811 #endif
6812 emit_int64(data);
6813 }
6814
6815 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
6816 if (reg_enc >= 8) {
6817 prefix(REX_B);
6818 reg_enc -= 8;
6819 } else if (byteinst && reg_enc >= 4) {
6820 prefix(REX);
6821 }
6822 return reg_enc;
6823 }
6824
6825 int Assembler::prefixq_and_encode(int reg_enc) {
6826 if (reg_enc < 8) {
6827 prefix(REX_W);
6828 } else {
6829 prefix(REX_WB);
6830 reg_enc -= 8;
6831 }
6832 return reg_enc;
6833 }
6834
6835 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
6836 if (dst_enc < 8) {
6837 if (src_enc >= 8) {
6838 prefix(REX_B);
6839 src_enc -= 8;
6840 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
6841 prefix(REX);
6842 }
6843 } else {
6844 if (src_enc < 8) {
6845 prefix(REX_R);
6846 } else {
6847 prefix(REX_RB);
6848 src_enc -= 8;
6849 }
6850 dst_enc -= 8;
6851 }
6852 return dst_enc << 3 | src_enc;
6853 }
6854
6855 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
6856 if (dst_enc < 8) {
6857 if (src_enc < 8) {
6858 prefix(REX_W);
6859 } else {
6860 prefix(REX_WB);
6861 src_enc -= 8;
6862 }
6863 } else {
6864 if (src_enc < 8) {
6865 prefix(REX_WR);
6866 } else {
6867 prefix(REX_WRB);
6868 src_enc -= 8;
6869 }
6870 dst_enc -= 8;
6871 }
6872 return dst_enc << 3 | src_enc;
6873 }
6874
6875 void Assembler::prefix(Register reg) {
6876 if (reg->encoding() >= 8) {
6877 prefix(REX_B);
6878 }
6879 }
6880
6881 void Assembler::prefix(Register dst, Register src, Prefix p) {
6882 if (src->encoding() >= 8) {
6883 p = (Prefix)(p | REX_B);
6884 }
6885 if (dst->encoding() >= 8) {
6886 p = (Prefix)( p | REX_R);
6887 }
6888 if (p != Prefix_EMPTY) {
6889 // do not generate an empty prefix
6890 prefix(p);
6891 }
6892 }
6893
6894 void Assembler::prefix(Register dst, Address adr, Prefix p) {
6895 if (adr.base_needs_rex()) {
6896 if (adr.index_needs_rex()) {
6897 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6898 } else {
6899 prefix(REX_B);
6900 }
6901 } else {
6902 if (adr.index_needs_rex()) {
6903 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
6904 }
6905 }
6906 if (dst->encoding() >= 8) {
6907 p = (Prefix)(p | REX_R);
6908 }
6909 if (p != Prefix_EMPTY) {
6910 // do not generate an empty prefix
6911 prefix(p);
6912 }
6913 }
6914
6915 void Assembler::prefix(Address adr) {
6916 if (adr.base_needs_rex()) {
6917 if (adr.index_needs_rex()) {
6918 prefix(REX_XB);
6919 } else {
6920 prefix(REX_B);
6921 }
6922 } else {
6923 if (adr.index_needs_rex()) {
6924 prefix(REX_X);
6925 }
6926 }
6927 }
6928
6929 void Assembler::prefixq(Address adr) {
6930 if (adr.base_needs_rex()) {
6931 if (adr.index_needs_rex()) {
6932 prefix(REX_WXB);
6933 } else {
6934 prefix(REX_WB);
6935 }
6936 } else {
6937 if (adr.index_needs_rex()) {
6938 prefix(REX_WX);
6939 } else {
6940 prefix(REX_W);
6941 }
6942 }
6943 }
6944
6945
6946 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
6947 if (reg->encoding() < 8) {
6948 if (adr.base_needs_rex()) {
6949 if (adr.index_needs_rex()) {
6950 prefix(REX_XB);
6951 } else {
6952 prefix(REX_B);
6953 }
6954 } else {
6955 if (adr.index_needs_rex()) {
6956 prefix(REX_X);
6957 } else if (byteinst && reg->encoding() >= 4 ) {
6958 prefix(REX);
6959 }
6960 }
6961 } else {
6962 if (adr.base_needs_rex()) {
6963 if (adr.index_needs_rex()) {
6964 prefix(REX_RXB);
6965 } else {
6966 prefix(REX_RB);
6967 }
6968 } else {
6969 if (adr.index_needs_rex()) {
6970 prefix(REX_RX);
6971 } else {
6972 prefix(REX_R);
6973 }
6974 }
6975 }
6976 }
6977
6978 void Assembler::prefixq(Address adr, Register src) {
6979 if (src->encoding() < 8) {
6980 if (adr.base_needs_rex()) {
6981 if (adr.index_needs_rex()) {
6982 prefix(REX_WXB);
6983 } else {
6984 prefix(REX_WB);
6985 }
6986 } else {
6987 if (adr.index_needs_rex()) {
6988 prefix(REX_WX);
6989 } else {
6990 prefix(REX_W);
6991 }
6992 }
6993 } else {
6994 if (adr.base_needs_rex()) {
6995 if (adr.index_needs_rex()) {
6996 prefix(REX_WRXB);
6997 } else {
6998 prefix(REX_WRB);
6999 }
7000 } else {
7001 if (adr.index_needs_rex()) {
7002 prefix(REX_WRX);
7003 } else {
7004 prefix(REX_WR);
7005 }
7006 }
7007 }
7008 }
7009
7010 void Assembler::prefix(Address adr, XMMRegister reg) {
7011 if (reg->encoding() < 8) {
7012 if (adr.base_needs_rex()) {
7013 if (adr.index_needs_rex()) {
7014 prefix(REX_XB);
7015 } else {
7016 prefix(REX_B);
7017 }
7018 } else {
7019 if (adr.index_needs_rex()) {
7020 prefix(REX_X);
7021 }
7022 }
7023 } else {
7024 if (adr.base_needs_rex()) {
7025 if (adr.index_needs_rex()) {
7026 prefix(REX_RXB);
7027 } else {
7028 prefix(REX_RB);
7029 }
7030 } else {
7031 if (adr.index_needs_rex()) {
7032 prefix(REX_RX);
7033 } else {
7034 prefix(REX_R);
7035 }
7036 }
7037 }
7038 }
7039
7040 void Assembler::prefixq(Address adr, XMMRegister src) {
7041 if (src->encoding() < 8) {
7042 if (adr.base_needs_rex()) {
7043 if (adr.index_needs_rex()) {
7044 prefix(REX_WXB);
7045 } else {
7046 prefix(REX_WB);
7047 }
7048 } else {
7049 if (adr.index_needs_rex()) {
7050 prefix(REX_WX);
7051 } else {
7052 prefix(REX_W);
7053 }
7054 }
7055 } else {
7056 if (adr.base_needs_rex()) {
7057 if (adr.index_needs_rex()) {
7058 prefix(REX_WRXB);
7059 } else {
7060 prefix(REX_WRB);
7061 }
7062 } else {
7063 if (adr.index_needs_rex()) {
7064 prefix(REX_WRX);
7065 } else {
7066 prefix(REX_WR);
7067 }
7068 }
7069 }
7070 }
7071
7072 void Assembler::adcq(Register dst, int32_t imm32) {
7073 (void) prefixq_and_encode(dst->encoding());
7074 emit_arith(0x81, 0xD0, dst, imm32);
7075 }
7076
7077 void Assembler::adcq(Register dst, Address src) {
7078 InstructionMark im(this);
7079 prefixq(src, dst);
7080 emit_int8(0x13);
7081 emit_operand(dst, src);
7082 }
7083
7084 void Assembler::adcq(Register dst, Register src) {
7085 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7086 emit_arith(0x13, 0xC0, dst, src);
7087 }
7088
7089 void Assembler::addq(Address dst, int32_t imm32) {
7090 InstructionMark im(this);
7091 prefixq(dst);
7092 emit_arith_operand(0x81, rax, dst,imm32);
7093 }
7094
7095 void Assembler::addq(Address dst, Register src) {
7096 InstructionMark im(this);
7097 prefixq(dst, src);
7098 emit_int8(0x01);
7099 emit_operand(src, dst);
7100 }
7101
7102 void Assembler::addq(Register dst, int32_t imm32) {
7103 (void) prefixq_and_encode(dst->encoding());
7104 emit_arith(0x81, 0xC0, dst, imm32);
7105 }
7106
7107 void Assembler::addq(Register dst, Address src) {
7108 InstructionMark im(this);
7109 prefixq(src, dst);
7110 emit_int8(0x03);
7111 emit_operand(dst, src);
7112 }
7113
7114 void Assembler::addq(Register dst, Register src) {
7115 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7116 emit_arith(0x03, 0xC0, dst, src);
7117 }
7118
7119 void Assembler::adcxq(Register dst, Register src) {
7120 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7121 emit_int8((unsigned char)0x66);
7122 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7123 emit_int8(0x0F);
7124 emit_int8(0x38);
7125 emit_int8((unsigned char)0xF6);
7126 emit_int8((unsigned char)(0xC0 | encode));
7127 }
7128
7129 void Assembler::adoxq(Register dst, Register src) {
7130 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7131 emit_int8((unsigned char)0xF3);
7132 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7133 emit_int8(0x0F);
7134 emit_int8(0x38);
7135 emit_int8((unsigned char)0xF6);
7136 emit_int8((unsigned char)(0xC0 | encode));
7137 }
7138
7139 void Assembler::andq(Address dst, int32_t imm32) {
7140 InstructionMark im(this);
7141 prefixq(dst);
7142 emit_int8((unsigned char)0x81);
7143 emit_operand(rsp, dst, 4);
7144 emit_int32(imm32);
7145 }
7146
7147 void Assembler::andq(Register dst, int32_t imm32) {
7148 (void) prefixq_and_encode(dst->encoding());
7149 emit_arith(0x81, 0xE0, dst, imm32);
7150 }
7151
7152 void Assembler::andq(Register dst, Address src) {
7153 InstructionMark im(this);
7154 prefixq(src, dst);
7155 emit_int8(0x23);
7156 emit_operand(dst, src);
7157 }
7158
7159 void Assembler::andq(Register dst, Register src) {
7160 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7161 emit_arith(0x23, 0xC0, dst, src);
7162 }
7163
7164 void Assembler::andnq(Register dst, Register src1, Register src2) {
7165 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7166 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7167 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7168 emit_int8((unsigned char)0xF2);
7169 emit_int8((unsigned char)(0xC0 | encode));
7170 }
7171
7172 void Assembler::andnq(Register dst, Register src1, Address src2) {
7173 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7174 InstructionMark im(this);
7175 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7176 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7177 emit_int8((unsigned char)0xF2);
7178 emit_operand(dst, src2);
7179 }
7180
7181 void Assembler::bsfq(Register dst, Register src) {
7182 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7183 emit_int8(0x0F);
7184 emit_int8((unsigned char)0xBC);
7185 emit_int8((unsigned char)(0xC0 | encode));
7186 }
7187
7188 void Assembler::bsrq(Register dst, Register src) {
7189 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7190 emit_int8(0x0F);
7191 emit_int8((unsigned char)0xBD);
7192 emit_int8((unsigned char)(0xC0 | encode));
7193 }
7194
7195 void Assembler::bswapq(Register reg) {
7196 int encode = prefixq_and_encode(reg->encoding());
7197 emit_int8(0x0F);
7198 emit_int8((unsigned char)(0xC8 | encode));
7199 }
7200
7201 void Assembler::blsiq(Register dst, Register src) {
7202 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7203 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7204 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7205 emit_int8((unsigned char)0xF3);
7206 emit_int8((unsigned char)(0xC0 | encode));
7207 }
7208
7209 void Assembler::blsiq(Register dst, Address src) {
7210 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7211 InstructionMark im(this);
7212 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7213 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7214 emit_int8((unsigned char)0xF3);
7215 emit_operand(rbx, src);
7216 }
7217
7218 void Assembler::blsmskq(Register dst, Register src) {
7219 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7220 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7221 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7222 emit_int8((unsigned char)0xF3);
7223 emit_int8((unsigned char)(0xC0 | encode));
7224 }
7225
7226 void Assembler::blsmskq(Register dst, Address src) {
7227 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7228 InstructionMark im(this);
7229 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7230 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7231 emit_int8((unsigned char)0xF3);
7232 emit_operand(rdx, src);
7233 }
7234
7235 void Assembler::blsrq(Register dst, Register src) {
7236 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7237 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7238 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7239 emit_int8((unsigned char)0xF3);
7240 emit_int8((unsigned char)(0xC0 | encode));
7241 }
7242
7243 void Assembler::blsrq(Register dst, Address src) {
7244 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7245 InstructionMark im(this);
7246 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7247 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7248 emit_int8((unsigned char)0xF3);
7249 emit_operand(rcx, src);
7250 }
7251
7252 void Assembler::cdqq() {
7253 prefix(REX_W);
7254 emit_int8((unsigned char)0x99);
7255 }
7256
7257 void Assembler::clflush(Address adr) {
7258 prefix(adr);
7259 emit_int8(0x0F);
7260 emit_int8((unsigned char)0xAE);
7261 emit_operand(rdi, adr);
7262 }
7263
7264 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7265 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7266 emit_int8(0x0F);
7267 emit_int8(0x40 | cc);
7268 emit_int8((unsigned char)(0xC0 | encode));
7269 }
7270
7271 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7272 InstructionMark im(this);
7273 prefixq(src, dst);
7274 emit_int8(0x0F);
7275 emit_int8(0x40 | cc);
7276 emit_operand(dst, src);
7277 }
7278
7279 void Assembler::cmpq(Address dst, int32_t imm32) {
7280 InstructionMark im(this);
7281 prefixq(dst);
7282 emit_int8((unsigned char)0x81);
7283 emit_operand(rdi, dst, 4);
7284 emit_int32(imm32);
7285 }
7286
7287 void Assembler::cmpq(Register dst, int32_t imm32) {
7288 (void) prefixq_and_encode(dst->encoding());
7289 emit_arith(0x81, 0xF8, dst, imm32);
7290 }
7291
7292 void Assembler::cmpq(Address dst, Register src) {
7293 InstructionMark im(this);
7294 prefixq(dst, src);
7295 emit_int8(0x3B);
7296 emit_operand(src, dst);
7297 }
7298
7299 void Assembler::cmpq(Register dst, Register src) {
7300 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7301 emit_arith(0x3B, 0xC0, dst, src);
7302 }
7303
7304 void Assembler::cmpq(Register dst, Address src) {
7305 InstructionMark im(this);
7306 prefixq(src, dst);
7307 emit_int8(0x3B);
7308 emit_operand(dst, src);
7309 }
7310
7311 void Assembler::cmpxchgq(Register reg, Address adr) {
7312 InstructionMark im(this);
7313 prefixq(adr, reg);
7314 emit_int8(0x0F);
7315 emit_int8((unsigned char)0xB1);
7316 emit_operand(reg, adr);
7317 }
7318
7319 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7320 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7321 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7322 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7323 emit_int8(0x2A);
7324 emit_int8((unsigned char)(0xC0 | encode));
7325 }
7326
7327 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7329 InstructionMark im(this);
7330 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7331 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7332 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7333 emit_int8(0x2A);
7334 emit_operand(dst, src);
7335 }
7336
7337 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7338 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7339 InstructionMark im(this);
7340 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7341 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7342 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7343 emit_int8(0x2A);
7344 emit_operand(dst, src);
7345 }
7346
7347 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7348 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7349 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7350 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7351 emit_int8(0x2C);
7352 emit_int8((unsigned char)(0xC0 | encode));
7353 }
7354
7355 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7356 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7357 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7358 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7359 emit_int8(0x2C);
7360 emit_int8((unsigned char)(0xC0 | encode));
7361 }
7362
7363 void Assembler::decl(Register dst) {
7364 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7365 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7366 int encode = prefix_and_encode(dst->encoding());
7367 emit_int8((unsigned char)0xFF);
7368 emit_int8((unsigned char)(0xC8 | encode));
7369 }
7370
7371 void Assembler::decq(Register dst) {
7372 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7373 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7374 int encode = prefixq_and_encode(dst->encoding());
7375 emit_int8((unsigned char)0xFF);
7376 emit_int8(0xC8 | encode);
7377 }
7378
7379 void Assembler::decq(Address dst) {
7380 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7381 InstructionMark im(this);
7382 prefixq(dst);
7383 emit_int8((unsigned char)0xFF);
7384 emit_operand(rcx, dst);
7385 }
7386
7387 void Assembler::fxrstor(Address src) {
7388 prefixq(src);
7389 emit_int8(0x0F);
7390 emit_int8((unsigned char)0xAE);
7391 emit_operand(as_Register(1), src);
7392 }
7393
7394 void Assembler::xrstor(Address src) {
7395 prefixq(src);
7396 emit_int8(0x0F);
7397 emit_int8((unsigned char)0xAE);
7398 emit_operand(as_Register(5), src);
7399 }
7400
7401 void Assembler::fxsave(Address dst) {
7402 prefixq(dst);
7403 emit_int8(0x0F);
7404 emit_int8((unsigned char)0xAE);
7405 emit_operand(as_Register(0), dst);
7406 }
7407
7408 void Assembler::xsave(Address dst) {
7409 prefixq(dst);
7410 emit_int8(0x0F);
7411 emit_int8((unsigned char)0xAE);
7412 emit_operand(as_Register(4), dst);
7413 }
7414
7415 void Assembler::idivq(Register src) {
7416 int encode = prefixq_and_encode(src->encoding());
7417 emit_int8((unsigned char)0xF7);
7418 emit_int8((unsigned char)(0xF8 | encode));
7419 }
7420
7421 void Assembler::imulq(Register dst, Register src) {
7422 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7423 emit_int8(0x0F);
7424 emit_int8((unsigned char)0xAF);
7425 emit_int8((unsigned char)(0xC0 | encode));
7426 }
7427
7428 void Assembler::imulq(Register dst, Register src, int value) {
7429 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7430 if (is8bit(value)) {
7431 emit_int8(0x6B);
7432 emit_int8((unsigned char)(0xC0 | encode));
7433 emit_int8(value & 0xFF);
7434 } else {
7435 emit_int8(0x69);
7436 emit_int8((unsigned char)(0xC0 | encode));
7437 emit_int32(value);
7438 }
7439 }
7440
7441 void Assembler::imulq(Register dst, Address src) {
7442 InstructionMark im(this);
7443 prefixq(src, dst);
7444 emit_int8(0x0F);
7445 emit_int8((unsigned char) 0xAF);
7446 emit_operand(dst, src);
7447 }
7448
7449 void Assembler::incl(Register dst) {
7450 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7451 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7452 int encode = prefix_and_encode(dst->encoding());
7453 emit_int8((unsigned char)0xFF);
7454 emit_int8((unsigned char)(0xC0 | encode));
7455 }
7456
7457 void Assembler::incq(Register dst) {
7458 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7459 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7460 int encode = prefixq_and_encode(dst->encoding());
7461 emit_int8((unsigned char)0xFF);
7462 emit_int8((unsigned char)(0xC0 | encode));
7463 }
7464
7465 void Assembler::incq(Address dst) {
7466 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7467 InstructionMark im(this);
7468 prefixq(dst);
7469 emit_int8((unsigned char)0xFF);
7470 emit_operand(rax, dst);
7471 }
7472
7473 void Assembler::lea(Register dst, Address src) {
7474 leaq(dst, src);
7475 }
7476
7477 void Assembler::leaq(Register dst, Address src) {
7478 InstructionMark im(this);
7479 prefixq(src, dst);
7480 emit_int8((unsigned char)0x8D);
7481 emit_operand(dst, src);
7482 }
7483
7484 void Assembler::mov64(Register dst, int64_t imm64) {
7485 InstructionMark im(this);
7486 int encode = prefixq_and_encode(dst->encoding());
7487 emit_int8((unsigned char)(0xB8 | encode));
7488 emit_int64(imm64);
7489 }
7490
7491 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7492 InstructionMark im(this);
7493 int encode = prefixq_and_encode(dst->encoding());
7494 emit_int8(0xB8 | encode);
7495 emit_data64(imm64, rspec);
7496 }
7497
7498 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7499 InstructionMark im(this);
7500 int encode = prefix_and_encode(dst->encoding());
7501 emit_int8((unsigned char)(0xB8 | encode));
7502 emit_data((int)imm32, rspec, narrow_oop_operand);
7503 }
7504
7505 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7506 InstructionMark im(this);
7507 prefix(dst);
7508 emit_int8((unsigned char)0xC7);
7509 emit_operand(rax, dst, 4);
7510 emit_data((int)imm32, rspec, narrow_oop_operand);
7511 }
7512
7513 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7514 InstructionMark im(this);
7515 int encode = prefix_and_encode(src1->encoding());
7516 emit_int8((unsigned char)0x81);
7517 emit_int8((unsigned char)(0xF8 | encode));
7518 emit_data((int)imm32, rspec, narrow_oop_operand);
7519 }
7520
7521 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7522 InstructionMark im(this);
7523 prefix(src1);
7524 emit_int8((unsigned char)0x81);
7525 emit_operand(rax, src1, 4);
7526 emit_data((int)imm32, rspec, narrow_oop_operand);
7527 }
7528
7529 void Assembler::lzcntq(Register dst, Register src) {
7530 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7531 emit_int8((unsigned char)0xF3);
7532 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7533 emit_int8(0x0F);
7534 emit_int8((unsigned char)0xBD);
7535 emit_int8((unsigned char)(0xC0 | encode));
7536 }
7537
7538 void Assembler::movdq(XMMRegister dst, Register src) {
7539 // table D-1 says MMX/SSE2
7540 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7541 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7542 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7543 emit_int8(0x6E);
7544 emit_int8((unsigned char)(0xC0 | encode));
7545 }
7546
7547 void Assembler::movdq(Register dst, XMMRegister src) {
7548 // table D-1 says MMX/SSE2
7549 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7550 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7551 // swap src/dst to get correct prefix
7552 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7553 emit_int8(0x7E);
7554 emit_int8((unsigned char)(0xC0 | encode));
7555 }
7556
7557 void Assembler::movq(Register dst, Register src) {
7558 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7559 emit_int8((unsigned char)0x8B);
7560 emit_int8((unsigned char)(0xC0 | encode));
7561 }
7562
7563 void Assembler::movq(Register dst, Address src) {
7564 InstructionMark im(this);
7565 prefixq(src, dst);
7566 emit_int8((unsigned char)0x8B);
7567 emit_operand(dst, src);
7568 }
7569
7570 void Assembler::movq(Address dst, Register src) {
7571 InstructionMark im(this);
7572 prefixq(dst, src);
7573 emit_int8((unsigned char)0x89);
7574 emit_operand(src, dst);
7575 }
7576
7577 void Assembler::movsbq(Register dst, Address src) {
7578 InstructionMark im(this);
7579 prefixq(src, dst);
7580 emit_int8(0x0F);
7581 emit_int8((unsigned char)0xBE);
7582 emit_operand(dst, src);
7583 }
7584
7585 void Assembler::movsbq(Register dst, Register src) {
7586 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7587 emit_int8(0x0F);
7588 emit_int8((unsigned char)0xBE);
7589 emit_int8((unsigned char)(0xC0 | encode));
7590 }
7591
7592 void Assembler::movslq(Register dst, int32_t imm32) {
7593 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
7594 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
7595 // as a result we shouldn't use until tested at runtime...
7596 ShouldNotReachHere();
7597 InstructionMark im(this);
7598 int encode = prefixq_and_encode(dst->encoding());
7599 emit_int8((unsigned char)(0xC7 | encode));
7600 emit_int32(imm32);
7601 }
7602
7603 void Assembler::movslq(Address dst, int32_t imm32) {
7604 assert(is_simm32(imm32), "lost bits");
7605 InstructionMark im(this);
7606 prefixq(dst);
7607 emit_int8((unsigned char)0xC7);
7608 emit_operand(rax, dst, 4);
7609 emit_int32(imm32);
7610 }
7611
7612 void Assembler::movslq(Register dst, Address src) {
7613 InstructionMark im(this);
7614 prefixq(src, dst);
7615 emit_int8(0x63);
7616 emit_operand(dst, src);
7617 }
7618
7619 void Assembler::movslq(Register dst, Register src) {
7620 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7621 emit_int8(0x63);
7622 emit_int8((unsigned char)(0xC0 | encode));
7623 }
7624
7625 void Assembler::movswq(Register dst, Address src) {
7626 InstructionMark im(this);
7627 prefixq(src, dst);
7628 emit_int8(0x0F);
7629 emit_int8((unsigned char)0xBF);
7630 emit_operand(dst, src);
7631 }
7632
7633 void Assembler::movswq(Register dst, Register src) {
7634 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7635 emit_int8((unsigned char)0x0F);
7636 emit_int8((unsigned char)0xBF);
7637 emit_int8((unsigned char)(0xC0 | encode));
7638 }
7639
7640 void Assembler::movzbq(Register dst, Address src) {
7641 InstructionMark im(this);
7642 prefixq(src, dst);
7643 emit_int8((unsigned char)0x0F);
7644 emit_int8((unsigned char)0xB6);
7645 emit_operand(dst, src);
7646 }
7647
7648 void Assembler::movzbq(Register dst, Register src) {
7649 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7650 emit_int8(0x0F);
7651 emit_int8((unsigned char)0xB6);
7652 emit_int8(0xC0 | encode);
7653 }
7654
7655 void Assembler::movzwq(Register dst, Address src) {
7656 InstructionMark im(this);
7657 prefixq(src, dst);
7658 emit_int8((unsigned char)0x0F);
7659 emit_int8((unsigned char)0xB7);
7660 emit_operand(dst, src);
7661 }
7662
7663 void Assembler::movzwq(Register dst, Register src) {
7664 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7665 emit_int8((unsigned char)0x0F);
7666 emit_int8((unsigned char)0xB7);
7667 emit_int8((unsigned char)(0xC0 | encode));
7668 }
7669
7670 void Assembler::mulq(Address src) {
7671 InstructionMark im(this);
7672 prefixq(src);
7673 emit_int8((unsigned char)0xF7);
7674 emit_operand(rsp, src);
7675 }
7676
7677 void Assembler::mulq(Register src) {
7678 int encode = prefixq_and_encode(src->encoding());
7679 emit_int8((unsigned char)0xF7);
7680 emit_int8((unsigned char)(0xE0 | encode));
7681 }
7682
7683 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
7684 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7685 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7686 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
7687 emit_int8((unsigned char)0xF6);
7688 emit_int8((unsigned char)(0xC0 | encode));
7689 }
7690
7691 void Assembler::negq(Register dst) {
7692 int encode = prefixq_and_encode(dst->encoding());
7693 emit_int8((unsigned char)0xF7);
7694 emit_int8((unsigned char)(0xD8 | encode));
7695 }
7696
7697 void Assembler::notq(Register dst) {
7698 int encode = prefixq_and_encode(dst->encoding());
7699 emit_int8((unsigned char)0xF7);
7700 emit_int8((unsigned char)(0xD0 | encode));
7701 }
7702
7703 void Assembler::orq(Address dst, int32_t imm32) {
7704 InstructionMark im(this);
7705 prefixq(dst);
7706 emit_int8((unsigned char)0x81);
7707 emit_operand(rcx, dst, 4);
7708 emit_int32(imm32);
7709 }
7710
7711 void Assembler::orq(Register dst, int32_t imm32) {
7712 (void) prefixq_and_encode(dst->encoding());
7713 emit_arith(0x81, 0xC8, dst, imm32);
7714 }
7715
7716 void Assembler::orq(Register dst, Address src) {
7717 InstructionMark im(this);
7718 prefixq(src, dst);
7719 emit_int8(0x0B);
7720 emit_operand(dst, src);
7721 }
7722
7723 void Assembler::orq(Register dst, Register src) {
7724 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7725 emit_arith(0x0B, 0xC0, dst, src);
7726 }
7727
7728 void Assembler::popa() { // 64bit
7729 movq(r15, Address(rsp, 0));
7730 movq(r14, Address(rsp, wordSize));
7731 movq(r13, Address(rsp, 2 * wordSize));
7732 movq(r12, Address(rsp, 3 * wordSize));
7733 movq(r11, Address(rsp, 4 * wordSize));
7734 movq(r10, Address(rsp, 5 * wordSize));
7735 movq(r9, Address(rsp, 6 * wordSize));
7736 movq(r8, Address(rsp, 7 * wordSize));
7737 movq(rdi, Address(rsp, 8 * wordSize));
7738 movq(rsi, Address(rsp, 9 * wordSize));
7739 movq(rbp, Address(rsp, 10 * wordSize));
7740 // skip rsp
7741 movq(rbx, Address(rsp, 12 * wordSize));
7742 movq(rdx, Address(rsp, 13 * wordSize));
7743 movq(rcx, Address(rsp, 14 * wordSize));
7744 movq(rax, Address(rsp, 15 * wordSize));
7745
7746 addq(rsp, 16 * wordSize);
7747 }
7748
7749 void Assembler::popcntq(Register dst, Address src) {
7750 assert(VM_Version::supports_popcnt(), "must support");
7751 InstructionMark im(this);
7752 emit_int8((unsigned char)0xF3);
7753 prefixq(src, dst);
7754 emit_int8((unsigned char)0x0F);
7755 emit_int8((unsigned char)0xB8);
7756 emit_operand(dst, src);
7757 }
7758
7759 void Assembler::popcntq(Register dst, Register src) {
7760 assert(VM_Version::supports_popcnt(), "must support");
7761 emit_int8((unsigned char)0xF3);
7762 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7763 emit_int8((unsigned char)0x0F);
7764 emit_int8((unsigned char)0xB8);
7765 emit_int8((unsigned char)(0xC0 | encode));
7766 }
7767
7768 void Assembler::popq(Address dst) {
7769 InstructionMark im(this);
7770 prefixq(dst);
7771 emit_int8((unsigned char)0x8F);
7772 emit_operand(rax, dst);
7773 }
7774
7775 void Assembler::pusha() { // 64bit
7776 // we have to store original rsp. ABI says that 128 bytes
7777 // below rsp are local scratch.
7778 movq(Address(rsp, -5 * wordSize), rsp);
7779
7780 subq(rsp, 16 * wordSize);
7781
7782 movq(Address(rsp, 15 * wordSize), rax);
7783 movq(Address(rsp, 14 * wordSize), rcx);
7784 movq(Address(rsp, 13 * wordSize), rdx);
7785 movq(Address(rsp, 12 * wordSize), rbx);
7786 // skip rsp
7787 movq(Address(rsp, 10 * wordSize), rbp);
7788 movq(Address(rsp, 9 * wordSize), rsi);
7789 movq(Address(rsp, 8 * wordSize), rdi);
7790 movq(Address(rsp, 7 * wordSize), r8);
7791 movq(Address(rsp, 6 * wordSize), r9);
7792 movq(Address(rsp, 5 * wordSize), r10);
7793 movq(Address(rsp, 4 * wordSize), r11);
7794 movq(Address(rsp, 3 * wordSize), r12);
7795 movq(Address(rsp, 2 * wordSize), r13);
7796 movq(Address(rsp, wordSize), r14);
7797 movq(Address(rsp, 0), r15);
7798 }
7799
7800 void Assembler::pushq(Address src) {
7801 InstructionMark im(this);
7802 prefixq(src);
7803 emit_int8((unsigned char)0xFF);
7804 emit_operand(rsi, src);
7805 }
7806
7807 void Assembler::rclq(Register dst, int imm8) {
7808 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7809 int encode = prefixq_and_encode(dst->encoding());
7810 if (imm8 == 1) {
7811 emit_int8((unsigned char)0xD1);
7812 emit_int8((unsigned char)(0xD0 | encode));
7813 } else {
7814 emit_int8((unsigned char)0xC1);
7815 emit_int8((unsigned char)(0xD0 | encode));
7816 emit_int8(imm8);
7817 }
7818 }
7819
7820 void Assembler::rcrq(Register dst, int imm8) {
7821 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7822 int encode = prefixq_and_encode(dst->encoding());
7823 if (imm8 == 1) {
7824 emit_int8((unsigned char)0xD1);
7825 emit_int8((unsigned char)(0xD8 | encode));
7826 } else {
7827 emit_int8((unsigned char)0xC1);
7828 emit_int8((unsigned char)(0xD8 | encode));
7829 emit_int8(imm8);
7830 }
7831 }
7832
7833 void Assembler::rorq(Register dst, int imm8) {
7834 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7835 int encode = prefixq_and_encode(dst->encoding());
7836 if (imm8 == 1) {
7837 emit_int8((unsigned char)0xD1);
7838 emit_int8((unsigned char)(0xC8 | encode));
7839 } else {
7840 emit_int8((unsigned char)0xC1);
7841 emit_int8((unsigned char)(0xc8 | encode));
7842 emit_int8(imm8);
7843 }
7844 }
7845
7846 void Assembler::rorxq(Register dst, Register src, int imm8) {
7847 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
7848 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7849 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
7850 emit_int8((unsigned char)0xF0);
7851 emit_int8((unsigned char)(0xC0 | encode));
7852 emit_int8(imm8);
7853 }
7854
7855 void Assembler::sarq(Register dst, int imm8) {
7856 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7857 int encode = prefixq_and_encode(dst->encoding());
7858 if (imm8 == 1) {
7859 emit_int8((unsigned char)0xD1);
7860 emit_int8((unsigned char)(0xF8 | encode));
7861 } else {
7862 emit_int8((unsigned char)0xC1);
7863 emit_int8((unsigned char)(0xF8 | encode));
7864 emit_int8(imm8);
7865 }
7866 }
7867
7868 void Assembler::sarq(Register dst) {
7869 int encode = prefixq_and_encode(dst->encoding());
7870 emit_int8((unsigned char)0xD3);
7871 emit_int8((unsigned char)(0xF8 | encode));
7872 }
7873
7874 void Assembler::sbbq(Address dst, int32_t imm32) {
7875 InstructionMark im(this);
7876 prefixq(dst);
7877 emit_arith_operand(0x81, rbx, dst, imm32);
7878 }
7879
7880 void Assembler::sbbq(Register dst, int32_t imm32) {
7881 (void) prefixq_and_encode(dst->encoding());
7882 emit_arith(0x81, 0xD8, dst, imm32);
7883 }
7884
7885 void Assembler::sbbq(Register dst, Address src) {
7886 InstructionMark im(this);
7887 prefixq(src, dst);
7888 emit_int8(0x1B);
7889 emit_operand(dst, src);
7890 }
7891
7892 void Assembler::sbbq(Register dst, Register src) {
7893 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7894 emit_arith(0x1B, 0xC0, dst, src);
7895 }
7896
7897 void Assembler::shlq(Register dst, int imm8) {
7898 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7899 int encode = prefixq_and_encode(dst->encoding());
7900 if (imm8 == 1) {
7901 emit_int8((unsigned char)0xD1);
7902 emit_int8((unsigned char)(0xE0 | encode));
7903 } else {
7904 emit_int8((unsigned char)0xC1);
7905 emit_int8((unsigned char)(0xE0 | encode));
7906 emit_int8(imm8);
7907 }
7908 }
7909
7910 void Assembler::shlq(Register dst) {
7911 int encode = prefixq_and_encode(dst->encoding());
7912 emit_int8((unsigned char)0xD3);
7913 emit_int8((unsigned char)(0xE0 | encode));
7914 }
7915
7916 void Assembler::shrq(Register dst, int imm8) {
7917 assert(isShiftCount(imm8 >> 1), "illegal shift count");
7918 int encode = prefixq_and_encode(dst->encoding());
7919 emit_int8((unsigned char)0xC1);
7920 emit_int8((unsigned char)(0xE8 | encode));
7921 emit_int8(imm8);
7922 }
7923
7924 void Assembler::shrq(Register dst) {
7925 int encode = prefixq_and_encode(dst->encoding());
7926 emit_int8((unsigned char)0xD3);
7927 emit_int8(0xE8 | encode);
7928 }
7929
7930 void Assembler::subq(Address dst, int32_t imm32) {
7931 InstructionMark im(this);
7932 prefixq(dst);
7933 emit_arith_operand(0x81, rbp, dst, imm32);
7934 }
7935
7936 void Assembler::subq(Address dst, Register src) {
7937 InstructionMark im(this);
7938 prefixq(dst, src);
7939 emit_int8(0x29);
7940 emit_operand(src, dst);
7941 }
7942
7943 void Assembler::subq(Register dst, int32_t imm32) {
7944 (void) prefixq_and_encode(dst->encoding());
7945 emit_arith(0x81, 0xE8, dst, imm32);
7946 }
7947
7948 // Force generation of a 4 byte immediate value even if it fits into 8bit
7949 void Assembler::subq_imm32(Register dst, int32_t imm32) {
7950 (void) prefixq_and_encode(dst->encoding());
7951 emit_arith_imm32(0x81, 0xE8, dst, imm32);
7952 }
7953
7954 void Assembler::subq(Register dst, Address src) {
7955 InstructionMark im(this);
7956 prefixq(src, dst);
7957 emit_int8(0x2B);
7958 emit_operand(dst, src);
7959 }
7960
7961 void Assembler::subq(Register dst, Register src) {
7962 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7963 emit_arith(0x2B, 0xC0, dst, src);
7964 }
7965
7966 void Assembler::testq(Register dst, int32_t imm32) {
7967 // not using emit_arith because test
7968 // doesn't support sign-extension of
7969 // 8bit operands
7970 int encode = dst->encoding();
7971 if (encode == 0) {
7972 prefix(REX_W);
7973 emit_int8((unsigned char)0xA9);
7974 } else {
7975 encode = prefixq_and_encode(encode);
7976 emit_int8((unsigned char)0xF7);
7977 emit_int8((unsigned char)(0xC0 | encode));
7978 }
7979 emit_int32(imm32);
7980 }
7981
7982 void Assembler::testq(Register dst, Register src) {
7983 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7984 emit_arith(0x85, 0xC0, dst, src);
7985 }
7986
7987 void Assembler::xaddq(Address dst, Register src) {
7988 InstructionMark im(this);
7989 prefixq(dst, src);
7990 emit_int8(0x0F);
7991 emit_int8((unsigned char)0xC1);
7992 emit_operand(src, dst);
7993 }
7994
7995 void Assembler::xchgq(Register dst, Address src) {
7996 InstructionMark im(this);
7997 prefixq(src, dst);
7998 emit_int8((unsigned char)0x87);
7999 emit_operand(dst, src);
8000 }
8001
8002 void Assembler::xchgq(Register dst, Register src) {
8003 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8004 emit_int8((unsigned char)0x87);
8005 emit_int8((unsigned char)(0xc0 | encode));
8006 }
8007
8008 void Assembler::xorq(Register dst, Register src) {
8009 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8010 emit_arith(0x33, 0xC0, dst, src);
8011 }
8012
8013 void Assembler::xorq(Register dst, Address src) {
8014 InstructionMark im(this);
8015 prefixq(src, dst);
8016 emit_int8(0x33);
8017 emit_operand(dst, src);
8018 }
8019
8020 #endif // !LP64