755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x59: // mulpd
776 case 0x6E: // movd
777 case 0x7E: // movd
778 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
779 debug_only(has_disp32 = true);
780 break;
781
782 case 0xAD: // shrd r, a, %cl
783 case 0xAF: // imul r, a
784 case 0xBE: // movsbl r, a (movsxb)
785 case 0xBF: // movswl r, a (movsxw)
786 case 0xB6: // movzbl r, a (movzxb)
787 case 0xB7: // movzwl r, a (movzxw)
788 case REP16(0x40): // cmovl cc, r, a
789 case 0xB0: // cmpxchgb
790 case 0xB1: // cmpxchg
791 case 0xC1: // xaddl
792 case 0xC7: // cmpxchg8
793 case REP16(0x90): // setcc a
794 debug_only(has_disp32 = true);
1873 emit_int8(0x0F);
1874 emit_int8(0x77);
1875 }
1876
1877 void Assembler::hlt() {
1878 emit_int8((unsigned char)0xF4);
1879 }
1880
1881 void Assembler::idivl(Register src) {
1882 int encode = prefix_and_encode(src->encoding());
1883 emit_int8((unsigned char)0xF7);
1884 emit_int8((unsigned char)(0xF8 | encode));
1885 }
1886
1887 void Assembler::divl(Register src) { // Unsigned
1888 int encode = prefix_and_encode(src->encoding());
1889 emit_int8((unsigned char)0xF7);
1890 emit_int8((unsigned char)(0xF0 | encode));
1891 }
1892
1893 void Assembler::imull(Register dst, Register src) {
1894 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1895 emit_int8(0x0F);
1896 emit_int8((unsigned char)0xAF);
1897 emit_int8((unsigned char)(0xC0 | encode));
1898 }
1899
1900
1901 void Assembler::imull(Register dst, Register src, int value) {
1902 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1903 if (is8bit(value)) {
1904 emit_int8(0x6B);
1905 emit_int8((unsigned char)(0xC0 | encode));
1906 emit_int8(value & 0xFF);
1907 } else {
1908 emit_int8(0x69);
1909 emit_int8((unsigned char)(0xC0 | encode));
1910 emit_int32(value);
1911 }
1912 }
3940 emit_int8(0x5C);
3941 emit_int8((unsigned char)(0xC0 | encode));
3942 }
3943
3944 void Assembler::subss(XMMRegister dst, Address src) {
3945 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3946 InstructionMark im(this);
3947 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3948 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3949 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3950 emit_int8(0x5C);
3951 emit_operand(dst, src);
3952 }
3953
3954 void Assembler::testb(Register dst, int imm8) {
3955 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3956 (void) prefix_and_encode(dst->encoding(), true);
3957 emit_arith_b(0xF6, 0xC0, dst, imm8);
3958 }
3959
3960 void Assembler::testl(Register dst, int32_t imm32) {
3961 // not using emit_arith because test
3962 // doesn't support sign-extension of
3963 // 8bit operands
3964 int encode = dst->encoding();
3965 if (encode == 0) {
3966 emit_int8((unsigned char)0xA9);
3967 } else {
3968 encode = prefix_and_encode(encode);
3969 emit_int8((unsigned char)0xF7);
3970 emit_int8((unsigned char)(0xC0 | encode));
3971 }
3972 emit_int32(imm32);
3973 }
3974
3975 void Assembler::testl(Register dst, Register src) {
3976 (void) prefix_and_encode(dst->encoding(), src->encoding());
3977 emit_arith(0x85, 0xC0, dst, src);
3978 }
3979
4268
4269 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4270 assert(VM_Version::supports_avx(), "");
4271 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4272 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4273 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4274 emit_int8(0x5C);
4275 emit_int8((unsigned char)(0xC0 | encode));
4276 }
4277
4278 //====================VECTOR ARITHMETIC=====================================
4279
4280 // Float-point vector arithmetic
4281
4282 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4283 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4284 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4285 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4286 emit_int8(0x58);
4287 emit_int8((unsigned char)(0xC0 | encode));
4288 }
4289
4290 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4291 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4292 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4294 emit_int8(0x58);
4295 emit_int8((unsigned char)(0xC0 | encode));
4296 }
4297
4298 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4299 assert(VM_Version::supports_avx(), "");
4300 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4301 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4302 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4303 emit_int8(0x58);
4304 emit_int8((unsigned char)(0xC0 | encode));
4305 }
4306
4307 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
|
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 debug_only(has_disp32 = true);
781 break;
782
783 case 0xAD: // shrd r, a, %cl
784 case 0xAF: // imul r, a
785 case 0xBE: // movsbl r, a (movsxb)
786 case 0xBF: // movswl r, a (movsxw)
787 case 0xB6: // movzbl r, a (movzxb)
788 case 0xB7: // movzwl r, a (movzxw)
789 case REP16(0x40): // cmovl cc, r, a
790 case 0xB0: // cmpxchgb
791 case 0xB1: // cmpxchg
792 case 0xC1: // xaddl
793 case 0xC7: // cmpxchg8
794 case REP16(0x90): // setcc a
795 debug_only(has_disp32 = true);
1874 emit_int8(0x0F);
1875 emit_int8(0x77);
1876 }
1877
1878 void Assembler::hlt() {
1879 emit_int8((unsigned char)0xF4);
1880 }
1881
1882 void Assembler::idivl(Register src) {
1883 int encode = prefix_and_encode(src->encoding());
1884 emit_int8((unsigned char)0xF7);
1885 emit_int8((unsigned char)(0xF8 | encode));
1886 }
1887
1888 void Assembler::divl(Register src) { // Unsigned
1889 int encode = prefix_and_encode(src->encoding());
1890 emit_int8((unsigned char)0xF7);
1891 emit_int8((unsigned char)(0xF0 | encode));
1892 }
1893
1894 void Assembler::imull(Register src) {
1895 int encode = prefix_and_encode(src->encoding());
1896 emit_int8((unsigned char)0xF7);
1897 emit_int8((unsigned char)(0xE8 | encode));
1898 }
1899
1900 void Assembler::imull(Register dst, Register src) {
1901 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1902 emit_int8(0x0F);
1903 emit_int8((unsigned char)0xAF);
1904 emit_int8((unsigned char)(0xC0 | encode));
1905 }
1906
1907
1908 void Assembler::imull(Register dst, Register src, int value) {
1909 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1910 if (is8bit(value)) {
1911 emit_int8(0x6B);
1912 emit_int8((unsigned char)(0xC0 | encode));
1913 emit_int8(value & 0xFF);
1914 } else {
1915 emit_int8(0x69);
1916 emit_int8((unsigned char)(0xC0 | encode));
1917 emit_int32(value);
1918 }
1919 }
3947 emit_int8(0x5C);
3948 emit_int8((unsigned char)(0xC0 | encode));
3949 }
3950
3951 void Assembler::subss(XMMRegister dst, Address src) {
3952 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3953 InstructionMark im(this);
3954 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3955 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3956 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3957 emit_int8(0x5C);
3958 emit_operand(dst, src);
3959 }
3960
3961 void Assembler::testb(Register dst, int imm8) {
3962 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
3963 (void) prefix_and_encode(dst->encoding(), true);
3964 emit_arith_b(0xF6, 0xC0, dst, imm8);
3965 }
3966
3967 void Assembler::testb(Address dst, int imm8) {
3968 InstructionMark im(this);
3969 prefix(dst);
3970 emit_int8((unsigned char)0xF6);
3971 emit_operand(rax, dst, 1);
3972 emit_int8(imm8);
3973
3974 }
3975
3976 void Assembler::testl(Register dst, int32_t imm32) {
3977 // not using emit_arith because test
3978 // doesn't support sign-extension of
3979 // 8bit operands
3980 int encode = dst->encoding();
3981 if (encode == 0) {
3982 emit_int8((unsigned char)0xA9);
3983 } else {
3984 encode = prefix_and_encode(encode);
3985 emit_int8((unsigned char)0xF7);
3986 emit_int8((unsigned char)(0xC0 | encode));
3987 }
3988 emit_int32(imm32);
3989 }
3990
3991 void Assembler::testl(Register dst, Register src) {
3992 (void) prefix_and_encode(dst->encoding(), src->encoding());
3993 emit_arith(0x85, 0xC0, dst, src);
3994 }
3995
4284
4285 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4286 assert(VM_Version::supports_avx(), "");
4287 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4288 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4289 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4290 emit_int8(0x5C);
4291 emit_int8((unsigned char)(0xC0 | encode));
4292 }
4293
4294 //====================VECTOR ARITHMETIC=====================================
4295
4296 // Float-point vector arithmetic
4297
4298 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4299 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4300 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4301 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4302 emit_int8(0x58);
4303 emit_int8((unsigned char)(0xC0 | encode));
4304 }
4305
4306 void Assembler::addpd(XMMRegister dst, Address src) {
4307 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4308 InstructionMark im(this);
4309 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4310 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4311 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4312 emit_int8(0x58);
4313 emit_operand(dst, src);
4314 }
4315
4316 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4317 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4318 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4319 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4320 emit_int8(0x58);
4321 emit_int8((unsigned char)(0xC0 | encode));
4322 }
4323
4324 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4325 assert(VM_Version::supports_avx(), "");
4326 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4327 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4328 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4329 emit_int8(0x58);
4330 emit_int8((unsigned char)(0xC0 | encode));
4331 }
4332
4333 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
|