9769 format %{ "SUB ESP,8\t # DMOD\n"
9770 "\tMOVSD [ESP+0],$src1\n"
9771 "\tFLD_D [ESP+0]\n"
9772 "\tMOVSD [ESP+0],$src0\n"
9773 "\tFLD_D [ESP+0]\n"
9774 "loop:\tFPREM\n"
9775 "\tFWAIT\n"
9776 "\tFNSTSW AX\n"
9777 "\tSAHF\n"
9778 "\tJP loop\n"
9779 "\tFSTP_D [ESP+0]\n"
9780 "\tMOVSD $dst,[ESP+0]\n"
9781 "\tADD ESP,8\n"
9782 "\tFSTP ST0\t # Restore FPU Stack"
9783 %}
9784 ins_cost(250);
9785 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9786 ins_pipe( pipe_slow );
9787 %}
9788
9789 instruct sinDPR_reg(regDPR1 dst, regDPR1 src) %{
9790 predicate (UseSSE<=1);
9791 match(Set dst (SinD src));
9792 ins_cost(1800);
9793 format %{ "DSIN $dst" %}
9794 opcode(0xD9, 0xFE);
9795 ins_encode( OpcP, OpcS );
9796 ins_pipe( pipe_slow );
9797 %}
9798
9799 instruct sinD_reg(regD dst, eFlagsReg cr) %{
9800 predicate (UseSSE>=2);
9801 match(Set dst (SinD dst));
9802 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9803 ins_cost(1800);
9804 format %{ "DSIN $dst" %}
9805 opcode(0xD9, 0xFE);
9806 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9807 ins_pipe( pipe_slow );
9808 %}
9809
9810 instruct cosDPR_reg(regDPR1 dst, regDPR1 src) %{
9811 predicate (UseSSE<=1);
9812 match(Set dst (CosD src));
9813 ins_cost(1800);
9814 format %{ "DCOS $dst" %}
9815 opcode(0xD9, 0xFF);
9816 ins_encode( OpcP, OpcS );
9817 ins_pipe( pipe_slow );
9818 %}
9819
9820 instruct cosD_reg(regD dst, eFlagsReg cr) %{
9821 predicate (UseSSE>=2);
9822 match(Set dst (CosD dst));
9823 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9824 ins_cost(1800);
9825 format %{ "DCOS $dst" %}
9826 opcode(0xD9, 0xFF);
9827 ins_encode( Push_SrcD(dst), OpcP, OpcS, Push_ResultD(dst) );
9828 ins_pipe( pipe_slow );
9829 %}
9830
9831 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9832 predicate (UseSSE<=1);
9833 match(Set dst(TanD src));
9834 format %{ "DTAN $dst" %}
9835 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9836 Opcode(0xDD), Opcode(0xD8)); // fstp st
9837 ins_pipe( pipe_slow );
9838 %}
9839
9840 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9841 predicate (UseSSE>=2);
9842 match(Set dst(TanD dst));
9843 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9844 format %{ "DTAN $dst" %}
9845 ins_encode( Push_SrcD(dst),
9846 Opcode(0xD9), Opcode(0xF2), // fptan
9847 Opcode(0xDD), Opcode(0xD8), // fstp st
9848 Push_ResultD(dst) );
9849 ins_pipe( pipe_slow );
9850 %}
|
9769 format %{ "SUB ESP,8\t # DMOD\n"
9770 "\tMOVSD [ESP+0],$src1\n"
9771 "\tFLD_D [ESP+0]\n"
9772 "\tMOVSD [ESP+0],$src0\n"
9773 "\tFLD_D [ESP+0]\n"
9774 "loop:\tFPREM\n"
9775 "\tFWAIT\n"
9776 "\tFNSTSW AX\n"
9777 "\tSAHF\n"
9778 "\tJP loop\n"
9779 "\tFSTP_D [ESP+0]\n"
9780 "\tMOVSD $dst,[ESP+0]\n"
9781 "\tADD ESP,8\n"
9782 "\tFSTP ST0\t # Restore FPU Stack"
9783 %}
9784 ins_cost(250);
9785 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9786 ins_pipe( pipe_slow );
9787 %}
9788
9789 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9790 predicate (UseSSE<=1);
9791 match(Set dst(TanD src));
9792 format %{ "DTAN $dst" %}
9793 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9794 Opcode(0xDD), Opcode(0xD8)); // fstp st
9795 ins_pipe( pipe_slow );
9796 %}
9797
9798 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9799 predicate (UseSSE>=2);
9800 match(Set dst(TanD dst));
9801 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9802 format %{ "DTAN $dst" %}
9803 ins_encode( Push_SrcD(dst),
9804 Opcode(0xD9), Opcode(0xF2), // fptan
9805 Opcode(0xDD), Opcode(0xD8), // fstp st
9806 Push_ResultD(dst) );
9807 ins_pipe( pipe_slow );
9808 %}
|