1 /*
   2  * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "code/vmreg.inline.hpp"
  35 #include "utilities/bitMap.inline.hpp"
  36 
  37 #ifndef PRODUCT
  38 
  39   static LinearScanStatistic _stat_before_alloc;
  40   static LinearScanStatistic _stat_after_asign;
  41   static LinearScanStatistic _stat_final;
  42 
  43   static LinearScanTimers _total_timer;
  44 
  45   // helper macro for short definition of timer
  46   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  47 
  48   // helper macro for short definition of trace-output inside code
  49   #define TRACE_LINEAR_SCAN(level, code)       \
  50     if (TraceLinearScanLevel >= level) {       \
  51       code;                                    \
  52     }
  53 
  54 #else
  55 
  56   #define TIME_LINEAR_SCAN(timer_name)
  57   #define TRACE_LINEAR_SCAN(level, code)
  58 
  59 #endif
  60 
  61 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  62 #ifdef _LP64
  63 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, -1};
  64 #else
  65 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
  66 #endif
  67 
  68 
  69 // Implementation of LinearScan
  70 
  71 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  72  : _compilation(ir->compilation())
  73  , _ir(ir)
  74  , _gen(gen)
  75  , _frame_map(frame_map)
  76  , _num_virtual_regs(gen->max_virtual_register_number())
  77  , _has_fpu_registers(false)
  78  , _num_calls(-1)
  79  , _max_spills(0)
  80  , _unused_spill_slot(-1)
  81  , _intervals(0)   // initialized later with correct length
  82  , _new_intervals_from_allocation(new IntervalList())
  83  , _sorted_intervals(NULL)
  84  , _needs_full_resort(false)
  85  , _lir_ops(0)     // initialized later with correct length
  86  , _block_of_op(0) // initialized later with correct length
  87  , _has_info(0)
  88  , _has_call(0)
  89  , _scope_value_cache(0) // initialized later with correct length
  90  , _interval_in_loop(0, 0) // initialized later with correct length
  91  , _cached_blocks(*ir->linear_scan_order())
  92 #ifdef X86
  93  , _fpu_stack_allocator(NULL)
  94 #endif
  95 {
  96   assert(this->ir() != NULL,          "check if valid");
  97   assert(this->compilation() != NULL, "check if valid");
  98   assert(this->gen() != NULL,         "check if valid");
  99   assert(this->frame_map() != NULL,   "check if valid");
 100 }
 101 
 102 
 103 // ********** functions for converting LIR-Operands to register numbers
 104 //
 105 // Emulate a flat register file comprising physical integer registers,
 106 // physical floating-point registers and virtual registers, in that order.
 107 // Virtual registers already have appropriate numbers, since V0 is
 108 // the number of physical registers.
 109 // Returns -1 for hi word if opr is a single word operand.
 110 //
 111 // Note: the inverse operation (calculating an operand for register numbers)
 112 //       is done in calc_operand_for_interval()
 113 
 114 int LinearScan::reg_num(LIR_Opr opr) {
 115   assert(opr->is_register(), "should not call this otherwise");
 116 
 117   if (opr->is_virtual_register()) {
 118     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 119     return opr->vreg_number();
 120   } else if (opr->is_single_cpu()) {
 121     return opr->cpu_regnr();
 122   } else if (opr->is_double_cpu()) {
 123     return opr->cpu_regnrLo();
 124 #ifdef X86
 125   } else if (opr->is_single_xmm()) {
 126     return opr->fpu_regnr() + pd_first_xmm_reg;
 127   } else if (opr->is_double_xmm()) {
 128     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 129 #endif
 130   } else if (opr->is_single_fpu()) {
 131     return opr->fpu_regnr() + pd_first_fpu_reg;
 132   } else if (opr->is_double_fpu()) {
 133     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 134   } else {
 135     ShouldNotReachHere();
 136     return -1;
 137   }
 138 }
 139 
 140 int LinearScan::reg_numHi(LIR_Opr opr) {
 141   assert(opr->is_register(), "should not call this otherwise");
 142 
 143   if (opr->is_virtual_register()) {
 144     return -1;
 145   } else if (opr->is_single_cpu()) {
 146     return -1;
 147   } else if (opr->is_double_cpu()) {
 148     return opr->cpu_regnrHi();
 149 #ifdef X86
 150   } else if (opr->is_single_xmm()) {
 151     return -1;
 152   } else if (opr->is_double_xmm()) {
 153     return -1;
 154 #endif
 155   } else if (opr->is_single_fpu()) {
 156     return -1;
 157   } else if (opr->is_double_fpu()) {
 158     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 159   } else {
 160     ShouldNotReachHere();
 161     return -1;
 162   }
 163 }
 164 
 165 
 166 // ********** functions for classification of intervals
 167 
 168 bool LinearScan::is_precolored_interval(const Interval* i) {
 169   return i->reg_num() < LinearScan::nof_regs;
 170 }
 171 
 172 bool LinearScan::is_virtual_interval(const Interval* i) {
 173   return i->reg_num() >= LIR_OprDesc::vreg_base;
 174 }
 175 
 176 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 177   return i->reg_num() < LinearScan::nof_cpu_regs;
 178 }
 179 
 180 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 181 #if defined(__SOFTFP__) || defined(E500V2)
 182   return i->reg_num() >= LIR_OprDesc::vreg_base;
 183 #else
 184   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 185 #endif // __SOFTFP__ or E500V2
 186 }
 187 
 188 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 189   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 190 }
 191 
 192 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 193 #if defined(__SOFTFP__) || defined(E500V2)
 194   return false;
 195 #else
 196   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 197 #endif // __SOFTFP__ or E500V2
 198 }
 199 
 200 bool LinearScan::is_in_fpu_register(const Interval* i) {
 201   // fixed intervals not needed for FPU stack allocation
 202   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 203 }
 204 
 205 bool LinearScan::is_oop_interval(const Interval* i) {
 206   // fixed intervals never contain oops
 207   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 208 }
 209 
 210 
 211 // ********** General helper functions
 212 
 213 // compute next unused stack index that can be used for spilling
 214 int LinearScan::allocate_spill_slot(bool double_word) {
 215   int spill_slot;
 216   if (double_word) {
 217     if ((_max_spills & 1) == 1) {
 218       // alignment of double-word values
 219       // the hole because of the alignment is filled with the next single-word value
 220       assert(_unused_spill_slot == -1, "wasting a spill slot");
 221       _unused_spill_slot = _max_spills;
 222       _max_spills++;
 223     }
 224     spill_slot = _max_spills;
 225     _max_spills += 2;
 226 
 227   } else if (_unused_spill_slot != -1) {
 228     // re-use hole that was the result of a previous double-word alignment
 229     spill_slot = _unused_spill_slot;
 230     _unused_spill_slot = -1;
 231 
 232   } else {
 233     spill_slot = _max_spills;
 234     _max_spills++;
 235   }
 236 
 237   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 238 
 239   // the class OopMapValue uses only 11 bits for storing the name of the
 240   // oop location. So a stack slot bigger than 2^11 leads to an overflow
 241   // that is not reported in product builds. Prevent this by checking the
 242   // spill slot here (altough this value and the later used location name
 243   // are slightly different)
 244   if (result > 2000) {
 245     bailout("too many stack slots used");
 246   }
 247 
 248   return result;
 249 }
 250 
 251 void LinearScan::assign_spill_slot(Interval* it) {
 252   // assign the canonical spill slot of the parent (if a part of the interval
 253   // is already spilled) or allocate a new spill slot
 254   if (it->canonical_spill_slot() >= 0) {
 255     it->assign_reg(it->canonical_spill_slot());
 256   } else {
 257     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 258     it->set_canonical_spill_slot(spill);
 259     it->assign_reg(spill);
 260   }
 261 }
 262 
 263 void LinearScan::propagate_spill_slots() {
 264   if (!frame_map()->finalize_frame(max_spills())) {
 265     bailout("frame too large");
 266   }
 267 }
 268 
 269 // create a new interval with a predefined reg_num
 270 // (only used for parent intervals that are created during the building phase)
 271 Interval* LinearScan::create_interval(int reg_num) {
 272   assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
 273 
 274   Interval* interval = new Interval(reg_num);
 275   _intervals.at_put(reg_num, interval);
 276 
 277   // assign register number for precolored intervals
 278   if (reg_num < LIR_OprDesc::vreg_base) {
 279     interval->assign_reg(reg_num);
 280   }
 281   return interval;
 282 }
 283 
 284 // assign a new reg_num to the interval and append it to the list of intervals
 285 // (only used for child intervals that are created during register allocation)
 286 void LinearScan::append_interval(Interval* it) {
 287   it->set_reg_num(_intervals.length());
 288   _intervals.append(it);
 289   _new_intervals_from_allocation->append(it);
 290 }
 291 
 292 // copy the vreg-flags if an interval is split
 293 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 294   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 295     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 296   }
 297   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 298     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 299   }
 300 
 301   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 302   //       intervals (only the very beginning of the interval must be in memory)
 303 }
 304 
 305 
 306 // ********** spill move optimization
 307 // eliminate moves from register to stack if stack slot is known to be correct
 308 
 309 // called during building of intervals
 310 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 311   assert(interval->is_split_parent(), "can only be called for split parents");
 312 
 313   switch (interval->spill_state()) {
 314     case noDefinitionFound:
 315       assert(interval->spill_definition_pos() == -1, "must no be set before");
 316       interval->set_spill_definition_pos(def_pos);
 317       interval->set_spill_state(oneDefinitionFound);
 318       break;
 319 
 320     case oneDefinitionFound:
 321       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 322       if (def_pos < interval->spill_definition_pos() - 2) {
 323         // second definition found, so no spill optimization possible for this interval
 324         interval->set_spill_state(noOptimization);
 325       } else {
 326         // two consecutive definitions (because of two-operand LIR form)
 327         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 328       }
 329       break;
 330 
 331     case noOptimization:
 332       // nothing to do
 333       break;
 334 
 335     default:
 336       assert(false, "other states not allowed at this time");
 337   }
 338 }
 339 
 340 // called during register allocation
 341 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 342   switch (interval->spill_state()) {
 343     case oneDefinitionFound: {
 344       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 345       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 346 
 347       if (def_loop_depth < spill_loop_depth) {
 348         // the loop depth of the spilling position is higher then the loop depth
 349         // at the definition of the interval -> move write to memory out of loop
 350         // by storing at definitin of the interval
 351         interval->set_spill_state(storeAtDefinition);
 352       } else {
 353         // the interval is currently spilled only once, so for now there is no
 354         // reason to store the interval at the definition
 355         interval->set_spill_state(oneMoveInserted);
 356       }
 357       break;
 358     }
 359 
 360     case oneMoveInserted: {
 361       // the interval is spilled more then once, so it is better to store it to
 362       // memory at the definition
 363       interval->set_spill_state(storeAtDefinition);
 364       break;
 365     }
 366 
 367     case storeAtDefinition:
 368     case startInMemory:
 369     case noOptimization:
 370     case noDefinitionFound:
 371       // nothing to do
 372       break;
 373 
 374     default:
 375       assert(false, "other states not allowed at this time");
 376   }
 377 }
 378 
 379 
 380 bool LinearScan::must_store_at_definition(const Interval* i) {
 381   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 382 }
 383 
 384 // called once before asignment of register numbers
 385 void LinearScan::eliminate_spill_moves() {
 386   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 387   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 388 
 389   // collect all intervals that must be stored after their definion.
 390   // the list is sorted by Interval::spill_definition_pos
 391   Interval* interval;
 392   Interval* temp_list;
 393   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 394 
 395 #ifdef ASSERT
 396   Interval* prev = NULL;
 397   Interval* temp = interval;
 398   while (temp != Interval::end()) {
 399     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 400     if (prev != NULL) {
 401       assert(temp->from() >= prev->from(), "intervals not sorted");
 402       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 403     }
 404 
 405     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 406     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 407     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 408 
 409     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 410 
 411     temp = temp->next();
 412   }
 413 #endif
 414 
 415   LIR_InsertionBuffer insertion_buffer;
 416   int num_blocks = block_count();
 417   for (int i = 0; i < num_blocks; i++) {
 418     BlockBegin* block = block_at(i);
 419     LIR_OpList* instructions = block->lir()->instructions_list();
 420     int         num_inst = instructions->length();
 421     bool        has_new = false;
 422 
 423     // iterate all instructions of the block. skip the first because it is always a label
 424     for (int j = 1; j < num_inst; j++) {
 425       LIR_Op* op = instructions->at(j);
 426       int op_id = op->id();
 427 
 428       if (op_id == -1) {
 429         // remove move from register to stack if the stack slot is guaranteed to be correct.
 430         // only moves that have been inserted by LinearScan can be removed.
 431         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 432         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 433         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 434 
 435         LIR_Op1* op1 = (LIR_Op1*)op;
 436         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 437 
 438         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 439           // move target is a stack slot that is always correct, so eliminate instruction
 440           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 441           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 442         }
 443 
 444       } else {
 445         // insert move from register to stack just after the beginning of the interval
 446         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 447         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 448 
 449         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 450           if (!has_new) {
 451             // prepare insertion buffer (appended when all instructions of the block are processed)
 452             insertion_buffer.init(block->lir());
 453             has_new = true;
 454           }
 455 
 456           LIR_Opr from_opr = operand_for_interval(interval);
 457           LIR_Opr to_opr = canonical_spill_opr(interval);
 458           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 459           assert(to_opr->is_stack(), "to operand must be a stack slot");
 460 
 461           insertion_buffer.move(j, from_opr, to_opr);
 462           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 463 
 464           interval = interval->next();
 465         }
 466       }
 467     } // end of instruction iteration
 468 
 469     if (has_new) {
 470       block->lir()->append(&insertion_buffer);
 471     }
 472   } // end of block iteration
 473 
 474   assert(interval == Interval::end(), "missed an interval");
 475 }
 476 
 477 
 478 // ********** Phase 1: number all instructions in all blocks
 479 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 480 
 481 void LinearScan::number_instructions() {
 482   {
 483     // dummy-timer to measure the cost of the timer itself
 484     // (this time is then subtracted from all other timers to get the real value)
 485     TIME_LINEAR_SCAN(timer_do_nothing);
 486   }
 487   TIME_LINEAR_SCAN(timer_number_instructions);
 488 
 489   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 490   int num_blocks = block_count();
 491   int num_instructions = 0;
 492   int i;
 493   for (i = 0; i < num_blocks; i++) {
 494     num_instructions += block_at(i)->lir()->instructions_list()->length();
 495   }
 496 
 497   // initialize with correct length
 498   _lir_ops = LIR_OpArray(num_instructions);
 499   _block_of_op = BlockBeginArray(num_instructions);
 500 
 501   int op_id = 0;
 502   int idx = 0;
 503 
 504   for (i = 0; i < num_blocks; i++) {
 505     BlockBegin* block = block_at(i);
 506     block->set_first_lir_instruction_id(op_id);
 507     LIR_OpList* instructions = block->lir()->instructions_list();
 508 
 509     int num_inst = instructions->length();
 510     for (int j = 0; j < num_inst; j++) {
 511       LIR_Op* op = instructions->at(j);
 512       op->set_id(op_id);
 513 
 514       _lir_ops.at_put(idx, op);
 515       _block_of_op.at_put(idx, block);
 516       assert(lir_op_with_id(op_id) == op, "must match");
 517 
 518       idx++;
 519       op_id += 2; // numbering of lir_ops by two
 520     }
 521     block->set_last_lir_instruction_id(op_id - 2);
 522   }
 523   assert(idx == num_instructions, "must match");
 524   assert(idx * 2 == op_id, "must match");
 525 
 526   _has_call = BitMap(num_instructions); _has_call.clear();
 527   _has_info = BitMap(num_instructions); _has_info.clear();
 528 }
 529 
 530 
 531 // ********** Phase 2: compute local live sets separately for each block
 532 // (sets live_gen and live_kill for each block)
 533 
 534 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 535   LIR_Opr opr = value->operand();
 536   Constant* con = value->as_Constant();
 537 
 538   // check some asumptions about debug information
 539   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 540   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
 541   assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
 542 
 543   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 544     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 545     int reg = opr->vreg_number();
 546     if (!live_kill.at(reg)) {
 547       live_gen.set_bit(reg);
 548       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 549     }
 550   }
 551 }
 552 
 553 
 554 void LinearScan::compute_local_live_sets() {
 555   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 556 
 557   int  num_blocks = block_count();
 558   int  live_size = live_set_size();
 559   bool local_has_fpu_registers = false;
 560   int  local_num_calls = 0;
 561   LIR_OpVisitState visitor;
 562 
 563   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 564   local_interval_in_loop.clear();
 565 
 566   // iterate all blocks
 567   for (int i = 0; i < num_blocks; i++) {
 568     BlockBegin* block = block_at(i);
 569 
 570     BitMap live_gen(live_size);  live_gen.clear();
 571     BitMap live_kill(live_size); live_kill.clear();
 572 
 573     if (block->is_set(BlockBegin::exception_entry_flag)) {
 574       // Phi functions at the begin of an exception handler are
 575       // implicitly defined (= killed) at the beginning of the block.
 576       for_each_phi_fun(block, phi,
 577         live_kill.set_bit(phi->operand()->vreg_number())
 578       );
 579     }
 580 
 581     LIR_OpList* instructions = block->lir()->instructions_list();
 582     int num_inst = instructions->length();
 583 
 584     // iterate all instructions of the block. skip the first because it is always a label
 585     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 586     for (int j = 1; j < num_inst; j++) {
 587       LIR_Op* op = instructions->at(j);
 588 
 589       // visit operation to collect all operands
 590       visitor.visit(op);
 591 
 592       if (visitor.has_call()) {
 593         _has_call.set_bit(op->id() >> 1);
 594         local_num_calls++;
 595       }
 596       if (visitor.info_count() > 0) {
 597         _has_info.set_bit(op->id() >> 1);
 598       }
 599 
 600       // iterate input operands of instruction
 601       int k, n, reg;
 602       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 603       for (k = 0; k < n; k++) {
 604         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 605         assert(opr->is_register(), "visitor should only return register operands");
 606 
 607         if (opr->is_virtual_register()) {
 608           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 609           reg = opr->vreg_number();
 610           if (!live_kill.at(reg)) {
 611             live_gen.set_bit(reg);
 612             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 613           }
 614           if (block->loop_index() >= 0) {
 615             local_interval_in_loop.set_bit(reg, block->loop_index());
 616           }
 617           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 618         }
 619 
 620 #ifdef ASSERT
 621         // fixed intervals are never live at block boundaries, so
 622         // they need not be processed in live sets.
 623         // this is checked by these assertions to be sure about it.
 624         // the entry block may have incoming values in registers, which is ok.
 625         if (!opr->is_virtual_register() && block != ir()->start()) {
 626           reg = reg_num(opr);
 627           if (is_processed_reg_num(reg)) {
 628             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 629           }
 630           reg = reg_numHi(opr);
 631           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 632             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 633           }
 634         }
 635 #endif
 636       }
 637 
 638       // Add uses of live locals from interpreter's point of view for proper debug information generation
 639       n = visitor.info_count();
 640       for (k = 0; k < n; k++) {
 641         CodeEmitInfo* info = visitor.info_at(k);
 642         ValueStack* stack = info->stack();
 643         for_each_state_value(stack, value,
 644           set_live_gen_kill(value, op, live_gen, live_kill)
 645         );
 646       }
 647 
 648       // iterate temp operands of instruction
 649       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 650       for (k = 0; k < n; k++) {
 651         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 652         assert(opr->is_register(), "visitor should only return register operands");
 653 
 654         if (opr->is_virtual_register()) {
 655           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 656           reg = opr->vreg_number();
 657           live_kill.set_bit(reg);
 658           if (block->loop_index() >= 0) {
 659             local_interval_in_loop.set_bit(reg, block->loop_index());
 660           }
 661           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 662         }
 663 
 664 #ifdef ASSERT
 665         // fixed intervals are never live at block boundaries, so
 666         // they need not be processed in live sets
 667         // process them only in debug mode so that this can be checked
 668         if (!opr->is_virtual_register()) {
 669           reg = reg_num(opr);
 670           if (is_processed_reg_num(reg)) {
 671             live_kill.set_bit(reg_num(opr));
 672           }
 673           reg = reg_numHi(opr);
 674           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 675             live_kill.set_bit(reg);
 676           }
 677         }
 678 #endif
 679       }
 680 
 681       // iterate output operands of instruction
 682       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 683       for (k = 0; k < n; k++) {
 684         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 685         assert(opr->is_register(), "visitor should only return register operands");
 686 
 687         if (opr->is_virtual_register()) {
 688           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 689           reg = opr->vreg_number();
 690           live_kill.set_bit(reg);
 691           if (block->loop_index() >= 0) {
 692             local_interval_in_loop.set_bit(reg, block->loop_index());
 693           }
 694           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 695         }
 696 
 697 #ifdef ASSERT
 698         // fixed intervals are never live at block boundaries, so
 699         // they need not be processed in live sets
 700         // process them only in debug mode so that this can be checked
 701         if (!opr->is_virtual_register()) {
 702           reg = reg_num(opr);
 703           if (is_processed_reg_num(reg)) {
 704             live_kill.set_bit(reg_num(opr));
 705           }
 706           reg = reg_numHi(opr);
 707           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 708             live_kill.set_bit(reg);
 709           }
 710         }
 711 #endif
 712       }
 713     } // end of instruction iteration
 714 
 715     block->set_live_gen (live_gen);
 716     block->set_live_kill(live_kill);
 717     block->set_live_in  (BitMap(live_size)); block->live_in().clear();
 718     block->set_live_out (BitMap(live_size)); block->live_out().clear();
 719 
 720     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 721     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 722   } // end of block iteration
 723 
 724   // propagate local calculated information into LinearScan object
 725   _has_fpu_registers = local_has_fpu_registers;
 726   compilation()->set_has_fpu_code(local_has_fpu_registers);
 727 
 728   _num_calls = local_num_calls;
 729   _interval_in_loop = local_interval_in_loop;
 730 }
 731 
 732 
 733 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 734 // (sets live_in and live_out for each block)
 735 
 736 void LinearScan::compute_global_live_sets() {
 737   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 738 
 739   int  num_blocks = block_count();
 740   bool change_occurred;
 741   bool change_occurred_in_block;
 742   int  iteration_count = 0;
 743   BitMap live_out(live_set_size()); live_out.clear(); // scratch set for calculations
 744 
 745   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 746   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 747   // Exception handlers must be processed because not all live values are
 748   // present in the state array, e.g. because of global value numbering
 749   do {
 750     change_occurred = false;
 751 
 752     // iterate all blocks in reverse order
 753     for (int i = num_blocks - 1; i >= 0; i--) {
 754       BlockBegin* block = block_at(i);
 755 
 756       change_occurred_in_block = false;
 757 
 758       // live_out(block) is the union of live_in(sux), for successors sux of block
 759       int n = block->number_of_sux();
 760       int e = block->number_of_exception_handlers();
 761       if (n + e > 0) {
 762         // block has successors
 763         if (n > 0) {
 764           live_out.set_from(block->sux_at(0)->live_in());
 765           for (int j = 1; j < n; j++) {
 766             live_out.set_union(block->sux_at(j)->live_in());
 767           }
 768         } else {
 769           live_out.clear();
 770         }
 771         for (int j = 0; j < e; j++) {
 772           live_out.set_union(block->exception_handler_at(j)->live_in());
 773         }
 774 
 775         if (!block->live_out().is_same(live_out)) {
 776           // A change occurred.  Swap the old and new live out sets to avoid copying.
 777           BitMap temp = block->live_out();
 778           block->set_live_out(live_out);
 779           live_out = temp;
 780 
 781           change_occurred = true;
 782           change_occurred_in_block = true;
 783         }
 784       }
 785 
 786       if (iteration_count == 0 || change_occurred_in_block) {
 787         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 788         // note: live_in has to be computed only in first iteration or if live_out has changed!
 789         BitMap live_in = block->live_in();
 790         live_in.set_from(block->live_out());
 791         live_in.set_difference(block->live_kill());
 792         live_in.set_union(block->live_gen());
 793       }
 794 
 795 #ifndef PRODUCT
 796       if (TraceLinearScanLevel >= 4) {
 797         char c = ' ';
 798         if (iteration_count == 0 || change_occurred_in_block) {
 799           c = '*';
 800         }
 801         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 802         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 803       }
 804 #endif
 805     }
 806     iteration_count++;
 807 
 808     if (change_occurred && iteration_count > 50) {
 809       BAILOUT("too many iterations in compute_global_live_sets");
 810     }
 811   } while (change_occurred);
 812 
 813 
 814 #ifdef ASSERT
 815   // check that fixed intervals are not live at block boundaries
 816   // (live set must be empty at fixed intervals)
 817   for (int i = 0; i < num_blocks; i++) {
 818     BlockBegin* block = block_at(i);
 819     for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
 820       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 821       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 822       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 823     }
 824   }
 825 #endif
 826 
 827   // check that the live_in set of the first block is empty
 828   BitMap live_in_args(ir()->start()->live_in().size());
 829   live_in_args.clear();
 830   if (!ir()->start()->live_in().is_same(live_in_args)) {
 831 #ifdef ASSERT
 832     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 833     tty->print_cr("affected registers:");
 834     print_bitmap(ir()->start()->live_in());
 835 
 836     // print some additional information to simplify debugging
 837     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 838       if (ir()->start()->live_in().at(i)) {
 839         Instruction* instr = gen()->instruction_for_vreg(i);
 840         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 841 
 842         for (int j = 0; j < num_blocks; j++) {
 843           BlockBegin* block = block_at(j);
 844           if (block->live_gen().at(i)) {
 845             tty->print_cr("  used in block B%d", block->block_id());
 846           }
 847           if (block->live_kill().at(i)) {
 848             tty->print_cr("  defined in block B%d", block->block_id());
 849           }
 850         }
 851       }
 852     }
 853 
 854 #endif
 855     // when this fails, virtual registers are used before they are defined.
 856     assert(false, "live_in set of first block must be empty");
 857     // bailout of if this occurs in product mode.
 858     bailout("live_in set of first block not empty");
 859   }
 860 }
 861 
 862 
 863 // ********** Phase 4: build intervals
 864 // (fills the list _intervals)
 865 
 866 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 867   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 868   LIR_Opr opr = value->operand();
 869   Constant* con = value->as_Constant();
 870 
 871   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 872     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 873     add_use(opr, from, to, use_kind);
 874   }
 875 }
 876 
 877 
 878 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 879   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 880   assert(opr->is_register(), "should not be called otherwise");
 881 
 882   if (opr->is_virtual_register()) {
 883     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 884     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 885 
 886   } else {
 887     int reg = reg_num(opr);
 888     if (is_processed_reg_num(reg)) {
 889       add_def(reg, def_pos, use_kind, opr->type_register());
 890     }
 891     reg = reg_numHi(opr);
 892     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 893       add_def(reg, def_pos, use_kind, opr->type_register());
 894     }
 895   }
 896 }
 897 
 898 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 899   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 900   assert(opr->is_register(), "should not be called otherwise");
 901 
 902   if (opr->is_virtual_register()) {
 903     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 904     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 905 
 906   } else {
 907     int reg = reg_num(opr);
 908     if (is_processed_reg_num(reg)) {
 909       add_use(reg, from, to, use_kind, opr->type_register());
 910     }
 911     reg = reg_numHi(opr);
 912     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 913       add_use(reg, from, to, use_kind, opr->type_register());
 914     }
 915   }
 916 }
 917 
 918 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 919   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 920   assert(opr->is_register(), "should not be called otherwise");
 921 
 922   if (opr->is_virtual_register()) {
 923     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 924     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 925 
 926   } else {
 927     int reg = reg_num(opr);
 928     if (is_processed_reg_num(reg)) {
 929       add_temp(reg, temp_pos, use_kind, opr->type_register());
 930     }
 931     reg = reg_numHi(opr);
 932     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 933       add_temp(reg, temp_pos, use_kind, opr->type_register());
 934     }
 935   }
 936 }
 937 
 938 
 939 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 940   Interval* interval = interval_at(reg_num);
 941   if (interval != NULL) {
 942     assert(interval->reg_num() == reg_num, "wrong interval");
 943 
 944     if (type != T_ILLEGAL) {
 945       interval->set_type(type);
 946     }
 947 
 948     Range* r = interval->first();
 949     if (r->from() <= def_pos) {
 950       // Update the starting point (when a range is first created for a use, its
 951       // start is the beginning of the current block until a def is encountered.)
 952       r->set_from(def_pos);
 953       interval->add_use_pos(def_pos, use_kind);
 954 
 955     } else {
 956       // Dead value - make vacuous interval
 957       // also add use_kind for dead intervals
 958       interval->add_range(def_pos, def_pos + 1);
 959       interval->add_use_pos(def_pos, use_kind);
 960       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 961     }
 962 
 963   } else {
 964     // Dead value - make vacuous interval
 965     // also add use_kind for dead intervals
 966     interval = create_interval(reg_num);
 967     if (type != T_ILLEGAL) {
 968       interval->set_type(type);
 969     }
 970 
 971     interval->add_range(def_pos, def_pos + 1);
 972     interval->add_use_pos(def_pos, use_kind);
 973     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 974   }
 975 
 976   change_spill_definition_pos(interval, def_pos);
 977   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 978         // detection of method-parameters and roundfp-results
 979         // TODO: move this directly to position where use-kind is computed
 980     interval->set_spill_state(startInMemory);
 981   }
 982 }
 983 
 984 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
 985   Interval* interval = interval_at(reg_num);
 986   if (interval == NULL) {
 987     interval = create_interval(reg_num);
 988   }
 989   assert(interval->reg_num() == reg_num, "wrong interval");
 990 
 991   if (type != T_ILLEGAL) {
 992     interval->set_type(type);
 993   }
 994 
 995   interval->add_range(from, to);
 996   interval->add_use_pos(to, use_kind);
 997 }
 998 
 999 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1000   Interval* interval = interval_at(reg_num);
1001   if (interval == NULL) {
1002     interval = create_interval(reg_num);
1003   }
1004   assert(interval->reg_num() == reg_num, "wrong interval");
1005 
1006   if (type != T_ILLEGAL) {
1007     interval->set_type(type);
1008   }
1009 
1010   interval->add_range(temp_pos, temp_pos + 1);
1011   interval->add_use_pos(temp_pos, use_kind);
1012 }
1013 
1014 
1015 // the results of this functions are used for optimizing spilling and reloading
1016 // if the functions return shouldHaveRegister and the interval is spilled,
1017 // it is not reloaded to a register.
1018 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1019   if (op->code() == lir_move) {
1020     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1021     LIR_Op1* move = (LIR_Op1*)op;
1022     LIR_Opr res = move->result_opr();
1023     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1024 
1025     if (result_in_memory) {
1026       // Begin of an interval with must_start_in_memory set.
1027       // This interval will always get a stack slot first, so return noUse.
1028       return noUse;
1029 
1030     } else if (move->in_opr()->is_stack()) {
1031       // method argument (condition must be equal to handle_method_arguments)
1032       return noUse;
1033 
1034     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1035       // Move from register to register
1036       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1037         // special handling of phi-function moves inside osr-entry blocks
1038         // input operand must have a register instead of output operand (leads to better register allocation)
1039         return shouldHaveRegister;
1040       }
1041     }
1042   }
1043 
1044   if (opr->is_virtual() &&
1045       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1046     // result is a stack-slot, so prevent immediate reloading
1047     return noUse;
1048   }
1049 
1050   // all other operands require a register
1051   return mustHaveRegister;
1052 }
1053 
1054 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1055   if (op->code() == lir_move) {
1056     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1057     LIR_Op1* move = (LIR_Op1*)op;
1058     LIR_Opr res = move->result_opr();
1059     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1060 
1061     if (result_in_memory) {
1062       // Move to an interval with must_start_in_memory set.
1063       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1064       return mustHaveRegister;
1065 
1066     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1067       // Move from register to register
1068       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1069         // special handling of phi-function moves inside osr-entry blocks
1070         // input operand must have a register instead of output operand (leads to better register allocation)
1071         return mustHaveRegister;
1072       }
1073 
1074       // The input operand is not forced to a register (moves from stack to register are allowed),
1075       // but it is faster if the input operand is in a register
1076       return shouldHaveRegister;
1077     }
1078   }
1079 
1080 
1081 #ifdef X86
1082   if (op->code() == lir_cmove) {
1083     // conditional moves can handle stack operands
1084     assert(op->result_opr()->is_register(), "result must always be in a register");
1085     return shouldHaveRegister;
1086   }
1087 
1088   // optimizations for second input operand of arithmehtic operations on Intel
1089   // this operand is allowed to be on the stack in some cases
1090   BasicType opr_type = opr->type_register();
1091   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1092     if ((UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2) {
1093       // SSE float instruction (T_DOUBLE only supported with SSE2)
1094       switch (op->code()) {
1095         case lir_cmp:
1096         case lir_add:
1097         case lir_sub:
1098         case lir_mul:
1099         case lir_div:
1100         {
1101           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1102           LIR_Op2* op2 = (LIR_Op2*)op;
1103           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1104             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1105             return shouldHaveRegister;
1106           }
1107         }
1108       }
1109     } else {
1110       // FPU stack float instruction
1111       switch (op->code()) {
1112         case lir_add:
1113         case lir_sub:
1114         case lir_mul:
1115         case lir_div:
1116         {
1117           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1118           LIR_Op2* op2 = (LIR_Op2*)op;
1119           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1120             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1121             return shouldHaveRegister;
1122           }
1123         }
1124       }
1125     }
1126     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1127     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1128     // T_OBJECT doesn't get spilled along with T_LONG.
1129   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1130     // integer instruction (note: long operands must always be in register)
1131     switch (op->code()) {
1132       case lir_cmp:
1133       case lir_add:
1134       case lir_sub:
1135       case lir_logic_and:
1136       case lir_logic_or:
1137       case lir_logic_xor:
1138       {
1139         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1140         LIR_Op2* op2 = (LIR_Op2*)op;
1141         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1142           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1143           return shouldHaveRegister;
1144         }
1145       }
1146     }
1147   }
1148 #endif // X86
1149 
1150   // all other operands require a register
1151   return mustHaveRegister;
1152 }
1153 
1154 
1155 void LinearScan::handle_method_arguments(LIR_Op* op) {
1156   // special handling for method arguments (moves from stack to virtual register):
1157   // the interval gets no register assigned, but the stack slot.
1158   // it is split before the first use by the register allocator.
1159 
1160   if (op->code() == lir_move) {
1161     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1162     LIR_Op1* move = (LIR_Op1*)op;
1163 
1164     if (move->in_opr()->is_stack()) {
1165 #ifdef ASSERT
1166       int arg_size = compilation()->method()->arg_size();
1167       LIR_Opr o = move->in_opr();
1168       if (o->is_single_stack()) {
1169         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1170       } else if (o->is_double_stack()) {
1171         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1172       } else {
1173         ShouldNotReachHere();
1174       }
1175 
1176       assert(move->id() > 0, "invalid id");
1177       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1178       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1179 
1180       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1181 #endif
1182 
1183       Interval* interval = interval_at(reg_num(move->result_opr()));
1184 
1185       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1186       interval->set_canonical_spill_slot(stack_slot);
1187       interval->assign_reg(stack_slot);
1188     }
1189   }
1190 }
1191 
1192 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1193   // special handling for doubleword move from memory to register:
1194   // in this case the registers of the input address and the result
1195   // registers must not overlap -> add a temp range for the input registers
1196   if (op->code() == lir_move) {
1197     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1198     LIR_Op1* move = (LIR_Op1*)op;
1199 
1200     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1201       LIR_Address* address = move->in_opr()->as_address_ptr();
1202       if (address != NULL) {
1203         if (address->base()->is_valid()) {
1204           add_temp(address->base(), op->id(), noUse);
1205         }
1206         if (address->index()->is_valid()) {
1207           add_temp(address->index(), op->id(), noUse);
1208         }
1209       }
1210     }
1211   }
1212 }
1213 
1214 void LinearScan::add_register_hints(LIR_Op* op) {
1215   switch (op->code()) {
1216     case lir_move:      // fall through
1217     case lir_convert: {
1218       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1219       LIR_Op1* move = (LIR_Op1*)op;
1220 
1221       LIR_Opr move_from = move->in_opr();
1222       LIR_Opr move_to = move->result_opr();
1223 
1224       if (move_to->is_register() && move_from->is_register()) {
1225         Interval* from = interval_at(reg_num(move_from));
1226         Interval* to = interval_at(reg_num(move_to));
1227         if (from != NULL && to != NULL) {
1228           to->set_register_hint(from);
1229           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1230         }
1231       }
1232       break;
1233     }
1234     case lir_cmove: {
1235       assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1236       LIR_Op2* cmove = (LIR_Op2*)op;
1237 
1238       LIR_Opr move_from = cmove->in_opr1();
1239       LIR_Opr move_to = cmove->result_opr();
1240 
1241       if (move_to->is_register() && move_from->is_register()) {
1242         Interval* from = interval_at(reg_num(move_from));
1243         Interval* to = interval_at(reg_num(move_to));
1244         if (from != NULL && to != NULL) {
1245           to->set_register_hint(from);
1246           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1247         }
1248       }
1249       break;
1250     }
1251   }
1252 }
1253 
1254 
1255 void LinearScan::build_intervals() {
1256   TIME_LINEAR_SCAN(timer_build_intervals);
1257 
1258   // initialize interval list with expected number of intervals
1259   // (32 is added to have some space for split children without having to resize the list)
1260   _intervals = IntervalList(num_virtual_regs() + 32);
1261   // initialize all slots that are used by build_intervals
1262   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1263 
1264   // create a list with all caller-save registers (cpu, fpu, xmm)
1265   // when an instruction is a call, a temp range is created for all these registers
1266   int num_caller_save_registers = 0;
1267   int caller_save_registers[LinearScan::nof_regs];
1268 
1269   int i;
1270   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1271     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1272     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1273     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1274     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1275   }
1276 
1277   // temp ranges for fpu registers are only created when the method has
1278   // virtual fpu operands. Otherwise no allocation for fpu registers is
1279   // perfomed and so the temp ranges would be useless
1280   if (has_fpu_registers()) {
1281 #ifdef X86
1282     if (UseSSE < 2) {
1283 #endif
1284       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1285         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1286         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1287         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1288         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1289       }
1290 #ifdef X86
1291     }
1292     if (UseSSE > 0) {
1293       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1294       for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1295         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1296         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1297         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1298         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1299       }
1300     }
1301 #endif
1302   }
1303   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1304 
1305 
1306   LIR_OpVisitState visitor;
1307 
1308   // iterate all blocks in reverse order
1309   for (i = block_count() - 1; i >= 0; i--) {
1310     BlockBegin* block = block_at(i);
1311     LIR_OpList* instructions = block->lir()->instructions_list();
1312     int         block_from =   block->first_lir_instruction_id();
1313     int         block_to =     block->last_lir_instruction_id();
1314 
1315     assert(block_from == instructions->at(0)->id(), "must be");
1316     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1317 
1318     // Update intervals for registers live at the end of this block;
1319     BitMap live = block->live_out();
1320     int size = (int)live.size();
1321     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1322       assert(live.at(number), "should not stop here otherwise");
1323       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1324       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1325 
1326       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1327 
1328       // add special use positions for loop-end blocks when the
1329       // interval is used anywhere inside this loop.  It's possible
1330       // that the block was part of a non-natural loop, so it might
1331       // have an invalid loop index.
1332       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1333           block->loop_index() != -1 &&
1334           is_interval_in_loop(number, block->loop_index())) {
1335         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1336       }
1337     }
1338 
1339     // iterate all instructions of the block in reverse order.
1340     // skip the first instruction because it is always a label
1341     // definitions of intervals are processed before uses
1342     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1343     for (int j = instructions->length() - 1; j >= 1; j--) {
1344       LIR_Op* op = instructions->at(j);
1345       int op_id = op->id();
1346 
1347       // visit operation to collect all operands
1348       visitor.visit(op);
1349 
1350       // add a temp range for each register if operation destroys caller-save registers
1351       if (visitor.has_call()) {
1352         for (int k = 0; k < num_caller_save_registers; k++) {
1353           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1354         }
1355         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1356       }
1357 
1358       // Add any platform dependent temps
1359       pd_add_temps(op);
1360 
1361       // visit definitions (output and temp operands)
1362       int k, n;
1363       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1364       for (k = 0; k < n; k++) {
1365         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1366         assert(opr->is_register(), "visitor should only return register operands");
1367         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1368       }
1369 
1370       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1371       for (k = 0; k < n; k++) {
1372         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1373         assert(opr->is_register(), "visitor should only return register operands");
1374         add_temp(opr, op_id, mustHaveRegister);
1375       }
1376 
1377       // visit uses (input operands)
1378       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1379       for (k = 0; k < n; k++) {
1380         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1381         assert(opr->is_register(), "visitor should only return register operands");
1382         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1383       }
1384 
1385       // Add uses of live locals from interpreter's point of view for proper
1386       // debug information generation
1387       // Treat these operands as temp values (if the life range is extended
1388       // to a call site, the value would be in a register at the call otherwise)
1389       n = visitor.info_count();
1390       for (k = 0; k < n; k++) {
1391         CodeEmitInfo* info = visitor.info_at(k);
1392         ValueStack* stack = info->stack();
1393         for_each_state_value(stack, value,
1394           add_use(value, block_from, op_id + 1, noUse);
1395         );
1396       }
1397 
1398       // special steps for some instructions (especially moves)
1399       handle_method_arguments(op);
1400       handle_doubleword_moves(op);
1401       add_register_hints(op);
1402 
1403     } // end of instruction iteration
1404   } // end of block iteration
1405 
1406 
1407   // add the range [0, 1[ to all fixed intervals
1408   // -> the register allocator need not handle unhandled fixed intervals
1409   for (int n = 0; n < LinearScan::nof_regs; n++) {
1410     Interval* interval = interval_at(n);
1411     if (interval != NULL) {
1412       interval->add_range(0, 1);
1413     }
1414   }
1415 }
1416 
1417 
1418 // ********** Phase 5: actual register allocation
1419 
1420 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1421   if (*a != NULL) {
1422     if (*b != NULL) {
1423       return (*a)->from() - (*b)->from();
1424     } else {
1425       return -1;
1426     }
1427   } else {
1428     if (*b != NULL) {
1429       return 1;
1430     } else {
1431       return 0;
1432     }
1433   }
1434 }
1435 
1436 #ifndef PRODUCT
1437 bool LinearScan::is_sorted(IntervalArray* intervals) {
1438   int from = -1;
1439   int i, j;
1440   for (i = 0; i < intervals->length(); i ++) {
1441     Interval* it = intervals->at(i);
1442     if (it != NULL) {
1443       if (from > it->from()) {
1444         assert(false, "");
1445         return false;
1446       }
1447       from = it->from();
1448     }
1449   }
1450 
1451   // check in both directions if sorted list and unsorted list contain same intervals
1452   for (i = 0; i < interval_count(); i++) {
1453     if (interval_at(i) != NULL) {
1454       int num_found = 0;
1455       for (j = 0; j < intervals->length(); j++) {
1456         if (interval_at(i) == intervals->at(j)) {
1457           num_found++;
1458         }
1459       }
1460       assert(num_found == 1, "lists do not contain same intervals");
1461     }
1462   }
1463   for (j = 0; j < intervals->length(); j++) {
1464     int num_found = 0;
1465     for (i = 0; i < interval_count(); i++) {
1466       if (interval_at(i) == intervals->at(j)) {
1467         num_found++;
1468       }
1469     }
1470     assert(num_found == 1, "lists do not contain same intervals");
1471   }
1472 
1473   return true;
1474 }
1475 #endif
1476 
1477 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1478   if (*prev != NULL) {
1479     (*prev)->set_next(interval);
1480   } else {
1481     *first = interval;
1482   }
1483   *prev = interval;
1484 }
1485 
1486 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1487   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1488 
1489   *list1 = *list2 = Interval::end();
1490 
1491   Interval* list1_prev = NULL;
1492   Interval* list2_prev = NULL;
1493   Interval* v;
1494 
1495   const int n = _sorted_intervals->length();
1496   for (int i = 0; i < n; i++) {
1497     v = _sorted_intervals->at(i);
1498     if (v == NULL) continue;
1499 
1500     if (is_list1(v)) {
1501       add_to_list(list1, &list1_prev, v);
1502     } else if (is_list2 == NULL || is_list2(v)) {
1503       add_to_list(list2, &list2_prev, v);
1504     }
1505   }
1506 
1507   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1508   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1509 
1510   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1511   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1512 }
1513 
1514 
1515 void LinearScan::sort_intervals_before_allocation() {
1516   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1517 
1518   if (_needs_full_resort) {
1519     // There is no known reason why this should occur but just in case...
1520     assert(false, "should never occur");
1521     // Re-sort existing interval list because an Interval::from() has changed
1522     _sorted_intervals->sort(interval_cmp);
1523     _needs_full_resort = false;
1524   }
1525 
1526   IntervalList* unsorted_list = &_intervals;
1527   int unsorted_len = unsorted_list->length();
1528   int sorted_len = 0;
1529   int unsorted_idx;
1530   int sorted_idx = 0;
1531   int sorted_from_max = -1;
1532 
1533   // calc number of items for sorted list (sorted list must not contain NULL values)
1534   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1535     if (unsorted_list->at(unsorted_idx) != NULL) {
1536       sorted_len++;
1537     }
1538   }
1539   IntervalArray* sorted_list = new IntervalArray(sorted_len);
1540 
1541   // special sorting algorithm: the original interval-list is almost sorted,
1542   // only some intervals are swapped. So this is much faster than a complete QuickSort
1543   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1544     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1545 
1546     if (cur_interval != NULL) {
1547       int cur_from = cur_interval->from();
1548 
1549       if (sorted_from_max <= cur_from) {
1550         sorted_list->at_put(sorted_idx++, cur_interval);
1551         sorted_from_max = cur_interval->from();
1552       } else {
1553         // the asumption that the intervals are already sorted failed,
1554         // so this interval must be sorted in manually
1555         int j;
1556         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1557           sorted_list->at_put(j + 1, sorted_list->at(j));
1558         }
1559         sorted_list->at_put(j + 1, cur_interval);
1560         sorted_idx++;
1561       }
1562     }
1563   }
1564   _sorted_intervals = sorted_list;
1565   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1566 }
1567 
1568 void LinearScan::sort_intervals_after_allocation() {
1569   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1570 
1571   if (_needs_full_resort) {
1572     // Re-sort existing interval list because an Interval::from() has changed
1573     _sorted_intervals->sort(interval_cmp);
1574     _needs_full_resort = false;
1575   }
1576 
1577   IntervalArray* old_list      = _sorted_intervals;
1578   IntervalList*  new_list      = _new_intervals_from_allocation;
1579   int old_len = old_list->length();
1580   int new_len = new_list->length();
1581 
1582   if (new_len == 0) {
1583     // no intervals have been added during allocation, so sorted list is already up to date
1584     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1585     return;
1586   }
1587 
1588   // conventional sort-algorithm for new intervals
1589   new_list->sort(interval_cmp);
1590 
1591   // merge old and new list (both already sorted) into one combined list
1592   IntervalArray* combined_list = new IntervalArray(old_len + new_len);
1593   int old_idx = 0;
1594   int new_idx = 0;
1595 
1596   while (old_idx + new_idx < old_len + new_len) {
1597     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1598       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1599       old_idx++;
1600     } else {
1601       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1602       new_idx++;
1603     }
1604   }
1605 
1606   _sorted_intervals = combined_list;
1607   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1608 }
1609 
1610 
1611 void LinearScan::allocate_registers() {
1612   TIME_LINEAR_SCAN(timer_allocate_registers);
1613 
1614   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1615   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1616 
1617   // allocate cpu registers
1618   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals,
1619                          is_precolored_cpu_interval, is_virtual_cpu_interval);
1620 
1621   // allocate fpu registers
1622   create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals,
1623                          is_precolored_fpu_interval, is_virtual_fpu_interval);
1624 
1625   // the fpu interval allocation cannot be moved down below with the fpu section as
1626   // the cpu_lsw.walk() changes interval positions.
1627 
1628   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1629   cpu_lsw.walk();
1630   cpu_lsw.finish_allocation();
1631 
1632   if (has_fpu_registers()) {
1633     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1634     fpu_lsw.walk();
1635     fpu_lsw.finish_allocation();
1636   }
1637 }
1638 
1639 
1640 // ********** Phase 6: resolve data flow
1641 // (insert moves at edges between blocks if intervals have been split)
1642 
1643 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1644 // instead of returning NULL
1645 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1646   Interval* result = interval->split_child_at_op_id(op_id, mode);
1647   if (result != NULL) {
1648     return result;
1649   }
1650 
1651   assert(false, "must find an interval, but do a clean bailout in product mode");
1652   result = new Interval(LIR_OprDesc::vreg_base);
1653   result->assign_reg(0);
1654   result->set_type(T_INT);
1655   BAILOUT_("LinearScan: interval is NULL", result);
1656 }
1657 
1658 
1659 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1660   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1661   assert(interval_at(reg_num) != NULL, "no interval found");
1662 
1663   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1664 }
1665 
1666 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1667   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1668   assert(interval_at(reg_num) != NULL, "no interval found");
1669 
1670   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1671 }
1672 
1673 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1674   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1675   assert(interval_at(reg_num) != NULL, "no interval found");
1676 
1677   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1678 }
1679 
1680 
1681 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1682   DEBUG_ONLY(move_resolver.check_empty());
1683 
1684   const int num_regs = num_virtual_regs();
1685   const int size = live_set_size();
1686   const BitMap live_at_edge = to_block->live_in();
1687 
1688   // visit all registers where the live_at_edge bit is set
1689   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1690     assert(r < num_regs, "live information set for not exisiting interval");
1691     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1692 
1693     Interval* from_interval = interval_at_block_end(from_block, r);
1694     Interval* to_interval = interval_at_block_begin(to_block, r);
1695 
1696     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1697       // need to insert move instruction
1698       move_resolver.add_mapping(from_interval, to_interval);
1699     }
1700   }
1701 }
1702 
1703 
1704 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1705   if (from_block->number_of_sux() <= 1) {
1706     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1707 
1708     LIR_OpList* instructions = from_block->lir()->instructions_list();
1709     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1710     if (branch != NULL) {
1711       // insert moves before branch
1712       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1713       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1714     } else {
1715       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1716     }
1717 
1718   } else {
1719     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1720 #ifdef ASSERT
1721     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1722 
1723     // because the number of predecessor edges matches the number of
1724     // successor edges, blocks which are reached by switch statements
1725     // may have be more than one predecessor but it will be guaranteed
1726     // that all predecessors will be the same.
1727     for (int i = 0; i < to_block->number_of_preds(); i++) {
1728       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1729     }
1730 #endif
1731 
1732     move_resolver.set_insert_position(to_block->lir(), 0);
1733   }
1734 }
1735 
1736 
1737 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1738 void LinearScan::resolve_data_flow() {
1739   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1740 
1741   int num_blocks = block_count();
1742   MoveResolver move_resolver(this);
1743   BitMap block_completed(num_blocks);  block_completed.clear();
1744   BitMap already_resolved(num_blocks); already_resolved.clear();
1745 
1746   int i;
1747   for (i = 0; i < num_blocks; i++) {
1748     BlockBegin* block = block_at(i);
1749 
1750     // check if block has only one predecessor and only one successor
1751     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1752       LIR_OpList* instructions = block->lir()->instructions_list();
1753       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1754       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1755       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1756 
1757       // check if block is empty (only label and branch)
1758       if (instructions->length() == 2) {
1759         BlockBegin* pred = block->pred_at(0);
1760         BlockBegin* sux = block->sux_at(0);
1761 
1762         // prevent optimization of two consecutive blocks
1763         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1764           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1765           block_completed.set_bit(block->linear_scan_number());
1766 
1767           // directly resolve between pred and sux (without looking at the empty block between)
1768           resolve_collect_mappings(pred, sux, move_resolver);
1769           if (move_resolver.has_mappings()) {
1770             move_resolver.set_insert_position(block->lir(), 0);
1771             move_resolver.resolve_and_append_moves();
1772           }
1773         }
1774       }
1775     }
1776   }
1777 
1778 
1779   for (i = 0; i < num_blocks; i++) {
1780     if (!block_completed.at(i)) {
1781       BlockBegin* from_block = block_at(i);
1782       already_resolved.set_from(block_completed);
1783 
1784       int num_sux = from_block->number_of_sux();
1785       for (int s = 0; s < num_sux; s++) {
1786         BlockBegin* to_block = from_block->sux_at(s);
1787 
1788         // check for duplicate edges between the same blocks (can happen with switch blocks)
1789         if (!already_resolved.at(to_block->linear_scan_number())) {
1790           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1791           already_resolved.set_bit(to_block->linear_scan_number());
1792 
1793           // collect all intervals that have been split between from_block and to_block
1794           resolve_collect_mappings(from_block, to_block, move_resolver);
1795           if (move_resolver.has_mappings()) {
1796             resolve_find_insert_pos(from_block, to_block, move_resolver);
1797             move_resolver.resolve_and_append_moves();
1798           }
1799         }
1800       }
1801     }
1802   }
1803 }
1804 
1805 
1806 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1807   if (interval_at(reg_num) == NULL) {
1808     // if a phi function is never used, no interval is created -> ignore this
1809     return;
1810   }
1811 
1812   Interval* interval = interval_at_block_begin(block, reg_num);
1813   int reg = interval->assigned_reg();
1814   int regHi = interval->assigned_regHi();
1815 
1816   if ((reg < nof_regs && interval->always_in_memory()) ||
1817       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1818     // the interval is split to get a short range that is located on the stack
1819     // in the following two cases:
1820     // * the interval started in memory (e.g. method parameter), but is currently in a register
1821     //   this is an optimization for exception handling that reduces the number of moves that
1822     //   are necessary for resolving the states when an exception uses this exception handler
1823     // * the interval would be on the fpu stack at the begin of the exception handler
1824     //   this is not allowed because of the complicated fpu stack handling on Intel
1825 
1826     // range that will be spilled to memory
1827     int from_op_id = block->first_lir_instruction_id();
1828     int to_op_id = from_op_id + 1;  // short live range of length 1
1829     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1830            "no split allowed between exception entry and first instruction");
1831 
1832     if (interval->from() != from_op_id) {
1833       // the part before from_op_id is unchanged
1834       interval = interval->split(from_op_id);
1835       interval->assign_reg(reg, regHi);
1836       append_interval(interval);
1837     } else {
1838       _needs_full_resort = true;
1839     }
1840     assert(interval->from() == from_op_id, "must be true now");
1841 
1842     Interval* spilled_part = interval;
1843     if (interval->to() != to_op_id) {
1844       // the part after to_op_id is unchanged
1845       spilled_part = interval->split_from_start(to_op_id);
1846       append_interval(spilled_part);
1847       move_resolver.add_mapping(spilled_part, interval);
1848     }
1849     assign_spill_slot(spilled_part);
1850 
1851     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1852   }
1853 }
1854 
1855 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1856   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1857   DEBUG_ONLY(move_resolver.check_empty());
1858 
1859   // visit all registers where the live_in bit is set
1860   int size = live_set_size();
1861   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1862     resolve_exception_entry(block, r, move_resolver);
1863   }
1864 
1865   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1866   for_each_phi_fun(block, phi,
1867     resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver)
1868   );
1869 
1870   if (move_resolver.has_mappings()) {
1871     // insert moves after first instruction
1872     move_resolver.set_insert_position(block->lir(), 0);
1873     move_resolver.resolve_and_append_moves();
1874   }
1875 }
1876 
1877 
1878 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1879   if (interval_at(reg_num) == NULL) {
1880     // if a phi function is never used, no interval is created -> ignore this
1881     return;
1882   }
1883 
1884   // the computation of to_interval is equal to resolve_collect_mappings,
1885   // but from_interval is more complicated because of phi functions
1886   BlockBegin* to_block = handler->entry_block();
1887   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1888 
1889   if (phi != NULL) {
1890     // phi function of the exception entry block
1891     // no moves are created for this phi function in the LIR_Generator, so the
1892     // interval at the throwing instruction must be searched using the operands
1893     // of the phi function
1894     Value from_value = phi->operand_at(handler->phi_operand());
1895 
1896     // with phi functions it can happen that the same from_value is used in
1897     // multiple mappings, so notify move-resolver that this is allowed
1898     move_resolver.set_multiple_reads_allowed();
1899 
1900     Constant* con = from_value->as_Constant();
1901     if (con != NULL && !con->is_pinned()) {
1902       // unpinned constants may have no register, so add mapping from constant to interval
1903       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1904     } else {
1905       // search split child at the throwing op_id
1906       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1907       move_resolver.add_mapping(from_interval, to_interval);
1908     }
1909 
1910   } else {
1911     // no phi function, so use reg_num also for from_interval
1912     // search split child at the throwing op_id
1913     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1914     if (from_interval != to_interval) {
1915       // optimization to reduce number of moves: when to_interval is on stack and
1916       // the stack slot is known to be always correct, then no move is necessary
1917       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1918         move_resolver.add_mapping(from_interval, to_interval);
1919       }
1920     }
1921   }
1922 }
1923 
1924 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1925   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1926 
1927   DEBUG_ONLY(move_resolver.check_empty());
1928   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1929   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1930   assert(handler->entry_code() == NULL, "code already present");
1931 
1932   // visit all registers where the live_in bit is set
1933   BlockBegin* block = handler->entry_block();
1934   int size = live_set_size();
1935   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1936     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1937   }
1938 
1939   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1940   for_each_phi_fun(block, phi,
1941     resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver)
1942   );
1943 
1944   if (move_resolver.has_mappings()) {
1945     LIR_List* entry_code = new LIR_List(compilation());
1946     move_resolver.set_insert_position(entry_code, 0);
1947     move_resolver.resolve_and_append_moves();
1948 
1949     entry_code->jump(handler->entry_block());
1950     handler->set_entry_code(entry_code);
1951   }
1952 }
1953 
1954 
1955 void LinearScan::resolve_exception_handlers() {
1956   MoveResolver move_resolver(this);
1957   LIR_OpVisitState visitor;
1958   int num_blocks = block_count();
1959 
1960   int i;
1961   for (i = 0; i < num_blocks; i++) {
1962     BlockBegin* block = block_at(i);
1963     if (block->is_set(BlockBegin::exception_entry_flag)) {
1964       resolve_exception_entry(block, move_resolver);
1965     }
1966   }
1967 
1968   for (i = 0; i < num_blocks; i++) {
1969     BlockBegin* block = block_at(i);
1970     LIR_List* ops = block->lir();
1971     int num_ops = ops->length();
1972 
1973     // iterate all instructions of the block. skip the first because it is always a label
1974     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
1975     for (int j = 1; j < num_ops; j++) {
1976       LIR_Op* op = ops->at(j);
1977       int op_id = op->id();
1978 
1979       if (op_id != -1 && has_info(op_id)) {
1980         // visit operation to collect all operands
1981         visitor.visit(op);
1982         assert(visitor.info_count() > 0, "should not visit otherwise");
1983 
1984         XHandlers* xhandlers = visitor.all_xhandler();
1985         int n = xhandlers->length();
1986         for (int k = 0; k < n; k++) {
1987           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
1988         }
1989 
1990 #ifdef ASSERT
1991       } else {
1992         visitor.visit(op);
1993         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
1994 #endif
1995       }
1996     }
1997   }
1998 }
1999 
2000 
2001 // ********** Phase 7: assign register numbers back to LIR
2002 // (includes computation of debug information and oop maps)
2003 
2004 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2005   VMReg reg = interval->cached_vm_reg();
2006   if (!reg->is_valid() ) {
2007     reg = vm_reg_for_operand(operand_for_interval(interval));
2008     interval->set_cached_vm_reg(reg);
2009   }
2010   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2011   return reg;
2012 }
2013 
2014 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2015   assert(opr->is_oop(), "currently only implemented for oop operands");
2016   return frame_map()->regname(opr);
2017 }
2018 
2019 
2020 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2021   LIR_Opr opr = interval->cached_opr();
2022   if (opr->is_illegal()) {
2023     opr = calc_operand_for_interval(interval);
2024     interval->set_cached_opr(opr);
2025   }
2026 
2027   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2028   return opr;
2029 }
2030 
2031 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2032   int assigned_reg = interval->assigned_reg();
2033   BasicType type = interval->type();
2034 
2035   if (assigned_reg >= nof_regs) {
2036     // stack slot
2037     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2038     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2039 
2040   } else {
2041     // register
2042     switch (type) {
2043       case T_OBJECT: {
2044         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2045         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2046         return LIR_OprFact::single_cpu_oop(assigned_reg);
2047       }
2048 
2049       case T_ADDRESS: {
2050         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2051         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2052         return LIR_OprFact::single_cpu_address(assigned_reg);
2053       }
2054 
2055       case T_METADATA: {
2056         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2057         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2058         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2059       }
2060 
2061 #ifdef __SOFTFP__
2062       case T_FLOAT:  // fall through
2063 #endif // __SOFTFP__
2064       case T_INT: {
2065         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2066         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2067         return LIR_OprFact::single_cpu(assigned_reg);
2068       }
2069 
2070 #ifdef __SOFTFP__
2071       case T_DOUBLE:  // fall through
2072 #endif // __SOFTFP__
2073       case T_LONG: {
2074         int assigned_regHi = interval->assigned_regHi();
2075         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2076         assert(num_physical_regs(T_LONG) == 1 ||
2077                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2078 
2079         assert(assigned_reg != assigned_regHi, "invalid allocation");
2080         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2081                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2082         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2083         if (requires_adjacent_regs(T_LONG)) {
2084           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2085         }
2086 
2087 #ifdef _LP64
2088         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2089 #else
2090 #if defined(SPARC) || defined(PPC32)
2091         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2092 #else
2093         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2094 #endif // SPARC
2095 #endif // LP64
2096       }
2097 
2098 #ifndef __SOFTFP__
2099       case T_FLOAT: {
2100 #ifdef X86
2101         if (UseSSE >= 1) {
2102           int last_xmm_reg = pd_last_xmm_reg;
2103 #ifdef _LP64
2104           if (UseAVX < 3) {
2105             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2106           }
2107 #endif
2108           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2109           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2110           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2111         }
2112 #endif
2113 
2114         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2115         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2116         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2117       }
2118 
2119       case T_DOUBLE: {
2120 #ifdef X86
2121         if (UseSSE >= 2) {
2122           int last_xmm_reg = pd_last_xmm_reg;
2123 #ifdef _LP64
2124           if (UseAVX < 3) {
2125             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2126           }
2127 #endif
2128           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2129           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2130           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2131         }
2132 #endif
2133 
2134 #ifdef SPARC
2135         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2136         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2137         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2138         LIR_Opr result = LIR_OprFact::double_fpu(interval->assigned_regHi() - pd_first_fpu_reg, assigned_reg - pd_first_fpu_reg);
2139 #elif defined(ARM32)
2140         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2141         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2142         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2143         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2144 #else
2145         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2146         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2147         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2148 #endif
2149         return result;
2150       }
2151 #endif // __SOFTFP__
2152 
2153       default: {
2154         ShouldNotReachHere();
2155         return LIR_OprFact::illegalOpr;
2156       }
2157     }
2158   }
2159 }
2160 
2161 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2162   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2163   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2164 }
2165 
2166 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2167   assert(opr->is_virtual(), "should not call this otherwise");
2168 
2169   Interval* interval = interval_at(opr->vreg_number());
2170   assert(interval != NULL, "interval must exist");
2171 
2172   if (op_id != -1) {
2173 #ifdef ASSERT
2174     BlockBegin* block = block_of_op_with_id(op_id);
2175     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2176       // check if spill moves could have been appended at the end of this block, but
2177       // before the branch instruction. So the split child information for this branch would
2178       // be incorrect.
2179       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2180       if (branch != NULL) {
2181         if (block->live_out().at(opr->vreg_number())) {
2182           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2183           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2184         }
2185       }
2186     }
2187 #endif
2188 
2189     // operands are not changed when an interval is split during allocation,
2190     // so search the right interval here
2191     interval = split_child_at_op_id(interval, op_id, mode);
2192   }
2193 
2194   LIR_Opr res = operand_for_interval(interval);
2195 
2196 #ifdef X86
2197   // new semantic for is_last_use: not only set on definite end of interval,
2198   // but also before hole
2199   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2200   // last use information is completely correct
2201   // information is only needed for fpu stack allocation
2202   if (res->is_fpu_register()) {
2203     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2204       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2205       res = res->make_last_use();
2206     }
2207   }
2208 #endif
2209 
2210   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2211 
2212   return res;
2213 }
2214 
2215 
2216 #ifdef ASSERT
2217 // some methods used to check correctness of debug information
2218 
2219 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2220   if (values == NULL) {
2221     return;
2222   }
2223 
2224   for (int i = 0; i < values->length(); i++) {
2225     ScopeValue* value = values->at(i);
2226 
2227     if (value->is_location()) {
2228       Location location = ((LocationValue*)value)->location();
2229       assert(location.where() == Location::on_stack, "value is in register");
2230     }
2231   }
2232 }
2233 
2234 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2235   if (values == NULL) {
2236     return;
2237   }
2238 
2239   for (int i = 0; i < values->length(); i++) {
2240     MonitorValue* value = values->at(i);
2241 
2242     if (value->owner()->is_location()) {
2243       Location location = ((LocationValue*)value->owner())->location();
2244       assert(location.where() == Location::on_stack, "owner is in register");
2245     }
2246     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2247   }
2248 }
2249 
2250 void assert_equal(Location l1, Location l2) {
2251   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2252 }
2253 
2254 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2255   if (v1->is_location()) {
2256     assert(v2->is_location(), "");
2257     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2258   } else if (v1->is_constant_int()) {
2259     assert(v2->is_constant_int(), "");
2260     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2261   } else if (v1->is_constant_double()) {
2262     assert(v2->is_constant_double(), "");
2263     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2264   } else if (v1->is_constant_long()) {
2265     assert(v2->is_constant_long(), "");
2266     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2267   } else if (v1->is_constant_oop()) {
2268     assert(v2->is_constant_oop(), "");
2269     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2270   } else {
2271     ShouldNotReachHere();
2272   }
2273 }
2274 
2275 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2276   assert_equal(m1->owner(), m2->owner());
2277   assert_equal(m1->basic_lock(), m2->basic_lock());
2278 }
2279 
2280 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2281   assert(d1->scope() == d2->scope(), "not equal");
2282   assert(d1->bci() == d2->bci(), "not equal");
2283 
2284   if (d1->locals() != NULL) {
2285     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2286     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2287     for (int i = 0; i < d1->locals()->length(); i++) {
2288       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2289     }
2290   } else {
2291     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2292   }
2293 
2294   if (d1->expressions() != NULL) {
2295     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2296     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2297     for (int i = 0; i < d1->expressions()->length(); i++) {
2298       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2299     }
2300   } else {
2301     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2302   }
2303 
2304   if (d1->monitors() != NULL) {
2305     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2306     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2307     for (int i = 0; i < d1->monitors()->length(); i++) {
2308       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2309     }
2310   } else {
2311     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2312   }
2313 
2314   if (d1->caller() != NULL) {
2315     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2316     assert_equal(d1->caller(), d2->caller());
2317   } else {
2318     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2319   }
2320 }
2321 
2322 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2323   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2324     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2325     switch (code) {
2326       case Bytecodes::_ifnull    : // fall through
2327       case Bytecodes::_ifnonnull : // fall through
2328       case Bytecodes::_ifeq      : // fall through
2329       case Bytecodes::_ifne      : // fall through
2330       case Bytecodes::_iflt      : // fall through
2331       case Bytecodes::_ifge      : // fall through
2332       case Bytecodes::_ifgt      : // fall through
2333       case Bytecodes::_ifle      : // fall through
2334       case Bytecodes::_if_icmpeq : // fall through
2335       case Bytecodes::_if_icmpne : // fall through
2336       case Bytecodes::_if_icmplt : // fall through
2337       case Bytecodes::_if_icmpge : // fall through
2338       case Bytecodes::_if_icmpgt : // fall through
2339       case Bytecodes::_if_icmple : // fall through
2340       case Bytecodes::_if_acmpeq : // fall through
2341       case Bytecodes::_if_acmpne :
2342         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2343         break;
2344     }
2345   }
2346 }
2347 
2348 #endif // ASSERT
2349 
2350 
2351 IntervalWalker* LinearScan::init_compute_oop_maps() {
2352   // setup lists of potential oops for walking
2353   Interval* oop_intervals;
2354   Interval* non_oop_intervals;
2355 
2356   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2357 
2358   // intervals that have no oops inside need not to be processed
2359   // to ensure a walking until the last instruction id, add a dummy interval
2360   // with a high operation id
2361   non_oop_intervals = new Interval(any_reg);
2362   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2363 
2364   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2365 }
2366 
2367 
2368 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2369   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2370 
2371   // walk before the current operation -> intervals that start at
2372   // the operation (= output operands of the operation) are not
2373   // included in the oop map
2374   iw->walk_before(op->id());
2375 
2376   int frame_size = frame_map()->framesize();
2377   int arg_count = frame_map()->oop_map_arg_count();
2378   OopMap* map = new OopMap(frame_size, arg_count);
2379 
2380   // Iterate through active intervals
2381   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2382     int assigned_reg = interval->assigned_reg();
2383 
2384     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2385     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2386     assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2387 
2388     // Check if this range covers the instruction. Intervals that
2389     // start or end at the current operation are not included in the
2390     // oop map, except in the case of patching moves.  For patching
2391     // moves, any intervals which end at this instruction are included
2392     // in the oop map since we may safepoint while doing the patch
2393     // before we've consumed the inputs.
2394     if (op->is_patching() || op->id() < interval->current_to()) {
2395 
2396       // caller-save registers must not be included into oop-maps at calls
2397       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2398 
2399       VMReg name = vm_reg_for_interval(interval);
2400       set_oop(map, name);
2401 
2402       // Spill optimization: when the stack value is guaranteed to be always correct,
2403       // then it must be added to the oop map even if the interval is currently in a register
2404       if (interval->always_in_memory() &&
2405           op->id() > interval->spill_definition_pos() &&
2406           interval->assigned_reg() != interval->canonical_spill_slot()) {
2407         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2408         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2409         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2410 
2411         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2412       }
2413     }
2414   }
2415 
2416   // add oops from lock stack
2417   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2418   int locks_count = info->stack()->total_locks_size();
2419   for (int i = 0; i < locks_count; i++) {
2420     set_oop(map, frame_map()->monitor_object_regname(i));
2421   }
2422 
2423   return map;
2424 }
2425 
2426 
2427 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2428   assert(visitor.info_count() > 0, "no oop map needed");
2429 
2430   // compute oop_map only for first CodeEmitInfo
2431   // because it is (in most cases) equal for all other infos of the same operation
2432   CodeEmitInfo* first_info = visitor.info_at(0);
2433   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2434 
2435   for (int i = 0; i < visitor.info_count(); i++) {
2436     CodeEmitInfo* info = visitor.info_at(i);
2437     OopMap* oop_map = first_oop_map;
2438 
2439     // compute worst case interpreter size in case of a deoptimization
2440     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2441 
2442     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2443       // this info has a different number of locks then the precomputed oop map
2444       // (possible for lock and unlock instructions) -> compute oop map with
2445       // correct lock information
2446       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2447     }
2448 
2449     if (info->_oop_map == NULL) {
2450       info->_oop_map = oop_map;
2451     } else {
2452       // a CodeEmitInfo can not be shared between different LIR-instructions
2453       // because interval splitting can occur anywhere between two instructions
2454       // and so the oop maps must be different
2455       // -> check if the already set oop_map is exactly the one calculated for this operation
2456       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2457     }
2458   }
2459 }
2460 
2461 
2462 // frequently used constants
2463 // Allocate them with new so they are never destroyed (otherwise, a
2464 // forced exit could destroy these objects while they are still in
2465 // use).
2466 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2467 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2468 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(0);
2469 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2470 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2471 LocationValue*         _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2472 
2473 void LinearScan::init_compute_debug_info() {
2474   // cache for frequently used scope values
2475   // (cpu registers and stack slots)
2476   _scope_value_cache = ScopeValueArray((LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2, NULL);
2477 }
2478 
2479 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2480   Location loc;
2481   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2482     bailout("too large frame");
2483   }
2484   ScopeValue* object_scope_value = new LocationValue(loc);
2485 
2486   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2487     bailout("too large frame");
2488   }
2489   return new MonitorValue(object_scope_value, loc);
2490 }
2491 
2492 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2493   Location loc;
2494   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2495     bailout("too large frame");
2496   }
2497   return new LocationValue(loc);
2498 }
2499 
2500 
2501 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2502   assert(opr->is_constant(), "should not be called otherwise");
2503 
2504   LIR_Const* c = opr->as_constant_ptr();
2505   BasicType t = c->type();
2506   switch (t) {
2507     case T_OBJECT: {
2508       jobject value = c->as_jobject();
2509       if (value == NULL) {
2510         scope_values->append(_oop_null_scope_value);
2511       } else {
2512         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2513       }
2514       return 1;
2515     }
2516 
2517     case T_INT: // fall through
2518     case T_FLOAT: {
2519       int value = c->as_jint_bits();
2520       switch (value) {
2521         case -1: scope_values->append(_int_m1_scope_value); break;
2522         case 0:  scope_values->append(_int_0_scope_value); break;
2523         case 1:  scope_values->append(_int_1_scope_value); break;
2524         case 2:  scope_values->append(_int_2_scope_value); break;
2525         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2526       }
2527       return 1;
2528     }
2529 
2530     case T_LONG: // fall through
2531     case T_DOUBLE: {
2532 #ifdef _LP64
2533       scope_values->append(_int_0_scope_value);
2534       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2535 #else
2536       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2537         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2538         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2539       } else {
2540         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2541         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2542       }
2543 #endif
2544       return 2;
2545     }
2546 
2547     case T_ADDRESS: {
2548 #ifdef _LP64
2549       scope_values->append(new ConstantLongValue(c->as_jint()));
2550 #else
2551       scope_values->append(new ConstantIntValue(c->as_jint()));
2552 #endif
2553       return 1;
2554     }
2555 
2556     default:
2557       ShouldNotReachHere();
2558       return -1;
2559   }
2560 }
2561 
2562 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2563   if (opr->is_single_stack()) {
2564     int stack_idx = opr->single_stack_ix();
2565     bool is_oop = opr->is_oop_register();
2566     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2567 
2568     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2569     if (sv == NULL) {
2570       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2571       sv = location_for_name(stack_idx, loc_type);
2572       _scope_value_cache.at_put(cache_idx, sv);
2573     }
2574 
2575     // check if cached value is correct
2576     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2577 
2578     scope_values->append(sv);
2579     return 1;
2580 
2581   } else if (opr->is_single_cpu()) {
2582     bool is_oop = opr->is_oop_register();
2583     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2584     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2585 
2586     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2587     if (sv == NULL) {
2588       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2589       VMReg rname = frame_map()->regname(opr);
2590       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2591       _scope_value_cache.at_put(cache_idx, sv);
2592     }
2593 
2594     // check if cached value is correct
2595     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2596 
2597     scope_values->append(sv);
2598     return 1;
2599 
2600 #ifdef X86
2601   } else if (opr->is_single_xmm()) {
2602     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2603     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2604 
2605     scope_values->append(sv);
2606     return 1;
2607 #endif
2608 
2609   } else if (opr->is_single_fpu()) {
2610 #ifdef X86
2611     // the exact location of fpu stack values is only known
2612     // during fpu stack allocation, so the stack allocator object
2613     // must be present
2614     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2615     assert(_fpu_stack_allocator != NULL, "must be present");
2616     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2617 #endif
2618 
2619     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2620     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2621 #ifndef __SOFTFP__
2622 #ifndef VM_LITTLE_ENDIAN
2623     if (! float_saved_as_double) {
2624       // On big endian system, we may have an issue if float registers use only
2625       // the low half of the (same) double registers.
2626       // Both the float and the double could have the same regnr but would correspond
2627       // to two different addresses once saved.
2628 
2629       // get next safely (no assertion checks)
2630       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2631       if (next->is_reg() &&
2632           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2633         // the back-end does use the same numbering for the double and the float
2634         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2635       }
2636     }
2637 #endif
2638 #endif
2639     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2640 
2641     scope_values->append(sv);
2642     return 1;
2643 
2644   } else {
2645     // double-size operands
2646 
2647     ScopeValue* first;
2648     ScopeValue* second;
2649 
2650     if (opr->is_double_stack()) {
2651 #ifdef _LP64
2652       Location loc1;
2653       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2654       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2655         bailout("too large frame");
2656       }
2657       // Does this reverse on x86 vs. sparc?
2658       first =  new LocationValue(loc1);
2659       second = _int_0_scope_value;
2660 #else
2661       Location loc1, loc2;
2662       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2663         bailout("too large frame");
2664       }
2665       first =  new LocationValue(loc1);
2666       second = new LocationValue(loc2);
2667 #endif // _LP64
2668 
2669     } else if (opr->is_double_cpu()) {
2670 #ifdef _LP64
2671       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2672       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2673       second = _int_0_scope_value;
2674 #else
2675       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2676       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2677 
2678       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2679         // lo/hi and swapped relative to first and second, so swap them
2680         VMReg tmp = rname_first;
2681         rname_first = rname_second;
2682         rname_second = tmp;
2683       }
2684 
2685       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2686       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2687 #endif //_LP64
2688 
2689 
2690 #ifdef X86
2691     } else if (opr->is_double_xmm()) {
2692       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2693       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2694 #  ifdef _LP64
2695       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2696       second = _int_0_scope_value;
2697 #  else
2698       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2699       // %%% This is probably a waste but we'll keep things as they were for now
2700       if (true) {
2701         VMReg rname_second = rname_first->next();
2702         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2703       }
2704 #  endif
2705 #endif
2706 
2707     } else if (opr->is_double_fpu()) {
2708       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2709       // the double as float registers in the native ordering. On X86,
2710       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2711       // the low-order word of the double and fpu_regnrLo + 1 is the
2712       // name for the other half.  *first and *second must represent the
2713       // least and most significant words, respectively.
2714 
2715 #ifdef X86
2716       // the exact location of fpu stack values is only known
2717       // during fpu stack allocation, so the stack allocator object
2718       // must be present
2719       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2720       assert(_fpu_stack_allocator != NULL, "must be present");
2721       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2722 
2723       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2724 #endif
2725 #ifdef SPARC
2726       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2727 #endif
2728 #ifdef ARM32
2729       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2730 #endif
2731 #ifdef PPC32
2732       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2733 #endif
2734 
2735 #ifdef VM_LITTLE_ENDIAN
2736       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2737 #else
2738       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2739 #endif
2740 
2741 #ifdef _LP64
2742       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2743       second = _int_0_scope_value;
2744 #else
2745       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2746       // %%% This is probably a waste but we'll keep things as they were for now
2747       if (true) {
2748         VMReg rname_second = rname_first->next();
2749         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2750       }
2751 #endif
2752 
2753     } else {
2754       ShouldNotReachHere();
2755       first = NULL;
2756       second = NULL;
2757     }
2758 
2759     assert(first != NULL && second != NULL, "must be set");
2760     // The convention the interpreter uses is that the second local
2761     // holds the first raw word of the native double representation.
2762     // This is actually reasonable, since locals and stack arrays
2763     // grow downwards in all implementations.
2764     // (If, on some machine, the interpreter's Java locals or stack
2765     // were to grow upwards, the embedded doubles would be word-swapped.)
2766     scope_values->append(second);
2767     scope_values->append(first);
2768     return 2;
2769   }
2770 }
2771 
2772 
2773 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2774   if (value != NULL) {
2775     LIR_Opr opr = value->operand();
2776     Constant* con = value->as_Constant();
2777 
2778     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2779     assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2780 
2781     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2782       // Unpinned constants may have a virtual operand for a part of the lifetime
2783       // or may be illegal when it was optimized away,
2784       // so always use a constant operand
2785       opr = LIR_OprFact::value_type(con->type());
2786     }
2787     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2788 
2789     if (opr->is_virtual()) {
2790       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2791 
2792       BlockBegin* block = block_of_op_with_id(op_id);
2793       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2794         // generating debug information for the last instruction of a block.
2795         // if this instruction is a branch, spill moves are inserted before this branch
2796         // and so the wrong operand would be returned (spill moves at block boundaries are not
2797         // considered in the live ranges of intervals)
2798         // Solution: use the first op_id of the branch target block instead.
2799         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2800           if (block->live_out().at(opr->vreg_number())) {
2801             op_id = block->sux_at(0)->first_lir_instruction_id();
2802             mode = LIR_OpVisitState::outputMode;
2803           }
2804         }
2805       }
2806 
2807       // Get current location of operand
2808       // The operand must be live because debug information is considered when building the intervals
2809       // if the interval is not live, color_lir_opr will cause an assertion failure
2810       opr = color_lir_opr(opr, op_id, mode);
2811       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2812 
2813       // Append to ScopeValue array
2814       return append_scope_value_for_operand(opr, scope_values);
2815 
2816     } else {
2817       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2818       assert(opr->is_constant(), "operand must be constant");
2819 
2820       return append_scope_value_for_constant(opr, scope_values);
2821     }
2822   } else {
2823     // append a dummy value because real value not needed
2824     scope_values->append(_illegal_value);
2825     return 1;
2826   }
2827 }
2828 
2829 
2830 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2831   IRScopeDebugInfo* caller_debug_info = NULL;
2832 
2833   ValueStack* caller_state = cur_state->caller_state();
2834   if (caller_state != NULL) {
2835     // process recursively to compute outermost scope first
2836     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2837   }
2838 
2839   // initialize these to null.
2840   // If we don't need deopt info or there are no locals, expressions or monitors,
2841   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2842   GrowableArray<ScopeValue*>*   locals      = NULL;
2843   GrowableArray<ScopeValue*>*   expressions = NULL;
2844   GrowableArray<MonitorValue*>* monitors    = NULL;
2845 
2846   // describe local variable values
2847   int nof_locals = cur_state->locals_size();
2848   if (nof_locals > 0) {
2849     locals = new GrowableArray<ScopeValue*>(nof_locals);
2850 
2851     int pos = 0;
2852     while (pos < nof_locals) {
2853       assert(pos < cur_state->locals_size(), "why not?");
2854 
2855       Value local = cur_state->local_at(pos);
2856       pos += append_scope_value(op_id, local, locals);
2857 
2858       assert(locals->length() == pos, "must match");
2859     }
2860     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2861     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2862   } else if (cur_scope->method()->max_locals() > 0) {
2863     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2864     nof_locals = cur_scope->method()->max_locals();
2865     locals = new GrowableArray<ScopeValue*>(nof_locals);
2866     for(int i = 0; i < nof_locals; i++) {
2867       locals->append(_illegal_value);
2868     }
2869   }
2870 
2871   // describe expression stack
2872   int nof_stack = cur_state->stack_size();
2873   if (nof_stack > 0) {
2874     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2875 
2876     int pos = 0;
2877     while (pos < nof_stack) {
2878       Value expression = cur_state->stack_at_inc(pos);
2879       append_scope_value(op_id, expression, expressions);
2880 
2881       assert(expressions->length() == pos, "must match");
2882     }
2883     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2884   }
2885 
2886   // describe monitors
2887   int nof_locks = cur_state->locks_size();
2888   if (nof_locks > 0) {
2889     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2890     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2891     for (int i = 0; i < nof_locks; i++) {
2892       monitors->append(location_for_monitor_index(lock_offset + i));
2893     }
2894   }
2895 
2896   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2897 }
2898 
2899 
2900 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2901   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2902 
2903   IRScope* innermost_scope = info->scope();
2904   ValueStack* innermost_state = info->stack();
2905 
2906   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2907 
2908   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2909 
2910   if (info->_scope_debug_info == NULL) {
2911     // compute debug information
2912     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2913   } else {
2914     // debug information already set. Check that it is correct from the current point of view
2915     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2916   }
2917 }
2918 
2919 
2920 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2921   LIR_OpVisitState visitor;
2922   int num_inst = instructions->length();
2923   bool has_dead = false;
2924 
2925   for (int j = 0; j < num_inst; j++) {
2926     LIR_Op* op = instructions->at(j);
2927     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2928       has_dead = true;
2929       continue;
2930     }
2931     int op_id = op->id();
2932 
2933     // visit instruction to get list of operands
2934     visitor.visit(op);
2935 
2936     // iterate all modes of the visitor and process all virtual operands
2937     for_each_visitor_mode(mode) {
2938       int n = visitor.opr_count(mode);
2939       for (int k = 0; k < n; k++) {
2940         LIR_Opr opr = visitor.opr_at(mode, k);
2941         if (opr->is_virtual_register()) {
2942           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2943         }
2944       }
2945     }
2946 
2947     if (visitor.info_count() > 0) {
2948       // exception handling
2949       if (compilation()->has_exception_handlers()) {
2950         XHandlers* xhandlers = visitor.all_xhandler();
2951         int n = xhandlers->length();
2952         for (int k = 0; k < n; k++) {
2953           XHandler* handler = xhandlers->handler_at(k);
2954           if (handler->entry_code() != NULL) {
2955             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
2956           }
2957         }
2958       } else {
2959         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2960       }
2961 
2962       // compute oop map
2963       assert(iw != NULL, "needed for compute_oop_map");
2964       compute_oop_map(iw, visitor, op);
2965 
2966       // compute debug information
2967       if (!use_fpu_stack_allocation()) {
2968         // compute debug information if fpu stack allocation is not needed.
2969         // when fpu stack allocation is needed, the debug information can not
2970         // be computed here because the exact location of fpu operands is not known
2971         // -> debug information is created inside the fpu stack allocator
2972         int n = visitor.info_count();
2973         for (int k = 0; k < n; k++) {
2974           compute_debug_info(visitor.info_at(k), op_id);
2975         }
2976       }
2977     }
2978 
2979 #ifdef ASSERT
2980     // make sure we haven't made the op invalid.
2981     op->verify();
2982 #endif
2983 
2984     // remove useless moves
2985     if (op->code() == lir_move) {
2986       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
2987       LIR_Op1* move = (LIR_Op1*)op;
2988       LIR_Opr src = move->in_opr();
2989       LIR_Opr dst = move->result_opr();
2990       if (dst == src ||
2991           !dst->is_pointer() && !src->is_pointer() &&
2992           src->is_same_register(dst)) {
2993         instructions->at_put(j, NULL);
2994         has_dead = true;
2995       }
2996     }
2997   }
2998 
2999   if (has_dead) {
3000     // iterate all instructions of the block and remove all null-values.
3001     int insert_point = 0;
3002     for (int j = 0; j < num_inst; j++) {
3003       LIR_Op* op = instructions->at(j);
3004       if (op != NULL) {
3005         if (insert_point != j) {
3006           instructions->at_put(insert_point, op);
3007         }
3008         insert_point++;
3009       }
3010     }
3011     instructions->truncate(insert_point);
3012   }
3013 }
3014 
3015 void LinearScan::assign_reg_num() {
3016   TIME_LINEAR_SCAN(timer_assign_reg_num);
3017 
3018   init_compute_debug_info();
3019   IntervalWalker* iw = init_compute_oop_maps();
3020 
3021   int num_blocks = block_count();
3022   for (int i = 0; i < num_blocks; i++) {
3023     BlockBegin* block = block_at(i);
3024     assign_reg_num(block->lir()->instructions_list(), iw);
3025   }
3026 }
3027 
3028 
3029 void LinearScan::do_linear_scan() {
3030   NOT_PRODUCT(_total_timer.begin_method());
3031 
3032   number_instructions();
3033 
3034   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3035 
3036   compute_local_live_sets();
3037   compute_global_live_sets();
3038   CHECK_BAILOUT();
3039 
3040   build_intervals();
3041   CHECK_BAILOUT();
3042   sort_intervals_before_allocation();
3043 
3044   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3045   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3046 
3047   allocate_registers();
3048   CHECK_BAILOUT();
3049 
3050   resolve_data_flow();
3051   if (compilation()->has_exception_handlers()) {
3052     resolve_exception_handlers();
3053   }
3054   // fill in number of spill slots into frame_map
3055   propagate_spill_slots();
3056   CHECK_BAILOUT();
3057 
3058   NOT_PRODUCT(print_intervals("After Register Allocation"));
3059   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3060 
3061   sort_intervals_after_allocation();
3062 
3063   DEBUG_ONLY(verify());
3064 
3065   eliminate_spill_moves();
3066   assign_reg_num();
3067   CHECK_BAILOUT();
3068 
3069   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3070   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3071 
3072   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3073 
3074     if (use_fpu_stack_allocation()) {
3075       allocate_fpu_stack(); // Only has effect on Intel
3076       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3077     }
3078   }
3079 
3080   { TIME_LINEAR_SCAN(timer_optimize_lir);
3081 
3082     EdgeMoveOptimizer::optimize(ir()->code());
3083     ControlFlowOptimizer::optimize(ir()->code());
3084     // check that cfg is still correct after optimizations
3085     ir()->verify();
3086   }
3087 
3088   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3089   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3090   NOT_PRODUCT(_total_timer.end_method(this));
3091 }
3092 
3093 
3094 // ********** Printing functions
3095 
3096 #ifndef PRODUCT
3097 
3098 void LinearScan::print_timers(double total) {
3099   _total_timer.print(total);
3100 }
3101 
3102 void LinearScan::print_statistics() {
3103   _stat_before_alloc.print("before allocation");
3104   _stat_after_asign.print("after assignment of register");
3105   _stat_final.print("after optimization");
3106 }
3107 
3108 void LinearScan::print_bitmap(BitMap& b) {
3109   for (unsigned int i = 0; i < b.size(); i++) {
3110     if (b.at(i)) tty->print("%d ", i);
3111   }
3112   tty->cr();
3113 }
3114 
3115 void LinearScan::print_intervals(const char* label) {
3116   if (TraceLinearScanLevel >= 1) {
3117     int i;
3118     tty->cr();
3119     tty->print_cr("%s", label);
3120 
3121     for (i = 0; i < interval_count(); i++) {
3122       Interval* interval = interval_at(i);
3123       if (interval != NULL) {
3124         interval->print();
3125       }
3126     }
3127 
3128     tty->cr();
3129     tty->print_cr("--- Basic Blocks ---");
3130     for (i = 0; i < block_count(); i++) {
3131       BlockBegin* block = block_at(i);
3132       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3133     }
3134     tty->cr();
3135     tty->cr();
3136   }
3137 
3138   if (PrintCFGToFile) {
3139     CFGPrinter::print_intervals(&_intervals, label);
3140   }
3141 }
3142 
3143 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3144   if (TraceLinearScanLevel >= level) {
3145     tty->cr();
3146     tty->print_cr("%s", label);
3147     print_LIR(ir()->linear_scan_order());
3148     tty->cr();
3149   }
3150 
3151   if (level == 1 && PrintCFGToFile) {
3152     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3153   }
3154 }
3155 
3156 #endif //PRODUCT
3157 
3158 
3159 // ********** verification functions for allocation
3160 // (check that all intervals have a correct register and that no registers are overwritten)
3161 #ifdef ASSERT
3162 
3163 void LinearScan::verify() {
3164   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3165   verify_intervals();
3166 
3167   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3168   verify_no_oops_in_fixed_intervals();
3169 
3170   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3171   verify_constants();
3172 
3173   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3174   verify_registers();
3175 
3176   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3177 }
3178 
3179 void LinearScan::verify_intervals() {
3180   int len = interval_count();
3181   bool has_error = false;
3182 
3183   for (int i = 0; i < len; i++) {
3184     Interval* i1 = interval_at(i);
3185     if (i1 == NULL) continue;
3186 
3187     i1->check_split_children();
3188 
3189     if (i1->reg_num() != i) {
3190       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3191       has_error = true;
3192     }
3193 
3194     if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3195       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3196       has_error = true;
3197     }
3198 
3199     if (i1->assigned_reg() == any_reg) {
3200       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3201       has_error = true;
3202     }
3203 
3204     if (i1->assigned_reg() == i1->assigned_regHi()) {
3205       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3206       has_error = true;
3207     }
3208 
3209     if (!is_processed_reg_num(i1->assigned_reg())) {
3210       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3211       has_error = true;
3212     }
3213 
3214     if (i1->first() == Range::end()) {
3215       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3216       has_error = true;
3217     }
3218 
3219     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3220       if (r->from() >= r->to()) {
3221         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3222         has_error = true;
3223       }
3224     }
3225 
3226     for (int j = i + 1; j < len; j++) {
3227       Interval* i2 = interval_at(j);
3228       if (i2 == NULL) continue;
3229 
3230       // special intervals that are created in MoveResolver
3231       // -> ignore them because the range information has no meaning there
3232       if (i1->from() == 1 && i1->to() == 2) continue;
3233       if (i2->from() == 1 && i2->to() == 2) continue;
3234 
3235       int r1 = i1->assigned_reg();
3236       int r1Hi = i1->assigned_regHi();
3237       int r2 = i2->assigned_reg();
3238       int r2Hi = i2->assigned_regHi();
3239       if (i1->intersects(i2) && (r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi)))) {
3240         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3241         i1->print(); tty->cr();
3242         i2->print(); tty->cr();
3243         has_error = true;
3244       }
3245     }
3246   }
3247 
3248   assert(has_error == false, "register allocation invalid");
3249 }
3250 
3251 
3252 void LinearScan::verify_no_oops_in_fixed_intervals() {
3253   Interval* fixed_intervals;
3254   Interval* other_intervals;
3255   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3256 
3257   // to ensure a walking until the last instruction id, add a dummy interval
3258   // with a high operation id
3259   other_intervals = new Interval(any_reg);
3260   other_intervals->add_range(max_jint - 2, max_jint - 1);
3261   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3262 
3263   LIR_OpVisitState visitor;
3264   for (int i = 0; i < block_count(); i++) {
3265     BlockBegin* block = block_at(i);
3266 
3267     LIR_OpList* instructions = block->lir()->instructions_list();
3268 
3269     for (int j = 0; j < instructions->length(); j++) {
3270       LIR_Op* op = instructions->at(j);
3271       int op_id = op->id();
3272 
3273       visitor.visit(op);
3274 
3275       if (visitor.info_count() > 0) {
3276         iw->walk_before(op->id());
3277         bool check_live = true;
3278         if (op->code() == lir_move) {
3279           LIR_Op1* move = (LIR_Op1*)op;
3280           check_live = (move->patch_code() == lir_patch_none);
3281         }
3282         LIR_OpBranch* branch = op->as_OpBranch();
3283         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3284           // Don't bother checking the stub in this case since the
3285           // exception stub will never return to normal control flow.
3286           check_live = false;
3287         }
3288 
3289         // Make sure none of the fixed registers is live across an
3290         // oopmap since we can't handle that correctly.
3291         if (check_live) {
3292           for (Interval* interval = iw->active_first(fixedKind);
3293                interval != Interval::end();
3294                interval = interval->next()) {
3295             if (interval->current_to() > op->id() + 1) {
3296               // This interval is live out of this op so make sure
3297               // that this interval represents some value that's
3298               // referenced by this op either as an input or output.
3299               bool ok = false;
3300               for_each_visitor_mode(mode) {
3301                 int n = visitor.opr_count(mode);
3302                 for (int k = 0; k < n; k++) {
3303                   LIR_Opr opr = visitor.opr_at(mode, k);
3304                   if (opr->is_fixed_cpu()) {
3305                     if (interval_at(reg_num(opr)) == interval) {
3306                       ok = true;
3307                       break;
3308                     }
3309                     int hi = reg_numHi(opr);
3310                     if (hi != -1 && interval_at(hi) == interval) {
3311                       ok = true;
3312                       break;
3313                     }
3314                   }
3315                 }
3316               }
3317               assert(ok, "fixed intervals should never be live across an oopmap point");
3318             }
3319           }
3320         }
3321       }
3322 
3323       // oop-maps at calls do not contain registers, so check is not needed
3324       if (!visitor.has_call()) {
3325 
3326         for_each_visitor_mode(mode) {
3327           int n = visitor.opr_count(mode);
3328           for (int k = 0; k < n; k++) {
3329             LIR_Opr opr = visitor.opr_at(mode, k);
3330 
3331             if (opr->is_fixed_cpu() && opr->is_oop()) {
3332               // operand is a non-virtual cpu register and contains an oop
3333               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3334 
3335               Interval* interval = interval_at(reg_num(opr));
3336               assert(interval != NULL, "no interval");
3337 
3338               if (mode == LIR_OpVisitState::inputMode) {
3339                 if (interval->to() >= op_id + 1) {
3340                   assert(interval->to() < op_id + 2 ||
3341                          interval->has_hole_between(op_id, op_id + 2),
3342                          "oop input operand live after instruction");
3343                 }
3344               } else if (mode == LIR_OpVisitState::outputMode) {
3345                 if (interval->from() <= op_id - 1) {
3346                   assert(interval->has_hole_between(op_id - 1, op_id),
3347                          "oop input operand live after instruction");
3348                 }
3349               }
3350             }
3351           }
3352         }
3353       }
3354     }
3355   }
3356 }
3357 
3358 
3359 void LinearScan::verify_constants() {
3360   int num_regs = num_virtual_regs();
3361   int size = live_set_size();
3362   int num_blocks = block_count();
3363 
3364   for (int i = 0; i < num_blocks; i++) {
3365     BlockBegin* block = block_at(i);
3366     BitMap live_at_edge = block->live_in();
3367 
3368     // visit all registers where the live_at_edge bit is set
3369     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3370       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3371 
3372       Value value = gen()->instruction_for_vreg(r);
3373 
3374       assert(value != NULL, "all intervals live across block boundaries must have Value");
3375       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3376       assert(value->operand()->vreg_number() == r, "register number must match");
3377       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3378     }
3379   }
3380 }
3381 
3382 
3383 class RegisterVerifier: public StackObj {
3384  private:
3385   LinearScan*   _allocator;
3386   BlockList     _work_list;      // all blocks that must be processed
3387   IntervalsList _saved_states;   // saved information of previous check
3388 
3389   // simplified access to methods of LinearScan
3390   Compilation*  compilation() const              { return _allocator->compilation(); }
3391   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3392   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3393 
3394   // currently, only registers are processed
3395   int           state_size()                     { return LinearScan::nof_regs; }
3396 
3397   // accessors
3398   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3399   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3400   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3401 
3402   // helper functions
3403   IntervalList* copy(IntervalList* input_state);
3404   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3405   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3406 
3407   void process_block(BlockBegin* block);
3408   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3409   void process_successor(BlockBegin* block, IntervalList* input_state);
3410   void process_operations(LIR_List* ops, IntervalList* input_state);
3411 
3412  public:
3413   RegisterVerifier(LinearScan* allocator)
3414     : _allocator(allocator)
3415     , _work_list(16)
3416     , _saved_states(BlockBegin::number_of_blocks(), NULL)
3417   { }
3418 
3419   void verify(BlockBegin* start);
3420 };
3421 
3422 
3423 // entry function from LinearScan that starts the verification
3424 void LinearScan::verify_registers() {
3425   RegisterVerifier verifier(this);
3426   verifier.verify(block_at(0));
3427 }
3428 
3429 
3430 void RegisterVerifier::verify(BlockBegin* start) {
3431   // setup input registers (method arguments) for first block
3432   IntervalList* input_state = new IntervalList(state_size(), NULL);
3433   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3434   for (int n = 0; n < args->length(); n++) {
3435     LIR_Opr opr = args->at(n);
3436     if (opr->is_register()) {
3437       Interval* interval = interval_at(reg_num(opr));
3438 
3439       if (interval->assigned_reg() < state_size()) {
3440         input_state->at_put(interval->assigned_reg(), interval);
3441       }
3442       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3443         input_state->at_put(interval->assigned_regHi(), interval);
3444       }
3445     }
3446   }
3447 
3448   set_state_for_block(start, input_state);
3449   add_to_work_list(start);
3450 
3451   // main loop for verification
3452   do {
3453     BlockBegin* block = _work_list.at(0);
3454     _work_list.remove_at(0);
3455 
3456     process_block(block);
3457   } while (!_work_list.is_empty());
3458 }
3459 
3460 void RegisterVerifier::process_block(BlockBegin* block) {
3461   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3462 
3463   // must copy state because it is modified
3464   IntervalList* input_state = copy(state_for_block(block));
3465 
3466   if (TraceLinearScanLevel >= 4) {
3467     tty->print_cr("Input-State of intervals:");
3468     tty->print("    ");
3469     for (int i = 0; i < state_size(); i++) {
3470       if (input_state->at(i) != NULL) {
3471         tty->print(" %4d", input_state->at(i)->reg_num());
3472       } else {
3473         tty->print("   __");
3474       }
3475     }
3476     tty->cr();
3477     tty->cr();
3478   }
3479 
3480   // process all operations of the block
3481   process_operations(block->lir(), input_state);
3482 
3483   // iterate all successors
3484   for (int i = 0; i < block->number_of_sux(); i++) {
3485     process_successor(block->sux_at(i), input_state);
3486   }
3487 }
3488 
3489 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3490   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3491 
3492   // must copy state because it is modified
3493   input_state = copy(input_state);
3494 
3495   if (xhandler->entry_code() != NULL) {
3496     process_operations(xhandler->entry_code(), input_state);
3497   }
3498   process_successor(xhandler->entry_block(), input_state);
3499 }
3500 
3501 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3502   IntervalList* saved_state = state_for_block(block);
3503 
3504   if (saved_state != NULL) {
3505     // this block was already processed before.
3506     // check if new input_state is consistent with saved_state
3507 
3508     bool saved_state_correct = true;
3509     for (int i = 0; i < state_size(); i++) {
3510       if (input_state->at(i) != saved_state->at(i)) {
3511         // current input_state and previous saved_state assume a different
3512         // interval in this register -> assume that this register is invalid
3513         if (saved_state->at(i) != NULL) {
3514           // invalidate old calculation only if it assumed that
3515           // register was valid. when the register was already invalid,
3516           // then the old calculation was correct.
3517           saved_state_correct = false;
3518           saved_state->at_put(i, NULL);
3519 
3520           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3521         }
3522       }
3523     }
3524 
3525     if (saved_state_correct) {
3526       // already processed block with correct input_state
3527       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3528     } else {
3529       // must re-visit this block
3530       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3531       add_to_work_list(block);
3532     }
3533 
3534   } else {
3535     // block was not processed before, so set initial input_state
3536     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3537 
3538     set_state_for_block(block, copy(input_state));
3539     add_to_work_list(block);
3540   }
3541 }
3542 
3543 
3544 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3545   IntervalList* copy_state = new IntervalList(input_state->length());
3546   copy_state->push_all(input_state);
3547   return copy_state;
3548 }
3549 
3550 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3551   if (reg != LinearScan::any_reg && reg < state_size()) {
3552     if (interval != NULL) {
3553       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3554     } else if (input_state->at(reg) != NULL) {
3555       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3556     }
3557 
3558     input_state->at_put(reg, interval);
3559   }
3560 }
3561 
3562 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3563   if (reg != LinearScan::any_reg && reg < state_size()) {
3564     if (input_state->at(reg) != interval) {
3565       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3566       return true;
3567     }
3568   }
3569   return false;
3570 }
3571 
3572 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3573   // visit all instructions of the block
3574   LIR_OpVisitState visitor;
3575   bool has_error = false;
3576 
3577   for (int i = 0; i < ops->length(); i++) {
3578     LIR_Op* op = ops->at(i);
3579     visitor.visit(op);
3580 
3581     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3582 
3583     // check if input operands are correct
3584     int j;
3585     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3586     for (j = 0; j < n; j++) {
3587       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3588       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3589         Interval* interval = interval_at(reg_num(opr));
3590         if (op->id() != -1) {
3591           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3592         }
3593 
3594         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3595         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3596 
3597         // When an operand is marked with is_last_use, then the fpu stack allocator
3598         // removes the register from the fpu stack -> the register contains no value
3599         if (opr->is_last_use()) {
3600           state_put(input_state, interval->assigned_reg(),   NULL);
3601           state_put(input_state, interval->assigned_regHi(), NULL);
3602         }
3603       }
3604     }
3605 
3606     // invalidate all caller save registers at calls
3607     if (visitor.has_call()) {
3608       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3609         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3610       }
3611       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3612         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3613       }
3614 
3615 #ifdef X86
3616       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3617       for (j = 0; j < num_caller_save_xmm_regs; j++) {
3618         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3619       }
3620 #endif
3621     }
3622 
3623     // process xhandler before output and temp operands
3624     XHandlers* xhandlers = visitor.all_xhandler();
3625     n = xhandlers->length();
3626     for (int k = 0; k < n; k++) {
3627       process_xhandler(xhandlers->handler_at(k), input_state);
3628     }
3629 
3630     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3631     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3632     for (j = 0; j < n; j++) {
3633       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3634       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3635         Interval* interval = interval_at(reg_num(opr));
3636         if (op->id() != -1) {
3637           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3638         }
3639 
3640         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3641         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3642       }
3643     }
3644 
3645     // set output operands
3646     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3647     for (j = 0; j < n; j++) {
3648       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3649       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3650         Interval* interval = interval_at(reg_num(opr));
3651         if (op->id() != -1) {
3652           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3653         }
3654 
3655         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3656         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3657       }
3658     }
3659   }
3660   assert(has_error == false, "Error in register allocation");
3661 }
3662 
3663 #endif // ASSERT
3664 
3665 
3666 
3667 // **** Implementation of MoveResolver ******************************
3668 
3669 MoveResolver::MoveResolver(LinearScan* allocator) :
3670   _allocator(allocator),
3671   _multiple_reads_allowed(false),
3672   _mapping_from(8),
3673   _mapping_from_opr(8),
3674   _mapping_to(8),
3675   _insert_list(NULL),
3676   _insert_idx(-1),
3677   _insertion_buffer()
3678 {
3679   for (int i = 0; i < LinearScan::nof_regs; i++) {
3680     _register_blocked[i] = 0;
3681   }
3682   DEBUG_ONLY(check_empty());
3683 }
3684 
3685 
3686 #ifdef ASSERT
3687 
3688 void MoveResolver::check_empty() {
3689   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3690   for (int i = 0; i < LinearScan::nof_regs; i++) {
3691     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3692   }
3693   assert(_multiple_reads_allowed == false, "must have default value");
3694 }
3695 
3696 void MoveResolver::verify_before_resolve() {
3697   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3698   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3699   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3700 
3701   int i, j;
3702   if (!_multiple_reads_allowed) {
3703     for (i = 0; i < _mapping_from.length(); i++) {
3704       for (j = i + 1; j < _mapping_from.length(); j++) {
3705         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3706       }
3707     }
3708   }
3709 
3710   for (i = 0; i < _mapping_to.length(); i++) {
3711     for (j = i + 1; j < _mapping_to.length(); j++) {
3712       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3713     }
3714   }
3715 
3716 
3717   BitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3718   used_regs.clear();
3719   if (!_multiple_reads_allowed) {
3720     for (i = 0; i < _mapping_from.length(); i++) {
3721       Interval* it = _mapping_from.at(i);
3722       if (it != NULL) {
3723         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3724         used_regs.set_bit(it->assigned_reg());
3725 
3726         if (it->assigned_regHi() != LinearScan::any_reg) {
3727           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3728           used_regs.set_bit(it->assigned_regHi());
3729         }
3730       }
3731     }
3732   }
3733 
3734   used_regs.clear();
3735   for (i = 0; i < _mapping_to.length(); i++) {
3736     Interval* it = _mapping_to.at(i);
3737     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3738     used_regs.set_bit(it->assigned_reg());
3739 
3740     if (it->assigned_regHi() != LinearScan::any_reg) {
3741       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3742       used_regs.set_bit(it->assigned_regHi());
3743     }
3744   }
3745 
3746   used_regs.clear();
3747   for (i = 0; i < _mapping_from.length(); i++) {
3748     Interval* it = _mapping_from.at(i);
3749     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3750       used_regs.set_bit(it->assigned_reg());
3751     }
3752   }
3753   for (i = 0; i < _mapping_to.length(); i++) {
3754     Interval* it = _mapping_to.at(i);
3755     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3756   }
3757 }
3758 
3759 #endif // ASSERT
3760 
3761 
3762 // mark assigned_reg and assigned_regHi of the interval as blocked
3763 void MoveResolver::block_registers(Interval* it) {
3764   int reg = it->assigned_reg();
3765   if (reg < LinearScan::nof_regs) {
3766     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3767     set_register_blocked(reg, 1);
3768   }
3769   reg = it->assigned_regHi();
3770   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3771     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3772     set_register_blocked(reg, 1);
3773   }
3774 }
3775 
3776 // mark assigned_reg and assigned_regHi of the interval as unblocked
3777 void MoveResolver::unblock_registers(Interval* it) {
3778   int reg = it->assigned_reg();
3779   if (reg < LinearScan::nof_regs) {
3780     assert(register_blocked(reg) > 0, "register already marked as unused");
3781     set_register_blocked(reg, -1);
3782   }
3783   reg = it->assigned_regHi();
3784   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3785     assert(register_blocked(reg) > 0, "register already marked as unused");
3786     set_register_blocked(reg, -1);
3787   }
3788 }
3789 
3790 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3791 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3792   int from_reg = -1;
3793   int from_regHi = -1;
3794   if (from != NULL) {
3795     from_reg = from->assigned_reg();
3796     from_regHi = from->assigned_regHi();
3797   }
3798 
3799   int reg = to->assigned_reg();
3800   if (reg < LinearScan::nof_regs) {
3801     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3802       return false;
3803     }
3804   }
3805   reg = to->assigned_regHi();
3806   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3807     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3808       return false;
3809     }
3810   }
3811 
3812   return true;
3813 }
3814 
3815 
3816 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3817   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3818   _insertion_buffer.init(list);
3819 }
3820 
3821 void MoveResolver::append_insertion_buffer() {
3822   if (_insertion_buffer.initialized()) {
3823     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3824   }
3825   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3826 
3827   _insert_list = NULL;
3828   _insert_idx = -1;
3829 }
3830 
3831 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3832   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3833   assert(from_interval->type() == to_interval->type(), "move between different types");
3834   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3835   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3836 
3837   LIR_Opr from_opr = LIR_OprFact::virtual_register(from_interval->reg_num(), from_interval->type());
3838   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3839 
3840   if (!_multiple_reads_allowed) {
3841     // the last_use flag is an optimization for FPU stack allocation. When the same
3842     // input interval is used in more than one move, then it is too difficult to determine
3843     // if this move is really the last use.
3844     from_opr = from_opr->make_last_use();
3845   }
3846   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3847 
3848   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3849 }
3850 
3851 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3852   assert(from_opr->type() == to_interval->type(), "move between different types");
3853   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3854   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3855 
3856   LIR_Opr to_opr = LIR_OprFact::virtual_register(to_interval->reg_num(), to_interval->type());
3857   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3858 
3859   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3860 }
3861 
3862 
3863 void MoveResolver::resolve_mappings() {
3864   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3865   DEBUG_ONLY(verify_before_resolve());
3866 
3867   // Block all registers that are used as input operands of a move.
3868   // When a register is blocked, no move to this register is emitted.
3869   // This is necessary for detecting cycles in moves.
3870   int i;
3871   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3872     Interval* from_interval = _mapping_from.at(i);
3873     if (from_interval != NULL) {
3874       block_registers(from_interval);
3875     }
3876   }
3877 
3878   int spill_candidate = -1;
3879   while (_mapping_from.length() > 0) {
3880     bool processed_interval = false;
3881 
3882     for (i = _mapping_from.length() - 1; i >= 0; i--) {
3883       Interval* from_interval = _mapping_from.at(i);
3884       Interval* to_interval = _mapping_to.at(i);
3885 
3886       if (save_to_process_move(from_interval, to_interval)) {
3887         // this inverval can be processed because target is free
3888         if (from_interval != NULL) {
3889           insert_move(from_interval, to_interval);
3890           unblock_registers(from_interval);
3891         } else {
3892           insert_move(_mapping_from_opr.at(i), to_interval);
3893         }
3894         _mapping_from.remove_at(i);
3895         _mapping_from_opr.remove_at(i);
3896         _mapping_to.remove_at(i);
3897 
3898         processed_interval = true;
3899       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
3900         // this interval cannot be processed now because target is not free
3901         // it starts in a register, so it is a possible candidate for spilling
3902         spill_candidate = i;
3903       }
3904     }
3905 
3906     if (!processed_interval) {
3907       // no move could be processed because there is a cycle in the move list
3908       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
3909       assert(spill_candidate != -1, "no interval in register for spilling found");
3910 
3911       // create a new spill interval and assign a stack slot to it
3912       Interval* from_interval = _mapping_from.at(spill_candidate);
3913       Interval* spill_interval = new Interval(-1);
3914       spill_interval->set_type(from_interval->type());
3915 
3916       // add a dummy range because real position is difficult to calculate
3917       // Note: this range is a special case when the integrity of the allocation is checked
3918       spill_interval->add_range(1, 2);
3919 
3920       //       do not allocate a new spill slot for temporary interval, but
3921       //       use spill slot assigned to from_interval. Otherwise moves from
3922       //       one stack slot to another can happen (not allowed by LIR_Assembler
3923       int spill_slot = from_interval->canonical_spill_slot();
3924       if (spill_slot < 0) {
3925         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
3926         from_interval->set_canonical_spill_slot(spill_slot);
3927       }
3928       spill_interval->assign_reg(spill_slot);
3929       allocator()->append_interval(spill_interval);
3930 
3931       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
3932 
3933       // insert a move from register to stack and update the mapping
3934       insert_move(from_interval, spill_interval);
3935       _mapping_from.at_put(spill_candidate, spill_interval);
3936       unblock_registers(from_interval);
3937     }
3938   }
3939 
3940   // reset to default value
3941   _multiple_reads_allowed = false;
3942 
3943   // check that all intervals have been processed
3944   DEBUG_ONLY(check_empty());
3945 }
3946 
3947 
3948 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
3949   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3950   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
3951 
3952   create_insertion_buffer(insert_list);
3953   _insert_list = insert_list;
3954   _insert_idx = insert_idx;
3955 }
3956 
3957 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
3958   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
3959 
3960   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
3961     // insert position changed -> resolve current mappings
3962     resolve_mappings();
3963   }
3964 
3965   if (insert_list != _insert_list) {
3966     // block changed -> append insertion_buffer because it is
3967     // bound to a specific block and create a new insertion_buffer
3968     append_insertion_buffer();
3969     create_insertion_buffer(insert_list);
3970   }
3971 
3972   _insert_list = insert_list;
3973   _insert_idx = insert_idx;
3974 }
3975 
3976 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
3977   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3978 
3979   _mapping_from.append(from_interval);
3980   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
3981   _mapping_to.append(to_interval);
3982 }
3983 
3984 
3985 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
3986   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3987   assert(from_opr->is_constant(), "only for constants");
3988 
3989   _mapping_from.append(NULL);
3990   _mapping_from_opr.append(from_opr);
3991   _mapping_to.append(to_interval);
3992 }
3993 
3994 void MoveResolver::resolve_and_append_moves() {
3995   if (has_mappings()) {
3996     resolve_mappings();
3997   }
3998   append_insertion_buffer();
3999 }
4000 
4001 
4002 
4003 // **** Implementation of Range *************************************
4004 
4005 Range::Range(int from, int to, Range* next) :
4006   _from(from),
4007   _to(to),
4008   _next(next)
4009 {
4010 }
4011 
4012 // initialize sentinel
4013 Range* Range::_end = NULL;
4014 void Range::initialize(Arena* arena) {
4015   _end = new (arena) Range(max_jint, max_jint, NULL);
4016 }
4017 
4018 int Range::intersects_at(Range* r2) const {
4019   const Range* r1 = this;
4020 
4021   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4022   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4023 
4024   do {
4025     if (r1->from() < r2->from()) {
4026       if (r1->to() <= r2->from()) {
4027         r1 = r1->next(); if (r1 == _end) return -1;
4028       } else {
4029         return r2->from();
4030       }
4031     } else if (r2->from() < r1->from()) {
4032       if (r2->to() <= r1->from()) {
4033         r2 = r2->next(); if (r2 == _end) return -1;
4034       } else {
4035         return r1->from();
4036       }
4037     } else { // r1->from() == r2->from()
4038       if (r1->from() == r1->to()) {
4039         r1 = r1->next(); if (r1 == _end) return -1;
4040       } else if (r2->from() == r2->to()) {
4041         r2 = r2->next(); if (r2 == _end) return -1;
4042       } else {
4043         return r1->from();
4044       }
4045     }
4046   } while (true);
4047 }
4048 
4049 #ifndef PRODUCT
4050 void Range::print(outputStream* out) const {
4051   out->print("[%d, %d[ ", _from, _to);
4052 }
4053 #endif
4054 
4055 
4056 
4057 // **** Implementation of Interval **********************************
4058 
4059 // initialize sentinel
4060 Interval* Interval::_end = NULL;
4061 void Interval::initialize(Arena* arena) {
4062   Range::initialize(arena);
4063   _end = new (arena) Interval(-1);
4064 }
4065 
4066 Interval::Interval(int reg_num) :
4067   _reg_num(reg_num),
4068   _type(T_ILLEGAL),
4069   _first(Range::end()),
4070   _use_pos_and_kinds(12),
4071   _current(Range::end()),
4072   _next(_end),
4073   _state(invalidState),
4074   _assigned_reg(LinearScan::any_reg),
4075   _assigned_regHi(LinearScan::any_reg),
4076   _cached_to(-1),
4077   _cached_opr(LIR_OprFact::illegalOpr),
4078   _cached_vm_reg(VMRegImpl::Bad()),
4079   _split_children(0),
4080   _canonical_spill_slot(-1),
4081   _insert_move_when_activated(false),
4082   _register_hint(NULL),
4083   _spill_state(noDefinitionFound),
4084   _spill_definition_pos(-1)
4085 {
4086   _split_parent = this;
4087   _current_split_child = this;
4088 }
4089 
4090 int Interval::calc_to() {
4091   assert(_first != Range::end(), "interval has no range");
4092 
4093   Range* r = _first;
4094   while (r->next() != Range::end()) {
4095     r = r->next();
4096   }
4097   return r->to();
4098 }
4099 
4100 
4101 #ifdef ASSERT
4102 // consistency check of split-children
4103 void Interval::check_split_children() {
4104   if (_split_children.length() > 0) {
4105     assert(is_split_parent(), "only split parents can have children");
4106 
4107     for (int i = 0; i < _split_children.length(); i++) {
4108       Interval* i1 = _split_children.at(i);
4109 
4110       assert(i1->split_parent() == this, "not a split child of this interval");
4111       assert(i1->type() == type(), "must be equal for all split children");
4112       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4113 
4114       for (int j = i + 1; j < _split_children.length(); j++) {
4115         Interval* i2 = _split_children.at(j);
4116 
4117         assert(i1->reg_num() != i2->reg_num(), "same register number");
4118 
4119         if (i1->from() < i2->from()) {
4120           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4121         } else {
4122           assert(i2->from() < i1->from(), "intervals start at same op_id");
4123           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4124         }
4125       }
4126     }
4127   }
4128 }
4129 #endif // ASSERT
4130 
4131 Interval* Interval::register_hint(bool search_split_child) const {
4132   if (!search_split_child) {
4133     return _register_hint;
4134   }
4135 
4136   if (_register_hint != NULL) {
4137     assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4138 
4139     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4140       return _register_hint;
4141 
4142     } else if (_register_hint->_split_children.length() > 0) {
4143       // search the first split child that has a register assigned
4144       int len = _register_hint->_split_children.length();
4145       for (int i = 0; i < len; i++) {
4146         Interval* cur = _register_hint->_split_children.at(i);
4147 
4148         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4149           return cur;
4150         }
4151       }
4152     }
4153   }
4154 
4155   // no hint interval found that has a register assigned
4156   return NULL;
4157 }
4158 
4159 
4160 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4161   assert(is_split_parent(), "can only be called for split parents");
4162   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4163 
4164   Interval* result;
4165   if (_split_children.length() == 0) {
4166     result = this;
4167   } else {
4168     result = NULL;
4169     int len = _split_children.length();
4170 
4171     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4172     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4173 
4174     int i;
4175     for (i = 0; i < len; i++) {
4176       Interval* cur = _split_children.at(i);
4177       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4178         if (i > 0) {
4179           // exchange current split child to start of list (faster access for next call)
4180           _split_children.at_put(i, _split_children.at(0));
4181           _split_children.at_put(0, cur);
4182         }
4183 
4184         // interval found
4185         result = cur;
4186         break;
4187       }
4188     }
4189 
4190 #ifdef ASSERT
4191     for (i = 0; i < len; i++) {
4192       Interval* tmp = _split_children.at(i);
4193       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4194         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4195         result->print();
4196         tmp->print();
4197         assert(false, "two valid result intervals found");
4198       }
4199     }
4200 #endif
4201   }
4202 
4203   assert(result != NULL, "no matching interval found");
4204   assert(result->covers(op_id, mode), "op_id not covered by interval");
4205 
4206   return result;
4207 }
4208 
4209 
4210 // returns the last split child that ends before the given op_id
4211 Interval* Interval::split_child_before_op_id(int op_id) {
4212   assert(op_id >= 0, "invalid op_id");
4213 
4214   Interval* parent = split_parent();
4215   Interval* result = NULL;
4216 
4217   int len = parent->_split_children.length();
4218   assert(len > 0, "no split children available");
4219 
4220   for (int i = len - 1; i >= 0; i--) {
4221     Interval* cur = parent->_split_children.at(i);
4222     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4223       result = cur;
4224     }
4225   }
4226 
4227   assert(result != NULL, "no split child found");
4228   return result;
4229 }
4230 
4231 
4232 // checks if op_id is covered by any split child
4233 bool Interval::split_child_covers(int op_id, LIR_OpVisitState::OprMode mode) {
4234   assert(is_split_parent(), "can only be called for split parents");
4235   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4236 
4237   if (_split_children.length() == 0) {
4238     // simple case if interval was not split
4239     return covers(op_id, mode);
4240 
4241   } else {
4242     // extended case: check all split children
4243     int len = _split_children.length();
4244     for (int i = 0; i < len; i++) {
4245       Interval* cur = _split_children.at(i);
4246       if (cur->covers(op_id, mode)) {
4247         return true;
4248       }
4249     }
4250     return false;
4251   }
4252 }
4253 
4254 
4255 // Note: use positions are sorted descending -> first use has highest index
4256 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4257   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4258 
4259   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4260     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4261       return _use_pos_and_kinds.at(i);
4262     }
4263   }
4264   return max_jint;
4265 }
4266 
4267 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4268   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4269 
4270   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4271     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4272       return _use_pos_and_kinds.at(i);
4273     }
4274   }
4275   return max_jint;
4276 }
4277 
4278 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4279   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4280 
4281   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4282     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4283       return _use_pos_and_kinds.at(i);
4284     }
4285   }
4286   return max_jint;
4287 }
4288 
4289 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4290   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4291 
4292   int prev = 0;
4293   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4294     if (_use_pos_and_kinds.at(i) > from) {
4295       return prev;
4296     }
4297     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4298       prev = _use_pos_and_kinds.at(i);
4299     }
4300   }
4301   return prev;
4302 }
4303 
4304 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4305   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4306 
4307   // do not add use positions for precolored intervals because
4308   // they are never used
4309   if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4310 #ifdef ASSERT
4311     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4312     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4313       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4314       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4315       if (i > 0) {
4316         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4317       }
4318     }
4319 #endif
4320 
4321     // Note: add_use is called in descending order, so list gets sorted
4322     //       automatically by just appending new use positions
4323     int len = _use_pos_and_kinds.length();
4324     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4325       _use_pos_and_kinds.append(pos);
4326       _use_pos_and_kinds.append(use_kind);
4327     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4328       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4329       _use_pos_and_kinds.at_put(len - 1, use_kind);
4330     }
4331   }
4332 }
4333 
4334 void Interval::add_range(int from, int to) {
4335   assert(from < to, "invalid range");
4336   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4337   assert(from <= first()->to(), "not inserting at begin of interval");
4338 
4339   if (first()->from() <= to) {
4340     // join intersecting ranges
4341     first()->set_from(MIN2(from, first()->from()));
4342     first()->set_to  (MAX2(to,   first()->to()));
4343   } else {
4344     // insert new range
4345     _first = new Range(from, to, first());
4346   }
4347 }
4348 
4349 Interval* Interval::new_split_child() {
4350   // allocate new interval
4351   Interval* result = new Interval(-1);
4352   result->set_type(type());
4353 
4354   Interval* parent = split_parent();
4355   result->_split_parent = parent;
4356   result->set_register_hint(parent);
4357 
4358   // insert new interval in children-list of parent
4359   if (parent->_split_children.length() == 0) {
4360     assert(is_split_parent(), "list must be initialized at first split");
4361 
4362     parent->_split_children = IntervalList(4);
4363     parent->_split_children.append(this);
4364   }
4365   parent->_split_children.append(result);
4366 
4367   return result;
4368 }
4369 
4370 // split this interval at the specified position and return
4371 // the remainder as a new interval.
4372 //
4373 // when an interval is split, a bi-directional link is established between the original interval
4374 // (the split parent) and the intervals that are split off this interval (the split children)
4375 // When a split child is split again, the new created interval is also a direct child
4376 // of the original parent (there is no tree of split children stored, but a flat list)
4377 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4378 //
4379 // Note: The new interval has no valid reg_num
4380 Interval* Interval::split(int split_pos) {
4381   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4382 
4383   // allocate new interval
4384   Interval* result = new_split_child();
4385 
4386   // split the ranges
4387   Range* prev = NULL;
4388   Range* cur = _first;
4389   while (cur != Range::end() && cur->to() <= split_pos) {
4390     prev = cur;
4391     cur = cur->next();
4392   }
4393   assert(cur != Range::end(), "split interval after end of last range");
4394 
4395   if (cur->from() < split_pos) {
4396     result->_first = new Range(split_pos, cur->to(), cur->next());
4397     cur->set_to(split_pos);
4398     cur->set_next(Range::end());
4399 
4400   } else {
4401     assert(prev != NULL, "split before start of first range");
4402     result->_first = cur;
4403     prev->set_next(Range::end());
4404   }
4405   result->_current = result->_first;
4406   _cached_to = -1; // clear cached value
4407 
4408   // split list of use positions
4409   int total_len = _use_pos_and_kinds.length();
4410   int start_idx = total_len - 2;
4411   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4412     start_idx -= 2;
4413   }
4414 
4415   intStack new_use_pos_and_kinds(total_len - start_idx);
4416   int i;
4417   for (i = start_idx + 2; i < total_len; i++) {
4418     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4419   }
4420 
4421   _use_pos_and_kinds.truncate(start_idx + 2);
4422   result->_use_pos_and_kinds = _use_pos_and_kinds;
4423   _use_pos_and_kinds = new_use_pos_and_kinds;
4424 
4425 #ifdef ASSERT
4426   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4427   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4428   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4429 
4430   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4431     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4432     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4433   }
4434   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4435     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4436     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4437   }
4438 #endif
4439 
4440   return result;
4441 }
4442 
4443 // split this interval at the specified position and return
4444 // the head as a new interval (the original interval is the tail)
4445 //
4446 // Currently, only the first range can be split, and the new interval
4447 // must not have split positions
4448 Interval* Interval::split_from_start(int split_pos) {
4449   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4450   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4451   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4452   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4453 
4454   // allocate new interval
4455   Interval* result = new_split_child();
4456 
4457   // the new created interval has only one range (checked by assertion above),
4458   // so the splitting of the ranges is very simple
4459   result->add_range(_first->from(), split_pos);
4460 
4461   if (split_pos == _first->to()) {
4462     assert(_first->next() != Range::end(), "must not be at end");
4463     _first = _first->next();
4464   } else {
4465     _first->set_from(split_pos);
4466   }
4467 
4468   return result;
4469 }
4470 
4471 
4472 // returns true if the op_id is inside the interval
4473 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4474   Range* cur  = _first;
4475 
4476   while (cur != Range::end() && cur->to() < op_id) {
4477     cur = cur->next();
4478   }
4479   if (cur != Range::end()) {
4480     assert(cur->to() != cur->next()->from(), "ranges not separated");
4481 
4482     if (mode == LIR_OpVisitState::outputMode) {
4483       return cur->from() <= op_id && op_id < cur->to();
4484     } else {
4485       return cur->from() <= op_id && op_id <= cur->to();
4486     }
4487   }
4488   return false;
4489 }
4490 
4491 // returns true if the interval has any hole between hole_from and hole_to
4492 // (even if the hole has only the length 1)
4493 bool Interval::has_hole_between(int hole_from, int hole_to) {
4494   assert(hole_from < hole_to, "check");
4495   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4496 
4497   Range* cur  = _first;
4498   while (cur != Range::end()) {
4499     assert(cur->to() < cur->next()->from(), "no space between ranges");
4500 
4501     // hole-range starts before this range -> hole
4502     if (hole_from < cur->from()) {
4503       return true;
4504 
4505     // hole-range completely inside this range -> no hole
4506     } else if (hole_to <= cur->to()) {
4507       return false;
4508 
4509     // overlapping of hole-range with this range -> hole
4510     } else if (hole_from <= cur->to()) {
4511       return true;
4512     }
4513 
4514     cur = cur->next();
4515   }
4516 
4517   return false;
4518 }
4519 
4520 
4521 #ifndef PRODUCT
4522 void Interval::print(outputStream* out) const {
4523   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4524   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4525 
4526   const char* type_name;
4527   LIR_Opr opr = LIR_OprFact::illegal();
4528   if (reg_num() < LIR_OprDesc::vreg_base) {
4529     type_name = "fixed";
4530     // need a temporary operand for fixed intervals because type() cannot be called
4531 #ifdef X86
4532     int last_xmm_reg = pd_last_xmm_reg;
4533 #ifdef _LP64
4534     if (UseAVX < 3) {
4535       last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
4536     }
4537 #endif
4538 #endif
4539     if (assigned_reg() >= pd_first_cpu_reg && assigned_reg() <= pd_last_cpu_reg) {
4540       opr = LIR_OprFact::single_cpu(assigned_reg());
4541     } else if (assigned_reg() >= pd_first_fpu_reg && assigned_reg() <= pd_last_fpu_reg) {
4542       opr = LIR_OprFact::single_fpu(assigned_reg() - pd_first_fpu_reg);
4543 #ifdef X86
4544     } else if (assigned_reg() >= pd_first_xmm_reg && assigned_reg() <= last_xmm_reg) {
4545       opr = LIR_OprFact::single_xmm(assigned_reg() - pd_first_xmm_reg);
4546 #endif
4547     } else {
4548       ShouldNotReachHere();
4549     }
4550   } else {
4551     type_name = type2name(type());
4552     if (assigned_reg() != -1 &&
4553         (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4554       opr = LinearScan::calc_operand_for_interval(this);
4555     }
4556   }
4557 
4558   out->print("%d %s ", reg_num(), type_name);
4559   if (opr->is_valid()) {
4560     out->print("\"");
4561     opr->print(out);
4562     out->print("\" ");
4563   }
4564   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4565 
4566   // print ranges
4567   Range* cur = _first;
4568   while (cur != Range::end()) {
4569     cur->print(out);
4570     cur = cur->next();
4571     assert(cur != NULL, "range list not closed with range sentinel");
4572   }
4573 
4574   // print use positions
4575   int prev = 0;
4576   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4577   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4578     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4579     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4580 
4581     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4582     prev = _use_pos_and_kinds.at(i);
4583   }
4584 
4585   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4586   out->cr();
4587 }
4588 #endif
4589 
4590 
4591 
4592 // **** Implementation of IntervalWalker ****************************
4593 
4594 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4595  : _compilation(allocator->compilation())
4596  , _allocator(allocator)
4597 {
4598   _unhandled_first[fixedKind] = unhandled_fixed_first;
4599   _unhandled_first[anyKind]   = unhandled_any_first;
4600   _active_first[fixedKind]    = Interval::end();
4601   _inactive_first[fixedKind]  = Interval::end();
4602   _active_first[anyKind]      = Interval::end();
4603   _inactive_first[anyKind]    = Interval::end();
4604   _current_position = -1;
4605   _current = NULL;
4606   next_interval();
4607 }
4608 
4609 
4610 // append interval at top of list
4611 void IntervalWalker::append_unsorted(Interval** list, Interval* interval) {
4612   interval->set_next(*list); *list = interval;
4613 }
4614 
4615 
4616 // append interval in order of current range from()
4617 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4618   Interval* prev = NULL;
4619   Interval* cur  = *list;
4620   while (cur->current_from() < interval->current_from()) {
4621     prev = cur; cur = cur->next();
4622   }
4623   if (prev == NULL) {
4624     *list = interval;
4625   } else {
4626     prev->set_next(interval);
4627   }
4628   interval->set_next(cur);
4629 }
4630 
4631 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4632   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4633 
4634   Interval* prev = NULL;
4635   Interval* cur  = *list;
4636   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4637     prev = cur; cur = cur->next();
4638   }
4639   if (prev == NULL) {
4640     *list = interval;
4641   } else {
4642     prev->set_next(interval);
4643   }
4644   interval->set_next(cur);
4645 }
4646 
4647 
4648 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4649   while (*list != Interval::end() && *list != i) {
4650     list = (*list)->next_addr();
4651   }
4652   if (*list != Interval::end()) {
4653     assert(*list == i, "check");
4654     *list = (*list)->next();
4655     return true;
4656   } else {
4657     return false;
4658   }
4659 }
4660 
4661 void IntervalWalker::remove_from_list(Interval* i) {
4662   bool deleted;
4663 
4664   if (i->state() == activeState) {
4665     deleted = remove_from_list(active_first_addr(anyKind), i);
4666   } else {
4667     assert(i->state() == inactiveState, "invalid state");
4668     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4669   }
4670 
4671   assert(deleted, "interval has not been found in list");
4672 }
4673 
4674 
4675 void IntervalWalker::walk_to(IntervalState state, int from) {
4676   assert (state == activeState || state == inactiveState, "wrong state");
4677   for_each_interval_kind(kind) {
4678     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4679     Interval* next   = *prev;
4680     while (next->current_from() <= from) {
4681       Interval* cur = next;
4682       next = cur->next();
4683 
4684       bool range_has_changed = false;
4685       while (cur->current_to() <= from) {
4686         cur->next_range();
4687         range_has_changed = true;
4688       }
4689 
4690       // also handle move from inactive list to active list
4691       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4692 
4693       if (range_has_changed) {
4694         // remove cur from list
4695         *prev = next;
4696         if (cur->current_at_end()) {
4697           // move to handled state (not maintained as a list)
4698           cur->set_state(handledState);
4699           interval_moved(cur, kind, state, handledState);
4700         } else if (cur->current_from() <= from){
4701           // sort into active list
4702           append_sorted(active_first_addr(kind), cur);
4703           cur->set_state(activeState);
4704           if (*prev == cur) {
4705             assert(state == activeState, "check");
4706             prev = cur->next_addr();
4707           }
4708           interval_moved(cur, kind, state, activeState);
4709         } else {
4710           // sort into inactive list
4711           append_sorted(inactive_first_addr(kind), cur);
4712           cur->set_state(inactiveState);
4713           if (*prev == cur) {
4714             assert(state == inactiveState, "check");
4715             prev = cur->next_addr();
4716           }
4717           interval_moved(cur, kind, state, inactiveState);
4718         }
4719       } else {
4720         prev = cur->next_addr();
4721         continue;
4722       }
4723     }
4724   }
4725 }
4726 
4727 
4728 void IntervalWalker::next_interval() {
4729   IntervalKind kind;
4730   Interval* any   = _unhandled_first[anyKind];
4731   Interval* fixed = _unhandled_first[fixedKind];
4732 
4733   if (any != Interval::end()) {
4734     // intervals may start at same position -> prefer fixed interval
4735     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4736 
4737     assert (kind == fixedKind && fixed->from() <= any->from() ||
4738             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4739     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4740 
4741   } else if (fixed != Interval::end()) {
4742     kind = fixedKind;
4743   } else {
4744     _current = NULL; return;
4745   }
4746   _current_kind = kind;
4747   _current = _unhandled_first[kind];
4748   _unhandled_first[kind] = _current->next();
4749   _current->set_next(Interval::end());
4750   _current->rewind_range();
4751 }
4752 
4753 
4754 void IntervalWalker::walk_to(int lir_op_id) {
4755   assert(_current_position <= lir_op_id, "can not walk backwards");
4756   while (current() != NULL) {
4757     bool is_active = current()->from() <= lir_op_id;
4758     int id = is_active ? current()->from() : lir_op_id;
4759 
4760     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4761 
4762     // set _current_position prior to call of walk_to
4763     _current_position = id;
4764 
4765     // call walk_to even if _current_position == id
4766     walk_to(activeState, id);
4767     walk_to(inactiveState, id);
4768 
4769     if (is_active) {
4770       current()->set_state(activeState);
4771       if (activate_current()) {
4772         append_sorted(active_first_addr(current_kind()), current());
4773         interval_moved(current(), current_kind(), unhandledState, activeState);
4774       }
4775 
4776       next_interval();
4777     } else {
4778       return;
4779     }
4780   }
4781 }
4782 
4783 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4784 #ifndef PRODUCT
4785   if (TraceLinearScanLevel >= 4) {
4786     #define print_state(state) \
4787     switch(state) {\
4788       case unhandledState: tty->print("unhandled"); break;\
4789       case activeState: tty->print("active"); break;\
4790       case inactiveState: tty->print("inactive"); break;\
4791       case handledState: tty->print("handled"); break;\
4792       default: ShouldNotReachHere(); \
4793     }
4794 
4795     print_state(from); tty->print(" to "); print_state(to);
4796     tty->fill_to(23);
4797     interval->print();
4798 
4799     #undef print_state
4800   }
4801 #endif
4802 }
4803 
4804 
4805 
4806 // **** Implementation of LinearScanWalker **************************
4807 
4808 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4809   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4810   , _move_resolver(allocator)
4811 {
4812   for (int i = 0; i < LinearScan::nof_regs; i++) {
4813     _spill_intervals[i] = new IntervalList(2);
4814   }
4815 }
4816 
4817 
4818 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4819   for (int i = _first_reg; i <= _last_reg; i++) {
4820     _use_pos[i] = max_jint;
4821 
4822     if (!only_process_use_pos) {
4823       _block_pos[i] = max_jint;
4824       _spill_intervals[i]->clear();
4825     }
4826   }
4827 }
4828 
4829 inline void LinearScanWalker::exclude_from_use(int reg) {
4830   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4831   if (reg >= _first_reg && reg <= _last_reg) {
4832     _use_pos[reg] = 0;
4833   }
4834 }
4835 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4836   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4837 
4838   exclude_from_use(i->assigned_reg());
4839   exclude_from_use(i->assigned_regHi());
4840 }
4841 
4842 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4843   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4844 
4845   if (reg >= _first_reg && reg <= _last_reg) {
4846     if (_use_pos[reg] > use_pos) {
4847       _use_pos[reg] = use_pos;
4848     }
4849     if (!only_process_use_pos) {
4850       _spill_intervals[reg]->append(i);
4851     }
4852   }
4853 }
4854 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4855   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4856   if (use_pos != -1) {
4857     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4858     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4859   }
4860 }
4861 
4862 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4863   if (reg >= _first_reg && reg <= _last_reg) {
4864     if (_block_pos[reg] > block_pos) {
4865       _block_pos[reg] = block_pos;
4866     }
4867     if (_use_pos[reg] > block_pos) {
4868       _use_pos[reg] = block_pos;
4869     }
4870   }
4871 }
4872 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4873   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4874   if (block_pos != -1) {
4875     set_block_pos(i->assigned_reg(), i, block_pos);
4876     set_block_pos(i->assigned_regHi(), i, block_pos);
4877   }
4878 }
4879 
4880 
4881 void LinearScanWalker::free_exclude_active_fixed() {
4882   Interval* list = active_first(fixedKind);
4883   while (list != Interval::end()) {
4884     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4885     exclude_from_use(list);
4886     list = list->next();
4887   }
4888 }
4889 
4890 void LinearScanWalker::free_exclude_active_any() {
4891   Interval* list = active_first(anyKind);
4892   while (list != Interval::end()) {
4893     exclude_from_use(list);
4894     list = list->next();
4895   }
4896 }
4897 
4898 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
4899   Interval* list = inactive_first(fixedKind);
4900   while (list != Interval::end()) {
4901     if (cur->to() <= list->current_from()) {
4902       assert(list->current_intersects_at(cur) == -1, "must not intersect");
4903       set_use_pos(list, list->current_from(), true);
4904     } else {
4905       set_use_pos(list, list->current_intersects_at(cur), true);
4906     }
4907     list = list->next();
4908   }
4909 }
4910 
4911 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
4912   Interval* list = inactive_first(anyKind);
4913   while (list != Interval::end()) {
4914     set_use_pos(list, list->current_intersects_at(cur), true);
4915     list = list->next();
4916   }
4917 }
4918 
4919 void LinearScanWalker::free_collect_unhandled(IntervalKind kind, Interval* cur) {
4920   Interval* list = unhandled_first(kind);
4921   while (list != Interval::end()) {
4922     set_use_pos(list, list->intersects_at(cur), true);
4923     if (kind == fixedKind && cur->to() <= list->from()) {
4924       set_use_pos(list, list->from(), true);
4925     }
4926     list = list->next();
4927   }
4928 }
4929 
4930 void LinearScanWalker::spill_exclude_active_fixed() {
4931   Interval* list = active_first(fixedKind);
4932   while (list != Interval::end()) {
4933     exclude_from_use(list);
4934     list = list->next();
4935   }
4936 }
4937 
4938 void LinearScanWalker::spill_block_unhandled_fixed(Interval* cur) {
4939   Interval* list = unhandled_first(fixedKind);
4940   while (list != Interval::end()) {
4941     set_block_pos(list, list->intersects_at(cur));
4942     list = list->next();
4943   }
4944 }
4945 
4946 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
4947   Interval* list = inactive_first(fixedKind);
4948   while (list != Interval::end()) {
4949     if (cur->to() > list->current_from()) {
4950       set_block_pos(list, list->current_intersects_at(cur));
4951     } else {
4952       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
4953     }
4954 
4955     list = list->next();
4956   }
4957 }
4958 
4959 void LinearScanWalker::spill_collect_active_any() {
4960   Interval* list = active_first(anyKind);
4961   while (list != Interval::end()) {
4962     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4963     list = list->next();
4964   }
4965 }
4966 
4967 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
4968   Interval* list = inactive_first(anyKind);
4969   while (list != Interval::end()) {
4970     if (list->current_intersects(cur)) {
4971       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
4972     }
4973     list = list->next();
4974   }
4975 }
4976 
4977 
4978 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
4979   // output all moves here. When source and target are equal, the move is
4980   // optimized away later in assign_reg_nums
4981 
4982   op_id = (op_id + 1) & ~1;
4983   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
4984   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
4985 
4986   // calculate index of instruction inside instruction list of current block
4987   // the minimal index (for a block with no spill moves) can be calculated because the
4988   // numbering of instructions is known.
4989   // When the block already contains spill moves, the index must be increased until the
4990   // correct index is reached.
4991   LIR_OpList* list = op_block->lir()->instructions_list();
4992   int index = (op_id - list->at(0)->id()) / 2;
4993   assert(list->at(index)->id() <= op_id, "error in calculation");
4994 
4995   while (list->at(index)->id() != op_id) {
4996     index++;
4997     assert(0 <= index && index < list->length(), "index out of bounds");
4998   }
4999   assert(1 <= index && index < list->length(), "index out of bounds");
5000   assert(list->at(index)->id() == op_id, "error in calculation");
5001 
5002   // insert new instruction before instruction at position index
5003   _move_resolver.move_insert_position(op_block->lir(), index - 1);
5004   _move_resolver.add_mapping(src_it, dst_it);
5005 }
5006 
5007 
5008 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5009   int from_block_nr = min_block->linear_scan_number();
5010   int to_block_nr = max_block->linear_scan_number();
5011 
5012   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5013   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5014   assert(from_block_nr < to_block_nr, "must cross block boundary");
5015 
5016   // Try to split at end of max_block. If this would be after
5017   // max_split_pos, then use the begin of max_block
5018   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5019   if (optimal_split_pos > max_split_pos) {
5020     optimal_split_pos = max_block->first_lir_instruction_id();
5021   }
5022 
5023   int min_loop_depth = max_block->loop_depth();
5024   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5025     BlockBegin* cur = block_at(i);
5026 
5027     if (cur->loop_depth() < min_loop_depth) {
5028       // block with lower loop-depth found -> split at the end of this block
5029       min_loop_depth = cur->loop_depth();
5030       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5031     }
5032   }
5033   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5034 
5035   return optimal_split_pos;
5036 }
5037 
5038 
5039 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5040   int optimal_split_pos = -1;
5041   if (min_split_pos == max_split_pos) {
5042     // trivial case, no optimization of split position possible
5043     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5044     optimal_split_pos = min_split_pos;
5045 
5046   } else {
5047     assert(min_split_pos < max_split_pos, "must be true then");
5048     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5049 
5050     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5051     // beginning of a block, then min_split_pos is also a possible split position.
5052     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5053     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5054 
5055     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5056     // when an interval ends at the end of the last block of the method
5057     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5058     // block at this op_id)
5059     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5060 
5061     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5062     if (min_block == max_block) {
5063       // split position cannot be moved to block boundary, so split as late as possible
5064       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5065       optimal_split_pos = max_split_pos;
5066 
5067     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5068       // Do not move split position if the interval has a hole before max_split_pos.
5069       // Intervals resulting from Phi-Functions have more than one definition (marked
5070       // as mustHaveRegister) with a hole before each definition. When the register is needed
5071       // for the second definition, an earlier reloading is unnecessary.
5072       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5073       optimal_split_pos = max_split_pos;
5074 
5075     } else {
5076       // seach optimal block boundary between min_split_pos and max_split_pos
5077       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5078 
5079       if (do_loop_optimization) {
5080         // Loop optimization: if a loop-end marker is found between min- and max-position,
5081         // then split before this loop
5082         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5083         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5084 
5085         assert(loop_end_pos > min_split_pos, "invalid order");
5086         if (loop_end_pos < max_split_pos) {
5087           // loop-end marker found between min- and max-position
5088           // if it is not the end marker for the same loop as the min-position, then move
5089           // the max-position to this loop block.
5090           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5091           // of the interval (normally, only mustHaveRegister causes a reloading)
5092           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5093 
5094           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5095           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5096 
5097           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5098           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5099             optimal_split_pos = -1;
5100             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5101           } else {
5102             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5103           }
5104         }
5105       }
5106 
5107       if (optimal_split_pos == -1) {
5108         // not calculated by loop optimization
5109         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5110       }
5111     }
5112   }
5113   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5114 
5115   return optimal_split_pos;
5116 }
5117 
5118 
5119 /*
5120   split an interval at the optimal position between min_split_pos and
5121   max_split_pos in two parts:
5122   1) the left part has already a location assigned
5123   2) the right part is sorted into to the unhandled-list
5124 */
5125 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5126   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5127   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5128 
5129   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5130   assert(current_position() < min_split_pos, "cannot split before current position");
5131   assert(min_split_pos <= max_split_pos,     "invalid order");
5132   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5133 
5134   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5135 
5136   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5137   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5138   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5139 
5140   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5141     // the split position would be just before the end of the interval
5142     // -> no split at all necessary
5143     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5144     return;
5145   }
5146 
5147   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5148   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5149 
5150   if (!allocator()->is_block_begin(optimal_split_pos)) {
5151     // move position before actual instruction (odd op_id)
5152     optimal_split_pos = (optimal_split_pos - 1) | 1;
5153   }
5154 
5155   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5156   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5157   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5158 
5159   Interval* split_part = it->split(optimal_split_pos);
5160 
5161   allocator()->append_interval(split_part);
5162   allocator()->copy_register_flags(it, split_part);
5163   split_part->set_insert_move_when_activated(move_necessary);
5164   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5165 
5166   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5167   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5168   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5169 }
5170 
5171 /*
5172   split an interval at the optimal position between min_split_pos and
5173   max_split_pos in two parts:
5174   1) the left part has already a location assigned
5175   2) the right part is always on the stack and therefore ignored in further processing
5176 */
5177 void LinearScanWalker::split_for_spilling(Interval* it) {
5178   // calculate allowed range of splitting position
5179   int max_split_pos = current_position();
5180   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5181 
5182   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5183   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5184 
5185   assert(it->state() == activeState,     "why spill interval that is not active?");
5186   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5187   assert(min_split_pos <= max_split_pos, "invalid order");
5188   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5189   assert(current_position() < it->to(),  "interval must not end before current position");
5190 
5191   if (min_split_pos == it->from()) {
5192     // the whole interval is never used, so spill it entirely to memory
5193     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5194     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5195 
5196     allocator()->assign_spill_slot(it);
5197     allocator()->change_spill_state(it, min_split_pos);
5198 
5199     // Also kick parent intervals out of register to memory when they have no use
5200     // position. This avoids short interval in register surrounded by intervals in
5201     // memory -> avoid useless moves from memory to register and back
5202     Interval* parent = it;
5203     while (parent != NULL && parent->is_split_child()) {
5204       parent = parent->split_child_before_op_id(parent->from());
5205 
5206       if (parent->assigned_reg() < LinearScan::nof_regs) {
5207         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5208           // parent is never used, so kick it out of its assigned register
5209           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5210           allocator()->assign_spill_slot(parent);
5211         } else {
5212           // do not go further back because the register is actually used by the interval
5213           parent = NULL;
5214         }
5215       }
5216     }
5217 
5218   } else {
5219     // search optimal split pos, split interval and spill only the right hand part
5220     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5221 
5222     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5223     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5224     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5225 
5226     if (!allocator()->is_block_begin(optimal_split_pos)) {
5227       // move position before actual instruction (odd op_id)
5228       optimal_split_pos = (optimal_split_pos - 1) | 1;
5229     }
5230 
5231     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5232     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5233     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5234 
5235     Interval* spilled_part = it->split(optimal_split_pos);
5236     allocator()->append_interval(spilled_part);
5237     allocator()->assign_spill_slot(spilled_part);
5238     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5239 
5240     if (!allocator()->is_block_begin(optimal_split_pos)) {
5241       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5242       insert_move(optimal_split_pos, it, spilled_part);
5243     }
5244 
5245     // the current_split_child is needed later when moves are inserted for reloading
5246     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5247     spilled_part->make_current_split_child();
5248 
5249     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5250     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5251     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5252   }
5253 }
5254 
5255 
5256 void LinearScanWalker::split_stack_interval(Interval* it) {
5257   int min_split_pos = current_position() + 1;
5258   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5259 
5260   split_before_usage(it, min_split_pos, max_split_pos);
5261 }
5262 
5263 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5264   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5265   int max_split_pos = register_available_until;
5266 
5267   split_before_usage(it, min_split_pos, max_split_pos);
5268 }
5269 
5270 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5271   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5272 
5273   int current_pos = current_position();
5274   if (it->state() == inactiveState) {
5275     // the interval is currently inactive, so no spill slot is needed for now.
5276     // when the split part is activated, the interval has a new chance to get a register,
5277     // so in the best case no stack slot is necessary
5278     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5279     split_before_usage(it, current_pos + 1, current_pos + 1);
5280 
5281   } else {
5282     // search the position where the interval must have a register and split
5283     // at the optimal position before.
5284     // The new created part is added to the unhandled list and will get a register
5285     // when it is activated
5286     int min_split_pos = current_pos + 1;
5287     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5288 
5289     split_before_usage(it, min_split_pos, max_split_pos);
5290 
5291     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5292     split_for_spilling(it);
5293   }
5294 }
5295 
5296 
5297 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5298   int min_full_reg = any_reg;
5299   int max_partial_reg = any_reg;
5300 
5301   for (int i = _first_reg; i <= _last_reg; i++) {
5302     if (i == ignore_reg) {
5303       // this register must be ignored
5304 
5305     } else if (_use_pos[i] >= interval_to) {
5306       // this register is free for the full interval
5307       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5308         min_full_reg = i;
5309       }
5310     } else if (_use_pos[i] > reg_needed_until) {
5311       // this register is at least free until reg_needed_until
5312       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5313         max_partial_reg = i;
5314       }
5315     }
5316   }
5317 
5318   if (min_full_reg != any_reg) {
5319     return min_full_reg;
5320   } else if (max_partial_reg != any_reg) {
5321     *need_split = true;
5322     return max_partial_reg;
5323   } else {
5324     return any_reg;
5325   }
5326 }
5327 
5328 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5329   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5330 
5331   int min_full_reg = any_reg;
5332   int max_partial_reg = any_reg;
5333 
5334   for (int i = _first_reg; i < _last_reg; i+=2) {
5335     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5336       // this register is free for the full interval
5337       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5338         min_full_reg = i;
5339       }
5340     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5341       // this register is at least free until reg_needed_until
5342       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5343         max_partial_reg = i;
5344       }
5345     }
5346   }
5347 
5348   if (min_full_reg != any_reg) {
5349     return min_full_reg;
5350   } else if (max_partial_reg != any_reg) {
5351     *need_split = true;
5352     return max_partial_reg;
5353   } else {
5354     return any_reg;
5355   }
5356 }
5357 
5358 
5359 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5360   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5361 
5362   init_use_lists(true);
5363   free_exclude_active_fixed();
5364   free_exclude_active_any();
5365   free_collect_inactive_fixed(cur);
5366   free_collect_inactive_any(cur);
5367 //  free_collect_unhandled(fixedKind, cur);
5368   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5369 
5370   // _use_pos contains the start of the next interval that has this register assigned
5371   // (either as a fixed register or a normal allocated register in the past)
5372   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5373   TRACE_LINEAR_SCAN(4, tty->print_cr("      state of registers:"));
5374   TRACE_LINEAR_SCAN(4, for (int i = _first_reg; i <= _last_reg; i++) tty->print_cr("      reg %d: use_pos: %d", i, _use_pos[i]));
5375 
5376   int hint_reg, hint_regHi;
5377   Interval* register_hint = cur->register_hint();
5378   if (register_hint != NULL) {
5379     hint_reg = register_hint->assigned_reg();
5380     hint_regHi = register_hint->assigned_regHi();
5381 
5382     if (allocator()->is_precolored_cpu_interval(register_hint)) {
5383       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5384       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5385     }
5386     TRACE_LINEAR_SCAN(4, tty->print("      hint registers %d, %d from interval ", hint_reg, hint_regHi); register_hint->print());
5387 
5388   } else {
5389     hint_reg = any_reg;
5390     hint_regHi = any_reg;
5391   }
5392   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5393   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5394 
5395   // the register must be free at least until this position
5396   int reg_needed_until = cur->from() + 1;
5397   int interval_to = cur->to();
5398 
5399   bool need_split = false;
5400   int split_pos = -1;
5401   int reg = any_reg;
5402   int regHi = any_reg;
5403 
5404   if (_adjacent_regs) {
5405     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5406     regHi = reg + 1;
5407     if (reg == any_reg) {
5408       return false;
5409     }
5410     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5411 
5412   } else {
5413     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5414     if (reg == any_reg) {
5415       return false;
5416     }
5417     split_pos = _use_pos[reg];
5418 
5419     if (_num_phys_regs == 2) {
5420       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5421 
5422       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5423         // do not split interval if only one register can be assigned until the split pos
5424         // (when one register is found for the whole interval, split&spill is only
5425         // performed for the hi register)
5426         return false;
5427 
5428       } else if (regHi != any_reg) {
5429         split_pos = MIN2(split_pos, _use_pos[regHi]);
5430 
5431         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5432         if (reg > regHi) {
5433           int temp = reg;
5434           reg = regHi;
5435           regHi = temp;
5436         }
5437       }
5438     }
5439   }
5440 
5441   cur->assign_reg(reg, regHi);
5442   TRACE_LINEAR_SCAN(2, tty->print_cr("selected register %d, %d", reg, regHi));
5443 
5444   assert(split_pos > 0, "invalid split_pos");
5445   if (need_split) {
5446     // register not available for full interval, so split it
5447     split_when_partial_register_available(cur, split_pos);
5448   }
5449 
5450   // only return true if interval is completely assigned
5451   return _num_phys_regs == 1 || regHi != any_reg;
5452 }
5453 
5454 
5455 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5456   int max_reg = any_reg;
5457 
5458   for (int i = _first_reg; i <= _last_reg; i++) {
5459     if (i == ignore_reg) {
5460       // this register must be ignored
5461 
5462     } else if (_use_pos[i] > reg_needed_until) {
5463       if (max_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_reg] && max_reg != hint_reg)) {
5464         max_reg = i;
5465       }
5466     }
5467   }
5468 
5469   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5470     *need_split = true;
5471   }
5472 
5473   return max_reg;
5474 }
5475 
5476 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5477   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5478 
5479   int max_reg = any_reg;
5480 
5481   for (int i = _first_reg; i < _last_reg; i+=2) {
5482     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5483       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5484         max_reg = i;
5485       }
5486     }
5487   }
5488 
5489   if (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to) {
5490     *need_split = true;
5491   }
5492 
5493   return max_reg;
5494 }
5495 
5496 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5497   assert(reg != any_reg, "no register assigned");
5498 
5499   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5500     Interval* it = _spill_intervals[reg]->at(i);
5501     remove_from_list(it);
5502     split_and_spill_interval(it);
5503   }
5504 
5505   if (regHi != any_reg) {
5506     IntervalList* processed = _spill_intervals[reg];
5507     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5508       Interval* it = _spill_intervals[regHi]->at(i);
5509       if (processed->index_of(it) == -1) {
5510         remove_from_list(it);
5511         split_and_spill_interval(it);
5512       }
5513     }
5514   }
5515 }
5516 
5517 
5518 // Split an Interval and spill it to memory so that cur can be placed in a register
5519 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5520   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5521 
5522   // collect current usage of registers
5523   init_use_lists(false);
5524   spill_exclude_active_fixed();
5525 //  spill_block_unhandled_fixed(cur);
5526   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5527   spill_block_inactive_fixed(cur);
5528   spill_collect_active_any();
5529   spill_collect_inactive_any(cur);
5530 
5531 #ifndef PRODUCT
5532   if (TraceLinearScanLevel >= 4) {
5533     tty->print_cr("      state of registers:");
5534     for (int i = _first_reg; i <= _last_reg; i++) {
5535       tty->print("      reg %d: use_pos: %d, block_pos: %d, intervals: ", i, _use_pos[i], _block_pos[i]);
5536       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5537         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5538       }
5539       tty->cr();
5540     }
5541   }
5542 #endif
5543 
5544   // the register must be free at least until this position
5545   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5546   int interval_to = cur->to();
5547   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5548 
5549   int split_pos = 0;
5550   int use_pos = 0;
5551   bool need_split = false;
5552   int reg, regHi;
5553 
5554   if (_adjacent_regs) {
5555     reg = find_locked_double_reg(reg_needed_until, interval_to, any_reg, &need_split);
5556     regHi = reg + 1;
5557 
5558     if (reg != any_reg) {
5559       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5560       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5561     }
5562   } else {
5563     reg = find_locked_reg(reg_needed_until, interval_to, any_reg, cur->assigned_reg(), &need_split);
5564     regHi = any_reg;
5565 
5566     if (reg != any_reg) {
5567       use_pos = _use_pos[reg];
5568       split_pos = _block_pos[reg];
5569 
5570       if (_num_phys_regs == 2) {
5571         if (cur->assigned_reg() != any_reg) {
5572           regHi = reg;
5573           reg = cur->assigned_reg();
5574         } else {
5575           regHi = find_locked_reg(reg_needed_until, interval_to, any_reg, reg, &need_split);
5576           if (regHi != any_reg) {
5577             use_pos = MIN2(use_pos, _use_pos[regHi]);
5578             split_pos = MIN2(split_pos, _block_pos[regHi]);
5579           }
5580         }
5581 
5582         if (regHi != any_reg && reg > regHi) {
5583           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5584           int temp = reg;
5585           reg = regHi;
5586           regHi = temp;
5587         }
5588       }
5589     }
5590   }
5591 
5592   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5593     // the first use of cur is later than the spilling position -> spill cur
5594     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5595 
5596     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5597       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5598       // assign a reasonable register and do a bailout in product mode to avoid errors
5599       allocator()->assign_spill_slot(cur);
5600       BAILOUT("LinearScan: no register found");
5601     }
5602 
5603     split_and_spill_interval(cur);
5604   } else {
5605     TRACE_LINEAR_SCAN(4, tty->print_cr("decided to use register %d, %d", reg, regHi));
5606     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5607     assert(split_pos > 0, "invalid split_pos");
5608     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5609 
5610     cur->assign_reg(reg, regHi);
5611     if (need_split) {
5612       // register not available for full interval, so split it
5613       split_when_partial_register_available(cur, split_pos);
5614     }
5615 
5616     // perform splitting and spilling for all affected intervalls
5617     split_and_spill_intersecting_intervals(reg, regHi);
5618   }
5619 }
5620 
5621 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5622 #ifdef X86
5623   // fast calculation of intervals that can never get a register because the
5624   // the next instruction is a call that blocks all registers
5625   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5626 
5627   // check if this interval is the result of a split operation
5628   // (an interval got a register until this position)
5629   int pos = cur->from();
5630   if ((pos & 1) == 1) {
5631     // the current instruction is a call that blocks all registers
5632     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5633       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5634 
5635       // safety check that there is really no register available
5636       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5637       return true;
5638     }
5639 
5640   }
5641 #endif
5642   return false;
5643 }
5644 
5645 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5646   BasicType type = cur->type();
5647   _num_phys_regs = LinearScan::num_physical_regs(type);
5648   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5649 
5650   if (pd_init_regs_for_alloc(cur)) {
5651     // the appropriate register range was selected.
5652   } else if (type == T_FLOAT || type == T_DOUBLE) {
5653     _first_reg = pd_first_fpu_reg;
5654     _last_reg = pd_last_fpu_reg;
5655   } else {
5656     _first_reg = pd_first_cpu_reg;
5657     _last_reg = FrameMap::last_cpu_reg();
5658   }
5659 
5660   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5661   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5662 }
5663 
5664 
5665 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5666   if (op->code() != lir_move) {
5667     return false;
5668   }
5669   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5670 
5671   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5672   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5673   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5674 }
5675 
5676 // optimization (especially for phi functions of nested loops):
5677 // assign same spill slot to non-intersecting intervals
5678 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5679   if (cur->is_split_child()) {
5680     // optimization is only suitable for split parents
5681     return;
5682   }
5683 
5684   Interval* register_hint = cur->register_hint(false);
5685   if (register_hint == NULL) {
5686     // cur is not the target of a move, otherwise register_hint would be set
5687     return;
5688   }
5689   assert(register_hint->is_split_parent(), "register hint must be split parent");
5690 
5691   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5692     // combining the stack slots for intervals where spill move optimization is applied
5693     // is not benefitial and would cause problems
5694     return;
5695   }
5696 
5697   int begin_pos = cur->from();
5698   int end_pos = cur->to();
5699   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5700     // safety check that lir_op_with_id is allowed
5701     return;
5702   }
5703 
5704   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5705     // cur and register_hint are not connected with two moves
5706     return;
5707   }
5708 
5709   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5710   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5711   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5712     // register_hint must be split, otherwise the re-writing of use positions does not work
5713     return;
5714   }
5715 
5716   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5717   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5718   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5719   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5720 
5721   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5722     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5723     return;
5724   }
5725   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5726 
5727   // modify intervals such that cur gets the same stack slot as register_hint
5728   // delete use positions to prevent the intervals to get a register at beginning
5729   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5730   cur->remove_first_use_pos();
5731   end_hint->remove_first_use_pos();
5732 }
5733 
5734 
5735 // allocate a physical register or memory location to an interval
5736 bool LinearScanWalker::activate_current() {
5737   Interval* cur = current();
5738   bool result = true;
5739 
5740   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5741   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5742 
5743   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5744     // activating an interval that has a stack slot assigned -> split it at first use position
5745     // used for method parameters
5746     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5747 
5748     split_stack_interval(cur);
5749     result = false;
5750 
5751   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5752     // activating an interval that must start in a stack slot, but may get a register later
5753     // used for lir_roundfp: rounding is done by store to stack and reload later
5754     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5755     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5756 
5757     allocator()->assign_spill_slot(cur);
5758     split_stack_interval(cur);
5759     result = false;
5760 
5761   } else if (cur->assigned_reg() == any_reg) {
5762     // interval has not assigned register -> normal allocation
5763     // (this is the normal case for most intervals)
5764     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5765 
5766     // assign same spill slot to non-intersecting intervals
5767     combine_spilled_intervals(cur);
5768 
5769     init_vars_for_alloc(cur);
5770     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5771       // no empty register available.
5772       // split and spill another interval so that this interval gets a register
5773       alloc_locked_reg(cur);
5774     }
5775 
5776     // spilled intervals need not be move to active-list
5777     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5778       result = false;
5779     }
5780   }
5781 
5782   // load spilled values that become active from stack slot to register
5783   if (cur->insert_move_when_activated()) {
5784     assert(cur->is_split_child(), "must be");
5785     assert(cur->current_split_child() != NULL, "must be");
5786     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5787     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5788 
5789     insert_move(cur->from(), cur->current_split_child(), cur);
5790   }
5791   cur->make_current_split_child();
5792 
5793   return result; // true = interval is moved to active list
5794 }
5795 
5796 
5797 // Implementation of EdgeMoveOptimizer
5798 
5799 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5800   _edge_instructions(4),
5801   _edge_instructions_idx(4)
5802 {
5803 }
5804 
5805 void EdgeMoveOptimizer::optimize(BlockList* code) {
5806   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5807 
5808   // ignore the first block in the list (index 0 is not processed)
5809   for (int i = code->length() - 1; i >= 1; i--) {
5810     BlockBegin* block = code->at(i);
5811 
5812     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5813       optimizer.optimize_moves_at_block_end(block);
5814     }
5815     if (block->number_of_sux() == 2) {
5816       optimizer.optimize_moves_at_block_begin(block);
5817     }
5818   }
5819 }
5820 
5821 
5822 // clear all internal data structures
5823 void EdgeMoveOptimizer::init_instructions() {
5824   _edge_instructions.clear();
5825   _edge_instructions_idx.clear();
5826 }
5827 
5828 // append a lir-instruction-list and the index of the current operation in to the list
5829 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5830   _edge_instructions.append(instructions);
5831   _edge_instructions_idx.append(instructions_idx);
5832 }
5833 
5834 // return the current operation of the given edge (predecessor or successor)
5835 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5836   LIR_OpList* instructions = _edge_instructions.at(edge);
5837   int idx = _edge_instructions_idx.at(edge);
5838 
5839   if (idx < instructions->length()) {
5840     return instructions->at(idx);
5841   } else {
5842     return NULL;
5843   }
5844 }
5845 
5846 // removes the current operation of the given edge (predecessor or successor)
5847 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5848   LIR_OpList* instructions = _edge_instructions.at(edge);
5849   int idx = _edge_instructions_idx.at(edge);
5850   instructions->remove_at(idx);
5851 
5852   if (decrement_index) {
5853     _edge_instructions_idx.at_put(edge, idx - 1);
5854   }
5855 }
5856 
5857 
5858 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5859   if (op1 == NULL || op2 == NULL) {
5860     // at least one block is already empty -> no optimization possible
5861     return true;
5862   }
5863 
5864   if (op1->code() == lir_move && op2->code() == lir_move) {
5865     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5866     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5867     LIR_Op1* move1 = (LIR_Op1*)op1;
5868     LIR_Op1* move2 = (LIR_Op1*)op2;
5869     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5870       // these moves are exactly equal and can be optimized
5871       return false;
5872     }
5873 
5874   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
5875     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
5876     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
5877     LIR_Op1* fxch1 = (LIR_Op1*)op1;
5878     LIR_Op1* fxch2 = (LIR_Op1*)op2;
5879     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
5880       // equal FPU stack operations can be optimized
5881       return false;
5882     }
5883 
5884   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
5885     // equal FPU stack operations can be optimized
5886     return false;
5887   }
5888 
5889   // no optimization possible
5890   return true;
5891 }
5892 
5893 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
5894   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
5895 
5896   if (block->is_predecessor(block)) {
5897     // currently we can't handle this correctly.
5898     return;
5899   }
5900 
5901   init_instructions();
5902   int num_preds = block->number_of_preds();
5903   assert(num_preds > 1, "do not call otherwise");
5904   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
5905 
5906   // setup a list with the lir-instructions of all predecessors
5907   int i;
5908   for (i = 0; i < num_preds; i++) {
5909     BlockBegin* pred = block->pred_at(i);
5910     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
5911 
5912     if (pred->number_of_sux() != 1) {
5913       // this can happen with switch-statements where multiple edges are between
5914       // the same blocks.
5915       return;
5916     }
5917 
5918     assert(pred->number_of_sux() == 1, "can handle only one successor");
5919     assert(pred->sux_at(0) == block, "invalid control flow");
5920     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5921     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5922     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5923 
5924     if (pred_instructions->last()->info() != NULL) {
5925       // can not optimize instructions when debug info is needed
5926       return;
5927     }
5928 
5929     // ignore the unconditional branch at the end of the block
5930     append_instructions(pred_instructions, pred_instructions->length() - 2);
5931   }
5932 
5933 
5934   // process lir-instructions while all predecessors end with the same instruction
5935   while (true) {
5936     LIR_Op* op = instruction_at(0);
5937     for (i = 1; i < num_preds; i++) {
5938       if (operations_different(op, instruction_at(i))) {
5939         // these instructions are different and cannot be optimized ->
5940         // no further optimization possible
5941         return;
5942       }
5943     }
5944 
5945     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
5946 
5947     // insert the instruction at the beginning of the current block
5948     block->lir()->insert_before(1, op);
5949 
5950     // delete the instruction at the end of all predecessors
5951     for (i = 0; i < num_preds; i++) {
5952       remove_cur_instruction(i, true);
5953     }
5954   }
5955 }
5956 
5957 
5958 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
5959   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
5960 
5961   init_instructions();
5962   int num_sux = block->number_of_sux();
5963 
5964   LIR_OpList* cur_instructions = block->lir()->instructions_list();
5965 
5966   assert(num_sux == 2, "method should not be called otherwise");
5967   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
5968   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
5969   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
5970 
5971   if (cur_instructions->last()->info() != NULL) {
5972     // can no optimize instructions when debug info is needed
5973     return;
5974   }
5975 
5976   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
5977   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
5978     // not a valid case for optimization
5979     // currently, only blocks that end with two branches (conditional branch followed
5980     // by unconditional branch) are optimized
5981     return;
5982   }
5983 
5984   // now it is guaranteed that the block ends with two branch instructions.
5985   // the instructions are inserted at the end of the block before these two branches
5986   int insert_idx = cur_instructions->length() - 2;
5987 
5988   int i;
5989 #ifdef ASSERT
5990   for (i = insert_idx - 1; i >= 0; i--) {
5991     LIR_Op* op = cur_instructions->at(i);
5992     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
5993       assert(false, "block with two successors can have only two branch instructions");
5994     }
5995   }
5996 #endif
5997 
5998   // setup a list with the lir-instructions of all successors
5999   for (i = 0; i < num_sux; i++) {
6000     BlockBegin* sux = block->sux_at(i);
6001     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6002 
6003     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6004 
6005     if (sux->number_of_preds() != 1) {
6006       // this can happen with switch-statements where multiple edges are between
6007       // the same blocks.
6008       return;
6009     }
6010     assert(sux->pred_at(0) == block, "invalid control flow");
6011     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6012 
6013     // ignore the label at the beginning of the block
6014     append_instructions(sux_instructions, 1);
6015   }
6016 
6017   // process lir-instructions while all successors begin with the same instruction
6018   while (true) {
6019     LIR_Op* op = instruction_at(0);
6020     for (i = 1; i < num_sux; i++) {
6021       if (operations_different(op, instruction_at(i))) {
6022         // these instructions are different and cannot be optimized ->
6023         // no further optimization possible
6024         return;
6025       }
6026     }
6027 
6028     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6029 
6030     // insert instruction at end of current block
6031     block->lir()->insert_before(insert_idx, op);
6032     insert_idx++;
6033 
6034     // delete the instructions at the beginning of all successors
6035     for (i = 0; i < num_sux; i++) {
6036       remove_cur_instruction(i, false);
6037     }
6038   }
6039 }
6040 
6041 
6042 // Implementation of ControlFlowOptimizer
6043 
6044 ControlFlowOptimizer::ControlFlowOptimizer() :
6045   _original_preds(4)
6046 {
6047 }
6048 
6049 void ControlFlowOptimizer::optimize(BlockList* code) {
6050   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6051 
6052   // push the OSR entry block to the end so that we're not jumping over it.
6053   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6054   if (osr_entry) {
6055     int index = osr_entry->linear_scan_number();
6056     assert(code->at(index) == osr_entry, "wrong index");
6057     code->remove_at(index);
6058     code->append(osr_entry);
6059   }
6060 
6061   optimizer.reorder_short_loops(code);
6062   optimizer.delete_empty_blocks(code);
6063   optimizer.delete_unnecessary_jumps(code);
6064   optimizer.delete_jumps_to_return(code);
6065 }
6066 
6067 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6068   int i = header_idx + 1;
6069   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6070   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6071     i++;
6072   }
6073 
6074   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6075     int end_idx = i - 1;
6076     BlockBegin* end_block = code->at(end_idx);
6077 
6078     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6079       // short loop from header_idx to end_idx found -> reorder blocks such that
6080       // the header_block is the last block instead of the first block of the loop
6081       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6082                                          end_idx - header_idx + 1,
6083                                          header_block->block_id(), end_block->block_id()));
6084 
6085       for (int j = header_idx; j < end_idx; j++) {
6086         code->at_put(j, code->at(j + 1));
6087       }
6088       code->at_put(end_idx, header_block);
6089 
6090       // correct the flags so that any loop alignment occurs in the right place.
6091       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6092       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6093       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6094     }
6095   }
6096 }
6097 
6098 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6099   for (int i = code->length() - 1; i >= 0; i--) {
6100     BlockBegin* block = code->at(i);
6101 
6102     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6103       reorder_short_loop(code, block, i);
6104     }
6105   }
6106 
6107   DEBUG_ONLY(verify(code));
6108 }
6109 
6110 // only blocks with exactly one successor can be deleted. Such blocks
6111 // must always end with an unconditional branch to this successor
6112 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6113   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6114     return false;
6115   }
6116 
6117   LIR_OpList* instructions = block->lir()->instructions_list();
6118 
6119   assert(instructions->length() >= 2, "block must have label and branch");
6120   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6121   assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6122   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6123   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6124 
6125   // block must have exactly one successor
6126 
6127   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6128     return true;
6129   }
6130   return false;
6131 }
6132 
6133 // substitute branch targets in all branch-instructions of this blocks
6134 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6135   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6136 
6137   LIR_OpList* instructions = block->lir()->instructions_list();
6138 
6139   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6140   for (int i = instructions->length() - 1; i >= 1; i--) {
6141     LIR_Op* op = instructions->at(i);
6142 
6143     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6144       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6145       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6146 
6147       if (branch->block() == target_from) {
6148         branch->change_block(target_to);
6149       }
6150       if (branch->ublock() == target_from) {
6151         branch->change_ublock(target_to);
6152       }
6153     }
6154   }
6155 }
6156 
6157 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6158   int old_pos = 0;
6159   int new_pos = 0;
6160   int num_blocks = code->length();
6161 
6162   while (old_pos < num_blocks) {
6163     BlockBegin* block = code->at(old_pos);
6164 
6165     if (can_delete_block(block)) {
6166       BlockBegin* new_target = block->sux_at(0);
6167 
6168       // propagate backward branch target flag for correct code alignment
6169       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6170         new_target->set(BlockBegin::backward_branch_target_flag);
6171       }
6172 
6173       // collect a list with all predecessors that contains each predecessor only once
6174       // the predecessors of cur are changed during the substitution, so a copy of the
6175       // predecessor list is necessary
6176       int j;
6177       _original_preds.clear();
6178       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6179         BlockBegin* pred = block->pred_at(j);
6180         if (_original_preds.index_of(pred) == -1) {
6181           _original_preds.append(pred);
6182         }
6183       }
6184 
6185       for (j = _original_preds.length() - 1; j >= 0; j--) {
6186         BlockBegin* pred = _original_preds.at(j);
6187         substitute_branch_target(pred, block, new_target);
6188         pred->substitute_sux(block, new_target);
6189       }
6190     } else {
6191       // adjust position of this block in the block list if blocks before
6192       // have been deleted
6193       if (new_pos != old_pos) {
6194         code->at_put(new_pos, code->at(old_pos));
6195       }
6196       new_pos++;
6197     }
6198     old_pos++;
6199   }
6200   code->truncate(new_pos);
6201 
6202   DEBUG_ONLY(verify(code));
6203 }
6204 
6205 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6206   // skip the last block because there a branch is always necessary
6207   for (int i = code->length() - 2; i >= 0; i--) {
6208     BlockBegin* block = code->at(i);
6209     LIR_OpList* instructions = block->lir()->instructions_list();
6210 
6211     LIR_Op* last_op = instructions->last();
6212     if (last_op->code() == lir_branch) {
6213       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6214       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6215 
6216       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6217       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6218 
6219       if (last_branch->info() == NULL) {
6220         if (last_branch->block() == code->at(i + 1)) {
6221 
6222           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6223 
6224           // delete last branch instruction
6225           instructions->truncate(instructions->length() - 1);
6226 
6227         } else {
6228           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6229           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6230             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6231             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6232 
6233             if (prev_branch->stub() == NULL) {
6234 
6235               LIR_Op2* prev_cmp = NULL;
6236               // There might be a cmove inserted for profiling which depends on the same
6237               // compare. If we change the condition of the respective compare, we have
6238               // to take care of this cmove as well.
6239               LIR_Op2* prev_cmove = NULL;
6240 
6241               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6242                 prev_op = instructions->at(j);
6243                 // check for the cmove
6244                 if (prev_op->code() == lir_cmove) {
6245                   assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
6246                   prev_cmove = (LIR_Op2*)prev_op;
6247                   assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6248                 }
6249                 if (prev_op->code() == lir_cmp) {
6250                   assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6251                   prev_cmp = (LIR_Op2*)prev_op;
6252                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6253                 }
6254               }
6255               assert(prev_cmp != NULL, "should have found comp instruction for branch");
6256               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6257 
6258                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6259 
6260                 // eliminate a conditional branch to the immediate successor
6261                 prev_branch->change_block(last_branch->block());
6262                 prev_branch->negate_cond();
6263                 prev_cmp->set_condition(prev_branch->cond());
6264                 instructions->truncate(instructions->length() - 1);
6265                 // if we do change the condition, we have to change the cmove as well
6266                 if (prev_cmove != NULL) {
6267                   prev_cmove->set_condition(prev_branch->cond());
6268                   LIR_Opr t = prev_cmove->in_opr1();
6269                   prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6270                   prev_cmove->set_in_opr2(t);
6271                 }
6272               }
6273             }
6274           }
6275         }
6276       }
6277     }
6278   }
6279 
6280   DEBUG_ONLY(verify(code));
6281 }
6282 
6283 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6284 #ifdef ASSERT
6285   BitMap return_converted(BlockBegin::number_of_blocks());
6286   return_converted.clear();
6287 #endif
6288 
6289   for (int i = code->length() - 1; i >= 0; i--) {
6290     BlockBegin* block = code->at(i);
6291     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6292     LIR_Op*     cur_last_op = cur_instructions->last();
6293 
6294     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6295     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6296       // the block contains only a label and a return
6297       // if a predecessor ends with an unconditional jump to this block, then the jump
6298       // can be replaced with a return instruction
6299       //
6300       // Note: the original block with only a return statement cannot be deleted completely
6301       //       because the predecessors might have other (conditional) jumps to this block
6302       //       -> this may lead to unnecesary return instructions in the final code
6303 
6304       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6305       assert(block->number_of_sux() == 0 ||
6306              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6307              "blocks that end with return must not have successors");
6308 
6309       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6310       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6311 
6312       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6313         BlockBegin* pred = block->pred_at(j);
6314         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6315         LIR_Op*     pred_last_op = pred_instructions->last();
6316 
6317         if (pred_last_op->code() == lir_branch) {
6318           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6319           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6320 
6321           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6322             // replace the jump to a return with a direct return
6323             // Note: currently the edge between the blocks is not deleted
6324             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_Op1(lir_return, return_opr));
6325 #ifdef ASSERT
6326             return_converted.set_bit(pred->block_id());
6327 #endif
6328           }
6329         }
6330       }
6331     }
6332   }
6333 }
6334 
6335 
6336 #ifdef ASSERT
6337 void ControlFlowOptimizer::verify(BlockList* code) {
6338   for (int i = 0; i < code->length(); i++) {
6339     BlockBegin* block = code->at(i);
6340     LIR_OpList* instructions = block->lir()->instructions_list();
6341 
6342     int j;
6343     for (j = 0; j < instructions->length(); j++) {
6344       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6345 
6346       if (op_branch != NULL) {
6347         assert(op_branch->block() == NULL || code->index_of(op_branch->block()) != -1, "branch target not valid");
6348         assert(op_branch->ublock() == NULL || code->index_of(op_branch->ublock()) != -1, "branch target not valid");
6349       }
6350     }
6351 
6352     for (j = 0; j < block->number_of_sux() - 1; j++) {
6353       BlockBegin* sux = block->sux_at(j);
6354       assert(code->index_of(sux) != -1, "successor not valid");
6355     }
6356 
6357     for (j = 0; j < block->number_of_preds() - 1; j++) {
6358       BlockBegin* pred = block->pred_at(j);
6359       assert(code->index_of(pred) != -1, "successor not valid");
6360     }
6361   }
6362 }
6363 #endif
6364 
6365 
6366 #ifndef PRODUCT
6367 
6368 // Implementation of LinearStatistic
6369 
6370 const char* LinearScanStatistic::counter_name(int counter_idx) {
6371   switch (counter_idx) {
6372     case counter_method:          return "compiled methods";
6373     case counter_fpu_method:      return "methods using fpu";
6374     case counter_loop_method:     return "methods with loops";
6375     case counter_exception_method:return "methods with xhandler";
6376 
6377     case counter_loop:            return "loops";
6378     case counter_block:           return "blocks";
6379     case counter_loop_block:      return "blocks inside loop";
6380     case counter_exception_block: return "exception handler entries";
6381     case counter_interval:        return "intervals";
6382     case counter_fixed_interval:  return "fixed intervals";
6383     case counter_range:           return "ranges";
6384     case counter_fixed_range:     return "fixed ranges";
6385     case counter_use_pos:         return "use positions";
6386     case counter_fixed_use_pos:   return "fixed use positions";
6387     case counter_spill_slots:     return "spill slots";
6388 
6389     // counter for classes of lir instructions
6390     case counter_instruction:     return "total instructions";
6391     case counter_label:           return "labels";
6392     case counter_entry:           return "method entries";
6393     case counter_return:          return "method returns";
6394     case counter_call:            return "method calls";
6395     case counter_move:            return "moves";
6396     case counter_cmp:             return "compare";
6397     case counter_cond_branch:     return "conditional branches";
6398     case counter_uncond_branch:   return "unconditional branches";
6399     case counter_stub_branch:     return "branches to stub";
6400     case counter_alu:             return "artithmetic + logic";
6401     case counter_alloc:           return "allocations";
6402     case counter_sync:            return "synchronisation";
6403     case counter_throw:           return "throw";
6404     case counter_unwind:          return "unwind";
6405     case counter_typecheck:       return "type+null-checks";
6406     case counter_fpu_stack:       return "fpu-stack";
6407     case counter_misc_inst:       return "other instructions";
6408     case counter_other_inst:      return "misc. instructions";
6409 
6410     // counter for different types of moves
6411     case counter_move_total:      return "total moves";
6412     case counter_move_reg_reg:    return "register->register";
6413     case counter_move_reg_stack:  return "register->stack";
6414     case counter_move_stack_reg:  return "stack->register";
6415     case counter_move_stack_stack:return "stack->stack";
6416     case counter_move_reg_mem:    return "register->memory";
6417     case counter_move_mem_reg:    return "memory->register";
6418     case counter_move_const_any:  return "constant->any";
6419 
6420     case blank_line_1:            return "";
6421     case blank_line_2:            return "";
6422 
6423     default: ShouldNotReachHere(); return "";
6424   }
6425 }
6426 
6427 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6428   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6429     return counter_method;
6430   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6431     return counter_block;
6432   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6433     return counter_instruction;
6434   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6435     return counter_move_total;
6436   }
6437   return invalid_counter;
6438 }
6439 
6440 LinearScanStatistic::LinearScanStatistic() {
6441   for (int i = 0; i < number_of_counters; i++) {
6442     _counters_sum[i] = 0;
6443     _counters_max[i] = -1;
6444   }
6445 
6446 }
6447 
6448 // add the method-local numbers to the total sum
6449 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6450   for (int i = 0; i < number_of_counters; i++) {
6451     _counters_sum[i] += method_statistic._counters_sum[i];
6452     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6453   }
6454 }
6455 
6456 void LinearScanStatistic::print(const char* title) {
6457   if (CountLinearScan || TraceLinearScanLevel > 0) {
6458     tty->cr();
6459     tty->print_cr("***** LinearScan statistic - %s *****", title);
6460 
6461     for (int i = 0; i < number_of_counters; i++) {
6462       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6463         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6464 
6465         if (base_counter(i) != invalid_counter) {
6466           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[base_counter(i)]);
6467         } else {
6468           tty->print("           ");
6469         }
6470 
6471         if (_counters_max[i] >= 0) {
6472           tty->print("%8d", _counters_max[i]);
6473         }
6474       }
6475       tty->cr();
6476     }
6477   }
6478 }
6479 
6480 void LinearScanStatistic::collect(LinearScan* allocator) {
6481   inc_counter(counter_method);
6482   if (allocator->has_fpu_registers()) {
6483     inc_counter(counter_fpu_method);
6484   }
6485   if (allocator->num_loops() > 0) {
6486     inc_counter(counter_loop_method);
6487   }
6488   inc_counter(counter_loop, allocator->num_loops());
6489   inc_counter(counter_spill_slots, allocator->max_spills());
6490 
6491   int i;
6492   for (i = 0; i < allocator->interval_count(); i++) {
6493     Interval* cur = allocator->interval_at(i);
6494 
6495     if (cur != NULL) {
6496       inc_counter(counter_interval);
6497       inc_counter(counter_use_pos, cur->num_use_positions());
6498       if (LinearScan::is_precolored_interval(cur)) {
6499         inc_counter(counter_fixed_interval);
6500         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6501       }
6502 
6503       Range* range = cur->first();
6504       while (range != Range::end()) {
6505         inc_counter(counter_range);
6506         if (LinearScan::is_precolored_interval(cur)) {
6507           inc_counter(counter_fixed_range);
6508         }
6509         range = range->next();
6510       }
6511     }
6512   }
6513 
6514   bool has_xhandlers = false;
6515   // Note: only count blocks that are in code-emit order
6516   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6517     BlockBegin* cur = allocator->ir()->code()->at(i);
6518 
6519     inc_counter(counter_block);
6520     if (cur->loop_depth() > 0) {
6521       inc_counter(counter_loop_block);
6522     }
6523     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6524       inc_counter(counter_exception_block);
6525       has_xhandlers = true;
6526     }
6527 
6528     LIR_OpList* instructions = cur->lir()->instructions_list();
6529     for (int j = 0; j < instructions->length(); j++) {
6530       LIR_Op* op = instructions->at(j);
6531 
6532       inc_counter(counter_instruction);
6533 
6534       switch (op->code()) {
6535         case lir_label:           inc_counter(counter_label); break;
6536         case lir_std_entry:
6537         case lir_osr_entry:       inc_counter(counter_entry); break;
6538         case lir_return:          inc_counter(counter_return); break;
6539 
6540         case lir_rtcall:
6541         case lir_static_call:
6542         case lir_optvirtual_call:
6543         case lir_virtual_call:    inc_counter(counter_call); break;
6544 
6545         case lir_move: {
6546           inc_counter(counter_move);
6547           inc_counter(counter_move_total);
6548 
6549           LIR_Opr in = op->as_Op1()->in_opr();
6550           LIR_Opr res = op->as_Op1()->result_opr();
6551           if (in->is_register()) {
6552             if (res->is_register()) {
6553               inc_counter(counter_move_reg_reg);
6554             } else if (res->is_stack()) {
6555               inc_counter(counter_move_reg_stack);
6556             } else if (res->is_address()) {
6557               inc_counter(counter_move_reg_mem);
6558             } else {
6559               ShouldNotReachHere();
6560             }
6561           } else if (in->is_stack()) {
6562             if (res->is_register()) {
6563               inc_counter(counter_move_stack_reg);
6564             } else {
6565               inc_counter(counter_move_stack_stack);
6566             }
6567           } else if (in->is_address()) {
6568             assert(res->is_register(), "must be");
6569             inc_counter(counter_move_mem_reg);
6570           } else if (in->is_constant()) {
6571             inc_counter(counter_move_const_any);
6572           } else {
6573             ShouldNotReachHere();
6574           }
6575           break;
6576         }
6577 
6578         case lir_cmp:             inc_counter(counter_cmp); break;
6579 
6580         case lir_branch:
6581         case lir_cond_float_branch: {
6582           LIR_OpBranch* branch = op->as_OpBranch();
6583           if (branch->block() == NULL) {
6584             inc_counter(counter_stub_branch);
6585           } else if (branch->cond() == lir_cond_always) {
6586             inc_counter(counter_uncond_branch);
6587           } else {
6588             inc_counter(counter_cond_branch);
6589           }
6590           break;
6591         }
6592 
6593         case lir_neg:
6594         case lir_add:
6595         case lir_sub:
6596         case lir_mul:
6597         case lir_mul_strictfp:
6598         case lir_div:
6599         case lir_div_strictfp:
6600         case lir_rem:
6601         case lir_sqrt:
6602         case lir_sin:
6603         case lir_cos:
6604         case lir_abs:
6605         case lir_log10:
6606         case lir_pow:
6607         case lir_logic_and:
6608         case lir_logic_or:
6609         case lir_logic_xor:
6610         case lir_shl:
6611         case lir_shr:
6612         case lir_ushr:            inc_counter(counter_alu); break;
6613 
6614         case lir_alloc_object:
6615         case lir_alloc_array:     inc_counter(counter_alloc); break;
6616 
6617         case lir_monaddr:
6618         case lir_lock:
6619         case lir_unlock:          inc_counter(counter_sync); break;
6620 
6621         case lir_throw:           inc_counter(counter_throw); break;
6622 
6623         case lir_unwind:          inc_counter(counter_unwind); break;
6624 
6625         case lir_null_check:
6626         case lir_leal:
6627         case lir_instanceof:
6628         case lir_checkcast:
6629         case lir_store_check:     inc_counter(counter_typecheck); break;
6630 
6631         case lir_fpop_raw:
6632         case lir_fxch:
6633         case lir_fld:             inc_counter(counter_fpu_stack); break;
6634 
6635         case lir_nop:
6636         case lir_push:
6637         case lir_pop:
6638         case lir_convert:
6639         case lir_roundfp:
6640         case lir_cmove:           inc_counter(counter_misc_inst); break;
6641 
6642         default:                  inc_counter(counter_other_inst); break;
6643       }
6644     }
6645   }
6646 
6647   if (has_xhandlers) {
6648     inc_counter(counter_exception_method);
6649   }
6650 }
6651 
6652 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6653   if (CountLinearScan || TraceLinearScanLevel > 0) {
6654 
6655     LinearScanStatistic local_statistic = LinearScanStatistic();
6656 
6657     local_statistic.collect(allocator);
6658     global_statistic.sum_up(local_statistic);
6659 
6660     if (TraceLinearScanLevel > 2) {
6661       local_statistic.print("current local statistic");
6662     }
6663   }
6664 }
6665 
6666 
6667 // Implementation of LinearTimers
6668 
6669 LinearScanTimers::LinearScanTimers() {
6670   for (int i = 0; i < number_of_timers; i++) {
6671     timer(i)->reset();
6672   }
6673 }
6674 
6675 const char* LinearScanTimers::timer_name(int idx) {
6676   switch (idx) {
6677     case timer_do_nothing:               return "Nothing (Time Check)";
6678     case timer_number_instructions:      return "Number Instructions";
6679     case timer_compute_local_live_sets:  return "Local Live Sets";
6680     case timer_compute_global_live_sets: return "Global Live Sets";
6681     case timer_build_intervals:          return "Build Intervals";
6682     case timer_sort_intervals_before:    return "Sort Intervals Before";
6683     case timer_allocate_registers:       return "Allocate Registers";
6684     case timer_resolve_data_flow:        return "Resolve Data Flow";
6685     case timer_sort_intervals_after:     return "Sort Intervals After";
6686     case timer_eliminate_spill_moves:    return "Spill optimization";
6687     case timer_assign_reg_num:           return "Assign Reg Num";
6688     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6689     case timer_optimize_lir:             return "Optimize LIR";
6690     default: ShouldNotReachHere();       return "";
6691   }
6692 }
6693 
6694 void LinearScanTimers::begin_method() {
6695   if (TimeEachLinearScan) {
6696     // reset all timers to measure only current method
6697     for (int i = 0; i < number_of_timers; i++) {
6698       timer(i)->reset();
6699     }
6700   }
6701 }
6702 
6703 void LinearScanTimers::end_method(LinearScan* allocator) {
6704   if (TimeEachLinearScan) {
6705 
6706     double c = timer(timer_do_nothing)->seconds();
6707     double total = 0;
6708     for (int i = 1; i < number_of_timers; i++) {
6709       total += timer(i)->seconds() - c;
6710     }
6711 
6712     if (total >= 0.0005) {
6713       // print all information in one line for automatic processing
6714       tty->print("@"); allocator->compilation()->method()->print_name();
6715 
6716       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6717       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6718       tty->print("@ %d ", allocator->block_count());
6719       tty->print("@ %d ", allocator->num_virtual_regs());
6720       tty->print("@ %d ", allocator->interval_count());
6721       tty->print("@ %d ", allocator->_num_calls);
6722       tty->print("@ %d ", allocator->num_loops());
6723 
6724       tty->print("@ %6.6f ", total);
6725       for (int i = 1; i < number_of_timers; i++) {
6726         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6727       }
6728       tty->cr();
6729     }
6730   }
6731 }
6732 
6733 void LinearScanTimers::print(double total_time) {
6734   if (TimeLinearScan) {
6735     // correction value: sum of dummy-timer that only measures the time that
6736     // is necesary to start and stop itself
6737     double c = timer(timer_do_nothing)->seconds();
6738 
6739     for (int i = 0; i < number_of_timers; i++) {
6740       double t = timer(i)->seconds();
6741       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6742     }
6743   }
6744 }
6745 
6746 #endif // #ifndef PRODUCT
--- EOF ---