2344 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2345 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2346 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2347 emit_int8(0x6F);
2348 emit_int8((unsigned char)(0xC0 | encode));
2349 }
2350
2351 void Assembler::movdqa(XMMRegister dst, Address src) {
2352 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2353 InstructionMark im(this);
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2355 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2356 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2357 emit_int8(0x6F);
2358 emit_operand(dst, src);
2359 }
2360
2361 void Assembler::movdqu(XMMRegister dst, Address src) {
2362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2363 InstructionMark im(this);
2364 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2365 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2366 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2367 emit_int8(0x6F);
2368 emit_operand(dst, src);
2369 }
2370
2371 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2374 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2375 emit_int8(0x6F);
2376 emit_int8((unsigned char)(0xC0 | encode));
2377 }
2378
2379 void Assembler::movdqu(Address dst, XMMRegister src) {
2380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2381 InstructionMark im(this);
2382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2383 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2384 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2385 emit_int8(0x7F);
2386 emit_operand(src, dst);
2387 }
2388
2389 // Move Unaligned 256bit Vector
2390 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2391 assert(UseAVX > 0, "");
2392 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2393 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2394 emit_int8(0x6F);
2395 emit_int8((unsigned char)(0xC0 | encode));
2396 }
2397
2398 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2399 assert(UseAVX > 0, "");
2400 InstructionMark im(this);
2401 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2402 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2403 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2404 emit_int8(0x6F);
2405 emit_operand(dst, src);
2406 }
2407
2408 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2409 assert(UseAVX > 0, "");
2410 InstructionMark im(this);
2411 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2412 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2413 // swap src<->dst for encoding
2414 assert(src != xnoreg, "sanity");
2415 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2416 emit_int8(0x7F);
2417 emit_operand(src, dst);
2418 }
2419
2420 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2421 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2469 assert(VM_Version::supports_evex(), "");
2470 assert(src != xnoreg, "sanity");
2471 InstructionMark im(this);
2472 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2473 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2474 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2475 emit_int8(0x7F);
2476 emit_operand(src, dst);
2477 }
2478 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2479 assert(VM_Version::supports_evex(), "");
2480 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2481 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2482 emit_int8(0x6F);
2483 emit_int8((unsigned char)(0xC0 | encode));
2484 }
2485
2486 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2487 assert(VM_Version::supports_evex(), "");
2488 InstructionMark im(this);
2489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2490 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2491 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2492 emit_int8(0x6F);
2493 emit_operand(dst, src);
2494 }
2495
2496 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2497 assert(VM_Version::supports_evex(), "");
2498 assert(src != xnoreg, "sanity");
2499 InstructionMark im(this);
2500 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2501 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2502 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2503 emit_int8(0x7F);
2504 emit_operand(src, dst);
2505 }
2506
2507 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2508 assert(VM_Version::supports_evex(), "");
2509 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2510 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2511 emit_int8(0x6F);
2512 emit_int8((unsigned char)(0xC0 | encode));
2513 }
2514
2515 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2516 assert(VM_Version::supports_evex(), "");
2517 InstructionMark im(this);
2518 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2519 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2520 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2521 emit_int8(0x6F);
2522 emit_operand(dst, src);
2523 }
2524
2525 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2526 assert(VM_Version::supports_evex(), "");
2527 assert(src != xnoreg, "sanity");
2528 InstructionMark im(this);
2529 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2530 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2531 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2532 emit_int8(0x7F);
2533 emit_operand(src, dst);
2534 }
2535
2536 // Uses zero extension on 64bit
2537
2538 void Assembler::movl(Register dst, int32_t imm32) {
2623 }
2624
2625 void Assembler::movsbl(Register dst, Address src) { // movsxb
2626 InstructionMark im(this);
2627 prefix(src, dst);
2628 emit_int8(0x0F);
2629 emit_int8((unsigned char)0xBE);
2630 emit_operand(dst, src);
2631 }
2632
2633 void Assembler::movsbl(Register dst, Register src) { // movsxb
2634 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2635 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2636 emit_int8(0x0F);
2637 emit_int8((unsigned char)0xBE);
2638 emit_int8((unsigned char)(0xC0 | encode));
2639 }
2640
2641 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2642 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2643 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2644 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2645 emit_int8(0x10);
2646 emit_int8((unsigned char)(0xC0 | encode));
2647 }
2648
2649 void Assembler::movsd(XMMRegister dst, Address src) {
2650 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2651 InstructionMark im(this);
2652 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2653 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2654 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2655 emit_int8(0x10);
2656 emit_operand(dst, src);
2657 }
2658
2659 void Assembler::movsd(Address dst, XMMRegister src) {
2660 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2661 InstructionMark im(this);
2662 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2663 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2664 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2665 emit_int8(0x11);
2666 emit_operand(src, dst);
2667 }
2668
2669 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2670 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2671 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2672 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2673 emit_int8(0x10);
2674 emit_int8((unsigned char)(0xC0 | encode));
2675 }
2676
2677 void Assembler::movss(XMMRegister dst, Address src) {
2678 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2679 InstructionMark im(this);
2680 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2681 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2682 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2683 emit_int8(0x10);
2684 emit_operand(dst, src);
2685 }
2686
2687 void Assembler::movss(Address dst, XMMRegister src) {
2688 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2689 InstructionMark im(this);
2690 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2691 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2692 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2693 emit_int8(0x11);
2694 emit_operand(src, dst);
2695 }
2696
2697 void Assembler::movswl(Register dst, Address src) { // movsxw
2698 InstructionMark im(this);
2699 prefix(src, dst);
2700 emit_int8(0x0F);
2765 emit_int8((unsigned char)0xB7);
2766 emit_int8(0xC0 | encode);
2767 }
2768
2769 void Assembler::mull(Address src) {
2770 InstructionMark im(this);
2771 prefix(src);
2772 emit_int8((unsigned char)0xF7);
2773 emit_operand(rsp, src);
2774 }
2775
2776 void Assembler::mull(Register src) {
2777 int encode = prefix_and_encode(src->encoding());
2778 emit_int8((unsigned char)0xF7);
2779 emit_int8((unsigned char)(0xE0 | encode));
2780 }
2781
2782 void Assembler::mulsd(XMMRegister dst, Address src) {
2783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2784 InstructionMark im(this);
2785 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2787 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2788 emit_int8(0x59);
2789 emit_operand(dst, src);
2790 }
2791
2792 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2793 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2794 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2795 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2796 emit_int8(0x59);
2797 emit_int8((unsigned char)(0xC0 | encode));
2798 }
2799
2800 void Assembler::mulss(XMMRegister dst, Address src) {
2801 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2802 InstructionMark im(this);
2803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2806 emit_int8(0x59);
2807 emit_operand(dst, src);
2808 }
2809
2810 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2811 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2813 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2814 emit_int8(0x59);
2815 emit_int8((unsigned char)(0xC0 | encode));
2816 }
2817
2818 void Assembler::negl(Register dst) {
2819 int encode = prefix_and_encode(dst->encoding());
2820 emit_int8((unsigned char)0xF7);
2821 emit_int8((unsigned char)(0xD8 | encode));
2822 }
2823
2824 void Assembler::nop(int i) {
2825 #ifdef ASSERT
2826 assert(i > 0, " ");
2827 // The fancy nops aren't currently recognized by debuggers making it a
2828 // pain to disassemble code while debugging. If asserts are on clearly
2829 // speed is not an issue so simply use the single byte traditional nop
2830 // to do alignment.
2831
2832 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3976 assert(isShiftCount(imm8), "illegal shift count");
3977 int encode = prefix_and_encode(dst->encoding());
3978 emit_int8((unsigned char)0xC1);
3979 emit_int8((unsigned char)(0xE8 | encode));
3980 emit_int8(imm8);
3981 }
3982
3983 void Assembler::shrl(Register dst) {
3984 int encode = prefix_and_encode(dst->encoding());
3985 emit_int8((unsigned char)0xD3);
3986 emit_int8((unsigned char)(0xE8 | encode));
3987 }
3988
3989 // copies a single word from [esi] to [edi]
3990 void Assembler::smovl() {
3991 emit_int8((unsigned char)0xA5);
3992 }
3993
3994 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3995 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3996 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3997 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3998 emit_int8(0x51);
3999 emit_int8((unsigned char)(0xC0 | encode));
4000 }
4001
4002 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4003 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4004 InstructionMark im(this);
4005 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4006 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4007 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4008 emit_int8(0x51);
4009 emit_operand(dst, src);
4010 }
4011
4012 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4013 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4014 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4015 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4016 emit_int8(0x51);
4017 emit_int8((unsigned char)(0xC0 | encode));
4018 }
4019
4020 void Assembler::std() {
4021 emit_int8((unsigned char)0xFD);
4022 }
4023
4024 void Assembler::sqrtss(XMMRegister dst, Address src) {
4025 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4026 InstructionMark im(this);
4027 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4028 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4029 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4030 emit_int8(0x51);
4031 emit_operand(dst, src);
4032 }
4033
4034 void Assembler::stmxcsr( Address dst) {
4035 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4036 InstructionMark im(this);
4037 prefix(dst);
4038 emit_int8(0x0F);
4039 emit_int8((unsigned char)0xAE);
4040 emit_operand(as_Register(3), dst);
4041 }
4042
4043 void Assembler::subl(Address dst, int32_t imm32) {
4044 InstructionMark im(this);
4045 prefix(dst);
4046 emit_arith_operand(0x81, rbp, dst, imm32);
4047 }
4061 // Force generation of a 4 byte immediate value even if it fits into 8bit
4062 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4063 prefix(dst);
4064 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4065 }
4066
4067 void Assembler::subl(Register dst, Address src) {
4068 InstructionMark im(this);
4069 prefix(src, dst);
4070 emit_int8(0x2B);
4071 emit_operand(dst, src);
4072 }
4073
4074 void Assembler::subl(Register dst, Register src) {
4075 (void) prefix_and_encode(dst->encoding(), src->encoding());
4076 emit_arith(0x2B, 0xC0, dst, src);
4077 }
4078
4079 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4080 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4081 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4082 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4083 emit_int8(0x5C);
4084 emit_int8((unsigned char)(0xC0 | encode));
4085 }
4086
4087 void Assembler::subsd(XMMRegister dst, Address src) {
4088 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4089 InstructionMark im(this);
4090 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4091 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4092 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4093 emit_int8(0x5C);
4094 emit_operand(dst, src);
4095 }
4096
4097 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4098 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4099 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4100 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4101 emit_int8(0x5C);
4102 emit_int8((unsigned char)(0xC0 | encode));
4103 }
4104
4105 void Assembler::subss(XMMRegister dst, Address src) {
4106 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4107 InstructionMark im(this);
4108 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4109 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4110 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4111 emit_int8(0x5C);
4112 emit_operand(dst, src);
4113 }
4114
4115 void Assembler::testb(Register dst, int imm8) {
4116 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4117 (void) prefix_and_encode(dst->encoding(), true);
4118 emit_arith_b(0xF6, 0xC0, dst, imm8);
4119 }
4120
4121 void Assembler::testb(Address dst, int imm8) {
4122 InstructionMark im(this);
4123 prefix(dst);
4124 emit_int8((unsigned char)0xF6);
4125 emit_operand(rax, dst, 1);
4126 emit_int8(imm8);
4127 }
4128
4276 emit_operand(dst, src);
4277 }
4278
4279 void Assembler::xorl(Register dst, Register src) {
4280 (void) prefix_and_encode(dst->encoding(), src->encoding());
4281 emit_arith(0x33, 0xC0, dst, src);
4282 }
4283
4284 void Assembler::xorb(Register dst, Address src) {
4285 InstructionMark im(this);
4286 prefix(src, dst);
4287 emit_int8(0x32);
4288 emit_operand(dst, src);
4289 }
4290
4291 // AVX 3-operands scalar float-point arithmetic instructions
4292
4293 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4294 assert(VM_Version::supports_avx(), "");
4295 InstructionMark im(this);
4296 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4297 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4298 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4299 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4300 emit_int8(0x58);
4301 emit_operand(dst, src);
4302 }
4303
4304 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4305 assert(VM_Version::supports_avx(), "");
4306 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4307 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4308 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4309 emit_int8(0x58);
4310 emit_int8((unsigned char)(0xC0 | encode));
4311 }
4312
4313 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4314 assert(VM_Version::supports_avx(), "");
4315 InstructionMark im(this);
4316 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4317 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4318 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4319 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4320 emit_int8(0x58);
4321 emit_operand(dst, src);
4322 }
4323
4324 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4325 assert(VM_Version::supports_avx(), "");
4326 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4327 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4328 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4329 emit_int8(0x58);
4330 emit_int8((unsigned char)(0xC0 | encode));
4331 }
4332
4333 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4334 assert(VM_Version::supports_avx(), "");
4335 InstructionMark im(this);
4336 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4337 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4338 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4339 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4340 emit_int8(0x5E);
4341 emit_operand(dst, src);
4342 }
4343
4344 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4345 assert(VM_Version::supports_avx(), "");
4346 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4347 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4348 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4349 emit_int8(0x5E);
4350 emit_int8((unsigned char)(0xC0 | encode));
4351 }
4352
4353 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4354 assert(VM_Version::supports_avx(), "");
4355 InstructionMark im(this);
4356 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4357 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4358 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4359 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4360 emit_int8(0x5E);
4361 emit_operand(dst, src);
4362 }
4363
4364 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4365 assert(VM_Version::supports_avx(), "");
4366 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4367 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4368 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4369 emit_int8(0x5E);
4370 emit_int8((unsigned char)(0xC0 | encode));
4371 }
4372
4373 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4374 assert(VM_Version::supports_avx(), "");
4375 InstructionMark im(this);
4376 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4377 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4378 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4379 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4380 emit_int8(0x59);
4381 emit_operand(dst, src);
4382 }
4383
4384 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4385 assert(VM_Version::supports_avx(), "");
4386 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4387 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4388 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4389 emit_int8(0x59);
4390 emit_int8((unsigned char)(0xC0 | encode));
4391 }
4392
4393 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4394 assert(VM_Version::supports_avx(), "");
4395 InstructionMark im(this);
4396 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4397 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4398 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4399 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4400 emit_int8(0x59);
4401 emit_operand(dst, src);
4402 }
4403
4404 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4405 assert(VM_Version::supports_avx(), "");
4406 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4407 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4408 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4409 emit_int8(0x59);
4410 emit_int8((unsigned char)(0xC0 | encode));
4411 }
4412
4413 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4414 assert(VM_Version::supports_avx(), "");
4415 InstructionMark im(this);
4416 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4417 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4418 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4419 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4420 emit_int8(0x5C);
4421 emit_operand(dst, src);
4422 }
4423
4424 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4425 assert(VM_Version::supports_avx(), "");
4426 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4427 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4428 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4429 emit_int8(0x5C);
4430 emit_int8((unsigned char)(0xC0 | encode));
4431 }
4432
4433 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4434 assert(VM_Version::supports_avx(), "");
4435 InstructionMark im(this);
4436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4437 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4438 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4439 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4440 emit_int8(0x5C);
4441 emit_operand(dst, src);
4442 }
4443
4444 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4445 assert(VM_Version::supports_avx(), "");
4446 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4447 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4448 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4449 emit_int8(0x5C);
4450 emit_int8((unsigned char)(0xC0 | encode));
4451 }
4452
4453 //====================VECTOR ARITHMETIC=====================================
4454
4455 // Float-point vector arithmetic
4456
4457 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4458 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4459 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4460 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4461 emit_int8(0x58);
4462 emit_int8((unsigned char)(0xC0 | encode));
4463 }
4464
4465 void Assembler::addpd(XMMRegister dst, Address src) {
4466 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5884 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5885 assert(VM_Version::supports_avx2(), "");
5886 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5887 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5888 emit_int8(0x58);
5889 emit_int8((unsigned char)(0xC0 | encode));
5890 }
5891
5892 // duplicate 2-bytes integer data from src into 16 locations in dest
5893 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
5894 assert(VM_Version::supports_avx2(), "");
5895 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5896 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5897 emit_int8(0x79);
5898 emit_int8((unsigned char)(0xC0 | encode));
5899 }
5900
5901 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5902 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5903 assert(VM_Version::supports_evex(), "");
5904 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5905 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5906 emit_int8(0x78);
5907 emit_int8((unsigned char)(0xC0 | encode));
5908 }
5909
5910 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5911 assert(VM_Version::supports_evex(), "");
5912 assert(dst != xnoreg, "sanity");
5913 InstructionMark im(this);
5914 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5915 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
5916 // swap src<->dst for encoding
5917 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5918 emit_int8(0x78);
5919 emit_operand(dst, src);
5920 }
5921
5922 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5923 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5924 assert(VM_Version::supports_evex(), "");
5925 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5926 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5927 emit_int8(0x79);
5928 emit_int8((unsigned char)(0xC0 | encode));
5929 }
5930
5931 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5932 assert(VM_Version::supports_evex(), "");
5933 assert(dst != xnoreg, "sanity");
5934 InstructionMark im(this);
5935 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5936 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
5937 // swap src<->dst for encoding
5938 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5939 emit_int8(0x79);
5940 emit_operand(dst, src);
5941 }
5942
5943 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5944 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5945 assert(VM_Version::supports_evex(), "");
5946 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5947 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5948 emit_int8(0x58);
5949 emit_int8((unsigned char)(0xC0 | encode));
5950 }
5951
5952 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5953 assert(VM_Version::supports_evex(), "");
5954 assert(dst != xnoreg, "sanity");
5955 InstructionMark im(this);
6010 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6011 emit_int8(0x19);
6012 emit_int8((unsigned char)(0xC0 | encode));
6013 }
6014
6015 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6016 assert(VM_Version::supports_evex(), "");
6017 assert(dst != xnoreg, "sanity");
6018 InstructionMark im(this);
6019 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6020 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6021 // swap src<->dst for encoding
6022 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6023 emit_int8(0x19);
6024 emit_operand(dst, src);
6025 }
6026
6027 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6028 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6029 assert(VM_Version::supports_evex(), "");
6030 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6031 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6032 emit_int8(0x7A);
6033 emit_int8((unsigned char)(0xC0 | encode));
6034 }
6035
6036 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6037 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6038 assert(VM_Version::supports_evex(), "");
6039 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6040 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6041 emit_int8(0x7B);
6042 emit_int8((unsigned char)(0xC0 | encode));
6043 }
6044
6045 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6046 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6047 assert(VM_Version::supports_evex(), "");
6048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6049 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6050 emit_int8(0x7C);
6051 emit_int8((unsigned char)(0xC0 | encode));
6052 }
6053
6054 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6055 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6056 assert(VM_Version::supports_evex(), "");
6057 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6058 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6059 emit_int8(0x7C);
|
2344 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2345 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2346 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2347 emit_int8(0x6F);
2348 emit_int8((unsigned char)(0xC0 | encode));
2349 }
2350
2351 void Assembler::movdqa(XMMRegister dst, Address src) {
2352 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2353 InstructionMark im(this);
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2355 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2356 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2357 emit_int8(0x6F);
2358 emit_operand(dst, src);
2359 }
2360
2361 void Assembler::movdqu(XMMRegister dst, Address src) {
2362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2363 InstructionMark im(this);
2364 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2365 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2366 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2367 emit_int8(0x6F);
2368 emit_operand(dst, src);
2369 }
2370
2371 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2374 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2375 emit_int8(0x6F);
2376 emit_int8((unsigned char)(0xC0 | encode));
2377 }
2378
2379 void Assembler::movdqu(Address dst, XMMRegister src) {
2380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2381 InstructionMark im(this);
2382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2383 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2384 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2385 emit_int8(0x7F);
2386 emit_operand(src, dst);
2387 }
2388
2389 // Move Unaligned 256bit Vector
2390 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2391 assert(UseAVX > 0, "");
2392 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2393 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2394 emit_int8(0x6F);
2395 emit_int8((unsigned char)(0xC0 | encode));
2396 }
2397
2398 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2399 assert(UseAVX > 0, "");
2400 InstructionMark im(this);
2401 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2402 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2403 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2404 emit_int8(0x6F);
2405 emit_operand(dst, src);
2406 }
2407
2408 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2409 assert(UseAVX > 0, "");
2410 InstructionMark im(this);
2411 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2412 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2413 // swap src<->dst for encoding
2414 assert(src != xnoreg, "sanity");
2415 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2416 emit_int8(0x7F);
2417 emit_operand(src, dst);
2418 }
2419
2420 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2421 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2469 assert(VM_Version::supports_evex(), "");
2470 assert(src != xnoreg, "sanity");
2471 InstructionMark im(this);
2472 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2473 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2474 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2475 emit_int8(0x7F);
2476 emit_operand(src, dst);
2477 }
2478 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2479 assert(VM_Version::supports_evex(), "");
2480 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2481 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2482 emit_int8(0x6F);
2483 emit_int8((unsigned char)(0xC0 | encode));
2484 }
2485
2486 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2487 assert(VM_Version::supports_evex(), "");
2488 InstructionMark im(this);
2489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2490 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2491 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2492 emit_int8(0x6F);
2493 emit_operand(dst, src);
2494 }
2495
2496 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2497 assert(VM_Version::supports_evex(), "");
2498 assert(src != xnoreg, "sanity");
2499 InstructionMark im(this);
2500 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2501 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2502 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2503 emit_int8(0x7F);
2504 emit_operand(src, dst);
2505 }
2506
2507 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2508 assert(VM_Version::supports_evex(), "");
2509 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2510 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2511 emit_int8(0x6F);
2512 emit_int8((unsigned char)(0xC0 | encode));
2513 }
2514
2515 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2516 assert(VM_Version::supports_evex(), "");
2517 InstructionMark im(this);
2518 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2519 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2520 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2521 emit_int8(0x6F);
2522 emit_operand(dst, src);
2523 }
2524
2525 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2526 assert(VM_Version::supports_evex(), "");
2527 assert(src != xnoreg, "sanity");
2528 InstructionMark im(this);
2529 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2530 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2531 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2532 emit_int8(0x7F);
2533 emit_operand(src, dst);
2534 }
2535
2536 // Uses zero extension on 64bit
2537
2538 void Assembler::movl(Register dst, int32_t imm32) {
2623 }
2624
2625 void Assembler::movsbl(Register dst, Address src) { // movsxb
2626 InstructionMark im(this);
2627 prefix(src, dst);
2628 emit_int8(0x0F);
2629 emit_int8((unsigned char)0xBE);
2630 emit_operand(dst, src);
2631 }
2632
2633 void Assembler::movsbl(Register dst, Register src) { // movsxb
2634 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2635 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2636 emit_int8(0x0F);
2637 emit_int8((unsigned char)0xBE);
2638 emit_int8((unsigned char)(0xC0 | encode));
2639 }
2640
2641 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2642 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2643 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2644 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2645 emit_int8(0x10);
2646 emit_int8((unsigned char)(0xC0 | encode));
2647 }
2648
2649 void Assembler::movsd(XMMRegister dst, Address src) {
2650 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2651 InstructionMark im(this);
2652 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2653 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2654 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2655 emit_int8(0x10);
2656 emit_operand(dst, src);
2657 }
2658
2659 void Assembler::movsd(Address dst, XMMRegister src) {
2660 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2661 InstructionMark im(this);
2662 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2663 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2664 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2665 emit_int8(0x11);
2666 emit_operand(src, dst);
2667 }
2668
2669 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2670 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2671 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2672 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2673 emit_int8(0x10);
2674 emit_int8((unsigned char)(0xC0 | encode));
2675 }
2676
2677 void Assembler::movss(XMMRegister dst, Address src) {
2678 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2679 InstructionMark im(this);
2680 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2681 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2682 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2683 emit_int8(0x10);
2684 emit_operand(dst, src);
2685 }
2686
2687 void Assembler::movss(Address dst, XMMRegister src) {
2688 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2689 InstructionMark im(this);
2690 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2691 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2692 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2693 emit_int8(0x11);
2694 emit_operand(src, dst);
2695 }
2696
2697 void Assembler::movswl(Register dst, Address src) { // movsxw
2698 InstructionMark im(this);
2699 prefix(src, dst);
2700 emit_int8(0x0F);
2765 emit_int8((unsigned char)0xB7);
2766 emit_int8(0xC0 | encode);
2767 }
2768
2769 void Assembler::mull(Address src) {
2770 InstructionMark im(this);
2771 prefix(src);
2772 emit_int8((unsigned char)0xF7);
2773 emit_operand(rsp, src);
2774 }
2775
2776 void Assembler::mull(Register src) {
2777 int encode = prefix_and_encode(src->encoding());
2778 emit_int8((unsigned char)0xF7);
2779 emit_int8((unsigned char)(0xE0 | encode));
2780 }
2781
2782 void Assembler::mulsd(XMMRegister dst, Address src) {
2783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2784 InstructionMark im(this);
2785 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2787 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2788 emit_int8(0x59);
2789 emit_operand(dst, src);
2790 }
2791
2792 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2793 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2794 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2795 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2796 emit_int8(0x59);
2797 emit_int8((unsigned char)(0xC0 | encode));
2798 }
2799
2800 void Assembler::mulss(XMMRegister dst, Address src) {
2801 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2802 InstructionMark im(this);
2803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2806 emit_int8(0x59);
2807 emit_operand(dst, src);
2808 }
2809
2810 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2811 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2813 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2814 emit_int8(0x59);
2815 emit_int8((unsigned char)(0xC0 | encode));
2816 }
2817
2818 void Assembler::negl(Register dst) {
2819 int encode = prefix_and_encode(dst->encoding());
2820 emit_int8((unsigned char)0xF7);
2821 emit_int8((unsigned char)(0xD8 | encode));
2822 }
2823
2824 void Assembler::nop(int i) {
2825 #ifdef ASSERT
2826 assert(i > 0, " ");
2827 // The fancy nops aren't currently recognized by debuggers making it a
2828 // pain to disassemble code while debugging. If asserts are on clearly
2829 // speed is not an issue so simply use the single byte traditional nop
2830 // to do alignment.
2831
2832 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3976 assert(isShiftCount(imm8), "illegal shift count");
3977 int encode = prefix_and_encode(dst->encoding());
3978 emit_int8((unsigned char)0xC1);
3979 emit_int8((unsigned char)(0xE8 | encode));
3980 emit_int8(imm8);
3981 }
3982
3983 void Assembler::shrl(Register dst) {
3984 int encode = prefix_and_encode(dst->encoding());
3985 emit_int8((unsigned char)0xD3);
3986 emit_int8((unsigned char)(0xE8 | encode));
3987 }
3988
3989 // copies a single word from [esi] to [edi]
3990 void Assembler::smovl() {
3991 emit_int8((unsigned char)0xA5);
3992 }
3993
3994 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
3995 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3996 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3997 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3998 emit_int8(0x51);
3999 emit_int8((unsigned char)(0xC0 | encode));
4000 }
4001
4002 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4003 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4004 InstructionMark im(this);
4005 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4006 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4007 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4008 emit_int8(0x51);
4009 emit_operand(dst, src);
4010 }
4011
4012 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4013 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4014 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4015 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4016 emit_int8(0x51);
4017 emit_int8((unsigned char)(0xC0 | encode));
4018 }
4019
4020 void Assembler::std() {
4021 emit_int8((unsigned char)0xFD);
4022 }
4023
4024 void Assembler::sqrtss(XMMRegister dst, Address src) {
4025 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4026 InstructionMark im(this);
4027 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4028 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4029 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4030 emit_int8(0x51);
4031 emit_operand(dst, src);
4032 }
4033
4034 void Assembler::stmxcsr( Address dst) {
4035 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4036 InstructionMark im(this);
4037 prefix(dst);
4038 emit_int8(0x0F);
4039 emit_int8((unsigned char)0xAE);
4040 emit_operand(as_Register(3), dst);
4041 }
4042
4043 void Assembler::subl(Address dst, int32_t imm32) {
4044 InstructionMark im(this);
4045 prefix(dst);
4046 emit_arith_operand(0x81, rbp, dst, imm32);
4047 }
4061 // Force generation of a 4 byte immediate value even if it fits into 8bit
4062 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4063 prefix(dst);
4064 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4065 }
4066
4067 void Assembler::subl(Register dst, Address src) {
4068 InstructionMark im(this);
4069 prefix(src, dst);
4070 emit_int8(0x2B);
4071 emit_operand(dst, src);
4072 }
4073
4074 void Assembler::subl(Register dst, Register src) {
4075 (void) prefix_and_encode(dst->encoding(), src->encoding());
4076 emit_arith(0x2B, 0xC0, dst, src);
4077 }
4078
4079 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4080 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4081 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4082 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4083 emit_int8(0x5C);
4084 emit_int8((unsigned char)(0xC0 | encode));
4085 }
4086
4087 void Assembler::subsd(XMMRegister dst, Address src) {
4088 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4089 InstructionMark im(this);
4090 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4091 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4092 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4093 emit_int8(0x5C);
4094 emit_operand(dst, src);
4095 }
4096
4097 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4098 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4099 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4100 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4101 emit_int8(0x5C);
4102 emit_int8((unsigned char)(0xC0 | encode));
4103 }
4104
4105 void Assembler::subss(XMMRegister dst, Address src) {
4106 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4107 InstructionMark im(this);
4108 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4109 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4110 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4111 emit_int8(0x5C);
4112 emit_operand(dst, src);
4113 }
4114
4115 void Assembler::testb(Register dst, int imm8) {
4116 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4117 (void) prefix_and_encode(dst->encoding(), true);
4118 emit_arith_b(0xF6, 0xC0, dst, imm8);
4119 }
4120
4121 void Assembler::testb(Address dst, int imm8) {
4122 InstructionMark im(this);
4123 prefix(dst);
4124 emit_int8((unsigned char)0xF6);
4125 emit_operand(rax, dst, 1);
4126 emit_int8(imm8);
4127 }
4128
4276 emit_operand(dst, src);
4277 }
4278
4279 void Assembler::xorl(Register dst, Register src) {
4280 (void) prefix_and_encode(dst->encoding(), src->encoding());
4281 emit_arith(0x33, 0xC0, dst, src);
4282 }
4283
4284 void Assembler::xorb(Register dst, Address src) {
4285 InstructionMark im(this);
4286 prefix(src, dst);
4287 emit_int8(0x32);
4288 emit_operand(dst, src);
4289 }
4290
4291 // AVX 3-operands scalar float-point arithmetic instructions
4292
4293 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4294 assert(VM_Version::supports_avx(), "");
4295 InstructionMark im(this);
4296 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4297 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4298 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4299 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4300 emit_int8(0x58);
4301 emit_operand(dst, src);
4302 }
4303
4304 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4305 assert(VM_Version::supports_avx(), "");
4306 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4307 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4308 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4309 emit_int8(0x58);
4310 emit_int8((unsigned char)(0xC0 | encode));
4311 }
4312
4313 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4314 assert(VM_Version::supports_avx(), "");
4315 InstructionMark im(this);
4316 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4317 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4318 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4319 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4320 emit_int8(0x58);
4321 emit_operand(dst, src);
4322 }
4323
4324 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4325 assert(VM_Version::supports_avx(), "");
4326 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4327 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4328 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4329 emit_int8(0x58);
4330 emit_int8((unsigned char)(0xC0 | encode));
4331 }
4332
4333 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4334 assert(VM_Version::supports_avx(), "");
4335 InstructionMark im(this);
4336 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4337 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4338 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4339 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4340 emit_int8(0x5E);
4341 emit_operand(dst, src);
4342 }
4343
4344 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4345 assert(VM_Version::supports_avx(), "");
4346 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4347 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4348 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4349 emit_int8(0x5E);
4350 emit_int8((unsigned char)(0xC0 | encode));
4351 }
4352
4353 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4354 assert(VM_Version::supports_avx(), "");
4355 InstructionMark im(this);
4356 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4357 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4358 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4359 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4360 emit_int8(0x5E);
4361 emit_operand(dst, src);
4362 }
4363
4364 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4365 assert(VM_Version::supports_avx(), "");
4366 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4367 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4368 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4369 emit_int8(0x5E);
4370 emit_int8((unsigned char)(0xC0 | encode));
4371 }
4372
4373 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4374 assert(VM_Version::supports_avx(), "");
4375 InstructionMark im(this);
4376 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4377 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4378 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4379 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4380 emit_int8(0x59);
4381 emit_operand(dst, src);
4382 }
4383
4384 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4385 assert(VM_Version::supports_avx(), "");
4386 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4387 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4388 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4389 emit_int8(0x59);
4390 emit_int8((unsigned char)(0xC0 | encode));
4391 }
4392
4393 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4394 assert(VM_Version::supports_avx(), "");
4395 InstructionMark im(this);
4396 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4397 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4398 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4399 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4400 emit_int8(0x59);
4401 emit_operand(dst, src);
4402 }
4403
4404 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4405 assert(VM_Version::supports_avx(), "");
4406 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4407 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4408 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4409 emit_int8(0x59);
4410 emit_int8((unsigned char)(0xC0 | encode));
4411 }
4412
4413 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4414 assert(VM_Version::supports_avx(), "");
4415 InstructionMark im(this);
4416 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4417 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4418 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4419 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4420 emit_int8(0x5C);
4421 emit_operand(dst, src);
4422 }
4423
4424 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4425 assert(VM_Version::supports_avx(), "");
4426 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4427 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4428 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4429 emit_int8(0x5C);
4430 emit_int8((unsigned char)(0xC0 | encode));
4431 }
4432
4433 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4434 assert(VM_Version::supports_avx(), "");
4435 InstructionMark im(this);
4436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4437 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4438 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4439 vex_prefix(src, nds_enc, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4440 emit_int8(0x5C);
4441 emit_operand(dst, src);
4442 }
4443
4444 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4445 assert(VM_Version::supports_avx(), "");
4446 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4447 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
4448 int encode = vex_prefix_and_encode(dst->encoding(), nds_enc, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4449 emit_int8(0x5C);
4450 emit_int8((unsigned char)(0xC0 | encode));
4451 }
4452
4453 //====================VECTOR ARITHMETIC=====================================
4454
4455 // Float-point vector arithmetic
4456
4457 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4458 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4459 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4460 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4461 emit_int8(0x58);
4462 emit_int8((unsigned char)(0xC0 | encode));
4463 }
4464
4465 void Assembler::addpd(XMMRegister dst, Address src) {
4466 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5884 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
5885 assert(VM_Version::supports_avx2(), "");
5886 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5887 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5888 emit_int8(0x58);
5889 emit_int8((unsigned char)(0xC0 | encode));
5890 }
5891
5892 // duplicate 2-bytes integer data from src into 16 locations in dest
5893 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
5894 assert(VM_Version::supports_avx2(), "");
5895 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5896 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5897 emit_int8(0x79);
5898 emit_int8((unsigned char)(0xC0 | encode));
5899 }
5900
5901 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
5902 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
5903 assert(VM_Version::supports_evex(), "");
5904 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5905 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5906 emit_int8(0x78);
5907 emit_int8((unsigned char)(0xC0 | encode));
5908 }
5909
5910 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
5911 assert(VM_Version::supports_evex(), "");
5912 assert(dst != xnoreg, "sanity");
5913 InstructionMark im(this);
5914 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5915 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
5916 // swap src<->dst for encoding
5917 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5918 emit_int8(0x78);
5919 emit_operand(dst, src);
5920 }
5921
5922 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
5923 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
5924 assert(VM_Version::supports_evex(), "");
5925 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5926 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5927 emit_int8(0x79);
5928 emit_int8((unsigned char)(0xC0 | encode));
5929 }
5930
5931 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
5932 assert(VM_Version::supports_evex(), "");
5933 assert(dst != xnoreg, "sanity");
5934 InstructionMark im(this);
5935 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5936 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
5937 // swap src<->dst for encoding
5938 vex_prefix(src, dst->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5939 emit_int8(0x79);
5940 emit_operand(dst, src);
5941 }
5942
5943 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
5944 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
5945 assert(VM_Version::supports_evex(), "");
5946 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5947 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5948 emit_int8(0x58);
5949 emit_int8((unsigned char)(0xC0 | encode));
5950 }
5951
5952 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
5953 assert(VM_Version::supports_evex(), "");
5954 assert(dst != xnoreg, "sanity");
5955 InstructionMark im(this);
6010 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6011 emit_int8(0x19);
6012 emit_int8((unsigned char)(0xC0 | encode));
6013 }
6014
6015 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6016 assert(VM_Version::supports_evex(), "");
6017 assert(dst != xnoreg, "sanity");
6018 InstructionMark im(this);
6019 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6020 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6021 // swap src<->dst for encoding
6022 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6023 emit_int8(0x19);
6024 emit_operand(dst, src);
6025 }
6026
6027 // duplicate 1-byte integer data from src into 16||32|64 locations in dest : requires AVX512BW and AVX512VL
6028 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6029 assert(VM_Version::supports_evex(), "");
6030 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6031 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6032 emit_int8(0x7A);
6033 emit_int8((unsigned char)(0xC0 | encode));
6034 }
6035
6036 // duplicate 2-byte integer data from src into 8|16||32 locations in dest : requires AVX512BW and AVX512VL
6037 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6038 assert(VM_Version::supports_evex(), "");
6039 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6040 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6041 emit_int8(0x7B);
6042 emit_int8((unsigned char)(0xC0 | encode));
6043 }
6044
6045 // duplicate 4-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6046 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6047 assert(VM_Version::supports_evex(), "");
6048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6049 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6050 emit_int8(0x7C);
6051 emit_int8((unsigned char)(0xC0 | encode));
6052 }
6053
6054 // duplicate 8-byte integer data from src into 4|8|16 locations in dest : requires AVX512VL
6055 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6056 assert(VM_Version::supports_evex(), "");
6057 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6058 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6059 emit_int8(0x7C);
|