1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableModRefBS.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/interfaceSupport.hpp"
35 #include "runtime/objectMonitor.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/sharedRuntime.hpp"
38 #include "runtime/stubRoutines.hpp"
39 #include "utilities/macros.hpp"
40 #if INCLUDE_ALL_GCS
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
43 #include "gc/g1/heapRegion.hpp"
44 #endif // INCLUDE_ALL_GCS
45
46 #ifdef PRODUCT
47 #define BLOCK_COMMENT(str) /* nothing */
48 #define STOP(error) stop(error)
49 #else
50 #define BLOCK_COMMENT(str) block_comment(str)
51 #define STOP(error) block_comment(error); stop(error)
52 #endif
53
54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
55 // Implementation of AddressLiteral
56
57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
59 // -----------------Table 4.5 -------------------- //
60 16, 32, 64, // EVEX_FV(0)
61 4, 4, 4, // EVEX_FV(1) - with Evex.b
62 16, 32, 64, // EVEX_FV(2) - with Evex.w
63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
64 8, 16, 32, // EVEX_HV(0)
65 4, 4, 4, // EVEX_HV(1) - with Evex.b
66 // -----------------Table 4.6 -------------------- //
67 16, 32, 64, // EVEX_FVM(0)
68 1, 1, 1, // EVEX_T1S(0)
69 2, 2, 2, // EVEX_T1S(1)
70 4, 4, 4, // EVEX_T1S(2)
71 8, 8, 8, // EVEX_T1S(3)
72 4, 4, 4, // EVEX_T1F(0)
73 8, 8, 8, // EVEX_T1F(1)
74 8, 8, 8, // EVEX_T2(0)
75 0, 16, 16, // EVEX_T2(1)
76 0, 16, 16, // EVEX_T4(0)
77 0, 0, 32, // EVEX_T4(1)
78 0, 0, 32, // EVEX_T8(0)
79 8, 16, 32, // EVEX_HVM(0)
80 4, 8, 16, // EVEX_QVM(0)
81 2, 4, 8, // EVEX_OVM(0)
82 16, 16, 16, // EVEX_M128(0)
83 8, 32, 64, // EVEX_DUP(0)
84 0, 0, 0 // EVEX_NTUP
85 };
86
87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
88 _is_lval = false;
89 _target = target;
90 switch (rtype) {
91 case relocInfo::oop_type:
92 case relocInfo::metadata_type:
93 // Oops are a special case. Normally they would be their own section
94 // but in cases like icBuffer they are literals in the code stream that
95 // we don't have a section for. We use none so that we get a literal address
96 // which is always patchable.
97 break;
98 case relocInfo::external_word_type:
99 _rspec = external_word_Relocation::spec(target);
100 break;
101 case relocInfo::internal_word_type:
102 _rspec = internal_word_Relocation::spec(target);
103 break;
104 case relocInfo::opt_virtual_call_type:
105 _rspec = opt_virtual_call_Relocation::spec();
106 break;
107 case relocInfo::static_call_type:
108 _rspec = static_call_Relocation::spec();
109 break;
110 case relocInfo::runtime_call_type:
111 _rspec = runtime_call_Relocation::spec();
112 break;
113 case relocInfo::poll_type:
114 case relocInfo::poll_return_type:
115 _rspec = Relocation::spec_simple(rtype);
116 break;
117 case relocInfo::none:
118 break;
119 default:
120 ShouldNotReachHere();
121 break;
122 }
123 }
124
125 // Implementation of Address
126
127 #ifdef _LP64
128
129 Address Address::make_array(ArrayAddress adr) {
130 // Not implementable on 64bit machines
131 // Should have been handled higher up the call chain.
132 ShouldNotReachHere();
133 return Address();
134 }
135
136 // exceedingly dangerous constructor
137 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
138 _base = noreg;
139 _index = noreg;
140 _scale = no_scale;
141 _disp = disp;
142 switch (rtype) {
143 case relocInfo::external_word_type:
144 _rspec = external_word_Relocation::spec(loc);
145 break;
146 case relocInfo::internal_word_type:
147 _rspec = internal_word_Relocation::spec(loc);
148 break;
149 case relocInfo::runtime_call_type:
150 // HMM
151 _rspec = runtime_call_Relocation::spec();
152 break;
153 case relocInfo::poll_type:
154 case relocInfo::poll_return_type:
155 _rspec = Relocation::spec_simple(rtype);
156 break;
157 case relocInfo::none:
158 break;
159 default:
160 ShouldNotReachHere();
161 }
162 }
163 #else // LP64
164
165 Address Address::make_array(ArrayAddress adr) {
166 AddressLiteral base = adr.base();
167 Address index = adr.index();
168 assert(index._disp == 0, "must not have disp"); // maybe it can?
169 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
170 array._rspec = base._rspec;
171 return array;
172 }
173
174 // exceedingly dangerous constructor
175 Address::Address(address loc, RelocationHolder spec) {
176 _base = noreg;
177 _index = noreg;
178 _scale = no_scale;
179 _disp = (intptr_t) loc;
180 _rspec = spec;
181 }
182
183 #endif // _LP64
184
185
186
187 // Convert the raw encoding form into the form expected by the constructor for
188 // Address. An index of 4 (rsp) corresponds to having no index, so convert
189 // that to noreg for the Address constructor.
190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
191 RelocationHolder rspec;
192 if (disp_reloc != relocInfo::none) {
193 rspec = Relocation::spec_simple(disp_reloc);
194 }
195 bool valid_index = index != rsp->encoding();
196 if (valid_index) {
197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
198 madr._rspec = rspec;
199 return madr;
200 } else {
201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
202 madr._rspec = rspec;
203 return madr;
204 }
205 }
206
207 // Implementation of Assembler
208
209 int AbstractAssembler::code_fill_byte() {
210 return (u_char)'\xF4'; // hlt
211 }
212
213 // make this go away someday
214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
215 if (rtype == relocInfo::none)
216 emit_int32(data);
217 else
218 emit_data(data, Relocation::spec_simple(rtype), format);
219 }
220
221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
222 assert(imm_operand == 0, "default format must be immediate in this file");
223 assert(inst_mark() != NULL, "must be inside InstructionMark");
224 if (rspec.type() != relocInfo::none) {
225 #ifdef ASSERT
226 check_relocation(rspec, format);
227 #endif
228 // Do not use AbstractAssembler::relocate, which is not intended for
229 // embedded words. Instead, relocate to the enclosing instruction.
230
231 // hack. call32 is too wide for mask so use disp32
232 if (format == call32_operand)
233 code_section()->relocate(inst_mark(), rspec, disp32_operand);
234 else
235 code_section()->relocate(inst_mark(), rspec, format);
236 }
237 emit_int32(data);
238 }
239
240 static int encode(Register r) {
241 int enc = r->encoding();
242 if (enc >= 8) {
243 enc -= 8;
244 }
245 return enc;
246 }
247
248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
249 assert(dst->has_byte_register(), "must have byte register");
250 assert(isByte(op1) && isByte(op2), "wrong opcode");
251 assert(isByte(imm8), "not a byte");
252 assert((op1 & 0x01) == 0, "should be 8bit operation");
253 emit_int8(op1);
254 emit_int8(op2 | encode(dst));
255 emit_int8(imm8);
256 }
257
258
259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
260 assert(isByte(op1) && isByte(op2), "wrong opcode");
261 assert((op1 & 0x01) == 1, "should be 32bit operation");
262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
263 if (is8bit(imm32)) {
264 emit_int8(op1 | 0x02); // set sign bit
265 emit_int8(op2 | encode(dst));
266 emit_int8(imm32 & 0xFF);
267 } else {
268 emit_int8(op1);
269 emit_int8(op2 | encode(dst));
270 emit_int32(imm32);
271 }
272 }
273
274 // Force generation of a 4 byte immediate value even if it fits into 8bit
275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
276 assert(isByte(op1) && isByte(op2), "wrong opcode");
277 assert((op1 & 0x01) == 1, "should be 32bit operation");
278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
279 emit_int8(op1);
280 emit_int8(op2 | encode(dst));
281 emit_int32(imm32);
282 }
283
284 // immediate-to-memory forms
285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
286 assert((op1 & 0x01) == 1, "should be 32bit operation");
287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
288 if (is8bit(imm32)) {
289 emit_int8(op1 | 0x02); // set sign bit
290 emit_operand(rm, adr, 1);
291 emit_int8(imm32 & 0xFF);
292 } else {
293 emit_int8(op1);
294 emit_operand(rm, adr, 4);
295 emit_int32(imm32);
296 }
297 }
298
299
300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
301 assert(isByte(op1) && isByte(op2), "wrong opcode");
302 emit_int8(op1);
303 emit_int8(op2 | encode(dst) << 3 | encode(src));
304 }
305
306
307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
309 int mod_idx = 0;
310 // We will test if the displacement fits the compressed format and if so
311 // apply the compression to the displacment iff the result is8bit.
312 if (VM_Version::supports_evex() && is_evex_inst) {
313 switch (cur_tuple_type) {
314 case EVEX_FV:
315 if ((cur_encoding & VEX_W) == VEX_W) {
316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
317 } else {
318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
319 }
320 break;
321
322 case EVEX_HV:
323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
324 break;
325
326 case EVEX_FVM:
327 break;
328
329 case EVEX_T1S:
330 switch (in_size_in_bits) {
331 case EVEX_8bit:
332 break;
333
334 case EVEX_16bit:
335 mod_idx = 1;
336 break;
337
338 case EVEX_32bit:
339 mod_idx = 2;
340 break;
341
342 case EVEX_64bit:
343 mod_idx = 3;
344 break;
345 }
346 break;
347
348 case EVEX_T1F:
349 case EVEX_T2:
350 case EVEX_T4:
351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
352 break;
353
354 case EVEX_T8:
355 break;
356
357 case EVEX_HVM:
358 break;
359
360 case EVEX_QVM:
361 break;
362
363 case EVEX_OVM:
364 break;
365
366 case EVEX_M128:
367 break;
368
369 case EVEX_DUP:
370 break;
371
372 default:
373 assert(0, "no valid evex tuple_table entry");
374 break;
375 }
376
377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
379 if ((disp % disp_factor) == 0) {
380 int new_disp = disp / disp_factor;
381 if ((-0x80 <= new_disp && new_disp < 0x80)) {
382 disp = new_disp;
383 }
384 } else {
385 return false;
386 }
387 }
388 }
389 return (-0x80 <= disp && disp < 0x80);
390 }
391
392
393 bool Assembler::emit_compressed_disp_byte(int &disp) {
394 int mod_idx = 0;
395 // We will test if the displacement fits the compressed format and if so
396 // apply the compression to the displacment iff the result is8bit.
397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
398 int evex_encoding = _attributes->get_evex_encoding();
399 int tuple_type = _attributes->get_tuple_type();
400 switch (tuple_type) {
401 case EVEX_FV:
402 if ((evex_encoding & VEX_W) == VEX_W) {
403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
404 } else {
405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
406 }
407 break;
408
409 case EVEX_HV:
410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
411 break;
412
413 case EVEX_FVM:
414 break;
415
416 case EVEX_T1S:
417 switch (_attributes->get_input_size()) {
418 case EVEX_8bit:
419 break;
420
421 case EVEX_16bit:
422 mod_idx = 1;
423 break;
424
425 case EVEX_32bit:
426 mod_idx = 2;
427 break;
428
429 case EVEX_64bit:
430 mod_idx = 3;
431 break;
432 }
433 break;
434
435 case EVEX_T1F:
436 case EVEX_T2:
437 case EVEX_T4:
438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
439 break;
440
441 case EVEX_T8:
442 break;
443
444 case EVEX_HVM:
445 break;
446
447 case EVEX_QVM:
448 break;
449
450 case EVEX_OVM:
451 break;
452
453 case EVEX_M128:
454 break;
455
456 case EVEX_DUP:
457 break;
458
459 default:
460 assert(0, "no valid evex tuple_table entry");
461 break;
462 }
463
464 int vector_len = _attributes->get_vector_len();
465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
467 if ((disp % disp_factor) == 0) {
468 int new_disp = disp / disp_factor;
469 if (is8bit(new_disp)) {
470 disp = new_disp;
471 }
472 } else {
473 return false;
474 }
475 }
476 }
477 return is8bit(disp);
478 }
479
480
481 void Assembler::emit_operand(Register reg, Register base, Register index,
482 Address::ScaleFactor scale, int disp,
483 RelocationHolder const& rspec,
484 int rip_relative_correction) {
485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
486
487 // Encode the registers as needed in the fields they are used in
488
489 int regenc = encode(reg) << 3;
490 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
491 int baseenc = base->is_valid() ? encode(base) : 0;
492
493 if (base->is_valid()) {
494 if (index->is_valid()) {
495 assert(scale != Address::no_scale, "inconsistent address");
496 // [base + index*scale + disp]
497 if (disp == 0 && rtype == relocInfo::none &&
498 base != rbp LP64_ONLY(&& base != r13)) {
499 // [base + index*scale]
500 // [00 reg 100][ss index base]
501 assert(index != rsp, "illegal addressing mode");
502 emit_int8(0x04 | regenc);
503 emit_int8(scale << 6 | indexenc | baseenc);
504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
505 // [base + index*scale + imm8]
506 // [01 reg 100][ss index base] imm8
507 assert(index != rsp, "illegal addressing mode");
508 emit_int8(0x44 | regenc);
509 emit_int8(scale << 6 | indexenc | baseenc);
510 emit_int8(disp & 0xFF);
511 } else {
512 // [base + index*scale + disp32]
513 // [10 reg 100][ss index base] disp32
514 assert(index != rsp, "illegal addressing mode");
515 emit_int8(0x84 | regenc);
516 emit_int8(scale << 6 | indexenc | baseenc);
517 emit_data(disp, rspec, disp32_operand);
518 }
519 } else if (base == rsp LP64_ONLY(|| base == r12)) {
520 // [rsp + disp]
521 if (disp == 0 && rtype == relocInfo::none) {
522 // [rsp]
523 // [00 reg 100][00 100 100]
524 emit_int8(0x04 | regenc);
525 emit_int8(0x24);
526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
527 // [rsp + imm8]
528 // [01 reg 100][00 100 100] disp8
529 emit_int8(0x44 | regenc);
530 emit_int8(0x24);
531 emit_int8(disp & 0xFF);
532 } else {
533 // [rsp + imm32]
534 // [10 reg 100][00 100 100] disp32
535 emit_int8(0x84 | regenc);
536 emit_int8(0x24);
537 emit_data(disp, rspec, disp32_operand);
538 }
539 } else {
540 // [base + disp]
541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
542 if (disp == 0 && rtype == relocInfo::none &&
543 base != rbp LP64_ONLY(&& base != r13)) {
544 // [base]
545 // [00 reg base]
546 emit_int8(0x00 | regenc | baseenc);
547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
548 // [base + disp8]
549 // [01 reg base] disp8
550 emit_int8(0x40 | regenc | baseenc);
551 emit_int8(disp & 0xFF);
552 } else {
553 // [base + disp32]
554 // [10 reg base] disp32
555 emit_int8(0x80 | regenc | baseenc);
556 emit_data(disp, rspec, disp32_operand);
557 }
558 }
559 } else {
560 if (index->is_valid()) {
561 assert(scale != Address::no_scale, "inconsistent address");
562 // [index*scale + disp]
563 // [00 reg 100][ss index 101] disp32
564 assert(index != rsp, "illegal addressing mode");
565 emit_int8(0x04 | regenc);
566 emit_int8(scale << 6 | indexenc | 0x05);
567 emit_data(disp, rspec, disp32_operand);
568 } else if (rtype != relocInfo::none ) {
569 // [disp] (64bit) RIP-RELATIVE (32bit) abs
570 // [00 000 101] disp32
571
572 emit_int8(0x05 | regenc);
573 // Note that the RIP-rel. correction applies to the generated
574 // disp field, but _not_ to the target address in the rspec.
575
576 // disp was created by converting the target address minus the pc
577 // at the start of the instruction. That needs more correction here.
578 // intptr_t disp = target - next_ip;
579 assert(inst_mark() != NULL, "must be inside InstructionMark");
580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
581 int64_t adjusted = disp;
582 // Do rip-rel adjustment for 64bit
583 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
584 assert(is_simm32(adjusted),
585 "must be 32bit offset (RIP relative address)");
586 emit_data((int32_t) adjusted, rspec, disp32_operand);
587
588 } else {
589 // 32bit never did this, did everything as the rip-rel/disp code above
590 // [disp] ABSOLUTE
591 // [00 reg 100][00 100 101] disp32
592 emit_int8(0x04 | regenc);
593 emit_int8(0x25);
594 emit_data(disp, rspec, disp32_operand);
595 }
596 }
597 }
598
599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
600 Address::ScaleFactor scale, int disp,
601 RelocationHolder const& rspec) {
602 if (UseAVX > 2) {
603 int xreg_enc = reg->encoding();
604 if (xreg_enc > 15) {
605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
606 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
607 return;
608 }
609 }
610 emit_operand((Register)reg, base, index, scale, disp, rspec);
611 }
612
613 // Secret local extension to Assembler::WhichOperand:
614 #define end_pc_operand (_WhichOperand_limit)
615
616 address Assembler::locate_operand(address inst, WhichOperand which) {
617 // Decode the given instruction, and return the address of
618 // an embedded 32-bit operand word.
619
620 // If "which" is disp32_operand, selects the displacement portion
621 // of an effective address specifier.
622 // If "which" is imm64_operand, selects the trailing immediate constant.
623 // If "which" is call32_operand, selects the displacement of a call or jump.
624 // Caller is responsible for ensuring that there is such an operand,
625 // and that it is 32/64 bits wide.
626
627 // If "which" is end_pc_operand, find the end of the instruction.
628
629 address ip = inst;
630 bool is_64bit = false;
631
632 debug_only(bool has_disp32 = false);
633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
634
635 again_after_prefix:
636 switch (0xFF & *ip++) {
637
638 // These convenience macros generate groups of "case" labels for the switch.
639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
641 case (x)+4: case (x)+5: case (x)+6: case (x)+7
642 #define REP16(x) REP8((x)+0): \
643 case REP8((x)+8)
644
645 case CS_segment:
646 case SS_segment:
647 case DS_segment:
648 case ES_segment:
649 case FS_segment:
650 case GS_segment:
651 // Seems dubious
652 LP64_ONLY(assert(false, "shouldn't have that prefix"));
653 assert(ip == inst+1, "only one prefix allowed");
654 goto again_after_prefix;
655
656 case 0x67:
657 case REX:
658 case REX_B:
659 case REX_X:
660 case REX_XB:
661 case REX_R:
662 case REX_RB:
663 case REX_RX:
664 case REX_RXB:
665 NOT_LP64(assert(false, "64bit prefixes"));
666 goto again_after_prefix;
667
668 case REX_W:
669 case REX_WB:
670 case REX_WX:
671 case REX_WXB:
672 case REX_WR:
673 case REX_WRB:
674 case REX_WRX:
675 case REX_WRXB:
676 NOT_LP64(assert(false, "64bit prefixes"));
677 is_64bit = true;
678 goto again_after_prefix;
679
680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
681 case 0x88: // movb a, r
682 case 0x89: // movl a, r
683 case 0x8A: // movb r, a
684 case 0x8B: // movl r, a
685 case 0x8F: // popl a
686 debug_only(has_disp32 = true);
687 break;
688
689 case 0x68: // pushq #32
690 if (which == end_pc_operand) {
691 return ip + 4;
692 }
693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
694 return ip; // not produced by emit_operand
695
696 case 0x66: // movw ... (size prefix)
697 again_after_size_prefix2:
698 switch (0xFF & *ip++) {
699 case REX:
700 case REX_B:
701 case REX_X:
702 case REX_XB:
703 case REX_R:
704 case REX_RB:
705 case REX_RX:
706 case REX_RXB:
707 case REX_W:
708 case REX_WB:
709 case REX_WX:
710 case REX_WXB:
711 case REX_WR:
712 case REX_WRB:
713 case REX_WRX:
714 case REX_WRXB:
715 NOT_LP64(assert(false, "64bit prefix found"));
716 goto again_after_size_prefix2;
717 case 0x8B: // movw r, a
718 case 0x89: // movw a, r
719 debug_only(has_disp32 = true);
720 break;
721 case 0xC7: // movw a, #16
722 debug_only(has_disp32 = true);
723 tail_size = 2; // the imm16
724 break;
725 case 0x0F: // several SSE/SSE2 variants
726 ip--; // reparse the 0x0F
727 goto again_after_prefix;
728 default:
729 ShouldNotReachHere();
730 }
731 break;
732
733 case REP8(0xB8): // movl/q r, #32/#64(oop?)
734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
735 // these asserts are somewhat nonsensical
736 #ifndef _LP64
737 assert(which == imm_operand || which == disp32_operand,
738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
739 #else
740 assert((which == call32_operand || which == imm_operand) && is_64bit ||
741 which == narrow_oop_operand && !is_64bit,
742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
743 #endif // _LP64
744 return ip;
745
746 case 0x69: // imul r, a, #32
747 case 0xC7: // movl a, #32(oop?)
748 tail_size = 4;
749 debug_only(has_disp32 = true); // has both kinds of operands!
750 break;
751
752 case 0x0F: // movx..., etc.
753 switch (0xFF & *ip++) {
754 case 0x3A: // pcmpestri
755 tail_size = 1;
756 case 0x38: // ptest, pmovzxbw
757 ip++; // skip opcode
758 debug_only(has_disp32 = true); // has both kinds of operands!
759 break;
760
761 case 0x70: // pshufd r, r/a, #8
762 debug_only(has_disp32 = true); // has both kinds of operands!
763 case 0x73: // psrldq r, #8
764 tail_size = 1;
765 break;
766
767 case 0x12: // movlps
768 case 0x28: // movaps
769 case 0x2E: // ucomiss
770 case 0x2F: // comiss
771 case 0x54: // andps
772 case 0x55: // andnps
773 case 0x56: // orps
774 case 0x57: // xorps
775 case 0x58: // addpd
776 case 0x59: // mulpd
777 case 0x6E: // movd
778 case 0x7E: // movd
779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
780 case 0xFE: // paddd
781 debug_only(has_disp32 = true);
782 break;
783
784 case 0xAD: // shrd r, a, %cl
785 case 0xAF: // imul r, a
786 case 0xBE: // movsbl r, a (movsxb)
787 case 0xBF: // movswl r, a (movsxw)
788 case 0xB6: // movzbl r, a (movzxb)
789 case 0xB7: // movzwl r, a (movzxw)
790 case REP16(0x40): // cmovl cc, r, a
791 case 0xB0: // cmpxchgb
792 case 0xB1: // cmpxchg
793 case 0xC1: // xaddl
794 case 0xC7: // cmpxchg8
795 case REP16(0x90): // setcc a
796 debug_only(has_disp32 = true);
797 // fall out of the switch to decode the address
798 break;
799
800 case 0xC4: // pinsrw r, a, #8
801 debug_only(has_disp32 = true);
802 case 0xC5: // pextrw r, r, #8
803 tail_size = 1; // the imm8
804 break;
805
806 case 0xAC: // shrd r, a, #8
807 debug_only(has_disp32 = true);
808 tail_size = 1; // the imm8
809 break;
810
811 case REP16(0x80): // jcc rdisp32
812 if (which == end_pc_operand) return ip + 4;
813 assert(which == call32_operand, "jcc has no disp32 or imm");
814 return ip;
815 default:
816 ShouldNotReachHere();
817 }
818 break;
819
820 case 0x81: // addl a, #32; addl r, #32
821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
822 // on 32bit in the case of cmpl, the imm might be an oop
823 tail_size = 4;
824 debug_only(has_disp32 = true); // has both kinds of operands!
825 break;
826
827 case 0x83: // addl a, #8; addl r, #8
828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
829 debug_only(has_disp32 = true); // has both kinds of operands!
830 tail_size = 1;
831 break;
832
833 case 0x9B:
834 switch (0xFF & *ip++) {
835 case 0xD9: // fnstcw a
836 debug_only(has_disp32 = true);
837 break;
838 default:
839 ShouldNotReachHere();
840 }
841 break;
842
843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
844 case REP4(0x10): // adc...
845 case REP4(0x20): // and...
846 case REP4(0x30): // xor...
847 case REP4(0x08): // or...
848 case REP4(0x18): // sbb...
849 case REP4(0x28): // sub...
850 case 0xF7: // mull a
851 case 0x8D: // lea r, a
852 case 0x87: // xchg r, a
853 case REP4(0x38): // cmp...
854 case 0x85: // test r, a
855 debug_only(has_disp32 = true); // has both kinds of operands!
856 break;
857
858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
859 case 0xC6: // movb a, #8
860 case 0x80: // cmpb a, #8
861 case 0x6B: // imul r, a, #8
862 debug_only(has_disp32 = true); // has both kinds of operands!
863 tail_size = 1; // the imm8
864 break;
865
866 case 0xC4: // VEX_3bytes
867 case 0xC5: // VEX_2bytes
868 assert((UseAVX > 0), "shouldn't have VEX prefix");
869 assert(ip == inst+1, "no prefixes allowed");
870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
871 // but they have prefix 0x0F and processed when 0x0F processed above.
872 //
873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
874 // instructions (these instructions are not supported in 64-bit mode).
875 // To distinguish them bits [7:6] are set in the VEX second byte since
876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
877 // those VEX bits REX and vvvv bits are inverted.
878 //
879 // Fortunately C2 doesn't generate these instructions so we don't need
880 // to check for them in product version.
881
882 // Check second byte
883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
884
885 int vex_opcode;
886 // First byte
887 if ((0xFF & *inst) == VEX_3bytes) {
888 vex_opcode = VEX_OPCODE_MASK & *ip;
889 ip++; // third byte
890 is_64bit = ((VEX_W & *ip) == VEX_W);
891 } else {
892 vex_opcode = VEX_OPCODE_0F;
893 }
894 ip++; // opcode
895 // To find the end of instruction (which == end_pc_operand).
896 switch (vex_opcode) {
897 case VEX_OPCODE_0F:
898 switch (0xFF & *ip) {
899 case 0x70: // pshufd r, r/a, #8
900 case 0x71: // ps[rl|ra|ll]w r, #8
901 case 0x72: // ps[rl|ra|ll]d r, #8
902 case 0x73: // ps[rl|ra|ll]q r, #8
903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
904 case 0xC4: // pinsrw r, r, r/a, #8
905 case 0xC5: // pextrw r/a, r, #8
906 case 0xC6: // shufp[s|d] r, r, r/a, #8
907 tail_size = 1; // the imm8
908 break;
909 }
910 break;
911 case VEX_OPCODE_0F_3A:
912 tail_size = 1;
913 break;
914 }
915 ip++; // skip opcode
916 debug_only(has_disp32 = true); // has both kinds of operands!
917 break;
918
919 case 0x62: // EVEX_4bytes
920 assert((UseAVX > 0), "shouldn't have EVEX prefix");
921 assert(ip == inst+1, "no prefixes allowed");
922 // no EVEX collisions, all instructions that have 0x62 opcodes
923 // have EVEX versions and are subopcodes of 0x66
924 ip++; // skip P0 and exmaine W in P1
925 is_64bit = ((VEX_W & *ip) == VEX_W);
926 ip++; // move to P2
927 ip++; // skip P2, move to opcode
928 // To find the end of instruction (which == end_pc_operand).
929 switch (0xFF & *ip) {
930 case 0x22: // pinsrd r, r/a, #8
931 case 0x61: // pcmpestri r, r/a, #8
932 case 0x70: // pshufd r, r/a, #8
933 case 0x73: // psrldq r, #8
934 tail_size = 1; // the imm8
935 break;
936 default:
937 break;
938 }
939 ip++; // skip opcode
940 debug_only(has_disp32 = true); // has both kinds of operands!
941 break;
942
943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
946 case 0xDD: // fld_d a; fst_d a; fstp_d a
947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
948 case 0xDF: // fild_d a; fistp_d a
949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
952 debug_only(has_disp32 = true);
953 break;
954
955 case 0xE8: // call rdisp32
956 case 0xE9: // jmp rdisp32
957 if (which == end_pc_operand) return ip + 4;
958 assert(which == call32_operand, "call has no disp32 or imm");
959 return ip;
960
961 case 0xF0: // Lock
962 assert(os::is_MP(), "only on MP");
963 goto again_after_prefix;
964
965 case 0xF3: // For SSE
966 case 0xF2: // For SSE2
967 switch (0xFF & *ip++) {
968 case REX:
969 case REX_B:
970 case REX_X:
971 case REX_XB:
972 case REX_R:
973 case REX_RB:
974 case REX_RX:
975 case REX_RXB:
976 case REX_W:
977 case REX_WB:
978 case REX_WX:
979 case REX_WXB:
980 case REX_WR:
981 case REX_WRB:
982 case REX_WRX:
983 case REX_WRXB:
984 NOT_LP64(assert(false, "found 64bit prefix"));
985 ip++;
986 default:
987 ip++;
988 }
989 debug_only(has_disp32 = true); // has both kinds of operands!
990 break;
991
992 default:
993 ShouldNotReachHere();
994
995 #undef REP8
996 #undef REP16
997 }
998
999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1000 #ifdef _LP64
1001 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1002 #else
1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1005 #endif // LP64
1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1007
1008 // parse the output of emit_operand
1009 int op2 = 0xFF & *ip++;
1010 int base = op2 & 0x07;
1011 int op3 = -1;
1012 const int b100 = 4;
1013 const int b101 = 5;
1014 if (base == b100 && (op2 >> 6) != 3) {
1015 op3 = 0xFF & *ip++;
1016 base = op3 & 0x07; // refetch the base
1017 }
1018 // now ip points at the disp (if any)
1019
1020 switch (op2 >> 6) {
1021 case 0:
1022 // [00 reg 100][ss index base]
1023 // [00 reg 100][00 100 esp]
1024 // [00 reg base]
1025 // [00 reg 100][ss index 101][disp32]
1026 // [00 reg 101] [disp32]
1027
1028 if (base == b101) {
1029 if (which == disp32_operand)
1030 return ip; // caller wants the disp32
1031 ip += 4; // skip the disp32
1032 }
1033 break;
1034
1035 case 1:
1036 // [01 reg 100][ss index base][disp8]
1037 // [01 reg 100][00 100 esp][disp8]
1038 // [01 reg base] [disp8]
1039 ip += 1; // skip the disp8
1040 break;
1041
1042 case 2:
1043 // [10 reg 100][ss index base][disp32]
1044 // [10 reg 100][00 100 esp][disp32]
1045 // [10 reg base] [disp32]
1046 if (which == disp32_operand)
1047 return ip; // caller wants the disp32
1048 ip += 4; // skip the disp32
1049 break;
1050
1051 case 3:
1052 // [11 reg base] (not a memory addressing mode)
1053 break;
1054 }
1055
1056 if (which == end_pc_operand) {
1057 return ip + tail_size;
1058 }
1059
1060 #ifdef _LP64
1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1062 #else
1063 assert(which == imm_operand, "instruction has only an imm field");
1064 #endif // LP64
1065 return ip;
1066 }
1067
1068 address Assembler::locate_next_instruction(address inst) {
1069 // Secretly share code with locate_operand:
1070 return locate_operand(inst, end_pc_operand);
1071 }
1072
1073
1074 #ifdef ASSERT
1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1076 address inst = inst_mark();
1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1078 address opnd;
1079
1080 Relocation* r = rspec.reloc();
1081 if (r->type() == relocInfo::none) {
1082 return;
1083 } else if (r->is_call() || format == call32_operand) {
1084 // assert(format == imm32_operand, "cannot specify a nonzero format");
1085 opnd = locate_operand(inst, call32_operand);
1086 } else if (r->is_data()) {
1087 assert(format == imm_operand || format == disp32_operand
1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1089 opnd = locate_operand(inst, (WhichOperand)format);
1090 } else {
1091 assert(format == imm_operand, "cannot specify a format");
1092 return;
1093 }
1094 assert(opnd == pc(), "must put operand where relocs can find it");
1095 }
1096 #endif // ASSERT
1097
1098 void Assembler::emit_operand32(Register reg, Address adr) {
1099 assert(reg->encoding() < 8, "no extended registers");
1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1102 adr._rspec);
1103 }
1104
1105 void Assembler::emit_operand(Register reg, Address adr,
1106 int rip_relative_correction) {
1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1108 adr._rspec,
1109 rip_relative_correction);
1110 }
1111
1112 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1114 adr._rspec);
1115 }
1116
1117 // MMX operations
1118 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1121 }
1122
1123 // work around gcc (3.2.1-7a) bug
1124 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1127 }
1128
1129
1130 void Assembler::emit_farith(int b1, int b2, int i) {
1131 assert(isByte(b1) && isByte(b2), "wrong opcode");
1132 assert(0 <= i && i < 8, "illegal stack offset");
1133 emit_int8(b1);
1134 emit_int8(b2 + i);
1135 }
1136
1137
1138 // Now the Assembler instructions (identical for 32/64 bits)
1139
1140 void Assembler::adcl(Address dst, int32_t imm32) {
1141 InstructionMark im(this);
1142 prefix(dst);
1143 emit_arith_operand(0x81, rdx, dst, imm32);
1144 }
1145
1146 void Assembler::adcl(Address dst, Register src) {
1147 InstructionMark im(this);
1148 prefix(dst, src);
1149 emit_int8(0x11);
1150 emit_operand(src, dst);
1151 }
1152
1153 void Assembler::adcl(Register dst, int32_t imm32) {
1154 prefix(dst);
1155 emit_arith(0x81, 0xD0, dst, imm32);
1156 }
1157
1158 void Assembler::adcl(Register dst, Address src) {
1159 InstructionMark im(this);
1160 prefix(src, dst);
1161 emit_int8(0x13);
1162 emit_operand(dst, src);
1163 }
1164
1165 void Assembler::adcl(Register dst, Register src) {
1166 (void) prefix_and_encode(dst->encoding(), src->encoding());
1167 emit_arith(0x13, 0xC0, dst, src);
1168 }
1169
1170 void Assembler::addl(Address dst, int32_t imm32) {
1171 InstructionMark im(this);
1172 prefix(dst);
1173 emit_arith_operand(0x81, rax, dst, imm32);
1174 }
1175
1176 void Assembler::addl(Address dst, Register src) {
1177 InstructionMark im(this);
1178 prefix(dst, src);
1179 emit_int8(0x01);
1180 emit_operand(src, dst);
1181 }
1182
1183 void Assembler::addl(Register dst, int32_t imm32) {
1184 prefix(dst);
1185 emit_arith(0x81, 0xC0, dst, imm32);
1186 }
1187
1188 void Assembler::addl(Register dst, Address src) {
1189 InstructionMark im(this);
1190 prefix(src, dst);
1191 emit_int8(0x03);
1192 emit_operand(dst, src);
1193 }
1194
1195 void Assembler::addl(Register dst, Register src) {
1196 (void) prefix_and_encode(dst->encoding(), src->encoding());
1197 emit_arith(0x03, 0xC0, dst, src);
1198 }
1199
1200 void Assembler::addr_nop_4() {
1201 assert(UseAddressNop, "no CPU support");
1202 // 4 bytes: NOP DWORD PTR [EAX+0]
1203 emit_int8(0x0F);
1204 emit_int8(0x1F);
1205 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1206 emit_int8(0); // 8-bits offset (1 byte)
1207 }
1208
1209 void Assembler::addr_nop_5() {
1210 assert(UseAddressNop, "no CPU support");
1211 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1212 emit_int8(0x0F);
1213 emit_int8(0x1F);
1214 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1215 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1216 emit_int8(0); // 8-bits offset (1 byte)
1217 }
1218
1219 void Assembler::addr_nop_7() {
1220 assert(UseAddressNop, "no CPU support");
1221 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1222 emit_int8(0x0F);
1223 emit_int8(0x1F);
1224 emit_int8((unsigned char)0x80);
1225 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1226 emit_int32(0); // 32-bits offset (4 bytes)
1227 }
1228
1229 void Assembler::addr_nop_8() {
1230 assert(UseAddressNop, "no CPU support");
1231 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1232 emit_int8(0x0F);
1233 emit_int8(0x1F);
1234 emit_int8((unsigned char)0x84);
1235 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1236 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1237 emit_int32(0); // 32-bits offset (4 bytes)
1238 }
1239
1240 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1241 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1242 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1243 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1244 emit_int8(0x58);
1245 emit_int8((unsigned char)(0xC0 | encode));
1246 }
1247
1248 void Assembler::addsd(XMMRegister dst, Address src) {
1249 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1250 InstructionMark im(this);
1251 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1252 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1253 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1254 emit_int8(0x58);
1255 emit_operand(dst, src);
1256 }
1257
1258 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1259 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1260 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1262 emit_int8(0x58);
1263 emit_int8((unsigned char)(0xC0 | encode));
1264 }
1265
1266 void Assembler::addss(XMMRegister dst, Address src) {
1267 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1268 InstructionMark im(this);
1269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1270 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1271 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1272 emit_int8(0x58);
1273 emit_operand(dst, src);
1274 }
1275
1276 void Assembler::aesdec(XMMRegister dst, Address src) {
1277 assert(VM_Version::supports_aes(), "");
1278 InstructionMark im(this);
1279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1280 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1281 emit_int8((unsigned char)0xDE);
1282 emit_operand(dst, src);
1283 }
1284
1285 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1286 assert(VM_Version::supports_aes(), "");
1287 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1288 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1289 emit_int8((unsigned char)0xDE);
1290 emit_int8(0xC0 | encode);
1291 }
1292
1293 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1294 assert(VM_Version::supports_aes(), "");
1295 InstructionMark im(this);
1296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1297 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1298 emit_int8((unsigned char)0xDF);
1299 emit_operand(dst, src);
1300 }
1301
1302 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1303 assert(VM_Version::supports_aes(), "");
1304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1305 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1306 emit_int8((unsigned char)0xDF);
1307 emit_int8((unsigned char)(0xC0 | encode));
1308 }
1309
1310 void Assembler::aesenc(XMMRegister dst, Address src) {
1311 assert(VM_Version::supports_aes(), "");
1312 InstructionMark im(this);
1313 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1314 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1315 emit_int8((unsigned char)0xDC);
1316 emit_operand(dst, src);
1317 }
1318
1319 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1320 assert(VM_Version::supports_aes(), "");
1321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1323 emit_int8((unsigned char)0xDC);
1324 emit_int8(0xC0 | encode);
1325 }
1326
1327 void Assembler::aesenclast(XMMRegister dst, Address src) {
1328 assert(VM_Version::supports_aes(), "");
1329 InstructionMark im(this);
1330 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1331 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1332 emit_int8((unsigned char)0xDD);
1333 emit_operand(dst, src);
1334 }
1335
1336 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1337 assert(VM_Version::supports_aes(), "");
1338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1339 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1340 emit_int8((unsigned char)0xDD);
1341 emit_int8((unsigned char)(0xC0 | encode));
1342 }
1343
1344 void Assembler::andl(Address dst, int32_t imm32) {
1345 InstructionMark im(this);
1346 prefix(dst);
1347 emit_int8((unsigned char)0x81);
1348 emit_operand(rsp, dst, 4);
1349 emit_int32(imm32);
1350 }
1351
1352 void Assembler::andl(Register dst, int32_t imm32) {
1353 prefix(dst);
1354 emit_arith(0x81, 0xE0, dst, imm32);
1355 }
1356
1357 void Assembler::andl(Register dst, Address src) {
1358 InstructionMark im(this);
1359 prefix(src, dst);
1360 emit_int8(0x23);
1361 emit_operand(dst, src);
1362 }
1363
1364 void Assembler::andl(Register dst, Register src) {
1365 (void) prefix_and_encode(dst->encoding(), src->encoding());
1366 emit_arith(0x23, 0xC0, dst, src);
1367 }
1368
1369 void Assembler::andnl(Register dst, Register src1, Register src2) {
1370 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1371 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1372 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1373 emit_int8((unsigned char)0xF2);
1374 emit_int8((unsigned char)(0xC0 | encode));
1375 }
1376
1377 void Assembler::andnl(Register dst, Register src1, Address src2) {
1378 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1379 InstructionMark im(this);
1380 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1381 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1382 emit_int8((unsigned char)0xF2);
1383 emit_operand(dst, src2);
1384 }
1385
1386 void Assembler::bsfl(Register dst, Register src) {
1387 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1388 emit_int8(0x0F);
1389 emit_int8((unsigned char)0xBC);
1390 emit_int8((unsigned char)(0xC0 | encode));
1391 }
1392
1393 void Assembler::bsrl(Register dst, Register src) {
1394 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1395 emit_int8(0x0F);
1396 emit_int8((unsigned char)0xBD);
1397 emit_int8((unsigned char)(0xC0 | encode));
1398 }
1399
1400 void Assembler::bswapl(Register reg) { // bswap
1401 int encode = prefix_and_encode(reg->encoding());
1402 emit_int8(0x0F);
1403 emit_int8((unsigned char)(0xC8 | encode));
1404 }
1405
1406 void Assembler::blsil(Register dst, Register src) {
1407 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1408 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1409 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1410 emit_int8((unsigned char)0xF3);
1411 emit_int8((unsigned char)(0xC0 | encode));
1412 }
1413
1414 void Assembler::blsil(Register dst, Address src) {
1415 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1416 InstructionMark im(this);
1417 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1418 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1419 emit_int8((unsigned char)0xF3);
1420 emit_operand(rbx, src);
1421 }
1422
1423 void Assembler::blsmskl(Register dst, Register src) {
1424 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1425 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1426 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1427 emit_int8((unsigned char)0xF3);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::blsmskl(Register dst, Address src) {
1432 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1433 InstructionMark im(this);
1434 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1435 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1436 emit_int8((unsigned char)0xF3);
1437 emit_operand(rdx, src);
1438 }
1439
1440 void Assembler::blsrl(Register dst, Register src) {
1441 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1442 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1443 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1444 emit_int8((unsigned char)0xF3);
1445 emit_int8((unsigned char)(0xC0 | encode));
1446 }
1447
1448 void Assembler::blsrl(Register dst, Address src) {
1449 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1450 InstructionMark im(this);
1451 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
1452 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1453 emit_int8((unsigned char)0xF3);
1454 emit_operand(rcx, src);
1455 }
1456
1457 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1458 // suspect disp32 is always good
1459 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1460
1461 if (L.is_bound()) {
1462 const int long_size = 5;
1463 int offs = (int)( target(L) - pc() );
1464 assert(offs <= 0, "assembler error");
1465 InstructionMark im(this);
1466 // 1110 1000 #32-bit disp
1467 emit_int8((unsigned char)0xE8);
1468 emit_data(offs - long_size, rtype, operand);
1469 } else {
1470 InstructionMark im(this);
1471 // 1110 1000 #32-bit disp
1472 L.add_patch_at(code(), locator());
1473
1474 emit_int8((unsigned char)0xE8);
1475 emit_data(int(0), rtype, operand);
1476 }
1477 }
1478
1479 void Assembler::call(Register dst) {
1480 int encode = prefix_and_encode(dst->encoding());
1481 emit_int8((unsigned char)0xFF);
1482 emit_int8((unsigned char)(0xD0 | encode));
1483 }
1484
1485
1486 void Assembler::call(Address adr) {
1487 InstructionMark im(this);
1488 prefix(adr);
1489 emit_int8((unsigned char)0xFF);
1490 emit_operand(rdx, adr);
1491 }
1492
1493 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1494 assert(entry != NULL, "call most probably wrong");
1495 InstructionMark im(this);
1496 emit_int8((unsigned char)0xE8);
1497 intptr_t disp = entry - (pc() + sizeof(int32_t));
1498 assert(is_simm32(disp), "must be 32bit offset (call2)");
1499 // Technically, should use call32_operand, but this format is
1500 // implied by the fact that we're emitting a call instruction.
1501
1502 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1503 emit_data((int) disp, rspec, operand);
1504 }
1505
1506 void Assembler::cdql() {
1507 emit_int8((unsigned char)0x99);
1508 }
1509
1510 void Assembler::cld() {
1511 emit_int8((unsigned char)0xFC);
1512 }
1513
1514 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1515 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1516 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1517 emit_int8(0x0F);
1518 emit_int8(0x40 | cc);
1519 emit_int8((unsigned char)(0xC0 | encode));
1520 }
1521
1522
1523 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1524 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1525 prefix(src, dst);
1526 emit_int8(0x0F);
1527 emit_int8(0x40 | cc);
1528 emit_operand(dst, src);
1529 }
1530
1531 void Assembler::cmpb(Address dst, int imm8) {
1532 InstructionMark im(this);
1533 prefix(dst);
1534 emit_int8((unsigned char)0x80);
1535 emit_operand(rdi, dst, 1);
1536 emit_int8(imm8);
1537 }
1538
1539 void Assembler::cmpl(Address dst, int32_t imm32) {
1540 InstructionMark im(this);
1541 prefix(dst);
1542 emit_int8((unsigned char)0x81);
1543 emit_operand(rdi, dst, 4);
1544 emit_int32(imm32);
1545 }
1546
1547 void Assembler::cmpl(Register dst, int32_t imm32) {
1548 prefix(dst);
1549 emit_arith(0x81, 0xF8, dst, imm32);
1550 }
1551
1552 void Assembler::cmpl(Register dst, Register src) {
1553 (void) prefix_and_encode(dst->encoding(), src->encoding());
1554 emit_arith(0x3B, 0xC0, dst, src);
1555 }
1556
1557 void Assembler::cmpl(Register dst, Address src) {
1558 InstructionMark im(this);
1559 prefix(src, dst);
1560 emit_int8((unsigned char)0x3B);
1561 emit_operand(dst, src);
1562 }
1563
1564 void Assembler::cmpw(Address dst, int imm16) {
1565 InstructionMark im(this);
1566 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1567 emit_int8(0x66);
1568 emit_int8((unsigned char)0x81);
1569 emit_operand(rdi, dst, 2);
1570 emit_int16(imm16);
1571 }
1572
1573 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1574 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1575 // The ZF is set if the compared values were equal, and cleared otherwise.
1576 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1577 InstructionMark im(this);
1578 prefix(adr, reg);
1579 emit_int8(0x0F);
1580 emit_int8((unsigned char)0xB1);
1581 emit_operand(reg, adr);
1582 }
1583
1584 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1585 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1586 // The ZF is set if the compared values were equal, and cleared otherwise.
1587 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1588 InstructionMark im(this);
1589 prefix(adr, reg, true);
1590 emit_int8(0x0F);
1591 emit_int8((unsigned char)0xB0);
1592 emit_operand(reg, adr);
1593 }
1594
1595 void Assembler::comisd(XMMRegister dst, Address src) {
1596 // NOTE: dbx seems to decode this as comiss even though the
1597 // 0x66 is there. Strangly ucomisd comes out correct
1598 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1599 InstructionMark im(this);
1600 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1601 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1602 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1603 emit_int8(0x2F);
1604 emit_operand(dst, src);
1605 }
1606
1607 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1608 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1609 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1610 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1611 emit_int8(0x2F);
1612 emit_int8((unsigned char)(0xC0 | encode));
1613 }
1614
1615 void Assembler::comiss(XMMRegister dst, Address src) {
1616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1617 InstructionMark im(this);
1618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1619 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1620 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1621 emit_int8(0x2F);
1622 emit_operand(dst, src);
1623 }
1624
1625 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1626 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1628 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1629 emit_int8(0x2F);
1630 emit_int8((unsigned char)(0xC0 | encode));
1631 }
1632
1633 void Assembler::cpuid() {
1634 emit_int8(0x0F);
1635 emit_int8((unsigned char)0xA2);
1636 }
1637
1638 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1639 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1640 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1641 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1642 //
1643 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1644 //
1645 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1646 //
1647 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1648 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1649 assert(VM_Version::supports_sse4_2(), "");
1650 int8_t w = 0x01;
1651 Prefix p = Prefix_EMPTY;
1652
1653 emit_int8((int8_t)0xF2);
1654 switch (sizeInBytes) {
1655 case 1:
1656 w = 0;
1657 break;
1658 case 2:
1659 case 4:
1660 break;
1661 LP64_ONLY(case 8:)
1662 // This instruction is not valid in 32 bits
1663 // Note:
1664 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1665 //
1666 // Page B - 72 Vol. 2C says
1667 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1668 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1669 // F0!!!
1670 // while 3 - 208 Vol. 2A
1671 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1672 //
1673 // the 0 on a last bit is reserved for a different flavor of this instruction :
1674 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1675 p = REX_W;
1676 break;
1677 default:
1678 assert(0, "Unsupported value for a sizeInBytes argument");
1679 break;
1680 }
1681 LP64_ONLY(prefix(crc, v, p);)
1682 emit_int8((int8_t)0x0F);
1683 emit_int8(0x38);
1684 emit_int8((int8_t)(0xF0 | w));
1685 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1686 }
1687
1688 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1689 assert(VM_Version::supports_sse4_2(), "");
1690 InstructionMark im(this);
1691 int8_t w = 0x01;
1692 Prefix p = Prefix_EMPTY;
1693
1694 emit_int8((int8_t)0xF2);
1695 switch (sizeInBytes) {
1696 case 1:
1697 w = 0;
1698 break;
1699 case 2:
1700 case 4:
1701 break;
1702 LP64_ONLY(case 8:)
1703 // This instruction is not valid in 32 bits
1704 p = REX_W;
1705 break;
1706 default:
1707 assert(0, "Unsupported value for a sizeInBytes argument");
1708 break;
1709 }
1710 LP64_ONLY(prefix(crc, adr, p);)
1711 emit_int8((int8_t)0x0F);
1712 emit_int8(0x38);
1713 emit_int8((int8_t)(0xF0 | w));
1714 emit_operand(crc, adr);
1715 }
1716
1717 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1718 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1719 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1720 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1721 emit_int8((unsigned char)0xE6);
1722 emit_int8((unsigned char)(0xC0 | encode));
1723 }
1724
1725 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1727 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1728 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1729 emit_int8(0x5B);
1730 emit_int8((unsigned char)(0xC0 | encode));
1731 }
1732
1733 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1735 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1736 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1737 emit_int8(0x5A);
1738 emit_int8((unsigned char)(0xC0 | encode));
1739 }
1740
1741 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1743 InstructionMark im(this);
1744 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1745 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1746 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1747 emit_int8(0x5A);
1748 emit_operand(dst, src);
1749 }
1750
1751 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1753 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1754 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1755 emit_int8(0x2A);
1756 emit_int8((unsigned char)(0xC0 | encode));
1757 }
1758
1759 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1761 InstructionMark im(this);
1762 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1763 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1764 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1765 emit_int8(0x2A);
1766 emit_operand(dst, src);
1767 }
1768
1769 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1770 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1772 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1773 emit_int8(0x2A);
1774 emit_int8((unsigned char)(0xC0 | encode));
1775 }
1776
1777 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1778 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1779 InstructionMark im(this);
1780 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1781 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1782 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1783 emit_int8(0x2A);
1784 emit_operand(dst, src);
1785 }
1786
1787 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1788 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1789 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1790 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1791 emit_int8(0x2A);
1792 emit_int8((unsigned char)(0xC0 | encode));
1793 }
1794
1795 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1796 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1798 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1799 emit_int8(0x5A);
1800 emit_int8((unsigned char)(0xC0 | encode));
1801 }
1802
1803 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1804 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1805 InstructionMark im(this);
1806 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1807 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1808 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1809 emit_int8(0x5A);
1810 emit_operand(dst, src);
1811 }
1812
1813
1814 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1815 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1817 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1818 emit_int8(0x2C);
1819 emit_int8((unsigned char)(0xC0 | encode));
1820 }
1821
1822 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1823 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1825 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1826 emit_int8(0x2C);
1827 emit_int8((unsigned char)(0xC0 | encode));
1828 }
1829
1830 void Assembler::decl(Address dst) {
1831 // Don't use it directly. Use MacroAssembler::decrement() instead.
1832 InstructionMark im(this);
1833 prefix(dst);
1834 emit_int8((unsigned char)0xFF);
1835 emit_operand(rcx, dst);
1836 }
1837
1838 void Assembler::divsd(XMMRegister dst, Address src) {
1839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1840 InstructionMark im(this);
1841 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1842 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1843 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1844 emit_int8(0x5E);
1845 emit_operand(dst, src);
1846 }
1847
1848 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1849 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1850 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1851 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1852 emit_int8(0x5E);
1853 emit_int8((unsigned char)(0xC0 | encode));
1854 }
1855
1856 void Assembler::divss(XMMRegister dst, Address src) {
1857 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1858 InstructionMark im(this);
1859 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1860 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1861 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1862 emit_int8(0x5E);
1863 emit_operand(dst, src);
1864 }
1865
1866 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1867 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1868 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1869 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1870 emit_int8(0x5E);
1871 emit_int8((unsigned char)(0xC0 | encode));
1872 }
1873
1874 void Assembler::emms() {
1875 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1876 emit_int8(0x0F);
1877 emit_int8(0x77);
1878 }
1879
1880 void Assembler::hlt() {
1881 emit_int8((unsigned char)0xF4);
1882 }
1883
1884 void Assembler::idivl(Register src) {
1885 int encode = prefix_and_encode(src->encoding());
1886 emit_int8((unsigned char)0xF7);
1887 emit_int8((unsigned char)(0xF8 | encode));
1888 }
1889
1890 void Assembler::divl(Register src) { // Unsigned
1891 int encode = prefix_and_encode(src->encoding());
1892 emit_int8((unsigned char)0xF7);
1893 emit_int8((unsigned char)(0xF0 | encode));
1894 }
1895
1896 void Assembler::imull(Register src) {
1897 int encode = prefix_and_encode(src->encoding());
1898 emit_int8((unsigned char)0xF7);
1899 emit_int8((unsigned char)(0xE8 | encode));
1900 }
1901
1902 void Assembler::imull(Register dst, Register src) {
1903 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1904 emit_int8(0x0F);
1905 emit_int8((unsigned char)0xAF);
1906 emit_int8((unsigned char)(0xC0 | encode));
1907 }
1908
1909
1910 void Assembler::imull(Register dst, Register src, int value) {
1911 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1912 if (is8bit(value)) {
1913 emit_int8(0x6B);
1914 emit_int8((unsigned char)(0xC0 | encode));
1915 emit_int8(value & 0xFF);
1916 } else {
1917 emit_int8(0x69);
1918 emit_int8((unsigned char)(0xC0 | encode));
1919 emit_int32(value);
1920 }
1921 }
1922
1923 void Assembler::imull(Register dst, Address src) {
1924 InstructionMark im(this);
1925 prefix(src, dst);
1926 emit_int8(0x0F);
1927 emit_int8((unsigned char) 0xAF);
1928 emit_operand(dst, src);
1929 }
1930
1931
1932 void Assembler::incl(Address dst) {
1933 // Don't use it directly. Use MacroAssembler::increment() instead.
1934 InstructionMark im(this);
1935 prefix(dst);
1936 emit_int8((unsigned char)0xFF);
1937 emit_operand(rax, dst);
1938 }
1939
1940 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
1941 InstructionMark im(this);
1942 assert((0 <= cc) && (cc < 16), "illegal cc");
1943 if (L.is_bound()) {
1944 address dst = target(L);
1945 assert(dst != NULL, "jcc most probably wrong");
1946
1947 const int short_size = 2;
1948 const int long_size = 6;
1949 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
1950 if (maybe_short && is8bit(offs - short_size)) {
1951 // 0111 tttn #8-bit disp
1952 emit_int8(0x70 | cc);
1953 emit_int8((offs - short_size) & 0xFF);
1954 } else {
1955 // 0000 1111 1000 tttn #32-bit disp
1956 assert(is_simm32(offs - long_size),
1957 "must be 32bit offset (call4)");
1958 emit_int8(0x0F);
1959 emit_int8((unsigned char)(0x80 | cc));
1960 emit_int32(offs - long_size);
1961 }
1962 } else {
1963 // Note: could eliminate cond. jumps to this jump if condition
1964 // is the same however, seems to be rather unlikely case.
1965 // Note: use jccb() if label to be bound is very close to get
1966 // an 8-bit displacement
1967 L.add_patch_at(code(), locator());
1968 emit_int8(0x0F);
1969 emit_int8((unsigned char)(0x80 | cc));
1970 emit_int32(0);
1971 }
1972 }
1973
1974 void Assembler::jccb(Condition cc, Label& L) {
1975 if (L.is_bound()) {
1976 const int short_size = 2;
1977 address entry = target(L);
1978 #ifdef ASSERT
1979 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
1980 intptr_t delta = short_branch_delta();
1981 if (delta != 0) {
1982 dist += (dist < 0 ? (-delta) :delta);
1983 }
1984 assert(is8bit(dist), "Dispacement too large for a short jmp");
1985 #endif
1986 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
1987 // 0111 tttn #8-bit disp
1988 emit_int8(0x70 | cc);
1989 emit_int8((offs - short_size) & 0xFF);
1990 } else {
1991 InstructionMark im(this);
1992 L.add_patch_at(code(), locator());
1993 emit_int8(0x70 | cc);
1994 emit_int8(0);
1995 }
1996 }
1997
1998 void Assembler::jmp(Address adr) {
1999 InstructionMark im(this);
2000 prefix(adr);
2001 emit_int8((unsigned char)0xFF);
2002 emit_operand(rsp, adr);
2003 }
2004
2005 void Assembler::jmp(Label& L, bool maybe_short) {
2006 if (L.is_bound()) {
2007 address entry = target(L);
2008 assert(entry != NULL, "jmp most probably wrong");
2009 InstructionMark im(this);
2010 const int short_size = 2;
2011 const int long_size = 5;
2012 intptr_t offs = entry - pc();
2013 if (maybe_short && is8bit(offs - short_size)) {
2014 emit_int8((unsigned char)0xEB);
2015 emit_int8((offs - short_size) & 0xFF);
2016 } else {
2017 emit_int8((unsigned char)0xE9);
2018 emit_int32(offs - long_size);
2019 }
2020 } else {
2021 // By default, forward jumps are always 32-bit displacements, since
2022 // we can't yet know where the label will be bound. If you're sure that
2023 // the forward jump will not run beyond 256 bytes, use jmpb to
2024 // force an 8-bit displacement.
2025 InstructionMark im(this);
2026 L.add_patch_at(code(), locator());
2027 emit_int8((unsigned char)0xE9);
2028 emit_int32(0);
2029 }
2030 }
2031
2032 void Assembler::jmp(Register entry) {
2033 int encode = prefix_and_encode(entry->encoding());
2034 emit_int8((unsigned char)0xFF);
2035 emit_int8((unsigned char)(0xE0 | encode));
2036 }
2037
2038 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2039 InstructionMark im(this);
2040 emit_int8((unsigned char)0xE9);
2041 assert(dest != NULL, "must have a target");
2042 intptr_t disp = dest - (pc() + sizeof(int32_t));
2043 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2044 emit_data(disp, rspec.reloc(), call32_operand);
2045 }
2046
2047 void Assembler::jmpb(Label& L) {
2048 if (L.is_bound()) {
2049 const int short_size = 2;
2050 address entry = target(L);
2051 assert(entry != NULL, "jmp most probably wrong");
2052 #ifdef ASSERT
2053 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2054 intptr_t delta = short_branch_delta();
2055 if (delta != 0) {
2056 dist += (dist < 0 ? (-delta) :delta);
2057 }
2058 assert(is8bit(dist), "Dispacement too large for a short jmp");
2059 #endif
2060 intptr_t offs = entry - pc();
2061 emit_int8((unsigned char)0xEB);
2062 emit_int8((offs - short_size) & 0xFF);
2063 } else {
2064 InstructionMark im(this);
2065 L.add_patch_at(code(), locator());
2066 emit_int8((unsigned char)0xEB);
2067 emit_int8(0);
2068 }
2069 }
2070
2071 void Assembler::ldmxcsr( Address src) {
2072 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2073 InstructionMark im(this);
2074 prefix(src);
2075 emit_int8(0x0F);
2076 emit_int8((unsigned char)0xAE);
2077 emit_operand(as_Register(2), src);
2078 }
2079
2080 void Assembler::leal(Register dst, Address src) {
2081 InstructionMark im(this);
2082 #ifdef _LP64
2083 emit_int8(0x67); // addr32
2084 prefix(src, dst);
2085 #endif // LP64
2086 emit_int8((unsigned char)0x8D);
2087 emit_operand(dst, src);
2088 }
2089
2090 void Assembler::lfence() {
2091 emit_int8(0x0F);
2092 emit_int8((unsigned char)0xAE);
2093 emit_int8((unsigned char)0xE8);
2094 }
2095
2096 void Assembler::lock() {
2097 emit_int8((unsigned char)0xF0);
2098 }
2099
2100 void Assembler::lzcntl(Register dst, Register src) {
2101 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2102 emit_int8((unsigned char)0xF3);
2103 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2104 emit_int8(0x0F);
2105 emit_int8((unsigned char)0xBD);
2106 emit_int8((unsigned char)(0xC0 | encode));
2107 }
2108
2109 // Emit mfence instruction
2110 void Assembler::mfence() {
2111 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2112 emit_int8(0x0F);
2113 emit_int8((unsigned char)0xAE);
2114 emit_int8((unsigned char)0xF0);
2115 }
2116
2117 void Assembler::mov(Register dst, Register src) {
2118 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2119 }
2120
2121 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2123 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2124 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2125 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2126 emit_int8(0x28);
2127 emit_int8((unsigned char)(0xC0 | encode));
2128 }
2129
2130 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2131 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2132 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2133 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2134 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2135 emit_int8(0x28);
2136 emit_int8((unsigned char)(0xC0 | encode));
2137 }
2138
2139 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2140 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2142 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2143 emit_int8(0x16);
2144 emit_int8((unsigned char)(0xC0 | encode));
2145 }
2146
2147 void Assembler::movb(Register dst, Address src) {
2148 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2149 InstructionMark im(this);
2150 prefix(src, dst, true);
2151 emit_int8((unsigned char)0x8A);
2152 emit_operand(dst, src);
2153 }
2154
2155 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2156 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2157 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2158 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2159 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2160 emit_int8(0x12);
2161 emit_int8(0xC0 | encode);
2162 }
2163
2164 void Assembler::kmovbl(KRegister dst, Register src) {
2165 assert(VM_Version::supports_avx512dq(), "");
2166 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2167 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2168 emit_int8((unsigned char)0x92);
2169 emit_int8((unsigned char)(0xC0 | encode));
2170 }
2171
2172 void Assembler::kmovbl(Register dst, KRegister src) {
2173 assert(VM_Version::supports_avx512dq(), "");
2174 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2175 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2176 emit_int8((unsigned char)0x93);
2177 emit_int8((unsigned char)(0xC0 | encode));
2178 }
2179
2180 void Assembler::kmovwl(KRegister dst, Register src) {
2181 assert(VM_Version::supports_evex(), "");
2182 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2183 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2184 emit_int8((unsigned char)0x92);
2185 emit_int8((unsigned char)(0xC0 | encode));
2186 }
2187
2188 void Assembler::kmovwl(Register dst, KRegister src) {
2189 assert(VM_Version::supports_evex(), "");
2190 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2191 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2192 emit_int8((unsigned char)0x93);
2193 emit_int8((unsigned char)(0xC0 | encode));
2194 }
2195
2196 void Assembler::kmovdl(KRegister dst, Register src) {
2197 assert(VM_Version::supports_avx512bw(), "");
2198 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2199 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2200 emit_int8((unsigned char)0x92);
2201 emit_int8((unsigned char)(0xC0 | encode));
2202 }
2203
2204 void Assembler::kmovdl(Register dst, KRegister src) {
2205 assert(VM_Version::supports_avx512bw(), "");
2206 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2207 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2208 emit_int8((unsigned char)0x93);
2209 emit_int8((unsigned char)(0xC0 | encode));
2210 }
2211
2212 void Assembler::kmovql(KRegister dst, KRegister src) {
2213 assert(VM_Version::supports_avx512bw(), "");
2214 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2215 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2216 emit_int8((unsigned char)0x90);
2217 emit_int8((unsigned char)(0xC0 | encode));
2218 }
2219
2220 void Assembler::kmovql(KRegister dst, Address src) {
2221 assert(VM_Version::supports_avx512bw(), "");
2222 InstructionMark im(this);
2223 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2224 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2225 emit_int8((unsigned char)0x90);
2226 emit_operand((Register)dst, src);
2227 }
2228
2229 void Assembler::kmovql(Address dst, KRegister src) {
2230 assert(VM_Version::supports_avx512bw(), "");
2231 InstructionMark im(this);
2232 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2233 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2234 emit_int8((unsigned char)0x90);
2235 emit_operand((Register)src, dst);
2236 }
2237
2238 void Assembler::kmovql(KRegister dst, Register src) {
2239 assert(VM_Version::supports_avx512bw(), "");
2240 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2241 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2242 emit_int8((unsigned char)0x92);
2243 emit_int8((unsigned char)(0xC0 | encode));
2244 }
2245
2246 void Assembler::kmovql(Register dst, KRegister src) {
2247 assert(VM_Version::supports_avx512bw(), "");
2248 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2249 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2250 emit_int8((unsigned char)0x93);
2251 emit_int8((unsigned char)(0xC0 | encode));
2252 }
2253
2254 // This instruction produces ZF or CF flags
2255 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2256 assert(VM_Version::supports_avx512dq(), "");
2257 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2258 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2259 emit_int8((unsigned char)0x98);
2260 emit_int8((unsigned char)(0xC0 | encode));
2261 }
2262
2263 // This instruction produces ZF or CF flags
2264 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2265 assert(VM_Version::supports_evex(), "");
2266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2267 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2268 emit_int8((unsigned char)0x98);
2269 emit_int8((unsigned char)(0xC0 | encode));
2270 }
2271
2272 // This instruction produces ZF or CF flags
2273 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2274 assert(VM_Version::supports_avx512bw(), "");
2275 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2276 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2277 emit_int8((unsigned char)0x98);
2278 emit_int8((unsigned char)(0xC0 | encode));
2279 }
2280
2281 // This instruction produces ZF or CF flags
2282 void Assembler::kortestql(KRegister src1, KRegister src2) {
2283 assert(VM_Version::supports_avx512bw(), "");
2284 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2285 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2286 emit_int8((unsigned char)0x98);
2287 emit_int8((unsigned char)(0xC0 | encode));
2288 }
2289
2290 void Assembler::movb(Address dst, int imm8) {
2291 InstructionMark im(this);
2292 prefix(dst);
2293 emit_int8((unsigned char)0xC6);
2294 emit_operand(rax, dst, 1);
2295 emit_int8(imm8);
2296 }
2297
2298
2299 void Assembler::movb(Address dst, Register src) {
2300 assert(src->has_byte_register(), "must have byte register");
2301 InstructionMark im(this);
2302 prefix(dst, src, true);
2303 emit_int8((unsigned char)0x88);
2304 emit_operand(src, dst);
2305 }
2306
2307 void Assembler::movdl(XMMRegister dst, Register src) {
2308 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2309 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2310 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2311 emit_int8(0x6E);
2312 emit_int8((unsigned char)(0xC0 | encode));
2313 }
2314
2315 void Assembler::movdl(Register dst, XMMRegister src) {
2316 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2317 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2318 // swap src/dst to get correct prefix
2319 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2320 emit_int8(0x7E);
2321 emit_int8((unsigned char)(0xC0 | encode));
2322 }
2323
2324 void Assembler::movdl(XMMRegister dst, Address src) {
2325 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2326 InstructionMark im(this);
2327 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2328 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2329 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2330 emit_int8(0x6E);
2331 emit_operand(dst, src);
2332 }
2333
2334 void Assembler::movdl(Address dst, XMMRegister src) {
2335 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2336 InstructionMark im(this);
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2338 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2339 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2340 emit_int8(0x7E);
2341 emit_operand(src, dst);
2342 }
2343
2344 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2346 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2347 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2348 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2349 emit_int8(0x6F);
2350 emit_int8((unsigned char)(0xC0 | encode));
2351 }
2352
2353 void Assembler::movdqa(XMMRegister dst, Address src) {
2354 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2355 InstructionMark im(this);
2356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2357 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2358 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2359 emit_int8(0x6F);
2360 emit_operand(dst, src);
2361 }
2362
2363 void Assembler::movdqu(XMMRegister dst, Address src) {
2364 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2365 InstructionMark im(this);
2366 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2367 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2368 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2369 emit_int8(0x6F);
2370 emit_operand(dst, src);
2371 }
2372
2373 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2374 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2376 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2377 emit_int8(0x6F);
2378 emit_int8((unsigned char)(0xC0 | encode));
2379 }
2380
2381 void Assembler::movdqu(Address dst, XMMRegister src) {
2382 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2383 InstructionMark im(this);
2384 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2385 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2386 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2387 emit_int8(0x7F);
2388 emit_operand(src, dst);
2389 }
2390
2391 // Move Unaligned 256bit Vector
2392 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2393 assert(UseAVX > 0, "");
2394 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2395 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2396 emit_int8(0x6F);
2397 emit_int8((unsigned char)(0xC0 | encode));
2398 }
2399
2400 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2401 assert(UseAVX > 0, "");
2402 InstructionMark im(this);
2403 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2404 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2405 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2406 emit_int8(0x6F);
2407 emit_operand(dst, src);
2408 }
2409
2410 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2411 assert(UseAVX > 0, "");
2412 InstructionMark im(this);
2413 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2414 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2415 // swap src<->dst for encoding
2416 assert(src != xnoreg, "sanity");
2417 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2418 emit_int8(0x7F);
2419 emit_operand(src, dst);
2420 }
2421
2422 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2423 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
2424 assert(VM_Version::supports_evex(), "");
2425 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2426 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2427 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2428 emit_int8(0x6F);
2429 emit_int8((unsigned char)(0xC0 | encode));
2430 }
2431
2432 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
2433 assert(VM_Version::supports_evex(), "");
2434 InstructionMark im(this);
2435 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2436 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2437 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2438 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2439 emit_int8(0x6F);
2440 emit_operand(dst, src);
2441 }
2442
2443 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) {
2444 assert(VM_Version::supports_evex(), "");
2445 assert(src != xnoreg, "sanity");
2446 InstructionMark im(this);
2447 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2448 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2449 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2450 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2451 emit_int8(0x7F);
2452 emit_operand(src, dst);
2453 }
2454
2455 void Assembler::evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) {
2456 assert(VM_Version::supports_evex(), "");
2457 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2458 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2459 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2460 emit_int8(0x6F);
2461 emit_int8((unsigned char)(0xC0 | encode));
2462 }
2463
2464 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
2465 assert(VM_Version::supports_evex(), "");
2466 InstructionMark im(this);
2467 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2468 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2469 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2470 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2471 emit_int8(0x6F);
2472 emit_operand(dst, src);
2473 }
2474
2475 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
2476 assert(VM_Version::supports_evex(), "");
2477 assert(src != xnoreg, "sanity");
2478 InstructionMark im(this);
2479 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2480 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2481 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2482 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2483 emit_int8(0x7F);
2484 emit_operand(src, dst);
2485 }
2486
2487 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2488 assert(VM_Version::supports_evex(), "");
2489 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2490 attributes.set_is_evex_instruction();
2491 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2492 emit_int8(0x6F);
2493 emit_int8((unsigned char)(0xC0 | encode));
2494 }
2495
2496 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2497 assert(VM_Version::supports_evex(), "");
2498 InstructionMark im(this);
2499 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2500 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2501 attributes.set_is_evex_instruction();
2502 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2503 emit_int8(0x6F);
2504 emit_operand(dst, src);
2505 }
2506
2507 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2508 assert(VM_Version::supports_evex(), "");
2509 assert(src != xnoreg, "sanity");
2510 InstructionMark im(this);
2511 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2512 attributes.set_is_evex_instruction();
2513 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2514 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2515 emit_int8(0x7F);
2516 emit_operand(src, dst);
2517 }
2518
2519 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2520 assert(VM_Version::supports_evex(), "");
2521 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2522 attributes.set_is_evex_instruction();
2523 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2524 emit_int8(0x6F);
2525 emit_int8((unsigned char)(0xC0 | encode));
2526 }
2527
2528 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2529 assert(VM_Version::supports_evex(), "");
2530 InstructionMark im(this);
2531 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2532 attributes.set_is_evex_instruction();
2533 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2534 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2535 emit_int8(0x6F);
2536 emit_operand(dst, src);
2537 }
2538
2539 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2540 assert(VM_Version::supports_evex(), "");
2541 assert(src != xnoreg, "sanity");
2542 InstructionMark im(this);
2543 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2544 attributes.set_is_evex_instruction();
2545 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2546 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2547 emit_int8(0x7F);
2548 emit_operand(src, dst);
2549 }
2550
2551 // Uses zero extension on 64bit
2552
2553 void Assembler::movl(Register dst, int32_t imm32) {
2554 int encode = prefix_and_encode(dst->encoding());
2555 emit_int8((unsigned char)(0xB8 | encode));
2556 emit_int32(imm32);
2557 }
2558
2559 void Assembler::movl(Register dst, Register src) {
2560 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2561 emit_int8((unsigned char)0x8B);
2562 emit_int8((unsigned char)(0xC0 | encode));
2563 }
2564
2565 void Assembler::movl(Register dst, Address src) {
2566 InstructionMark im(this);
2567 prefix(src, dst);
2568 emit_int8((unsigned char)0x8B);
2569 emit_operand(dst, src);
2570 }
2571
2572 void Assembler::movl(Address dst, int32_t imm32) {
2573 InstructionMark im(this);
2574 prefix(dst);
2575 emit_int8((unsigned char)0xC7);
2576 emit_operand(rax, dst, 4);
2577 emit_int32(imm32);
2578 }
2579
2580 void Assembler::movl(Address dst, Register src) {
2581 InstructionMark im(this);
2582 prefix(dst, src);
2583 emit_int8((unsigned char)0x89);
2584 emit_operand(src, dst);
2585 }
2586
2587 // New cpus require to use movsd and movss to avoid partial register stall
2588 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2589 // The selection is done in MacroAssembler::movdbl() and movflt().
2590 void Assembler::movlpd(XMMRegister dst, Address src) {
2591 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2592 InstructionMark im(this);
2593 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2594 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2595 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2596 emit_int8(0x12);
2597 emit_operand(dst, src);
2598 }
2599
2600 void Assembler::movq( MMXRegister dst, Address src ) {
2601 assert( VM_Version::supports_mmx(), "" );
2602 emit_int8(0x0F);
2603 emit_int8(0x6F);
2604 emit_operand(dst, src);
2605 }
2606
2607 void Assembler::movq( Address dst, MMXRegister src ) {
2608 assert( VM_Version::supports_mmx(), "" );
2609 emit_int8(0x0F);
2610 emit_int8(0x7F);
2611 // workaround gcc (3.2.1-7a) bug
2612 // In that version of gcc with only an emit_operand(MMX, Address)
2613 // gcc will tail jump and try and reverse the parameters completely
2614 // obliterating dst in the process. By having a version available
2615 // that doesn't need to swap the args at the tail jump the bug is
2616 // avoided.
2617 emit_operand(dst, src);
2618 }
2619
2620 void Assembler::movq(XMMRegister dst, Address src) {
2621 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2622 InstructionMark im(this);
2623 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2624 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2625 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2626 emit_int8(0x7E);
2627 emit_operand(dst, src);
2628 }
2629
2630 void Assembler::movq(Address dst, XMMRegister src) {
2631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2632 InstructionMark im(this);
2633 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2634 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2635 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2636 emit_int8((unsigned char)0xD6);
2637 emit_operand(src, dst);
2638 }
2639
2640 void Assembler::movsbl(Register dst, Address src) { // movsxb
2641 InstructionMark im(this);
2642 prefix(src, dst);
2643 emit_int8(0x0F);
2644 emit_int8((unsigned char)0xBE);
2645 emit_operand(dst, src);
2646 }
2647
2648 void Assembler::movsbl(Register dst, Register src) { // movsxb
2649 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2650 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2651 emit_int8(0x0F);
2652 emit_int8((unsigned char)0xBE);
2653 emit_int8((unsigned char)(0xC0 | encode));
2654 }
2655
2656 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2657 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2658 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2659 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2660 emit_int8(0x10);
2661 emit_int8((unsigned char)(0xC0 | encode));
2662 }
2663
2664 void Assembler::movsd(XMMRegister dst, Address src) {
2665 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2666 InstructionMark im(this);
2667 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2669 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2670 emit_int8(0x10);
2671 emit_operand(dst, src);
2672 }
2673
2674 void Assembler::movsd(Address dst, XMMRegister src) {
2675 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2676 InstructionMark im(this);
2677 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2678 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2679 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2680 emit_int8(0x11);
2681 emit_operand(src, dst);
2682 }
2683
2684 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2685 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2686 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2687 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2688 emit_int8(0x10);
2689 emit_int8((unsigned char)(0xC0 | encode));
2690 }
2691
2692 void Assembler::movss(XMMRegister dst, Address src) {
2693 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2694 InstructionMark im(this);
2695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2696 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2697 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2698 emit_int8(0x10);
2699 emit_operand(dst, src);
2700 }
2701
2702 void Assembler::movss(Address dst, XMMRegister src) {
2703 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2704 InstructionMark im(this);
2705 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2706 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2707 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2708 emit_int8(0x11);
2709 emit_operand(src, dst);
2710 }
2711
2712 void Assembler::movswl(Register dst, Address src) { // movsxw
2713 InstructionMark im(this);
2714 prefix(src, dst);
2715 emit_int8(0x0F);
2716 emit_int8((unsigned char)0xBF);
2717 emit_operand(dst, src);
2718 }
2719
2720 void Assembler::movswl(Register dst, Register src) { // movsxw
2721 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2722 emit_int8(0x0F);
2723 emit_int8((unsigned char)0xBF);
2724 emit_int8((unsigned char)(0xC0 | encode));
2725 }
2726
2727 void Assembler::movw(Address dst, int imm16) {
2728 InstructionMark im(this);
2729
2730 emit_int8(0x66); // switch to 16-bit mode
2731 prefix(dst);
2732 emit_int8((unsigned char)0xC7);
2733 emit_operand(rax, dst, 2);
2734 emit_int16(imm16);
2735 }
2736
2737 void Assembler::movw(Register dst, Address src) {
2738 InstructionMark im(this);
2739 emit_int8(0x66);
2740 prefix(src, dst);
2741 emit_int8((unsigned char)0x8B);
2742 emit_operand(dst, src);
2743 }
2744
2745 void Assembler::movw(Address dst, Register src) {
2746 InstructionMark im(this);
2747 emit_int8(0x66);
2748 prefix(dst, src);
2749 emit_int8((unsigned char)0x89);
2750 emit_operand(src, dst);
2751 }
2752
2753 void Assembler::movzbl(Register dst, Address src) { // movzxb
2754 InstructionMark im(this);
2755 prefix(src, dst);
2756 emit_int8(0x0F);
2757 emit_int8((unsigned char)0xB6);
2758 emit_operand(dst, src);
2759 }
2760
2761 void Assembler::movzbl(Register dst, Register src) { // movzxb
2762 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2763 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2764 emit_int8(0x0F);
2765 emit_int8((unsigned char)0xB6);
2766 emit_int8(0xC0 | encode);
2767 }
2768
2769 void Assembler::movzwl(Register dst, Address src) { // movzxw
2770 InstructionMark im(this);
2771 prefix(src, dst);
2772 emit_int8(0x0F);
2773 emit_int8((unsigned char)0xB7);
2774 emit_operand(dst, src);
2775 }
2776
2777 void Assembler::movzwl(Register dst, Register src) { // movzxw
2778 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2779 emit_int8(0x0F);
2780 emit_int8((unsigned char)0xB7);
2781 emit_int8(0xC0 | encode);
2782 }
2783
2784 void Assembler::mull(Address src) {
2785 InstructionMark im(this);
2786 prefix(src);
2787 emit_int8((unsigned char)0xF7);
2788 emit_operand(rsp, src);
2789 }
2790
2791 void Assembler::mull(Register src) {
2792 int encode = prefix_and_encode(src->encoding());
2793 emit_int8((unsigned char)0xF7);
2794 emit_int8((unsigned char)(0xE0 | encode));
2795 }
2796
2797 void Assembler::mulsd(XMMRegister dst, Address src) {
2798 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2799 InstructionMark im(this);
2800 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2801 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2802 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2803 emit_int8(0x59);
2804 emit_operand(dst, src);
2805 }
2806
2807 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
2808 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2809 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2810 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2811 emit_int8(0x59);
2812 emit_int8((unsigned char)(0xC0 | encode));
2813 }
2814
2815 void Assembler::mulss(XMMRegister dst, Address src) {
2816 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2817 InstructionMark im(this);
2818 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2819 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2820 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2821 emit_int8(0x59);
2822 emit_operand(dst, src);
2823 }
2824
2825 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
2826 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2827 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2828 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2829 emit_int8(0x59);
2830 emit_int8((unsigned char)(0xC0 | encode));
2831 }
2832
2833 void Assembler::negl(Register dst) {
2834 int encode = prefix_and_encode(dst->encoding());
2835 emit_int8((unsigned char)0xF7);
2836 emit_int8((unsigned char)(0xD8 | encode));
2837 }
2838
2839 void Assembler::nop(int i) {
2840 #ifdef ASSERT
2841 assert(i > 0, " ");
2842 // The fancy nops aren't currently recognized by debuggers making it a
2843 // pain to disassemble code while debugging. If asserts are on clearly
2844 // speed is not an issue so simply use the single byte traditional nop
2845 // to do alignment.
2846
2847 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
2848 return;
2849
2850 #endif // ASSERT
2851
2852 if (UseAddressNop && VM_Version::is_intel()) {
2853 //
2854 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
2855 // 1: 0x90
2856 // 2: 0x66 0x90
2857 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2858 // 4: 0x0F 0x1F 0x40 0x00
2859 // 5: 0x0F 0x1F 0x44 0x00 0x00
2860 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2861 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2862 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2863 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2864 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2865 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2866
2867 // The rest coding is Intel specific - don't use consecutive address nops
2868
2869 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2870 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2871 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2872 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
2873
2874 while(i >= 15) {
2875 // For Intel don't generate consecutive addess nops (mix with regular nops)
2876 i -= 15;
2877 emit_int8(0x66); // size prefix
2878 emit_int8(0x66); // size prefix
2879 emit_int8(0x66); // size prefix
2880 addr_nop_8();
2881 emit_int8(0x66); // size prefix
2882 emit_int8(0x66); // size prefix
2883 emit_int8(0x66); // size prefix
2884 emit_int8((unsigned char)0x90);
2885 // nop
2886 }
2887 switch (i) {
2888 case 14:
2889 emit_int8(0x66); // size prefix
2890 case 13:
2891 emit_int8(0x66); // size prefix
2892 case 12:
2893 addr_nop_8();
2894 emit_int8(0x66); // size prefix
2895 emit_int8(0x66); // size prefix
2896 emit_int8(0x66); // size prefix
2897 emit_int8((unsigned char)0x90);
2898 // nop
2899 break;
2900 case 11:
2901 emit_int8(0x66); // size prefix
2902 case 10:
2903 emit_int8(0x66); // size prefix
2904 case 9:
2905 emit_int8(0x66); // size prefix
2906 case 8:
2907 addr_nop_8();
2908 break;
2909 case 7:
2910 addr_nop_7();
2911 break;
2912 case 6:
2913 emit_int8(0x66); // size prefix
2914 case 5:
2915 addr_nop_5();
2916 break;
2917 case 4:
2918 addr_nop_4();
2919 break;
2920 case 3:
2921 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
2922 emit_int8(0x66); // size prefix
2923 case 2:
2924 emit_int8(0x66); // size prefix
2925 case 1:
2926 emit_int8((unsigned char)0x90);
2927 // nop
2928 break;
2929 default:
2930 assert(i == 0, " ");
2931 }
2932 return;
2933 }
2934 if (UseAddressNop && VM_Version::is_amd()) {
2935 //
2936 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
2937 // 1: 0x90
2938 // 2: 0x66 0x90
2939 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
2940 // 4: 0x0F 0x1F 0x40 0x00
2941 // 5: 0x0F 0x1F 0x44 0x00 0x00
2942 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
2943 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2944 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2945 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2946 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2947 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2948
2949 // The rest coding is AMD specific - use consecutive address nops
2950
2951 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2952 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
2953 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2954 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
2955 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
2956 // Size prefixes (0x66) are added for larger sizes
2957
2958 while(i >= 22) {
2959 i -= 11;
2960 emit_int8(0x66); // size prefix
2961 emit_int8(0x66); // size prefix
2962 emit_int8(0x66); // size prefix
2963 addr_nop_8();
2964 }
2965 // Generate first nop for size between 21-12
2966 switch (i) {
2967 case 21:
2968 i -= 1;
2969 emit_int8(0x66); // size prefix
2970 case 20:
2971 case 19:
2972 i -= 1;
2973 emit_int8(0x66); // size prefix
2974 case 18:
2975 case 17:
2976 i -= 1;
2977 emit_int8(0x66); // size prefix
2978 case 16:
2979 case 15:
2980 i -= 8;
2981 addr_nop_8();
2982 break;
2983 case 14:
2984 case 13:
2985 i -= 7;
2986 addr_nop_7();
2987 break;
2988 case 12:
2989 i -= 6;
2990 emit_int8(0x66); // size prefix
2991 addr_nop_5();
2992 break;
2993 default:
2994 assert(i < 12, " ");
2995 }
2996
2997 // Generate second nop for size between 11-1
2998 switch (i) {
2999 case 11:
3000 emit_int8(0x66); // size prefix
3001 case 10:
3002 emit_int8(0x66); // size prefix
3003 case 9:
3004 emit_int8(0x66); // size prefix
3005 case 8:
3006 addr_nop_8();
3007 break;
3008 case 7:
3009 addr_nop_7();
3010 break;
3011 case 6:
3012 emit_int8(0x66); // size prefix
3013 case 5:
3014 addr_nop_5();
3015 break;
3016 case 4:
3017 addr_nop_4();
3018 break;
3019 case 3:
3020 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3021 emit_int8(0x66); // size prefix
3022 case 2:
3023 emit_int8(0x66); // size prefix
3024 case 1:
3025 emit_int8((unsigned char)0x90);
3026 // nop
3027 break;
3028 default:
3029 assert(i == 0, " ");
3030 }
3031 return;
3032 }
3033
3034 // Using nops with size prefixes "0x66 0x90".
3035 // From AMD Optimization Guide:
3036 // 1: 0x90
3037 // 2: 0x66 0x90
3038 // 3: 0x66 0x66 0x90
3039 // 4: 0x66 0x66 0x66 0x90
3040 // 5: 0x66 0x66 0x90 0x66 0x90
3041 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3042 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3043 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3044 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3045 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3046 //
3047 while(i > 12) {
3048 i -= 4;
3049 emit_int8(0x66); // size prefix
3050 emit_int8(0x66);
3051 emit_int8(0x66);
3052 emit_int8((unsigned char)0x90);
3053 // nop
3054 }
3055 // 1 - 12 nops
3056 if(i > 8) {
3057 if(i > 9) {
3058 i -= 1;
3059 emit_int8(0x66);
3060 }
3061 i -= 3;
3062 emit_int8(0x66);
3063 emit_int8(0x66);
3064 emit_int8((unsigned char)0x90);
3065 }
3066 // 1 - 8 nops
3067 if(i > 4) {
3068 if(i > 6) {
3069 i -= 1;
3070 emit_int8(0x66);
3071 }
3072 i -= 3;
3073 emit_int8(0x66);
3074 emit_int8(0x66);
3075 emit_int8((unsigned char)0x90);
3076 }
3077 switch (i) {
3078 case 4:
3079 emit_int8(0x66);
3080 case 3:
3081 emit_int8(0x66);
3082 case 2:
3083 emit_int8(0x66);
3084 case 1:
3085 emit_int8((unsigned char)0x90);
3086 break;
3087 default:
3088 assert(i == 0, " ");
3089 }
3090 }
3091
3092 void Assembler::notl(Register dst) {
3093 int encode = prefix_and_encode(dst->encoding());
3094 emit_int8((unsigned char)0xF7);
3095 emit_int8((unsigned char)(0xD0 | encode));
3096 }
3097
3098 void Assembler::orl(Address dst, int32_t imm32) {
3099 InstructionMark im(this);
3100 prefix(dst);
3101 emit_arith_operand(0x81, rcx, dst, imm32);
3102 }
3103
3104 void Assembler::orl(Register dst, int32_t imm32) {
3105 prefix(dst);
3106 emit_arith(0x81, 0xC8, dst, imm32);
3107 }
3108
3109 void Assembler::orl(Register dst, Address src) {
3110 InstructionMark im(this);
3111 prefix(src, dst);
3112 emit_int8(0x0B);
3113 emit_operand(dst, src);
3114 }
3115
3116 void Assembler::orl(Register dst, Register src) {
3117 (void) prefix_and_encode(dst->encoding(), src->encoding());
3118 emit_arith(0x0B, 0xC0, dst, src);
3119 }
3120
3121 void Assembler::orl(Address dst, Register src) {
3122 InstructionMark im(this);
3123 prefix(dst, src);
3124 emit_int8(0x09);
3125 emit_operand(src, dst);
3126 }
3127
3128 void Assembler::packuswb(XMMRegister dst, Address src) {
3129 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3130 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3131 InstructionMark im(this);
3132 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3133 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3134 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3135 emit_int8(0x67);
3136 emit_operand(dst, src);
3137 }
3138
3139 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3142 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3143 emit_int8(0x67);
3144 emit_int8((unsigned char)(0xC0 | encode));
3145 }
3146
3147 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3148 assert(UseAVX > 0, "some form of AVX must be enabled");
3149 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3150 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3151 emit_int8(0x67);
3152 emit_int8((unsigned char)(0xC0 | encode));
3153 }
3154
3155 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3156 assert(VM_Version::supports_avx2(), "");
3157 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3158 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3159 emit_int8(0x00);
3160 emit_int8(0xC0 | encode);
3161 emit_int8(imm8);
3162 }
3163
3164 void Assembler::pause() {
3165 emit_int8((unsigned char)0xF3);
3166 emit_int8((unsigned char)0x90);
3167 }
3168
3169 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3170 assert(VM_Version::supports_sse4_2(), "");
3171 InstructionMark im(this);
3172 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3173 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3174 emit_int8(0x61);
3175 emit_operand(dst, src);
3176 emit_int8(imm8);
3177 }
3178
3179 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3180 assert(VM_Version::supports_sse4_2(), "");
3181 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3182 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3183 emit_int8(0x61);
3184 emit_int8((unsigned char)(0xC0 | encode));
3185 emit_int8(imm8);
3186 }
3187
3188 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3189 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3190 assert(VM_Version::supports_sse2(), "");
3191 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3192 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3193 emit_int8(0x74);
3194 emit_int8((unsigned char)(0xC0 | encode));
3195 }
3196
3197 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3198 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3199 assert(VM_Version::supports_avx(), "");
3200 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3201 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3202 emit_int8(0x74);
3203 emit_int8((unsigned char)(0xC0 | encode));
3204 }
3205
3206 // In this context, kdst is written the mask used to process the equal components
3207 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3208 assert(VM_Version::supports_avx512bw(), "");
3209 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3210 attributes.set_is_evex_instruction();
3211 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3212 emit_int8(0x74);
3213 emit_int8((unsigned char)(0xC0 | encode));
3214 }
3215
3216 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3217 assert(VM_Version::supports_avx512bw(), "");
3218 InstructionMark im(this);
3219 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3220 attributes.set_is_evex_instruction();
3221 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3222 int dst_enc = kdst->encoding();
3223 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3224 emit_int8(0x74);
3225 emit_operand(as_Register(dst_enc), src);
3226 }
3227
3228 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3229 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3230 assert(VM_Version::supports_sse2(), "");
3231 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3232 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3233 emit_int8(0x75);
3234 emit_int8((unsigned char)(0xC0 | encode));
3235 }
3236
3237 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3238 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3239 assert(VM_Version::supports_avx(), "");
3240 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3241 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3242 emit_int8(0x75);
3243 emit_int8((unsigned char)(0xC0 | encode));
3244 }
3245
3246 // In this context, kdst is written the mask used to process the equal components
3247 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3248 assert(VM_Version::supports_avx512bw(), "");
3249 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3250 attributes.set_is_evex_instruction();
3251 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3252 emit_int8(0x75);
3253 emit_int8((unsigned char)(0xC0 | encode));
3254 }
3255
3256 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3257 assert(VM_Version::supports_avx512bw(), "");
3258 InstructionMark im(this);
3259 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3260 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3261 attributes.set_is_evex_instruction();
3262 int dst_enc = kdst->encoding();
3263 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3264 emit_int8(0x75);
3265 emit_operand(as_Register(dst_enc), src);
3266 }
3267
3268 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3269 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3270 assert(VM_Version::supports_sse2(), "");
3271 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3272 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3273 emit_int8(0x76);
3274 emit_int8((unsigned char)(0xC0 | encode));
3275 }
3276
3277 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3278 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3279 assert(VM_Version::supports_avx(), "");
3280 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3281 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3282 emit_int8(0x76);
3283 emit_int8((unsigned char)(0xC0 | encode));
3284 }
3285
3286 // In this context, kdst is written the mask used to process the equal components
3287 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3288 assert(VM_Version::supports_evex(), "");
3289 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3290 attributes.set_is_evex_instruction();
3291 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3292 emit_int8(0x76);
3293 emit_int8((unsigned char)(0xC0 | encode));
3294 }
3295
3296 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3297 assert(VM_Version::supports_evex(), "");
3298 InstructionMark im(this);
3299 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3300 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3301 attributes.set_is_evex_instruction();
3302 int dst_enc = kdst->encoding();
3303 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3304 emit_int8(0x76);
3305 emit_operand(as_Register(dst_enc), src);
3306 }
3307
3308 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3309 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3310 assert(VM_Version::supports_sse4_1(), "");
3311 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3312 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3313 emit_int8(0x29);
3314 emit_int8((unsigned char)(0xC0 | encode));
3315 }
3316
3317 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3318 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3319 assert(VM_Version::supports_avx(), "");
3320 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3321 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3322 emit_int8(0x29);
3323 emit_int8((unsigned char)(0xC0 | encode));
3324 }
3325
3326 // In this context, kdst is written the mask used to process the equal components
3327 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3328 assert(VM_Version::supports_evex(), "");
3329 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3330 attributes.set_is_evex_instruction();
3331 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3332 emit_int8(0x29);
3333 emit_int8((unsigned char)(0xC0 | encode));
3334 }
3335
3336 // In this context, kdst is written the mask used to process the equal components
3337 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3338 assert(VM_Version::supports_evex(), "");
3339 InstructionMark im(this);
3340 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3341 attributes.set_is_evex_instruction();
3342 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3343 int dst_enc = kdst->encoding();
3344 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3345 emit_int8(0x29);
3346 emit_operand(as_Register(dst_enc), src);
3347 }
3348
3349 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3350 assert(VM_Version::supports_sse2(), "");
3351 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3352 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3353 emit_int8((unsigned char)0xD7);
3354 emit_int8((unsigned char)(0xC0 | encode));
3355 }
3356
3357 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3358 assert(VM_Version::supports_avx2(), "");
3359 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3360 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3361 emit_int8((unsigned char)0xD7);
3362 emit_int8((unsigned char)(0xC0 | encode));
3363 }
3364
3365 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3366 assert(VM_Version::supports_sse4_1(), "");
3367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3368 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3369 emit_int8(0x16);
3370 emit_int8((unsigned char)(0xC0 | encode));
3371 emit_int8(imm8);
3372 }
3373
3374 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3375 assert(VM_Version::supports_sse4_1(), "");
3376 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3377 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3378 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3379 emit_int8(0x16);
3380 emit_operand(src, dst);
3381 emit_int8(imm8);
3382 }
3383
3384 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3385 assert(VM_Version::supports_sse4_1(), "");
3386 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3387 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3388 emit_int8(0x16);
3389 emit_int8((unsigned char)(0xC0 | encode));
3390 emit_int8(imm8);
3391 }
3392
3393 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3394 assert(VM_Version::supports_sse4_1(), "");
3395 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3396 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3397 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3398 emit_int8(0x16);
3399 emit_operand(src, dst);
3400 emit_int8(imm8);
3401 }
3402
3403 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3404 assert(VM_Version::supports_sse2(), "");
3405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3406 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3407 emit_int8((unsigned char)0xC5);
3408 emit_int8((unsigned char)(0xC0 | encode));
3409 emit_int8(imm8);
3410 }
3411
3412 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3413 assert(VM_Version::supports_sse4_1(), "");
3414 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3415 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3416 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3417 emit_int8((unsigned char)0x15);
3418 emit_operand(src, dst);
3419 emit_int8(imm8);
3420 }
3421
3422 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3423 assert(VM_Version::supports_sse4_1(), "");
3424 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3425 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3426 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3427 emit_int8(0x14);
3428 emit_operand(src, dst);
3429 emit_int8(imm8);
3430 }
3431
3432 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3433 assert(VM_Version::supports_sse4_1(), "");
3434 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3435 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3436 emit_int8(0x22);
3437 emit_int8((unsigned char)(0xC0 | encode));
3438 emit_int8(imm8);
3439 }
3440
3441 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3442 assert(VM_Version::supports_sse4_1(), "");
3443 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3444 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3445 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3446 emit_int8(0x22);
3447 emit_operand(dst,src);
3448 emit_int8(imm8);
3449 }
3450
3451 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3452 assert(VM_Version::supports_sse4_1(), "");
3453 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3454 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3455 emit_int8(0x22);
3456 emit_int8((unsigned char)(0xC0 | encode));
3457 emit_int8(imm8);
3458 }
3459
3460 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
3461 assert(VM_Version::supports_sse4_1(), "");
3462 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3463 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3464 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3465 emit_int8(0x22);
3466 emit_operand(dst, src);
3467 emit_int8(imm8);
3468 }
3469
3470 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
3471 assert(VM_Version::supports_sse2(), "");
3472 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3473 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3474 emit_int8((unsigned char)0xC4);
3475 emit_int8((unsigned char)(0xC0 | encode));
3476 emit_int8(imm8);
3477 }
3478
3479 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
3480 assert(VM_Version::supports_sse2(), "");
3481 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3482 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3483 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3484 emit_int8((unsigned char)0xC4);
3485 emit_operand(dst, src);
3486 emit_int8(imm8);
3487 }
3488
3489 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
3490 assert(VM_Version::supports_sse4_1(), "");
3491 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3492 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3493 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3494 emit_int8(0x20);
3495 emit_operand(dst, src);
3496 emit_int8(imm8);
3497 }
3498
3499 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
3500 assert(VM_Version::supports_sse4_1(), "");
3501 InstructionMark im(this);
3502 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3503 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3504 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3505 emit_int8(0x30);
3506 emit_operand(dst, src);
3507 }
3508
3509 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3510 assert(VM_Version::supports_sse4_1(), "");
3511 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3512 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3513 emit_int8(0x30);
3514 emit_int8((unsigned char)(0xC0 | encode));
3515 }
3516
3517 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3518 assert(VM_Version::supports_avx(), "");
3519 InstructionMark im(this);
3520 assert(dst != xnoreg, "sanity");
3521 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3522 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
3523 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3524 emit_int8(0x30);
3525 emit_operand(dst, src);
3526 }
3527
3528 // generic
3529 void Assembler::pop(Register dst) {
3530 int encode = prefix_and_encode(dst->encoding());
3531 emit_int8(0x58 | encode);
3532 }
3533
3534 void Assembler::popcntl(Register dst, Address src) {
3535 assert(VM_Version::supports_popcnt(), "must support");
3536 InstructionMark im(this);
3537 emit_int8((unsigned char)0xF3);
3538 prefix(src, dst);
3539 emit_int8(0x0F);
3540 emit_int8((unsigned char)0xB8);
3541 emit_operand(dst, src);
3542 }
3543
3544 void Assembler::popcntl(Register dst, Register src) {
3545 assert(VM_Version::supports_popcnt(), "must support");
3546 emit_int8((unsigned char)0xF3);
3547 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3548 emit_int8(0x0F);
3549 emit_int8((unsigned char)0xB8);
3550 emit_int8((unsigned char)(0xC0 | encode));
3551 }
3552
3553 void Assembler::popf() {
3554 emit_int8((unsigned char)0x9D);
3555 }
3556
3557 #ifndef _LP64 // no 32bit push/pop on amd64
3558 void Assembler::popl(Address dst) {
3559 // NOTE: this will adjust stack by 8byte on 64bits
3560 InstructionMark im(this);
3561 prefix(dst);
3562 emit_int8((unsigned char)0x8F);
3563 emit_operand(rax, dst);
3564 }
3565 #endif
3566
3567 void Assembler::prefetch_prefix(Address src) {
3568 prefix(src);
3569 emit_int8(0x0F);
3570 }
3571
3572 void Assembler::prefetchnta(Address src) {
3573 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3574 InstructionMark im(this);
3575 prefetch_prefix(src);
3576 emit_int8(0x18);
3577 emit_operand(rax, src); // 0, src
3578 }
3579
3580 void Assembler::prefetchr(Address src) {
3581 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3582 InstructionMark im(this);
3583 prefetch_prefix(src);
3584 emit_int8(0x0D);
3585 emit_operand(rax, src); // 0, src
3586 }
3587
3588 void Assembler::prefetcht0(Address src) {
3589 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3590 InstructionMark im(this);
3591 prefetch_prefix(src);
3592 emit_int8(0x18);
3593 emit_operand(rcx, src); // 1, src
3594 }
3595
3596 void Assembler::prefetcht1(Address src) {
3597 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3598 InstructionMark im(this);
3599 prefetch_prefix(src);
3600 emit_int8(0x18);
3601 emit_operand(rdx, src); // 2, src
3602 }
3603
3604 void Assembler::prefetcht2(Address src) {
3605 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
3606 InstructionMark im(this);
3607 prefetch_prefix(src);
3608 emit_int8(0x18);
3609 emit_operand(rbx, src); // 3, src
3610 }
3611
3612 void Assembler::prefetchw(Address src) {
3613 assert(VM_Version::supports_3dnow_prefetch(), "must support");
3614 InstructionMark im(this);
3615 prefetch_prefix(src);
3616 emit_int8(0x0D);
3617 emit_operand(rcx, src); // 1, src
3618 }
3619
3620 void Assembler::prefix(Prefix p) {
3621 emit_int8(p);
3622 }
3623
3624 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
3625 assert(VM_Version::supports_ssse3(), "");
3626 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3627 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3628 emit_int8(0x00);
3629 emit_int8((unsigned char)(0xC0 | encode));
3630 }
3631
3632 void Assembler::pshufb(XMMRegister dst, Address src) {
3633 assert(VM_Version::supports_ssse3(), "");
3634 InstructionMark im(this);
3635 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3636 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3637 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3638 emit_int8(0x00);
3639 emit_operand(dst, src);
3640 }
3641
3642 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
3643 assert(isByte(mode), "invalid value");
3644 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3645 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
3646 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3647 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3648 emit_int8(0x70);
3649 emit_int8((unsigned char)(0xC0 | encode));
3650 emit_int8(mode & 0xFF);
3651 }
3652
3653 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
3654 assert(isByte(mode), "invalid value");
3655 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3656 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3657 InstructionMark im(this);
3658 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3659 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3660 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3661 emit_int8(0x70);
3662 emit_operand(dst, src);
3663 emit_int8(mode & 0xFF);
3664 }
3665
3666 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3667 assert(isByte(mode), "invalid value");
3668 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3669 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3670 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3671 emit_int8(0x70);
3672 emit_int8((unsigned char)(0xC0 | encode));
3673 emit_int8(mode & 0xFF);
3674 }
3675
3676 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
3677 assert(isByte(mode), "invalid value");
3678 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3679 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3680 InstructionMark im(this);
3681 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3682 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3683 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3684 emit_int8(0x70);
3685 emit_operand(dst, src);
3686 emit_int8(mode & 0xFF);
3687 }
3688
3689 void Assembler::psrldq(XMMRegister dst, int shift) {
3690 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3691 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3692 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3693 // XMM3 is for /3 encoding: 66 0F 73 /3 ib
3694 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3695 emit_int8(0x73);
3696 emit_int8((unsigned char)(0xC0 | encode));
3697 emit_int8(shift);
3698 }
3699
3700 void Assembler::pslldq(XMMRegister dst, int shift) {
3701 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
3702 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3703 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3704 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
3705 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3706 emit_int8(0x73);
3707 emit_int8((unsigned char)(0xC0 | encode));
3708 emit_int8(shift);
3709 }
3710
3711 void Assembler::ptest(XMMRegister dst, Address src) {
3712 assert(VM_Version::supports_sse4_1(), "");
3713 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3714 InstructionMark im(this);
3715 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3716 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3717 emit_int8(0x17);
3718 emit_operand(dst, src);
3719 }
3720
3721 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
3722 assert(VM_Version::supports_sse4_1(), "");
3723 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3724 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3725 emit_int8(0x17);
3726 emit_int8((unsigned char)(0xC0 | encode));
3727 }
3728
3729 void Assembler::vptest(XMMRegister dst, Address src) {
3730 assert(VM_Version::supports_avx(), "");
3731 InstructionMark im(this);
3732 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3733 assert(dst != xnoreg, "sanity");
3734 // swap src<->dst for encoding
3735 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3736 emit_int8(0x17);
3737 emit_operand(dst, src);
3738 }
3739
3740 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
3741 assert(VM_Version::supports_avx(), "");
3742 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3743 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3744 emit_int8(0x17);
3745 emit_int8((unsigned char)(0xC0 | encode));
3746 }
3747
3748 void Assembler::punpcklbw(XMMRegister dst, Address src) {
3749 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3750 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3751 InstructionMark im(this);
3752 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3753 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3754 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3755 emit_int8(0x60);
3756 emit_operand(dst, src);
3757 }
3758
3759 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3760 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3761 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
3762 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3763 emit_int8(0x60);
3764 emit_int8((unsigned char)(0xC0 | encode));
3765 }
3766
3767 void Assembler::punpckldq(XMMRegister dst, Address src) {
3768 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3769 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3770 InstructionMark im(this);
3771 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3772 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3773 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3774 emit_int8(0x62);
3775 emit_operand(dst, src);
3776 }
3777
3778 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
3779 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3780 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3781 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3782 emit_int8(0x62);
3783 emit_int8((unsigned char)(0xC0 | encode));
3784 }
3785
3786 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
3787 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3788 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3789 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3790 emit_int8(0x6C);
3791 emit_int8((unsigned char)(0xC0 | encode));
3792 }
3793
3794 void Assembler::push(int32_t imm32) {
3795 // in 64bits we push 64bits onto the stack but only
3796 // take a 32bit immediate
3797 emit_int8(0x68);
3798 emit_int32(imm32);
3799 }
3800
3801 void Assembler::push(Register src) {
3802 int encode = prefix_and_encode(src->encoding());
3803
3804 emit_int8(0x50 | encode);
3805 }
3806
3807 void Assembler::pushf() {
3808 emit_int8((unsigned char)0x9C);
3809 }
3810
3811 #ifndef _LP64 // no 32bit push/pop on amd64
3812 void Assembler::pushl(Address src) {
3813 // Note this will push 64bit on 64bit
3814 InstructionMark im(this);
3815 prefix(src);
3816 emit_int8((unsigned char)0xFF);
3817 emit_operand(rsi, src);
3818 }
3819 #endif
3820
3821 void Assembler::rcll(Register dst, int imm8) {
3822 assert(isShiftCount(imm8), "illegal shift count");
3823 int encode = prefix_and_encode(dst->encoding());
3824 if (imm8 == 1) {
3825 emit_int8((unsigned char)0xD1);
3826 emit_int8((unsigned char)(0xD0 | encode));
3827 } else {
3828 emit_int8((unsigned char)0xC1);
3829 emit_int8((unsigned char)0xD0 | encode);
3830 emit_int8(imm8);
3831 }
3832 }
3833
3834 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
3835 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3836 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3837 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3838 emit_int8(0x53);
3839 emit_int8((unsigned char)(0xC0 | encode));
3840 }
3841
3842 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
3843 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3844 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3845 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3846 emit_int8(0x53);
3847 emit_int8((unsigned char)(0xC0 | encode));
3848 }
3849
3850 void Assembler::rdtsc() {
3851 emit_int8((unsigned char)0x0F);
3852 emit_int8((unsigned char)0x31);
3853 }
3854
3855 // copies data from [esi] to [edi] using rcx pointer sized words
3856 // generic
3857 void Assembler::rep_mov() {
3858 emit_int8((unsigned char)0xF3);
3859 // MOVSQ
3860 LP64_ONLY(prefix(REX_W));
3861 emit_int8((unsigned char)0xA5);
3862 }
3863
3864 // sets rcx bytes with rax, value at [edi]
3865 void Assembler::rep_stosb() {
3866 emit_int8((unsigned char)0xF3); // REP
3867 LP64_ONLY(prefix(REX_W));
3868 emit_int8((unsigned char)0xAA); // STOSB
3869 }
3870
3871 // sets rcx pointer sized words with rax, value at [edi]
3872 // generic
3873 void Assembler::rep_stos() {
3874 emit_int8((unsigned char)0xF3); // REP
3875 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
3876 emit_int8((unsigned char)0xAB);
3877 }
3878
3879 // scans rcx pointer sized words at [edi] for occurance of rax,
3880 // generic
3881 void Assembler::repne_scan() { // repne_scan
3882 emit_int8((unsigned char)0xF2);
3883 // SCASQ
3884 LP64_ONLY(prefix(REX_W));
3885 emit_int8((unsigned char)0xAF);
3886 }
3887
3888 #ifdef _LP64
3889 // scans rcx 4 byte words at [edi] for occurance of rax,
3890 // generic
3891 void Assembler::repne_scanl() { // repne_scan
3892 emit_int8((unsigned char)0xF2);
3893 // SCASL
3894 emit_int8((unsigned char)0xAF);
3895 }
3896 #endif
3897
3898 void Assembler::ret(int imm16) {
3899 if (imm16 == 0) {
3900 emit_int8((unsigned char)0xC3);
3901 } else {
3902 emit_int8((unsigned char)0xC2);
3903 emit_int16(imm16);
3904 }
3905 }
3906
3907 void Assembler::sahf() {
3908 #ifdef _LP64
3909 // Not supported in 64bit mode
3910 ShouldNotReachHere();
3911 #endif
3912 emit_int8((unsigned char)0x9E);
3913 }
3914
3915 void Assembler::sarl(Register dst, int imm8) {
3916 int encode = prefix_and_encode(dst->encoding());
3917 assert(isShiftCount(imm8), "illegal shift count");
3918 if (imm8 == 1) {
3919 emit_int8((unsigned char)0xD1);
3920 emit_int8((unsigned char)(0xF8 | encode));
3921 } else {
3922 emit_int8((unsigned char)0xC1);
3923 emit_int8((unsigned char)(0xF8 | encode));
3924 emit_int8(imm8);
3925 }
3926 }
3927
3928 void Assembler::sarl(Register dst) {
3929 int encode = prefix_and_encode(dst->encoding());
3930 emit_int8((unsigned char)0xD3);
3931 emit_int8((unsigned char)(0xF8 | encode));
3932 }
3933
3934 void Assembler::sbbl(Address dst, int32_t imm32) {
3935 InstructionMark im(this);
3936 prefix(dst);
3937 emit_arith_operand(0x81, rbx, dst, imm32);
3938 }
3939
3940 void Assembler::sbbl(Register dst, int32_t imm32) {
3941 prefix(dst);
3942 emit_arith(0x81, 0xD8, dst, imm32);
3943 }
3944
3945
3946 void Assembler::sbbl(Register dst, Address src) {
3947 InstructionMark im(this);
3948 prefix(src, dst);
3949 emit_int8(0x1B);
3950 emit_operand(dst, src);
3951 }
3952
3953 void Assembler::sbbl(Register dst, Register src) {
3954 (void) prefix_and_encode(dst->encoding(), src->encoding());
3955 emit_arith(0x1B, 0xC0, dst, src);
3956 }
3957
3958 void Assembler::setb(Condition cc, Register dst) {
3959 assert(0 <= cc && cc < 16, "illegal cc");
3960 int encode = prefix_and_encode(dst->encoding(), true);
3961 emit_int8(0x0F);
3962 emit_int8((unsigned char)0x90 | cc);
3963 emit_int8((unsigned char)(0xC0 | encode));
3964 }
3965
3966 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
3967 assert(VM_Version::supports_ssse3(), "");
3968 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
3969 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3970 emit_int8((unsigned char)0x0F);
3971 emit_int8((unsigned char)(0xC0 | encode));
3972 emit_int8(imm8);
3973 }
3974
3975 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
3976 assert(VM_Version::supports_sse4_1(), "");
3977 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3978 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3979 emit_int8((unsigned char)0x0E);
3980 emit_int8((unsigned char)(0xC0 | encode));
3981 emit_int8(imm8);
3982 }
3983
3984 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
3985 assert(VM_Version::supports_sha(), "");
3986 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3987 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
3988 emit_int8((unsigned char)0xCC);
3989 emit_int8((unsigned char)(0xC0 | encode));
3990 emit_int8((unsigned char)imm8);
3991 }
3992
3993 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
3994 assert(VM_Version::supports_sha(), "");
3995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3996 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
3997 emit_int8((unsigned char)0xC8);
3998 emit_int8((unsigned char)(0xC0 | encode));
3999 }
4000
4001 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4002 assert(VM_Version::supports_sha(), "");
4003 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4004 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4005 emit_int8((unsigned char)0xC9);
4006 emit_int8((unsigned char)(0xC0 | encode));
4007 }
4008
4009 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4010 assert(VM_Version::supports_sha(), "");
4011 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4012 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4013 emit_int8((unsigned char)0xCA);
4014 emit_int8((unsigned char)(0xC0 | encode));
4015 }
4016
4017 // xmm0 is implicit additional source to this instruction.
4018 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4019 assert(VM_Version::supports_sha(), "");
4020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4021 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4022 emit_int8((unsigned char)0xCB);
4023 emit_int8((unsigned char)(0xC0 | encode));
4024 }
4025
4026 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4027 assert(VM_Version::supports_sha(), "");
4028 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4029 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4030 emit_int8((unsigned char)0xCC);
4031 emit_int8((unsigned char)(0xC0 | encode));
4032 }
4033
4034 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4035 assert(VM_Version::supports_sha(), "");
4036 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4037 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4038 emit_int8((unsigned char)0xCD);
4039 emit_int8((unsigned char)(0xC0 | encode));
4040 }
4041
4042
4043 void Assembler::shll(Register dst, int imm8) {
4044 assert(isShiftCount(imm8), "illegal shift count");
4045 int encode = prefix_and_encode(dst->encoding());
4046 if (imm8 == 1 ) {
4047 emit_int8((unsigned char)0xD1);
4048 emit_int8((unsigned char)(0xE0 | encode));
4049 } else {
4050 emit_int8((unsigned char)0xC1);
4051 emit_int8((unsigned char)(0xE0 | encode));
4052 emit_int8(imm8);
4053 }
4054 }
4055
4056 void Assembler::shll(Register dst) {
4057 int encode = prefix_and_encode(dst->encoding());
4058 emit_int8((unsigned char)0xD3);
4059 emit_int8((unsigned char)(0xE0 | encode));
4060 }
4061
4062 void Assembler::shrl(Register dst, int imm8) {
4063 assert(isShiftCount(imm8), "illegal shift count");
4064 int encode = prefix_and_encode(dst->encoding());
4065 emit_int8((unsigned char)0xC1);
4066 emit_int8((unsigned char)(0xE8 | encode));
4067 emit_int8(imm8);
4068 }
4069
4070 void Assembler::shrl(Register dst) {
4071 int encode = prefix_and_encode(dst->encoding());
4072 emit_int8((unsigned char)0xD3);
4073 emit_int8((unsigned char)(0xE8 | encode));
4074 }
4075
4076 // copies a single word from [esi] to [edi]
4077 void Assembler::smovl() {
4078 emit_int8((unsigned char)0xA5);
4079 }
4080
4081 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4082 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4083 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4084 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4085 emit_int8(0x51);
4086 emit_int8((unsigned char)(0xC0 | encode));
4087 }
4088
4089 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4091 InstructionMark im(this);
4092 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4093 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4094 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4095 emit_int8(0x51);
4096 emit_operand(dst, src);
4097 }
4098
4099 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4100 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4101 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4102 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4103 emit_int8(0x51);
4104 emit_int8((unsigned char)(0xC0 | encode));
4105 }
4106
4107 void Assembler::std() {
4108 emit_int8((unsigned char)0xFD);
4109 }
4110
4111 void Assembler::sqrtss(XMMRegister dst, Address src) {
4112 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4113 InstructionMark im(this);
4114 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4115 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4116 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4117 emit_int8(0x51);
4118 emit_operand(dst, src);
4119 }
4120
4121 void Assembler::stmxcsr( Address dst) {
4122 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4123 InstructionMark im(this);
4124 prefix(dst);
4125 emit_int8(0x0F);
4126 emit_int8((unsigned char)0xAE);
4127 emit_operand(as_Register(3), dst);
4128 }
4129
4130 void Assembler::subl(Address dst, int32_t imm32) {
4131 InstructionMark im(this);
4132 prefix(dst);
4133 emit_arith_operand(0x81, rbp, dst, imm32);
4134 }
4135
4136 void Assembler::subl(Address dst, Register src) {
4137 InstructionMark im(this);
4138 prefix(dst, src);
4139 emit_int8(0x29);
4140 emit_operand(src, dst);
4141 }
4142
4143 void Assembler::subl(Register dst, int32_t imm32) {
4144 prefix(dst);
4145 emit_arith(0x81, 0xE8, dst, imm32);
4146 }
4147
4148 // Force generation of a 4 byte immediate value even if it fits into 8bit
4149 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4150 prefix(dst);
4151 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4152 }
4153
4154 void Assembler::subl(Register dst, Address src) {
4155 InstructionMark im(this);
4156 prefix(src, dst);
4157 emit_int8(0x2B);
4158 emit_operand(dst, src);
4159 }
4160
4161 void Assembler::subl(Register dst, Register src) {
4162 (void) prefix_and_encode(dst->encoding(), src->encoding());
4163 emit_arith(0x2B, 0xC0, dst, src);
4164 }
4165
4166 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4167 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4168 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4169 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4170 emit_int8(0x5C);
4171 emit_int8((unsigned char)(0xC0 | encode));
4172 }
4173
4174 void Assembler::subsd(XMMRegister dst, Address src) {
4175 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4176 InstructionMark im(this);
4177 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4178 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4179 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4180 emit_int8(0x5C);
4181 emit_operand(dst, src);
4182 }
4183
4184 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4185 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4186 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false);
4187 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4188 emit_int8(0x5C);
4189 emit_int8((unsigned char)(0xC0 | encode));
4190 }
4191
4192 void Assembler::subss(XMMRegister dst, Address src) {
4193 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4194 InstructionMark im(this);
4195 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4196 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4197 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4198 emit_int8(0x5C);
4199 emit_operand(dst, src);
4200 }
4201
4202 void Assembler::testb(Register dst, int imm8) {
4203 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4204 (void) prefix_and_encode(dst->encoding(), true);
4205 emit_arith_b(0xF6, 0xC0, dst, imm8);
4206 }
4207
4208 void Assembler::testb(Address dst, int imm8) {
4209 InstructionMark im(this);
4210 prefix(dst);
4211 emit_int8((unsigned char)0xF6);
4212 emit_operand(rax, dst, 1);
4213 emit_int8(imm8);
4214 }
4215
4216 void Assembler::testl(Register dst, int32_t imm32) {
4217 // not using emit_arith because test
4218 // doesn't support sign-extension of
4219 // 8bit operands
4220 int encode = dst->encoding();
4221 if (encode == 0) {
4222 emit_int8((unsigned char)0xA9);
4223 } else {
4224 encode = prefix_and_encode(encode);
4225 emit_int8((unsigned char)0xF7);
4226 emit_int8((unsigned char)(0xC0 | encode));
4227 }
4228 emit_int32(imm32);
4229 }
4230
4231 void Assembler::testl(Register dst, Register src) {
4232 (void) prefix_and_encode(dst->encoding(), src->encoding());
4233 emit_arith(0x85, 0xC0, dst, src);
4234 }
4235
4236 void Assembler::testl(Register dst, Address src) {
4237 InstructionMark im(this);
4238 prefix(src, dst);
4239 emit_int8((unsigned char)0x85);
4240 emit_operand(dst, src);
4241 }
4242
4243 void Assembler::tzcntl(Register dst, Register src) {
4244 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4245 emit_int8((unsigned char)0xF3);
4246 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4247 emit_int8(0x0F);
4248 emit_int8((unsigned char)0xBC);
4249 emit_int8((unsigned char)0xC0 | encode);
4250 }
4251
4252 void Assembler::tzcntq(Register dst, Register src) {
4253 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4254 emit_int8((unsigned char)0xF3);
4255 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4256 emit_int8(0x0F);
4257 emit_int8((unsigned char)0xBC);
4258 emit_int8((unsigned char)(0xC0 | encode));
4259 }
4260
4261 void Assembler::ucomisd(XMMRegister dst, Address src) {
4262 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4263 InstructionMark im(this);
4264 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4265 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4266 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4267 emit_int8(0x2E);
4268 emit_operand(dst, src);
4269 }
4270
4271 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4272 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4273 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4274 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4275 emit_int8(0x2E);
4276 emit_int8((unsigned char)(0xC0 | encode));
4277 }
4278
4279 void Assembler::ucomiss(XMMRegister dst, Address src) {
4280 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4281 InstructionMark im(this);
4282 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4283 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4284 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4285 emit_int8(0x2E);
4286 emit_operand(dst, src);
4287 }
4288
4289 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
4290 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4291 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4292 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4293 emit_int8(0x2E);
4294 emit_int8((unsigned char)(0xC0 | encode));
4295 }
4296
4297 void Assembler::xabort(int8_t imm8) {
4298 emit_int8((unsigned char)0xC6);
4299 emit_int8((unsigned char)0xF8);
4300 emit_int8((unsigned char)(imm8 & 0xFF));
4301 }
4302
4303 void Assembler::xaddl(Address dst, Register src) {
4304 InstructionMark im(this);
4305 prefix(dst, src);
4306 emit_int8(0x0F);
4307 emit_int8((unsigned char)0xC1);
4308 emit_operand(src, dst);
4309 }
4310
4311 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
4312 InstructionMark im(this);
4313 relocate(rtype);
4314 if (abort.is_bound()) {
4315 address entry = target(abort);
4316 assert(entry != NULL, "abort entry NULL");
4317 intptr_t offset = entry - pc();
4318 emit_int8((unsigned char)0xC7);
4319 emit_int8((unsigned char)0xF8);
4320 emit_int32(offset - 6); // 2 opcode + 4 address
4321 } else {
4322 abort.add_patch_at(code(), locator());
4323 emit_int8((unsigned char)0xC7);
4324 emit_int8((unsigned char)0xF8);
4325 emit_int32(0);
4326 }
4327 }
4328
4329 void Assembler::xchgl(Register dst, Address src) { // xchg
4330 InstructionMark im(this);
4331 prefix(src, dst);
4332 emit_int8((unsigned char)0x87);
4333 emit_operand(dst, src);
4334 }
4335
4336 void Assembler::xchgl(Register dst, Register src) {
4337 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4338 emit_int8((unsigned char)0x87);
4339 emit_int8((unsigned char)(0xC0 | encode));
4340 }
4341
4342 void Assembler::xend() {
4343 emit_int8((unsigned char)0x0F);
4344 emit_int8((unsigned char)0x01);
4345 emit_int8((unsigned char)0xD5);
4346 }
4347
4348 void Assembler::xgetbv() {
4349 emit_int8(0x0F);
4350 emit_int8(0x01);
4351 emit_int8((unsigned char)0xD0);
4352 }
4353
4354 void Assembler::xorl(Register dst, int32_t imm32) {
4355 prefix(dst);
4356 emit_arith(0x81, 0xF0, dst, imm32);
4357 }
4358
4359 void Assembler::xorl(Register dst, Address src) {
4360 InstructionMark im(this);
4361 prefix(src, dst);
4362 emit_int8(0x33);
4363 emit_operand(dst, src);
4364 }
4365
4366 void Assembler::xorl(Register dst, Register src) {
4367 (void) prefix_and_encode(dst->encoding(), src->encoding());
4368 emit_arith(0x33, 0xC0, dst, src);
4369 }
4370
4371 void Assembler::xorb(Register dst, Address src) {
4372 InstructionMark im(this);
4373 prefix(src, dst);
4374 emit_int8(0x32);
4375 emit_operand(dst, src);
4376 }
4377
4378 // AVX 3-operands scalar float-point arithmetic instructions
4379
4380 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
4381 assert(VM_Version::supports_avx(), "");
4382 InstructionMark im(this);
4383 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4384 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4385 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4386 emit_int8(0x58);
4387 emit_operand(dst, src);
4388 }
4389
4390 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4391 assert(VM_Version::supports_avx(), "");
4392 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4393 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4394 emit_int8(0x58);
4395 emit_int8((unsigned char)(0xC0 | encode));
4396 }
4397
4398 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
4399 assert(VM_Version::supports_avx(), "");
4400 InstructionMark im(this);
4401 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4402 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4403 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4404 emit_int8(0x58);
4405 emit_operand(dst, src);
4406 }
4407
4408 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4409 assert(VM_Version::supports_avx(), "");
4410 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4411 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4412 emit_int8(0x58);
4413 emit_int8((unsigned char)(0xC0 | encode));
4414 }
4415
4416 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
4417 assert(VM_Version::supports_avx(), "");
4418 InstructionMark im(this);
4419 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4420 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4421 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4422 emit_int8(0x5E);
4423 emit_operand(dst, src);
4424 }
4425
4426 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4427 assert(VM_Version::supports_avx(), "");
4428 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4429 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4430 emit_int8(0x5E);
4431 emit_int8((unsigned char)(0xC0 | encode));
4432 }
4433
4434 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
4435 assert(VM_Version::supports_avx(), "");
4436 InstructionMark im(this);
4437 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4438 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4439 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4440 emit_int8(0x5E);
4441 emit_operand(dst, src);
4442 }
4443
4444 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4445 assert(VM_Version::supports_avx(), "");
4446 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4447 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4448 emit_int8(0x5E);
4449 emit_int8((unsigned char)(0xC0 | encode));
4450 }
4451
4452 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
4453 assert(VM_Version::supports_avx(), "");
4454 InstructionMark im(this);
4455 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4456 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4457 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4458 emit_int8(0x59);
4459 emit_operand(dst, src);
4460 }
4461
4462 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4463 assert(VM_Version::supports_avx(), "");
4464 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4465 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4466 emit_int8(0x59);
4467 emit_int8((unsigned char)(0xC0 | encode));
4468 }
4469
4470 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
4471 assert(VM_Version::supports_avx(), "");
4472 InstructionMark im(this);
4473 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4474 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4475 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4476 emit_int8(0x59);
4477 emit_operand(dst, src);
4478 }
4479
4480 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4481 assert(VM_Version::supports_avx(), "");
4482 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4483 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4484 emit_int8(0x59);
4485 emit_int8((unsigned char)(0xC0 | encode));
4486 }
4487
4488 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
4489 assert(VM_Version::supports_avx(), "");
4490 InstructionMark im(this);
4491 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4492 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4493 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4494 emit_int8(0x5C);
4495 emit_operand(dst, src);
4496 }
4497
4498 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4499 assert(VM_Version::supports_avx(), "");
4500 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4501 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4502 emit_int8(0x5C);
4503 emit_int8((unsigned char)(0xC0 | encode));
4504 }
4505
4506 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
4507 assert(VM_Version::supports_avx(), "");
4508 InstructionMark im(this);
4509 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4510 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4511 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4512 emit_int8(0x5C);
4513 emit_operand(dst, src);
4514 }
4515
4516 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
4517 assert(VM_Version::supports_avx(), "");
4518 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4519 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4520 emit_int8(0x5C);
4521 emit_int8((unsigned char)(0xC0 | encode));
4522 }
4523
4524 //====================VECTOR ARITHMETIC=====================================
4525
4526 // Float-point vector arithmetic
4527
4528 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
4529 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4530 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4531 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4532 emit_int8(0x58);
4533 emit_int8((unsigned char)(0xC0 | encode));
4534 }
4535
4536 void Assembler::addpd(XMMRegister dst, Address src) {
4537 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4538 InstructionMark im(this);
4539 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4540 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4541 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4542 emit_int8(0x58);
4543 emit_operand(dst, src);
4544 }
4545
4546
4547 void Assembler::addps(XMMRegister dst, XMMRegister src) {
4548 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4549 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4550 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4551 emit_int8(0x58);
4552 emit_int8((unsigned char)(0xC0 | encode));
4553 }
4554
4555 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4556 assert(VM_Version::supports_avx(), "");
4557 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4558 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4559 emit_int8(0x58);
4560 emit_int8((unsigned char)(0xC0 | encode));
4561 }
4562
4563 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4564 assert(VM_Version::supports_avx(), "");
4565 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4566 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4567 emit_int8(0x58);
4568 emit_int8((unsigned char)(0xC0 | encode));
4569 }
4570
4571 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4572 assert(VM_Version::supports_avx(), "");
4573 InstructionMark im(this);
4574 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4575 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4576 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4577 emit_int8(0x58);
4578 emit_operand(dst, src);
4579 }
4580
4581 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4582 assert(VM_Version::supports_avx(), "");
4583 InstructionMark im(this);
4584 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4585 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4586 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4587 emit_int8(0x58);
4588 emit_operand(dst, src);
4589 }
4590
4591 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
4592 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4593 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4594 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4595 emit_int8(0x5C);
4596 emit_int8((unsigned char)(0xC0 | encode));
4597 }
4598
4599 void Assembler::subps(XMMRegister dst, XMMRegister src) {
4600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4601 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4602 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4603 emit_int8(0x5C);
4604 emit_int8((unsigned char)(0xC0 | encode));
4605 }
4606
4607 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4608 assert(VM_Version::supports_avx(), "");
4609 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4610 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4611 emit_int8(0x5C);
4612 emit_int8((unsigned char)(0xC0 | encode));
4613 }
4614
4615 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4616 assert(VM_Version::supports_avx(), "");
4617 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4618 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4619 emit_int8(0x5C);
4620 emit_int8((unsigned char)(0xC0 | encode));
4621 }
4622
4623 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4624 assert(VM_Version::supports_avx(), "");
4625 InstructionMark im(this);
4626 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4627 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4628 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4629 emit_int8(0x5C);
4630 emit_operand(dst, src);
4631 }
4632
4633 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4634 assert(VM_Version::supports_avx(), "");
4635 InstructionMark im(this);
4636 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4637 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4638 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4639 emit_int8(0x5C);
4640 emit_operand(dst, src);
4641 }
4642
4643 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
4644 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4645 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4646 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4647 emit_int8(0x59);
4648 emit_int8((unsigned char)(0xC0 | encode));
4649 }
4650
4651 void Assembler::mulpd(XMMRegister dst, Address src) {
4652 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4653 InstructionMark im(this);
4654 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4655 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4656 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4657 emit_int8(0x59);
4658 emit_operand(dst, src);
4659 }
4660
4661 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
4662 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4663 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4664 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4665 emit_int8(0x59);
4666 emit_int8((unsigned char)(0xC0 | encode));
4667 }
4668
4669 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4670 assert(VM_Version::supports_avx(), "");
4671 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4672 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4673 emit_int8(0x59);
4674 emit_int8((unsigned char)(0xC0 | encode));
4675 }
4676
4677 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4678 assert(VM_Version::supports_avx(), "");
4679 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4680 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4681 emit_int8(0x59);
4682 emit_int8((unsigned char)(0xC0 | encode));
4683 }
4684
4685 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4686 assert(VM_Version::supports_avx(), "");
4687 InstructionMark im(this);
4688 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4689 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4690 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4691 emit_int8(0x59);
4692 emit_operand(dst, src);
4693 }
4694
4695 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4696 assert(VM_Version::supports_avx(), "");
4697 InstructionMark im(this);
4698 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4699 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4700 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4701 emit_int8(0x59);
4702 emit_operand(dst, src);
4703 }
4704
4705 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
4706 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4707 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4708 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4709 emit_int8(0x5E);
4710 emit_int8((unsigned char)(0xC0 | encode));
4711 }
4712
4713 void Assembler::divps(XMMRegister dst, XMMRegister src) {
4714 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4715 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4716 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4717 emit_int8(0x5E);
4718 emit_int8((unsigned char)(0xC0 | encode));
4719 }
4720
4721 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4722 assert(VM_Version::supports_avx(), "");
4723 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4724 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4725 emit_int8(0x5E);
4726 emit_int8((unsigned char)(0xC0 | encode));
4727 }
4728
4729 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4730 assert(VM_Version::supports_avx(), "");
4731 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4732 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4733 emit_int8(0x5E);
4734 emit_int8((unsigned char)(0xC0 | encode));
4735 }
4736
4737 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4738 assert(VM_Version::supports_avx(), "");
4739 InstructionMark im(this);
4740 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4741 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4742 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4743 emit_int8(0x5E);
4744 emit_operand(dst, src);
4745 }
4746
4747 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4748 assert(VM_Version::supports_avx(), "");
4749 InstructionMark im(this);
4750 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4751 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4752 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4753 emit_int8(0x5E);
4754 emit_operand(dst, src);
4755 }
4756
4757 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
4758 assert(VM_Version::supports_avx(), "");
4759 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4760 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4761 emit_int8(0x51);
4762 emit_int8((unsigned char)(0xC0 | encode));
4763 }
4764
4765 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
4766 assert(VM_Version::supports_avx(), "");
4767 InstructionMark im(this);
4768 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4769 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4770 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4771 emit_int8(0x51);
4772 emit_operand(dst, src);
4773 }
4774
4775 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
4776 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4777 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4778 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4779 emit_int8(0x54);
4780 emit_int8((unsigned char)(0xC0 | encode));
4781 }
4782
4783 void Assembler::andps(XMMRegister dst, XMMRegister src) {
4784 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4785 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4786 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4787 emit_int8(0x54);
4788 emit_int8((unsigned char)(0xC0 | encode));
4789 }
4790
4791 void Assembler::andps(XMMRegister dst, Address src) {
4792 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4793 InstructionMark im(this);
4794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4795 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4796 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4797 emit_int8(0x54);
4798 emit_operand(dst, src);
4799 }
4800
4801 void Assembler::andpd(XMMRegister dst, Address src) {
4802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4803 InstructionMark im(this);
4804 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4805 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4806 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4807 emit_int8(0x54);
4808 emit_operand(dst, src);
4809 }
4810
4811 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4812 assert(VM_Version::supports_avx(), "");
4813 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4814 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4815 emit_int8(0x54);
4816 emit_int8((unsigned char)(0xC0 | encode));
4817 }
4818
4819 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4820 assert(VM_Version::supports_avx(), "");
4821 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4822 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4823 emit_int8(0x54);
4824 emit_int8((unsigned char)(0xC0 | encode));
4825 }
4826
4827 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4828 assert(VM_Version::supports_avx(), "");
4829 InstructionMark im(this);
4830 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4831 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4832 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4833 emit_int8(0x54);
4834 emit_operand(dst, src);
4835 }
4836
4837 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4838 assert(VM_Version::supports_avx(), "");
4839 InstructionMark im(this);
4840 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4841 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4842 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4843 emit_int8(0x54);
4844 emit_operand(dst, src);
4845 }
4846
4847 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
4848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4849 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4850 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4851 emit_int8(0x15);
4852 emit_int8((unsigned char)(0xC0 | encode));
4853 }
4854
4855 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
4856 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4857 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4858 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4859 emit_int8(0x14);
4860 emit_int8((unsigned char)(0xC0 | encode));
4861 }
4862
4863 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
4864 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4865 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4866 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4867 emit_int8(0x57);
4868 emit_int8((unsigned char)(0xC0 | encode));
4869 }
4870
4871 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
4872 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4873 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4874 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4875 emit_int8(0x57);
4876 emit_int8((unsigned char)(0xC0 | encode));
4877 }
4878
4879 void Assembler::xorpd(XMMRegister dst, Address src) {
4880 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4881 InstructionMark im(this);
4882 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4883 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4884 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4885 emit_int8(0x57);
4886 emit_operand(dst, src);
4887 }
4888
4889 void Assembler::xorps(XMMRegister dst, Address src) {
4890 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4891 InstructionMark im(this);
4892 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4893 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4894 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4895 emit_int8(0x57);
4896 emit_operand(dst, src);
4897 }
4898
4899 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4900 assert(VM_Version::supports_avx(), "");
4901 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4902 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4903 emit_int8(0x57);
4904 emit_int8((unsigned char)(0xC0 | encode));
4905 }
4906
4907 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4908 assert(VM_Version::supports_avx(), "");
4909 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4910 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4911 emit_int8(0x57);
4912 emit_int8((unsigned char)(0xC0 | encode));
4913 }
4914
4915 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4916 assert(VM_Version::supports_avx(), "");
4917 InstructionMark im(this);
4918 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4919 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4920 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4921 emit_int8(0x57);
4922 emit_operand(dst, src);
4923 }
4924
4925 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4926 assert(VM_Version::supports_avx(), "");
4927 InstructionMark im(this);
4928 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
4929 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4930 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4931 emit_int8(0x57);
4932 emit_operand(dst, src);
4933 }
4934
4935 // Integer vector arithmetic
4936 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4937 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4938 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4939 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4940 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4941 emit_int8(0x01);
4942 emit_int8((unsigned char)(0xC0 | encode));
4943 }
4944
4945 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4946 assert(VM_Version::supports_avx() && (vector_len == 0) ||
4947 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
4948 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4949 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4950 emit_int8(0x02);
4951 emit_int8((unsigned char)(0xC0 | encode));
4952 }
4953
4954 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
4955 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4956 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4957 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4958 emit_int8((unsigned char)0xFC);
4959 emit_int8((unsigned char)(0xC0 | encode));
4960 }
4961
4962 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
4963 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4964 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4965 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4966 emit_int8((unsigned char)0xFD);
4967 emit_int8((unsigned char)(0xC0 | encode));
4968 }
4969
4970 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
4971 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4972 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4973 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4974 emit_int8((unsigned char)0xFE);
4975 emit_int8((unsigned char)(0xC0 | encode));
4976 }
4977
4978 void Assembler::paddd(XMMRegister dst, Address src) {
4979 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4980 InstructionMark im(this);
4981 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4982 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4983 emit_int8((unsigned char)0xFE);
4984 emit_operand(dst, src);
4985 }
4986
4987 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
4988 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4989 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4990 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4991 emit_int8((unsigned char)0xD4);
4992 emit_int8((unsigned char)(0xC0 | encode));
4993 }
4994
4995 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
4996 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
4997 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4998 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4999 emit_int8(0x01);
5000 emit_int8((unsigned char)(0xC0 | encode));
5001 }
5002
5003 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5004 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
5005 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5006 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5007 emit_int8(0x02);
5008 emit_int8((unsigned char)(0xC0 | encode));
5009 }
5010
5011 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5012 assert(UseAVX > 0, "requires some form of AVX");
5013 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5014 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5015 emit_int8((unsigned char)0xFC);
5016 emit_int8((unsigned char)(0xC0 | encode));
5017 }
5018
5019 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5020 assert(UseAVX > 0, "requires some form of AVX");
5021 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5022 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5023 emit_int8((unsigned char)0xFD);
5024 emit_int8((unsigned char)(0xC0 | encode));
5025 }
5026
5027 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5028 assert(UseAVX > 0, "requires some form of AVX");
5029 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5030 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5031 emit_int8((unsigned char)0xFE);
5032 emit_int8((unsigned char)(0xC0 | encode));
5033 }
5034
5035 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5036 assert(UseAVX > 0, "requires some form of AVX");
5037 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5038 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5039 emit_int8((unsigned char)0xD4);
5040 emit_int8((unsigned char)(0xC0 | encode));
5041 }
5042
5043 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5044 assert(UseAVX > 0, "requires some form of AVX");
5045 InstructionMark im(this);
5046 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5047 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5048 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5049 emit_int8((unsigned char)0xFC);
5050 emit_operand(dst, src);
5051 }
5052
5053 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5054 assert(UseAVX > 0, "requires some form of AVX");
5055 InstructionMark im(this);
5056 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5057 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5058 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5059 emit_int8((unsigned char)0xFD);
5060 emit_operand(dst, src);
5061 }
5062
5063 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5064 assert(UseAVX > 0, "requires some form of AVX");
5065 InstructionMark im(this);
5066 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5067 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5068 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5069 emit_int8((unsigned char)0xFE);
5070 emit_operand(dst, src);
5071 }
5072
5073 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5074 assert(UseAVX > 0, "requires some form of AVX");
5075 InstructionMark im(this);
5076 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5077 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5078 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5079 emit_int8((unsigned char)0xD4);
5080 emit_operand(dst, src);
5081 }
5082
5083 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5085 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5086 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5087 emit_int8((unsigned char)0xF8);
5088 emit_int8((unsigned char)(0xC0 | encode));
5089 }
5090
5091 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5092 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5093 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5094 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5095 emit_int8((unsigned char)0xF9);
5096 emit_int8((unsigned char)(0xC0 | encode));
5097 }
5098
5099 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5100 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5101 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5102 emit_int8((unsigned char)0xFA);
5103 emit_int8((unsigned char)(0xC0 | encode));
5104 }
5105
5106 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5107 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5108 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5109 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5110 emit_int8((unsigned char)0xFB);
5111 emit_int8((unsigned char)(0xC0 | encode));
5112 }
5113
5114 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5115 assert(UseAVX > 0, "requires some form of AVX");
5116 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5117 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5118 emit_int8((unsigned char)0xF8);
5119 emit_int8((unsigned char)(0xC0 | encode));
5120 }
5121
5122 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5123 assert(UseAVX > 0, "requires some form of AVX");
5124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5125 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5126 emit_int8((unsigned char)0xF9);
5127 emit_int8((unsigned char)(0xC0 | encode));
5128 }
5129
5130 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5131 assert(UseAVX > 0, "requires some form of AVX");
5132 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5133 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5134 emit_int8((unsigned char)0xFA);
5135 emit_int8((unsigned char)(0xC0 | encode));
5136 }
5137
5138 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5139 assert(UseAVX > 0, "requires some form of AVX");
5140 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5141 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5142 emit_int8((unsigned char)0xFB);
5143 emit_int8((unsigned char)(0xC0 | encode));
5144 }
5145
5146 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5147 assert(UseAVX > 0, "requires some form of AVX");
5148 InstructionMark im(this);
5149 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5150 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5151 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5152 emit_int8((unsigned char)0xF8);
5153 emit_operand(dst, src);
5154 }
5155
5156 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5157 assert(UseAVX > 0, "requires some form of AVX");
5158 InstructionMark im(this);
5159 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5160 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5161 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5162 emit_int8((unsigned char)0xF9);
5163 emit_operand(dst, src);
5164 }
5165
5166 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5167 assert(UseAVX > 0, "requires some form of AVX");
5168 InstructionMark im(this);
5169 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5170 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5171 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5172 emit_int8((unsigned char)0xFA);
5173 emit_operand(dst, src);
5174 }
5175
5176 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5177 assert(UseAVX > 0, "requires some form of AVX");
5178 InstructionMark im(this);
5179 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5180 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5181 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5182 emit_int8((unsigned char)0xFB);
5183 emit_operand(dst, src);
5184 }
5185
5186 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
5187 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5188 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5189 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5190 emit_int8((unsigned char)0xD5);
5191 emit_int8((unsigned char)(0xC0 | encode));
5192 }
5193
5194 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
5195 assert(VM_Version::supports_sse4_1(), "");
5196 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5197 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5198 emit_int8(0x40);
5199 emit_int8((unsigned char)(0xC0 | encode));
5200 }
5201
5202 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5203 assert(UseAVX > 0, "requires some form of AVX");
5204 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5205 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5206 emit_int8((unsigned char)0xD5);
5207 emit_int8((unsigned char)(0xC0 | encode));
5208 }
5209
5210 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5211 assert(UseAVX > 0, "requires some form of AVX");
5212 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5213 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5214 emit_int8(0x40);
5215 emit_int8((unsigned char)(0xC0 | encode));
5216 }
5217
5218 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5219 assert(UseAVX > 2, "requires some form of AVX");
5220 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5221 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5222 emit_int8(0x40);
5223 emit_int8((unsigned char)(0xC0 | encode));
5224 }
5225
5226 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5227 assert(UseAVX > 0, "requires some form of AVX");
5228 InstructionMark im(this);
5229 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5230 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5231 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5232 emit_int8((unsigned char)0xD5);
5233 emit_operand(dst, src);
5234 }
5235
5236 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5237 assert(UseAVX > 0, "requires some form of AVX");
5238 InstructionMark im(this);
5239 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5240 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5241 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5242 emit_int8(0x40);
5243 emit_operand(dst, src);
5244 }
5245
5246 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5247 assert(UseAVX > 0, "requires some form of AVX");
5248 InstructionMark im(this);
5249 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5250 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5251 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5252 emit_int8(0x40);
5253 emit_operand(dst, src);
5254 }
5255
5256 // Shift packed integers left by specified number of bits.
5257 void Assembler::psllw(XMMRegister dst, int shift) {
5258 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5259 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5260 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5261 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5262 emit_int8(0x71);
5263 emit_int8((unsigned char)(0xC0 | encode));
5264 emit_int8(shift & 0xFF);
5265 }
5266
5267 void Assembler::pslld(XMMRegister dst, int shift) {
5268 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5270 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5271 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5272 emit_int8(0x72);
5273 emit_int8((unsigned char)(0xC0 | encode));
5274 emit_int8(shift & 0xFF);
5275 }
5276
5277 void Assembler::psllq(XMMRegister dst, int shift) {
5278 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5279 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5280 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5281 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5282 emit_int8(0x73);
5283 emit_int8((unsigned char)(0xC0 | encode));
5284 emit_int8(shift & 0xFF);
5285 }
5286
5287 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
5288 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5290 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5291 emit_int8((unsigned char)0xF1);
5292 emit_int8((unsigned char)(0xC0 | encode));
5293 }
5294
5295 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
5296 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5297 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5298 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5299 emit_int8((unsigned char)0xF2);
5300 emit_int8((unsigned char)(0xC0 | encode));
5301 }
5302
5303 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
5304 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5305 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5306 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5307 emit_int8((unsigned char)0xF3);
5308 emit_int8((unsigned char)(0xC0 | encode));
5309 }
5310
5311 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5312 assert(UseAVX > 0, "requires some form of AVX");
5313 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5314 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
5315 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5316 emit_int8(0x71);
5317 emit_int8((unsigned char)(0xC0 | encode));
5318 emit_int8(shift & 0xFF);
5319 }
5320
5321 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5322 assert(UseAVX > 0, "requires some form of AVX");
5323 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5324 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5325 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
5326 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5327 emit_int8(0x72);
5328 emit_int8((unsigned char)(0xC0 | encode));
5329 emit_int8(shift & 0xFF);
5330 }
5331
5332 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5333 assert(UseAVX > 0, "requires some form of AVX");
5334 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5335 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
5336 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5337 emit_int8(0x73);
5338 emit_int8((unsigned char)(0xC0 | encode));
5339 emit_int8(shift & 0xFF);
5340 }
5341
5342 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5343 assert(UseAVX > 0, "requires some form of AVX");
5344 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5345 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5346 emit_int8((unsigned char)0xF1);
5347 emit_int8((unsigned char)(0xC0 | encode));
5348 }
5349
5350 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5351 assert(UseAVX > 0, "requires some form of AVX");
5352 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5353 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5354 emit_int8((unsigned char)0xF2);
5355 emit_int8((unsigned char)(0xC0 | encode));
5356 }
5357
5358 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5359 assert(UseAVX > 0, "requires some form of AVX");
5360 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5361 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5362 emit_int8((unsigned char)0xF3);
5363 emit_int8((unsigned char)(0xC0 | encode));
5364 }
5365
5366 // Shift packed integers logically right by specified number of bits.
5367 void Assembler::psrlw(XMMRegister dst, int shift) {
5368 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5369 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5370 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5371 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5372 emit_int8(0x71);
5373 emit_int8((unsigned char)(0xC0 | encode));
5374 emit_int8(shift & 0xFF);
5375 }
5376
5377 void Assembler::psrld(XMMRegister dst, int shift) {
5378 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5379 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5380 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5381 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5382 emit_int8(0x72);
5383 emit_int8((unsigned char)(0xC0 | encode));
5384 emit_int8(shift & 0xFF);
5385 }
5386
5387 void Assembler::psrlq(XMMRegister dst, int shift) {
5388 // Do not confuse it with psrldq SSE2 instruction which
5389 // shifts 128 bit value in xmm register by number of bytes.
5390 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5391 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5392 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5393 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5394 emit_int8(0x73);
5395 emit_int8((unsigned char)(0xC0 | encode));
5396 emit_int8(shift & 0xFF);
5397 }
5398
5399 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
5400 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5401 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5402 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5403 emit_int8((unsigned char)0xD1);
5404 emit_int8((unsigned char)(0xC0 | encode));
5405 }
5406
5407 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
5408 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5409 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5410 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5411 emit_int8((unsigned char)0xD2);
5412 emit_int8((unsigned char)(0xC0 | encode));
5413 }
5414
5415 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
5416 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5417 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5418 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5419 emit_int8((unsigned char)0xD3);
5420 emit_int8((unsigned char)(0xC0 | encode));
5421 }
5422
5423 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5424 assert(UseAVX > 0, "requires some form of AVX");
5425 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5426 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
5427 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5428 emit_int8(0x71);
5429 emit_int8((unsigned char)(0xC0 | encode));
5430 emit_int8(shift & 0xFF);
5431 }
5432
5433 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5434 assert(UseAVX > 0, "requires some form of AVX");
5435 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5436 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
5437 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5438 emit_int8(0x72);
5439 emit_int8((unsigned char)(0xC0 | encode));
5440 emit_int8(shift & 0xFF);
5441 }
5442
5443 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5444 assert(UseAVX > 0, "requires some form of AVX");
5445 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5446 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
5447 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5448 emit_int8(0x73);
5449 emit_int8((unsigned char)(0xC0 | encode));
5450 emit_int8(shift & 0xFF);
5451 }
5452
5453 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5454 assert(UseAVX > 0, "requires some form of AVX");
5455 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5456 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5457 emit_int8((unsigned char)0xD1);
5458 emit_int8((unsigned char)(0xC0 | encode));
5459 }
5460
5461 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5462 assert(UseAVX > 0, "requires some form of AVX");
5463 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5464 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5465 emit_int8((unsigned char)0xD2);
5466 emit_int8((unsigned char)(0xC0 | encode));
5467 }
5468
5469 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5470 assert(UseAVX > 0, "requires some form of AVX");
5471 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5472 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5473 emit_int8((unsigned char)0xD3);
5474 emit_int8((unsigned char)(0xC0 | encode));
5475 }
5476
5477 // Shift packed integers arithmetically right by specified number of bits.
5478 void Assembler::psraw(XMMRegister dst, int shift) {
5479 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5480 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5481 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5482 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5483 emit_int8(0x71);
5484 emit_int8((unsigned char)(0xC0 | encode));
5485 emit_int8(shift & 0xFF);
5486 }
5487
5488 void Assembler::psrad(XMMRegister dst, int shift) {
5489 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5490 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5491 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
5492 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5493 emit_int8(0x72);
5494 emit_int8((unsigned char)(0xC0 | encode));
5495 emit_int8(shift & 0xFF);
5496 }
5497
5498 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
5499 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5500 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5501 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5502 emit_int8((unsigned char)0xE1);
5503 emit_int8((unsigned char)(0xC0 | encode));
5504 }
5505
5506 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
5507 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5508 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5509 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5510 emit_int8((unsigned char)0xE2);
5511 emit_int8((unsigned char)(0xC0 | encode));
5512 }
5513
5514 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5515 assert(UseAVX > 0, "requires some form of AVX");
5516 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5517 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5518 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5519 emit_int8(0x71);
5520 emit_int8((unsigned char)(0xC0 | encode));
5521 emit_int8(shift & 0xFF);
5522 }
5523
5524 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5525 assert(UseAVX > 0, "requires some form of AVX");
5526 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5527 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
5528 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5529 emit_int8(0x72);
5530 emit_int8((unsigned char)(0xC0 | encode));
5531 emit_int8(shift & 0xFF);
5532 }
5533
5534 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5535 assert(UseAVX > 0, "requires some form of AVX");
5536 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5537 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5538 emit_int8((unsigned char)0xE1);
5539 emit_int8((unsigned char)(0xC0 | encode));
5540 }
5541
5542 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
5543 assert(UseAVX > 0, "requires some form of AVX");
5544 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5545 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5546 emit_int8((unsigned char)0xE2);
5547 emit_int8((unsigned char)(0xC0 | encode));
5548 }
5549
5550
5551 // logical operations packed integers
5552 void Assembler::pand(XMMRegister dst, XMMRegister src) {
5553 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5554 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5555 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5556 emit_int8((unsigned char)0xDB);
5557 emit_int8((unsigned char)(0xC0 | encode));
5558 }
5559
5560 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5561 assert(UseAVX > 0, "requires some form of AVX");
5562 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5563 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5564 emit_int8((unsigned char)0xDB);
5565 emit_int8((unsigned char)(0xC0 | encode));
5566 }
5567
5568 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5569 assert(UseAVX > 0, "requires some form of AVX");
5570 InstructionMark im(this);
5571 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5572 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5573 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5574 emit_int8((unsigned char)0xDB);
5575 emit_operand(dst, src);
5576 }
5577
5578 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
5579 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5580 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5581 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5582 emit_int8((unsigned char)0xDF);
5583 emit_int8((unsigned char)(0xC0 | encode));
5584 }
5585
5586 void Assembler::por(XMMRegister dst, XMMRegister src) {
5587 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5588 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5589 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5590 emit_int8((unsigned char)0xEB);
5591 emit_int8((unsigned char)(0xC0 | encode));
5592 }
5593
5594 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5595 assert(UseAVX > 0, "requires some form of AVX");
5596 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5597 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5598 emit_int8((unsigned char)0xEB);
5599 emit_int8((unsigned char)(0xC0 | encode));
5600 }
5601
5602 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5603 assert(UseAVX > 0, "requires some form of AVX");
5604 InstructionMark im(this);
5605 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5606 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5607 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5608 emit_int8((unsigned char)0xEB);
5609 emit_operand(dst, src);
5610 }
5611
5612 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
5613 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5614 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5615 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5616 emit_int8((unsigned char)0xEF);
5617 emit_int8((unsigned char)(0xC0 | encode));
5618 }
5619
5620 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5621 assert(UseAVX > 0, "requires some form of AVX");
5622 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5623 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5624 emit_int8((unsigned char)0xEF);
5625 emit_int8((unsigned char)(0xC0 | encode));
5626 }
5627
5628 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5629 assert(UseAVX > 0, "requires some form of AVX");
5630 InstructionMark im(this);
5631 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5632 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5633 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5634 emit_int8((unsigned char)0xEF);
5635 emit_operand(dst, src);
5636 }
5637
5638
5639 // vinserti forms
5640
5641 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5642 assert(VM_Version::supports_avx2(), "");
5643 assert(imm8 <= 0x01, "imm8: %u", imm8);
5644 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5645 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5646 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5647 emit_int8(0x38);
5648 emit_int8((unsigned char)(0xC0 | encode));
5649 // 0x00 - insert into lower 128 bits
5650 // 0x01 - insert into upper 128 bits
5651 emit_int8(imm8 & 0x01);
5652 }
5653
5654 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5655 assert(VM_Version::supports_avx2(), "");
5656 assert(dst != xnoreg, "sanity");
5657 assert(imm8 <= 0x01, "imm8: %u", imm8);
5658 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5659 InstructionMark im(this);
5660 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5661 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5662 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5663 emit_int8(0x38);
5664 emit_operand(dst, src);
5665 // 0x00 - insert into lower 128 bits
5666 // 0x01 - insert into upper 128 bits
5667 emit_int8(imm8 & 0x01);
5668 }
5669
5670 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5671 assert(VM_Version::supports_evex(), "");
5672 assert(imm8 <= 0x03, "imm8: %u", imm8);
5673 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5674 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5675 emit_int8(0x38);
5676 emit_int8((unsigned char)(0xC0 | encode));
5677 // 0x00 - insert into q0 128 bits (0..127)
5678 // 0x01 - insert into q1 128 bits (128..255)
5679 // 0x02 - insert into q2 128 bits (256..383)
5680 // 0x03 - insert into q3 128 bits (384..511)
5681 emit_int8(imm8 & 0x03);
5682 }
5683
5684 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5685 assert(VM_Version::supports_avx(), "");
5686 assert(dst != xnoreg, "sanity");
5687 assert(imm8 <= 0x03, "imm8: %u", imm8);
5688 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5689 InstructionMark im(this);
5690 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5691 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5692 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5693 emit_int8(0x18);
5694 emit_operand(dst, src);
5695 // 0x00 - insert into q0 128 bits (0..127)
5696 // 0x01 - insert into q1 128 bits (128..255)
5697 // 0x02 - insert into q2 128 bits (256..383)
5698 // 0x03 - insert into q3 128 bits (384..511)
5699 emit_int8(imm8 & 0x03);
5700 }
5701
5702 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5703 assert(VM_Version::supports_evex(), "");
5704 assert(imm8 <= 0x01, "imm8: %u", imm8);
5705 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5706 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5707 emit_int8(0x38);
5708 emit_int8((unsigned char)(0xC0 | encode));
5709 // 0x00 - insert into lower 256 bits
5710 // 0x01 - insert into upper 256 bits
5711 emit_int8(imm8 & 0x01);
5712 }
5713
5714
5715 // vinsertf forms
5716
5717 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5718 assert(VM_Version::supports_avx(), "");
5719 assert(imm8 <= 0x01, "imm8: %u", imm8);
5720 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5721 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5722 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5723 emit_int8(0x18);
5724 emit_int8((unsigned char)(0xC0 | encode));
5725 // 0x00 - insert into lower 128 bits
5726 // 0x01 - insert into upper 128 bits
5727 emit_int8(imm8 & 0x01);
5728 }
5729
5730 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5731 assert(VM_Version::supports_avx(), "");
5732 assert(dst != xnoreg, "sanity");
5733 assert(imm8 <= 0x01, "imm8: %u", imm8);
5734 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5735 InstructionMark im(this);
5736 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5737 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5738 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5739 emit_int8(0x18);
5740 emit_operand(dst, src);
5741 // 0x00 - insert into lower 128 bits
5742 // 0x01 - insert into upper 128 bits
5743 emit_int8(imm8 & 0x01);
5744 }
5745
5746 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5747 assert(VM_Version::supports_evex(), "");
5748 assert(imm8 <= 0x03, "imm8: %u", imm8);
5749 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5750 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5751 emit_int8(0x18);
5752 emit_int8((unsigned char)(0xC0 | encode));
5753 // 0x00 - insert into q0 128 bits (0..127)
5754 // 0x01 - insert into q1 128 bits (128..255)
5755 // 0x02 - insert into q2 128 bits (256..383)
5756 // 0x03 - insert into q3 128 bits (384..511)
5757 emit_int8(imm8 & 0x03);
5758 }
5759
5760 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5761 assert(VM_Version::supports_avx(), "");
5762 assert(dst != xnoreg, "sanity");
5763 assert(imm8 <= 0x03, "imm8: %u", imm8);
5764 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5765 InstructionMark im(this);
5766 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5767 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5768 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5769 emit_int8(0x18);
5770 emit_operand(dst, src);
5771 // 0x00 - insert into q0 128 bits (0..127)
5772 // 0x01 - insert into q1 128 bits (128..255)
5773 // 0x02 - insert into q2 128 bits (256..383)
5774 // 0x03 - insert into q3 128 bits (384..511)
5775 emit_int8(imm8 & 0x03);
5776 }
5777
5778 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5779 assert(VM_Version::supports_evex(), "");
5780 assert(imm8 <= 0x01, "imm8: %u", imm8);
5781 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5782 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5783 emit_int8(0x1A);
5784 emit_int8((unsigned char)(0xC0 | encode));
5785 // 0x00 - insert into lower 256 bits
5786 // 0x01 - insert into upper 256 bits
5787 emit_int8(imm8 & 0x01);
5788 }
5789
5790 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
5791 assert(VM_Version::supports_evex(), "");
5792 assert(dst != xnoreg, "sanity");
5793 assert(imm8 <= 0x01, "imm8: %u", imm8);
5794 InstructionMark im(this);
5795 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5796 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
5797 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5798 emit_int8(0x1A);
5799 emit_operand(dst, src);
5800 // 0x00 - insert into lower 256 bits
5801 // 0x01 - insert into upper 256 bits
5802 emit_int8(imm8 & 0x01);
5803 }
5804
5805
5806 // vextracti forms
5807
5808 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5809 assert(VM_Version::supports_avx(), "");
5810 assert(imm8 <= 0x01, "imm8: %u", imm8);
5811 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5812 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5813 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5814 emit_int8(0x39);
5815 emit_int8((unsigned char)(0xC0 | encode));
5816 // 0x00 - extract from lower 128 bits
5817 // 0x01 - extract from upper 128 bits
5818 emit_int8(imm8 & 0x01);
5819 }
5820
5821 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
5822 assert(VM_Version::supports_avx2(), "");
5823 assert(src != xnoreg, "sanity");
5824 assert(imm8 <= 0x01, "imm8: %u", imm8);
5825 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5826 InstructionMark im(this);
5827 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5828 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5829 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5830 emit_int8(0x39);
5831 emit_operand(src, dst);
5832 // 0x00 - extract from lower 128 bits
5833 // 0x01 - extract from upper 128 bits
5834 emit_int8(imm8 & 0x01);
5835 }
5836
5837 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5838 assert(VM_Version::supports_avx(), "");
5839 assert(imm8 <= 0x03, "imm8: %u", imm8);
5840 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5841 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5842 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5843 emit_int8(0x39);
5844 emit_int8((unsigned char)(0xC0 | encode));
5845 // 0x00 - extract from bits 127:0
5846 // 0x01 - extract from bits 255:128
5847 // 0x02 - extract from bits 383:256
5848 // 0x03 - extract from bits 511:384
5849 emit_int8(imm8 & 0x03);
5850 }
5851
5852 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
5853 assert(VM_Version::supports_evex(), "");
5854 assert(src != xnoreg, "sanity");
5855 assert(imm8 <= 0x03, "imm8: %u", imm8);
5856 InstructionMark im(this);
5857 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5858 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5859 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5860 emit_int8(0x39);
5861 emit_operand(src, dst);
5862 // 0x00 - extract from bits 127:0
5863 // 0x01 - extract from bits 255:128
5864 // 0x02 - extract from bits 383:256
5865 // 0x03 - extract from bits 511:384
5866 emit_int8(imm8 & 0x03);
5867 }
5868
5869 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5870 assert(VM_Version::supports_evex(), "");
5871 assert(imm8 <= 0x03, "imm8: %u", imm8);
5872 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5873 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5874 emit_int8(0x39);
5875 emit_int8((unsigned char)(0xC0 | encode));
5876 // 0x00 - extract from bits 127:0
5877 // 0x01 - extract from bits 255:128
5878 // 0x02 - extract from bits 383:256
5879 // 0x03 - extract from bits 511:384
5880 emit_int8(imm8 & 0x03);
5881 }
5882
5883 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5884 assert(VM_Version::supports_evex(), "");
5885 assert(imm8 <= 0x01, "imm8: %u", imm8);
5886 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5887 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5888 emit_int8(0x3B);
5889 emit_int8((unsigned char)(0xC0 | encode));
5890 // 0x00 - extract from lower 256 bits
5891 // 0x01 - extract from upper 256 bits
5892 emit_int8(imm8 & 0x01);
5893 }
5894
5895
5896 // vextractf forms
5897
5898 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5899 assert(VM_Version::supports_avx(), "");
5900 assert(imm8 <= 0x01, "imm8: %u", imm8);
5901 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5902 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5903 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5904 emit_int8(0x19);
5905 emit_int8((unsigned char)(0xC0 | encode));
5906 // 0x00 - extract from lower 128 bits
5907 // 0x01 - extract from upper 128 bits
5908 emit_int8(imm8 & 0x01);
5909 }
5910
5911 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
5912 assert(VM_Version::supports_avx(), "");
5913 assert(src != xnoreg, "sanity");
5914 assert(imm8 <= 0x01, "imm8: %u", imm8);
5915 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
5916 InstructionMark im(this);
5917 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5918 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5919 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5920 emit_int8(0x19);
5921 emit_operand(src, dst);
5922 // 0x00 - extract from lower 128 bits
5923 // 0x01 - extract from upper 128 bits
5924 emit_int8(imm8 & 0x01);
5925 }
5926
5927 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5928 assert(VM_Version::supports_avx(), "");
5929 assert(imm8 <= 0x03, "imm8: %u", imm8);
5930 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
5931 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5932 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5933 emit_int8(0x19);
5934 emit_int8((unsigned char)(0xC0 | encode));
5935 // 0x00 - extract from bits 127:0
5936 // 0x01 - extract from bits 255:128
5937 // 0x02 - extract from bits 383:256
5938 // 0x03 - extract from bits 511:384
5939 emit_int8(imm8 & 0x03);
5940 }
5941
5942 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
5943 assert(VM_Version::supports_evex(), "");
5944 assert(src != xnoreg, "sanity");
5945 assert(imm8 <= 0x03, "imm8: %u", imm8);
5946 InstructionMark im(this);
5947 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5948 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
5949 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5950 emit_int8(0x19);
5951 emit_operand(src, dst);
5952 // 0x00 - extract from bits 127:0
5953 // 0x01 - extract from bits 255:128
5954 // 0x02 - extract from bits 383:256
5955 // 0x03 - extract from bits 511:384
5956 emit_int8(imm8 & 0x03);
5957 }
5958
5959 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5960 assert(VM_Version::supports_evex(), "");
5961 assert(imm8 <= 0x03, "imm8: %u", imm8);
5962 InstructionAttr attributes(AVX_512bit, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5963 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5964 emit_int8(0x19);
5965 emit_int8((unsigned char)(0xC0 | encode));
5966 // 0x00 - extract from bits 127:0
5967 // 0x01 - extract from bits 255:128
5968 // 0x02 - extract from bits 383:256
5969 // 0x03 - extract from bits 511:384
5970 emit_int8(imm8 & 0x03);
5971 }
5972
5973 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
5974 assert(VM_Version::supports_evex(), "");
5975 assert(imm8 <= 0x01, "imm8: %u", imm8);
5976 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5977 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5978 emit_int8(0x1B);
5979 emit_int8((unsigned char)(0xC0 | encode));
5980 // 0x00 - extract from lower 256 bits
5981 // 0x01 - extract from upper 256 bits
5982 emit_int8(imm8 & 0x01);
5983 }
5984
5985 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
5986 assert(VM_Version::supports_evex(), "");
5987 assert(src != xnoreg, "sanity");
5988 assert(imm8 <= 0x01, "imm8: %u", imm8);
5989 InstructionMark im(this);
5990 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
5991 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
5992 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5993 emit_int8(0x1B);
5994 emit_operand(src, dst);
5995 // 0x00 - extract from lower 256 bits
5996 // 0x01 - extract from upper 256 bits
5997 emit_int8(imm8 & 0x01);
5998 }
5999
6000
6001 // legacy word/dword replicate
6002 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
6003 assert(VM_Version::supports_avx2(), "");
6004 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6005 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6006 emit_int8(0x79);
6007 emit_int8((unsigned char)(0xC0 | encode));
6008 }
6009
6010 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
6011 assert(VM_Version::supports_avx2(), "");
6012 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6013 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6014 emit_int8(0x58);
6015 emit_int8((unsigned char)(0xC0 | encode));
6016 }
6017
6018
6019 // xmm/mem sourced byte/word/dword/qword replicate
6020
6021 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6022 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
6023 assert(VM_Version::supports_evex(), "");
6024 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6025 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6026 emit_int8(0x78);
6027 emit_int8((unsigned char)(0xC0 | encode));
6028 }
6029
6030 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
6031 assert(VM_Version::supports_evex(), "");
6032 assert(dst != xnoreg, "sanity");
6033 InstructionMark im(this);
6034 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6035 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
6036 // swap src<->dst for encoding
6037 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6038 emit_int8(0x78);
6039 emit_operand(dst, src);
6040 }
6041
6042 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6043 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
6044 assert(VM_Version::supports_evex(), "");
6045 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6046 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6047 emit_int8(0x79);
6048 emit_int8((unsigned char)(0xC0 | encode));
6049 }
6050
6051 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
6052 assert(VM_Version::supports_evex(), "");
6053 assert(dst != xnoreg, "sanity");
6054 InstructionMark im(this);
6055 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6056 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
6057 // swap src<->dst for encoding
6058 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6059 emit_int8(0x79);
6060 emit_operand(dst, src);
6061 }
6062
6063 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6064 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
6065 assert(VM_Version::supports_evex(), "");
6066 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6067 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6068 emit_int8(0x58);
6069 emit_int8((unsigned char)(0xC0 | encode));
6070 }
6071
6072 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
6073 assert(VM_Version::supports_evex(), "");
6074 assert(dst != xnoreg, "sanity");
6075 InstructionMark im(this);
6076 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6077 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6078 // swap src<->dst for encoding
6079 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6080 emit_int8(0x58);
6081 emit_operand(dst, src);
6082 }
6083
6084 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6085 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
6086 assert(VM_Version::supports_evex(), "");
6087 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6088 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6089 emit_int8(0x59);
6090 emit_int8((unsigned char)(0xC0 | encode));
6091 }
6092
6093 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
6094 assert(VM_Version::supports_evex(), "");
6095 assert(dst != xnoreg, "sanity");
6096 InstructionMark im(this);
6097 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6098 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6099 // swap src<->dst for encoding
6100 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6101 emit_int8(0x59);
6102 emit_operand(dst, src);
6103 }
6104
6105
6106 // scalar single/double precision replicate
6107
6108 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
6109 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
6110 assert(VM_Version::supports_evex(), "");
6111 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6112 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6113 emit_int8(0x18);
6114 emit_int8((unsigned char)(0xC0 | encode));
6115 }
6116
6117 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
6118 assert(VM_Version::supports_evex(), "");
6119 assert(dst != xnoreg, "sanity");
6120 InstructionMark im(this);
6121 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6122 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6123 // swap src<->dst for encoding
6124 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6125 emit_int8(0x18);
6126 emit_operand(dst, src);
6127 }
6128
6129 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
6130 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
6131 assert(VM_Version::supports_evex(), "");
6132 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6133 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6134 emit_int8(0x19);
6135 emit_int8((unsigned char)(0xC0 | encode));
6136 }
6137
6138 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
6139 assert(VM_Version::supports_evex(), "");
6140 assert(dst != xnoreg, "sanity");
6141 InstructionMark im(this);
6142 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6143 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6144 // swap src<->dst for encoding
6145 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6146 emit_int8(0x19);
6147 emit_operand(dst, src);
6148 }
6149
6150
6151 // gpr source broadcast forms
6152
6153 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6154 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
6155 assert(VM_Version::supports_evex(), "");
6156 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6157 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6158 if (attributes.is_evex_instruction()) {
6159 emit_int8(0x7A);
6160 } else {
6161 emit_int8(0x78);
6162 }
6163 emit_int8((unsigned char)(0xC0 | encode));
6164 }
6165
6166 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
6167 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
6168 assert(VM_Version::supports_evex(), "");
6169 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6170 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6171 if (attributes.is_evex_instruction()) {
6172 emit_int8(0x7B);
6173 } else {
6174 emit_int8(0x79);
6175 }
6176 emit_int8((unsigned char)(0xC0 | encode));
6177 }
6178
6179 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
6180 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
6181 assert(VM_Version::supports_evex(), "");
6182 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6183 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6184 if (attributes.is_evex_instruction()) {
6185 emit_int8(0x7C);
6186 } else {
6187 emit_int8(0x58);
6188 }
6189 emit_int8((unsigned char)(0xC0 | encode));
6190 }
6191
6192 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
6193 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
6194 assert(VM_Version::supports_evex(), "");
6195 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6196 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6197 if (attributes.is_evex_instruction()) {
6198 emit_int8(0x7C);
6199 } else {
6200 emit_int8(0x59);
6201 }
6202 emit_int8((unsigned char)(0xC0 | encode));
6203 }
6204
6205
6206 // Carry-Less Multiplication Quadword
6207 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
6208 assert(VM_Version::supports_clmul(), "");
6209 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6210 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6211 emit_int8(0x44);
6212 emit_int8((unsigned char)(0xC0 | encode));
6213 emit_int8((unsigned char)mask);
6214 }
6215
6216 // Carry-Less Multiplication Quadword
6217 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
6218 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
6219 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6220 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6221 emit_int8(0x44);
6222 emit_int8((unsigned char)(0xC0 | encode));
6223 emit_int8((unsigned char)mask);
6224 }
6225
6226 void Assembler::vzeroupper() {
6227 assert(VM_Version::supports_avx(), "");
6228 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6229 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6230 emit_int8(0x77);
6231 }
6232
6233
6234 #ifndef _LP64
6235 // 32bit only pieces of the assembler
6236
6237 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
6238 // NO PREFIX AS NEVER 64BIT
6239 InstructionMark im(this);
6240 emit_int8((unsigned char)0x81);
6241 emit_int8((unsigned char)(0xF8 | src1->encoding()));
6242 emit_data(imm32, rspec, 0);
6243 }
6244
6245 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
6246 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
6247 InstructionMark im(this);
6248 emit_int8((unsigned char)0x81);
6249 emit_operand(rdi, src1);
6250 emit_data(imm32, rspec, 0);
6251 }
6252
6253 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
6254 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
6255 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
6256 void Assembler::cmpxchg8(Address adr) {
6257 InstructionMark im(this);
6258 emit_int8(0x0F);
6259 emit_int8((unsigned char)0xC7);
6260 emit_operand(rcx, adr);
6261 }
6262
6263 void Assembler::decl(Register dst) {
6264 // Don't use it directly. Use MacroAssembler::decrementl() instead.
6265 emit_int8(0x48 | dst->encoding());
6266 }
6267
6268 #endif // _LP64
6269
6270 // 64bit typically doesn't use the x87 but needs to for the trig funcs
6271
6272 void Assembler::fabs() {
6273 emit_int8((unsigned char)0xD9);
6274 emit_int8((unsigned char)0xE1);
6275 }
6276
6277 void Assembler::fadd(int i) {
6278 emit_farith(0xD8, 0xC0, i);
6279 }
6280
6281 void Assembler::fadd_d(Address src) {
6282 InstructionMark im(this);
6283 emit_int8((unsigned char)0xDC);
6284 emit_operand32(rax, src);
6285 }
6286
6287 void Assembler::fadd_s(Address src) {
6288 InstructionMark im(this);
6289 emit_int8((unsigned char)0xD8);
6290 emit_operand32(rax, src);
6291 }
6292
6293 void Assembler::fadda(int i) {
6294 emit_farith(0xDC, 0xC0, i);
6295 }
6296
6297 void Assembler::faddp(int i) {
6298 emit_farith(0xDE, 0xC0, i);
6299 }
6300
6301 void Assembler::fchs() {
6302 emit_int8((unsigned char)0xD9);
6303 emit_int8((unsigned char)0xE0);
6304 }
6305
6306 void Assembler::fcom(int i) {
6307 emit_farith(0xD8, 0xD0, i);
6308 }
6309
6310 void Assembler::fcomp(int i) {
6311 emit_farith(0xD8, 0xD8, i);
6312 }
6313
6314 void Assembler::fcomp_d(Address src) {
6315 InstructionMark im(this);
6316 emit_int8((unsigned char)0xDC);
6317 emit_operand32(rbx, src);
6318 }
6319
6320 void Assembler::fcomp_s(Address src) {
6321 InstructionMark im(this);
6322 emit_int8((unsigned char)0xD8);
6323 emit_operand32(rbx, src);
6324 }
6325
6326 void Assembler::fcompp() {
6327 emit_int8((unsigned char)0xDE);
6328 emit_int8((unsigned char)0xD9);
6329 }
6330
6331 void Assembler::fcos() {
6332 emit_int8((unsigned char)0xD9);
6333 emit_int8((unsigned char)0xFF);
6334 }
6335
6336 void Assembler::fdecstp() {
6337 emit_int8((unsigned char)0xD9);
6338 emit_int8((unsigned char)0xF6);
6339 }
6340
6341 void Assembler::fdiv(int i) {
6342 emit_farith(0xD8, 0xF0, i);
6343 }
6344
6345 void Assembler::fdiv_d(Address src) {
6346 InstructionMark im(this);
6347 emit_int8((unsigned char)0xDC);
6348 emit_operand32(rsi, src);
6349 }
6350
6351 void Assembler::fdiv_s(Address src) {
6352 InstructionMark im(this);
6353 emit_int8((unsigned char)0xD8);
6354 emit_operand32(rsi, src);
6355 }
6356
6357 void Assembler::fdiva(int i) {
6358 emit_farith(0xDC, 0xF8, i);
6359 }
6360
6361 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
6362 // is erroneous for some of the floating-point instructions below.
6363
6364 void Assembler::fdivp(int i) {
6365 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
6366 }
6367
6368 void Assembler::fdivr(int i) {
6369 emit_farith(0xD8, 0xF8, i);
6370 }
6371
6372 void Assembler::fdivr_d(Address src) {
6373 InstructionMark im(this);
6374 emit_int8((unsigned char)0xDC);
6375 emit_operand32(rdi, src);
6376 }
6377
6378 void Assembler::fdivr_s(Address src) {
6379 InstructionMark im(this);
6380 emit_int8((unsigned char)0xD8);
6381 emit_operand32(rdi, src);
6382 }
6383
6384 void Assembler::fdivra(int i) {
6385 emit_farith(0xDC, 0xF0, i);
6386 }
6387
6388 void Assembler::fdivrp(int i) {
6389 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
6390 }
6391
6392 void Assembler::ffree(int i) {
6393 emit_farith(0xDD, 0xC0, i);
6394 }
6395
6396 void Assembler::fild_d(Address adr) {
6397 InstructionMark im(this);
6398 emit_int8((unsigned char)0xDF);
6399 emit_operand32(rbp, adr);
6400 }
6401
6402 void Assembler::fild_s(Address adr) {
6403 InstructionMark im(this);
6404 emit_int8((unsigned char)0xDB);
6405 emit_operand32(rax, adr);
6406 }
6407
6408 void Assembler::fincstp() {
6409 emit_int8((unsigned char)0xD9);
6410 emit_int8((unsigned char)0xF7);
6411 }
6412
6413 void Assembler::finit() {
6414 emit_int8((unsigned char)0x9B);
6415 emit_int8((unsigned char)0xDB);
6416 emit_int8((unsigned char)0xE3);
6417 }
6418
6419 void Assembler::fist_s(Address adr) {
6420 InstructionMark im(this);
6421 emit_int8((unsigned char)0xDB);
6422 emit_operand32(rdx, adr);
6423 }
6424
6425 void Assembler::fistp_d(Address adr) {
6426 InstructionMark im(this);
6427 emit_int8((unsigned char)0xDF);
6428 emit_operand32(rdi, adr);
6429 }
6430
6431 void Assembler::fistp_s(Address adr) {
6432 InstructionMark im(this);
6433 emit_int8((unsigned char)0xDB);
6434 emit_operand32(rbx, adr);
6435 }
6436
6437 void Assembler::fld1() {
6438 emit_int8((unsigned char)0xD9);
6439 emit_int8((unsigned char)0xE8);
6440 }
6441
6442 void Assembler::fld_d(Address adr) {
6443 InstructionMark im(this);
6444 emit_int8((unsigned char)0xDD);
6445 emit_operand32(rax, adr);
6446 }
6447
6448 void Assembler::fld_s(Address adr) {
6449 InstructionMark im(this);
6450 emit_int8((unsigned char)0xD9);
6451 emit_operand32(rax, adr);
6452 }
6453
6454
6455 void Assembler::fld_s(int index) {
6456 emit_farith(0xD9, 0xC0, index);
6457 }
6458
6459 void Assembler::fld_x(Address adr) {
6460 InstructionMark im(this);
6461 emit_int8((unsigned char)0xDB);
6462 emit_operand32(rbp, adr);
6463 }
6464
6465 void Assembler::fldcw(Address src) {
6466 InstructionMark im(this);
6467 emit_int8((unsigned char)0xD9);
6468 emit_operand32(rbp, src);
6469 }
6470
6471 void Assembler::fldenv(Address src) {
6472 InstructionMark im(this);
6473 emit_int8((unsigned char)0xD9);
6474 emit_operand32(rsp, src);
6475 }
6476
6477 void Assembler::fldlg2() {
6478 emit_int8((unsigned char)0xD9);
6479 emit_int8((unsigned char)0xEC);
6480 }
6481
6482 void Assembler::fldln2() {
6483 emit_int8((unsigned char)0xD9);
6484 emit_int8((unsigned char)0xED);
6485 }
6486
6487 void Assembler::fldz() {
6488 emit_int8((unsigned char)0xD9);
6489 emit_int8((unsigned char)0xEE);
6490 }
6491
6492 void Assembler::flog() {
6493 fldln2();
6494 fxch();
6495 fyl2x();
6496 }
6497
6498 void Assembler::flog10() {
6499 fldlg2();
6500 fxch();
6501 fyl2x();
6502 }
6503
6504 void Assembler::fmul(int i) {
6505 emit_farith(0xD8, 0xC8, i);
6506 }
6507
6508 void Assembler::fmul_d(Address src) {
6509 InstructionMark im(this);
6510 emit_int8((unsigned char)0xDC);
6511 emit_operand32(rcx, src);
6512 }
6513
6514 void Assembler::fmul_s(Address src) {
6515 InstructionMark im(this);
6516 emit_int8((unsigned char)0xD8);
6517 emit_operand32(rcx, src);
6518 }
6519
6520 void Assembler::fmula(int i) {
6521 emit_farith(0xDC, 0xC8, i);
6522 }
6523
6524 void Assembler::fmulp(int i) {
6525 emit_farith(0xDE, 0xC8, i);
6526 }
6527
6528 void Assembler::fnsave(Address dst) {
6529 InstructionMark im(this);
6530 emit_int8((unsigned char)0xDD);
6531 emit_operand32(rsi, dst);
6532 }
6533
6534 void Assembler::fnstcw(Address src) {
6535 InstructionMark im(this);
6536 emit_int8((unsigned char)0x9B);
6537 emit_int8((unsigned char)0xD9);
6538 emit_operand32(rdi, src);
6539 }
6540
6541 void Assembler::fnstsw_ax() {
6542 emit_int8((unsigned char)0xDF);
6543 emit_int8((unsigned char)0xE0);
6544 }
6545
6546 void Assembler::fprem() {
6547 emit_int8((unsigned char)0xD9);
6548 emit_int8((unsigned char)0xF8);
6549 }
6550
6551 void Assembler::fprem1() {
6552 emit_int8((unsigned char)0xD9);
6553 emit_int8((unsigned char)0xF5);
6554 }
6555
6556 void Assembler::frstor(Address src) {
6557 InstructionMark im(this);
6558 emit_int8((unsigned char)0xDD);
6559 emit_operand32(rsp, src);
6560 }
6561
6562 void Assembler::fsin() {
6563 emit_int8((unsigned char)0xD9);
6564 emit_int8((unsigned char)0xFE);
6565 }
6566
6567 void Assembler::fsqrt() {
6568 emit_int8((unsigned char)0xD9);
6569 emit_int8((unsigned char)0xFA);
6570 }
6571
6572 void Assembler::fst_d(Address adr) {
6573 InstructionMark im(this);
6574 emit_int8((unsigned char)0xDD);
6575 emit_operand32(rdx, adr);
6576 }
6577
6578 void Assembler::fst_s(Address adr) {
6579 InstructionMark im(this);
6580 emit_int8((unsigned char)0xD9);
6581 emit_operand32(rdx, adr);
6582 }
6583
6584 void Assembler::fstp_d(Address adr) {
6585 InstructionMark im(this);
6586 emit_int8((unsigned char)0xDD);
6587 emit_operand32(rbx, adr);
6588 }
6589
6590 void Assembler::fstp_d(int index) {
6591 emit_farith(0xDD, 0xD8, index);
6592 }
6593
6594 void Assembler::fstp_s(Address adr) {
6595 InstructionMark im(this);
6596 emit_int8((unsigned char)0xD9);
6597 emit_operand32(rbx, adr);
6598 }
6599
6600 void Assembler::fstp_x(Address adr) {
6601 InstructionMark im(this);
6602 emit_int8((unsigned char)0xDB);
6603 emit_operand32(rdi, adr);
6604 }
6605
6606 void Assembler::fsub(int i) {
6607 emit_farith(0xD8, 0xE0, i);
6608 }
6609
6610 void Assembler::fsub_d(Address src) {
6611 InstructionMark im(this);
6612 emit_int8((unsigned char)0xDC);
6613 emit_operand32(rsp, src);
6614 }
6615
6616 void Assembler::fsub_s(Address src) {
6617 InstructionMark im(this);
6618 emit_int8((unsigned char)0xD8);
6619 emit_operand32(rsp, src);
6620 }
6621
6622 void Assembler::fsuba(int i) {
6623 emit_farith(0xDC, 0xE8, i);
6624 }
6625
6626 void Assembler::fsubp(int i) {
6627 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
6628 }
6629
6630 void Assembler::fsubr(int i) {
6631 emit_farith(0xD8, 0xE8, i);
6632 }
6633
6634 void Assembler::fsubr_d(Address src) {
6635 InstructionMark im(this);
6636 emit_int8((unsigned char)0xDC);
6637 emit_operand32(rbp, src);
6638 }
6639
6640 void Assembler::fsubr_s(Address src) {
6641 InstructionMark im(this);
6642 emit_int8((unsigned char)0xD8);
6643 emit_operand32(rbp, src);
6644 }
6645
6646 void Assembler::fsubra(int i) {
6647 emit_farith(0xDC, 0xE0, i);
6648 }
6649
6650 void Assembler::fsubrp(int i) {
6651 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
6652 }
6653
6654 void Assembler::ftan() {
6655 emit_int8((unsigned char)0xD9);
6656 emit_int8((unsigned char)0xF2);
6657 emit_int8((unsigned char)0xDD);
6658 emit_int8((unsigned char)0xD8);
6659 }
6660
6661 void Assembler::ftst() {
6662 emit_int8((unsigned char)0xD9);
6663 emit_int8((unsigned char)0xE4);
6664 }
6665
6666 void Assembler::fucomi(int i) {
6667 // make sure the instruction is supported (introduced for P6, together with cmov)
6668 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6669 emit_farith(0xDB, 0xE8, i);
6670 }
6671
6672 void Assembler::fucomip(int i) {
6673 // make sure the instruction is supported (introduced for P6, together with cmov)
6674 guarantee(VM_Version::supports_cmov(), "illegal instruction");
6675 emit_farith(0xDF, 0xE8, i);
6676 }
6677
6678 void Assembler::fwait() {
6679 emit_int8((unsigned char)0x9B);
6680 }
6681
6682 void Assembler::fxch(int i) {
6683 emit_farith(0xD9, 0xC8, i);
6684 }
6685
6686 void Assembler::fyl2x() {
6687 emit_int8((unsigned char)0xD9);
6688 emit_int8((unsigned char)0xF1);
6689 }
6690
6691 void Assembler::frndint() {
6692 emit_int8((unsigned char)0xD9);
6693 emit_int8((unsigned char)0xFC);
6694 }
6695
6696 void Assembler::f2xm1() {
6697 emit_int8((unsigned char)0xD9);
6698 emit_int8((unsigned char)0xF0);
6699 }
6700
6701 void Assembler::fldl2e() {
6702 emit_int8((unsigned char)0xD9);
6703 emit_int8((unsigned char)0xEA);
6704 }
6705
6706 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
6707 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
6708 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
6709 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
6710
6711 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
6712 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6713 if (pre > 0) {
6714 emit_int8(simd_pre[pre]);
6715 }
6716 if (rex_w) {
6717 prefixq(adr, xreg);
6718 } else {
6719 prefix(adr, xreg);
6720 }
6721 if (opc > 0) {
6722 emit_int8(0x0F);
6723 int opc2 = simd_opc[opc];
6724 if (opc2 > 0) {
6725 emit_int8(opc2);
6726 }
6727 }
6728 }
6729
6730 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
6731 if (pre > 0) {
6732 emit_int8(simd_pre[pre]);
6733 }
6734 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
6735 if (opc > 0) {
6736 emit_int8(0x0F);
6737 int opc2 = simd_opc[opc];
6738 if (opc2 > 0) {
6739 emit_int8(opc2);
6740 }
6741 }
6742 return encode;
6743 }
6744
6745
6746 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
6747 int vector_len = _attributes->get_vector_len();
6748 bool vex_w = _attributes->is_rex_vex_w();
6749 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
6750 prefix(VEX_3bytes);
6751
6752 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
6753 byte1 = (~byte1) & 0xE0;
6754 byte1 |= opc;
6755 emit_int8(byte1);
6756
6757 int byte2 = ((~nds_enc) & 0xf) << 3;
6758 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
6759 emit_int8(byte2);
6760 } else {
6761 prefix(VEX_2bytes);
6762
6763 int byte1 = vex_r ? VEX_R : 0;
6764 byte1 = (~byte1) & 0x80;
6765 byte1 |= ((~nds_enc) & 0xf) << 3;
6766 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
6767 emit_int8(byte1);
6768 }
6769 }
6770
6771 // This is a 4 byte encoding
6772 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
6773 // EVEX 0x62 prefix
6774 prefix(EVEX_4bytes);
6775 bool vex_w = _attributes->is_rex_vex_w();
6776 int evex_encoding = (vex_w ? VEX_W : 0);
6777 // EVEX.b is not currently used for broadcast of single element or data rounding modes
6778 _attributes->set_evex_encoding(evex_encoding);
6779
6780 // P0: byte 2, initialized to RXBR`00mm
6781 // instead of not'd
6782 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
6783 byte2 = (~byte2) & 0xF0;
6784 // confine opc opcode extensions in mm bits to lower two bits
6785 // of form {0F, 0F_38, 0F_3A}
6786 byte2 |= opc;
6787 emit_int8(byte2);
6788
6789 // P1: byte 3 as Wvvvv1pp
6790 int byte3 = ((~nds_enc) & 0xf) << 3;
6791 // p[10] is always 1
6792 byte3 |= EVEX_F;
6793 byte3 |= (vex_w & 1) << 7;
6794 // confine pre opcode extensions in pp bits to lower two bits
6795 // of form {66, F3, F2}
6796 byte3 |= pre;
6797 emit_int8(byte3);
6798
6799 // P2: byte 4 as zL'Lbv'aaa
6800 int byte4 = (_attributes->is_no_reg_mask()) ? 0 : 1; // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
6801 // EVEX.v` for extending EVEX.vvvv or VIDX
6802 byte4 |= (evex_v ? 0: EVEX_V);
6803 // third EXEC.b for broadcast actions
6804 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
6805 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
6806 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
6807 // last is EVEX.z for zero/merge actions
6808 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
6809 emit_int8(byte4);
6810 }
6811
6812 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6813 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
6814 bool vex_b = adr.base_needs_rex();
6815 bool vex_x = adr.index_needs_rex();
6816 set_attributes(attributes);
6817 attributes->set_current_assembler(this);
6818
6819 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6820 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6821 switch (attributes->get_vector_len()) {
6822 case AVX_128bit:
6823 case AVX_256bit:
6824 attributes->set_is_legacy_mode();
6825 break;
6826 }
6827 }
6828
6829 // For pure EVEX check and see if this instruction
6830 // is allowed in legacy mode and has resources which will
6831 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6832 // else that field is set when we encode to EVEX
6833 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6834 !_is_managed && !attributes->is_evex_instruction()) {
6835 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6836 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6837 if (check_register_bank) {
6838 // check nds_enc and xreg_enc for upper bank usage
6839 if (nds_enc < 16 && xreg_enc < 16) {
6840 attributes->set_is_legacy_mode();
6841 }
6842 } else {
6843 attributes->set_is_legacy_mode();
6844 }
6845 }
6846 }
6847
6848 _is_managed = false;
6849 if (UseAVX > 2 && !attributes->is_legacy_mode())
6850 {
6851 bool evex_r = (xreg_enc >= 16);
6852 bool evex_v = (nds_enc >= 16);
6853 attributes->set_is_evex_instruction();
6854 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6855 } else {
6856 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6857 }
6858 }
6859
6860 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
6861 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
6862 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
6863 bool vex_x = false;
6864 set_attributes(attributes);
6865 attributes->set_current_assembler(this);
6866 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
6867
6868 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
6869 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
6870 switch (attributes->get_vector_len()) {
6871 case AVX_128bit:
6872 case AVX_256bit:
6873 if (check_register_bank) {
6874 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
6875 // up propagate arithmetic instructions to meet RA requirements
6876 attributes->set_vector_len(AVX_512bit);
6877 } else {
6878 attributes->set_is_legacy_mode();
6879 }
6880 } else {
6881 attributes->set_is_legacy_mode();
6882 }
6883 break;
6884 }
6885 }
6886
6887 // For pure EVEX check and see if this instruction
6888 // is allowed in legacy mode and has resources which will
6889 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
6890 // else that field is set when we encode to EVEX
6891 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
6892 !_is_managed && !attributes->is_evex_instruction()) {
6893 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
6894 if (check_register_bank) {
6895 // check dst_enc, nds_enc and src_enc for upper bank usage
6896 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
6897 attributes->set_is_legacy_mode();
6898 }
6899 } else {
6900 attributes->set_is_legacy_mode();
6901 }
6902 }
6903 }
6904
6905 _is_managed = false;
6906 if (UseAVX > 2 && !attributes->is_legacy_mode())
6907 {
6908 bool evex_r = (dst_enc >= 16);
6909 bool evex_v = (nds_enc >= 16);
6910 // can use vex_x as bank extender on rm encoding
6911 vex_x = (src_enc >= 16);
6912 attributes->set_is_evex_instruction();
6913 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
6914 } else {
6915 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
6916 }
6917
6918 // return modrm byte components for operands
6919 return (((dst_enc & 7) << 3) | (src_enc & 7));
6920 }
6921
6922
6923 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
6924 VexOpcode opc, InstructionAttr *attributes) {
6925 if (UseAVX > 0) {
6926 int xreg_enc = xreg->encoding();
6927 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6928 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
6929 } else {
6930 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
6931 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
6932 }
6933 }
6934
6935 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
6936 VexOpcode opc, InstructionAttr *attributes) {
6937 int dst_enc = dst->encoding();
6938 int src_enc = src->encoding();
6939 if (UseAVX > 0) {
6940 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
6941 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
6942 } else {
6943 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
6944 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
6945 }
6946 }
6947
6948 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
6949 assert(VM_Version::supports_avx(), "");
6950 assert(!VM_Version::supports_evex(), "");
6951 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6952 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6953 emit_int8((unsigned char)0xC2);
6954 emit_int8((unsigned char)(0xC0 | encode));
6955 emit_int8((unsigned char)(0xF & cop));
6956 }
6957
6958 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
6959 assert(VM_Version::supports_avx(), "");
6960 assert(!VM_Version::supports_evex(), "");
6961 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
6962 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6963 emit_int8((unsigned char)0x4B);
6964 emit_int8((unsigned char)(0xC0 | encode));
6965 int src2_enc = src2->encoding();
6966 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
6967 }
6968
6969
6970 #ifndef _LP64
6971
6972 void Assembler::incl(Register dst) {
6973 // Don't use it directly. Use MacroAssembler::incrementl() instead.
6974 emit_int8(0x40 | dst->encoding());
6975 }
6976
6977 void Assembler::lea(Register dst, Address src) {
6978 leal(dst, src);
6979 }
6980
6981 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
6982 InstructionMark im(this);
6983 emit_int8((unsigned char)0xC7);
6984 emit_operand(rax, dst);
6985 emit_data((int)imm32, rspec, 0);
6986 }
6987
6988 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
6989 InstructionMark im(this);
6990 int encode = prefix_and_encode(dst->encoding());
6991 emit_int8((unsigned char)(0xB8 | encode));
6992 emit_data((int)imm32, rspec, 0);
6993 }
6994
6995 void Assembler::popa() { // 32bit
6996 emit_int8(0x61);
6997 }
6998
6999 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
7000 InstructionMark im(this);
7001 emit_int8(0x68);
7002 emit_data(imm32, rspec, 0);
7003 }
7004
7005 void Assembler::pusha() { // 32bit
7006 emit_int8(0x60);
7007 }
7008
7009 void Assembler::set_byte_if_not_zero(Register dst) {
7010 emit_int8(0x0F);
7011 emit_int8((unsigned char)0x95);
7012 emit_int8((unsigned char)(0xE0 | dst->encoding()));
7013 }
7014
7015 void Assembler::shldl(Register dst, Register src) {
7016 emit_int8(0x0F);
7017 emit_int8((unsigned char)0xA5);
7018 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7019 }
7020
7021 // 0F A4 / r ib
7022 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
7023 emit_int8(0x0F);
7024 emit_int8((unsigned char)0xA4);
7025 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7026 emit_int8(imm8);
7027 }
7028
7029 void Assembler::shrdl(Register dst, Register src) {
7030 emit_int8(0x0F);
7031 emit_int8((unsigned char)0xAD);
7032 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
7033 }
7034
7035 #else // LP64
7036
7037 void Assembler::set_byte_if_not_zero(Register dst) {
7038 int enc = prefix_and_encode(dst->encoding(), true);
7039 emit_int8(0x0F);
7040 emit_int8((unsigned char)0x95);
7041 emit_int8((unsigned char)(0xE0 | enc));
7042 }
7043
7044 // 64bit only pieces of the assembler
7045 // This should only be used by 64bit instructions that can use rip-relative
7046 // it cannot be used by instructions that want an immediate value.
7047
7048 bool Assembler::reachable(AddressLiteral adr) {
7049 int64_t disp;
7050 // None will force a 64bit literal to the code stream. Likely a placeholder
7051 // for something that will be patched later and we need to certain it will
7052 // always be reachable.
7053 if (adr.reloc() == relocInfo::none) {
7054 return false;
7055 }
7056 if (adr.reloc() == relocInfo::internal_word_type) {
7057 // This should be rip relative and easily reachable.
7058 return true;
7059 }
7060 if (adr.reloc() == relocInfo::virtual_call_type ||
7061 adr.reloc() == relocInfo::opt_virtual_call_type ||
7062 adr.reloc() == relocInfo::static_call_type ||
7063 adr.reloc() == relocInfo::static_stub_type ) {
7064 // This should be rip relative within the code cache and easily
7065 // reachable until we get huge code caches. (At which point
7066 // ic code is going to have issues).
7067 return true;
7068 }
7069 if (adr.reloc() != relocInfo::external_word_type &&
7070 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
7071 adr.reloc() != relocInfo::poll_type && // relocs to identify them
7072 adr.reloc() != relocInfo::runtime_call_type ) {
7073 return false;
7074 }
7075
7076 // Stress the correction code
7077 if (ForceUnreachable) {
7078 // Must be runtimecall reloc, see if it is in the codecache
7079 // Flipping stuff in the codecache to be unreachable causes issues
7080 // with things like inline caches where the additional instructions
7081 // are not handled.
7082 if (CodeCache::find_blob(adr._target) == NULL) {
7083 return false;
7084 }
7085 }
7086 // For external_word_type/runtime_call_type if it is reachable from where we
7087 // are now (possibly a temp buffer) and where we might end up
7088 // anywhere in the codeCache then we are always reachable.
7089 // This would have to change if we ever save/restore shared code
7090 // to be more pessimistic.
7091 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
7092 if (!is_simm32(disp)) return false;
7093 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
7094 if (!is_simm32(disp)) return false;
7095
7096 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
7097
7098 // Because rip relative is a disp + address_of_next_instruction and we
7099 // don't know the value of address_of_next_instruction we apply a fudge factor
7100 // to make sure we will be ok no matter the size of the instruction we get placed into.
7101 // We don't have to fudge the checks above here because they are already worst case.
7102
7103 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
7104 // + 4 because better safe than sorry.
7105 const int fudge = 12 + 4;
7106 if (disp < 0) {
7107 disp -= fudge;
7108 } else {
7109 disp += fudge;
7110 }
7111 return is_simm32(disp);
7112 }
7113
7114 // Check if the polling page is not reachable from the code cache using rip-relative
7115 // addressing.
7116 bool Assembler::is_polling_page_far() {
7117 intptr_t addr = (intptr_t)os::get_polling_page();
7118 return ForceUnreachable ||
7119 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
7120 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
7121 }
7122
7123 void Assembler::emit_data64(jlong data,
7124 relocInfo::relocType rtype,
7125 int format) {
7126 if (rtype == relocInfo::none) {
7127 emit_int64(data);
7128 } else {
7129 emit_data64(data, Relocation::spec_simple(rtype), format);
7130 }
7131 }
7132
7133 void Assembler::emit_data64(jlong data,
7134 RelocationHolder const& rspec,
7135 int format) {
7136 assert(imm_operand == 0, "default format must be immediate in this file");
7137 assert(imm_operand == format, "must be immediate");
7138 assert(inst_mark() != NULL, "must be inside InstructionMark");
7139 // Do not use AbstractAssembler::relocate, which is not intended for
7140 // embedded words. Instead, relocate to the enclosing instruction.
7141 code_section()->relocate(inst_mark(), rspec, format);
7142 #ifdef ASSERT
7143 check_relocation(rspec, format);
7144 #endif
7145 emit_int64(data);
7146 }
7147
7148 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
7149 if (reg_enc >= 8) {
7150 prefix(REX_B);
7151 reg_enc -= 8;
7152 } else if (byteinst && reg_enc >= 4) {
7153 prefix(REX);
7154 }
7155 return reg_enc;
7156 }
7157
7158 int Assembler::prefixq_and_encode(int reg_enc) {
7159 if (reg_enc < 8) {
7160 prefix(REX_W);
7161 } else {
7162 prefix(REX_WB);
7163 reg_enc -= 8;
7164 }
7165 return reg_enc;
7166 }
7167
7168 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
7169 if (dst_enc < 8) {
7170 if (src_enc >= 8) {
7171 prefix(REX_B);
7172 src_enc -= 8;
7173 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
7174 prefix(REX);
7175 }
7176 } else {
7177 if (src_enc < 8) {
7178 prefix(REX_R);
7179 } else {
7180 prefix(REX_RB);
7181 src_enc -= 8;
7182 }
7183 dst_enc -= 8;
7184 }
7185 return dst_enc << 3 | src_enc;
7186 }
7187
7188 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
7189 if (dst_enc < 8) {
7190 if (src_enc < 8) {
7191 prefix(REX_W);
7192 } else {
7193 prefix(REX_WB);
7194 src_enc -= 8;
7195 }
7196 } else {
7197 if (src_enc < 8) {
7198 prefix(REX_WR);
7199 } else {
7200 prefix(REX_WRB);
7201 src_enc -= 8;
7202 }
7203 dst_enc -= 8;
7204 }
7205 return dst_enc << 3 | src_enc;
7206 }
7207
7208 void Assembler::prefix(Register reg) {
7209 if (reg->encoding() >= 8) {
7210 prefix(REX_B);
7211 }
7212 }
7213
7214 void Assembler::prefix(Register dst, Register src, Prefix p) {
7215 if (src->encoding() >= 8) {
7216 p = (Prefix)(p | REX_B);
7217 }
7218 if (dst->encoding() >= 8) {
7219 p = (Prefix)( p | REX_R);
7220 }
7221 if (p != Prefix_EMPTY) {
7222 // do not generate an empty prefix
7223 prefix(p);
7224 }
7225 }
7226
7227 void Assembler::prefix(Register dst, Address adr, Prefix p) {
7228 if (adr.base_needs_rex()) {
7229 if (adr.index_needs_rex()) {
7230 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7231 } else {
7232 prefix(REX_B);
7233 }
7234 } else {
7235 if (adr.index_needs_rex()) {
7236 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
7237 }
7238 }
7239 if (dst->encoding() >= 8) {
7240 p = (Prefix)(p | REX_R);
7241 }
7242 if (p != Prefix_EMPTY) {
7243 // do not generate an empty prefix
7244 prefix(p);
7245 }
7246 }
7247
7248 void Assembler::prefix(Address adr) {
7249 if (adr.base_needs_rex()) {
7250 if (adr.index_needs_rex()) {
7251 prefix(REX_XB);
7252 } else {
7253 prefix(REX_B);
7254 }
7255 } else {
7256 if (adr.index_needs_rex()) {
7257 prefix(REX_X);
7258 }
7259 }
7260 }
7261
7262 void Assembler::prefixq(Address adr) {
7263 if (adr.base_needs_rex()) {
7264 if (adr.index_needs_rex()) {
7265 prefix(REX_WXB);
7266 } else {
7267 prefix(REX_WB);
7268 }
7269 } else {
7270 if (adr.index_needs_rex()) {
7271 prefix(REX_WX);
7272 } else {
7273 prefix(REX_W);
7274 }
7275 }
7276 }
7277
7278
7279 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
7280 if (reg->encoding() < 8) {
7281 if (adr.base_needs_rex()) {
7282 if (adr.index_needs_rex()) {
7283 prefix(REX_XB);
7284 } else {
7285 prefix(REX_B);
7286 }
7287 } else {
7288 if (adr.index_needs_rex()) {
7289 prefix(REX_X);
7290 } else if (byteinst && reg->encoding() >= 4 ) {
7291 prefix(REX);
7292 }
7293 }
7294 } else {
7295 if (adr.base_needs_rex()) {
7296 if (adr.index_needs_rex()) {
7297 prefix(REX_RXB);
7298 } else {
7299 prefix(REX_RB);
7300 }
7301 } else {
7302 if (adr.index_needs_rex()) {
7303 prefix(REX_RX);
7304 } else {
7305 prefix(REX_R);
7306 }
7307 }
7308 }
7309 }
7310
7311 void Assembler::prefixq(Address adr, Register src) {
7312 if (src->encoding() < 8) {
7313 if (adr.base_needs_rex()) {
7314 if (adr.index_needs_rex()) {
7315 prefix(REX_WXB);
7316 } else {
7317 prefix(REX_WB);
7318 }
7319 } else {
7320 if (adr.index_needs_rex()) {
7321 prefix(REX_WX);
7322 } else {
7323 prefix(REX_W);
7324 }
7325 }
7326 } else {
7327 if (adr.base_needs_rex()) {
7328 if (adr.index_needs_rex()) {
7329 prefix(REX_WRXB);
7330 } else {
7331 prefix(REX_WRB);
7332 }
7333 } else {
7334 if (adr.index_needs_rex()) {
7335 prefix(REX_WRX);
7336 } else {
7337 prefix(REX_WR);
7338 }
7339 }
7340 }
7341 }
7342
7343 void Assembler::prefix(Address adr, XMMRegister reg) {
7344 if (reg->encoding() < 8) {
7345 if (adr.base_needs_rex()) {
7346 if (adr.index_needs_rex()) {
7347 prefix(REX_XB);
7348 } else {
7349 prefix(REX_B);
7350 }
7351 } else {
7352 if (adr.index_needs_rex()) {
7353 prefix(REX_X);
7354 }
7355 }
7356 } else {
7357 if (adr.base_needs_rex()) {
7358 if (adr.index_needs_rex()) {
7359 prefix(REX_RXB);
7360 } else {
7361 prefix(REX_RB);
7362 }
7363 } else {
7364 if (adr.index_needs_rex()) {
7365 prefix(REX_RX);
7366 } else {
7367 prefix(REX_R);
7368 }
7369 }
7370 }
7371 }
7372
7373 void Assembler::prefixq(Address adr, XMMRegister src) {
7374 if (src->encoding() < 8) {
7375 if (adr.base_needs_rex()) {
7376 if (adr.index_needs_rex()) {
7377 prefix(REX_WXB);
7378 } else {
7379 prefix(REX_WB);
7380 }
7381 } else {
7382 if (adr.index_needs_rex()) {
7383 prefix(REX_WX);
7384 } else {
7385 prefix(REX_W);
7386 }
7387 }
7388 } else {
7389 if (adr.base_needs_rex()) {
7390 if (adr.index_needs_rex()) {
7391 prefix(REX_WRXB);
7392 } else {
7393 prefix(REX_WRB);
7394 }
7395 } else {
7396 if (adr.index_needs_rex()) {
7397 prefix(REX_WRX);
7398 } else {
7399 prefix(REX_WR);
7400 }
7401 }
7402 }
7403 }
7404
7405 void Assembler::adcq(Register dst, int32_t imm32) {
7406 (void) prefixq_and_encode(dst->encoding());
7407 emit_arith(0x81, 0xD0, dst, imm32);
7408 }
7409
7410 void Assembler::adcq(Register dst, Address src) {
7411 InstructionMark im(this);
7412 prefixq(src, dst);
7413 emit_int8(0x13);
7414 emit_operand(dst, src);
7415 }
7416
7417 void Assembler::adcq(Register dst, Register src) {
7418 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7419 emit_arith(0x13, 0xC0, dst, src);
7420 }
7421
7422 void Assembler::addq(Address dst, int32_t imm32) {
7423 InstructionMark im(this);
7424 prefixq(dst);
7425 emit_arith_operand(0x81, rax, dst,imm32);
7426 }
7427
7428 void Assembler::addq(Address dst, Register src) {
7429 InstructionMark im(this);
7430 prefixq(dst, src);
7431 emit_int8(0x01);
7432 emit_operand(src, dst);
7433 }
7434
7435 void Assembler::addq(Register dst, int32_t imm32) {
7436 (void) prefixq_and_encode(dst->encoding());
7437 emit_arith(0x81, 0xC0, dst, imm32);
7438 }
7439
7440 void Assembler::addq(Register dst, Address src) {
7441 InstructionMark im(this);
7442 prefixq(src, dst);
7443 emit_int8(0x03);
7444 emit_operand(dst, src);
7445 }
7446
7447 void Assembler::addq(Register dst, Register src) {
7448 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7449 emit_arith(0x03, 0xC0, dst, src);
7450 }
7451
7452 void Assembler::adcxq(Register dst, Register src) {
7453 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7454 emit_int8((unsigned char)0x66);
7455 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7456 emit_int8(0x0F);
7457 emit_int8(0x38);
7458 emit_int8((unsigned char)0xF6);
7459 emit_int8((unsigned char)(0xC0 | encode));
7460 }
7461
7462 void Assembler::adoxq(Register dst, Register src) {
7463 //assert(VM_Version::supports_adx(), "adx instructions not supported");
7464 emit_int8((unsigned char)0xF3);
7465 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7466 emit_int8(0x0F);
7467 emit_int8(0x38);
7468 emit_int8((unsigned char)0xF6);
7469 emit_int8((unsigned char)(0xC0 | encode));
7470 }
7471
7472 void Assembler::andq(Address dst, int32_t imm32) {
7473 InstructionMark im(this);
7474 prefixq(dst);
7475 emit_int8((unsigned char)0x81);
7476 emit_operand(rsp, dst, 4);
7477 emit_int32(imm32);
7478 }
7479
7480 void Assembler::andq(Register dst, int32_t imm32) {
7481 (void) prefixq_and_encode(dst->encoding());
7482 emit_arith(0x81, 0xE0, dst, imm32);
7483 }
7484
7485 void Assembler::andq(Register dst, Address src) {
7486 InstructionMark im(this);
7487 prefixq(src, dst);
7488 emit_int8(0x23);
7489 emit_operand(dst, src);
7490 }
7491
7492 void Assembler::andq(Register dst, Register src) {
7493 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7494 emit_arith(0x23, 0xC0, dst, src);
7495 }
7496
7497 void Assembler::andnq(Register dst, Register src1, Register src2) {
7498 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7499 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7500 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7501 emit_int8((unsigned char)0xF2);
7502 emit_int8((unsigned char)(0xC0 | encode));
7503 }
7504
7505 void Assembler::andnq(Register dst, Register src1, Address src2) {
7506 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7507 InstructionMark im(this);
7508 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7509 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7510 emit_int8((unsigned char)0xF2);
7511 emit_operand(dst, src2);
7512 }
7513
7514 void Assembler::bsfq(Register dst, Register src) {
7515 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7516 emit_int8(0x0F);
7517 emit_int8((unsigned char)0xBC);
7518 emit_int8((unsigned char)(0xC0 | encode));
7519 }
7520
7521 void Assembler::bsrq(Register dst, Register src) {
7522 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7523 emit_int8(0x0F);
7524 emit_int8((unsigned char)0xBD);
7525 emit_int8((unsigned char)(0xC0 | encode));
7526 }
7527
7528 void Assembler::bswapq(Register reg) {
7529 int encode = prefixq_and_encode(reg->encoding());
7530 emit_int8(0x0F);
7531 emit_int8((unsigned char)(0xC8 | encode));
7532 }
7533
7534 void Assembler::blsiq(Register dst, Register src) {
7535 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7536 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7537 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7538 emit_int8((unsigned char)0xF3);
7539 emit_int8((unsigned char)(0xC0 | encode));
7540 }
7541
7542 void Assembler::blsiq(Register dst, Address src) {
7543 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7544 InstructionMark im(this);
7545 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7546 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7547 emit_int8((unsigned char)0xF3);
7548 emit_operand(rbx, src);
7549 }
7550
7551 void Assembler::blsmskq(Register dst, Register src) {
7552 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7553 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7554 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7555 emit_int8((unsigned char)0xF3);
7556 emit_int8((unsigned char)(0xC0 | encode));
7557 }
7558
7559 void Assembler::blsmskq(Register dst, Address src) {
7560 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7561 InstructionMark im(this);
7562 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7563 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7564 emit_int8((unsigned char)0xF3);
7565 emit_operand(rdx, src);
7566 }
7567
7568 void Assembler::blsrq(Register dst, Register src) {
7569 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7570 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7571 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7572 emit_int8((unsigned char)0xF3);
7573 emit_int8((unsigned char)(0xC0 | encode));
7574 }
7575
7576 void Assembler::blsrq(Register dst, Address src) {
7577 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
7578 InstructionMark im(this);
7579 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7580 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
7581 emit_int8((unsigned char)0xF3);
7582 emit_operand(rcx, src);
7583 }
7584
7585 void Assembler::cdqq() {
7586 prefix(REX_W);
7587 emit_int8((unsigned char)0x99);
7588 }
7589
7590 void Assembler::clflush(Address adr) {
7591 prefix(adr);
7592 emit_int8(0x0F);
7593 emit_int8((unsigned char)0xAE);
7594 emit_operand(rdi, adr);
7595 }
7596
7597 void Assembler::cmovq(Condition cc, Register dst, Register src) {
7598 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7599 emit_int8(0x0F);
7600 emit_int8(0x40 | cc);
7601 emit_int8((unsigned char)(0xC0 | encode));
7602 }
7603
7604 void Assembler::cmovq(Condition cc, Register dst, Address src) {
7605 InstructionMark im(this);
7606 prefixq(src, dst);
7607 emit_int8(0x0F);
7608 emit_int8(0x40 | cc);
7609 emit_operand(dst, src);
7610 }
7611
7612 void Assembler::cmpq(Address dst, int32_t imm32) {
7613 InstructionMark im(this);
7614 prefixq(dst);
7615 emit_int8((unsigned char)0x81);
7616 emit_operand(rdi, dst, 4);
7617 emit_int32(imm32);
7618 }
7619
7620 void Assembler::cmpq(Register dst, int32_t imm32) {
7621 (void) prefixq_and_encode(dst->encoding());
7622 emit_arith(0x81, 0xF8, dst, imm32);
7623 }
7624
7625 void Assembler::cmpq(Address dst, Register src) {
7626 InstructionMark im(this);
7627 prefixq(dst, src);
7628 emit_int8(0x3B);
7629 emit_operand(src, dst);
7630 }
7631
7632 void Assembler::cmpq(Register dst, Register src) {
7633 (void) prefixq_and_encode(dst->encoding(), src->encoding());
7634 emit_arith(0x3B, 0xC0, dst, src);
7635 }
7636
7637 void Assembler::cmpq(Register dst, Address src) {
7638 InstructionMark im(this);
7639 prefixq(src, dst);
7640 emit_int8(0x3B);
7641 emit_operand(dst, src);
7642 }
7643
7644 void Assembler::cmpxchgq(Register reg, Address adr) {
7645 InstructionMark im(this);
7646 prefixq(adr, reg);
7647 emit_int8(0x0F);
7648 emit_int8((unsigned char)0xB1);
7649 emit_operand(reg, adr);
7650 }
7651
7652 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
7653 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7654 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7655 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7656 emit_int8(0x2A);
7657 emit_int8((unsigned char)(0xC0 | encode));
7658 }
7659
7660 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
7661 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7662 InstructionMark im(this);
7663 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7664 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7665 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7666 emit_int8(0x2A);
7667 emit_operand(dst, src);
7668 }
7669
7670 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
7671 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7672 InstructionMark im(this);
7673 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7674 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7675 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7676 emit_int8(0x2A);
7677 emit_operand(dst, src);
7678 }
7679
7680 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
7681 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7682 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7683 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
7684 emit_int8(0x2C);
7685 emit_int8((unsigned char)(0xC0 | encode));
7686 }
7687
7688 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
7689 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7690 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7691 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
7692 emit_int8(0x2C);
7693 emit_int8((unsigned char)(0xC0 | encode));
7694 }
7695
7696 void Assembler::decl(Register dst) {
7697 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7698 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
7699 int encode = prefix_and_encode(dst->encoding());
7700 emit_int8((unsigned char)0xFF);
7701 emit_int8((unsigned char)(0xC8 | encode));
7702 }
7703
7704 void Assembler::decq(Register dst) {
7705 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7706 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7707 int encode = prefixq_and_encode(dst->encoding());
7708 emit_int8((unsigned char)0xFF);
7709 emit_int8(0xC8 | encode);
7710 }
7711
7712 void Assembler::decq(Address dst) {
7713 // Don't use it directly. Use MacroAssembler::decrementq() instead.
7714 InstructionMark im(this);
7715 prefixq(dst);
7716 emit_int8((unsigned char)0xFF);
7717 emit_operand(rcx, dst);
7718 }
7719
7720 void Assembler::fxrstor(Address src) {
7721 prefixq(src);
7722 emit_int8(0x0F);
7723 emit_int8((unsigned char)0xAE);
7724 emit_operand(as_Register(1), src);
7725 }
7726
7727 void Assembler::xrstor(Address src) {
7728 prefixq(src);
7729 emit_int8(0x0F);
7730 emit_int8((unsigned char)0xAE);
7731 emit_operand(as_Register(5), src);
7732 }
7733
7734 void Assembler::fxsave(Address dst) {
7735 prefixq(dst);
7736 emit_int8(0x0F);
7737 emit_int8((unsigned char)0xAE);
7738 emit_operand(as_Register(0), dst);
7739 }
7740
7741 void Assembler::xsave(Address dst) {
7742 prefixq(dst);
7743 emit_int8(0x0F);
7744 emit_int8((unsigned char)0xAE);
7745 emit_operand(as_Register(4), dst);
7746 }
7747
7748 void Assembler::idivq(Register src) {
7749 int encode = prefixq_and_encode(src->encoding());
7750 emit_int8((unsigned char)0xF7);
7751 emit_int8((unsigned char)(0xF8 | encode));
7752 }
7753
7754 void Assembler::imulq(Register dst, Register src) {
7755 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7756 emit_int8(0x0F);
7757 emit_int8((unsigned char)0xAF);
7758 emit_int8((unsigned char)(0xC0 | encode));
7759 }
7760
7761 void Assembler::imulq(Register dst, Register src, int value) {
7762 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7763 if (is8bit(value)) {
7764 emit_int8(0x6B);
7765 emit_int8((unsigned char)(0xC0 | encode));
7766 emit_int8(value & 0xFF);
7767 } else {
7768 emit_int8(0x69);
7769 emit_int8((unsigned char)(0xC0 | encode));
7770 emit_int32(value);
7771 }
7772 }
7773
7774 void Assembler::imulq(Register dst, Address src) {
7775 InstructionMark im(this);
7776 prefixq(src, dst);
7777 emit_int8(0x0F);
7778 emit_int8((unsigned char) 0xAF);
7779 emit_operand(dst, src);
7780 }
7781
7782 void Assembler::incl(Register dst) {
7783 // Don't use it directly. Use MacroAssembler::incrementl() instead.
7784 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7785 int encode = prefix_and_encode(dst->encoding());
7786 emit_int8((unsigned char)0xFF);
7787 emit_int8((unsigned char)(0xC0 | encode));
7788 }
7789
7790 void Assembler::incq(Register dst) {
7791 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7792 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
7793 int encode = prefixq_and_encode(dst->encoding());
7794 emit_int8((unsigned char)0xFF);
7795 emit_int8((unsigned char)(0xC0 | encode));
7796 }
7797
7798 void Assembler::incq(Address dst) {
7799 // Don't use it directly. Use MacroAssembler::incrementq() instead.
7800 InstructionMark im(this);
7801 prefixq(dst);
7802 emit_int8((unsigned char)0xFF);
7803 emit_operand(rax, dst);
7804 }
7805
7806 void Assembler::lea(Register dst, Address src) {
7807 leaq(dst, src);
7808 }
7809
7810 void Assembler::leaq(Register dst, Address src) {
7811 InstructionMark im(this);
7812 prefixq(src, dst);
7813 emit_int8((unsigned char)0x8D);
7814 emit_operand(dst, src);
7815 }
7816
7817 void Assembler::mov64(Register dst, int64_t imm64) {
7818 InstructionMark im(this);
7819 int encode = prefixq_and_encode(dst->encoding());
7820 emit_int8((unsigned char)(0xB8 | encode));
7821 emit_int64(imm64);
7822 }
7823
7824 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
7825 InstructionMark im(this);
7826 int encode = prefixq_and_encode(dst->encoding());
7827 emit_int8(0xB8 | encode);
7828 emit_data64(imm64, rspec);
7829 }
7830
7831 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
7832 InstructionMark im(this);
7833 int encode = prefix_and_encode(dst->encoding());
7834 emit_int8((unsigned char)(0xB8 | encode));
7835 emit_data((int)imm32, rspec, narrow_oop_operand);
7836 }
7837
7838 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
7839 InstructionMark im(this);
7840 prefix(dst);
7841 emit_int8((unsigned char)0xC7);
7842 emit_operand(rax, dst, 4);
7843 emit_data((int)imm32, rspec, narrow_oop_operand);
7844 }
7845
7846 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7847 InstructionMark im(this);
7848 int encode = prefix_and_encode(src1->encoding());
7849 emit_int8((unsigned char)0x81);
7850 emit_int8((unsigned char)(0xF8 | encode));
7851 emit_data((int)imm32, rspec, narrow_oop_operand);
7852 }
7853
7854 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7855 InstructionMark im(this);
7856 prefix(src1);
7857 emit_int8((unsigned char)0x81);
7858 emit_operand(rax, src1, 4);
7859 emit_data((int)imm32, rspec, narrow_oop_operand);
7860 }
7861
7862 void Assembler::lzcntq(Register dst, Register src) {
7863 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
7864 emit_int8((unsigned char)0xF3);
7865 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7866 emit_int8(0x0F);
7867 emit_int8((unsigned char)0xBD);
7868 emit_int8((unsigned char)(0xC0 | encode));
7869 }
7870
7871 void Assembler::movdq(XMMRegister dst, Register src) {
7872 // table D-1 says MMX/SSE2
7873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7874 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7875 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7876 emit_int8(0x6E);
7877 emit_int8((unsigned char)(0xC0 | encode));
7878 }
7879
7880 void Assembler::movdq(Register dst, XMMRegister src) {
7881 // table D-1 says MMX/SSE2
7882 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7883 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7884 // swap src/dst to get correct prefix
7885 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7886 emit_int8(0x7E);
7887 emit_int8((unsigned char)(0xC0 | encode));
7888 }
7889
7890 void Assembler::movq(Register dst, Register src) {
7891 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7892 emit_int8((unsigned char)0x8B);
7893 emit_int8((unsigned char)(0xC0 | encode));
7894 }
7895
7896 void Assembler::movq(Register dst, Address src) {
7897 InstructionMark im(this);
7898 prefixq(src, dst);
7899 emit_int8((unsigned char)0x8B);
7900 emit_operand(dst, src);
7901 }
7902
7903 void Assembler::movq(Address dst, Register src) {
7904 InstructionMark im(this);
7905 prefixq(dst, src);
7906 emit_int8((unsigned char)0x89);
7907 emit_operand(src, dst);
7908 }
7909
7910 void Assembler::movsbq(Register dst, Address src) {
7911 InstructionMark im(this);
7912 prefixq(src, dst);
7913 emit_int8(0x0F);
7914 emit_int8((unsigned char)0xBE);
7915 emit_operand(dst, src);
7916 }
7917
7918 void Assembler::movsbq(Register dst, Register src) {
7919 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7920 emit_int8(0x0F);
7921 emit_int8((unsigned char)0xBE);
7922 emit_int8((unsigned char)(0xC0 | encode));
7923 }
7924
7925 void Assembler::movslq(Register dst, int32_t imm32) {
7926 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
7927 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
7928 // as a result we shouldn't use until tested at runtime...
7929 ShouldNotReachHere();
7930 InstructionMark im(this);
7931 int encode = prefixq_and_encode(dst->encoding());
7932 emit_int8((unsigned char)(0xC7 | encode));
7933 emit_int32(imm32);
7934 }
7935
7936 void Assembler::movslq(Address dst, int32_t imm32) {
7937 assert(is_simm32(imm32), "lost bits");
7938 InstructionMark im(this);
7939 prefixq(dst);
7940 emit_int8((unsigned char)0xC7);
7941 emit_operand(rax, dst, 4);
7942 emit_int32(imm32);
7943 }
7944
7945 void Assembler::movslq(Register dst, Address src) {
7946 InstructionMark im(this);
7947 prefixq(src, dst);
7948 emit_int8(0x63);
7949 emit_operand(dst, src);
7950 }
7951
7952 void Assembler::movslq(Register dst, Register src) {
7953 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7954 emit_int8(0x63);
7955 emit_int8((unsigned char)(0xC0 | encode));
7956 }
7957
7958 void Assembler::movswq(Register dst, Address src) {
7959 InstructionMark im(this);
7960 prefixq(src, dst);
7961 emit_int8(0x0F);
7962 emit_int8((unsigned char)0xBF);
7963 emit_operand(dst, src);
7964 }
7965
7966 void Assembler::movswq(Register dst, Register src) {
7967 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7968 emit_int8((unsigned char)0x0F);
7969 emit_int8((unsigned char)0xBF);
7970 emit_int8((unsigned char)(0xC0 | encode));
7971 }
7972
7973 void Assembler::movzbq(Register dst, Address src) {
7974 InstructionMark im(this);
7975 prefixq(src, dst);
7976 emit_int8((unsigned char)0x0F);
7977 emit_int8((unsigned char)0xB6);
7978 emit_operand(dst, src);
7979 }
7980
7981 void Assembler::movzbq(Register dst, Register src) {
7982 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7983 emit_int8(0x0F);
7984 emit_int8((unsigned char)0xB6);
7985 emit_int8(0xC0 | encode);
7986 }
7987
7988 void Assembler::movzwq(Register dst, Address src) {
7989 InstructionMark im(this);
7990 prefixq(src, dst);
7991 emit_int8((unsigned char)0x0F);
7992 emit_int8((unsigned char)0xB7);
7993 emit_operand(dst, src);
7994 }
7995
7996 void Assembler::movzwq(Register dst, Register src) {
7997 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
7998 emit_int8((unsigned char)0x0F);
7999 emit_int8((unsigned char)0xB7);
8000 emit_int8((unsigned char)(0xC0 | encode));
8001 }
8002
8003 void Assembler::mulq(Address src) {
8004 InstructionMark im(this);
8005 prefixq(src);
8006 emit_int8((unsigned char)0xF7);
8007 emit_operand(rsp, src);
8008 }
8009
8010 void Assembler::mulq(Register src) {
8011 int encode = prefixq_and_encode(src->encoding());
8012 emit_int8((unsigned char)0xF7);
8013 emit_int8((unsigned char)(0xE0 | encode));
8014 }
8015
8016 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
8017 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8018 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8019 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
8020 emit_int8((unsigned char)0xF6);
8021 emit_int8((unsigned char)(0xC0 | encode));
8022 }
8023
8024 void Assembler::negq(Register dst) {
8025 int encode = prefixq_and_encode(dst->encoding());
8026 emit_int8((unsigned char)0xF7);
8027 emit_int8((unsigned char)(0xD8 | encode));
8028 }
8029
8030 void Assembler::notq(Register dst) {
8031 int encode = prefixq_and_encode(dst->encoding());
8032 emit_int8((unsigned char)0xF7);
8033 emit_int8((unsigned char)(0xD0 | encode));
8034 }
8035
8036 void Assembler::orq(Address dst, int32_t imm32) {
8037 InstructionMark im(this);
8038 prefixq(dst);
8039 emit_int8((unsigned char)0x81);
8040 emit_operand(rcx, dst, 4);
8041 emit_int32(imm32);
8042 }
8043
8044 void Assembler::orq(Register dst, int32_t imm32) {
8045 (void) prefixq_and_encode(dst->encoding());
8046 emit_arith(0x81, 0xC8, dst, imm32);
8047 }
8048
8049 void Assembler::orq(Register dst, Address src) {
8050 InstructionMark im(this);
8051 prefixq(src, dst);
8052 emit_int8(0x0B);
8053 emit_operand(dst, src);
8054 }
8055
8056 void Assembler::orq(Register dst, Register src) {
8057 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8058 emit_arith(0x0B, 0xC0, dst, src);
8059 }
8060
8061 void Assembler::popa() { // 64bit
8062 movq(r15, Address(rsp, 0));
8063 movq(r14, Address(rsp, wordSize));
8064 movq(r13, Address(rsp, 2 * wordSize));
8065 movq(r12, Address(rsp, 3 * wordSize));
8066 movq(r11, Address(rsp, 4 * wordSize));
8067 movq(r10, Address(rsp, 5 * wordSize));
8068 movq(r9, Address(rsp, 6 * wordSize));
8069 movq(r8, Address(rsp, 7 * wordSize));
8070 movq(rdi, Address(rsp, 8 * wordSize));
8071 movq(rsi, Address(rsp, 9 * wordSize));
8072 movq(rbp, Address(rsp, 10 * wordSize));
8073 // skip rsp
8074 movq(rbx, Address(rsp, 12 * wordSize));
8075 movq(rdx, Address(rsp, 13 * wordSize));
8076 movq(rcx, Address(rsp, 14 * wordSize));
8077 movq(rax, Address(rsp, 15 * wordSize));
8078
8079 addq(rsp, 16 * wordSize);
8080 }
8081
8082 void Assembler::popcntq(Register dst, Address src) {
8083 assert(VM_Version::supports_popcnt(), "must support");
8084 InstructionMark im(this);
8085 emit_int8((unsigned char)0xF3);
8086 prefixq(src, dst);
8087 emit_int8((unsigned char)0x0F);
8088 emit_int8((unsigned char)0xB8);
8089 emit_operand(dst, src);
8090 }
8091
8092 void Assembler::popcntq(Register dst, Register src) {
8093 assert(VM_Version::supports_popcnt(), "must support");
8094 emit_int8((unsigned char)0xF3);
8095 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8096 emit_int8((unsigned char)0x0F);
8097 emit_int8((unsigned char)0xB8);
8098 emit_int8((unsigned char)(0xC0 | encode));
8099 }
8100
8101 void Assembler::popq(Address dst) {
8102 InstructionMark im(this);
8103 prefixq(dst);
8104 emit_int8((unsigned char)0x8F);
8105 emit_operand(rax, dst);
8106 }
8107
8108 void Assembler::pusha() { // 64bit
8109 // we have to store original rsp. ABI says that 128 bytes
8110 // below rsp are local scratch.
8111 movq(Address(rsp, -5 * wordSize), rsp);
8112
8113 subq(rsp, 16 * wordSize);
8114
8115 movq(Address(rsp, 15 * wordSize), rax);
8116 movq(Address(rsp, 14 * wordSize), rcx);
8117 movq(Address(rsp, 13 * wordSize), rdx);
8118 movq(Address(rsp, 12 * wordSize), rbx);
8119 // skip rsp
8120 movq(Address(rsp, 10 * wordSize), rbp);
8121 movq(Address(rsp, 9 * wordSize), rsi);
8122 movq(Address(rsp, 8 * wordSize), rdi);
8123 movq(Address(rsp, 7 * wordSize), r8);
8124 movq(Address(rsp, 6 * wordSize), r9);
8125 movq(Address(rsp, 5 * wordSize), r10);
8126 movq(Address(rsp, 4 * wordSize), r11);
8127 movq(Address(rsp, 3 * wordSize), r12);
8128 movq(Address(rsp, 2 * wordSize), r13);
8129 movq(Address(rsp, wordSize), r14);
8130 movq(Address(rsp, 0), r15);
8131 }
8132
8133 void Assembler::pushq(Address src) {
8134 InstructionMark im(this);
8135 prefixq(src);
8136 emit_int8((unsigned char)0xFF);
8137 emit_operand(rsi, src);
8138 }
8139
8140 void Assembler::rclq(Register dst, int imm8) {
8141 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8142 int encode = prefixq_and_encode(dst->encoding());
8143 if (imm8 == 1) {
8144 emit_int8((unsigned char)0xD1);
8145 emit_int8((unsigned char)(0xD0 | encode));
8146 } else {
8147 emit_int8((unsigned char)0xC1);
8148 emit_int8((unsigned char)(0xD0 | encode));
8149 emit_int8(imm8);
8150 }
8151 }
8152
8153 void Assembler::rcrq(Register dst, int imm8) {
8154 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8155 int encode = prefixq_and_encode(dst->encoding());
8156 if (imm8 == 1) {
8157 emit_int8((unsigned char)0xD1);
8158 emit_int8((unsigned char)(0xD8 | encode));
8159 } else {
8160 emit_int8((unsigned char)0xC1);
8161 emit_int8((unsigned char)(0xD8 | encode));
8162 emit_int8(imm8);
8163 }
8164 }
8165
8166 void Assembler::rorq(Register dst, int imm8) {
8167 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8168 int encode = prefixq_and_encode(dst->encoding());
8169 if (imm8 == 1) {
8170 emit_int8((unsigned char)0xD1);
8171 emit_int8((unsigned char)(0xC8 | encode));
8172 } else {
8173 emit_int8((unsigned char)0xC1);
8174 emit_int8((unsigned char)(0xc8 | encode));
8175 emit_int8(imm8);
8176 }
8177 }
8178
8179 void Assembler::rorxq(Register dst, Register src, int imm8) {
8180 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
8181 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8182 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
8183 emit_int8((unsigned char)0xF0);
8184 emit_int8((unsigned char)(0xC0 | encode));
8185 emit_int8(imm8);
8186 }
8187
8188 void Assembler::sarq(Register dst, int imm8) {
8189 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8190 int encode = prefixq_and_encode(dst->encoding());
8191 if (imm8 == 1) {
8192 emit_int8((unsigned char)0xD1);
8193 emit_int8((unsigned char)(0xF8 | encode));
8194 } else {
8195 emit_int8((unsigned char)0xC1);
8196 emit_int8((unsigned char)(0xF8 | encode));
8197 emit_int8(imm8);
8198 }
8199 }
8200
8201 void Assembler::sarq(Register dst) {
8202 int encode = prefixq_and_encode(dst->encoding());
8203 emit_int8((unsigned char)0xD3);
8204 emit_int8((unsigned char)(0xF8 | encode));
8205 }
8206
8207 void Assembler::sbbq(Address dst, int32_t imm32) {
8208 InstructionMark im(this);
8209 prefixq(dst);
8210 emit_arith_operand(0x81, rbx, dst, imm32);
8211 }
8212
8213 void Assembler::sbbq(Register dst, int32_t imm32) {
8214 (void) prefixq_and_encode(dst->encoding());
8215 emit_arith(0x81, 0xD8, dst, imm32);
8216 }
8217
8218 void Assembler::sbbq(Register dst, Address src) {
8219 InstructionMark im(this);
8220 prefixq(src, dst);
8221 emit_int8(0x1B);
8222 emit_operand(dst, src);
8223 }
8224
8225 void Assembler::sbbq(Register dst, Register src) {
8226 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8227 emit_arith(0x1B, 0xC0, dst, src);
8228 }
8229
8230 void Assembler::shlq(Register dst, int imm8) {
8231 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8232 int encode = prefixq_and_encode(dst->encoding());
8233 if (imm8 == 1) {
8234 emit_int8((unsigned char)0xD1);
8235 emit_int8((unsigned char)(0xE0 | encode));
8236 } else {
8237 emit_int8((unsigned char)0xC1);
8238 emit_int8((unsigned char)(0xE0 | encode));
8239 emit_int8(imm8);
8240 }
8241 }
8242
8243 void Assembler::shlq(Register dst) {
8244 int encode = prefixq_and_encode(dst->encoding());
8245 emit_int8((unsigned char)0xD3);
8246 emit_int8((unsigned char)(0xE0 | encode));
8247 }
8248
8249 void Assembler::shrq(Register dst, int imm8) {
8250 assert(isShiftCount(imm8 >> 1), "illegal shift count");
8251 int encode = prefixq_and_encode(dst->encoding());
8252 emit_int8((unsigned char)0xC1);
8253 emit_int8((unsigned char)(0xE8 | encode));
8254 emit_int8(imm8);
8255 }
8256
8257 void Assembler::shrq(Register dst) {
8258 int encode = prefixq_and_encode(dst->encoding());
8259 emit_int8((unsigned char)0xD3);
8260 emit_int8(0xE8 | encode);
8261 }
8262
8263 void Assembler::subq(Address dst, int32_t imm32) {
8264 InstructionMark im(this);
8265 prefixq(dst);
8266 emit_arith_operand(0x81, rbp, dst, imm32);
8267 }
8268
8269 void Assembler::subq(Address dst, Register src) {
8270 InstructionMark im(this);
8271 prefixq(dst, src);
8272 emit_int8(0x29);
8273 emit_operand(src, dst);
8274 }
8275
8276 void Assembler::subq(Register dst, int32_t imm32) {
8277 (void) prefixq_and_encode(dst->encoding());
8278 emit_arith(0x81, 0xE8, dst, imm32);
8279 }
8280
8281 // Force generation of a 4 byte immediate value even if it fits into 8bit
8282 void Assembler::subq_imm32(Register dst, int32_t imm32) {
8283 (void) prefixq_and_encode(dst->encoding());
8284 emit_arith_imm32(0x81, 0xE8, dst, imm32);
8285 }
8286
8287 void Assembler::subq(Register dst, Address src) {
8288 InstructionMark im(this);
8289 prefixq(src, dst);
8290 emit_int8(0x2B);
8291 emit_operand(dst, src);
8292 }
8293
8294 void Assembler::subq(Register dst, Register src) {
8295 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8296 emit_arith(0x2B, 0xC0, dst, src);
8297 }
8298
8299 void Assembler::testq(Register dst, int32_t imm32) {
8300 // not using emit_arith because test
8301 // doesn't support sign-extension of
8302 // 8bit operands
8303 int encode = dst->encoding();
8304 if (encode == 0) {
8305 prefix(REX_W);
8306 emit_int8((unsigned char)0xA9);
8307 } else {
8308 encode = prefixq_and_encode(encode);
8309 emit_int8((unsigned char)0xF7);
8310 emit_int8((unsigned char)(0xC0 | encode));
8311 }
8312 emit_int32(imm32);
8313 }
8314
8315 void Assembler::testq(Register dst, Register src) {
8316 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8317 emit_arith(0x85, 0xC0, dst, src);
8318 }
8319
8320 void Assembler::xaddq(Address dst, Register src) {
8321 InstructionMark im(this);
8322 prefixq(dst, src);
8323 emit_int8(0x0F);
8324 emit_int8((unsigned char)0xC1);
8325 emit_operand(src, dst);
8326 }
8327
8328 void Assembler::xchgq(Register dst, Address src) {
8329 InstructionMark im(this);
8330 prefixq(src, dst);
8331 emit_int8((unsigned char)0x87);
8332 emit_operand(dst, src);
8333 }
8334
8335 void Assembler::xchgq(Register dst, Register src) {
8336 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
8337 emit_int8((unsigned char)0x87);
8338 emit_int8((unsigned char)(0xc0 | encode));
8339 }
8340
8341 void Assembler::xorq(Register dst, Register src) {
8342 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8343 emit_arith(0x33, 0xC0, dst, src);
8344 }
8345
8346 void Assembler::xorq(Register dst, Address src) {
8347 InstructionMark im(this);
8348 prefixq(src, dst);
8349 emit_int8(0x33);
8350 emit_operand(dst, src);
8351 }
8352
8353 #endif // !LP64