src/cpu/aarch64/vm/aarch64.ad

@@ -2845,10 +2845,24 @@
 
   uint MachNopNode::size(PhaseRegAlloc*) const {
     return _count * NativeInstruction::instruction_size;
   }
 
+#ifndef PRODUCT
+  void MachMskNode::format(PhaseRegAlloc*, outputStream* st) const {
+    // TBD
+  }
+#endif
+
+  void MachMskNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
+    // TBD
+  }
+
+  uint MachMskNode::size(PhaseRegAlloc* ra_) const {
+    return 0; // TBD
+  }
+
 //=============================================================================
 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
 
 int Compile::ConstantTable::calculate_table_base_offset() const {
   return 0;  // absolute addressing, no offset

@@ -3344,10 +3358,14 @@
   // Add rules here.
 
   return ret_value;  // Per default match rules are supported.
 }
 
+const bool Matcher::has_predicated_vectors(void) {
+  return false;
+}
+
 const int Matcher::float_pressure(int default_pressure_threshold) {
   return default_pressure_threshold;
 }
 
 int Matcher::regnum_to_fpu_offset(int regnum)