1 //
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   3 // Copyright (c) 2012, 2016 SAP SE. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
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  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 //
  25 
  26 //
  27 // PPC64 Architecture Description File
  28 //
  29 
  30 //----------REGISTER DEFINITION BLOCK------------------------------------------
  31 // This information is used by the matcher and the register allocator to
  32 // describe individual registers and classes of registers within the target
  33 // architecture.
  34 register %{
  35 //----------Architecture Description Register Definitions----------------------
  36 // General Registers
  37 // "reg_def"  name (register save type, C convention save type,
  38 //                  ideal register type, encoding);
  39 //
  40 // Register Save Types:
  41 //
  42 //   NS  = No-Save:     The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method, &
  44 //                      that they do not need to be saved at call sites.
  45 //
  46 //   SOC = Save-On-Call: The register allocator assumes that these registers
  47 //                      can be used without saving upon entry to the method,
  48 //                      but that they must be saved at call sites.
  49 //                      These are called "volatiles" on ppc.
  50 //
  51 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, but they do not need to be saved at call
  54 //                      sites.
  55 //                      These are called "nonvolatiles" on ppc.
  56 //
  57 //   AS  = Always-Save:   The register allocator assumes that these registers
  58 //                      must be saved before using them upon entry to the
  59 //                      method, & that they must be saved at call sites.
  60 //
  61 // Ideal Register Type is used to determine how to save & restore a
  62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  64 //
  65 // The encoding number is the actual bit-pattern placed into the opcodes.
  66 //
  67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
  68 // Supplement Version 1.7 as of 2003-10-29.
  69 //
  70 // For each 64-bit register we must define two registers: the register
  71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
  72 // e.g. R3_H, which is needed by the allocator, but is not used
  73 // for stores, loads, etc.
  74 
  75 // ----------------------------
  76 // Integer/Long Registers
  77 // ----------------------------
  78 
  79   // PPC64 has 32 64-bit integer registers.
  80 
  81   // types: v = volatile, nv = non-volatile, s = system
  82   reg_def R0   ( SOC, SOC, Op_RegI,  0, R0->as_VMReg()         );  // v   used in prologs
  83   reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
  84   reg_def R1   ( NS,  NS,  Op_RegI,  1, R1->as_VMReg()         );  // s   SP
  85   reg_def R1_H ( NS,  NS,  Op_RegI, 99, R1->as_VMReg()->next() );
  86   reg_def R2   ( SOC, SOC, Op_RegI,  2, R2->as_VMReg()         );  // v   TOC
  87   reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
  88   reg_def R3   ( SOC, SOC, Op_RegI,  3, R3->as_VMReg()         );  // v   iarg1 & iret
  89   reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
  90   reg_def R4   ( SOC, SOC, Op_RegI,  4, R4->as_VMReg()         );  //     iarg2
  91   reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
  92   reg_def R5   ( SOC, SOC, Op_RegI,  5, R5->as_VMReg()         );  // v   iarg3
  93   reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
  94   reg_def R6   ( SOC, SOC, Op_RegI,  6, R6->as_VMReg()         );  // v   iarg4
  95   reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
  96   reg_def R7   ( SOC, SOC, Op_RegI,  7, R7->as_VMReg()         );  // v   iarg5
  97   reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
  98   reg_def R8   ( SOC, SOC, Op_RegI,  8, R8->as_VMReg()         );  // v   iarg6
  99   reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
 100   reg_def R9   ( SOC, SOC, Op_RegI,  9, R9->as_VMReg()         );  // v   iarg7
 101   reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
 102   reg_def R10  ( SOC, SOC, Op_RegI, 10, R10->as_VMReg()        );  // v   iarg8
 103   reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
 104   reg_def R11  ( SOC, SOC, Op_RegI, 11, R11->as_VMReg()        );  // v   ENV / scratch
 105   reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
 106   reg_def R12  ( SOC, SOC, Op_RegI, 12, R12->as_VMReg()        );  // v   scratch
 107   reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
 108   reg_def R13  ( NS,  NS,  Op_RegI, 13, R13->as_VMReg()        );  // s   system thread id
 109   reg_def R13_H( NS,  NS,  Op_RegI, 99, R13->as_VMReg()->next());
 110   reg_def R14  ( SOC, SOE, Op_RegI, 14, R14->as_VMReg()        );  // nv
 111   reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
 112   reg_def R15  ( SOC, SOE, Op_RegI, 15, R15->as_VMReg()        );  // nv
 113   reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
 114   reg_def R16  ( SOC, SOE, Op_RegI, 16, R16->as_VMReg()        );  // nv
 115   reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
 116   reg_def R17  ( SOC, SOE, Op_RegI, 17, R17->as_VMReg()        );  // nv
 117   reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
 118   reg_def R18  ( SOC, SOE, Op_RegI, 18, R18->as_VMReg()        );  // nv
 119   reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
 120   reg_def R19  ( SOC, SOE, Op_RegI, 19, R19->as_VMReg()        );  // nv
 121   reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
 122   reg_def R20  ( SOC, SOE, Op_RegI, 20, R20->as_VMReg()        );  // nv
 123   reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
 124   reg_def R21  ( SOC, SOE, Op_RegI, 21, R21->as_VMReg()        );  // nv
 125   reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
 126   reg_def R22  ( SOC, SOE, Op_RegI, 22, R22->as_VMReg()        );  // nv
 127   reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
 128   reg_def R23  ( SOC, SOE, Op_RegI, 23, R23->as_VMReg()        );  // nv
 129   reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
 130   reg_def R24  ( SOC, SOE, Op_RegI, 24, R24->as_VMReg()        );  // nv
 131   reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
 132   reg_def R25  ( SOC, SOE, Op_RegI, 25, R25->as_VMReg()        );  // nv
 133   reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
 134   reg_def R26  ( SOC, SOE, Op_RegI, 26, R26->as_VMReg()        );  // nv
 135   reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
 136   reg_def R27  ( SOC, SOE, Op_RegI, 27, R27->as_VMReg()        );  // nv
 137   reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
 138   reg_def R28  ( SOC, SOE, Op_RegI, 28, R28->as_VMReg()        );  // nv
 139   reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
 140   reg_def R29  ( SOC, SOE, Op_RegI, 29, R29->as_VMReg()        );  // nv
 141   reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
 142   reg_def R30  ( SOC, SOE, Op_RegI, 30, R30->as_VMReg()        );  // nv
 143   reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
 144   reg_def R31  ( SOC, SOE, Op_RegI, 31, R31->as_VMReg()        );  // nv
 145   reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
 146 
 147 
 148 // ----------------------------
 149 // Float/Double Registers
 150 // ----------------------------
 151 
 152   // Double Registers
 153   // The rules of ADL require that double registers be defined in pairs.
 154   // Each pair must be two 32-bit values, but not necessarily a pair of
 155   // single float registers. In each pair, ADLC-assigned register numbers
 156   // must be adjacent, with the lower number even. Finally, when the
 157   // CPU stores such a register pair to memory, the word associated with
 158   // the lower ADLC-assigned number must be stored to the lower address.
 159 
 160   // PPC64 has 32 64-bit floating-point registers. Each can store a single
 161   // or double precision floating-point value.
 162 
 163   // types: v = volatile, nv = non-volatile, s = system
 164   reg_def F0   ( SOC, SOC, Op_RegF,  0, F0->as_VMReg()         );  // v   scratch
 165   reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
 166   reg_def F1   ( SOC, SOC, Op_RegF,  1, F1->as_VMReg()         );  // v   farg1 & fret
 167   reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
 168   reg_def F2   ( SOC, SOC, Op_RegF,  2, F2->as_VMReg()         );  // v   farg2
 169   reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
 170   reg_def F3   ( SOC, SOC, Op_RegF,  3, F3->as_VMReg()         );  // v   farg3
 171   reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
 172   reg_def F4   ( SOC, SOC, Op_RegF,  4, F4->as_VMReg()         );  // v   farg4
 173   reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
 174   reg_def F5   ( SOC, SOC, Op_RegF,  5, F5->as_VMReg()         );  // v   farg5
 175   reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
 176   reg_def F6   ( SOC, SOC, Op_RegF,  6, F6->as_VMReg()         );  // v   farg6
 177   reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
 178   reg_def F7   ( SOC, SOC, Op_RegF,  7, F7->as_VMReg()         );  // v   farg7
 179   reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
 180   reg_def F8   ( SOC, SOC, Op_RegF,  8, F8->as_VMReg()         );  // v   farg8
 181   reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
 182   reg_def F9   ( SOC, SOC, Op_RegF,  9, F9->as_VMReg()         );  // v   farg9
 183   reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
 184   reg_def F10  ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()        );  // v   farg10
 185   reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
 186   reg_def F11  ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()        );  // v   farg11
 187   reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
 188   reg_def F12  ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()        );  // v   farg12
 189   reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
 190   reg_def F13  ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()        );  // v   farg13
 191   reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
 192   reg_def F14  ( SOC, SOE, Op_RegF, 14, F14->as_VMReg()        );  // nv
 193   reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
 194   reg_def F15  ( SOC, SOE, Op_RegF, 15, F15->as_VMReg()        );  // nv
 195   reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
 196   reg_def F16  ( SOC, SOE, Op_RegF, 16, F16->as_VMReg()        );  // nv
 197   reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
 198   reg_def F17  ( SOC, SOE, Op_RegF, 17, F17->as_VMReg()        );  // nv
 199   reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
 200   reg_def F18  ( SOC, SOE, Op_RegF, 18, F18->as_VMReg()        );  // nv
 201   reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
 202   reg_def F19  ( SOC, SOE, Op_RegF, 19, F19->as_VMReg()        );  // nv
 203   reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
 204   reg_def F20  ( SOC, SOE, Op_RegF, 20, F20->as_VMReg()        );  // nv
 205   reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
 206   reg_def F21  ( SOC, SOE, Op_RegF, 21, F21->as_VMReg()        );  // nv
 207   reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
 208   reg_def F22  ( SOC, SOE, Op_RegF, 22, F22->as_VMReg()        );  // nv
 209   reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
 210   reg_def F23  ( SOC, SOE, Op_RegF, 23, F23->as_VMReg()        );  // nv
 211   reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
 212   reg_def F24  ( SOC, SOE, Op_RegF, 24, F24->as_VMReg()        );  // nv
 213   reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
 214   reg_def F25  ( SOC, SOE, Op_RegF, 25, F25->as_VMReg()        );  // nv
 215   reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
 216   reg_def F26  ( SOC, SOE, Op_RegF, 26, F26->as_VMReg()        );  // nv
 217   reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
 218   reg_def F27  ( SOC, SOE, Op_RegF, 27, F27->as_VMReg()        );  // nv
 219   reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
 220   reg_def F28  ( SOC, SOE, Op_RegF, 28, F28->as_VMReg()        );  // nv
 221   reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
 222   reg_def F29  ( SOC, SOE, Op_RegF, 29, F29->as_VMReg()        );  // nv
 223   reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
 224   reg_def F30  ( SOC, SOE, Op_RegF, 30, F30->as_VMReg()        );  // nv
 225   reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
 226   reg_def F31  ( SOC, SOE, Op_RegF, 31, F31->as_VMReg()        );  // nv
 227   reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
 228 
 229 // ----------------------------
 230 // Special Registers
 231 // ----------------------------
 232 
 233 // Condition Codes Flag Registers
 234 
 235   // PPC64 has 8 condition code "registers" which are all contained
 236   // in the CR register.
 237 
 238   // types: v = volatile, nv = non-volatile, s = system
 239   reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg());  // v
 240   reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg());  // v
 241   reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg());  // nv
 242   reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg());  // nv
 243   reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg());  // nv
 244   reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg());  // v
 245   reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg());  // v
 246   reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg());  // v
 247 
 248   // Special registers of PPC64
 249 
 250   reg_def SR_XER(    SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg());     // v
 251   reg_def SR_LR(     SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg());      // v
 252   reg_def SR_CTR(    SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg());     // v
 253   reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg());  // v
 254   reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
 255   reg_def SR_PPR(    SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg());     // v
 256 
 257 
 258 // ----------------------------
 259 // Specify priority of register selection within phases of register
 260 // allocation. Highest priority is first. A useful heuristic is to
 261 // give registers a low priority when they are required by machine
 262 // instructions, like EAX and EDX on I486, and choose no-save registers
 263 // before save-on-call, & save-on-call before save-on-entry. Registers
 264 // which participate in fixed calling sequences should come last.
 265 // Registers which are used as pairs must fall on an even boundary.
 266 
 267 // It's worth about 1% on SPEC geomean to get this right.
 268 
 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
 271 // R3_num. Therefore, R3_num may not be (and in reality is not)
 272 // the same as R3->encoding()! Furthermore, we cannot make any
 273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
 274 // Additionally, the function
 275 //   static enum RC rc_class(OptoReg::Name reg )
 276 // maps a given <register>_num value to its chunk type (except for flags)
 277 // and its current implementation relies on chunk0 and chunk1 having a
 278 // size of 64 each.
 279 
 280 // If you change this allocation class, please have a look at the
 281 // default values for the parameters RoundRobinIntegerRegIntervalStart
 282 // and RoundRobinFloatRegIntervalStart
 283 
 284 alloc_class chunk0 (
 285   // Chunk0 contains *all* 64 integer registers halves.
 286 
 287   // "non-volatile" registers
 288   R14, R14_H,
 289   R15, R15_H,
 290   R17, R17_H,
 291   R18, R18_H,
 292   R19, R19_H,
 293   R20, R20_H,
 294   R21, R21_H,
 295   R22, R22_H,
 296   R23, R23_H,
 297   R24, R24_H,
 298   R25, R25_H,
 299   R26, R26_H,
 300   R27, R27_H,
 301   R28, R28_H,
 302   R29, R29_H,
 303   R30, R30_H,
 304   R31, R31_H,
 305 
 306   // scratch/special registers
 307   R11, R11_H,
 308   R12, R12_H,
 309 
 310   // argument registers
 311   R10, R10_H,
 312   R9,  R9_H,
 313   R8,  R8_H,
 314   R7,  R7_H,
 315   R6,  R6_H,
 316   R5,  R5_H,
 317   R4,  R4_H,
 318   R3,  R3_H,
 319 
 320   // special registers, not available for allocation
 321   R16, R16_H,     // R16_thread
 322   R13, R13_H,     // system thread id
 323   R2,  R2_H,      // may be used for TOC
 324   R1,  R1_H,      // SP
 325   R0,  R0_H       // R0 (scratch)
 326 );
 327 
 328 // If you change this allocation class, please have a look at the
 329 // default values for the parameters RoundRobinIntegerRegIntervalStart
 330 // and RoundRobinFloatRegIntervalStart
 331 
 332 alloc_class chunk1 (
 333   // Chunk1 contains *all* 64 floating-point registers halves.
 334 
 335   // scratch register
 336   F0,  F0_H,
 337 
 338   // argument registers
 339   F13, F13_H,
 340   F12, F12_H,
 341   F11, F11_H,
 342   F10, F10_H,
 343   F9,  F9_H,
 344   F8,  F8_H,
 345   F7,  F7_H,
 346   F6,  F6_H,
 347   F5,  F5_H,
 348   F4,  F4_H,
 349   F3,  F3_H,
 350   F2,  F2_H,
 351   F1,  F1_H,
 352 
 353   // non-volatile registers
 354   F14, F14_H,
 355   F15, F15_H,
 356   F16, F16_H,
 357   F17, F17_H,
 358   F18, F18_H,
 359   F19, F19_H,
 360   F20, F20_H,
 361   F21, F21_H,
 362   F22, F22_H,
 363   F23, F23_H,
 364   F24, F24_H,
 365   F25, F25_H,
 366   F26, F26_H,
 367   F27, F27_H,
 368   F28, F28_H,
 369   F29, F29_H,
 370   F30, F30_H,
 371   F31, F31_H
 372 );
 373 
 374 alloc_class chunk2 (
 375   // Chunk2 contains *all* 8 condition code registers.
 376 
 377   CCR0,
 378   CCR1,
 379   CCR2,
 380   CCR3,
 381   CCR4,
 382   CCR5,
 383   CCR6,
 384   CCR7
 385 );
 386 
 387 alloc_class chunk3 (
 388   // special registers
 389   // These registers are not allocated, but used for nodes generated by postalloc expand.
 390   SR_XER,
 391   SR_LR,
 392   SR_CTR,
 393   SR_VRSAVE,
 394   SR_SPEFSCR,
 395   SR_PPR
 396 );
 397 
 398 //-------Architecture Description Register Classes-----------------------
 399 
 400 // Several register classes are automatically defined based upon
 401 // information in this architecture description.
 402 
 403 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 404 // 2) reg_class compiler_method_oop_reg    ( as defined in frame section )
 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 407 //
 408 
 409 // ----------------------------
 410 // 32 Bit Register Classes
 411 // ----------------------------
 412 
 413 // We specify registers twice, once as read/write, and once read-only.
 414 // We use the read-only registers for source operands. With this, we
 415 // can include preset read only registers in this class, as a hard-coded
 416 // '0'-register. (We used to simulate this on ppc.)
 417 
 418 // 32 bit registers that can be read and written i.e. these registers
 419 // can be dest (or src) of normal instructions.
 420 reg_class bits32_reg_rw(
 421 /*R0*/              // R0
 422 /*R1*/              // SP
 423   R2,               // TOC
 424   R3,
 425   R4,
 426   R5,
 427   R6,
 428   R7,
 429   R8,
 430   R9,
 431   R10,
 432   R11,
 433   R12,
 434 /*R13*/             // system thread id
 435   R14,
 436   R15,
 437 /*R16*/             // R16_thread
 438   R17,
 439   R18,
 440   R19,
 441   R20,
 442   R21,
 443   R22,
 444   R23,
 445   R24,
 446   R25,
 447   R26,
 448   R27,
 449   R28,
 450 /*R29,*/             // global TOC
 451   R30,
 452   R31
 453 );
 454 
 455 // 32 bit registers that can only be read i.e. these registers can
 456 // only be src of all instructions.
 457 reg_class bits32_reg_ro(
 458 /*R0*/              // R0
 459 /*R1*/              // SP
 460   R2                // TOC
 461   R3,
 462   R4,
 463   R5,
 464   R6,
 465   R7,
 466   R8,
 467   R9,
 468   R10,
 469   R11,
 470   R12,
 471 /*R13*/             // system thread id
 472   R14,
 473   R15,
 474 /*R16*/             // R16_thread
 475   R17,
 476   R18,
 477   R19,
 478   R20,
 479   R21,
 480   R22,
 481   R23,
 482   R24,
 483   R25,
 484   R26,
 485   R27,
 486   R28,
 487 /*R29,*/
 488   R30,
 489   R31
 490 );
 491 
 492 reg_class rscratch1_bits32_reg(R11);
 493 reg_class rscratch2_bits32_reg(R12);
 494 reg_class rarg1_bits32_reg(R3);
 495 reg_class rarg2_bits32_reg(R4);
 496 reg_class rarg3_bits32_reg(R5);
 497 reg_class rarg4_bits32_reg(R6);
 498 
 499 // ----------------------------
 500 // 64 Bit Register Classes
 501 // ----------------------------
 502 // 64-bit build means 64-bit pointers means hi/lo pairs
 503 
 504 reg_class rscratch1_bits64_reg(R11_H, R11);
 505 reg_class rscratch2_bits64_reg(R12_H, R12);
 506 reg_class rarg1_bits64_reg(R3_H, R3);
 507 reg_class rarg2_bits64_reg(R4_H, R4);
 508 reg_class rarg3_bits64_reg(R5_H, R5);
 509 reg_class rarg4_bits64_reg(R6_H, R6);
 510 // Thread register, 'written' by tlsLoadP, see there.
 511 reg_class thread_bits64_reg(R16_H, R16);
 512 
 513 reg_class r19_bits64_reg(R19_H, R19);
 514 
 515 // 64 bit registers that can be read and written i.e. these registers
 516 // can be dest (or src) of normal instructions.
 517 reg_class bits64_reg_rw(
 518 /*R0_H,  R0*/     // R0
 519 /*R1_H,  R1*/     // SP
 520   R2_H,  R2,      // TOC
 521   R3_H,  R3,
 522   R4_H,  R4,
 523   R5_H,  R5,
 524   R6_H,  R6,
 525   R7_H,  R7,
 526   R8_H,  R8,
 527   R9_H,  R9,
 528   R10_H, R10,
 529   R11_H, R11,
 530   R12_H, R12,
 531 /*R13_H, R13*/   // system thread id
 532   R14_H, R14,
 533   R15_H, R15,
 534 /*R16_H, R16*/   // R16_thread
 535   R17_H, R17,
 536   R18_H, R18,
 537   R19_H, R19,
 538   R20_H, R20,
 539   R21_H, R21,
 540   R22_H, R22,
 541   R23_H, R23,
 542   R24_H, R24,
 543   R25_H, R25,
 544   R26_H, R26,
 545   R27_H, R27,
 546   R28_H, R28,
 547 /*R29_H, R29,*/
 548   R30_H, R30,
 549   R31_H, R31
 550 );
 551 
 552 // 64 bit registers used excluding r2, r11 and r12
 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
 554 // r2, r11 and r12 internally.
 555 reg_class bits64_reg_leaf_call(
 556 /*R0_H,  R0*/     // R0
 557 /*R1_H,  R1*/     // SP
 558 /*R2_H,  R2*/     // TOC
 559   R3_H,  R3,
 560   R4_H,  R4,
 561   R5_H,  R5,
 562   R6_H,  R6,
 563   R7_H,  R7,
 564   R8_H,  R8,
 565   R9_H,  R9,
 566   R10_H, R10,
 567 /*R11_H, R11*/
 568 /*R12_H, R12*/
 569 /*R13_H, R13*/   // system thread id
 570   R14_H, R14,
 571   R15_H, R15,
 572 /*R16_H, R16*/   // R16_thread
 573   R17_H, R17,
 574   R18_H, R18,
 575   R19_H, R19,
 576   R20_H, R20,
 577   R21_H, R21,
 578   R22_H, R22,
 579   R23_H, R23,
 580   R24_H, R24,
 581   R25_H, R25,
 582   R26_H, R26,
 583   R27_H, R27,
 584   R28_H, R28,
 585 /*R29_H, R29,*/
 586   R30_H, R30,
 587   R31_H, R31
 588 );
 589 
 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
 591 // which uses r19 as inline cache internally and expanded LeafCall which uses
 592 // r2, r11 and r12 internally.
 593 reg_class bits64_constant_table_base(
 594 /*R0_H,  R0*/     // R0
 595 /*R1_H,  R1*/     // SP
 596 /*R2_H,  R2*/     // TOC
 597   R3_H,  R3,
 598   R4_H,  R4,
 599   R5_H,  R5,
 600   R6_H,  R6,
 601   R7_H,  R7,
 602   R8_H,  R8,
 603   R9_H,  R9,
 604   R10_H, R10,
 605 /*R11_H, R11*/
 606 /*R12_H, R12*/
 607 /*R13_H, R13*/   // system thread id
 608   R14_H, R14,
 609   R15_H, R15,
 610 /*R16_H, R16*/   // R16_thread
 611   R17_H, R17,
 612   R18_H, R18,
 613 /*R19_H, R19*/
 614   R20_H, R20,
 615   R21_H, R21,
 616   R22_H, R22,
 617   R23_H, R23,
 618   R24_H, R24,
 619   R25_H, R25,
 620   R26_H, R26,
 621   R27_H, R27,
 622   R28_H, R28,
 623 /*R29_H, R29,*/
 624   R30_H, R30,
 625   R31_H, R31
 626 );
 627 
 628 // 64 bit registers that can only be read i.e. these registers can
 629 // only be src of all instructions.
 630 reg_class bits64_reg_ro(
 631 /*R0_H,  R0*/     // R0
 632   R1_H,  R1,
 633   R2_H,  R2,       // TOC
 634   R3_H,  R3,
 635   R4_H,  R4,
 636   R5_H,  R5,
 637   R6_H,  R6,
 638   R7_H,  R7,
 639   R8_H,  R8,
 640   R9_H,  R9,
 641   R10_H, R10,
 642   R11_H, R11,
 643   R12_H, R12,
 644 /*R13_H, R13*/   // system thread id
 645   R14_H, R14,
 646   R15_H, R15,
 647   R16_H, R16,    // R16_thread
 648   R17_H, R17,
 649   R18_H, R18,
 650   R19_H, R19,
 651   R20_H, R20,
 652   R21_H, R21,
 653   R22_H, R22,
 654   R23_H, R23,
 655   R24_H, R24,
 656   R25_H, R25,
 657   R26_H, R26,
 658   R27_H, R27,
 659   R28_H, R28,
 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
 661   R30_H, R30,
 662   R31_H, R31
 663 );
 664 
 665 
 666 // ----------------------------
 667 // Special Class for Condition Code Flags Register
 668 
 669 reg_class int_flags(
 670 /*CCR0*/             // scratch
 671 /*CCR1*/             // scratch
 672 /*CCR2*/             // nv!
 673 /*CCR3*/             // nv!
 674 /*CCR4*/             // nv!
 675   CCR5,
 676   CCR6,
 677   CCR7
 678 );
 679 
 680 reg_class int_flags_ro(
 681   CCR0,
 682   CCR1,
 683   CCR2,
 684   CCR3,
 685   CCR4,
 686   CCR5,
 687   CCR6,
 688   CCR7
 689 );
 690 
 691 reg_class int_flags_CR0(CCR0);
 692 reg_class int_flags_CR1(CCR1);
 693 reg_class int_flags_CR6(CCR6);
 694 reg_class ctr_reg(SR_CTR);
 695 
 696 // ----------------------------
 697 // Float Register Classes
 698 // ----------------------------
 699 
 700 reg_class flt_reg(
 701   F0,
 702   F1,
 703   F2,
 704   F3,
 705   F4,
 706   F5,
 707   F6,
 708   F7,
 709   F8,
 710   F9,
 711   F10,
 712   F11,
 713   F12,
 714   F13,
 715   F14,              // nv!
 716   F15,              // nv!
 717   F16,              // nv!
 718   F17,              // nv!
 719   F18,              // nv!
 720   F19,              // nv!
 721   F20,              // nv!
 722   F21,              // nv!
 723   F22,              // nv!
 724   F23,              // nv!
 725   F24,              // nv!
 726   F25,              // nv!
 727   F26,              // nv!
 728   F27,              // nv!
 729   F28,              // nv!
 730   F29,              // nv!
 731   F30,              // nv!
 732   F31               // nv!
 733 );
 734 
 735 // Double precision float registers have virtual `high halves' that
 736 // are needed by the allocator.
 737 reg_class dbl_reg(
 738   F0,  F0_H,
 739   F1,  F1_H,
 740   F2,  F2_H,
 741   F3,  F3_H,
 742   F4,  F4_H,
 743   F5,  F5_H,
 744   F6,  F6_H,
 745   F7,  F7_H,
 746   F8,  F8_H,
 747   F9,  F9_H,
 748   F10, F10_H,
 749   F11, F11_H,
 750   F12, F12_H,
 751   F13, F13_H,
 752   F14, F14_H,    // nv!
 753   F15, F15_H,    // nv!
 754   F16, F16_H,    // nv!
 755   F17, F17_H,    // nv!
 756   F18, F18_H,    // nv!
 757   F19, F19_H,    // nv!
 758   F20, F20_H,    // nv!
 759   F21, F21_H,    // nv!
 760   F22, F22_H,    // nv!
 761   F23, F23_H,    // nv!
 762   F24, F24_H,    // nv!
 763   F25, F25_H,    // nv!
 764   F26, F26_H,    // nv!
 765   F27, F27_H,    // nv!
 766   F28, F28_H,    // nv!
 767   F29, F29_H,    // nv!
 768   F30, F30_H,    // nv!
 769   F31, F31_H     // nv!
 770 );
 771 
 772  %}
 773 
 774 //----------DEFINITION BLOCK---------------------------------------------------
 775 // Define name --> value mappings to inform the ADLC of an integer valued name
 776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 777 // Format:
 778 //        int_def  <name>         ( <int_value>, <expression>);
 779 // Generated Code in ad_<arch>.hpp
 780 //        #define  <name>   (<expression>)
 781 //        // value == <int_value>
 782 // Generated code in ad_<arch>.cpp adlc_verification()
 783 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 784 //
 785 definitions %{
 786   // The default cost (of an ALU instruction).
 787   int_def DEFAULT_COST_LOW        (     30,      30);
 788   int_def DEFAULT_COST            (    100,     100);
 789   int_def HUGE_COST               (1000000, 1000000);
 790 
 791   // Memory refs
 792   int_def MEMORY_REF_COST_LOW     (    200, DEFAULT_COST * 2);
 793   int_def MEMORY_REF_COST         (    300, DEFAULT_COST * 3);
 794 
 795   // Branches are even more expensive.
 796   int_def BRANCH_COST             (    900, DEFAULT_COST * 9);
 797   int_def CALL_COST               (   1300, DEFAULT_COST * 13);
 798 %}
 799 
 800 
 801 //----------SOURCE BLOCK-------------------------------------------------------
 802 // This is a block of C++ code which provides values, functions, and
 803 // definitions necessary in the rest of the architecture description.
 804 source_hpp %{
 805   // Header information of the source block.
 806   // Method declarations/definitions which are used outside
 807   // the ad-scope can conveniently be defined here.
 808   //
 809   // To keep related declarations/definitions/uses close together,
 810   // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 811 
 812   // Returns true if Node n is followed by a MemBar node that
 813   // will do an acquire. If so, this node must not do the acquire
 814   // operation.
 815   bool followed_by_acquire(const Node *n);
 816 %}
 817 
 818 source %{
 819 
 820 // Optimize load-acquire.
 821 //
 822 // Check if acquire is unnecessary due to following operation that does
 823 // acquire anyways.
 824 // Walk the pattern:
 825 //
 826 //      n: Load.acq
 827 //           |
 828 //      MemBarAcquire
 829 //       |         |
 830 //  Proj(ctrl)  Proj(mem)
 831 //       |         |
 832 //   MemBarRelease/Volatile
 833 //
 834 bool followed_by_acquire(const Node *load) {
 835   assert(load->is_Load(), "So far implemented only for loads.");
 836 
 837   // Find MemBarAcquire.
 838   const Node *mba = NULL;
 839   for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
 840     const Node *out = load->fast_out(i);
 841     if (out->Opcode() == Op_MemBarAcquire) {
 842       if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
 843       mba = out;
 844       break;
 845     }
 846   }
 847   if (!mba) return false;
 848 
 849   // Find following MemBar node.
 850   //
 851   // The following node must be reachable by control AND memory
 852   // edge to assure no other operations are in between the two nodes.
 853   //
 854   // So first get the Proj node, mem_proj, to use it to iterate forward.
 855   Node *mem_proj = NULL;
 856   for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
 857     mem_proj = mba->fast_out(i);      // Throw out-of-bounds if proj not found
 858     assert(mem_proj->is_Proj(), "only projections here");
 859     ProjNode *proj = mem_proj->as_Proj();
 860     if (proj->_con == TypeFunc::Memory &&
 861         !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
 862       break;
 863   }
 864   assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
 865 
 866   // Search MemBar behind Proj. If there are other memory operations
 867   // behind the Proj we lost.
 868   for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
 869     Node *x = mem_proj->fast_out(j);
 870     // Proj might have an edge to a store or load node which precedes the membar.
 871     if (x->is_Mem()) return false;
 872 
 873     // On PPC64 release and volatile are implemented by an instruction
 874     // that also has acquire semantics. I.e. there is no need for an
 875     // acquire before these.
 876     int xop = x->Opcode();
 877     if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
 878       // Make sure we're not missing Call/Phi/MergeMem by checking
 879       // control edges. The control edge must directly lead back
 880       // to the MemBarAcquire
 881       Node *ctrl_proj = x->in(0);
 882       if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
 883         return true;
 884       }
 885     }
 886   }
 887 
 888   return false;
 889 }
 890 
 891 #define __ _masm.
 892 
 893 // Tertiary op of a LoadP or StoreP encoding.
 894 #define REGP_OP true
 895 
 896 // ****************************************************************************
 897 
 898 // REQUIRED FUNCTIONALITY
 899 
 900 // !!!!! Special hack to get all type of calls to specify the byte offset
 901 //       from the start of the call to the point where the return address
 902 //       will point.
 903 
 904 // PPC port: Removed use of lazy constant construct.
 905 
 906 int MachCallStaticJavaNode::ret_addr_offset() {
 907   // It's only a single branch-and-link instruction.
 908   return 4;
 909 }
 910 
 911 int MachCallDynamicJavaNode::ret_addr_offset() {
 912   // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
 913   // postalloc expanded calls if we use inline caches and do not update method data.
 914   if (UseInlineCaches)
 915     return 4;
 916 
 917   int vtable_index = this->_vtable_index;
 918   if (vtable_index < 0) {
 919     // Must be invalid_vtable_index, not nonvirtual_vtable_index.
 920     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 921     return 12;
 922   } else {
 923     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 924     return 24;
 925   }
 926 }
 927 
 928 int MachCallRuntimeNode::ret_addr_offset() {
 929 #if defined(ABI_ELFv2)
 930   return 28;
 931 #else
 932   return 40;
 933 #endif
 934 }
 935 
 936 //=============================================================================
 937 
 938 // condition code conversions
 939 
 940 static int cc_to_boint(int cc) {
 941   return Assembler::bcondCRbiIs0 | (cc & 8);
 942 }
 943 
 944 static int cc_to_inverse_boint(int cc) {
 945   return Assembler::bcondCRbiIs0 | (8-(cc & 8));
 946 }
 947 
 948 static int cc_to_biint(int cc, int flags_reg) {
 949   return (flags_reg << 2) | (cc & 3);
 950 }
 951 
 952 //=============================================================================
 953 
 954 // Compute padding required for nodes which need alignment. The padding
 955 // is the number of bytes (not instructions) which will be inserted before
 956 // the instruction. The padding must match the size of a NOP instruction.
 957 
 958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const {
 959   return (3*4-current_offset)&31;  // see MacroAssembler::string_indexof_1
 960 }
 961 
 962 int string_indexOf_imm1Node::compute_padding(int current_offset) const {
 963   return (3*4-current_offset)&31;  // see MacroAssembler::string_indexof_1
 964 }
 965 
 966 int string_indexOfCharNode::compute_padding(int current_offset) const {
 967   return (3*4-current_offset)&31;  // see MacroAssembler::string_indexof_1
 968 }
 969 
 970 int string_indexOf_immNode::compute_padding(int current_offset) const {
 971   return (3*4-current_offset)&31;  // see MacroAssembler::string_indexof(constant needlecount)
 972 }
 973 
 974 int string_indexOfNode::compute_padding(int current_offset) const {
 975   return (1*4-current_offset)&31;  // see MacroAssembler::string_indexof(variable needlecount)
 976 }
 977 
 978 int string_compareNode::compute_padding(int current_offset) const {
 979   return (2*4-current_offset)&31;  // see MacroAssembler::string_compare
 980 }
 981 
 982 int string_equals_immNode::compute_padding(int current_offset) const {
 983   if (opnd_array(3)->constant() < 16) return 0; // For strlen < 16 no nops because loop completely unrolled
 984   return (2*4-current_offset)&31;               // Genral case - see MacroAssembler::char_arrays_equalsImm
 985 }
 986 
 987 int string_equalsNode::compute_padding(int current_offset) const {
 988   return (7*4-current_offset)&31;  // see MacroAssembler::char_arrays_equals
 989 }
 990 
 991 int inlineCallClearArrayNode::compute_padding(int current_offset) const {
 992   return (2*4-current_offset)&31;  // see MacroAssembler::clear_memory_doubleword
 993 }
 994 
 995 //=============================================================================
 996 
 997 // Indicate if the safepoint node needs the polling page as an input.
 998 bool SafePointNode::needs_polling_address_input() {
 999   // The address is loaded from thread by a seperate node.
1000   return true;
1001 }
1002 
1003 //=============================================================================
1004 
1005 // Emit an interrupt that is caught by the debugger (for debugging compiler).
1006 void emit_break(CodeBuffer &cbuf) {
1007   MacroAssembler _masm(&cbuf);
1008   __ illtrap();
1009 }
1010 
1011 #ifndef PRODUCT
1012 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1013   st->print("BREAKPOINT");
1014 }
1015 #endif
1016 
1017 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1018   emit_break(cbuf);
1019 }
1020 
1021 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
1022   return MachNode::size(ra_);
1023 }
1024 
1025 //=============================================================================
1026 
1027 void emit_nop(CodeBuffer &cbuf) {
1028   MacroAssembler _masm(&cbuf);
1029   __ nop();
1030 }
1031 
1032 static inline void emit_long(CodeBuffer &cbuf, int value) {
1033   *((int*)(cbuf.insts_end())) = value;
1034   cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1035 }
1036 
1037 //=============================================================================
1038 
1039 %} // interrupt source
1040 
1041 source_hpp %{ // Header information of the source block.
1042 
1043 //--------------------------------------------------------------
1044 //---<  Used for optimization in Compile::Shorten_branches  >---
1045 //--------------------------------------------------------------
1046 
1047 class CallStubImpl {
1048 
1049  public:
1050 
1051   // Emit call stub, compiled java to interpreter.
1052   static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1053 
1054   // Size of call trampoline stub.
1055   // This doesn't need to be accurate to the byte, but it
1056   // must be larger than or equal to the real size of the stub.
1057   static uint size_call_trampoline() {
1058     return MacroAssembler::trampoline_stub_size;
1059   }
1060 
1061   // number of relocations needed by a call trampoline stub
1062   static uint reloc_call_trampoline() {
1063     return 5;
1064   }
1065 
1066 };
1067 
1068 %} // end source_hpp
1069 
1070 source %{
1071 
1072 // Emit a trampoline stub for a call to a target which is too far away.
1073 //
1074 // code sequences:
1075 //
1076 // call-site:
1077 //   branch-and-link to <destination> or <trampoline stub>
1078 //
1079 // Related trampoline stub for this call-site in the stub section:
1080 //   load the call target from the constant pool
1081 //   branch via CTR (LR/link still points to the call-site above)
1082 
1083 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1084   address stub = __ emit_trampoline_stub(destination_toc_offset, insts_call_instruction_offset);
1085   if (stub == NULL) {
1086     ciEnv::current()->record_out_of_memory_failure();
1087   }
1088 }
1089 
1090 //=============================================================================
1091 
1092 // Emit an inline branch-and-link call and a related trampoline stub.
1093 //
1094 // code sequences:
1095 //
1096 // call-site:
1097 //   branch-and-link to <destination> or <trampoline stub>
1098 //
1099 // Related trampoline stub for this call-site in the stub section:
1100 //   load the call target from the constant pool
1101 //   branch via CTR (LR/link still points to the call-site above)
1102 //
1103 
1104 typedef struct {
1105   int insts_call_instruction_offset;
1106   int ret_addr_offset;
1107 } EmitCallOffsets;
1108 
1109 // Emit a branch-and-link instruction that branches to a trampoline.
1110 // - Remember the offset of the branch-and-link instruction.
1111 // - Add a relocation at the branch-and-link instruction.
1112 // - Emit a branch-and-link.
1113 // - Remember the return pc offset.
1114 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1115   EmitCallOffsets offsets = { -1, -1 };
1116   const int start_offset = __ offset();
1117   offsets.insts_call_instruction_offset = __ offset();
1118 
1119   // No entry point given, use the current pc.
1120   if (entry_point == NULL) entry_point = __ pc();
1121 
1122   if (!Compile::current()->in_scratch_emit_size()) {
1123     // Put the entry point as a constant into the constant pool.
1124     const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
1125     if (entry_point_toc_addr == NULL) {
1126       ciEnv::current()->record_out_of_memory_failure();
1127       return offsets;
1128     }
1129     const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1130 
1131     // Emit the trampoline stub which will be related to the branch-and-link below.
1132     CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1133     if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1134     __ relocate(rtype);
1135   }
1136 
1137   // Note: At this point we do not have the address of the trampoline
1138   // stub, and the entry point might be too far away for bl, so __ pc()
1139   // serves as dummy and the bl will be patched later.
1140   __ bl((address) __ pc());
1141 
1142   offsets.ret_addr_offset = __ offset() - start_offset;
1143 
1144   return offsets;
1145 }
1146 
1147 //=============================================================================
1148 
1149 // Factory for creating loadConL* nodes for large/small constant pool.
1150 
1151 static inline jlong replicate_immF(float con) {
1152   // Replicate float con 2 times and pack into vector.
1153   int val = *((int*)&con);
1154   jlong lval = val;
1155   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1156   return lval;
1157 }
1158 
1159 //=============================================================================
1160 
1161 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1162 int Compile::ConstantTable::calculate_table_base_offset() const {
1163   return 0;  // absolute addressing, no offset
1164 }
1165 
1166 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1167 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1168   iRegPdstOper *op_dst = new iRegPdstOper();
1169   MachNode *m1 = new loadToc_hiNode();
1170   MachNode *m2 = new loadToc_loNode();
1171 
1172   m1->add_req(NULL);
1173   m2->add_req(NULL, m1);
1174   m1->_opnds[0] = op_dst;
1175   m2->_opnds[0] = op_dst;
1176   m2->_opnds[1] = op_dst;
1177   ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1178   ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1179   nodes->push(m1);
1180   nodes->push(m2);
1181 }
1182 
1183 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1184   // Is postalloc expanded.
1185   ShouldNotReachHere();
1186 }
1187 
1188 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1189   return 0;
1190 }
1191 
1192 #ifndef PRODUCT
1193 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1194   st->print("-- \t// MachConstantBaseNode (empty encoding)");
1195 }
1196 #endif
1197 
1198 //=============================================================================
1199 
1200 #ifndef PRODUCT
1201 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1202   Compile* C = ra_->C;
1203   const long framesize = C->frame_slots() << LogBytesPerInt;
1204 
1205   st->print("PROLOG\n\t");
1206   if (C->need_stack_bang(framesize)) {
1207     st->print("stack_overflow_check\n\t");
1208   }
1209 
1210   if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1211     st->print("save return pc\n\t");
1212     st->print("push frame %ld\n\t", -framesize);
1213   }
1214 }
1215 #endif
1216 
1217 // Macro used instead of the common __ to emulate the pipes of PPC.
1218 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1219 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1220 // still no scheduling of this code is possible, the micro scheduler is aware of the
1221 // code and can update its internal data. The following mechanism is used to achieve this:
1222 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1223 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1224 #if 0 // TODO: PPC port
1225 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1226                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1227                 _masm.
1228 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1229                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1230 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling())                 \
1231                   C->hb_scheduling()->_pdScheduling->advance_offset
1232 #else
1233 #define ___(op) if (UsePower6SchedulerPPC64)                                          \
1234                   Unimplemented();                                                    \
1235                 _masm.
1236 #define ___stop if (UsePower6SchedulerPPC64)                                          \
1237                   Unimplemented()
1238 #define ___advance if (UsePower6SchedulerPPC64)                                       \
1239                   Unimplemented()
1240 #endif
1241 
1242 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1243   Compile* C = ra_->C;
1244   MacroAssembler _masm(&cbuf);
1245 
1246   const long framesize = C->frame_size_in_bytes();
1247   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1248 
1249   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1250 
1251   const Register return_pc            = R20; // Must match return_addr() in frame section.
1252   const Register callers_sp           = R21;
1253   const Register push_frame_temp      = R22;
1254   const Register toc_temp             = R23;
1255   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1256 
1257   if (method_is_frameless) {
1258     // Add nop at beginning of all frameless methods to prevent any
1259     // oop instructions from getting overwritten by make_not_entrant
1260     // (patching attempt would fail).
1261     ___(nop) nop();
1262   } else {
1263     // Get return pc.
1264     ___(mflr) mflr(return_pc);
1265   }
1266 
1267   // Calls to C2R adapters often do not accept exceptional returns.
1268   // We require that their callers must bang for them. But be
1269   // careful, because some VM calls (such as call site linkage) can
1270   // use several kilobytes of stack. But the stack safety zone should
1271   // account for that. See bugs 4446381, 4468289, 4497237.
1272 
1273   int bangsize = C->bang_size_in_bytes();
1274   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1275   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1276     // Unfortunately we cannot use the function provided in
1277     // assembler.cpp as we have to emulate the pipes. So I had to
1278     // insert the code of generate_stack_overflow_check(), see
1279     // assembler.cpp for some illuminative comments.
1280     const int page_size = os::vm_page_size();
1281     int bang_end = JavaThread::stack_shadow_zone_size();
1282 
1283     // This is how far the previous frame's stack banging extended.
1284     const int bang_end_safe = bang_end;
1285 
1286     if (bangsize > page_size) {
1287       bang_end += bangsize;
1288     }
1289 
1290     int bang_offset = bang_end_safe;
1291 
1292     while (bang_offset <= bang_end) {
1293       // Need at least one stack bang at end of shadow zone.
1294 
1295       // Again I had to copy code, this time from assembler_ppc.cpp,
1296       // bang_stack_with_offset - see there for comments.
1297 
1298       // Stack grows down, caller passes positive offset.
1299       assert(bang_offset > 0, "must bang with positive offset");
1300 
1301       long stdoffset = -bang_offset;
1302 
1303       if (Assembler::is_simm(stdoffset, 16)) {
1304         // Signed 16 bit offset, a simple std is ok.
1305         if (UseLoadInstructionsForStackBangingPPC64) {
1306           ___(ld) ld(R0,  (int)(signed short)stdoffset, R1_SP);
1307         } else {
1308           ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1309         }
1310       } else if (Assembler::is_simm(stdoffset, 31)) {
1311         // Use largeoffset calculations for addis & ld/std.
1312         const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1313         const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1314 
1315         Register tmp = R11;
1316         ___(addis) addis(tmp, R1_SP, hi);
1317         if (UseLoadInstructionsForStackBangingPPC64) {
1318           ___(ld) ld(R0, lo, tmp);
1319         } else {
1320           ___(std) std(R0, lo, tmp);
1321         }
1322       } else {
1323         ShouldNotReachHere();
1324       }
1325 
1326       bang_offset += page_size;
1327     }
1328     // R11 trashed
1329   } // C->need_stack_bang(framesize) && UseStackBanging
1330 
1331   unsigned int bytes = (unsigned int)framesize;
1332   long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1333   ciMethod *currMethod = C->method();
1334 
1335   // Optimized version for most common case.
1336   if (UsePower6SchedulerPPC64 &&
1337       !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1338       !(false /* ConstantsALot TODO: PPC port*/)) {
1339     ___(or) mr(callers_sp, R1_SP);
1340     ___(std) std(return_pc, _abi(lr), R1_SP);
1341     ___(stdu) stdu(R1_SP, -offset, R1_SP);
1342     return;
1343   }
1344 
1345   if (!method_is_frameless) {
1346     // Get callers sp.
1347     ___(or) mr(callers_sp, R1_SP);
1348 
1349     // Push method's frame, modifies SP.
1350     assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1351     // The ABI is already accounted for in 'framesize' via the
1352     // 'out_preserve' area.
1353     Register tmp = push_frame_temp;
1354     // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1355     if (Assembler::is_simm(-offset, 16)) {
1356       ___(stdu) stdu(R1_SP, -offset, R1_SP);
1357     } else {
1358       long x = -offset;
1359       // Had to insert load_const(tmp, -offset).
1360       ___(addis)  lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1361       ___(ori)    ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1362       ___(rldicr) sldi(tmp, tmp, 32);
1363       ___(oris)   oris(tmp, tmp, (x & 0xffff0000) >> 16);
1364       ___(ori)    ori( tmp, tmp, (x & 0x0000ffff));
1365 
1366       ___(stdux) stdux(R1_SP, R1_SP, tmp);
1367     }
1368   }
1369 #if 0 // TODO: PPC port
1370   // For testing large constant pools, emit a lot of constants to constant pool.
1371   // "Randomize" const_size.
1372   if (ConstantsALot) {
1373     const int num_consts = const_size();
1374     for (int i = 0; i < num_consts; i++) {
1375       __ long_constant(0xB0B5B00BBABE);
1376     }
1377   }
1378 #endif
1379   if (!method_is_frameless) {
1380     // Save return pc.
1381     ___(std) std(return_pc, _abi(lr), callers_sp);
1382   }
1383 }
1384 #undef ___
1385 #undef ___stop
1386 #undef ___advance
1387 
1388 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1389   // Variable size. determine dynamically.
1390   return MachNode::size(ra_);
1391 }
1392 
1393 int MachPrologNode::reloc() const {
1394   // Return number of relocatable values contained in this instruction.
1395   return 1; // 1 reloc entry for load_const(toc).
1396 }
1397 
1398 //=============================================================================
1399 
1400 #ifndef PRODUCT
1401 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1402   Compile* C = ra_->C;
1403 
1404   st->print("EPILOG\n\t");
1405   st->print("restore return pc\n\t");
1406   st->print("pop frame\n\t");
1407 
1408   if (do_polling() && C->is_method_compilation()) {
1409     st->print("touch polling page\n\t");
1410   }
1411 }
1412 #endif
1413 
1414 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1415   Compile* C = ra_->C;
1416   MacroAssembler _masm(&cbuf);
1417 
1418   const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1419   assert(framesize >= 0, "negative frame-size?");
1420 
1421   const bool method_needs_polling = do_polling() && C->is_method_compilation();
1422   const bool method_is_frameless  = false /* TODO: PPC port C->is_frameless_method()*/;
1423   const Register return_pc        = R11;
1424   const Register polling_page     = R12;
1425 
1426   if (!method_is_frameless) {
1427     // Restore return pc relative to callers' sp.
1428     __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1429   }
1430 
1431   if (method_needs_polling) {
1432     if (LoadPollAddressFromThread) {
1433       // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1434       Unimplemented();
1435     } else {
1436       __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1437     }
1438   }
1439 
1440   if (!method_is_frameless) {
1441     // Move return pc to LR.
1442     __ mtlr(return_pc);
1443     // Pop frame (fixed frame-size).
1444     __ addi(R1_SP, R1_SP, (int)framesize);
1445   }
1446 
1447   if (method_needs_polling) {
1448     // We need to mark the code position where the load from the safepoint
1449     // polling page was emitted as relocInfo::poll_return_type here.
1450     __ relocate(relocInfo::poll_return_type);
1451     __ load_from_polling_page(polling_page);
1452   }
1453 }
1454 
1455 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1456   // Variable size. Determine dynamically.
1457   return MachNode::size(ra_);
1458 }
1459 
1460 int MachEpilogNode::reloc() const {
1461   // Return number of relocatable values contained in this instruction.
1462   return 1; // 1 for load_from_polling_page.
1463 }
1464 
1465 const Pipeline * MachEpilogNode::pipeline() const {
1466   return MachNode::pipeline_class();
1467 }
1468 
1469 // This method seems to be obsolete. It is declared in machnode.hpp
1470 // and defined in all *.ad files, but it is never called. Should we
1471 // get rid of it?
1472 int MachEpilogNode::safepoint_offset() const {
1473   assert(do_polling(), "no return for this epilog node");
1474   return 0;
1475 }
1476 
1477 #if 0 // TODO: PPC port
1478 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1479   MacroAssembler _masm(&cbuf);
1480   if (LoadPollAddressFromThread) {
1481     _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1482   } else {
1483     _masm.nop();
1484   }
1485 }
1486 
1487 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1488   if (LoadPollAddressFromThread) {
1489     return 4;
1490   } else {
1491     return 4;
1492   }
1493 }
1494 
1495 #ifndef PRODUCT
1496 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1497   st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1498 }
1499 #endif
1500 
1501 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1502   return RSCRATCH1_BITS64_REG_mask();
1503 }
1504 #endif // PPC port
1505 
1506 // =============================================================================
1507 
1508 // Figure out which register class each belongs in: rc_int, rc_float or
1509 // rc_stack.
1510 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1511 
1512 static enum RC rc_class(OptoReg::Name reg) {
1513   // Return the register class for the given register. The given register
1514   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1515   // enumeration in adGlobals_ppc.hpp.
1516 
1517   if (reg == OptoReg::Bad) return rc_bad;
1518 
1519   // We have 64 integer register halves, starting at index 0.
1520   if (reg < 64) return rc_int;
1521 
1522   // We have 64 floating-point register halves, starting at index 64.
1523   if (reg < 64+64) return rc_float;
1524 
1525   // Between float regs & stack are the flags regs.
1526   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1527 
1528   return rc_stack;
1529 }
1530 
1531 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1532                         bool do_print, Compile* C, outputStream *st) {
1533 
1534   assert(opcode == Assembler::LD_OPCODE   ||
1535          opcode == Assembler::STD_OPCODE  ||
1536          opcode == Assembler::LWZ_OPCODE  ||
1537          opcode == Assembler::STW_OPCODE  ||
1538          opcode == Assembler::LFD_OPCODE  ||
1539          opcode == Assembler::STFD_OPCODE ||
1540          opcode == Assembler::LFS_OPCODE  ||
1541          opcode == Assembler::STFS_OPCODE,
1542          "opcode not supported");
1543 
1544   if (cbuf) {
1545     int d =
1546       (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1547         Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1548       : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1549     emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1550   }
1551 #ifndef PRODUCT
1552   else if (do_print) {
1553     st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1554               op_str,
1555               Matcher::regName[reg],
1556               offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1557   }
1558 #endif
1559   return 4; // size
1560 }
1561 
1562 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1563   Compile* C = ra_->C;
1564 
1565   // Get registers to move.
1566   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1567   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1568   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1569   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1570 
1571   enum RC src_hi_rc = rc_class(src_hi);
1572   enum RC src_lo_rc = rc_class(src_lo);
1573   enum RC dst_hi_rc = rc_class(dst_hi);
1574   enum RC dst_lo_rc = rc_class(dst_lo);
1575 
1576   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1577   if (src_hi != OptoReg::Bad)
1578     assert((src_lo&1)==0 && src_lo+1==src_hi &&
1579            (dst_lo&1)==0 && dst_lo+1==dst_hi,
1580            "expected aligned-adjacent pairs");
1581   // Generate spill code!
1582   int size = 0;
1583 
1584   if (src_lo == dst_lo && src_hi == dst_hi)
1585     return size;            // Self copy, no move.
1586 
1587   // --------------------------------------
1588   // Memory->Memory Spill. Use R0 to hold the value.
1589   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1590     int src_offset = ra_->reg2offset(src_lo);
1591     int dst_offset = ra_->reg2offset(dst_lo);
1592     if (src_hi != OptoReg::Bad) {
1593       assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1594              "expected same type of move for high parts");
1595       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE,  R0_num, src_offset, !do_size, C, st);
1596       if (!cbuf && !do_size) st->print("\n\t");
1597       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1598     } else {
1599       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1600       if (!cbuf && !do_size) st->print("\n\t");
1601       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1602     }
1603     return size;
1604   }
1605 
1606   // --------------------------------------
1607   // Check for float->int copy; requires a trip through memory.
1608   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1609     Unimplemented();
1610   }
1611 
1612   // --------------------------------------
1613   // Check for integer reg-reg copy.
1614   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1615       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1616       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1617       size = (Rsrc != Rdst) ? 4 : 0;
1618 
1619       if (cbuf) {
1620         MacroAssembler _masm(cbuf);
1621         if (size) {
1622           __ mr(Rdst, Rsrc);
1623         }
1624       }
1625 #ifndef PRODUCT
1626       else if (!do_size) {
1627         if (size) {
1628           st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1629         } else {
1630           st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1631         }
1632       }
1633 #endif
1634       return size;
1635   }
1636 
1637   // Check for integer store.
1638   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1639     int dst_offset = ra_->reg2offset(dst_lo);
1640     if (src_hi != OptoReg::Bad) {
1641       assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1642              "expected same type of move for high parts");
1643       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1644     } else {
1645       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1646     }
1647     return size;
1648   }
1649 
1650   // Check for integer load.
1651   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1652     int src_offset = ra_->reg2offset(src_lo);
1653     if (src_hi != OptoReg::Bad) {
1654       assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1655              "expected same type of move for high parts");
1656       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1657     } else {
1658       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1659     }
1660     return size;
1661   }
1662 
1663   // Check for float reg-reg copy.
1664   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1665     if (cbuf) {
1666       MacroAssembler _masm(cbuf);
1667       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1668       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1669       __ fmr(Rdst, Rsrc);
1670     }
1671 #ifndef PRODUCT
1672     else if (!do_size) {
1673       st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1674     }
1675 #endif
1676     return 4;
1677   }
1678 
1679   // Check for float store.
1680   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1681     int dst_offset = ra_->reg2offset(dst_lo);
1682     if (src_hi != OptoReg::Bad) {
1683       assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1684              "expected same type of move for high parts");
1685       size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1686     } else {
1687       size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1688     }
1689     return size;
1690   }
1691 
1692   // Check for float load.
1693   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1694     int src_offset = ra_->reg2offset(src_lo);
1695     if (src_hi != OptoReg::Bad) {
1696       assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1697              "expected same type of move for high parts");
1698       size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1699     } else {
1700       size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1701     }
1702     return size;
1703   }
1704 
1705   // --------------------------------------------------------------------
1706   // Check for hi bits still needing moving. Only happens for misaligned
1707   // arguments to native calls.
1708   if (src_hi == dst_hi)
1709     return size;               // Self copy; no move.
1710 
1711   assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1712   ShouldNotReachHere(); // Unimplemented
1713   return 0;
1714 }
1715 
1716 #ifndef PRODUCT
1717 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1718   if (!ra_)
1719     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1720   else
1721     implementation(NULL, ra_, false, st);
1722 }
1723 #endif
1724 
1725 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1726   implementation(&cbuf, ra_, false, NULL);
1727 }
1728 
1729 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1730   return implementation(NULL, ra_, true, NULL);
1731 }
1732 
1733 #if 0 // TODO: PPC port
1734 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1735 #ifndef PRODUCT
1736   if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1737 #endif
1738   assert(ra_->node_regs_max_index() != 0, "");
1739 
1740   // Get registers to move.
1741   OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1742   OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1743   OptoReg::Name dst_hi = ra_->get_reg_second(n);
1744   OptoReg::Name dst_lo = ra_->get_reg_first(n);
1745 
1746   enum RC src_lo_rc = rc_class(src_lo);
1747   enum RC dst_lo_rc = rc_class(dst_lo);
1748 
1749   if (src_lo == dst_lo && src_hi == dst_hi)
1750     return ppc64Opcode_none;            // Self copy, no move.
1751 
1752   // --------------------------------------
1753   // Memory->Memory Spill. Use R0 to hold the value.
1754   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1755     return ppc64Opcode_compound;
1756   }
1757 
1758   // --------------------------------------
1759   // Check for float->int copy; requires a trip through memory.
1760   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1761     Unimplemented();
1762   }
1763 
1764   // --------------------------------------
1765   // Check for integer reg-reg copy.
1766   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1767     Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1768     Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1769     if (Rsrc == Rdst) {
1770       return ppc64Opcode_none;
1771     } else {
1772       return ppc64Opcode_or;
1773     }
1774   }
1775 
1776   // Check for integer store.
1777   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1778     if (src_hi != OptoReg::Bad) {
1779       return ppc64Opcode_std;
1780     } else {
1781       return ppc64Opcode_stw;
1782     }
1783   }
1784 
1785   // Check for integer load.
1786   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1787     if (src_hi != OptoReg::Bad) {
1788       return ppc64Opcode_ld;
1789     } else {
1790       return ppc64Opcode_lwz;
1791     }
1792   }
1793 
1794   // Check for float reg-reg copy.
1795   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1796     return ppc64Opcode_fmr;
1797   }
1798 
1799   // Check for float store.
1800   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1801     if (src_hi != OptoReg::Bad) {
1802       return ppc64Opcode_stfd;
1803     } else {
1804       return ppc64Opcode_stfs;
1805     }
1806   }
1807 
1808   // Check for float load.
1809   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1810     if (src_hi != OptoReg::Bad) {
1811       return ppc64Opcode_lfd;
1812     } else {
1813       return ppc64Opcode_lfs;
1814     }
1815   }
1816 
1817   // --------------------------------------------------------------------
1818   // Check for hi bits still needing moving. Only happens for misaligned
1819   // arguments to native calls.
1820   if (src_hi == dst_hi) {
1821     return ppc64Opcode_none;               // Self copy; no move.
1822   }
1823 
1824   ShouldNotReachHere();
1825   return ppc64Opcode_undefined;
1826 }
1827 #endif // PPC port
1828 
1829 #ifndef PRODUCT
1830 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1831   st->print("NOP \t// %d nops to pad for loops.", _count);
1832 }
1833 #endif
1834 
1835 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1836   MacroAssembler _masm(&cbuf);
1837   // _count contains the number of nops needed for padding.
1838   for (int i = 0; i < _count; i++) {
1839     __ nop();
1840   }
1841 }
1842 
1843 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1844   return _count * 4;
1845 }
1846 
1847 #ifndef PRODUCT
1848 void MachMskNode::format(PhaseRegAlloc*, outputStream* st) const {
1849   // TBD
1850 }
1851 #endif
1852 
1853 void MachMskNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
1854   // TBD
1855 }
1856 
1857 uint MachMskNode::size(PhaseRegAlloc* ra_) const {
1858   return 0; // TBD
1859 }
1860 
1861 #ifndef PRODUCT
1862 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1863   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1864   char reg_str[128];
1865   ra_->dump_register(this, reg_str);
1866   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
1867 }
1868 #endif
1869 
1870 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1871   MacroAssembler _masm(&cbuf);
1872 
1873   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1874   int reg    = ra_->get_encode(this);
1875 
1876   if (Assembler::is_simm(offset, 16)) {
1877     __ addi(as_Register(reg), R1, offset);
1878   } else {
1879     ShouldNotReachHere();
1880   }
1881 }
1882 
1883 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1884   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1885   return 4;
1886 }
1887 
1888 #ifndef PRODUCT
1889 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1890   st->print_cr("---- MachUEPNode ----");
1891   st->print_cr("...");
1892 }
1893 #endif
1894 
1895 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1896   // This is the unverified entry point.
1897   MacroAssembler _masm(&cbuf);
1898 
1899   // Inline_cache contains a klass.
1900   Register ic_klass       = as_Register(Matcher::inline_cache_reg_encode());
1901   Register receiver_klass = R12_scratch2;  // tmp
1902 
1903   assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1904   assert(R11_scratch1 == R11, "need prologue scratch register");
1905 
1906   // Check for NULL argument if we don't have implicit null checks.
1907   if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1908     if (TrapBasedNullChecks) {
1909       __ trap_null_check(R3_ARG1);
1910     } else {
1911       Label valid;
1912       __ cmpdi(CCR0, R3_ARG1, 0);
1913       __ bne_predict_taken(CCR0, valid);
1914       // We have a null argument, branch to ic_miss_stub.
1915       __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1916                            relocInfo::runtime_call_type);
1917       __ bind(valid);
1918     }
1919   }
1920   // Assume argument is not NULL, load klass from receiver.
1921   __ load_klass(receiver_klass, R3_ARG1);
1922 
1923   if (TrapBasedICMissChecks) {
1924     __ trap_ic_miss_check(receiver_klass, ic_klass);
1925   } else {
1926     Label valid;
1927     __ cmpd(CCR0, receiver_klass, ic_klass);
1928     __ beq_predict_taken(CCR0, valid);
1929     // We have an unexpected klass, branch to ic_miss_stub.
1930     __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1931                          relocInfo::runtime_call_type);
1932     __ bind(valid);
1933   }
1934 
1935   // Argument is valid and klass is as expected, continue.
1936 }
1937 
1938 #if 0 // TODO: PPC port
1939 // Optimize UEP code on z (save a load_const() call in main path).
1940 int MachUEPNode::ep_offset() {
1941   return 0;
1942 }
1943 #endif
1944 
1945 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1946   // Variable size. Determine dynamically.
1947   return MachNode::size(ra_);
1948 }
1949 
1950 //=============================================================================
1951 
1952 %} // interrupt source
1953 
1954 source_hpp %{ // Header information of the source block.
1955 
1956 class HandlerImpl {
1957 
1958  public:
1959 
1960   static int emit_exception_handler(CodeBuffer &cbuf);
1961   static int emit_deopt_handler(CodeBuffer& cbuf);
1962 
1963   static uint size_exception_handler() {
1964     // The exception_handler is a b64_patchable.
1965     return MacroAssembler::b64_patchable_size;
1966   }
1967 
1968   static uint size_deopt_handler() {
1969     // The deopt_handler is a bl64_patchable.
1970     return MacroAssembler::bl64_patchable_size;
1971   }
1972 
1973 };
1974 
1975 %} // end source_hpp
1976 
1977 source %{
1978 
1979 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1980   MacroAssembler _masm(&cbuf);
1981 
1982   address base = __ start_a_stub(size_exception_handler());
1983   if (base == NULL) return 0; // CodeBuffer::expand failed
1984 
1985   int offset = __ offset();
1986   __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
1987                        relocInfo::runtime_call_type);
1988   assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
1989   __ end_a_stub();
1990 
1991   return offset;
1992 }
1993 
1994 // The deopt_handler is like the exception handler, but it calls to
1995 // the deoptimization blob instead of jumping to the exception blob.
1996 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1997   MacroAssembler _masm(&cbuf);
1998 
1999   address base = __ start_a_stub(size_deopt_handler());
2000   if (base == NULL) return 0; // CodeBuffer::expand failed
2001 
2002   int offset = __ offset();
2003   __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
2004                         relocInfo::runtime_call_type);
2005   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
2006   __ end_a_stub();
2007 
2008   return offset;
2009 }
2010 
2011 //=============================================================================
2012 
2013 // Use a frame slots bias for frameless methods if accessing the stack.
2014 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
2015   if (as_Register(reg_enc) == R1_SP) {
2016     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
2017   }
2018   return 0;
2019 }
2020 
2021 const bool Matcher::match_rule_supported(int opcode) {
2022   if (!has_match_rule(opcode))
2023     return false;
2024 
2025   switch (opcode) {
2026   case Op_SqrtD:
2027     return VM_Version::has_fsqrt();
2028   case Op_CountLeadingZerosI:
2029   case Op_CountLeadingZerosL:
2030   case Op_CountTrailingZerosI:
2031   case Op_CountTrailingZerosL:
2032     if (!UseCountLeadingZerosInstructionsPPC64)
2033       return false;
2034     break;
2035 
2036   case Op_PopCountI:
2037   case Op_PopCountL:
2038     return (UsePopCountInstruction && VM_Version::has_popcntw());
2039 
2040   case Op_StrComp:
2041     return SpecialStringCompareTo;
2042   case Op_StrEquals:
2043     return SpecialStringEquals;
2044   case Op_StrIndexOf:
2045     return SpecialStringIndexOf;
2046   case Op_StrIndexOfChar:
2047     return SpecialStringIndexOf;
2048   }
2049 
2050   return true;  // Per default match rules are supported.
2051 }
2052 
2053 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2054 
2055   // TODO
2056   // identify extra cases that we might want to provide match rules for
2057   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2058   bool ret_value = match_rule_supported(opcode);
2059   // Add rules here.
2060 
2061   return ret_value;  // Per default match rules are supported.
2062 }
2063 
2064 const bool Matcher::has_predicated_vectors(void) {
2065   return false;
2066 }
2067 
2068 const int Matcher::float_pressure(int default_pressure_threshold) {
2069   return default_pressure_threshold;
2070 }
2071 
2072 int Matcher::regnum_to_fpu_offset(int regnum) {
2073   // No user for this method?
2074   Unimplemented();
2075   return 999;
2076 }
2077 
2078 const bool Matcher::convL2FSupported(void) {
2079   // fcfids can do the conversion (>= Power7).
2080   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2081   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2082 }
2083 
2084 // Vector width in bytes.
2085 const int Matcher::vector_width_in_bytes(BasicType bt) {
2086   assert(MaxVectorSize == 8, "");
2087   return 8;
2088 }
2089 
2090 // Vector ideal reg.
2091 const int Matcher::vector_ideal_reg(int size) {
2092   assert(MaxVectorSize == 8 && size == 8, "");
2093   return Op_RegL;
2094 }
2095 
2096 const int Matcher::vector_shift_count_ideal_reg(int size) {
2097   fatal("vector shift is not supported");
2098   return Node::NotAMachineReg;
2099 }
2100 
2101 // Limits on vector size (number of elements) loaded into vector.
2102 const int Matcher::max_vector_size(const BasicType bt) {
2103   assert(is_java_primitive(bt), "only primitive type vectors");
2104   return vector_width_in_bytes(bt)/type2aelembytes(bt);
2105 }
2106 
2107 const int Matcher::min_vector_size(const BasicType bt) {
2108   return max_vector_size(bt); // Same as max.
2109 }
2110 
2111 // PPC doesn't support misaligned vectors store/load.
2112 const bool Matcher::misaligned_vectors_ok() {
2113   return false;
2114 }
2115 
2116 // PPC AES support not yet implemented
2117 const bool Matcher::pass_original_key_for_aes() {
2118   return false;
2119 }
2120 
2121 // RETURNS: whether this branch offset is short enough that a short
2122 // branch can be used.
2123 //
2124 // If the platform does not provide any short branch variants, then
2125 // this method should return `false' for offset 0.
2126 //
2127 // `Compile::Fill_buffer' will decide on basis of this information
2128 // whether to do the pass `Compile::Shorten_branches' at all.
2129 //
2130 // And `Compile::Shorten_branches' will decide on basis of this
2131 // information whether to replace particular branch sites by short
2132 // ones.
2133 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2134   // Is the offset within the range of a ppc64 pc relative branch?
2135   bool b;
2136 
2137   const int safety_zone = 3 * BytesPerInstWord;
2138   b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2139                          29 - 16 + 1 + 2);
2140   return b;
2141 }
2142 
2143 const bool Matcher::isSimpleConstant64(jlong value) {
2144   // Probably always true, even if a temp register is required.
2145   return true;
2146 }
2147 /* TODO: PPC port
2148 // Make a new machine dependent decode node (with its operands).
2149 MachTypeNode *Matcher::make_decode_node() {
2150   assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2151          "This method is only implemented for unscaled cOops mode so far");
2152   MachTypeNode *decode = new decodeN_unscaledNode();
2153   decode->set_opnd_array(0, new iRegPdstOper());
2154   decode->set_opnd_array(1, new iRegNsrcOper());
2155   return decode;
2156 }
2157 */
2158 
2159 // false => size gets scaled to BytesPerLong, ok.
2160 const bool Matcher::init_array_count_is_in_bytes = false;
2161 
2162 // Use conditional move (CMOVL) on Power7.
2163 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2164 
2165 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2166 // fsel doesn't accept a condition register as input, so this would be slightly different.
2167 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2168 
2169 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2170 const bool Matcher::require_postalloc_expand = true;
2171 
2172 // Should the Matcher clone shifts on addressing modes, expecting them to
2173 // be subsumed into complex addressing expressions or compute them into
2174 // registers? True for Intel but false for most RISCs.
2175 const bool Matcher::clone_shift_expressions = false;
2176 
2177 // Do we need to mask the count passed to shift instructions or does
2178 // the cpu only look at the lower 5/6 bits anyway?
2179 // PowerPC requires masked shift counts.
2180 const bool Matcher::need_masked_shift_count = true;
2181 
2182 // This affects two different things:
2183 //  - how Decode nodes are matched
2184 //  - how ImplicitNullCheck opportunities are recognized
2185 // If true, the matcher will try to remove all Decodes and match them
2186 // (as operands) into nodes. NullChecks are not prepared to deal with
2187 // Decodes by final_graph_reshaping().
2188 // If false, final_graph_reshaping() forces the decode behind the Cmp
2189 // for a NullCheck. The matcher matches the Decode node into a register.
2190 // Implicit_null_check optimization moves the Decode along with the
2191 // memory operation back up before the NullCheck.
2192 bool Matcher::narrow_oop_use_complex_address() {
2193   // TODO: PPC port if (MatchDecodeNodes) return true;
2194   return false;
2195 }
2196 
2197 bool Matcher::narrow_klass_use_complex_address() {
2198   NOT_LP64(ShouldNotCallThis());
2199   assert(UseCompressedClassPointers, "only for compressed klass code");
2200   // TODO: PPC port if (MatchDecodeNodes) return true;
2201   return false;
2202 }
2203 
2204 // Is it better to copy float constants, or load them directly from memory?
2205 // Intel can load a float constant from a direct address, requiring no
2206 // extra registers. Most RISCs will have to materialize an address into a
2207 // register first, so they would do better to copy the constant from stack.
2208 const bool Matcher::rematerialize_float_constants = false;
2209 
2210 // If CPU can load and store mis-aligned doubles directly then no fixup is
2211 // needed. Else we split the double into 2 integer pieces and move it
2212 // piece-by-piece. Only happens when passing doubles into C code as the
2213 // Java calling convention forces doubles to be aligned.
2214 const bool Matcher::misaligned_doubles_ok = true;
2215 
2216 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2217  Unimplemented();
2218 }
2219 
2220 // Advertise here if the CPU requires explicit rounding operations
2221 // to implement the UseStrictFP mode.
2222 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2223 
2224 // Do floats take an entire double register or just half?
2225 //
2226 // A float occupies a ppc64 double register. For the allocator, a
2227 // ppc64 double register appears as a pair of float registers.
2228 bool Matcher::float_in_double() { return true; }
2229 
2230 // Do ints take an entire long register or just half?
2231 // The relevant question is how the int is callee-saved:
2232 // the whole long is written but de-opt'ing will have to extract
2233 // the relevant 32 bits.
2234 const bool Matcher::int_in_long = true;
2235 
2236 // Constants for c2c and c calling conventions.
2237 
2238 const MachRegisterNumbers iarg_reg[8] = {
2239   R3_num, R4_num, R5_num, R6_num,
2240   R7_num, R8_num, R9_num, R10_num
2241 };
2242 
2243 const MachRegisterNumbers farg_reg[13] = {
2244   F1_num, F2_num, F3_num, F4_num,
2245   F5_num, F6_num, F7_num, F8_num,
2246   F9_num, F10_num, F11_num, F12_num,
2247   F13_num
2248 };
2249 
2250 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2251 
2252 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2253 
2254 // Return whether or not this register is ever used as an argument. This
2255 // function is used on startup to build the trampoline stubs in generateOptoStub.
2256 // Registers not mentioned will be killed by the VM call in the trampoline, and
2257 // arguments in those registers not be available to the callee.
2258 bool Matcher::can_be_java_arg(int reg) {
2259   // We return true for all registers contained in iarg_reg[] and
2260   // farg_reg[] and their virtual halves.
2261   // We must include the virtual halves in order to get STDs and LDs
2262   // instead of STWs and LWs in the trampoline stubs.
2263 
2264   if (   reg == R3_num  || reg == R3_H_num
2265       || reg == R4_num  || reg == R4_H_num
2266       || reg == R5_num  || reg == R5_H_num
2267       || reg == R6_num  || reg == R6_H_num
2268       || reg == R7_num  || reg == R7_H_num
2269       || reg == R8_num  || reg == R8_H_num
2270       || reg == R9_num  || reg == R9_H_num
2271       || reg == R10_num || reg == R10_H_num)
2272     return true;
2273 
2274   if (   reg == F1_num  || reg == F1_H_num
2275       || reg == F2_num  || reg == F2_H_num
2276       || reg == F3_num  || reg == F3_H_num
2277       || reg == F4_num  || reg == F4_H_num
2278       || reg == F5_num  || reg == F5_H_num
2279       || reg == F6_num  || reg == F6_H_num
2280       || reg == F7_num  || reg == F7_H_num
2281       || reg == F8_num  || reg == F8_H_num
2282       || reg == F9_num  || reg == F9_H_num
2283       || reg == F10_num || reg == F10_H_num
2284       || reg == F11_num || reg == F11_H_num
2285       || reg == F12_num || reg == F12_H_num
2286       || reg == F13_num || reg == F13_H_num)
2287     return true;
2288 
2289   return false;
2290 }
2291 
2292 bool Matcher::is_spillable_arg(int reg) {
2293   return can_be_java_arg(reg);
2294 }
2295 
2296 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2297   return false;
2298 }
2299 
2300 // Register for DIVI projection of divmodI.
2301 RegMask Matcher::divI_proj_mask() {
2302   ShouldNotReachHere();
2303   return RegMask();
2304 }
2305 
2306 // Register for MODI projection of divmodI.
2307 RegMask Matcher::modI_proj_mask() {
2308   ShouldNotReachHere();
2309   return RegMask();
2310 }
2311 
2312 // Register for DIVL projection of divmodL.
2313 RegMask Matcher::divL_proj_mask() {
2314   ShouldNotReachHere();
2315   return RegMask();
2316 }
2317 
2318 // Register for MODL projection of divmodL.
2319 RegMask Matcher::modL_proj_mask() {
2320   ShouldNotReachHere();
2321   return RegMask();
2322 }
2323 
2324 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2325   return RegMask();
2326 }
2327 
2328 %}
2329 
2330 //----------ENCODING BLOCK-----------------------------------------------------
2331 // This block specifies the encoding classes used by the compiler to output
2332 // byte streams. Encoding classes are parameterized macros used by
2333 // Machine Instruction Nodes in order to generate the bit encoding of the
2334 // instruction. Operands specify their base encoding interface with the
2335 // interface keyword. There are currently supported four interfaces,
2336 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2337 // operand to generate a function which returns its register number when
2338 // queried. CONST_INTER causes an operand to generate a function which
2339 // returns the value of the constant when queried. MEMORY_INTER causes an
2340 // operand to generate four functions which return the Base Register, the
2341 // Index Register, the Scale Value, and the Offset Value of the operand when
2342 // queried. COND_INTER causes an operand to generate six functions which
2343 // return the encoding code (ie - encoding bits for the instruction)
2344 // associated with each basic boolean condition for a conditional instruction.
2345 //
2346 // Instructions specify two basic values for encoding. Again, a function
2347 // is available to check if the constant displacement is an oop. They use the
2348 // ins_encode keyword to specify their encoding classes (which must be
2349 // a sequence of enc_class names, and their parameters, specified in
2350 // the encoding block), and they use the
2351 // opcode keyword to specify, in order, their primary, secondary, and
2352 // tertiary opcode. Only the opcode sections which a particular instruction
2353 // needs for encoding need to be specified.
2354 encode %{
2355   enc_class enc_unimplemented %{
2356     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2357     MacroAssembler _masm(&cbuf);
2358     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2359   %}
2360 
2361   enc_class enc_untested %{
2362 #ifdef ASSERT
2363     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2364     MacroAssembler _masm(&cbuf);
2365     __ untested("Untested mach node encoding in AD file.");
2366 #else
2367     // TODO: PPC port $archOpcode(ppc64Opcode_none);
2368 #endif
2369   %}
2370 
2371   enc_class enc_lbz(iRegIdst dst, memory mem) %{
2372     // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2373     MacroAssembler _masm(&cbuf);
2374     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2375     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2376   %}
2377 
2378   // Load acquire.
2379   enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2380     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2381     MacroAssembler _masm(&cbuf);
2382     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2383     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2384     __ twi_0($dst$$Register);
2385     __ isync();
2386   %}
2387 
2388   enc_class enc_lhz(iRegIdst dst, memory mem) %{
2389     // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2390 
2391     MacroAssembler _masm(&cbuf);
2392     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2393     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2394   %}
2395 
2396   // Load acquire.
2397   enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2398     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2399 
2400     MacroAssembler _masm(&cbuf);
2401     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2402     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2403     __ twi_0($dst$$Register);
2404     __ isync();
2405   %}
2406 
2407   enc_class enc_lwz(iRegIdst dst, memory mem) %{
2408     // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2409 
2410     MacroAssembler _masm(&cbuf);
2411     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2412     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2413   %}
2414 
2415   // Load acquire.
2416   enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2417     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2418 
2419     MacroAssembler _masm(&cbuf);
2420     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2421     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2422     __ twi_0($dst$$Register);
2423     __ isync();
2424   %}
2425 
2426   enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2427     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2428     MacroAssembler _masm(&cbuf);
2429     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2430     // Operand 'ds' requires 4-alignment.
2431     assert((Idisp & 0x3) == 0, "unaligned offset");
2432     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2433   %}
2434 
2435   // Load acquire.
2436   enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2437     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2438     MacroAssembler _masm(&cbuf);
2439     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2440     // Operand 'ds' requires 4-alignment.
2441     assert((Idisp & 0x3) == 0, "unaligned offset");
2442     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2443     __ twi_0($dst$$Register);
2444     __ isync();
2445   %}
2446 
2447   enc_class enc_lfd(RegF dst, memory mem) %{
2448     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2449     MacroAssembler _masm(&cbuf);
2450     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2451     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2452   %}
2453 
2454   enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2455     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2456 
2457     MacroAssembler _masm(&cbuf);
2458     int toc_offset = 0;
2459 
2460     if (!ra_->C->in_scratch_emit_size()) {
2461       address const_toc_addr;
2462       // Create a non-oop constant, no relocation needed.
2463       // If it is an IC, it has a virtual_call_Relocation.
2464       const_toc_addr = __ long_constant((jlong)$src$$constant);
2465       if (const_toc_addr == NULL) {
2466         ciEnv::current()->record_out_of_memory_failure();
2467         return;
2468       }
2469 
2470       // Get the constant's TOC offset.
2471       toc_offset = __ offset_to_method_toc(const_toc_addr);
2472 
2473       // Keep the current instruction offset in mind.
2474       ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2475     }
2476 
2477     __ ld($dst$$Register, toc_offset, $toc$$Register);
2478   %}
2479 
2480   enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2481     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2482 
2483     MacroAssembler _masm(&cbuf);
2484 
2485     if (!ra_->C->in_scratch_emit_size()) {
2486       address const_toc_addr;
2487       // Create a non-oop constant, no relocation needed.
2488       // If it is an IC, it has a virtual_call_Relocation.
2489       const_toc_addr = __ long_constant((jlong)$src$$constant);
2490       if (const_toc_addr == NULL) {
2491         ciEnv::current()->record_out_of_memory_failure();
2492         return;
2493       }
2494 
2495       // Get the constant's TOC offset.
2496       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2497       // Store the toc offset of the constant.
2498       ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2499 
2500       // Also keep the current instruction offset in mind.
2501       ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2502     }
2503 
2504     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2505   %}
2506 
2507 %} // encode
2508 
2509 source %{
2510 
2511 typedef struct {
2512   loadConL_hiNode *_large_hi;
2513   loadConL_loNode *_large_lo;
2514   loadConLNode    *_small;
2515   MachNode        *_last;
2516 } loadConLNodesTuple;
2517 
2518 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2519                                              OptoReg::Name reg_second, OptoReg::Name reg_first) {
2520   loadConLNodesTuple nodes;
2521 
2522   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2523   if (large_constant_pool) {
2524     // Create new nodes.
2525     loadConL_hiNode *m1 = new loadConL_hiNode();
2526     loadConL_loNode *m2 = new loadConL_loNode();
2527 
2528     // inputs for new nodes
2529     m1->add_req(NULL, toc);
2530     m2->add_req(NULL, m1);
2531 
2532     // operands for new nodes
2533     m1->_opnds[0] = new iRegLdstOper(); // dst
2534     m1->_opnds[1] = immSrc;             // src
2535     m1->_opnds[2] = new iRegPdstOper(); // toc
2536     m2->_opnds[0] = new iRegLdstOper(); // dst
2537     m2->_opnds[1] = immSrc;             // src
2538     m2->_opnds[2] = new iRegLdstOper(); // base
2539 
2540     // Initialize ins_attrib TOC fields.
2541     m1->_const_toc_offset = -1;
2542     m2->_const_toc_offset_hi_node = m1;
2543 
2544     // Initialize ins_attrib instruction offset.
2545     m1->_cbuf_insts_offset = -1;
2546 
2547     // register allocation for new nodes
2548     ra_->set_pair(m1->_idx, reg_second, reg_first);
2549     ra_->set_pair(m2->_idx, reg_second, reg_first);
2550 
2551     // Create result.
2552     nodes._large_hi = m1;
2553     nodes._large_lo = m2;
2554     nodes._small = NULL;
2555     nodes._last = nodes._large_lo;
2556     assert(m2->bottom_type()->isa_long(), "must be long");
2557   } else {
2558     loadConLNode *m2 = new loadConLNode();
2559 
2560     // inputs for new nodes
2561     m2->add_req(NULL, toc);
2562 
2563     // operands for new nodes
2564     m2->_opnds[0] = new iRegLdstOper(); // dst
2565     m2->_opnds[1] = immSrc;             // src
2566     m2->_opnds[2] = new iRegPdstOper(); // toc
2567 
2568     // Initialize ins_attrib instruction offset.
2569     m2->_cbuf_insts_offset = -1;
2570 
2571     // register allocation for new nodes
2572     ra_->set_pair(m2->_idx, reg_second, reg_first);
2573 
2574     // Create result.
2575     nodes._large_hi = NULL;
2576     nodes._large_lo = NULL;
2577     nodes._small = m2;
2578     nodes._last = nodes._small;
2579     assert(m2->bottom_type()->isa_long(), "must be long");
2580   }
2581 
2582   return nodes;
2583 }
2584 
2585 %} // source
2586 
2587 encode %{
2588   // Postalloc expand emitter for loading a long constant from the method's TOC.
2589   // Enc_class needed as consttanttablebase is not supported by postalloc
2590   // expand.
2591   enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2592     // Create new nodes.
2593     loadConLNodesTuple loadConLNodes =
2594       loadConLNodesTuple_create(ra_, n_toc, op_src,
2595                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
2596 
2597     // Push new nodes.
2598     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2599     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
2600 
2601     // some asserts
2602     assert(nodes->length() >= 1, "must have created at least 1 node");
2603     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2604   %}
2605 
2606   enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2607     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2608 
2609     MacroAssembler _masm(&cbuf);
2610     int toc_offset = 0;
2611 
2612     if (!ra_->C->in_scratch_emit_size()) {
2613       intptr_t val = $src$$constant;
2614       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2615       address const_toc_addr;
2616       if (constant_reloc == relocInfo::oop_type) {
2617         // Create an oop constant and a corresponding relocation.
2618         AddressLiteral a = __ allocate_oop_address((jobject)val);
2619         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2620         __ relocate(a.rspec());
2621       } else if (constant_reloc == relocInfo::metadata_type) {
2622         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2623         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2624         __ relocate(a.rspec());
2625       } else {
2626         // Create a non-oop constant, no relocation needed.
2627         const_toc_addr = __ long_constant((jlong)$src$$constant);
2628       }
2629 
2630       if (const_toc_addr == NULL) {
2631         ciEnv::current()->record_out_of_memory_failure();
2632         return;
2633       }
2634       // Get the constant's TOC offset.
2635       toc_offset = __ offset_to_method_toc(const_toc_addr);
2636     }
2637 
2638     __ ld($dst$$Register, toc_offset, $toc$$Register);
2639   %}
2640 
2641   enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2642     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2643 
2644     MacroAssembler _masm(&cbuf);
2645     if (!ra_->C->in_scratch_emit_size()) {
2646       intptr_t val = $src$$constant;
2647       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2648       address const_toc_addr;
2649       if (constant_reloc == relocInfo::oop_type) {
2650         // Create an oop constant and a corresponding relocation.
2651         AddressLiteral a = __ allocate_oop_address((jobject)val);
2652         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2653         __ relocate(a.rspec());
2654       } else if (constant_reloc == relocInfo::metadata_type) {
2655         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2656         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2657         __ relocate(a.rspec());
2658       } else {  // non-oop pointers, e.g. card mark base, heap top
2659         // Create a non-oop constant, no relocation needed.
2660         const_toc_addr = __ long_constant((jlong)$src$$constant);
2661       }
2662 
2663       if (const_toc_addr == NULL) {
2664         ciEnv::current()->record_out_of_memory_failure();
2665         return;
2666       }
2667       // Get the constant's TOC offset.
2668       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2669       // Store the toc offset of the constant.
2670       ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2671     }
2672 
2673     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2674   %}
2675 
2676   // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2677   // Enc_class needed as consttanttablebase is not supported by postalloc
2678   // expand.
2679   enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2680     const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2681     if (large_constant_pool) {
2682       // Create new nodes.
2683       loadConP_hiNode *m1 = new loadConP_hiNode();
2684       loadConP_loNode *m2 = new loadConP_loNode();
2685 
2686       // inputs for new nodes
2687       m1->add_req(NULL, n_toc);
2688       m2->add_req(NULL, m1);
2689 
2690       // operands for new nodes
2691       m1->_opnds[0] = new iRegPdstOper(); // dst
2692       m1->_opnds[1] = op_src;             // src
2693       m1->_opnds[2] = new iRegPdstOper(); // toc
2694       m2->_opnds[0] = new iRegPdstOper(); // dst
2695       m2->_opnds[1] = op_src;             // src
2696       m2->_opnds[2] = new iRegLdstOper(); // base
2697 
2698       // Initialize ins_attrib TOC fields.
2699       m1->_const_toc_offset = -1;
2700       m2->_const_toc_offset_hi_node = m1;
2701 
2702       // Register allocation for new nodes.
2703       ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2704       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2705 
2706       nodes->push(m1);
2707       nodes->push(m2);
2708       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2709     } else {
2710       loadConPNode *m2 = new loadConPNode();
2711 
2712       // inputs for new nodes
2713       m2->add_req(NULL, n_toc);
2714 
2715       // operands for new nodes
2716       m2->_opnds[0] = new iRegPdstOper(); // dst
2717       m2->_opnds[1] = op_src;             // src
2718       m2->_opnds[2] = new iRegPdstOper(); // toc
2719 
2720       // Register allocation for new nodes.
2721       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2722 
2723       nodes->push(m2);
2724       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2725     }
2726   %}
2727 
2728   // Enc_class needed as consttanttablebase is not supported by postalloc
2729   // expand.
2730   enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2731     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2732 
2733     MachNode *m2;
2734     if (large_constant_pool) {
2735       m2 = new loadConFCompNode();
2736     } else {
2737       m2 = new loadConFNode();
2738     }
2739     // inputs for new nodes
2740     m2->add_req(NULL, n_toc);
2741 
2742     // operands for new nodes
2743     m2->_opnds[0] = op_dst;
2744     m2->_opnds[1] = op_src;
2745     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2746 
2747     // register allocation for new nodes
2748     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2749     nodes->push(m2);
2750   %}
2751 
2752   // Enc_class needed as consttanttablebase is not supported by postalloc
2753   // expand.
2754   enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2755     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2756 
2757     MachNode *m2;
2758     if (large_constant_pool) {
2759       m2 = new loadConDCompNode();
2760     } else {
2761       m2 = new loadConDNode();
2762     }
2763     // inputs for new nodes
2764     m2->add_req(NULL, n_toc);
2765 
2766     // operands for new nodes
2767     m2->_opnds[0] = op_dst;
2768     m2->_opnds[1] = op_src;
2769     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2770 
2771     // register allocation for new nodes
2772     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2773     nodes->push(m2);
2774   %}
2775 
2776   enc_class enc_stw(iRegIsrc src, memory mem) %{
2777     // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2778     MacroAssembler _masm(&cbuf);
2779     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2780     __ stw($src$$Register, Idisp, $mem$$base$$Register);
2781   %}
2782 
2783   enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2784     // TODO: PPC port $archOpcode(ppc64Opcode_std);
2785     MacroAssembler _masm(&cbuf);
2786     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2787     // Operand 'ds' requires 4-alignment.
2788     assert((Idisp & 0x3) == 0, "unaligned offset");
2789     __ std($src$$Register, Idisp, $mem$$base$$Register);
2790   %}
2791 
2792   enc_class enc_stfs(RegF src, memory mem) %{
2793     // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2794     MacroAssembler _masm(&cbuf);
2795     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2796     __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2797   %}
2798 
2799   enc_class enc_stfd(RegF src, memory mem) %{
2800     // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2801     MacroAssembler _masm(&cbuf);
2802     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2803     __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2804   %}
2805 
2806   // Use release_store for card-marking to ensure that previous
2807   // oop-stores are visible before the card-mark change.
2808   enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2809     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2810     // FIXME: Implement this as a cmove and use a fixed condition code
2811     // register which is written on every transition to compiled code,
2812     // e.g. in call-stub and when returning from runtime stubs.
2813     //
2814     // Proposed code sequence for the cmove implementation:
2815     //
2816     // Label skip_release;
2817     // __ beq(CCRfixed, skip_release);
2818     // __ release();
2819     // __ bind(skip_release);
2820     // __ stb(card mark);
2821 
2822     MacroAssembler _masm(&cbuf);
2823     Label skip_storestore;
2824 
2825 #if 0 // TODO: PPC port
2826     // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2827     // StoreStore barrier conditionally.
2828     __ lwz(R0, 0, $releaseFieldAddr$$Register);
2829     __ cmpwi($crx$$CondRegister, R0, 0);
2830     __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2831 #endif
2832     __ li(R0, 0);
2833     __ membar(Assembler::StoreStore);
2834 #if 0 // TODO: PPC port
2835     __ bind(skip_storestore);
2836 #endif
2837 
2838     // Do the store.
2839     if ($mem$$index == 0) {
2840       __ stb(R0, $mem$$disp, $mem$$base$$Register);
2841     } else {
2842       assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2843       __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2844     }
2845   %}
2846 
2847   enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2848 
2849     if (VM_Version::has_isel()) {
2850       // use isel instruction with Power 7
2851       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2852       encodeP_subNode    *n_sub_base = new encodeP_subNode();
2853       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2854       cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2855 
2856       n_compare->add_req(n_region, n_src);
2857       n_compare->_opnds[0] = op_crx;
2858       n_compare->_opnds[1] = op_src;
2859       n_compare->_opnds[2] = new immL16Oper(0);
2860 
2861       n_sub_base->add_req(n_region, n_src);
2862       n_sub_base->_opnds[0] = op_dst;
2863       n_sub_base->_opnds[1] = op_src;
2864       n_sub_base->_bottom_type = _bottom_type;
2865 
2866       n_shift->add_req(n_region, n_sub_base);
2867       n_shift->_opnds[0] = op_dst;
2868       n_shift->_opnds[1] = op_dst;
2869       n_shift->_bottom_type = _bottom_type;
2870 
2871       n_cond_set->add_req(n_region, n_compare, n_shift);
2872       n_cond_set->_opnds[0] = op_dst;
2873       n_cond_set->_opnds[1] = op_crx;
2874       n_cond_set->_opnds[2] = op_dst;
2875       n_cond_set->_bottom_type = _bottom_type;
2876 
2877       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2878       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2879       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2880       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2881 
2882       nodes->push(n_compare);
2883       nodes->push(n_sub_base);
2884       nodes->push(n_shift);
2885       nodes->push(n_cond_set);
2886 
2887     } else {
2888       // before Power 7
2889       moveRegNode        *n_move     = new moveRegNode();
2890       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2891       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2892       cond_sub_baseNode  *n_sub_base = new cond_sub_baseNode();
2893 
2894       n_move->add_req(n_region, n_src);
2895       n_move->_opnds[0] = op_dst;
2896       n_move->_opnds[1] = op_src;
2897       ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2898 
2899       n_compare->add_req(n_region, n_src);
2900       n_compare->add_prec(n_move);
2901 
2902       n_compare->_opnds[0] = op_crx;
2903       n_compare->_opnds[1] = op_src;
2904       n_compare->_opnds[2] = new immL16Oper(0);
2905 
2906       n_sub_base->add_req(n_region, n_compare, n_src);
2907       n_sub_base->_opnds[0] = op_dst;
2908       n_sub_base->_opnds[1] = op_crx;
2909       n_sub_base->_opnds[2] = op_src;
2910       n_sub_base->_bottom_type = _bottom_type;
2911 
2912       n_shift->add_req(n_region, n_sub_base);
2913       n_shift->_opnds[0] = op_dst;
2914       n_shift->_opnds[1] = op_dst;
2915       n_shift->_bottom_type = _bottom_type;
2916 
2917       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2918       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2919       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2920       ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2921 
2922       nodes->push(n_move);
2923       nodes->push(n_compare);
2924       nodes->push(n_sub_base);
2925       nodes->push(n_shift);
2926     }
2927 
2928     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2929   %}
2930 
2931   enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2932 
2933     encodeP_subNode *n1 = new encodeP_subNode();
2934     n1->add_req(n_region, n_src);
2935     n1->_opnds[0] = op_dst;
2936     n1->_opnds[1] = op_src;
2937     n1->_bottom_type = _bottom_type;
2938 
2939     encodeP_shiftNode *n2 = new encodeP_shiftNode();
2940     n2->add_req(n_region, n1);
2941     n2->_opnds[0] = op_dst;
2942     n2->_opnds[1] = op_dst;
2943     n2->_bottom_type = _bottom_type;
2944     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2945     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2946 
2947     nodes->push(n1);
2948     nodes->push(n2);
2949     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2950   %}
2951 
2952   enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2953     decodeN_shiftNode *n_shift    = new decodeN_shiftNode();
2954     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
2955 
2956     n_compare->add_req(n_region, n_src);
2957     n_compare->_opnds[0] = op_crx;
2958     n_compare->_opnds[1] = op_src;
2959     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2960 
2961     n_shift->add_req(n_region, n_src);
2962     n_shift->_opnds[0] = op_dst;
2963     n_shift->_opnds[1] = op_src;
2964     n_shift->_bottom_type = _bottom_type;
2965 
2966     if (VM_Version::has_isel()) {
2967       // use isel instruction with Power 7
2968 
2969       decodeN_addNode *n_add_base = new decodeN_addNode();
2970       n_add_base->add_req(n_region, n_shift);
2971       n_add_base->_opnds[0] = op_dst;
2972       n_add_base->_opnds[1] = op_dst;
2973       n_add_base->_bottom_type = _bottom_type;
2974 
2975       cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2976       n_cond_set->add_req(n_region, n_compare, n_add_base);
2977       n_cond_set->_opnds[0] = op_dst;
2978       n_cond_set->_opnds[1] = op_crx;
2979       n_cond_set->_opnds[2] = op_dst;
2980       n_cond_set->_bottom_type = _bottom_type;
2981 
2982       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2983       ra_->set_oop(n_cond_set, true);
2984 
2985       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2986       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2987       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2988       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2989 
2990       nodes->push(n_compare);
2991       nodes->push(n_shift);
2992       nodes->push(n_add_base);
2993       nodes->push(n_cond_set);
2994 
2995     } else {
2996       // before Power 7
2997       cond_add_baseNode *n_add_base = new cond_add_baseNode();
2998 
2999       n_add_base->add_req(n_region, n_compare, n_shift);
3000       n_add_base->_opnds[0] = op_dst;
3001       n_add_base->_opnds[1] = op_crx;
3002       n_add_base->_opnds[2] = op_dst;
3003       n_add_base->_bottom_type = _bottom_type;
3004 
3005       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3006       ra_->set_oop(n_add_base, true);
3007 
3008       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3009       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
3010       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3011 
3012       nodes->push(n_compare);
3013       nodes->push(n_shift);
3014       nodes->push(n_add_base);
3015     }
3016   %}
3017 
3018   enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
3019     decodeN_shiftNode *n1 = new decodeN_shiftNode();
3020     n1->add_req(n_region, n_src);
3021     n1->_opnds[0] = op_dst;
3022     n1->_opnds[1] = op_src;
3023     n1->_bottom_type = _bottom_type;
3024 
3025     decodeN_addNode *n2 = new decodeN_addNode();
3026     n2->add_req(n_region, n1);
3027     n2->_opnds[0] = op_dst;
3028     n2->_opnds[1] = op_dst;
3029     n2->_bottom_type = _bottom_type;
3030     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3031     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3032 
3033     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3034     ra_->set_oop(n2, true);
3035 
3036     nodes->push(n1);
3037     nodes->push(n2);
3038   %}
3039 
3040   enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3041     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3042 
3043     MacroAssembler _masm(&cbuf);
3044     int cc        = $cmp$$cmpcode;
3045     int flags_reg = $crx$$reg;
3046     Label done;
3047     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3048     // Branch if not (cmp crx).
3049     __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3050     __ mr($dst$$Register, $src$$Register);
3051     // TODO PPC port __ endgroup_if_needed(_size == 12);
3052     __ bind(done);
3053   %}
3054 
3055   enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3056     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3057 
3058     MacroAssembler _masm(&cbuf);
3059     Label done;
3060     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3061     // Branch if not (cmp crx).
3062     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3063     __ li($dst$$Register, $src$$constant);
3064     // TODO PPC port __ endgroup_if_needed(_size == 12);
3065     __ bind(done);
3066   %}
3067 
3068   // New atomics.
3069   enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3070     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3071 
3072     MacroAssembler _masm(&cbuf);
3073     Register Rtmp   = R0;
3074     Register Rres   = $res$$Register;
3075     Register Rsrc   = $src$$Register;
3076     Register Rptr   = $mem_ptr$$Register;
3077     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3078     Register Rold   = RegCollision ? Rtmp : Rres;
3079 
3080     Label Lretry;
3081     __ bind(Lretry);
3082     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3083     __ add(Rtmp, Rsrc, Rold);
3084     __ stwcx_(Rtmp, Rptr);
3085     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3086       __ bne_predict_not_taken(CCR0, Lretry);
3087     } else {
3088       __ bne(                  CCR0, Lretry);
3089     }
3090     if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3091     __ fence();
3092   %}
3093 
3094   enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3095     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3096 
3097     MacroAssembler _masm(&cbuf);
3098     Register Rtmp   = R0;
3099     Register Rres   = $res$$Register;
3100     Register Rsrc   = $src$$Register;
3101     Register Rptr   = $mem_ptr$$Register;
3102     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3103     Register Rold   = RegCollision ? Rtmp : Rres;
3104 
3105     Label Lretry;
3106     __ bind(Lretry);
3107     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3108     __ add(Rtmp, Rsrc, Rold);
3109     __ stdcx_(Rtmp, Rptr);
3110     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3111       __ bne_predict_not_taken(CCR0, Lretry);
3112     } else {
3113       __ bne(                  CCR0, Lretry);
3114     }
3115     if (RegCollision) __ subf(Rres, Rsrc, Rtmp);
3116     __ fence();
3117   %}
3118 
3119   enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{
3120     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3121 
3122     MacroAssembler _masm(&cbuf);
3123     Register Rtmp   = R0;
3124     Register Rres   = $res$$Register;
3125     Register Rsrc   = $src$$Register;
3126     Register Rptr   = $mem_ptr$$Register;
3127     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3128     Register Rold   = RegCollision ? Rtmp : Rres;
3129 
3130     Label Lretry;
3131     __ bind(Lretry);
3132     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3133     __ stwcx_(Rsrc, Rptr);
3134     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3135       __ bne_predict_not_taken(CCR0, Lretry);
3136     } else {
3137       __ bne(                  CCR0, Lretry);
3138     }
3139     if (RegCollision) __ mr(Rres, Rtmp);
3140     __ fence();
3141   %}
3142 
3143   enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{
3144     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3145 
3146     MacroAssembler _masm(&cbuf);
3147     Register Rtmp   = R0;
3148     Register Rres   = $res$$Register;
3149     Register Rsrc   = $src$$Register;
3150     Register Rptr   = $mem_ptr$$Register;
3151     bool RegCollision = (Rres == Rsrc) || (Rres == Rptr);
3152     Register Rold   = RegCollision ? Rtmp : Rres;
3153 
3154     Label Lretry;
3155     __ bind(Lretry);
3156     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3157     __ stdcx_(Rsrc, Rptr);
3158     if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3159       __ bne_predict_not_taken(CCR0, Lretry);
3160     } else {
3161       __ bne(                  CCR0, Lretry);
3162     }
3163     if (RegCollision) __ mr(Rres, Rtmp);
3164     __ fence();
3165   %}
3166 
3167   // This enc_class is needed so that scheduler gets proper
3168   // input mapping for latency computation.
3169   enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3170     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3171     MacroAssembler _masm(&cbuf);
3172     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3173   %}
3174 
3175   enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3176     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3177 
3178     MacroAssembler _masm(&cbuf);
3179 
3180     Label done;
3181     __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3182     __ li($dst$$Register, $zero$$constant);
3183     __ beq($crx$$CondRegister, done);
3184     __ li($dst$$Register, $notzero$$constant);
3185     __ bind(done);
3186   %}
3187 
3188   enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3189     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3190 
3191     MacroAssembler _masm(&cbuf);
3192 
3193     Label done;
3194     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3195     __ li($dst$$Register, $zero$$constant);
3196     __ beq($crx$$CondRegister, done);
3197     __ li($dst$$Register, $notzero$$constant);
3198     __ bind(done);
3199   %}
3200 
3201   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3202     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3203 
3204     MacroAssembler _masm(&cbuf);
3205     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3206     Label done;
3207     __ bso($crx$$CondRegister, done);
3208     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3209     // TODO PPC port __ endgroup_if_needed(_size == 12);
3210     __ bind(done);
3211   %}
3212 
3213   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3214     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3215 
3216     MacroAssembler _masm(&cbuf);
3217     Label d;   // dummy
3218     __ bind(d);
3219     Label* p = ($lbl$$label);
3220     // `p' is `NULL' when this encoding class is used only to
3221     // determine the size of the encoded instruction.
3222     Label& l = (NULL == p)? d : *(p);
3223     int cc = $cmp$$cmpcode;
3224     int flags_reg = $crx$$reg;
3225     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3226     int bhint = Assembler::bhintNoHint;
3227 
3228     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3229       if (_prob <= PROB_NEVER) {
3230         bhint = Assembler::bhintIsNotTaken;
3231       } else if (_prob >= PROB_ALWAYS) {
3232         bhint = Assembler::bhintIsTaken;
3233       }
3234     }
3235 
3236     __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3237           cc_to_biint(cc, flags_reg),
3238           l);
3239   %}
3240 
3241   enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3242     // The scheduler doesn't know about branch shortening, so we set the opcode
3243     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3244     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3245 
3246     MacroAssembler _masm(&cbuf);
3247     Label d;    // dummy
3248     __ bind(d);
3249     Label* p = ($lbl$$label);
3250     // `p' is `NULL' when this encoding class is used only to
3251     // determine the size of the encoded instruction.
3252     Label& l = (NULL == p)? d : *(p);
3253     int cc = $cmp$$cmpcode;
3254     int flags_reg = $crx$$reg;
3255     int bhint = Assembler::bhintNoHint;
3256 
3257     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3258       if (_prob <= PROB_NEVER) {
3259         bhint = Assembler::bhintIsNotTaken;
3260       } else if (_prob >= PROB_ALWAYS) {
3261         bhint = Assembler::bhintIsTaken;
3262       }
3263     }
3264 
3265     // Tell the conditional far branch to optimize itself when being relocated.
3266     __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3267                   cc_to_biint(cc, flags_reg),
3268                   l,
3269                   MacroAssembler::bc_far_optimize_on_relocate);
3270   %}
3271 
3272   // Branch used with Power6 scheduling (can be shortened without changing the node).
3273   enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3274     // The scheduler doesn't know about branch shortening, so we set the opcode
3275     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3276     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3277 
3278     MacroAssembler _masm(&cbuf);
3279     Label d;   // dummy
3280     __ bind(d);
3281     Label* p = ($lbl$$label);
3282     // `p' is `NULL' when this encoding class is used only to
3283     // determine the size of the encoded instruction.
3284     Label& l = (NULL == p)? d : *(p);
3285     int cc = $cmp$$cmpcode;
3286     int flags_reg = $crx$$reg;
3287     int bhint = Assembler::bhintNoHint;
3288 
3289     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3290       if (_prob <= PROB_NEVER) {
3291         bhint = Assembler::bhintIsNotTaken;
3292       } else if (_prob >= PROB_ALWAYS) {
3293         bhint = Assembler::bhintIsTaken;
3294       }
3295     }
3296 
3297 #if 0 // TODO: PPC port
3298     if (_size == 8) {
3299       // Tell the conditional far branch to optimize itself when being relocated.
3300       __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3301                     cc_to_biint(cc, flags_reg),
3302                     l,
3303                     MacroAssembler::bc_far_optimize_on_relocate);
3304     } else {
3305       __ bc    (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3306                     cc_to_biint(cc, flags_reg),
3307                     l);
3308     }
3309 #endif
3310     Unimplemented();
3311   %}
3312 
3313   // Postalloc expand emitter for loading a replicatef float constant from
3314   // the method's TOC.
3315   // Enc_class needed as consttanttablebase is not supported by postalloc
3316   // expand.
3317   enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3318     // Create new nodes.
3319 
3320     // Make an operand with the bit pattern to load as float.
3321     immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3322 
3323     loadConLNodesTuple loadConLNodes =
3324       loadConLNodesTuple_create(ra_, n_toc, op_repl,
3325                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
3326 
3327     // Push new nodes.
3328     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3329     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
3330 
3331     assert(nodes->length() >= 1, "must have created at least 1 node");
3332     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3333   %}
3334 
3335   // This enc_class is needed so that scheduler gets proper
3336   // input mapping for latency computation.
3337   enc_class enc_poll(immI dst, iRegLdst poll) %{
3338     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3339     // Fake operand dst needed for PPC scheduler.
3340     assert($dst$$constant == 0x0, "dst must be 0x0");
3341 
3342     MacroAssembler _masm(&cbuf);
3343     // Mark the code position where the load from the safepoint
3344     // polling page was emitted as relocInfo::poll_type.
3345     __ relocate(relocInfo::poll_type);
3346     __ load_from_polling_page($poll$$Register);
3347   %}
3348 
3349   // A Java static call or a runtime call.
3350   //
3351   // Branch-and-link relative to a trampoline.
3352   // The trampoline loads the target address and does a long branch to there.
3353   // In case we call java, the trampoline branches to a interpreter_stub
3354   // which loads the inline cache and the real call target from the constant pool.
3355   //
3356   // This basically looks like this:
3357   //
3358   // >>>> consts      -+  -+
3359   //                   |   |- offset1
3360   // [call target1]    | <-+
3361   // [IC cache]        |- offset2
3362   // [call target2] <--+
3363   //
3364   // <<<< consts
3365   // >>>> insts
3366   //
3367   // bl offset16               -+  -+             ??? // How many bits available?
3368   //                            |   |
3369   // <<<< insts                 |   |
3370   // >>>> stubs                 |   |
3371   //                            |   |- trampoline_stub_Reloc
3372   // trampoline stub:           | <-+
3373   //   r2 = toc                 |
3374   //   r2 = [r2 + offset1]      |       // Load call target1 from const section
3375   //   mtctr r2                 |
3376   //   bctr                     |- static_stub_Reloc
3377   // comp_to_interp_stub:   <---+
3378   //   r1 = toc
3379   //   ICreg = [r1 + IC_offset]         // Load IC from const section
3380   //   r1    = [r1 + offset2]           // Load call target2 from const section
3381   //   mtctr r1
3382   //   bctr
3383   //
3384   // <<<< stubs
3385   //
3386   // The call instruction in the code either
3387   // - Branches directly to a compiled method if the offset is encodable in instruction.
3388   // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3389   // - Branches to the compiled_to_interp stub if the target is interpreted.
3390   //
3391   // Further there are three relocations from the loads to the constants in
3392   // the constant section.
3393   //
3394   // Usage of r1 and r2 in the stubs allows to distinguish them.
3395   enc_class enc_java_static_call(method meth) %{
3396     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3397 
3398     MacroAssembler _masm(&cbuf);
3399     address entry_point = (address)$meth$$method;
3400 
3401     if (!_method) {
3402       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3403       emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3404     } else {
3405       // Remember the offset not the address.
3406       const int start_offset = __ offset();
3407       // The trampoline stub.
3408       if (!Compile::current()->in_scratch_emit_size()) {
3409         // No entry point given, use the current pc.
3410         // Make sure branch fits into
3411         if (entry_point == 0) entry_point = __ pc();
3412 
3413         // Put the entry point as a constant into the constant pool.
3414         const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
3415         if (entry_point_toc_addr == NULL) {
3416           ciEnv::current()->record_out_of_memory_failure();
3417           return;
3418         }
3419         const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3420 
3421 
3422         // Emit the trampoline stub which will be related to the branch-and-link below.
3423         CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3424         if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3425         int method_index = resolved_method_index(cbuf);
3426         __ relocate(_optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
3427                                        : static_call_Relocation::spec(method_index));
3428       }
3429 
3430       // The real call.
3431       // Note: At this point we do not have the address of the trampoline
3432       // stub, and the entry point might be too far away for bl, so __ pc()
3433       // serves as dummy and the bl will be patched later.
3434       cbuf.set_insts_mark();
3435       __ bl(__ pc());  // Emits a relocation.
3436 
3437       // The stub for call to interpreter.
3438       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3439       if (stub == NULL) {
3440         ciEnv::current()->record_failure("CodeCache is full");
3441         return;
3442       }
3443     }
3444   %}
3445 
3446   // Second node of expanded dynamic call - the call.
3447   enc_class enc_java_dynamic_call_sched(method meth) %{
3448     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3449 
3450     MacroAssembler _masm(&cbuf);
3451 
3452     if (!ra_->C->in_scratch_emit_size()) {
3453       // Create a call trampoline stub for the given method.
3454       const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3455       const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3456       if (entry_point_const == NULL) {
3457         ciEnv::current()->record_out_of_memory_failure();
3458         return;
3459       }
3460       const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3461       CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3462       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3463 
3464       // Build relocation at call site with ic position as data.
3465       assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3466              (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3467              "must have one, but can't have both");
3468       assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3469              (_load_ic_node != NULL    && _load_ic_node->_cbuf_insts_offset != -1),
3470              "must contain instruction offset");
3471       const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3472         ? _load_ic_hi_node->_cbuf_insts_offset
3473         : _load_ic_node->_cbuf_insts_offset;
3474       const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3475       assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3476              "should be load from TOC");
3477       int method_index = resolved_method_index(cbuf);
3478       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
3479     }
3480 
3481     // At this point I do not have the address of the trampoline stub,
3482     // and the entry point might be too far away for bl. Pc() serves
3483     // as dummy and bl will be patched later.
3484     __ bl((address) __ pc());
3485   %}
3486 
3487   // postalloc expand emitter for virtual calls.
3488   enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3489 
3490     // Create the nodes for loading the IC from the TOC.
3491     loadConLNodesTuple loadConLNodes_IC =
3492       loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3493                                 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3494 
3495     // Create the call node.
3496     CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3497     call->_method_handle_invoke = _method_handle_invoke;
3498     call->_vtable_index      = _vtable_index;
3499     call->_method            = _method;
3500     call->_bci               = _bci;
3501     call->_optimized_virtual = _optimized_virtual;
3502     call->_tf                = _tf;
3503     call->_entry_point       = _entry_point;
3504     call->_cnt               = _cnt;
3505     call->_argsize           = _argsize;
3506     call->_oop_map           = _oop_map;
3507     call->_jvms              = _jvms;
3508     call->_jvmadj            = _jvmadj;
3509     call->_in_rms            = _in_rms;
3510     call->_nesting           = _nesting;
3511     call->_override_symbolic_info = _override_symbolic_info;
3512 
3513     // New call needs all inputs of old call.
3514     // Req...
3515     for (uint i = 0; i < req(); ++i) {
3516       // The expanded node does not need toc any more.
3517       // Add the inline cache constant here instead. This expresses the
3518       // register of the inline cache must be live at the call.
3519       // Else we would have to adapt JVMState by -1.
3520       if (i == mach_constant_base_node_input()) {
3521         call->add_req(loadConLNodes_IC._last);
3522       } else {
3523         call->add_req(in(i));
3524       }
3525     }
3526     // ...as well as prec
3527     for (uint i = req(); i < len(); ++i) {
3528       call->add_prec(in(i));
3529     }
3530 
3531     // Remember nodes loading the inline cache into r19.
3532     call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3533     call->_load_ic_node    = loadConLNodes_IC._small;
3534 
3535     // Operands for new nodes.
3536     call->_opnds[0] = _opnds[0];
3537     call->_opnds[1] = _opnds[1];
3538 
3539     // Only the inline cache is associated with a register.
3540     assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3541 
3542     // Push new nodes.
3543     if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3544     if (loadConLNodes_IC._last)     nodes->push(loadConLNodes_IC._last);
3545     nodes->push(call);
3546   %}
3547 
3548   // Compound version of call dynamic
3549   // Toc is only passed so that it can be used in ins_encode statement.
3550   // In the code we have to use $constanttablebase.
3551   enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3552     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3553     MacroAssembler _masm(&cbuf);
3554     int start_offset = __ offset();
3555 
3556     Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3557 #if 0
3558     int vtable_index = this->_vtable_index;
3559     if (_vtable_index < 0) {
3560       // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3561       assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3562       Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3563 
3564       // Virtual call relocation will point to ic load.
3565       address virtual_call_meta_addr = __ pc();
3566       // Load a clear inline cache.
3567       AddressLiteral empty_ic((address) Universe::non_oop_word());
3568       bool success = __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc, /*fixed_size*/ true);
3569       if (!success) {
3570         ciEnv::current()->record_out_of_memory_failure();
3571         return;
3572       }
3573       // CALL to fixup routine.  Fixup routine uses ScopeDesc info
3574       // to determine who we intended to call.
3575       __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3576       emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3577       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3578              "Fix constant in ret_addr_offset()");
3579     } else {
3580       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3581       // Go thru the vtable. Get receiver klass. Receiver already
3582       // checked for non-null. If we'll go thru a C2I adapter, the
3583       // interpreter expects method in R19_method.
3584 
3585       __ load_klass(R11_scratch1, R3);
3586 
3587       int entry_offset = in_bytes(Klass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes();
3588       int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
3589       __ li(R19_method, v_off);
3590       __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3591       // NOTE: for vtable dispatches, the vtable entry will never be
3592       // null. However it may very well end up in handle_wrong_method
3593       // if the method is abstract for the particular class.
3594       __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3595       // Call target. Either compiled code or C2I adapter.
3596       __ mtctr(R11_scratch1);
3597       __ bctrl();
3598       if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3599         tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3600       }
3601       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3602              "Fix constant in ret_addr_offset()");
3603     }
3604 #endif
3605     Unimplemented();  // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3606   %}
3607 
3608   // a runtime call
3609   enc_class enc_java_to_runtime_call (method meth) %{
3610     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3611 
3612     MacroAssembler _masm(&cbuf);
3613     const address start_pc = __ pc();
3614 
3615 #if defined(ABI_ELFv2)
3616     address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3617     __ call_c(entry, relocInfo::runtime_call_type);
3618 #else
3619     // The function we're going to call.
3620     FunctionDescriptor fdtemp;
3621     const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3622 
3623     Register Rtoc = R12_scratch2;
3624     // Calculate the method's TOC.
3625     __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3626     // Put entry, env, toc into the constant pool, this needs up to 3 constant
3627     // pool entries; call_c_using_toc will optimize the call.
3628     bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3629     if (!success) {
3630       ciEnv::current()->record_out_of_memory_failure();
3631       return;
3632     }
3633 #endif
3634 
3635     // Check the ret_addr_offset.
3636     assert(((MachCallRuntimeNode*)this)->ret_addr_offset() ==  __ last_calls_return_pc() - start_pc,
3637            "Fix constant in ret_addr_offset()");
3638   %}
3639 
3640   // Move to ctr for leaf call.
3641   // This enc_class is needed so that scheduler gets proper
3642   // input mapping for latency computation.
3643   enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3644     // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3645     MacroAssembler _masm(&cbuf);
3646     __ mtctr($src$$Register);
3647   %}
3648 
3649   // Postalloc expand emitter for runtime leaf calls.
3650   enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3651     loadConLNodesTuple loadConLNodes_Entry;
3652 #if defined(ABI_ELFv2)
3653     jlong entry_address = (jlong) this->entry_point();
3654     assert(entry_address, "need address here");
3655     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3656                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3657 #else
3658     // Get the struct that describes the function we are about to call.
3659     FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3660     assert(fd, "need fd here");
3661     jlong entry_address = (jlong) fd->entry();
3662     // new nodes
3663     loadConLNodesTuple loadConLNodes_Env;
3664     loadConLNodesTuple loadConLNodes_Toc;
3665 
3666     // Create nodes and operands for loading the entry point.
3667     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3668                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3669 
3670 
3671     // Create nodes and operands for loading the env pointer.
3672     if (fd->env() != NULL) {
3673       loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3674                                                     OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3675     } else {
3676       loadConLNodes_Env._large_hi = NULL;
3677       loadConLNodes_Env._large_lo = NULL;
3678       loadConLNodes_Env._small    = NULL;
3679       loadConLNodes_Env._last = new loadConL16Node();
3680       loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3681       loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3682       ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3683     }
3684 
3685     // Create nodes and operands for loading the Toc point.
3686     loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3687                                                   OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3688 #endif // ABI_ELFv2
3689     // mtctr node
3690     MachNode *mtctr = new CallLeafDirect_mtctrNode();
3691 
3692     assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3693     mtctr->add_req(0, loadConLNodes_Entry._last);
3694 
3695     mtctr->_opnds[0] = new iRegLdstOper();
3696     mtctr->_opnds[1] = new iRegLdstOper();
3697 
3698     // call node
3699     MachCallLeafNode *call = new CallLeafDirectNode();
3700 
3701     call->_opnds[0] = _opnds[0];
3702     call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3703 
3704     // Make the new call node look like the old one.
3705     call->_name        = _name;
3706     call->_tf          = _tf;
3707     call->_entry_point = _entry_point;
3708     call->_cnt         = _cnt;
3709     call->_argsize     = _argsize;
3710     call->_oop_map     = _oop_map;
3711     guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3712     call->_jvms        = NULL;
3713     call->_jvmadj      = _jvmadj;
3714     call->_in_rms      = _in_rms;
3715     call->_nesting     = _nesting;
3716 
3717 
3718     // New call needs all inputs of old call.
3719     // Req...
3720     for (uint i = 0; i < req(); ++i) {
3721       if (i != mach_constant_base_node_input()) {
3722         call->add_req(in(i));
3723       }
3724     }
3725 
3726     // These must be reqired edges, as the registers are live up to
3727     // the call. Else the constants are handled as kills.
3728     call->add_req(mtctr);
3729 #if !defined(ABI_ELFv2)
3730     call->add_req(loadConLNodes_Env._last);
3731     call->add_req(loadConLNodes_Toc._last);
3732 #endif
3733 
3734     // ...as well as prec
3735     for (uint i = req(); i < len(); ++i) {
3736       call->add_prec(in(i));
3737     }
3738 
3739     // registers
3740     ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3741 
3742     // Insert the new nodes.
3743     if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3744     if (loadConLNodes_Entry._last)     nodes->push(loadConLNodes_Entry._last);
3745 #if !defined(ABI_ELFv2)
3746     if (loadConLNodes_Env._large_hi)   nodes->push(loadConLNodes_Env._large_hi);
3747     if (loadConLNodes_Env._last)       nodes->push(loadConLNodes_Env._last);
3748     if (loadConLNodes_Toc._large_hi)   nodes->push(loadConLNodes_Toc._large_hi);
3749     if (loadConLNodes_Toc._last)       nodes->push(loadConLNodes_Toc._last);
3750 #endif
3751     nodes->push(mtctr);
3752     nodes->push(call);
3753   %}
3754 %}
3755 
3756 //----------FRAME--------------------------------------------------------------
3757 // Definition of frame structure and management information.
3758 
3759 frame %{
3760   // What direction does stack grow in (assumed to be same for native & Java).
3761   stack_direction(TOWARDS_LOW);
3762 
3763   // These two registers define part of the calling convention between
3764   // compiled code and the interpreter.
3765 
3766   // Inline Cache Register or method for I2C.
3767   inline_cache_reg(R19); // R19_method
3768 
3769   // Method Oop Register when calling interpreter.
3770   interpreter_method_oop_reg(R19); // R19_method
3771 
3772   // Optional: name the operand used by cisc-spilling to access
3773   // [stack_pointer + offset].
3774   cisc_spilling_operand_name(indOffset);
3775 
3776   // Number of stack slots consumed by a Monitor enter.
3777   sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3778 
3779   // Compiled code's Frame Pointer.
3780   frame_pointer(R1); // R1_SP
3781 
3782   // Interpreter stores its frame pointer in a register which is
3783   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3784   // interpreted java to compiled java.
3785   //
3786   // R14_state holds pointer to caller's cInterpreter.
3787   interpreter_frame_pointer(R14); // R14_state
3788 
3789   stack_alignment(frame::alignment_in_bytes);
3790 
3791   in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3792 
3793   // Number of outgoing stack slots killed above the
3794   // out_preserve_stack_slots for calls to C. Supports the var-args
3795   // backing area for register parms.
3796   //
3797   varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3798 
3799   // The after-PROLOG location of the return address. Location of
3800   // return address specifies a type (REG or STACK) and a number
3801   // representing the register number (i.e. - use a register name) or
3802   // stack slot.
3803   //
3804   // A: Link register is stored in stack slot ...
3805   // M:  ... but it's in the caller's frame according to PPC-64 ABI.
3806   // J: Therefore, we make sure that the link register is also in R11_scratch1
3807   //    at the end of the prolog.
3808   // B: We use R20, now.
3809   //return_addr(REG R20);
3810 
3811   // G: After reading the comments made by all the luminaries on their
3812   //    failure to tell the compiler where the return address really is,
3813   //    I hardly dare to try myself.  However, I'm convinced it's in slot
3814   //    4 what apparently works and saves us some spills.
3815   return_addr(STACK 4);
3816 
3817   // This is the body of the function
3818   //
3819   // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3820   //                                  uint length,      // length of array
3821   //                                  bool is_outgoing)
3822   //
3823   // The `sig' array is to be updated. sig[j] represents the location
3824   // of the j-th argument, either a register or a stack slot.
3825 
3826   // Comment taken from i486.ad:
3827   // Body of function which returns an integer array locating
3828   // arguments either in registers or in stack slots. Passed an array
3829   // of ideal registers called "sig" and a "length" count. Stack-slot
3830   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3831   // arguments for a CALLEE. Incoming stack arguments are
3832   // automatically biased by the preserve_stack_slots field above.
3833   calling_convention %{
3834     // No difference between ingoing/outgoing. Just pass false.
3835     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3836   %}
3837 
3838   // Comment taken from i486.ad:
3839   // Body of function which returns an integer array locating
3840   // arguments either in registers or in stack slots. Passed an array
3841   // of ideal registers called "sig" and a "length" count. Stack-slot
3842   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3843   // arguments for a CALLEE. Incoming stack arguments are
3844   // automatically biased by the preserve_stack_slots field above.
3845   c_calling_convention %{
3846     // This is obviously always outgoing.
3847     // C argument in register AND stack slot.
3848     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3849   %}
3850 
3851   // Location of native (C/C++) and interpreter return values. This
3852   // is specified to be the same as Java. In the 32-bit VM, long
3853   // values are actually returned from native calls in O0:O1 and
3854   // returned to the interpreter in I0:I1. The copying to and from
3855   // the register pairs is done by the appropriate call and epilog
3856   // opcodes. This simplifies the register allocator.
3857   c_return_value %{
3858     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3859             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3860             "only return normal values");
3861     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3862     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3863     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3864     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3865   %}
3866 
3867   // Location of compiled Java return values.  Same as C
3868   return_value %{
3869     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3870             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3871             "only return normal values");
3872     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3873     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3874     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3875     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3876   %}
3877 %}
3878 
3879 
3880 //----------ATTRIBUTES---------------------------------------------------------
3881 
3882 //----------Operand Attributes-------------------------------------------------
3883 op_attrib op_cost(1);          // Required cost attribute.
3884 
3885 //----------Instruction Attributes---------------------------------------------
3886 
3887 // Cost attribute. required.
3888 ins_attrib ins_cost(DEFAULT_COST);
3889 
3890 // Is this instruction a non-matching short branch variant of some
3891 // long branch? Not required.
3892 ins_attrib ins_short_branch(0);
3893 
3894 ins_attrib ins_is_TrapBasedCheckNode(true);
3895 
3896 // Number of constants.
3897 // This instruction uses the given number of constants
3898 // (optional attribute).
3899 // This is needed to determine in time whether the constant pool will
3900 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3901 // is determined. It's also used to compute the constant pool size
3902 // in Output().
3903 ins_attrib ins_num_consts(0);
3904 
3905 // Required alignment attribute (must be a power of 2) specifies the
3906 // alignment that some part of the instruction (not necessarily the
3907 // start) requires. If > 1, a compute_padding() function must be
3908 // provided for the instruction.
3909 ins_attrib ins_alignment(1);
3910 
3911 // Enforce/prohibit rematerializations.
3912 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3913 //   then rematerialization of that instruction is prohibited and the
3914 //   instruction's value will be spilled if necessary.
3915 //   Causes that MachNode::rematerialize() returns false.
3916 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3917 //   then rematerialization should be enforced and a copy of the instruction
3918 //   should be inserted if possible; rematerialization is not guaranteed.
3919 //   Note: this may result in rematerializations in front of every use.
3920 //   Causes that MachNode::rematerialize() can return true.
3921 // (optional attribute)
3922 ins_attrib ins_cannot_rematerialize(false);
3923 ins_attrib ins_should_rematerialize(false);
3924 
3925 // Instruction has variable size depending on alignment.
3926 ins_attrib ins_variable_size_depending_on_alignment(false);
3927 
3928 // Instruction is a nop.
3929 ins_attrib ins_is_nop(false);
3930 
3931 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3932 ins_attrib ins_use_mach_if_fast_lock_node(false);
3933 
3934 // Field for the toc offset of a constant.
3935 //
3936 // This is needed if the toc offset is not encodable as an immediate in
3937 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3938 // added to the toc, and from this a load with immediate is performed.
3939 // With postalloc expand, we get two nodes that require the same offset
3940 // but which don't know about each other. The offset is only known
3941 // when the constant is added to the constant pool during emitting.
3942 // It is generated in the 'hi'-node adding the upper bits, and saved
3943 // in this node.  The 'lo'-node has a link to the 'hi'-node and reads
3944 // the offset from there when it gets encoded.
3945 ins_attrib ins_field_const_toc_offset(0);
3946 ins_attrib ins_field_const_toc_offset_hi_node(0);
3947 
3948 // A field that can hold the instructions offset in the code buffer.
3949 // Set in the nodes emitter.
3950 ins_attrib ins_field_cbuf_insts_offset(-1);
3951 
3952 // Fields for referencing a call's load-IC-node.
3953 // If the toc offset can not be encoded as an immediate in a load, we
3954 // use two nodes.
3955 ins_attrib ins_field_load_ic_hi_node(0);
3956 ins_attrib ins_field_load_ic_node(0);
3957 
3958 //----------OPERANDS-----------------------------------------------------------
3959 // Operand definitions must precede instruction definitions for correct
3960 // parsing in the ADLC because operands constitute user defined types
3961 // which are used in instruction definitions.
3962 //
3963 // Formats are generated automatically for constants and base registers.
3964 
3965 //----------Simple Operands----------------------------------------------------
3966 // Immediate Operands
3967 
3968 // Integer Immediate: 32-bit
3969 operand immI() %{
3970   match(ConI);
3971   op_cost(40);
3972   format %{ %}
3973   interface(CONST_INTER);
3974 %}
3975 
3976 operand immI8() %{
3977   predicate(Assembler::is_simm(n->get_int(), 8));
3978   op_cost(0);
3979   match(ConI);
3980   format %{ %}
3981   interface(CONST_INTER);
3982 %}
3983 
3984 // Integer Immediate: 16-bit
3985 operand immI16() %{
3986   predicate(Assembler::is_simm(n->get_int(), 16));
3987   op_cost(0);
3988   match(ConI);
3989   format %{ %}
3990   interface(CONST_INTER);
3991 %}
3992 
3993 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
3994 operand immIhi16() %{
3995   predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
3996   match(ConI);
3997   op_cost(0);
3998   format %{ %}
3999   interface(CONST_INTER);
4000 %}
4001 
4002 operand immInegpow2() %{
4003   predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
4004   match(ConI);
4005   op_cost(0);
4006   format %{ %}
4007   interface(CONST_INTER);
4008 %}
4009 
4010 operand immIpow2minus1() %{
4011   predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
4012   match(ConI);
4013   op_cost(0);
4014   format %{ %}
4015   interface(CONST_INTER);
4016 %}
4017 
4018 operand immIpowerOf2() %{
4019   predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
4020   match(ConI);
4021   op_cost(0);
4022   format %{ %}
4023   interface(CONST_INTER);
4024 %}
4025 
4026 // Unsigned Integer Immediate: the values 0-31
4027 operand uimmI5() %{
4028   predicate(Assembler::is_uimm(n->get_int(), 5));
4029   match(ConI);
4030   op_cost(0);
4031   format %{ %}
4032   interface(CONST_INTER);
4033 %}
4034 
4035 // Unsigned Integer Immediate: 6-bit
4036 operand uimmI6() %{
4037   predicate(Assembler::is_uimm(n->get_int(), 6));
4038   match(ConI);
4039   op_cost(0);
4040   format %{ %}
4041   interface(CONST_INTER);
4042 %}
4043 
4044 // Unsigned Integer Immediate:  6-bit int, greater than 32
4045 operand uimmI6_ge32() %{
4046   predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
4047   match(ConI);
4048   op_cost(0);
4049   format %{ %}
4050   interface(CONST_INTER);
4051 %}
4052 
4053 // Unsigned Integer Immediate: 15-bit
4054 operand uimmI15() %{
4055   predicate(Assembler::is_uimm(n->get_int(), 15));
4056   match(ConI);
4057   op_cost(0);
4058   format %{ %}
4059   interface(CONST_INTER);
4060 %}
4061 
4062 // Unsigned Integer Immediate: 16-bit
4063 operand uimmI16() %{
4064   predicate(Assembler::is_uimm(n->get_int(), 16));
4065   match(ConI);
4066   op_cost(0);
4067   format %{ %}
4068   interface(CONST_INTER);
4069 %}
4070 
4071 // constant 'int 0'.
4072 operand immI_0() %{
4073   predicate(n->get_int() == 0);
4074   match(ConI);
4075   op_cost(0);
4076   format %{ %}
4077   interface(CONST_INTER);
4078 %}
4079 
4080 // constant 'int 1'.
4081 operand immI_1() %{
4082   predicate(n->get_int() == 1);
4083   match(ConI);
4084   op_cost(0);
4085   format %{ %}
4086   interface(CONST_INTER);
4087 %}
4088 
4089 // constant 'int -1'.
4090 operand immI_minus1() %{
4091   predicate(n->get_int() == -1);
4092   match(ConI);
4093   op_cost(0);
4094   format %{ %}
4095   interface(CONST_INTER);
4096 %}
4097 
4098 // int value 16.
4099 operand immI_16() %{
4100   predicate(n->get_int() == 16);
4101   match(ConI);
4102   op_cost(0);
4103   format %{ %}
4104   interface(CONST_INTER);
4105 %}
4106 
4107 // int value 24.
4108 operand immI_24() %{
4109   predicate(n->get_int() == 24);
4110   match(ConI);
4111   op_cost(0);
4112   format %{ %}
4113   interface(CONST_INTER);
4114 %}
4115 
4116 // Compressed oops constants
4117 // Pointer Immediate
4118 operand immN() %{
4119   match(ConN);
4120 
4121   op_cost(10);
4122   format %{ %}
4123   interface(CONST_INTER);
4124 %}
4125 
4126 // NULL Pointer Immediate
4127 operand immN_0() %{
4128   predicate(n->get_narrowcon() == 0);
4129   match(ConN);
4130 
4131   op_cost(0);
4132   format %{ %}
4133   interface(CONST_INTER);
4134 %}
4135 
4136 // Compressed klass constants
4137 operand immNKlass() %{
4138   match(ConNKlass);
4139 
4140   op_cost(0);
4141   format %{ %}
4142   interface(CONST_INTER);
4143 %}
4144 
4145 // This operand can be used to avoid matching of an instruct
4146 // with chain rule.
4147 operand immNKlass_NM() %{
4148   match(ConNKlass);
4149   predicate(false);
4150   op_cost(0);
4151   format %{ %}
4152   interface(CONST_INTER);
4153 %}
4154 
4155 // Pointer Immediate: 64-bit
4156 operand immP() %{
4157   match(ConP);
4158   op_cost(0);
4159   format %{ %}
4160   interface(CONST_INTER);
4161 %}
4162 
4163 // Operand to avoid match of loadConP.
4164 // This operand can be used to avoid matching of an instruct
4165 // with chain rule.
4166 operand immP_NM() %{
4167   match(ConP);
4168   predicate(false);
4169   op_cost(0);
4170   format %{ %}
4171   interface(CONST_INTER);
4172 %}
4173 
4174 // costant 'pointer 0'.
4175 operand immP_0() %{
4176   predicate(n->get_ptr() == 0);
4177   match(ConP);
4178   op_cost(0);
4179   format %{ %}
4180   interface(CONST_INTER);
4181 %}
4182 
4183 // pointer 0x0 or 0x1
4184 operand immP_0or1() %{
4185   predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4186   match(ConP);
4187   op_cost(0);
4188   format %{ %}
4189   interface(CONST_INTER);
4190 %}
4191 
4192 operand immL() %{
4193   match(ConL);
4194   op_cost(40);
4195   format %{ %}
4196   interface(CONST_INTER);
4197 %}
4198 
4199 // Long Immediate: 16-bit
4200 operand immL16() %{
4201   predicate(Assembler::is_simm(n->get_long(), 16));
4202   match(ConL);
4203   op_cost(0);
4204   format %{ %}
4205   interface(CONST_INTER);
4206 %}
4207 
4208 // Long Immediate: 16-bit, 4-aligned
4209 operand immL16Alg4() %{
4210   predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4211   match(ConL);
4212   op_cost(0);
4213   format %{ %}
4214   interface(CONST_INTER);
4215 %}
4216 
4217 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4218 operand immL32hi16() %{
4219   predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4220   match(ConL);
4221   op_cost(0);
4222   format %{ %}
4223   interface(CONST_INTER);
4224 %}
4225 
4226 // Long Immediate: 32-bit
4227 operand immL32() %{
4228   predicate(Assembler::is_simm(n->get_long(), 32));
4229   match(ConL);
4230   op_cost(0);
4231   format %{ %}
4232   interface(CONST_INTER);
4233 %}
4234 
4235 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4236 operand immLhighest16() %{
4237   predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4238   match(ConL);
4239   op_cost(0);
4240   format %{ %}
4241   interface(CONST_INTER);
4242 %}
4243 
4244 operand immLnegpow2() %{
4245   predicate(is_power_of_2_long((jlong)-(n->get_long())));
4246   match(ConL);
4247   op_cost(0);
4248   format %{ %}
4249   interface(CONST_INTER);
4250 %}
4251 
4252 operand immLpow2minus1() %{
4253   predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4254             (n->get_long() != (jlong)0xffffffffffffffffL));
4255   match(ConL);
4256   op_cost(0);
4257   format %{ %}
4258   interface(CONST_INTER);
4259 %}
4260 
4261 // constant 'long 0'.
4262 operand immL_0() %{
4263   predicate(n->get_long() == 0L);
4264   match(ConL);
4265   op_cost(0);
4266   format %{ %}
4267   interface(CONST_INTER);
4268 %}
4269 
4270 // constat ' long -1'.
4271 operand immL_minus1() %{
4272   predicate(n->get_long() == -1L);
4273   match(ConL);
4274   op_cost(0);
4275   format %{ %}
4276   interface(CONST_INTER);
4277 %}
4278 
4279 // Long Immediate: low 32-bit mask
4280 operand immL_32bits() %{
4281   predicate(n->get_long() == 0xFFFFFFFFL);
4282   match(ConL);
4283   op_cost(0);
4284   format %{ %}
4285   interface(CONST_INTER);
4286 %}
4287 
4288 // Unsigned Long Immediate: 16-bit
4289 operand uimmL16() %{
4290   predicate(Assembler::is_uimm(n->get_long(), 16));
4291   match(ConL);
4292   op_cost(0);
4293   format %{ %}
4294   interface(CONST_INTER);
4295 %}
4296 
4297 // Float Immediate
4298 operand immF() %{
4299   match(ConF);
4300   op_cost(40);
4301   format %{ %}
4302   interface(CONST_INTER);
4303 %}
4304 
4305 // Float Immediate: +0.0f.
4306 operand immF_0() %{
4307   predicate(jint_cast(n->getf()) == 0);
4308   match(ConF);
4309 
4310   op_cost(0);
4311   format %{ %}
4312   interface(CONST_INTER);
4313 %}
4314 
4315 // Double Immediate
4316 operand immD() %{
4317   match(ConD);
4318   op_cost(40);
4319   format %{ %}
4320   interface(CONST_INTER);
4321 %}
4322 
4323 // Integer Register Operands
4324 // Integer Destination Register
4325 // See definition of reg_class bits32_reg_rw.
4326 operand iRegIdst() %{
4327   constraint(ALLOC_IN_RC(bits32_reg_rw));
4328   match(RegI);
4329   match(rscratch1RegI);
4330   match(rscratch2RegI);
4331   match(rarg1RegI);
4332   match(rarg2RegI);
4333   match(rarg3RegI);
4334   match(rarg4RegI);
4335   format %{ %}
4336   interface(REG_INTER);
4337 %}
4338 
4339 // Integer Source Register
4340 // See definition of reg_class bits32_reg_ro.
4341 operand iRegIsrc() %{
4342   constraint(ALLOC_IN_RC(bits32_reg_ro));
4343   match(RegI);
4344   match(rscratch1RegI);
4345   match(rscratch2RegI);
4346   match(rarg1RegI);
4347   match(rarg2RegI);
4348   match(rarg3RegI);
4349   match(rarg4RegI);
4350   format %{ %}
4351   interface(REG_INTER);
4352 %}
4353 
4354 operand rscratch1RegI() %{
4355   constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4356   match(iRegIdst);
4357   format %{ %}
4358   interface(REG_INTER);
4359 %}
4360 
4361 operand rscratch2RegI() %{
4362   constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4363   match(iRegIdst);
4364   format %{ %}
4365   interface(REG_INTER);
4366 %}
4367 
4368 operand rarg1RegI() %{
4369   constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4370   match(iRegIdst);
4371   format %{ %}
4372   interface(REG_INTER);
4373 %}
4374 
4375 operand rarg2RegI() %{
4376   constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4377   match(iRegIdst);
4378   format %{ %}
4379   interface(REG_INTER);
4380 %}
4381 
4382 operand rarg3RegI() %{
4383   constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4384   match(iRegIdst);
4385   format %{ %}
4386   interface(REG_INTER);
4387 %}
4388 
4389 operand rarg4RegI() %{
4390   constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4391   match(iRegIdst);
4392   format %{ %}
4393   interface(REG_INTER);
4394 %}
4395 
4396 operand rarg1RegL() %{
4397   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4398   match(iRegLdst);
4399   format %{ %}
4400   interface(REG_INTER);
4401 %}
4402 
4403 operand rarg2RegL() %{
4404   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4405   match(iRegLdst);
4406   format %{ %}
4407   interface(REG_INTER);
4408 %}
4409 
4410 operand rarg3RegL() %{
4411   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4412   match(iRegLdst);
4413   format %{ %}
4414   interface(REG_INTER);
4415 %}
4416 
4417 operand rarg4RegL() %{
4418   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4419   match(iRegLdst);
4420   format %{ %}
4421   interface(REG_INTER);
4422 %}
4423 
4424 // Pointer Destination Register
4425 // See definition of reg_class bits64_reg_rw.
4426 operand iRegPdst() %{
4427   constraint(ALLOC_IN_RC(bits64_reg_rw));
4428   match(RegP);
4429   match(rscratch1RegP);
4430   match(rscratch2RegP);
4431   match(rarg1RegP);
4432   match(rarg2RegP);
4433   match(rarg3RegP);
4434   match(rarg4RegP);
4435   format %{ %}
4436   interface(REG_INTER);
4437 %}
4438 
4439 // Pointer Destination Register
4440 // Operand not using r11 and r12 (killed in epilog).
4441 operand iRegPdstNoScratch() %{
4442   constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4443   match(RegP);
4444   match(rarg1RegP);
4445   match(rarg2RegP);
4446   match(rarg3RegP);
4447   match(rarg4RegP);
4448   format %{ %}
4449   interface(REG_INTER);
4450 %}
4451 
4452 // Pointer Source Register
4453 // See definition of reg_class bits64_reg_ro.
4454 operand iRegPsrc() %{
4455   constraint(ALLOC_IN_RC(bits64_reg_ro));
4456   match(RegP);
4457   match(iRegPdst);
4458   match(rscratch1RegP);
4459   match(rscratch2RegP);
4460   match(rarg1RegP);
4461   match(rarg2RegP);
4462   match(rarg3RegP);
4463   match(rarg4RegP);
4464   match(threadRegP);
4465   format %{ %}
4466   interface(REG_INTER);
4467 %}
4468 
4469 // Thread operand.
4470 operand threadRegP() %{
4471   constraint(ALLOC_IN_RC(thread_bits64_reg));
4472   match(iRegPdst);
4473   format %{ "R16" %}
4474   interface(REG_INTER);
4475 %}
4476 
4477 operand rscratch1RegP() %{
4478   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4479   match(iRegPdst);
4480   format %{ "R11" %}
4481   interface(REG_INTER);
4482 %}
4483 
4484 operand rscratch2RegP() %{
4485   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4486   match(iRegPdst);
4487   format %{ %}
4488   interface(REG_INTER);
4489 %}
4490 
4491 operand rarg1RegP() %{
4492   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4493   match(iRegPdst);
4494   format %{ %}
4495   interface(REG_INTER);
4496 %}
4497 
4498 operand rarg2RegP() %{
4499   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4500   match(iRegPdst);
4501   format %{ %}
4502   interface(REG_INTER);
4503 %}
4504 
4505 operand rarg3RegP() %{
4506   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4507   match(iRegPdst);
4508   format %{ %}
4509   interface(REG_INTER);
4510 %}
4511 
4512 operand rarg4RegP() %{
4513   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4514   match(iRegPdst);
4515   format %{ %}
4516   interface(REG_INTER);
4517 %}
4518 
4519 operand iRegNsrc() %{
4520   constraint(ALLOC_IN_RC(bits32_reg_ro));
4521   match(RegN);
4522   match(iRegNdst);
4523 
4524   format %{ %}
4525   interface(REG_INTER);
4526 %}
4527 
4528 operand iRegNdst() %{
4529   constraint(ALLOC_IN_RC(bits32_reg_rw));
4530   match(RegN);
4531 
4532   format %{ %}
4533   interface(REG_INTER);
4534 %}
4535 
4536 // Long Destination Register
4537 // See definition of reg_class bits64_reg_rw.
4538 operand iRegLdst() %{
4539   constraint(ALLOC_IN_RC(bits64_reg_rw));
4540   match(RegL);
4541   match(rscratch1RegL);
4542   match(rscratch2RegL);
4543   format %{ %}
4544   interface(REG_INTER);
4545 %}
4546 
4547 // Long Source Register
4548 // See definition of reg_class bits64_reg_ro.
4549 operand iRegLsrc() %{
4550   constraint(ALLOC_IN_RC(bits64_reg_ro));
4551   match(RegL);
4552   match(iRegLdst);
4553   match(rscratch1RegL);
4554   match(rscratch2RegL);
4555   format %{ %}
4556   interface(REG_INTER);
4557 %}
4558 
4559 // Special operand for ConvL2I.
4560 operand iRegL2Isrc(iRegLsrc reg) %{
4561   constraint(ALLOC_IN_RC(bits64_reg_ro));
4562   match(ConvL2I reg);
4563   format %{ "ConvL2I($reg)" %}
4564   interface(REG_INTER)
4565 %}
4566 
4567 operand rscratch1RegL() %{
4568   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4569   match(RegL);
4570   format %{ %}
4571   interface(REG_INTER);
4572 %}
4573 
4574 operand rscratch2RegL() %{
4575   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4576   match(RegL);
4577   format %{ %}
4578   interface(REG_INTER);
4579 %}
4580 
4581 // Condition Code Flag Registers
4582 operand flagsReg() %{
4583   constraint(ALLOC_IN_RC(int_flags));
4584   match(RegFlags);
4585   format %{ %}
4586   interface(REG_INTER);
4587 %}
4588 
4589 operand flagsRegSrc() %{
4590   constraint(ALLOC_IN_RC(int_flags_ro));
4591   match(RegFlags);
4592   match(flagsReg);
4593   match(flagsRegCR0);
4594   format %{ %}
4595   interface(REG_INTER);
4596 %}
4597 
4598 // Condition Code Flag Register CR0
4599 operand flagsRegCR0() %{
4600   constraint(ALLOC_IN_RC(int_flags_CR0));
4601   match(RegFlags);
4602   format %{ "CR0" %}
4603   interface(REG_INTER);
4604 %}
4605 
4606 operand flagsRegCR1() %{
4607   constraint(ALLOC_IN_RC(int_flags_CR1));
4608   match(RegFlags);
4609   format %{ "CR1" %}
4610   interface(REG_INTER);
4611 %}
4612 
4613 operand flagsRegCR6() %{
4614   constraint(ALLOC_IN_RC(int_flags_CR6));
4615   match(RegFlags);
4616   format %{ "CR6" %}
4617   interface(REG_INTER);
4618 %}
4619 
4620 operand regCTR() %{
4621   constraint(ALLOC_IN_RC(ctr_reg));
4622   // RegFlags should work. Introducing a RegSpecial type would cause a
4623   // lot of changes.
4624   match(RegFlags);
4625   format %{"SR_CTR" %}
4626   interface(REG_INTER);
4627 %}
4628 
4629 operand regD() %{
4630   constraint(ALLOC_IN_RC(dbl_reg));
4631   match(RegD);
4632   format %{ %}
4633   interface(REG_INTER);
4634 %}
4635 
4636 operand regF() %{
4637   constraint(ALLOC_IN_RC(flt_reg));
4638   match(RegF);
4639   format %{ %}
4640   interface(REG_INTER);
4641 %}
4642 
4643 // Special Registers
4644 
4645 // Method Register
4646 operand inline_cache_regP(iRegPdst reg) %{
4647   constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4648   match(reg);
4649   format %{ %}
4650   interface(REG_INTER);
4651 %}
4652 
4653 operand compiler_method_oop_regP(iRegPdst reg) %{
4654   constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4655   match(reg);
4656   format %{ %}
4657   interface(REG_INTER);
4658 %}
4659 
4660 operand interpreter_method_oop_regP(iRegPdst reg) %{
4661   constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4662   match(reg);
4663   format %{ %}
4664   interface(REG_INTER);
4665 %}
4666 
4667 // Operands to remove register moves in unscaled mode.
4668 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4669 operand iRegP2N(iRegPsrc reg) %{
4670   predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4671   constraint(ALLOC_IN_RC(bits64_reg_ro));
4672   match(EncodeP reg);
4673   format %{ "$reg" %}
4674   interface(REG_INTER)
4675 %}
4676 
4677 operand iRegN2P(iRegNsrc reg) %{
4678   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4679   constraint(ALLOC_IN_RC(bits32_reg_ro));
4680   match(DecodeN reg);
4681   format %{ "$reg" %}
4682   interface(REG_INTER)
4683 %}
4684 
4685 operand iRegN2P_klass(iRegNsrc reg) %{
4686   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4687   constraint(ALLOC_IN_RC(bits32_reg_ro));
4688   match(DecodeNKlass reg);
4689   format %{ "$reg" %}
4690   interface(REG_INTER)
4691 %}
4692 
4693 //----------Complex Operands---------------------------------------------------
4694 // Indirect Memory Reference
4695 operand indirect(iRegPsrc reg) %{
4696   constraint(ALLOC_IN_RC(bits64_reg_ro));
4697   match(reg);
4698   op_cost(100);
4699   format %{ "[$reg]" %}
4700   interface(MEMORY_INTER) %{
4701     base($reg);
4702     index(0x0);
4703     scale(0x0);
4704     disp(0x0);
4705   %}
4706 %}
4707 
4708 // Indirect with Offset
4709 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4710   constraint(ALLOC_IN_RC(bits64_reg_ro));
4711   match(AddP reg offset);
4712   op_cost(100);
4713   format %{ "[$reg + $offset]" %}
4714   interface(MEMORY_INTER) %{
4715     base($reg);
4716     index(0x0);
4717     scale(0x0);
4718     disp($offset);
4719   %}
4720 %}
4721 
4722 // Indirect with 4-aligned Offset
4723 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4724   constraint(ALLOC_IN_RC(bits64_reg_ro));
4725   match(AddP reg offset);
4726   op_cost(100);
4727   format %{ "[$reg + $offset]" %}
4728   interface(MEMORY_INTER) %{
4729     base($reg);
4730     index(0x0);
4731     scale(0x0);
4732     disp($offset);
4733   %}
4734 %}
4735 
4736 //----------Complex Operands for Compressed OOPs-------------------------------
4737 // Compressed OOPs with narrow_oop_shift == 0.
4738 
4739 // Indirect Memory Reference, compressed OOP
4740 operand indirectNarrow(iRegNsrc reg) %{
4741   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4742   constraint(ALLOC_IN_RC(bits64_reg_ro));
4743   match(DecodeN reg);
4744   op_cost(100);
4745   format %{ "[$reg]" %}
4746   interface(MEMORY_INTER) %{
4747     base($reg);
4748     index(0x0);
4749     scale(0x0);
4750     disp(0x0);
4751   %}
4752 %}
4753 
4754 operand indirectNarrow_klass(iRegNsrc reg) %{
4755   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4756   constraint(ALLOC_IN_RC(bits64_reg_ro));
4757   match(DecodeNKlass reg);
4758   op_cost(100);
4759   format %{ "[$reg]" %}
4760   interface(MEMORY_INTER) %{
4761     base($reg);
4762     index(0x0);
4763     scale(0x0);
4764     disp(0x0);
4765   %}
4766 %}
4767 
4768 // Indirect with Offset, compressed OOP
4769 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4770   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4771   constraint(ALLOC_IN_RC(bits64_reg_ro));
4772   match(AddP (DecodeN reg) offset);
4773   op_cost(100);
4774   format %{ "[$reg + $offset]" %}
4775   interface(MEMORY_INTER) %{
4776     base($reg);
4777     index(0x0);
4778     scale(0x0);
4779     disp($offset);
4780   %}
4781 %}
4782 
4783 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4784   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4785   constraint(ALLOC_IN_RC(bits64_reg_ro));
4786   match(AddP (DecodeNKlass reg) offset);
4787   op_cost(100);
4788   format %{ "[$reg + $offset]" %}
4789   interface(MEMORY_INTER) %{
4790     base($reg);
4791     index(0x0);
4792     scale(0x0);
4793     disp($offset);
4794   %}
4795 %}
4796 
4797 // Indirect with 4-aligned Offset, compressed OOP
4798 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4799   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4800   constraint(ALLOC_IN_RC(bits64_reg_ro));
4801   match(AddP (DecodeN reg) offset);
4802   op_cost(100);
4803   format %{ "[$reg + $offset]" %}
4804   interface(MEMORY_INTER) %{
4805     base($reg);
4806     index(0x0);
4807     scale(0x0);
4808     disp($offset);
4809   %}
4810 %}
4811 
4812 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4813   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4814   constraint(ALLOC_IN_RC(bits64_reg_ro));
4815   match(AddP (DecodeNKlass reg) offset);
4816   op_cost(100);
4817   format %{ "[$reg + $offset]" %}
4818   interface(MEMORY_INTER) %{
4819     base($reg);
4820     index(0x0);
4821     scale(0x0);
4822     disp($offset);
4823   %}
4824 %}
4825 
4826 //----------Special Memory Operands--------------------------------------------
4827 // Stack Slot Operand
4828 //
4829 // This operand is used for loading and storing temporary values on
4830 // the stack where a match requires a value to flow through memory.
4831 operand stackSlotI(sRegI reg) %{
4832   constraint(ALLOC_IN_RC(stack_slots));
4833   op_cost(100);
4834   //match(RegI);
4835   format %{ "[sp+$reg]" %}
4836   interface(MEMORY_INTER) %{
4837     base(0x1);   // R1_SP
4838     index(0x0);
4839     scale(0x0);
4840     disp($reg);  // Stack Offset
4841   %}
4842 %}
4843 
4844 operand stackSlotL(sRegL reg) %{
4845   constraint(ALLOC_IN_RC(stack_slots));
4846   op_cost(100);
4847   //match(RegL);
4848   format %{ "[sp+$reg]" %}
4849   interface(MEMORY_INTER) %{
4850     base(0x1);   // R1_SP
4851     index(0x0);
4852     scale(0x0);
4853     disp($reg);  // Stack Offset
4854   %}
4855 %}
4856 
4857 operand stackSlotP(sRegP reg) %{
4858   constraint(ALLOC_IN_RC(stack_slots));
4859   op_cost(100);
4860   //match(RegP);
4861   format %{ "[sp+$reg]" %}
4862   interface(MEMORY_INTER) %{
4863     base(0x1);   // R1_SP
4864     index(0x0);
4865     scale(0x0);
4866     disp($reg);  // Stack Offset
4867   %}
4868 %}
4869 
4870 operand stackSlotF(sRegF reg) %{
4871   constraint(ALLOC_IN_RC(stack_slots));
4872   op_cost(100);
4873   //match(RegF);
4874   format %{ "[sp+$reg]" %}
4875   interface(MEMORY_INTER) %{
4876     base(0x1);   // R1_SP
4877     index(0x0);
4878     scale(0x0);
4879     disp($reg);  // Stack Offset
4880   %}
4881 %}
4882 
4883 operand stackSlotD(sRegD reg) %{
4884   constraint(ALLOC_IN_RC(stack_slots));
4885   op_cost(100);
4886   //match(RegD);
4887   format %{ "[sp+$reg]" %}
4888   interface(MEMORY_INTER) %{
4889     base(0x1);   // R1_SP
4890     index(0x0);
4891     scale(0x0);
4892     disp($reg);  // Stack Offset
4893   %}
4894 %}
4895 
4896 // Operands for expressing Control Flow
4897 // NOTE: Label is a predefined operand which should not be redefined in
4898 //       the AD file. It is generically handled within the ADLC.
4899 
4900 //----------Conditional Branch Operands----------------------------------------
4901 // Comparison Op
4902 //
4903 // This is the operation of the comparison, and is limited to the
4904 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4905 // (!=).
4906 //
4907 // Other attributes of the comparison, such as unsignedness, are specified
4908 // by the comparison instruction that sets a condition code flags register.
4909 // That result is represented by a flags operand whose subtype is appropriate
4910 // to the unsignedness (etc.) of the comparison.
4911 //
4912 // Later, the instruction which matches both the Comparison Op (a Bool) and
4913 // the flags (produced by the Cmp) specifies the coding of the comparison op
4914 // by matching a specific subtype of Bool operand below.
4915 
4916 // When used for floating point comparisons: unordered same as less.
4917 operand cmpOp() %{
4918   match(Bool);
4919   format %{ "" %}
4920   interface(COND_INTER) %{
4921                            // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4922                            //           BO          &  BI
4923     equal(0xA);            // 10 10:   bcondCRbiIs1 & Condition::equal
4924     not_equal(0x2);        // 00 10:   bcondCRbiIs0 & Condition::equal
4925     less(0x8);             // 10 00:   bcondCRbiIs1 & Condition::less
4926     greater_equal(0x0);    // 00 00:   bcondCRbiIs0 & Condition::less
4927     less_equal(0x1);       // 00 01:   bcondCRbiIs0 & Condition::greater
4928     greater(0x9);          // 10 01:   bcondCRbiIs1 & Condition::greater
4929     overflow(0xB);         // 10 11:   bcondCRbiIs1 & Condition::summary_overflow
4930     no_overflow(0x3);      // 00 11:   bcondCRbiIs0 & Condition::summary_overflow
4931   %}
4932 %}
4933 
4934 //----------OPERAND CLASSES----------------------------------------------------
4935 // Operand Classes are groups of operands that are used to simplify
4936 // instruction definitions by not requiring the AD writer to specify
4937 // seperate instructions for every form of operand when the
4938 // instruction accepts multiple operand types with the same basic
4939 // encoding and format. The classic case of this is memory operands.
4940 // Indirect is not included since its use is limited to Compare & Swap.
4941 
4942 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4943 // Memory operand where offsets are 4-aligned. Required for ld, std.
4944 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4945 opclass indirectMemory(indirect, indirectNarrow);
4946 
4947 // Special opclass for I and ConvL2I.
4948 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4949 
4950 // Operand classes to match encode and decode. iRegN_P2N is only used
4951 // for storeN. I have never seen an encode node elsewhere.
4952 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4953 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4954 
4955 //----------PIPELINE-----------------------------------------------------------
4956 
4957 pipeline %{
4958 
4959 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4960 // J. Res. & Dev., No. 1, Jan. 2002.
4961 
4962 //----------ATTRIBUTES---------------------------------------------------------
4963 attributes %{
4964 
4965   // Power4 instructions are of fixed length.
4966   fixed_size_instructions;
4967 
4968   // TODO: if `bundle' means number of instructions fetched
4969   // per cycle, this is 8. If `bundle' means Power4 `group', that is
4970   // max instructions issued per cycle, this is 5.
4971   max_instructions_per_bundle = 8;
4972 
4973   // A Power4 instruction is 4 bytes long.
4974   instruction_unit_size = 4;
4975 
4976   // The Power4 processor fetches 64 bytes...
4977   instruction_fetch_unit_size = 64;
4978 
4979   // ...in one line
4980   instruction_fetch_units = 1
4981 
4982   // Unused, list one so that array generated by adlc is not empty.
4983   // Aix compiler chokes if _nop_count = 0.
4984   nops(fxNop);
4985 %}
4986 
4987 //----------RESOURCES----------------------------------------------------------
4988 // Resources are the functional units available to the machine
4989 resources(
4990    PPC_BR,         // branch unit
4991    PPC_CR,         // condition unit
4992    PPC_FX1,        // integer arithmetic unit 1
4993    PPC_FX2,        // integer arithmetic unit 2
4994    PPC_LDST1,      // load/store unit 1
4995    PPC_LDST2,      // load/store unit 2
4996    PPC_FP1,        // float arithmetic unit 1
4997    PPC_FP2,        // float arithmetic unit 2
4998    PPC_LDST = PPC_LDST1 | PPC_LDST2,
4999    PPC_FX = PPC_FX1 | PPC_FX2,
5000    PPC_FP = PPC_FP1 | PPC_FP2
5001  );
5002 
5003 //----------PIPELINE DESCRIPTION-----------------------------------------------
5004 // Pipeline Description specifies the stages in the machine's pipeline
5005 pipe_desc(
5006    // Power4 longest pipeline path
5007    PPC_IF,   // instruction fetch
5008    PPC_IC,
5009    //PPC_BP, // branch prediction
5010    PPC_D0,   // decode
5011    PPC_D1,   // decode
5012    PPC_D2,   // decode
5013    PPC_D3,   // decode
5014    PPC_Xfer1,
5015    PPC_GD,   // group definition
5016    PPC_MP,   // map
5017    PPC_ISS,  // issue
5018    PPC_RF,   // resource fetch
5019    PPC_EX1,  // execute (all units)
5020    PPC_EX2,  // execute (FP, LDST)
5021    PPC_EX3,  // execute (FP, LDST)
5022    PPC_EX4,  // execute (FP)
5023    PPC_EX5,  // execute (FP)
5024    PPC_EX6,  // execute (FP)
5025    PPC_WB,   // write back
5026    PPC_Xfer2,
5027    PPC_CP
5028  );
5029 
5030 //----------PIPELINE CLASSES---------------------------------------------------
5031 // Pipeline Classes describe the stages in which input and output are
5032 // referenced by the hardware pipeline.
5033 
5034 // Simple pipeline classes.
5035 
5036 // Default pipeline class.
5037 pipe_class pipe_class_default() %{
5038   single_instruction;
5039   fixed_latency(2);
5040 %}
5041 
5042 // Pipeline class for empty instructions.
5043 pipe_class pipe_class_empty() %{
5044   single_instruction;
5045   fixed_latency(0);
5046 %}
5047 
5048 // Pipeline class for compares.
5049 pipe_class pipe_class_compare() %{
5050   single_instruction;
5051   fixed_latency(16);
5052 %}
5053 
5054 // Pipeline class for traps.
5055 pipe_class pipe_class_trap() %{
5056   single_instruction;
5057   fixed_latency(100);
5058 %}
5059 
5060 // Pipeline class for memory operations.
5061 pipe_class pipe_class_memory() %{
5062   single_instruction;
5063   fixed_latency(16);
5064 %}
5065 
5066 // Pipeline class for call.
5067 pipe_class pipe_class_call() %{
5068   single_instruction;
5069   fixed_latency(100);
5070 %}
5071 
5072 // Define the class for the Nop node.
5073 define %{
5074    MachNop = pipe_class_default;
5075 %}
5076 
5077 %}
5078 
5079 //----------INSTRUCTIONS-------------------------------------------------------
5080 
5081 // Naming of instructions:
5082 //   opA_operB / opA_operB_operC:
5083 //     Operation 'op' with one or two source operands 'oper'. Result
5084 //     type is A, source operand types are B and C.
5085 //     Iff A == B == C, B and C are left out.
5086 //
5087 // The instructions are ordered according to the following scheme:
5088 //  - loads
5089 //  - load constants
5090 //  - prefetch
5091 //  - store
5092 //  - encode/decode
5093 //  - membar
5094 //  - conditional moves
5095 //  - compare & swap
5096 //  - arithmetic and logic operations
5097 //    * int: Add, Sub, Mul, Div, Mod
5098 //    * int: lShift, arShift, urShift, rot
5099 //    * float: Add, Sub, Mul, Div
5100 //    * and, or, xor ...
5101 //  - register moves: float <-> int, reg <-> stack, repl
5102 //  - cast (high level type cast, XtoP, castPP, castII, not_null etc.
5103 //  - conv (low level type cast requiring bit changes (sign extend etc)
5104 //  - compares, range & zero checks.
5105 //  - branches
5106 //  - complex operations, intrinsics, min, max, replicate
5107 //  - lock
5108 //  - Calls
5109 //
5110 // If there are similar instructions with different types they are sorted:
5111 // int before float
5112 // small before big
5113 // signed before unsigned
5114 // e.g., loadS before loadUS before loadI before loadF.
5115 
5116 
5117 //----------Load/Store Instructions--------------------------------------------
5118 
5119 //----------Load Instructions--------------------------------------------------
5120 
5121 // Converts byte to int.
5122 // As convB2I_reg, but without match rule.  The match rule of convB2I_reg
5123 // reuses the 'amount' operand, but adlc expects that operand specification
5124 // and operands in match rule are equivalent.
5125 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5126   effect(DEF dst, USE src);
5127   format %{ "EXTSB   $dst, $src \t// byte->int" %}
5128   size(4);
5129   ins_encode %{
5130     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5131     __ extsb($dst$$Register, $src$$Register);
5132   %}
5133   ins_pipe(pipe_class_default);
5134 %}
5135 
5136 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5137   // match-rule, false predicate
5138   match(Set dst (LoadB mem));
5139   predicate(false);
5140 
5141   format %{ "LBZ     $dst, $mem" %}
5142   size(4);
5143   ins_encode( enc_lbz(dst, mem) );
5144   ins_pipe(pipe_class_memory);
5145 %}
5146 
5147 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5148   // match-rule, false predicate
5149   match(Set dst (LoadB mem));
5150   predicate(false);
5151 
5152   format %{ "LBZ     $dst, $mem\n\t"
5153             "TWI     $dst\n\t"
5154             "ISYNC" %}
5155   size(12);
5156   ins_encode( enc_lbz_ac(dst, mem) );
5157   ins_pipe(pipe_class_memory);
5158 %}
5159 
5160 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5161 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5162   match(Set dst (LoadB mem));
5163   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5164   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5165   expand %{
5166     iRegIdst tmp;
5167     loadUB_indirect(tmp, mem);
5168     convB2I_reg_2(dst, tmp);
5169   %}
5170 %}
5171 
5172 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5173   match(Set dst (LoadB mem));
5174   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5175   expand %{
5176     iRegIdst tmp;
5177     loadUB_indirect_ac(tmp, mem);
5178     convB2I_reg_2(dst, tmp);
5179   %}
5180 %}
5181 
5182 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5183   // match-rule, false predicate
5184   match(Set dst (LoadB mem));
5185   predicate(false);
5186 
5187   format %{ "LBZ     $dst, $mem" %}
5188   size(4);
5189   ins_encode( enc_lbz(dst, mem) );
5190   ins_pipe(pipe_class_memory);
5191 %}
5192 
5193 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5194   // match-rule, false predicate
5195   match(Set dst (LoadB mem));
5196   predicate(false);
5197 
5198   format %{ "LBZ     $dst, $mem\n\t"
5199             "TWI     $dst\n\t"
5200             "ISYNC" %}
5201   size(12);
5202   ins_encode( enc_lbz_ac(dst, mem) );
5203   ins_pipe(pipe_class_memory);
5204 %}
5205 
5206 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5207 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5208   match(Set dst (LoadB mem));
5209   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5210   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5211 
5212   expand %{
5213     iRegIdst tmp;
5214     loadUB_indOffset16(tmp, mem);
5215     convB2I_reg_2(dst, tmp);
5216   %}
5217 %}
5218 
5219 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5220   match(Set dst (LoadB mem));
5221   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5222 
5223   expand %{
5224     iRegIdst tmp;
5225     loadUB_indOffset16_ac(tmp, mem);
5226     convB2I_reg_2(dst, tmp);
5227   %}
5228 %}
5229 
5230 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5231 instruct loadUB(iRegIdst dst, memory mem) %{
5232   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5233   match(Set dst (LoadUB mem));
5234   ins_cost(MEMORY_REF_COST);
5235 
5236   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int" %}
5237   size(4);
5238   ins_encode( enc_lbz(dst, mem) );
5239   ins_pipe(pipe_class_memory);
5240 %}
5241 
5242 // Load  Unsigned Byte (8bit UNsigned) acquire.
5243 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5244   match(Set dst (LoadUB mem));
5245   ins_cost(3*MEMORY_REF_COST);
5246 
5247   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5248             "TWI     $dst\n\t"
5249             "ISYNC" %}
5250   size(12);
5251   ins_encode( enc_lbz_ac(dst, mem) );
5252   ins_pipe(pipe_class_memory);
5253 %}
5254 
5255 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5256 instruct loadUB2L(iRegLdst dst, memory mem) %{
5257   match(Set dst (ConvI2L (LoadUB mem)));
5258   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5259   ins_cost(MEMORY_REF_COST);
5260 
5261   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long" %}
5262   size(4);
5263   ins_encode( enc_lbz(dst, mem) );
5264   ins_pipe(pipe_class_memory);
5265 %}
5266 
5267 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5268   match(Set dst (ConvI2L (LoadUB mem)));
5269   ins_cost(3*MEMORY_REF_COST);
5270 
5271   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5272             "TWI     $dst\n\t"
5273             "ISYNC" %}
5274   size(12);
5275   ins_encode( enc_lbz_ac(dst, mem) );
5276   ins_pipe(pipe_class_memory);
5277 %}
5278 
5279 // Load Short (16bit signed)
5280 instruct loadS(iRegIdst dst, memory mem) %{
5281   match(Set dst (LoadS mem));
5282   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5283   ins_cost(MEMORY_REF_COST);
5284 
5285   format %{ "LHA     $dst, $mem" %}
5286   size(4);
5287   ins_encode %{
5288     // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5289     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5290     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5291   %}
5292   ins_pipe(pipe_class_memory);
5293 %}
5294 
5295 // Load Short (16bit signed) acquire.
5296 instruct loadS_ac(iRegIdst dst, memory mem) %{
5297   match(Set dst (LoadS mem));
5298   ins_cost(3*MEMORY_REF_COST);
5299 
5300   format %{ "LHA     $dst, $mem\t acquire\n\t"
5301             "TWI     $dst\n\t"
5302             "ISYNC" %}
5303   size(12);
5304   ins_encode %{
5305     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5306     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5307     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5308     __ twi_0($dst$$Register);
5309     __ isync();
5310   %}
5311   ins_pipe(pipe_class_memory);
5312 %}
5313 
5314 // Load Char (16bit unsigned)
5315 instruct loadUS(iRegIdst dst, memory mem) %{
5316   match(Set dst (LoadUS mem));
5317   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5318   ins_cost(MEMORY_REF_COST);
5319 
5320   format %{ "LHZ     $dst, $mem" %}
5321   size(4);
5322   ins_encode( enc_lhz(dst, mem) );
5323   ins_pipe(pipe_class_memory);
5324 %}
5325 
5326 // Load Char (16bit unsigned) acquire.
5327 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5328   match(Set dst (LoadUS mem));
5329   ins_cost(3*MEMORY_REF_COST);
5330 
5331   format %{ "LHZ     $dst, $mem \t// acquire\n\t"
5332             "TWI     $dst\n\t"
5333             "ISYNC" %}
5334   size(12);
5335   ins_encode( enc_lhz_ac(dst, mem) );
5336   ins_pipe(pipe_class_memory);
5337 %}
5338 
5339 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5340 instruct loadUS2L(iRegLdst dst, memory mem) %{
5341   match(Set dst (ConvI2L (LoadUS mem)));
5342   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5343   ins_cost(MEMORY_REF_COST);
5344 
5345   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long" %}
5346   size(4);
5347   ins_encode( enc_lhz(dst, mem) );
5348   ins_pipe(pipe_class_memory);
5349 %}
5350 
5351 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5352 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5353   match(Set dst (ConvI2L (LoadUS mem)));
5354   ins_cost(3*MEMORY_REF_COST);
5355 
5356   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5357             "TWI     $dst\n\t"
5358             "ISYNC" %}
5359   size(12);
5360   ins_encode( enc_lhz_ac(dst, mem) );
5361   ins_pipe(pipe_class_memory);
5362 %}
5363 
5364 // Load Integer.
5365 instruct loadI(iRegIdst dst, memory mem) %{
5366   match(Set dst (LoadI mem));
5367   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5368   ins_cost(MEMORY_REF_COST);
5369 
5370   format %{ "LWZ     $dst, $mem" %}
5371   size(4);
5372   ins_encode( enc_lwz(dst, mem) );
5373   ins_pipe(pipe_class_memory);
5374 %}
5375 
5376 // Load Integer acquire.
5377 instruct loadI_ac(iRegIdst dst, memory mem) %{
5378   match(Set dst (LoadI mem));
5379   ins_cost(3*MEMORY_REF_COST);
5380 
5381   format %{ "LWZ     $dst, $mem \t// load acquire\n\t"
5382             "TWI     $dst\n\t"
5383             "ISYNC" %}
5384   size(12);
5385   ins_encode( enc_lwz_ac(dst, mem) );
5386   ins_pipe(pipe_class_memory);
5387 %}
5388 
5389 // Match loading integer and casting it to unsigned int in
5390 // long register.
5391 // LoadI + ConvI2L + AndL 0xffffffff.
5392 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5393   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5394   predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5395   ins_cost(MEMORY_REF_COST);
5396 
5397   format %{ "LWZ     $dst, $mem \t// zero-extend to long" %}
5398   size(4);
5399   ins_encode( enc_lwz(dst, mem) );
5400   ins_pipe(pipe_class_memory);
5401 %}
5402 
5403 // Match loading integer and casting it to long.
5404 instruct loadI2L(iRegLdst dst, memory mem) %{
5405   match(Set dst (ConvI2L (LoadI mem)));
5406   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5407   ins_cost(MEMORY_REF_COST);
5408 
5409   format %{ "LWA     $dst, $mem \t// loadI2L" %}
5410   size(4);
5411   ins_encode %{
5412     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5413     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5414     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5415   %}
5416   ins_pipe(pipe_class_memory);
5417 %}
5418 
5419 // Match loading integer and casting it to long - acquire.
5420 instruct loadI2L_ac(iRegLdst dst, memory mem) %{
5421   match(Set dst (ConvI2L (LoadI mem)));
5422   ins_cost(3*MEMORY_REF_COST);
5423 
5424   format %{ "LWA     $dst, $mem \t// loadI2L acquire"
5425             "TWI     $dst\n\t"
5426             "ISYNC" %}
5427   size(12);
5428   ins_encode %{
5429     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5430     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5431     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5432     __ twi_0($dst$$Register);
5433     __ isync();
5434   %}
5435   ins_pipe(pipe_class_memory);
5436 %}
5437 
5438 // Load Long - aligned
5439 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5440   match(Set dst (LoadL mem));
5441   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5442   ins_cost(MEMORY_REF_COST);
5443 
5444   format %{ "LD      $dst, $mem \t// long" %}
5445   size(4);
5446   ins_encode( enc_ld(dst, mem) );
5447   ins_pipe(pipe_class_memory);
5448 %}
5449 
5450 // Load Long - aligned acquire.
5451 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5452   match(Set dst (LoadL mem));
5453   ins_cost(3*MEMORY_REF_COST);
5454 
5455   format %{ "LD      $dst, $mem \t// long acquire\n\t"
5456             "TWI     $dst\n\t"
5457             "ISYNC" %}
5458   size(12);
5459   ins_encode( enc_ld_ac(dst, mem) );
5460   ins_pipe(pipe_class_memory);
5461 %}
5462 
5463 // Load Long - UNaligned
5464 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5465   match(Set dst (LoadL_unaligned mem));
5466   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5467   ins_cost(MEMORY_REF_COST);
5468 
5469   format %{ "LD      $dst, $mem \t// unaligned long" %}
5470   size(4);
5471   ins_encode( enc_ld(dst, mem) );
5472   ins_pipe(pipe_class_memory);
5473 %}
5474 
5475 // Load nodes for superwords
5476 
5477 // Load Aligned Packed Byte
5478 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5479   predicate(n->as_LoadVector()->memory_size() == 8);
5480   match(Set dst (LoadVector mem));
5481   ins_cost(MEMORY_REF_COST);
5482 
5483   format %{ "LD      $dst, $mem \t// load 8-byte Vector" %}
5484   size(4);
5485   ins_encode( enc_ld(dst, mem) );
5486   ins_pipe(pipe_class_memory);
5487 %}
5488 
5489 // Load Range, range = array length (=jint)
5490 instruct loadRange(iRegIdst dst, memory mem) %{
5491   match(Set dst (LoadRange mem));
5492   ins_cost(MEMORY_REF_COST);
5493 
5494   format %{ "LWZ     $dst, $mem \t// range" %}
5495   size(4);
5496   ins_encode( enc_lwz(dst, mem) );
5497   ins_pipe(pipe_class_memory);
5498 %}
5499 
5500 // Load Compressed Pointer
5501 instruct loadN(iRegNdst dst, memory mem) %{
5502   match(Set dst (LoadN mem));
5503   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5504   ins_cost(MEMORY_REF_COST);
5505 
5506   format %{ "LWZ     $dst, $mem \t// load compressed ptr" %}
5507   size(4);
5508   ins_encode( enc_lwz(dst, mem) );
5509   ins_pipe(pipe_class_memory);
5510 %}
5511 
5512 // Load Compressed Pointer acquire.
5513 instruct loadN_ac(iRegNdst dst, memory mem) %{
5514   match(Set dst (LoadN mem));
5515   ins_cost(3*MEMORY_REF_COST);
5516 
5517   format %{ "LWZ     $dst, $mem \t// load acquire compressed ptr\n\t"
5518             "TWI     $dst\n\t"
5519             "ISYNC" %}
5520   size(12);
5521   ins_encode( enc_lwz_ac(dst, mem) );
5522   ins_pipe(pipe_class_memory);
5523 %}
5524 
5525 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5526 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5527   match(Set dst (DecodeN (LoadN mem)));
5528   predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5529   ins_cost(MEMORY_REF_COST);
5530 
5531   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5532   size(4);
5533   ins_encode( enc_lwz(dst, mem) );
5534   ins_pipe(pipe_class_memory);
5535 %}
5536 
5537 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5538   match(Set dst (DecodeNKlass (LoadNKlass mem)));
5539   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5540             _kids[0]->_leaf->as_Load()->is_unordered());
5541   ins_cost(MEMORY_REF_COST);
5542 
5543   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5544   size(4);
5545   ins_encode( enc_lwz(dst, mem) );
5546   ins_pipe(pipe_class_memory);
5547 %}
5548 
5549 // Load Pointer
5550 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5551   match(Set dst (LoadP mem));
5552   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5553   ins_cost(MEMORY_REF_COST);
5554 
5555   format %{ "LD      $dst, $mem \t// ptr" %}
5556   size(4);
5557   ins_encode( enc_ld(dst, mem) );
5558   ins_pipe(pipe_class_memory);
5559 %}
5560 
5561 // Load Pointer acquire.
5562 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5563   match(Set dst (LoadP mem));
5564   ins_cost(3*MEMORY_REF_COST);
5565 
5566   format %{ "LD      $dst, $mem \t// ptr acquire\n\t"
5567             "TWI     $dst\n\t"
5568             "ISYNC" %}
5569   size(12);
5570   ins_encode( enc_ld_ac(dst, mem) );
5571   ins_pipe(pipe_class_memory);
5572 %}
5573 
5574 // LoadP + CastP2L
5575 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5576   match(Set dst (CastP2X (LoadP mem)));
5577   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5578   ins_cost(MEMORY_REF_COST);
5579 
5580   format %{ "LD      $dst, $mem \t// ptr + p2x" %}
5581   size(4);
5582   ins_encode( enc_ld(dst, mem) );
5583   ins_pipe(pipe_class_memory);
5584 %}
5585 
5586 // Load compressed klass pointer.
5587 instruct loadNKlass(iRegNdst dst, memory mem) %{
5588   match(Set dst (LoadNKlass mem));
5589   ins_cost(MEMORY_REF_COST);
5590 
5591   format %{ "LWZ     $dst, $mem \t// compressed klass ptr" %}
5592   size(4);
5593   ins_encode( enc_lwz(dst, mem) );
5594   ins_pipe(pipe_class_memory);
5595 %}
5596 
5597 // Load Klass Pointer
5598 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5599   match(Set dst (LoadKlass mem));
5600   ins_cost(MEMORY_REF_COST);
5601 
5602   format %{ "LD      $dst, $mem \t// klass ptr" %}
5603   size(4);
5604   ins_encode( enc_ld(dst, mem) );
5605   ins_pipe(pipe_class_memory);
5606 %}
5607 
5608 // Load Float
5609 instruct loadF(regF dst, memory mem) %{
5610   match(Set dst (LoadF mem));
5611   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5612   ins_cost(MEMORY_REF_COST);
5613 
5614   format %{ "LFS     $dst, $mem" %}
5615   size(4);
5616   ins_encode %{
5617     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5618     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5619     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5620   %}
5621   ins_pipe(pipe_class_memory);
5622 %}
5623 
5624 // Load Float acquire.
5625 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5626   match(Set dst (LoadF mem));
5627   effect(TEMP cr0);
5628   ins_cost(3*MEMORY_REF_COST);
5629 
5630   format %{ "LFS     $dst, $mem \t// acquire\n\t"
5631             "FCMPU   cr0, $dst, $dst\n\t"
5632             "BNE     cr0, next\n"
5633             "next:\n\t"
5634             "ISYNC" %}
5635   size(16);
5636   ins_encode %{
5637     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5638     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5639     Label next;
5640     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5641     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5642     __ bne(CCR0, next);
5643     __ bind(next);
5644     __ isync();
5645   %}
5646   ins_pipe(pipe_class_memory);
5647 %}
5648 
5649 // Load Double - aligned
5650 instruct loadD(regD dst, memory mem) %{
5651   match(Set dst (LoadD mem));
5652   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5653   ins_cost(MEMORY_REF_COST);
5654 
5655   format %{ "LFD     $dst, $mem" %}
5656   size(4);
5657   ins_encode( enc_lfd(dst, mem) );
5658   ins_pipe(pipe_class_memory);
5659 %}
5660 
5661 // Load Double - aligned acquire.
5662 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5663   match(Set dst (LoadD mem));
5664   effect(TEMP cr0);
5665   ins_cost(3*MEMORY_REF_COST);
5666 
5667   format %{ "LFD     $dst, $mem \t// acquire\n\t"
5668             "FCMPU   cr0, $dst, $dst\n\t"
5669             "BNE     cr0, next\n"
5670             "next:\n\t"
5671             "ISYNC" %}
5672   size(16);
5673   ins_encode %{
5674     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5675     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5676     Label next;
5677     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5678     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5679     __ bne(CCR0, next);
5680     __ bind(next);
5681     __ isync();
5682   %}
5683   ins_pipe(pipe_class_memory);
5684 %}
5685 
5686 // Load Double - UNaligned
5687 instruct loadD_unaligned(regD dst, memory mem) %{
5688   match(Set dst (LoadD_unaligned mem));
5689   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5690   ins_cost(MEMORY_REF_COST);
5691 
5692   format %{ "LFD     $dst, $mem" %}
5693   size(4);
5694   ins_encode( enc_lfd(dst, mem) );
5695   ins_pipe(pipe_class_memory);
5696 %}
5697 
5698 //----------Constants--------------------------------------------------------
5699 
5700 // Load MachConstantTableBase: add hi offset to global toc.
5701 // TODO: Handle hidden register r29 in bundler!
5702 instruct loadToc_hi(iRegLdst dst) %{
5703   effect(DEF dst);
5704   ins_cost(DEFAULT_COST);
5705 
5706   format %{ "ADDIS   $dst, R29, DISP.hi \t// load TOC hi" %}
5707   size(4);
5708   ins_encode %{
5709     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5710     __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5711   %}
5712   ins_pipe(pipe_class_default);
5713 %}
5714 
5715 // Load MachConstantTableBase: add lo offset to global toc.
5716 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5717   effect(DEF dst, USE src);
5718   ins_cost(DEFAULT_COST);
5719 
5720   format %{ "ADDI    $dst, $src, DISP.lo \t// load TOC lo" %}
5721   size(4);
5722   ins_encode %{
5723     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5724     __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5725   %}
5726   ins_pipe(pipe_class_default);
5727 %}
5728 
5729 // Load 16-bit integer constant 0xssss????
5730 instruct loadConI16(iRegIdst dst, immI16 src) %{
5731   match(Set dst src);
5732 
5733   format %{ "LI      $dst, $src" %}
5734   size(4);
5735   ins_encode %{
5736     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5737     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5738   %}
5739   ins_pipe(pipe_class_default);
5740 %}
5741 
5742 // Load integer constant 0x????0000
5743 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5744   match(Set dst src);
5745   ins_cost(DEFAULT_COST);
5746 
5747   format %{ "LIS     $dst, $src.hi" %}
5748   size(4);
5749   ins_encode %{
5750     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5751     // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5752     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5753   %}
5754   ins_pipe(pipe_class_default);
5755 %}
5756 
5757 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5758 // and sign extended), this adds the low 16 bits.
5759 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5760   // no match-rule, false predicate
5761   effect(DEF dst, USE src1, USE src2);
5762   predicate(false);
5763 
5764   format %{ "ORI     $dst, $src1.hi, $src2.lo" %}
5765   size(4);
5766   ins_encode %{
5767     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5768     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5769   %}
5770   ins_pipe(pipe_class_default);
5771 %}
5772 
5773 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5774   match(Set dst src);
5775   ins_cost(DEFAULT_COST*2);
5776 
5777   expand %{
5778     // Would like to use $src$$constant.
5779     immI16 srcLo %{ _opnds[1]->constant() %}
5780     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5781     immIhi16 srcHi %{ _opnds[1]->constant() %}
5782     iRegIdst tmpI;
5783     loadConIhi16(tmpI, srcHi);
5784     loadConI32_lo16(dst, tmpI, srcLo);
5785   %}
5786 %}
5787 
5788 // No constant pool entries required.
5789 instruct loadConL16(iRegLdst dst, immL16 src) %{
5790   match(Set dst src);
5791 
5792   format %{ "LI      $dst, $src \t// long" %}
5793   size(4);
5794   ins_encode %{
5795     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5796     __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5797   %}
5798   ins_pipe(pipe_class_default);
5799 %}
5800 
5801 // Load long constant 0xssssssss????0000
5802 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5803   match(Set dst src);
5804   ins_cost(DEFAULT_COST);
5805 
5806   format %{ "LIS     $dst, $src.hi \t// long" %}
5807   size(4);
5808   ins_encode %{
5809     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5810     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5811   %}
5812   ins_pipe(pipe_class_default);
5813 %}
5814 
5815 // To load a 32 bit constant: merge lower 16 bits into already loaded
5816 // high 16 bits.
5817 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5818   // no match-rule, false predicate
5819   effect(DEF dst, USE src1, USE src2);
5820   predicate(false);
5821 
5822   format %{ "ORI     $dst, $src1, $src2.lo" %}
5823   size(4);
5824   ins_encode %{
5825     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5826     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5827   %}
5828   ins_pipe(pipe_class_default);
5829 %}
5830 
5831 // Load 32-bit long constant
5832 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5833   match(Set dst src);
5834   ins_cost(DEFAULT_COST*2);
5835 
5836   expand %{
5837     // Would like to use $src$$constant.
5838     immL16     srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5839     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5840     immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5841     iRegLdst tmpL;
5842     loadConL32hi16(tmpL, srcHi);
5843     loadConL32_lo16(dst, tmpL, srcLo);
5844   %}
5845 %}
5846 
5847 // Load long constant 0x????000000000000.
5848 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5849   match(Set dst src);
5850   ins_cost(DEFAULT_COST);
5851 
5852   expand %{
5853     immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5854     immI shift32 %{ 32 %}
5855     iRegLdst tmpL;
5856     loadConL32hi16(tmpL, srcHi);
5857     lshiftL_regL_immI(dst, tmpL, shift32);
5858   %}
5859 %}
5860 
5861 // Expand node for constant pool load: small offset.
5862 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5863   effect(DEF dst, USE src, USE toc);
5864   ins_cost(MEMORY_REF_COST);
5865 
5866   ins_num_consts(1);
5867   // Needed so that CallDynamicJavaDirect can compute the address of this
5868   // instruction for relocation.
5869   ins_field_cbuf_insts_offset(int);
5870 
5871   format %{ "LD      $dst, offset, $toc \t// load long $src from TOC" %}
5872   size(4);
5873   ins_encode( enc_load_long_constL(dst, src, toc) );
5874   ins_pipe(pipe_class_memory);
5875 %}
5876 
5877 // Expand node for constant pool load: large offset.
5878 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5879   effect(DEF dst, USE src, USE toc);
5880   predicate(false);
5881 
5882   ins_num_consts(1);
5883   ins_field_const_toc_offset(int);
5884   // Needed so that CallDynamicJavaDirect can compute the address of this
5885   // instruction for relocation.
5886   ins_field_cbuf_insts_offset(int);
5887 
5888   format %{ "ADDIS   $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5889   size(4);
5890   ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5891   ins_pipe(pipe_class_default);
5892 %}
5893 
5894 // Expand node for constant pool load: large offset.
5895 // No constant pool entries required.
5896 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5897   effect(DEF dst, USE src, USE base);
5898   predicate(false);
5899 
5900   ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5901 
5902   format %{ "LD      $dst, offset, $base \t// load long $src from TOC (lo)" %}
5903   size(4);
5904   ins_encode %{
5905     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5906     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5907     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5908   %}
5909   ins_pipe(pipe_class_memory);
5910 %}
5911 
5912 // Load long constant from constant table. Expand in case of
5913 // offset > 16 bit is needed.
5914 // Adlc adds toc node MachConstantTableBase.
5915 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5916   match(Set dst src);
5917   ins_cost(MEMORY_REF_COST);
5918 
5919   format %{ "LD      $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5920   // We can not inline the enc_class for the expand as that does not support constanttablebase.
5921   postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5922 %}
5923 
5924 // Load NULL as compressed oop.
5925 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5926   match(Set dst src);
5927   ins_cost(DEFAULT_COST);
5928 
5929   format %{ "LI      $dst, $src \t// compressed ptr" %}
5930   size(4);
5931   ins_encode %{
5932     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5933     __ li($dst$$Register, 0);
5934   %}
5935   ins_pipe(pipe_class_default);
5936 %}
5937 
5938 // Load hi part of compressed oop constant.
5939 instruct loadConN_hi(iRegNdst dst, immN src) %{
5940   effect(DEF dst, USE src);
5941   ins_cost(DEFAULT_COST);
5942 
5943   format %{ "LIS     $dst, $src \t// narrow oop hi" %}
5944   size(4);
5945   ins_encode %{
5946     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5947     __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5948   %}
5949   ins_pipe(pipe_class_default);
5950 %}
5951 
5952 // Add lo part of compressed oop constant to already loaded hi part.
5953 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5954   effect(DEF dst, USE src1, USE src2);
5955   ins_cost(DEFAULT_COST);
5956 
5957   format %{ "ORI     $dst, $src1, $src2 \t// narrow oop lo" %}
5958   size(4);
5959   ins_encode %{
5960     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5961     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5962     int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5963     RelocationHolder rspec = oop_Relocation::spec(oop_index);
5964     __ relocate(rspec, 1);
5965     __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5966   %}
5967   ins_pipe(pipe_class_default);
5968 %}
5969 
5970 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5971 // leaving the upper 32 bits with sign-extension bits.
5972 // This clears these bits: dst = src & 0xFFFFFFFF.
5973 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5974 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5975   effect(DEF dst, USE src);
5976   predicate(false);
5977 
5978   format %{ "MASK    $dst, $src, 0xFFFFFFFF" %} // mask
5979   size(4);
5980   ins_encode %{
5981     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5982     __ clrldi($dst$$Register, $src$$Register, 0x20);
5983   %}
5984   ins_pipe(pipe_class_default);
5985 %}
5986 
5987 // Optimize DecodeN for disjoint base.
5988 // Load base of compressed oops into a register
5989 instruct loadBase(iRegLdst dst) %{
5990   effect(DEF dst);
5991 
5992   format %{ "LoadConst $dst, heapbase" %}
5993   ins_encode %{
5994     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5995     __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
5996   %}
5997   ins_pipe(pipe_class_default);
5998 %}
5999 
6000 // Loading ConN must be postalloc expanded so that edges between
6001 // the nodes are safe. They may not interfere with a safepoint.
6002 // GL TODO: This needs three instructions: better put this into the constant pool.
6003 instruct loadConN_Ex(iRegNdst dst, immN src) %{
6004   match(Set dst src);
6005   ins_cost(DEFAULT_COST*2);
6006 
6007   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6008   postalloc_expand %{
6009     MachNode *m1 = new loadConN_hiNode();
6010     MachNode *m2 = new loadConN_loNode();
6011     MachNode *m3 = new clearMs32bNode();
6012     m1->add_req(NULL);
6013     m2->add_req(NULL, m1);
6014     m3->add_req(NULL, m2);
6015     m1->_opnds[0] = op_dst;
6016     m1->_opnds[1] = op_src;
6017     m2->_opnds[0] = op_dst;
6018     m2->_opnds[1] = op_dst;
6019     m2->_opnds[2] = op_src;
6020     m3->_opnds[0] = op_dst;
6021     m3->_opnds[1] = op_dst;
6022     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6023     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6024     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6025     nodes->push(m1);
6026     nodes->push(m2);
6027     nodes->push(m3);
6028   %}
6029 %}
6030 
6031 // We have seen a safepoint between the hi and lo parts, and this node was handled
6032 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
6033 // not a narrow oop.
6034 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
6035   match(Set dst src);
6036   effect(DEF dst, USE src);
6037   ins_cost(DEFAULT_COST);
6038 
6039   format %{ "LIS     $dst, $src \t// narrow klass hi" %}
6040   size(4);
6041   ins_encode %{
6042     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
6043     intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
6044     __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
6045   %}
6046   ins_pipe(pipe_class_default);
6047 %}
6048 
6049 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
6050 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6051   match(Set dst src1);
6052   effect(TEMP src2);
6053   ins_cost(DEFAULT_COST);
6054 
6055   format %{ "MASK    $dst, $src2, 0xFFFFFFFF" %} // mask
6056   size(4);
6057   ins_encode %{
6058     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6059     __ clrldi($dst$$Register, $src2$$Register, 0x20);
6060   %}
6061   ins_pipe(pipe_class_default);
6062 %}
6063 
6064 // This needs a match rule so that build_oop_map knows this is
6065 // not a narrow oop.
6066 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
6067   match(Set dst src1);
6068   effect(TEMP src2);
6069   ins_cost(DEFAULT_COST);
6070 
6071   format %{ "ORI     $dst, $src1, $src2 \t// narrow klass lo" %}
6072   size(4);
6073   ins_encode %{
6074     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
6075     intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
6076     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
6077     int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
6078     RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6079 
6080     __ relocate(rspec, 1);
6081     __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
6082   %}
6083   ins_pipe(pipe_class_default);
6084 %}
6085 
6086 // Loading ConNKlass must be postalloc expanded so that edges between
6087 // the nodes are safe. They may not interfere with a safepoint.
6088 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
6089   match(Set dst src);
6090   ins_cost(DEFAULT_COST*2);
6091 
6092   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
6093   postalloc_expand %{
6094     // Load high bits into register. Sign extended.
6095     MachNode *m1 = new loadConNKlass_hiNode();
6096     m1->add_req(NULL);
6097     m1->_opnds[0] = op_dst;
6098     m1->_opnds[1] = op_src;
6099     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6100     nodes->push(m1);
6101 
6102     MachNode *m2 = m1;
6103     if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6104       // Value might be 1-extended. Mask out these bits.
6105       m2 = new loadConNKlass_maskNode();
6106       m2->add_req(NULL, m1);
6107       m2->_opnds[0] = op_dst;
6108       m2->_opnds[1] = op_src;
6109       m2->_opnds[2] = op_dst;
6110       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6111       nodes->push(m2);
6112     }
6113 
6114     MachNode *m3 = new loadConNKlass_loNode();
6115     m3->add_req(NULL, m2);
6116     m3->_opnds[0] = op_dst;
6117     m3->_opnds[1] = op_src;
6118     m3->_opnds[2] = op_dst;
6119     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6120     nodes->push(m3);
6121   %}
6122 %}
6123 
6124 // 0x1 is used in object initialization (initial object header).
6125 // No constant pool entries required.
6126 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6127   match(Set dst src);
6128 
6129   format %{ "LI      $dst, $src \t// ptr" %}
6130   size(4);
6131   ins_encode %{
6132     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6133     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6134   %}
6135   ins_pipe(pipe_class_default);
6136 %}
6137 
6138 // Expand node for constant pool load: small offset.
6139 // The match rule is needed to generate the correct bottom_type(),
6140 // however this node should never match. The use of predicate is not
6141 // possible since ADLC forbids predicates for chain rules. The higher
6142 // costs do not prevent matching in this case. For that reason the
6143 // operand immP_NM with predicate(false) is used.
6144 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6145   match(Set dst src);
6146   effect(TEMP toc);
6147 
6148   ins_num_consts(1);
6149 
6150   format %{ "LD      $dst, offset, $toc \t// load ptr $src from TOC" %}
6151   size(4);
6152   ins_encode( enc_load_long_constP(dst, src, toc) );
6153   ins_pipe(pipe_class_memory);
6154 %}
6155 
6156 // Expand node for constant pool load: large offset.
6157 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6158   effect(DEF dst, USE src, USE toc);
6159   predicate(false);
6160 
6161   ins_num_consts(1);
6162   ins_field_const_toc_offset(int);
6163 
6164   format %{ "ADDIS   $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6165   size(4);
6166   ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6167   ins_pipe(pipe_class_default);
6168 %}
6169 
6170 // Expand node for constant pool load: large offset.
6171 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6172   match(Set dst src);
6173   effect(TEMP base);
6174 
6175   ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6176 
6177   format %{ "LD      $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6178   size(4);
6179   ins_encode %{
6180     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6181     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6182     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6183   %}
6184   ins_pipe(pipe_class_memory);
6185 %}
6186 
6187 // Load pointer constant from constant table. Expand in case an
6188 // offset > 16 bit is needed.
6189 // Adlc adds toc node MachConstantTableBase.
6190 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6191   match(Set dst src);
6192   ins_cost(MEMORY_REF_COST);
6193 
6194   // This rule does not use "expand" because then
6195   // the result type is not known to be an Oop.  An ADLC
6196   // enhancement will be needed to make that work - not worth it!
6197 
6198   // If this instruction rematerializes, it prolongs the live range
6199   // of the toc node, causing illegal graphs.
6200   // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6201   ins_cannot_rematerialize(true);
6202 
6203   format %{ "LD    $dst, offset, $constanttablebase \t//  load ptr $src from table, postalloc expanded" %}
6204   postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6205 %}
6206 
6207 // Expand node for constant pool load: small offset.
6208 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6209   effect(DEF dst, USE src, USE toc);
6210   ins_cost(MEMORY_REF_COST);
6211 
6212   ins_num_consts(1);
6213 
6214   format %{ "LFS     $dst, offset, $toc \t// load float $src from TOC" %}
6215   size(4);
6216   ins_encode %{
6217     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6218     address float_address = __ float_constant($src$$constant);
6219     if (float_address == NULL) {
6220       ciEnv::current()->record_out_of_memory_failure();
6221       return;
6222     }
6223     __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6224   %}
6225   ins_pipe(pipe_class_memory);
6226 %}
6227 
6228 // Expand node for constant pool load: large offset.
6229 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6230   effect(DEF dst, USE src, USE toc);
6231   ins_cost(MEMORY_REF_COST);
6232 
6233   ins_num_consts(1);
6234 
6235   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6236             "LFS     $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6237             "ADDIS   $toc, $toc, -offset_hi"%}
6238   size(12);
6239   ins_encode %{
6240     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6241     FloatRegister Rdst    = $dst$$FloatRegister;
6242     Register Rtoc         = $toc$$Register;
6243     address float_address = __ float_constant($src$$constant);
6244     if (float_address == NULL) {
6245       ciEnv::current()->record_out_of_memory_failure();
6246       return;
6247     }
6248     int offset            = __ offset_to_method_toc(float_address);
6249     int hi = (offset + (1<<15))>>16;
6250     int lo = offset - hi * (1<<16);
6251 
6252     __ addis(Rtoc, Rtoc, hi);
6253     __ lfs(Rdst, lo, Rtoc);
6254     __ addis(Rtoc, Rtoc, -hi);
6255   %}
6256   ins_pipe(pipe_class_memory);
6257 %}
6258 
6259 // Adlc adds toc node MachConstantTableBase.
6260 instruct loadConF_Ex(regF dst, immF src) %{
6261   match(Set dst src);
6262   ins_cost(MEMORY_REF_COST);
6263 
6264   // See loadConP.
6265   ins_cannot_rematerialize(true);
6266 
6267   format %{ "LFS     $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6268   postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6269 %}
6270 
6271 // Expand node for constant pool load: small offset.
6272 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6273   effect(DEF dst, USE src, USE toc);
6274   ins_cost(MEMORY_REF_COST);
6275 
6276   ins_num_consts(1);
6277 
6278   format %{ "LFD     $dst, offset, $toc \t// load double $src from TOC" %}
6279   size(4);
6280   ins_encode %{
6281     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6282     address float_address = __ double_constant($src$$constant);
6283     if (float_address == NULL) {
6284       ciEnv::current()->record_out_of_memory_failure();
6285       return;
6286     }
6287     int offset =  __ offset_to_method_toc(float_address);
6288     __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6289   %}
6290   ins_pipe(pipe_class_memory);
6291 %}
6292 
6293 // Expand node for constant pool load: large offset.
6294 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6295   effect(DEF dst, USE src, USE toc);
6296   ins_cost(MEMORY_REF_COST);
6297 
6298   ins_num_consts(1);
6299 
6300   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6301             "LFD     $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6302             "ADDIS   $toc, $toc, -offset_hi" %}
6303   size(12);
6304   ins_encode %{
6305     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6306     FloatRegister Rdst    = $dst$$FloatRegister;
6307     Register      Rtoc    = $toc$$Register;
6308     address float_address = __ double_constant($src$$constant);
6309     if (float_address == NULL) {
6310       ciEnv::current()->record_out_of_memory_failure();
6311       return;
6312     }
6313     int offset = __ offset_to_method_toc(float_address);
6314     int hi = (offset + (1<<15))>>16;
6315     int lo = offset - hi * (1<<16);
6316 
6317     __ addis(Rtoc, Rtoc, hi);
6318     __ lfd(Rdst, lo, Rtoc);
6319     __ addis(Rtoc, Rtoc, -hi);
6320   %}
6321   ins_pipe(pipe_class_memory);
6322 %}
6323 
6324 // Adlc adds toc node MachConstantTableBase.
6325 instruct loadConD_Ex(regD dst, immD src) %{
6326   match(Set dst src);
6327   ins_cost(MEMORY_REF_COST);
6328 
6329   // See loadConP.
6330   ins_cannot_rematerialize(true);
6331 
6332   format %{ "ConD    $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6333   postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6334 %}
6335 
6336 // Prefetch instructions.
6337 // Must be safe to execute with invalid address (cannot fault).
6338 
6339 // Special prefetch versions which use the dcbz instruction.
6340 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6341   match(PrefetchAllocation (AddP mem src));
6342   predicate(AllocatePrefetchStyle == 3);
6343   ins_cost(MEMORY_REF_COST);
6344 
6345   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6346   size(4);
6347   ins_encode %{
6348     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6349     __ dcbz($src$$Register, $mem$$base$$Register);
6350   %}
6351   ins_pipe(pipe_class_memory);
6352 %}
6353 
6354 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6355   match(PrefetchAllocation mem);
6356   predicate(AllocatePrefetchStyle == 3);
6357   ins_cost(MEMORY_REF_COST);
6358 
6359   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6360   size(4);
6361   ins_encode %{
6362     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6363     __ dcbz($mem$$base$$Register);
6364   %}
6365   ins_pipe(pipe_class_memory);
6366 %}
6367 
6368 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6369   match(PrefetchAllocation (AddP mem src));
6370   predicate(AllocatePrefetchStyle != 3);
6371   ins_cost(MEMORY_REF_COST);
6372 
6373   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6374   size(4);
6375   ins_encode %{
6376     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6377     __ dcbtst($src$$Register, $mem$$base$$Register);
6378   %}
6379   ins_pipe(pipe_class_memory);
6380 %}
6381 
6382 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6383   match(PrefetchAllocation mem);
6384   predicate(AllocatePrefetchStyle != 3);
6385   ins_cost(MEMORY_REF_COST);
6386 
6387   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6388   size(4);
6389   ins_encode %{
6390     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6391     __ dcbtst($mem$$base$$Register);
6392   %}
6393   ins_pipe(pipe_class_memory);
6394 %}
6395 
6396 //----------Store Instructions-------------------------------------------------
6397 
6398 // Store Byte
6399 instruct storeB(memory mem, iRegIsrc src) %{
6400   match(Set mem (StoreB mem src));
6401   ins_cost(MEMORY_REF_COST);
6402 
6403   format %{ "STB     $src, $mem \t// byte" %}
6404   size(4);
6405   ins_encode %{
6406     // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6407     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6408     __ stb($src$$Register, Idisp, $mem$$base$$Register);
6409   %}
6410   ins_pipe(pipe_class_memory);
6411 %}
6412 
6413 // Store Char/Short
6414 instruct storeC(memory mem, iRegIsrc src) %{
6415   match(Set mem (StoreC mem src));
6416   ins_cost(MEMORY_REF_COST);
6417 
6418   format %{ "STH     $src, $mem \t// short" %}
6419   size(4);
6420   ins_encode %{
6421     // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6422     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6423     __ sth($src$$Register, Idisp, $mem$$base$$Register);
6424   %}
6425   ins_pipe(pipe_class_memory);
6426 %}
6427 
6428 // Store Integer
6429 instruct storeI(memory mem, iRegIsrc src) %{
6430   match(Set mem (StoreI mem src));
6431   ins_cost(MEMORY_REF_COST);
6432 
6433   format %{ "STW     $src, $mem" %}
6434   size(4);
6435   ins_encode( enc_stw(src, mem) );
6436   ins_pipe(pipe_class_memory);
6437 %}
6438 
6439 // ConvL2I + StoreI.
6440 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6441   match(Set mem (StoreI mem (ConvL2I src)));
6442   ins_cost(MEMORY_REF_COST);
6443 
6444   format %{ "STW     l2i($src), $mem" %}
6445   size(4);
6446   ins_encode( enc_stw(src, mem) );
6447   ins_pipe(pipe_class_memory);
6448 %}
6449 
6450 // Store Long
6451 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6452   match(Set mem (StoreL mem src));
6453   ins_cost(MEMORY_REF_COST);
6454 
6455   format %{ "STD     $src, $mem \t// long" %}
6456   size(4);
6457   ins_encode( enc_std(src, mem) );
6458   ins_pipe(pipe_class_memory);
6459 %}
6460 
6461 // Store super word nodes.
6462 
6463 // Store Aligned Packed Byte long register to memory
6464 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6465   predicate(n->as_StoreVector()->memory_size() == 8);
6466   match(Set mem (StoreVector mem src));
6467   ins_cost(MEMORY_REF_COST);
6468 
6469   format %{ "STD     $mem, $src \t// packed8B" %}
6470   size(4);
6471   ins_encode( enc_std(src, mem) );
6472   ins_pipe(pipe_class_memory);
6473 %}
6474 
6475 // Store Compressed Oop
6476 instruct storeN(memory dst, iRegN_P2N src) %{
6477   match(Set dst (StoreN dst src));
6478   ins_cost(MEMORY_REF_COST);
6479 
6480   format %{ "STW     $src, $dst \t// compressed oop" %}
6481   size(4);
6482   ins_encode( enc_stw(src, dst) );
6483   ins_pipe(pipe_class_memory);
6484 %}
6485 
6486 // Store Compressed KLass
6487 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6488   match(Set dst (StoreNKlass dst src));
6489   ins_cost(MEMORY_REF_COST);
6490 
6491   format %{ "STW     $src, $dst \t// compressed klass" %}
6492   size(4);
6493   ins_encode( enc_stw(src, dst) );
6494   ins_pipe(pipe_class_memory);
6495 %}
6496 
6497 // Store Pointer
6498 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6499   match(Set dst (StoreP dst src));
6500   ins_cost(MEMORY_REF_COST);
6501 
6502   format %{ "STD     $src, $dst \t// ptr" %}
6503   size(4);
6504   ins_encode( enc_std(src, dst) );
6505   ins_pipe(pipe_class_memory);
6506 %}
6507 
6508 // Store Float
6509 instruct storeF(memory mem, regF src) %{
6510   match(Set mem (StoreF mem src));
6511   ins_cost(MEMORY_REF_COST);
6512 
6513   format %{ "STFS    $src, $mem" %}
6514   size(4);
6515   ins_encode( enc_stfs(src, mem) );
6516   ins_pipe(pipe_class_memory);
6517 %}
6518 
6519 // Store Double
6520 instruct storeD(memory mem, regD src) %{
6521   match(Set mem (StoreD mem src));
6522   ins_cost(MEMORY_REF_COST);
6523 
6524   format %{ "STFD    $src, $mem" %}
6525   size(4);
6526   ins_encode( enc_stfd(src, mem) );
6527   ins_pipe(pipe_class_memory);
6528 %}
6529 
6530 //----------Store Instructions With Zeros--------------------------------------
6531 
6532 // Card-mark for CMS garbage collection.
6533 // This cardmark does an optimization so that it must not always
6534 // do a releasing store. For this, it gets the address of
6535 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6536 // (Using releaseFieldAddr in the match rule is a hack.)
6537 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6538   match(Set mem (StoreCM mem releaseFieldAddr));
6539   effect(TEMP crx);
6540   predicate(false);
6541   ins_cost(MEMORY_REF_COST);
6542 
6543   // See loadConP.
6544   ins_cannot_rematerialize(true);
6545 
6546   format %{ "STB     #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6547   ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6548   ins_pipe(pipe_class_memory);
6549 %}
6550 
6551 // Card-mark for CMS garbage collection.
6552 // This cardmark does an optimization so that it must not always
6553 // do a releasing store. For this, it needs the constant address of
6554 // CMSCollectorCardTableModRefBSExt::_requires_release.
6555 // This constant address is split off here by expand so we can use
6556 // adlc / matcher functionality to load it from the constant section.
6557 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6558   match(Set mem (StoreCM mem zero));
6559   predicate(UseConcMarkSweepGC);
6560 
6561   expand %{
6562     immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6563     iRegLdst releaseFieldAddress;
6564     flagsReg crx;
6565     loadConL_Ex(releaseFieldAddress, baseImm);
6566     storeCM_CMS(mem, releaseFieldAddress, crx);
6567   %}
6568 %}
6569 
6570 instruct storeCM_G1(memory mem, immI_0 zero) %{
6571   match(Set mem (StoreCM mem zero));
6572   predicate(UseG1GC);
6573   ins_cost(MEMORY_REF_COST);
6574 
6575   ins_cannot_rematerialize(true);
6576 
6577   format %{ "STB     #0, $mem \t// CMS card-mark byte store (G1)" %}
6578   size(8);
6579   ins_encode %{
6580     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6581     __ li(R0, 0);
6582     //__ release(); // G1: oops are allowed to get visible after dirty marking
6583     guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6584     __ stb(R0, $mem$$disp, $mem$$base$$Register);
6585   %}
6586   ins_pipe(pipe_class_memory);
6587 %}
6588 
6589 // Convert oop pointer into compressed form.
6590 
6591 // Nodes for postalloc expand.
6592 
6593 // Shift node for expand.
6594 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6595   // The match rule is needed to make it a 'MachTypeNode'!
6596   match(Set dst (EncodeP src));
6597   predicate(false);
6598 
6599   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6600   size(4);
6601   ins_encode %{
6602     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6603     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6604   %}
6605   ins_pipe(pipe_class_default);
6606 %}
6607 
6608 // Add node for expand.
6609 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6610   // The match rule is needed to make it a 'MachTypeNode'!
6611   match(Set dst (EncodeP src));
6612   predicate(false);
6613 
6614   format %{ "SUB     $dst, $src, oop_base \t// encode" %}
6615   ins_encode %{
6616     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6617     __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6618   %}
6619   ins_pipe(pipe_class_default);
6620 %}
6621 
6622 // Conditional sub base.
6623 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6624   // The match rule is needed to make it a 'MachTypeNode'!
6625   match(Set dst (EncodeP (Binary crx src1)));
6626   predicate(false);
6627 
6628   format %{ "BEQ     $crx, done\n\t"
6629             "SUB     $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6630             "done:" %}
6631   ins_encode %{
6632     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6633     Label done;
6634     __ beq($crx$$CondRegister, done);
6635     __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6636     __ bind(done);
6637   %}
6638   ins_pipe(pipe_class_default);
6639 %}
6640 
6641 // Power 7 can use isel instruction
6642 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6643   // The match rule is needed to make it a 'MachTypeNode'!
6644   match(Set dst (EncodeP (Binary crx src1)));
6645   predicate(false);
6646 
6647   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6648   size(4);
6649   ins_encode %{
6650     // This is a Power7 instruction for which no machine description exists.
6651     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6652     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6653   %}
6654   ins_pipe(pipe_class_default);
6655 %}
6656 
6657 // Disjoint narrow oop base.
6658 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6659   match(Set dst (EncodeP src));
6660   predicate(Universe::narrow_oop_base_disjoint());
6661 
6662   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
6663   size(4);
6664   ins_encode %{
6665     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6666     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6667   %}
6668   ins_pipe(pipe_class_default);
6669 %}
6670 
6671 // shift != 0, base != 0
6672 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6673   match(Set dst (EncodeP src));
6674   effect(TEMP crx);
6675   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6676             Universe::narrow_oop_shift() != 0 &&
6677             Universe::narrow_oop_base_overlaps());
6678 
6679   format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6680   postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6681 %}
6682 
6683 // shift != 0, base != 0
6684 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6685   match(Set dst (EncodeP src));
6686   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6687             Universe::narrow_oop_shift() != 0 &&
6688             Universe::narrow_oop_base_overlaps());
6689 
6690   format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6691   postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6692 %}
6693 
6694 // shift != 0, base == 0
6695 // TODO: This is the same as encodeP_shift. Merge!
6696 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6697   match(Set dst (EncodeP src));
6698   predicate(Universe::narrow_oop_shift() != 0 &&
6699             Universe::narrow_oop_base() ==0);
6700 
6701   format %{ "SRDI    $dst, $src, #3 \t// encodeP, $src != NULL" %}
6702   size(4);
6703   ins_encode %{
6704     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6705     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6706   %}
6707   ins_pipe(pipe_class_default);
6708 %}
6709 
6710 // Compressed OOPs with narrow_oop_shift == 0.
6711 // shift == 0, base == 0
6712 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6713   match(Set dst (EncodeP src));
6714   predicate(Universe::narrow_oop_shift() == 0);
6715 
6716   format %{ "MR      $dst, $src \t// Ptr->Narrow" %}
6717   // variable size, 0 or 4.
6718   ins_encode %{
6719     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6720     __ mr_if_needed($dst$$Register, $src$$Register);
6721   %}
6722   ins_pipe(pipe_class_default);
6723 %}
6724 
6725 // Decode nodes.
6726 
6727 // Shift node for expand.
6728 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6729   // The match rule is needed to make it a 'MachTypeNode'!
6730   match(Set dst (DecodeN src));
6731   predicate(false);
6732 
6733   format %{ "SLDI    $dst, $src, #3 \t// DecodeN" %}
6734   size(4);
6735   ins_encode %{
6736     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6737     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6738   %}
6739   ins_pipe(pipe_class_default);
6740 %}
6741 
6742 // Add node for expand.
6743 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6744   // The match rule is needed to make it a 'MachTypeNode'!
6745   match(Set dst (DecodeN src));
6746   predicate(false);
6747 
6748   format %{ "ADD     $dst, $src, heapbase \t// DecodeN, add oop base" %}
6749   ins_encode %{
6750     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6751     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6752   %}
6753   ins_pipe(pipe_class_default);
6754 %}
6755 
6756 // conditianal add base for expand
6757 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6758   // The match rule is needed to make it a 'MachTypeNode'!
6759   // NOTICE that the rule is nonsense - we just have to make sure that:
6760   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6761   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6762   match(Set dst (DecodeN (Binary crx src)));
6763   predicate(false);
6764 
6765   format %{ "BEQ     $crx, done\n\t"
6766             "ADD     $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6767             "done:" %}
6768   ins_encode %{
6769     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6770     Label done;
6771     __ beq($crx$$CondRegister, done);
6772     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6773     __ bind(done);
6774   %}
6775   ins_pipe(pipe_class_default);
6776 %}
6777 
6778 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6779   // The match rule is needed to make it a 'MachTypeNode'!
6780   // NOTICE that the rule is nonsense - we just have to make sure that:
6781   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6782   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6783   match(Set dst (DecodeN (Binary crx src1)));
6784   predicate(false);
6785 
6786   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6787   size(4);
6788   ins_encode %{
6789     // This is a Power7 instruction for which no machine description exists.
6790     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6791     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6792   %}
6793   ins_pipe(pipe_class_default);
6794 %}
6795 
6796 //  shift != 0, base != 0
6797 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6798   match(Set dst (DecodeN src));
6799   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6800              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6801             Universe::narrow_oop_shift() != 0 &&
6802             Universe::narrow_oop_base() != 0);
6803   ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6804   effect(TEMP crx);
6805 
6806   format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6807   postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6808 %}
6809 
6810 // shift != 0, base == 0
6811 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6812   match(Set dst (DecodeN src));
6813   predicate(Universe::narrow_oop_shift() != 0 &&
6814             Universe::narrow_oop_base() == 0);
6815 
6816   format %{ "SLDI    $dst, $src, #3 \t// DecodeN (zerobased)" %}
6817   size(4);
6818   ins_encode %{
6819     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6820     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6821   %}
6822   ins_pipe(pipe_class_default);
6823 %}
6824 
6825 // Optimize DecodeN for disjoint base.
6826 // Shift narrow oop and or it into register that already contains the heap base.
6827 // Base == dst must hold, and is assured by construction in postaloc_expand.
6828 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6829   match(Set dst (DecodeN src));
6830   effect(TEMP base);
6831   predicate(false);
6832 
6833   format %{ "RLDIMI  $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6834   size(4);
6835   ins_encode %{
6836     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6837     __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6838   %}
6839   ins_pipe(pipe_class_default);
6840 %}
6841 
6842 // Optimize DecodeN for disjoint base.
6843 // This node requires only one cycle on the critical path.
6844 // We must postalloc_expand as we can not express use_def effects where
6845 // the used register is L and the def'ed register P.
6846 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6847   match(Set dst (DecodeN src));
6848   effect(TEMP_DEF dst);
6849   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6850              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6851             Universe::narrow_oop_base_disjoint());
6852   ins_cost(DEFAULT_COST);
6853 
6854   format %{ "MOV     $dst, heapbase \t\n"
6855             "RLDIMI  $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6856   postalloc_expand %{
6857     loadBaseNode *n1 = new loadBaseNode();
6858     n1->add_req(NULL);
6859     n1->_opnds[0] = op_dst;
6860 
6861     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6862     n2->add_req(n_region, n_src, n1);
6863     n2->_opnds[0] = op_dst;
6864     n2->_opnds[1] = op_src;
6865     n2->_opnds[2] = op_dst;
6866     n2->_bottom_type = _bottom_type;
6867 
6868     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6869     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6870 
6871     nodes->push(n1);
6872     nodes->push(n2);
6873   %}
6874 %}
6875 
6876 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6877   match(Set dst (DecodeN src));
6878   effect(TEMP_DEF dst, TEMP crx);
6879   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6880              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6881             Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6882   ins_cost(3 * DEFAULT_COST);
6883 
6884   format %{ "DecodeN  $dst, $src \t// decode with disjoint base using isel" %}
6885   postalloc_expand %{
6886     loadBaseNode *n1 = new loadBaseNode();
6887     n1->add_req(NULL);
6888     n1->_opnds[0] = op_dst;
6889 
6890     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
6891     n_compare->add_req(n_region, n_src);
6892     n_compare->_opnds[0] = op_crx;
6893     n_compare->_opnds[1] = op_src;
6894     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6895 
6896     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6897     n2->add_req(n_region, n_src, n1);
6898     n2->_opnds[0] = op_dst;
6899     n2->_opnds[1] = op_src;
6900     n2->_opnds[2] = op_dst;
6901     n2->_bottom_type = _bottom_type;
6902 
6903     cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6904     n_cond_set->add_req(n_region, n_compare, n2);
6905     n_cond_set->_opnds[0] = op_dst;
6906     n_cond_set->_opnds[1] = op_crx;
6907     n_cond_set->_opnds[2] = op_dst;
6908     n_cond_set->_bottom_type = _bottom_type;
6909 
6910     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6911     ra_->set_oop(n_cond_set, true);
6912 
6913     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6914     ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6915     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6916     ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6917 
6918     nodes->push(n1);
6919     nodes->push(n_compare);
6920     nodes->push(n2);
6921     nodes->push(n_cond_set);
6922   %}
6923 %}
6924 
6925 // src != 0, shift != 0, base != 0
6926 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6927   match(Set dst (DecodeN src));
6928   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6929              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6930             Universe::narrow_oop_shift() != 0 &&
6931             Universe::narrow_oop_base() != 0);
6932   ins_cost(2 * DEFAULT_COST);
6933 
6934   format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6935   postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6936 %}
6937 
6938 // Compressed OOPs with narrow_oop_shift == 0.
6939 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6940   match(Set dst (DecodeN src));
6941   predicate(Universe::narrow_oop_shift() == 0);
6942   ins_cost(DEFAULT_COST);
6943 
6944   format %{ "MR      $dst, $src \t// DecodeN (unscaled)" %}
6945   // variable size, 0 or 4.
6946   ins_encode %{
6947     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6948     __ mr_if_needed($dst$$Register, $src$$Register);
6949   %}
6950   ins_pipe(pipe_class_default);
6951 %}
6952 
6953 // Convert compressed oop into int for vectors alignment masking.
6954 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6955   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6956   predicate(Universe::narrow_oop_shift() == 0);
6957   ins_cost(DEFAULT_COST);
6958 
6959   format %{ "MR      $dst, $src \t// (int)DecodeN (unscaled)" %}
6960   // variable size, 0 or 4.
6961   ins_encode %{
6962     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6963     __ mr_if_needed($dst$$Register, $src$$Register);
6964   %}
6965   ins_pipe(pipe_class_default);
6966 %}
6967 
6968 // Convert klass pointer into compressed form.
6969 
6970 // Nodes for postalloc expand.
6971 
6972 // Shift node for expand.
6973 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6974   // The match rule is needed to make it a 'MachTypeNode'!
6975   match(Set dst (EncodePKlass src));
6976   predicate(false);
6977 
6978   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6979   size(4);
6980   ins_encode %{
6981     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6982     __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6983   %}
6984   ins_pipe(pipe_class_default);
6985 %}
6986 
6987 // Add node for expand.
6988 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6989   // The match rule is needed to make it a 'MachTypeNode'!
6990   match(Set dst (EncodePKlass (Binary base src)));
6991   predicate(false);
6992 
6993   format %{ "SUB     $dst, $base, $src \t// encode" %}
6994   size(4);
6995   ins_encode %{
6996     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6997     __ subf($dst$$Register, $base$$Register, $src$$Register);
6998   %}
6999   ins_pipe(pipe_class_default);
7000 %}
7001 
7002 // Disjoint narrow oop base.
7003 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
7004   match(Set dst (EncodePKlass src));
7005   predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
7006 
7007   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
7008   size(4);
7009   ins_encode %{
7010     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
7011     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
7012   %}
7013   ins_pipe(pipe_class_default);
7014 %}
7015 
7016 // shift != 0, base != 0
7017 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
7018   match(Set dst (EncodePKlass (Binary base src)));
7019   predicate(false);
7020 
7021   format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7022   postalloc_expand %{
7023     encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
7024     n1->add_req(n_region, n_base, n_src);
7025     n1->_opnds[0] = op_dst;
7026     n1->_opnds[1] = op_base;
7027     n1->_opnds[2] = op_src;
7028     n1->_bottom_type = _bottom_type;
7029 
7030     encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
7031     n2->add_req(n_region, n1);
7032     n2->_opnds[0] = op_dst;
7033     n2->_opnds[1] = op_dst;
7034     n2->_bottom_type = _bottom_type;
7035     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7036     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7037 
7038     nodes->push(n1);
7039     nodes->push(n2);
7040   %}
7041 %}
7042 
7043 // shift != 0, base != 0
7044 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
7045   match(Set dst (EncodePKlass src));
7046   //predicate(Universe::narrow_klass_shift() != 0 &&
7047   //          true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
7048 
7049   //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
7050   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7051   expand %{
7052     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
7053     iRegLdst base;
7054     loadConL_Ex(base, baseImm);
7055     encodePKlass_not_null_Ex(dst, base, src);
7056   %}
7057 %}
7058 
7059 // Decode nodes.
7060 
7061 // Shift node for expand.
7062 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
7063   // The match rule is needed to make it a 'MachTypeNode'!
7064   match(Set dst (DecodeNKlass src));
7065   predicate(false);
7066 
7067   format %{ "SLDI    $dst, $src, #3 \t// DecodeNKlass" %}
7068   size(4);
7069   ins_encode %{
7070     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
7071     __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
7072   %}
7073   ins_pipe(pipe_class_default);
7074 %}
7075 
7076 // Add node for expand.
7077 
7078 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
7079   // The match rule is needed to make it a 'MachTypeNode'!
7080   match(Set dst (DecodeNKlass (Binary base src)));
7081   predicate(false);
7082 
7083   format %{ "ADD     $dst, $base, $src \t// DecodeNKlass, add klass base" %}
7084   size(4);
7085   ins_encode %{
7086     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7087     __ add($dst$$Register, $base$$Register, $src$$Register);
7088   %}
7089   ins_pipe(pipe_class_default);
7090 %}
7091 
7092 // src != 0, shift != 0, base != 0
7093 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
7094   match(Set dst (DecodeNKlass (Binary base src)));
7095   //effect(kill src); // We need a register for the immediate result after shifting.
7096   predicate(false);
7097 
7098   format %{ "DecodeNKlass $dst =  $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
7099   postalloc_expand %{
7100     decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
7101     n1->add_req(n_region, n_base, n_src);
7102     n1->_opnds[0] = op_dst;
7103     n1->_opnds[1] = op_base;
7104     n1->_opnds[2] = op_src;
7105     n1->_bottom_type = _bottom_type;
7106 
7107     decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7108     n2->add_req(n_region, n1);
7109     n2->_opnds[0] = op_dst;
7110     n2->_opnds[1] = op_dst;
7111     n2->_bottom_type = _bottom_type;
7112 
7113     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7114     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7115 
7116     nodes->push(n1);
7117     nodes->push(n2);
7118   %}
7119 %}
7120 
7121 // src != 0, shift != 0, base != 0
7122 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7123   match(Set dst (DecodeNKlass src));
7124   // predicate(Universe::narrow_klass_shift() != 0 &&
7125   //           Universe::narrow_klass_base() != 0);
7126 
7127   //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7128 
7129   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7130   expand %{
7131     // We add first, then we shift. Like this, we can get along with one register less.
7132     // But we have to load the base pre-shifted.
7133     immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7134     iRegLdst base;
7135     loadConL_Ex(base, baseImm);
7136     decodeNKlass_notNull_addBase_Ex(dst, base, src);
7137   %}
7138 %}
7139 
7140 //----------MemBar Instructions-----------------------------------------------
7141 // Memory barrier flavors
7142 
7143 instruct membar_acquire() %{
7144   match(LoadFence);
7145   ins_cost(4*MEMORY_REF_COST);
7146 
7147   format %{ "MEMBAR-acquire" %}
7148   size(4);
7149   ins_encode %{
7150     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7151     __ acquire();
7152   %}
7153   ins_pipe(pipe_class_default);
7154 %}
7155 
7156 instruct unnecessary_membar_acquire() %{
7157   match(MemBarAcquire);
7158   ins_cost(0);
7159 
7160   format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7161   size(0);
7162   ins_encode( /*empty*/ );
7163   ins_pipe(pipe_class_default);
7164 %}
7165 
7166 instruct membar_acquire_lock() %{
7167   match(MemBarAcquireLock);
7168   ins_cost(0);
7169 
7170   format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7171   size(0);
7172   ins_encode( /*empty*/ );
7173   ins_pipe(pipe_class_default);
7174 %}
7175 
7176 instruct membar_release() %{
7177   match(MemBarRelease);
7178   match(StoreFence);
7179   ins_cost(4*MEMORY_REF_COST);
7180 
7181   format %{ "MEMBAR-release" %}
7182   size(4);
7183   ins_encode %{
7184     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7185     __ release();
7186   %}
7187   ins_pipe(pipe_class_default);
7188 %}
7189 
7190 instruct membar_storestore() %{
7191   match(MemBarStoreStore);
7192   ins_cost(4*MEMORY_REF_COST);
7193 
7194   format %{ "MEMBAR-store-store" %}
7195   size(4);
7196   ins_encode %{
7197     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7198     __ membar(Assembler::StoreStore);
7199   %}
7200   ins_pipe(pipe_class_default);
7201 %}
7202 
7203 instruct membar_release_lock() %{
7204   match(MemBarReleaseLock);
7205   ins_cost(0);
7206 
7207   format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7208   size(0);
7209   ins_encode( /*empty*/ );
7210   ins_pipe(pipe_class_default);
7211 %}
7212 
7213 instruct membar_volatile() %{
7214   match(MemBarVolatile);
7215   ins_cost(4*MEMORY_REF_COST);
7216 
7217   format %{ "MEMBAR-volatile" %}
7218   size(4);
7219   ins_encode %{
7220     // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7221     __ fence();
7222   %}
7223   ins_pipe(pipe_class_default);
7224 %}
7225 
7226 // This optimization is wrong on PPC. The following pattern is not supported:
7227 //  MemBarVolatile
7228 //   ^        ^
7229 //   |        |
7230 //  CtrlProj MemProj
7231 //   ^        ^
7232 //   |        |
7233 //   |       Load
7234 //   |
7235 //  MemBarVolatile
7236 //
7237 //  The first MemBarVolatile could get optimized out! According to
7238 //  Vladimir, this pattern can not occur on Oracle platforms.
7239 //  However, it does occur on PPC64 (because of membars in
7240 //  inline_unsafe_load_store).
7241 //
7242 // Add this node again if we found a good solution for inline_unsafe_load_store().
7243 // Don't forget to look at the implementation of post_store_load_barrier again,
7244 // we did other fixes in that method.
7245 //instruct unnecessary_membar_volatile() %{
7246 //  match(MemBarVolatile);
7247 //  predicate(Matcher::post_store_load_barrier(n));
7248 //  ins_cost(0);
7249 //
7250 //  format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7251 //  size(0);
7252 //  ins_encode( /*empty*/ );
7253 //  ins_pipe(pipe_class_default);
7254 //%}
7255 
7256 instruct membar_CPUOrder() %{
7257   match(MemBarCPUOrder);
7258   ins_cost(0);
7259 
7260   format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7261   size(0);
7262   ins_encode( /*empty*/ );
7263   ins_pipe(pipe_class_default);
7264 %}
7265 
7266 //----------Conditional Move---------------------------------------------------
7267 
7268 // Cmove using isel.
7269 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7270   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7271   predicate(VM_Version::has_isel());
7272   ins_cost(DEFAULT_COST);
7273 
7274   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7275   size(4);
7276   ins_encode %{
7277     // This is a Power7 instruction for which no machine description
7278     // exists. Anyways, the scheduler should be off on Power7.
7279     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7280     int cc        = $cmp$$cmpcode;
7281     __ isel($dst$$Register, $crx$$CondRegister,
7282             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7283   %}
7284   ins_pipe(pipe_class_default);
7285 %}
7286 
7287 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7288   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7289   predicate(!VM_Version::has_isel());
7290   ins_cost(DEFAULT_COST+BRANCH_COST);
7291 
7292   ins_variable_size_depending_on_alignment(true);
7293 
7294   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7295   // Worst case is branch + move + stop, no stop without scheduler
7296   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7297   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7298   ins_pipe(pipe_class_default);
7299 %}
7300 
7301 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7302   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7303   ins_cost(DEFAULT_COST+BRANCH_COST);
7304 
7305   ins_variable_size_depending_on_alignment(true);
7306 
7307   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7308   // Worst case is branch + move + stop, no stop without scheduler
7309   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7310   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7311   ins_pipe(pipe_class_default);
7312 %}
7313 
7314 // Cmove using isel.
7315 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7316   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7317   predicate(VM_Version::has_isel());
7318   ins_cost(DEFAULT_COST);
7319 
7320   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7321   size(4);
7322   ins_encode %{
7323     // This is a Power7 instruction for which no machine description
7324     // exists. Anyways, the scheduler should be off on Power7.
7325     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7326     int cc        = $cmp$$cmpcode;
7327     __ isel($dst$$Register, $crx$$CondRegister,
7328             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7329   %}
7330   ins_pipe(pipe_class_default);
7331 %}
7332 
7333 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7334   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7335   predicate(!VM_Version::has_isel());
7336   ins_cost(DEFAULT_COST+BRANCH_COST);
7337 
7338   ins_variable_size_depending_on_alignment(true);
7339 
7340   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7341   // Worst case is branch + move + stop, no stop without scheduler.
7342   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7343   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7344   ins_pipe(pipe_class_default);
7345 %}
7346 
7347 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7348   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7349   ins_cost(DEFAULT_COST+BRANCH_COST);
7350 
7351   ins_variable_size_depending_on_alignment(true);
7352 
7353   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7354   // Worst case is branch + move + stop, no stop without scheduler.
7355   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7356   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7357   ins_pipe(pipe_class_default);
7358 %}
7359 
7360 // Cmove using isel.
7361 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7362   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7363   predicate(VM_Version::has_isel());
7364   ins_cost(DEFAULT_COST);
7365 
7366   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7367   size(4);
7368   ins_encode %{
7369     // This is a Power7 instruction for which no machine description
7370     // exists. Anyways, the scheduler should be off on Power7.
7371     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7372     int cc        = $cmp$$cmpcode;
7373     __ isel($dst$$Register, $crx$$CondRegister,
7374             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7375   %}
7376   ins_pipe(pipe_class_default);
7377 %}
7378 
7379 // Conditional move for RegN. Only cmov(reg, reg).
7380 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7381   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7382   predicate(!VM_Version::has_isel());
7383   ins_cost(DEFAULT_COST+BRANCH_COST);
7384 
7385   ins_variable_size_depending_on_alignment(true);
7386 
7387   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7388   // Worst case is branch + move + stop, no stop without scheduler.
7389   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7390   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7391   ins_pipe(pipe_class_default);
7392 %}
7393 
7394 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7395   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7396   ins_cost(DEFAULT_COST+BRANCH_COST);
7397 
7398   ins_variable_size_depending_on_alignment(true);
7399 
7400   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7401   // Worst case is branch + move + stop, no stop without scheduler.
7402   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7403   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7404   ins_pipe(pipe_class_default);
7405 %}
7406 
7407 // Cmove using isel.
7408 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7409   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7410   predicate(VM_Version::has_isel());
7411   ins_cost(DEFAULT_COST);
7412 
7413   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7414   size(4);
7415   ins_encode %{
7416     // This is a Power7 instruction for which no machine description
7417     // exists. Anyways, the scheduler should be off on Power7.
7418     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7419     int cc        = $cmp$$cmpcode;
7420     __ isel($dst$$Register, $crx$$CondRegister,
7421             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7422   %}
7423   ins_pipe(pipe_class_default);
7424 %}
7425 
7426 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7427   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7428   predicate(!VM_Version::has_isel());
7429   ins_cost(DEFAULT_COST+BRANCH_COST);
7430 
7431   ins_variable_size_depending_on_alignment(true);
7432 
7433   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7434   // Worst case is branch + move + stop, no stop without scheduler.
7435   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7436   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7437   ins_pipe(pipe_class_default);
7438 %}
7439 
7440 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7441   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7442   ins_cost(DEFAULT_COST+BRANCH_COST);
7443 
7444   ins_variable_size_depending_on_alignment(true);
7445 
7446   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7447   // Worst case is branch + move + stop, no stop without scheduler.
7448   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7449   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7450   ins_pipe(pipe_class_default);
7451 %}
7452 
7453 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7454   match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7455   ins_cost(DEFAULT_COST+BRANCH_COST);
7456 
7457   ins_variable_size_depending_on_alignment(true);
7458 
7459   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7460   // Worst case is branch + move + stop, no stop without scheduler.
7461   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7462   ins_encode %{
7463     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7464     Label done;
7465     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7466     // Branch if not (cmp crx).
7467     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7468     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7469     // TODO PPC port __ endgroup_if_needed(_size == 12);
7470     __ bind(done);
7471   %}
7472   ins_pipe(pipe_class_default);
7473 %}
7474 
7475 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7476   match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7477   ins_cost(DEFAULT_COST+BRANCH_COST);
7478 
7479   ins_variable_size_depending_on_alignment(true);
7480 
7481   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7482   // Worst case is branch + move + stop, no stop without scheduler.
7483   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7484   ins_encode %{
7485     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7486     Label done;
7487     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7488     // Branch if not (cmp crx).
7489     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7490     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7491     // TODO PPC port __ endgroup_if_needed(_size == 12);
7492     __ bind(done);
7493   %}
7494   ins_pipe(pipe_class_default);
7495 %}
7496 
7497 //----------Conditional_store--------------------------------------------------
7498 // Conditional-store of the updated heap-top.
7499 // Used during allocation of the shared heap.
7500 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7501 
7502 // As compareAndSwapL, but return flag register instead of boolean value in
7503 // int register.
7504 // Used by sun/misc/AtomicLongCSImpl.java.
7505 // Mem_ptr must be a memory operand, else this node does not get
7506 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7507 // can be rematerialized which leads to errors.
7508 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7509   match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7510   effect(TEMP cr0);
7511   format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7512   ins_encode %{
7513     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7514     __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7515                 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7516                 noreg, NULL, true);
7517   %}
7518   ins_pipe(pipe_class_default);
7519 %}
7520 
7521 // As compareAndSwapP, but return flag register instead of boolean value in
7522 // int register.
7523 // This instruction is matched if UseTLAB is off.
7524 // Mem_ptr must be a memory operand, else this node does not get
7525 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7526 // can be rematerialized which leads to errors.
7527 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7528   match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7529   ins_cost(2*MEMORY_REF_COST);
7530 
7531   format %{ "STDCX_  if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7532   ins_encode %{
7533     // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7534     __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7535   %}
7536   ins_pipe(pipe_class_memory);
7537 %}
7538 
7539 // Implement LoadPLocked. Must be ordered against changes of the memory location
7540 // by storePConditional.
7541 // Don't know whether this is ever used.
7542 instruct loadPLocked(iRegPdst dst, memory mem) %{
7543   match(Set dst (LoadPLocked mem));
7544   ins_cost(2*MEMORY_REF_COST);
7545 
7546   format %{ "LDARX   $dst, $mem \t// loadPLocked\n\t" %}
7547   size(4);
7548   ins_encode %{
7549     // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7550     __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7551   %}
7552   ins_pipe(pipe_class_memory);
7553 %}
7554 
7555 //----------Compare-And-Swap---------------------------------------------------
7556 
7557 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7558 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))"  cannot be
7559 // matched.
7560 
7561 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7562   match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7563   effect(TEMP cr0);
7564   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7565   // Variable size: instruction count smaller if regs are disjoint.
7566   ins_encode %{
7567     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7568     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7569     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7570                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7571                 $res$$Register, true);
7572   %}
7573   ins_pipe(pipe_class_default);
7574 %}
7575 
7576 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7577   match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7578   effect(TEMP cr0);
7579   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7580   // Variable size: instruction count smaller if regs are disjoint.
7581   ins_encode %{
7582     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7583     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7584     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7585                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7586                 $res$$Register, true);
7587   %}
7588   ins_pipe(pipe_class_default);
7589 %}
7590 
7591 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7592   match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7593   effect(TEMP cr0);
7594   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7595   // Variable size: instruction count smaller if regs are disjoint.
7596   ins_encode %{
7597     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7598     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7599     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7600                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7601                 $res$$Register, NULL, true);
7602   %}
7603   ins_pipe(pipe_class_default);
7604 %}
7605 
7606 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7607   match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7608   effect(TEMP cr0);
7609   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7610   // Variable size: instruction count smaller if regs are disjoint.
7611   ins_encode %{
7612     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7613     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7614     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7615                 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(),
7616                 $res$$Register, NULL, true);
7617   %}
7618   ins_pipe(pipe_class_default);
7619 %}
7620 
7621 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7622   match(Set res (GetAndAddI mem_ptr src));
7623   effect(TEMP cr0);
7624   format %{ "GetAndAddI $res, $mem_ptr, $src" %}
7625   // Variable size: instruction count smaller if regs are disjoint.
7626   ins_encode( enc_GetAndAddI(res, mem_ptr, src) );
7627   ins_pipe(pipe_class_default);
7628 %}
7629 
7630 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7631   match(Set res (GetAndAddL mem_ptr src));
7632   effect(TEMP cr0);
7633   format %{ "GetAndAddL $res, $mem_ptr, $src" %}
7634   // Variable size: instruction count smaller if regs are disjoint.
7635   ins_encode( enc_GetAndAddL(res, mem_ptr, src) );
7636   ins_pipe(pipe_class_default);
7637 %}
7638 
7639 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
7640   match(Set res (GetAndSetI mem_ptr src));
7641   effect(TEMP cr0);
7642   format %{ "GetAndSetI $res, $mem_ptr, $src" %}
7643   // Variable size: instruction count smaller if regs are disjoint.
7644   ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7645   ins_pipe(pipe_class_default);
7646 %}
7647 
7648 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
7649   match(Set res (GetAndSetL mem_ptr src));
7650   effect(TEMP cr0);
7651   format %{ "GetAndSetL $res, $mem_ptr, $src" %}
7652   // Variable size: instruction count smaller if regs are disjoint.
7653   ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7654   ins_pipe(pipe_class_default);
7655 %}
7656 
7657 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
7658   match(Set res (GetAndSetP mem_ptr src));
7659   effect(TEMP cr0);
7660   format %{ "GetAndSetP $res, $mem_ptr, $src" %}
7661   // Variable size: instruction count smaller if regs are disjoint.
7662   ins_encode( enc_GetAndSetL(res, mem_ptr, src) );
7663   ins_pipe(pipe_class_default);
7664 %}
7665 
7666 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
7667   match(Set res (GetAndSetN mem_ptr src));
7668   effect(TEMP cr0);
7669   format %{ "GetAndSetN $res, $mem_ptr, $src" %}
7670   // Variable size: instruction count smaller if regs are disjoint.
7671   ins_encode( enc_GetAndSetI(res, mem_ptr, src) );
7672   ins_pipe(pipe_class_default);
7673 %}
7674 
7675 //----------Arithmetic Instructions--------------------------------------------
7676 // Addition Instructions
7677 
7678 // Register Addition
7679 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
7680   match(Set dst (AddI src1 src2));
7681   format %{ "ADD     $dst, $src1, $src2" %}
7682   size(4);
7683   ins_encode %{
7684     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7685     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7686   %}
7687   ins_pipe(pipe_class_default);
7688 %}
7689 
7690 // Expand does not work with above instruct. (??)
7691 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7692   // no match-rule
7693   effect(DEF dst, USE src1, USE src2);
7694   format %{ "ADD     $dst, $src1, $src2" %}
7695   size(4);
7696   ins_encode %{
7697     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7698     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7699   %}
7700   ins_pipe(pipe_class_default);
7701 %}
7702 
7703 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
7704   match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
7705   ins_cost(DEFAULT_COST*3);
7706 
7707   expand %{
7708     // FIXME: we should do this in the ideal world.
7709     iRegIdst tmp1;
7710     iRegIdst tmp2;
7711     addI_reg_reg(tmp1, src1, src2);
7712     addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
7713     addI_reg_reg(dst, tmp1, tmp2);
7714   %}
7715 %}
7716 
7717 // Immediate Addition
7718 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
7719   match(Set dst (AddI src1 src2));
7720   format %{ "ADDI    $dst, $src1, $src2" %}
7721   size(4);
7722   ins_encode %{
7723     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7724     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7725   %}
7726   ins_pipe(pipe_class_default);
7727 %}
7728 
7729 // Immediate Addition with 16-bit shifted operand
7730 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
7731   match(Set dst (AddI src1 src2));
7732   format %{ "ADDIS   $dst, $src1, $src2" %}
7733   size(4);
7734   ins_encode %{
7735     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7736     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7737   %}
7738   ins_pipe(pipe_class_default);
7739 %}
7740 
7741 // Long Addition
7742 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7743   match(Set dst (AddL src1 src2));
7744   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
7745   size(4);
7746   ins_encode %{
7747     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7748     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7749   %}
7750   ins_pipe(pipe_class_default);
7751 %}
7752 
7753 // Expand does not work with above instruct. (??)
7754 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7755   // no match-rule
7756   effect(DEF dst, USE src1, USE src2);
7757   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
7758   size(4);
7759   ins_encode %{
7760     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7761     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7762   %}
7763   ins_pipe(pipe_class_default);
7764 %}
7765 
7766 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
7767   match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
7768   ins_cost(DEFAULT_COST*3);
7769 
7770   expand %{
7771     // FIXME: we should do this in the ideal world.
7772     iRegLdst tmp1;
7773     iRegLdst tmp2;
7774     addL_reg_reg(tmp1, src1, src2);
7775     addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
7776     addL_reg_reg(dst, tmp1, tmp2);
7777   %}
7778 %}
7779 
7780 // AddL + ConvL2I.
7781 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7782   match(Set dst (ConvL2I (AddL src1 src2)));
7783 
7784   format %{ "ADD     $dst, $src1, $src2 \t// long + l2i" %}
7785   size(4);
7786   ins_encode %{
7787     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7788     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7789   %}
7790   ins_pipe(pipe_class_default);
7791 %}
7792 
7793 // No constant pool entries required.
7794 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
7795   match(Set dst (AddL src1 src2));
7796 
7797   format %{ "ADDI    $dst, $src1, $src2" %}
7798   size(4);
7799   ins_encode %{
7800     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7801     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7802   %}
7803   ins_pipe(pipe_class_default);
7804 %}
7805 
7806 // Long Immediate Addition with 16-bit shifted operand.
7807 // No constant pool entries required.
7808 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
7809   match(Set dst (AddL src1 src2));
7810 
7811   format %{ "ADDIS   $dst, $src1, $src2" %}
7812   size(4);
7813   ins_encode %{
7814     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7815     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7816   %}
7817   ins_pipe(pipe_class_default);
7818 %}
7819 
7820 // Pointer Register Addition
7821 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
7822   match(Set dst (AddP src1 src2));
7823   format %{ "ADD     $dst, $src1, $src2" %}
7824   size(4);
7825   ins_encode %{
7826     // TODO: PPC port $archOpcode(ppc64Opcode_add);
7827     __ add($dst$$Register, $src1$$Register, $src2$$Register);
7828   %}
7829   ins_pipe(pipe_class_default);
7830 %}
7831 
7832 // Pointer Immediate Addition
7833 // No constant pool entries required.
7834 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
7835   match(Set dst (AddP src1 src2));
7836 
7837   format %{ "ADDI    $dst, $src1, $src2" %}
7838   size(4);
7839   ins_encode %{
7840     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
7841     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
7842   %}
7843   ins_pipe(pipe_class_default);
7844 %}
7845 
7846 // Pointer Immediate Addition with 16-bit shifted operand.
7847 // No constant pool entries required.
7848 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
7849   match(Set dst (AddP src1 src2));
7850 
7851   format %{ "ADDIS   $dst, $src1, $src2" %}
7852   size(4);
7853   ins_encode %{
7854     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
7855     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
7856   %}
7857   ins_pipe(pipe_class_default);
7858 %}
7859 
7860 //---------------------
7861 // Subtraction Instructions
7862 
7863 // Register Subtraction
7864 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
7865   match(Set dst (SubI src1 src2));
7866   format %{ "SUBF    $dst, $src2, $src1" %}
7867   size(4);
7868   ins_encode %{
7869     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7870     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7871   %}
7872   ins_pipe(pipe_class_default);
7873 %}
7874 
7875 // Immediate Subtraction
7876 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
7877 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
7878 
7879 // SubI from constant (using subfic).
7880 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
7881   match(Set dst (SubI src1 src2));
7882   format %{ "SUBI    $dst, $src1, $src2" %}
7883 
7884   size(4);
7885   ins_encode %{
7886     // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
7887     __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
7888   %}
7889   ins_pipe(pipe_class_default);
7890 %}
7891 
7892 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
7893 // positive integers and 0xF...F for negative ones.
7894 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
7895   // no match-rule, false predicate
7896   effect(DEF dst, USE src);
7897   predicate(false);
7898 
7899   format %{ "SRAWI   $dst, $src, #31" %}
7900   size(4);
7901   ins_encode %{
7902     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
7903     __ srawi($dst$$Register, $src$$Register, 0x1f);
7904   %}
7905   ins_pipe(pipe_class_default);
7906 %}
7907 
7908 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
7909   match(Set dst (AbsI src));
7910   ins_cost(DEFAULT_COST*3);
7911 
7912   expand %{
7913     iRegIdst tmp1;
7914     iRegIdst tmp2;
7915     signmask32I_regI(tmp1, src);
7916     xorI_reg_reg(tmp2, tmp1, src);
7917     subI_reg_reg(dst, tmp2, tmp1);
7918   %}
7919 %}
7920 
7921 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
7922   match(Set dst (SubI zero src2));
7923   format %{ "NEG     $dst, $src2" %}
7924   size(4);
7925   ins_encode %{
7926     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7927     __ neg($dst$$Register, $src2$$Register);
7928   %}
7929   ins_pipe(pipe_class_default);
7930 %}
7931 
7932 // Long subtraction
7933 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
7934   match(Set dst (SubL src1 src2));
7935   format %{ "SUBF    $dst, $src2, $src1 \t// long" %}
7936   size(4);
7937   ins_encode %{
7938     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7939     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7940   %}
7941   ins_pipe(pipe_class_default);
7942 %}
7943 
7944 // SubL + convL2I.
7945 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
7946   match(Set dst (ConvL2I (SubL src1 src2)));
7947 
7948   format %{ "SUBF    $dst, $src2, $src1 \t// long + l2i" %}
7949   size(4);
7950   ins_encode %{
7951     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
7952     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
7953   %}
7954   ins_pipe(pipe_class_default);
7955 %}
7956 
7957 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7958 // positive longs and 0xF...F for negative ones.
7959 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
7960   // no match-rule, false predicate
7961   effect(DEF dst, USE src);
7962   predicate(false);
7963 
7964   format %{ "SRADI   $dst, $src, #63" %}
7965   size(4);
7966   ins_encode %{
7967     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7968     __ sradi($dst$$Register, $src$$Register, 0x3f);
7969   %}
7970   ins_pipe(pipe_class_default);
7971 %}
7972 
7973 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
7974 // positive longs and 0xF...F for negative ones.
7975 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
7976   // no match-rule, false predicate
7977   effect(DEF dst, USE src);
7978   predicate(false);
7979 
7980   format %{ "SRADI   $dst, $src, #63" %}
7981   size(4);
7982   ins_encode %{
7983     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
7984     __ sradi($dst$$Register, $src$$Register, 0x3f);
7985   %}
7986   ins_pipe(pipe_class_default);
7987 %}
7988 
7989 // Long negation
7990 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
7991   match(Set dst (SubL zero src2));
7992   format %{ "NEG     $dst, $src2 \t// long" %}
7993   size(4);
7994   ins_encode %{
7995     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
7996     __ neg($dst$$Register, $src2$$Register);
7997   %}
7998   ins_pipe(pipe_class_default);
7999 %}
8000 
8001 // NegL + ConvL2I.
8002 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8003   match(Set dst (ConvL2I (SubL zero src2)));
8004 
8005   format %{ "NEG     $dst, $src2 \t// long + l2i" %}
8006   size(4);
8007   ins_encode %{
8008     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8009     __ neg($dst$$Register, $src2$$Register);
8010   %}
8011   ins_pipe(pipe_class_default);
8012 %}
8013 
8014 // Multiplication Instructions
8015 // Integer Multiplication
8016 
8017 // Register Multiplication
8018 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8019   match(Set dst (MulI src1 src2));
8020   ins_cost(DEFAULT_COST);
8021 
8022   format %{ "MULLW   $dst, $src1, $src2" %}
8023   size(4);
8024   ins_encode %{
8025     // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8026     __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8027   %}
8028   ins_pipe(pipe_class_default);
8029 %}
8030 
8031 // Immediate Multiplication
8032 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8033   match(Set dst (MulI src1 src2));
8034   ins_cost(DEFAULT_COST);
8035 
8036   format %{ "MULLI   $dst, $src1, $src2" %}
8037   size(4);
8038   ins_encode %{
8039     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8040     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8041   %}
8042   ins_pipe(pipe_class_default);
8043 %}
8044 
8045 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8046   match(Set dst (MulL src1 src2));
8047   ins_cost(DEFAULT_COST);
8048 
8049   format %{ "MULLD   $dst $src1, $src2 \t// long" %}
8050   size(4);
8051   ins_encode %{
8052     // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8053     __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8054   %}
8055   ins_pipe(pipe_class_default);
8056 %}
8057 
8058 // Multiply high for optimized long division by constant.
8059 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8060   match(Set dst (MulHiL src1 src2));
8061   ins_cost(DEFAULT_COST);
8062 
8063   format %{ "MULHD   $dst $src1, $src2 \t// long" %}
8064   size(4);
8065   ins_encode %{
8066     // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8067     __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8068   %}
8069   ins_pipe(pipe_class_default);
8070 %}
8071 
8072 // Immediate Multiplication
8073 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8074   match(Set dst (MulL src1 src2));
8075   ins_cost(DEFAULT_COST);
8076 
8077   format %{ "MULLI   $dst, $src1, $src2" %}
8078   size(4);
8079   ins_encode %{
8080     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8081     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8082   %}
8083   ins_pipe(pipe_class_default);
8084 %}
8085 
8086 // Integer Division with Immediate -1: Negate.
8087 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8088   match(Set dst (DivI src1 src2));
8089   ins_cost(DEFAULT_COST);
8090 
8091   format %{ "NEG     $dst, $src1 \t// /-1" %}
8092   size(4);
8093   ins_encode %{
8094     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8095     __ neg($dst$$Register, $src1$$Register);
8096   %}
8097   ins_pipe(pipe_class_default);
8098 %}
8099 
8100 // Integer Division with constant, but not -1.
8101 // We should be able to improve this by checking the type of src2.
8102 // It might well be that src2 is known to be positive.
8103 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8104   match(Set dst (DivI src1 src2));
8105   predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8106   ins_cost(2*DEFAULT_COST);
8107 
8108   format %{ "DIVW    $dst, $src1, $src2 \t// /not-1" %}
8109   size(4);
8110   ins_encode %{
8111     // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8112     __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8113   %}
8114   ins_pipe(pipe_class_default);
8115 %}
8116 
8117 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8118   effect(USE_DEF dst, USE src1, USE crx);
8119   predicate(false);
8120 
8121   ins_variable_size_depending_on_alignment(true);
8122 
8123   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8124   // Worst case is branch + move + stop, no stop without scheduler.
8125   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8126   ins_encode %{
8127     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8128     Label done;
8129     __ bne($crx$$CondRegister, done);
8130     __ neg($dst$$Register, $src1$$Register);
8131     // TODO PPC port __ endgroup_if_needed(_size == 12);
8132     __ bind(done);
8133   %}
8134   ins_pipe(pipe_class_default);
8135 %}
8136 
8137 // Integer Division with Registers not containing constants.
8138 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8139   match(Set dst (DivI src1 src2));
8140   ins_cost(10*DEFAULT_COST);
8141 
8142   expand %{
8143     immI16 imm %{ (int)-1 %}
8144     flagsReg tmp1;
8145     cmpI_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8146     divI_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8147     cmovI_bne_negI_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8148   %}
8149 %}
8150 
8151 // Long Division with Immediate -1: Negate.
8152 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8153   match(Set dst (DivL src1 src2));
8154   ins_cost(DEFAULT_COST);
8155 
8156   format %{ "NEG     $dst, $src1 \t// /-1, long" %}
8157   size(4);
8158   ins_encode %{
8159     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8160     __ neg($dst$$Register, $src1$$Register);
8161   %}
8162   ins_pipe(pipe_class_default);
8163 %}
8164 
8165 // Long Division with constant, but not -1.
8166 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8167   match(Set dst (DivL src1 src2));
8168   predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8169   ins_cost(2*DEFAULT_COST);
8170 
8171   format %{ "DIVD    $dst, $src1, $src2 \t// /not-1, long" %}
8172   size(4);
8173   ins_encode %{
8174     // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8175     __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8176   %}
8177   ins_pipe(pipe_class_default);
8178 %}
8179 
8180 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8181   effect(USE_DEF dst, USE src1, USE crx);
8182   predicate(false);
8183 
8184   ins_variable_size_depending_on_alignment(true);
8185 
8186   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8187   // Worst case is branch + move + stop, no stop without scheduler.
8188   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8189   ins_encode %{
8190     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8191     Label done;
8192     __ bne($crx$$CondRegister, done);
8193     __ neg($dst$$Register, $src1$$Register);
8194     // TODO PPC port __ endgroup_if_needed(_size == 12);
8195     __ bind(done);
8196   %}
8197   ins_pipe(pipe_class_default);
8198 %}
8199 
8200 // Long Division with Registers not containing constants.
8201 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8202   match(Set dst (DivL src1 src2));
8203   ins_cost(10*DEFAULT_COST);
8204 
8205   expand %{
8206     immL16 imm %{ (int)-1 %}
8207     flagsReg tmp1;
8208     cmpL_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8209     divL_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8210     cmovL_bne_negL_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8211   %}
8212 %}
8213 
8214 // Integer Remainder with registers.
8215 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8216   match(Set dst (ModI src1 src2));
8217   ins_cost(10*DEFAULT_COST);
8218 
8219   expand %{
8220     immI16 imm %{ (int)-1 %}
8221     flagsReg tmp1;
8222     iRegIdst tmp2;
8223     iRegIdst tmp3;
8224     cmpI_reg_imm16(tmp1, src2, imm);           // check src2 == -1
8225     divI_reg_regnotMinus1(tmp2, src1, src2);   // tmp2 = src1 / src2
8226     cmovI_bne_negI_reg(tmp2, tmp1, src1);      // cmove tmp2 = neg(src1) if src2 == -1
8227     mulI_reg_reg(tmp3, src2, tmp2);            // tmp3 = src2 * tmp2
8228     subI_reg_reg(dst, src1, tmp3);             // dst = src1 - tmp3
8229   %}
8230 %}
8231 
8232 // Long Remainder with registers
8233 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8234   match(Set dst (ModL src1 src2));
8235   ins_cost(10*DEFAULT_COST);
8236 
8237   expand %{
8238     immL16 imm %{ (int)-1 %}
8239     flagsReg tmp1;
8240     iRegLdst tmp2;
8241     iRegLdst tmp3;
8242     cmpL_reg_imm16(tmp1, src2, imm);             // check src2 == -1
8243     divL_reg_regnotMinus1(tmp2, src1, src2);     // tmp2 = src1 / src2
8244     cmovL_bne_negL_reg(tmp2, tmp1, src1);        // cmove tmp2 = neg(src1) if src2 == -1
8245     mulL_reg_reg(tmp3, src2, tmp2);              // tmp3 = src2 * tmp2
8246     subL_reg_reg(dst, src1, tmp3);               // dst = src1 - tmp3
8247   %}
8248 %}
8249 
8250 // Integer Shift Instructions
8251 
8252 // Register Shift Left
8253 
8254 // Clear all but the lowest #mask bits.
8255 // Used to normalize shift amounts in registers.
8256 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8257   // no match-rule, false predicate
8258   effect(DEF dst, USE src, USE mask);
8259   predicate(false);
8260 
8261   format %{ "MASK    $dst, $src, $mask \t// clear $mask upper bits" %}
8262   size(4);
8263   ins_encode %{
8264     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8265     __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8266   %}
8267   ins_pipe(pipe_class_default);
8268 %}
8269 
8270 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8271   // no match-rule, false predicate
8272   effect(DEF dst, USE src1, USE src2);
8273   predicate(false);
8274 
8275   format %{ "SLW     $dst, $src1, $src2" %}
8276   size(4);
8277   ins_encode %{
8278     // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8279     __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8280   %}
8281   ins_pipe(pipe_class_default);
8282 %}
8283 
8284 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8285   match(Set dst (LShiftI src1 src2));
8286   ins_cost(DEFAULT_COST*2);
8287   expand %{
8288     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8289     iRegIdst tmpI;
8290     maskI_reg_imm(tmpI, src2, mask);
8291     lShiftI_reg_reg(dst, src1, tmpI);
8292   %}
8293 %}
8294 
8295 // Register Shift Left Immediate
8296 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8297   match(Set dst (LShiftI src1 src2));
8298 
8299   format %{ "SLWI    $dst, $src1, ($src2 & 0x1f)" %}
8300   size(4);
8301   ins_encode %{
8302     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8303     __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8304   %}
8305   ins_pipe(pipe_class_default);
8306 %}
8307 
8308 // AndI with negpow2-constant + LShiftI
8309 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8310   match(Set dst (LShiftI (AndI src1 src2) src3));
8311   predicate(UseRotateAndMaskInstructionsPPC64);
8312 
8313   format %{ "RLWINM  $dst, lShiftI(AndI($src1, $src2), $src3)" %}
8314   size(4);
8315   ins_encode %{
8316     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8317     long src2      = $src2$$constant;
8318     long src3      = $src3$$constant;
8319     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
8320     if (maskbits >= 32) {
8321       __ li($dst$$Register, 0); // addi
8322     } else {
8323       __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
8324     }
8325   %}
8326   ins_pipe(pipe_class_default);
8327 %}
8328 
8329 // RShiftI + AndI with negpow2-constant + LShiftI
8330 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
8331   match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
8332   predicate(UseRotateAndMaskInstructionsPPC64);
8333 
8334   format %{ "RLWINM  $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
8335   size(4);
8336   ins_encode %{
8337     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
8338     long src2      = $src2$$constant;
8339     long src3      = $src3$$constant;
8340     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
8341     if (maskbits >= 32) {
8342       __ li($dst$$Register, 0); // addi
8343     } else {
8344       __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
8345     }
8346   %}
8347   ins_pipe(pipe_class_default);
8348 %}
8349 
8350 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8351   // no match-rule, false predicate
8352   effect(DEF dst, USE src1, USE src2);
8353   predicate(false);
8354 
8355   format %{ "SLD     $dst, $src1, $src2" %}
8356   size(4);
8357   ins_encode %{
8358     // TODO: PPC port $archOpcode(ppc64Opcode_sld);
8359     __ sld($dst$$Register, $src1$$Register, $src2$$Register);
8360   %}
8361   ins_pipe(pipe_class_default);
8362 %}
8363 
8364 // Register Shift Left
8365 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8366   match(Set dst (LShiftL src1 src2));
8367   ins_cost(DEFAULT_COST*2);
8368   expand %{
8369     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8370     iRegIdst tmpI;
8371     maskI_reg_imm(tmpI, src2, mask);
8372     lShiftL_regL_regI(dst, src1, tmpI);
8373   %}
8374 %}
8375 
8376 // Register Shift Left Immediate
8377 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8378   match(Set dst (LShiftL src1 src2));
8379   format %{ "SLDI    $dst, $src1, ($src2 & 0x3f)" %}
8380   size(4);
8381   ins_encode %{
8382     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8383     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8384   %}
8385   ins_pipe(pipe_class_default);
8386 %}
8387 
8388 // If we shift more than 32 bits, we need not convert I2L.
8389 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
8390   match(Set dst (LShiftL (ConvI2L src1) src2));
8391   ins_cost(DEFAULT_COST);
8392 
8393   size(4);
8394   format %{ "SLDI    $dst, i2l($src1), $src2" %}
8395   ins_encode %{
8396     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8397     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8398   %}
8399   ins_pipe(pipe_class_default);
8400 %}
8401 
8402 // Shift a postivie int to the left.
8403 // Clrlsldi clears the upper 32 bits and shifts.
8404 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
8405   match(Set dst (LShiftL (ConvI2L src1) src2));
8406   predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
8407 
8408   format %{ "SLDI    $dst, i2l(positive_int($src1)), $src2" %}
8409   size(4);
8410   ins_encode %{
8411     // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
8412     __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
8413   %}
8414   ins_pipe(pipe_class_default);
8415 %}
8416 
8417 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8418   // no match-rule, false predicate
8419   effect(DEF dst, USE src1, USE src2);
8420   predicate(false);
8421 
8422   format %{ "SRAW    $dst, $src1, $src2" %}
8423   size(4);
8424   ins_encode %{
8425     // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
8426     __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
8427   %}
8428   ins_pipe(pipe_class_default);
8429 %}
8430 
8431 // Register Arithmetic Shift Right
8432 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8433   match(Set dst (RShiftI src1 src2));
8434   ins_cost(DEFAULT_COST*2);
8435   expand %{
8436     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8437     iRegIdst tmpI;
8438     maskI_reg_imm(tmpI, src2, mask);
8439     arShiftI_reg_reg(dst, src1, tmpI);
8440   %}
8441 %}
8442 
8443 // Register Arithmetic Shift Right Immediate
8444 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8445   match(Set dst (RShiftI src1 src2));
8446 
8447   format %{ "SRAWI   $dst, $src1, ($src2 & 0x1f)" %}
8448   size(4);
8449   ins_encode %{
8450     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8451     __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8452   %}
8453   ins_pipe(pipe_class_default);
8454 %}
8455 
8456 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8457   // no match-rule, false predicate
8458   effect(DEF dst, USE src1, USE src2);
8459   predicate(false);
8460 
8461   format %{ "SRAD    $dst, $src1, $src2" %}
8462   size(4);
8463   ins_encode %{
8464     // TODO: PPC port $archOpcode(ppc64Opcode_srad);
8465     __ srad($dst$$Register, $src1$$Register, $src2$$Register);
8466   %}
8467   ins_pipe(pipe_class_default);
8468 %}
8469 
8470 // Register Shift Right Arithmetic Long
8471 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8472   match(Set dst (RShiftL src1 src2));
8473   ins_cost(DEFAULT_COST*2);
8474 
8475   expand %{
8476     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8477     iRegIdst tmpI;
8478     maskI_reg_imm(tmpI, src2, mask);
8479     arShiftL_regL_regI(dst, src1, tmpI);
8480   %}
8481 %}
8482 
8483 // Register Shift Right Immediate
8484 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8485   match(Set dst (RShiftL src1 src2));
8486 
8487   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f)" %}
8488   size(4);
8489   ins_encode %{
8490     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8491     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8492   %}
8493   ins_pipe(pipe_class_default);
8494 %}
8495 
8496 // RShiftL + ConvL2I
8497 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8498   match(Set dst (ConvL2I (RShiftL src1 src2)));
8499 
8500   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8501   size(4);
8502   ins_encode %{
8503     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8504     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8505   %}
8506   ins_pipe(pipe_class_default);
8507 %}
8508 
8509 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8510   // no match-rule, false predicate
8511   effect(DEF dst, USE src1, USE src2);
8512   predicate(false);
8513 
8514   format %{ "SRW     $dst, $src1, $src2" %}
8515   size(4);
8516   ins_encode %{
8517     // TODO: PPC port $archOpcode(ppc64Opcode_srw);
8518     __ srw($dst$$Register, $src1$$Register, $src2$$Register);
8519   %}
8520   ins_pipe(pipe_class_default);
8521 %}
8522 
8523 // Register Shift Right
8524 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8525   match(Set dst (URShiftI src1 src2));
8526   ins_cost(DEFAULT_COST*2);
8527 
8528   expand %{
8529     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
8530     iRegIdst tmpI;
8531     maskI_reg_imm(tmpI, src2, mask);
8532     urShiftI_reg_reg(dst, src1, tmpI);
8533   %}
8534 %}
8535 
8536 // Register Shift Right Immediate
8537 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
8538   match(Set dst (URShiftI src1 src2));
8539 
8540   format %{ "SRWI    $dst, $src1, ($src2 & 0x1f)" %}
8541   size(4);
8542   ins_encode %{
8543     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8544     __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
8545   %}
8546   ins_pipe(pipe_class_default);
8547 %}
8548 
8549 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8550   // no match-rule, false predicate
8551   effect(DEF dst, USE src1, USE src2);
8552   predicate(false);
8553 
8554   format %{ "SRD     $dst, $src1, $src2" %}
8555   size(4);
8556   ins_encode %{
8557     // TODO: PPC port $archOpcode(ppc64Opcode_srd);
8558     __ srd($dst$$Register, $src1$$Register, $src2$$Register);
8559   %}
8560   ins_pipe(pipe_class_default);
8561 %}
8562 
8563 // Register Shift Right
8564 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
8565   match(Set dst (URShiftL src1 src2));
8566   ins_cost(DEFAULT_COST*2);
8567 
8568   expand %{
8569     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
8570     iRegIdst tmpI;
8571     maskI_reg_imm(tmpI, src2, mask);
8572     urShiftL_regL_regI(dst, src1, tmpI);
8573   %}
8574 %}
8575 
8576 // Register Shift Right Immediate
8577 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
8578   match(Set dst (URShiftL src1 src2));
8579 
8580   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f)" %}
8581   size(4);
8582   ins_encode %{
8583     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8584     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8585   %}
8586   ins_pipe(pipe_class_default);
8587 %}
8588 
8589 // URShiftL + ConvL2I.
8590 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
8591   match(Set dst (ConvL2I (URShiftL src1 src2)));
8592 
8593   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
8594   size(4);
8595   ins_encode %{
8596     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8597     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8598   %}
8599   ins_pipe(pipe_class_default);
8600 %}
8601 
8602 // Register Shift Right Immediate with a CastP2X
8603 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
8604   match(Set dst (URShiftL (CastP2X src1) src2));
8605 
8606   format %{ "SRDI    $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
8607   size(4);
8608   ins_encode %{
8609     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8610     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
8611   %}
8612   ins_pipe(pipe_class_default);
8613 %}
8614 
8615 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
8616   match(Set dst (ConvL2I (ConvI2L src)));
8617 
8618   format %{ "EXTSW   $dst, $src \t// int->int" %}
8619   size(4);
8620   ins_encode %{
8621     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
8622     __ extsw($dst$$Register, $src$$Register);
8623   %}
8624   ins_pipe(pipe_class_default);
8625 %}
8626 
8627 //----------Rotate Instructions------------------------------------------------
8628 
8629 // Rotate Left by 8-bit immediate
8630 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
8631   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
8632   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8633 
8634   format %{ "ROTLWI  $dst, $src, $lshift" %}
8635   size(4);
8636   ins_encode %{
8637     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8638     __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
8639   %}
8640   ins_pipe(pipe_class_default);
8641 %}
8642 
8643 // Rotate Right by 8-bit immediate
8644 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
8645   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
8646   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8647 
8648   format %{ "ROTRWI  $dst, $rshift" %}
8649   size(4);
8650   ins_encode %{
8651     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8652     __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
8653   %}
8654   ins_pipe(pipe_class_default);
8655 %}
8656 
8657 //----------Floating Point Arithmetic Instructions-----------------------------
8658 
8659 // Add float single precision
8660 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
8661   match(Set dst (AddF src1 src2));
8662 
8663   format %{ "FADDS   $dst, $src1, $src2" %}
8664   size(4);
8665   ins_encode %{
8666     // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
8667     __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8668   %}
8669   ins_pipe(pipe_class_default);
8670 %}
8671 
8672 // Add float double precision
8673 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
8674   match(Set dst (AddD src1 src2));
8675 
8676   format %{ "FADD    $dst, $src1, $src2" %}
8677   size(4);
8678   ins_encode %{
8679     // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
8680     __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8681   %}
8682   ins_pipe(pipe_class_default);
8683 %}
8684 
8685 // Sub float single precision
8686 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
8687   match(Set dst (SubF src1 src2));
8688 
8689   format %{ "FSUBS   $dst, $src1, $src2" %}
8690   size(4);
8691   ins_encode %{
8692     // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
8693     __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8694   %}
8695   ins_pipe(pipe_class_default);
8696 %}
8697 
8698 // Sub float double precision
8699 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
8700   match(Set dst (SubD src1 src2));
8701   format %{ "FSUB    $dst, $src1, $src2" %}
8702   size(4);
8703   ins_encode %{
8704     // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
8705     __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8706   %}
8707   ins_pipe(pipe_class_default);
8708 %}
8709 
8710 // Mul float single precision
8711 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
8712   match(Set dst (MulF src1 src2));
8713   format %{ "FMULS   $dst, $src1, $src2" %}
8714   size(4);
8715   ins_encode %{
8716     // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
8717     __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8718   %}
8719   ins_pipe(pipe_class_default);
8720 %}
8721 
8722 // Mul float double precision
8723 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
8724   match(Set dst (MulD src1 src2));
8725   format %{ "FMUL    $dst, $src1, $src2" %}
8726   size(4);
8727   ins_encode %{
8728     // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
8729     __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8730   %}
8731   ins_pipe(pipe_class_default);
8732 %}
8733 
8734 // Div float single precision
8735 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
8736   match(Set dst (DivF src1 src2));
8737   format %{ "FDIVS   $dst, $src1, $src2" %}
8738   size(4);
8739   ins_encode %{
8740     // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
8741     __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8742   %}
8743   ins_pipe(pipe_class_default);
8744 %}
8745 
8746 // Div float double precision
8747 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
8748   match(Set dst (DivD src1 src2));
8749   format %{ "FDIV    $dst, $src1, $src2" %}
8750   size(4);
8751   ins_encode %{
8752     // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
8753     __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
8754   %}
8755   ins_pipe(pipe_class_default);
8756 %}
8757 
8758 // Absolute float single precision
8759 instruct absF_reg(regF dst, regF src) %{
8760   match(Set dst (AbsF src));
8761   format %{ "FABS    $dst, $src \t// float" %}
8762   size(4);
8763   ins_encode %{
8764     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8765     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8766   %}
8767   ins_pipe(pipe_class_default);
8768 %}
8769 
8770 // Absolute float double precision
8771 instruct absD_reg(regD dst, regD src) %{
8772   match(Set dst (AbsD src));
8773   format %{ "FABS    $dst, $src \t// double" %}
8774   size(4);
8775   ins_encode %{
8776     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
8777     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
8778   %}
8779   ins_pipe(pipe_class_default);
8780 %}
8781 
8782 instruct negF_reg(regF dst, regF src) %{
8783   match(Set dst (NegF src));
8784   format %{ "FNEG    $dst, $src \t// float" %}
8785   size(4);
8786   ins_encode %{
8787     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8788     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8789   %}
8790   ins_pipe(pipe_class_default);
8791 %}
8792 
8793 instruct negD_reg(regD dst, regD src) %{
8794   match(Set dst (NegD src));
8795   format %{ "FNEG    $dst, $src \t// double" %}
8796   size(4);
8797   ins_encode %{
8798     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
8799     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
8800   %}
8801   ins_pipe(pipe_class_default);
8802 %}
8803 
8804 // AbsF + NegF.
8805 instruct negF_absF_reg(regF dst, regF src) %{
8806   match(Set dst (NegF (AbsF src)));
8807   format %{ "FNABS   $dst, $src \t// float" %}
8808   size(4);
8809   ins_encode %{
8810     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8811     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8812   %}
8813   ins_pipe(pipe_class_default);
8814 %}
8815 
8816 // AbsD + NegD.
8817 instruct negD_absD_reg(regD dst, regD src) %{
8818   match(Set dst (NegD (AbsD src)));
8819   format %{ "FNABS   $dst, $src \t// double" %}
8820   size(4);
8821   ins_encode %{
8822     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
8823     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
8824   %}
8825   ins_pipe(pipe_class_default);
8826 %}
8827 
8828 // VM_Version::has_fsqrt() decides if this node will be used.
8829 // Sqrt float double precision
8830 instruct sqrtD_reg(regD dst, regD src) %{
8831   match(Set dst (SqrtD src));
8832   format %{ "FSQRT   $dst, $src" %}
8833   size(4);
8834   ins_encode %{
8835     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
8836     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
8837   %}
8838   ins_pipe(pipe_class_default);
8839 %}
8840 
8841 // Single-precision sqrt.
8842 instruct sqrtF_reg(regF dst, regF src) %{
8843   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8844   predicate(VM_Version::has_fsqrts());
8845   ins_cost(DEFAULT_COST);
8846 
8847   format %{ "FSQRTS  $dst, $src" %}
8848   size(4);
8849   ins_encode %{
8850     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
8851     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
8852   %}
8853   ins_pipe(pipe_class_default);
8854 %}
8855 
8856 instruct roundDouble_nop(regD dst) %{
8857   match(Set dst (RoundDouble dst));
8858   ins_cost(0);
8859 
8860   format %{ " -- \t// RoundDouble not needed - empty" %}
8861   size(0);
8862   // PPC results are already "rounded" (i.e., normal-format IEEE).
8863   ins_encode( /*empty*/ );
8864   ins_pipe(pipe_class_default);
8865 %}
8866 
8867 instruct roundFloat_nop(regF dst) %{
8868   match(Set dst (RoundFloat dst));
8869   ins_cost(0);
8870 
8871   format %{ " -- \t// RoundFloat not needed - empty" %}
8872   size(0);
8873   // PPC results are already "rounded" (i.e., normal-format IEEE).
8874   ins_encode( /*empty*/ );
8875   ins_pipe(pipe_class_default);
8876 %}
8877 
8878 //----------Logical Instructions-----------------------------------------------
8879 
8880 // And Instructions
8881 
8882 // Register And
8883 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8884   match(Set dst (AndI src1 src2));
8885   format %{ "AND     $dst, $src1, $src2" %}
8886   size(4);
8887   ins_encode %{
8888     // TODO: PPC port $archOpcode(ppc64Opcode_and);
8889     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8890   %}
8891   ins_pipe(pipe_class_default);
8892 %}
8893 
8894 // Immediate And
8895 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
8896   match(Set dst (AndI src1 src2));
8897   effect(KILL cr0);
8898 
8899   format %{ "ANDI    $dst, $src1, $src2" %}
8900   size(4);
8901   ins_encode %{
8902     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8903     // FIXME: avoid andi_ ?
8904     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8905   %}
8906   ins_pipe(pipe_class_default);
8907 %}
8908 
8909 // Immediate And where the immediate is a negative power of 2.
8910 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
8911   match(Set dst (AndI src1 src2));
8912   format %{ "ANDWI   $dst, $src1, $src2" %}
8913   size(4);
8914   ins_encode %{
8915     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8916     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
8917   %}
8918   ins_pipe(pipe_class_default);
8919 %}
8920 
8921 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
8922   match(Set dst (AndI src1 src2));
8923   format %{ "ANDWI   $dst, $src1, $src2" %}
8924   size(4);
8925   ins_encode %{
8926     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8927     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8928   %}
8929   ins_pipe(pipe_class_default);
8930 %}
8931 
8932 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
8933   match(Set dst (AndI src1 src2));
8934   predicate(UseRotateAndMaskInstructionsPPC64);
8935   format %{ "ANDWI   $dst, $src1, $src2" %}
8936   size(4);
8937   ins_encode %{
8938     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
8939     __ rlwinm($dst$$Register, $src1$$Register, 0,
8940               (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
8941   %}
8942   ins_pipe(pipe_class_default);
8943 %}
8944 
8945 // Register And Long
8946 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8947   match(Set dst (AndL src1 src2));
8948   ins_cost(DEFAULT_COST);
8949 
8950   format %{ "AND     $dst, $src1, $src2 \t// long" %}
8951   size(4);
8952   ins_encode %{
8953     // TODO: PPC port $archOpcode(ppc64Opcode_and);
8954     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
8955   %}
8956   ins_pipe(pipe_class_default);
8957 %}
8958 
8959 // Immediate And long
8960 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
8961   match(Set dst (AndL src1 src2));
8962   effect(KILL cr0);
8963 
8964   format %{ "ANDI    $dst, $src1, $src2 \t// long" %}
8965   size(4);
8966   ins_encode %{
8967     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
8968     // FIXME: avoid andi_ ?
8969     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
8970   %}
8971   ins_pipe(pipe_class_default);
8972 %}
8973 
8974 // Immediate And Long where the immediate is a negative power of 2.
8975 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
8976   match(Set dst (AndL src1 src2));
8977   format %{ "ANDDI   $dst, $src1, $src2" %}
8978   size(4);
8979   ins_encode %{
8980     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
8981     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
8982   %}
8983   ins_pipe(pipe_class_default);
8984 %}
8985 
8986 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8987   match(Set dst (AndL src1 src2));
8988   format %{ "ANDDI   $dst, $src1, $src2" %}
8989   size(4);
8990   ins_encode %{
8991     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8992     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
8993   %}
8994   ins_pipe(pipe_class_default);
8995 %}
8996 
8997 // AndL + ConvL2I.
8998 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
8999   match(Set dst (ConvL2I (AndL src1 src2)));
9000   ins_cost(DEFAULT_COST);
9001 
9002   format %{ "ANDDI   $dst, $src1, $src2 \t// long + l2i" %}
9003   size(4);
9004   ins_encode %{
9005     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9006     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9007   %}
9008   ins_pipe(pipe_class_default);
9009 %}
9010 
9011 // Or Instructions
9012 
9013 // Register Or
9014 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9015   match(Set dst (OrI src1 src2));
9016   format %{ "OR      $dst, $src1, $src2" %}
9017   size(4);
9018   ins_encode %{
9019     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9020     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9021   %}
9022   ins_pipe(pipe_class_default);
9023 %}
9024 
9025 // Expand does not work with above instruct. (??)
9026 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9027   // no match-rule
9028   effect(DEF dst, USE src1, USE src2);
9029   format %{ "OR      $dst, $src1, $src2" %}
9030   size(4);
9031   ins_encode %{
9032     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9033     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9034   %}
9035   ins_pipe(pipe_class_default);
9036 %}
9037 
9038 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9039   match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9040   ins_cost(DEFAULT_COST*3);
9041 
9042   expand %{
9043     // FIXME: we should do this in the ideal world.
9044     iRegIdst tmp1;
9045     iRegIdst tmp2;
9046     orI_reg_reg(tmp1, src1, src2);
9047     orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9048     orI_reg_reg(dst, tmp1, tmp2);
9049   %}
9050 %}
9051 
9052 // Immediate Or
9053 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9054   match(Set dst (OrI src1 src2));
9055   format %{ "ORI     $dst, $src1, $src2" %}
9056   size(4);
9057   ins_encode %{
9058     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9059     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9060   %}
9061   ins_pipe(pipe_class_default);
9062 %}
9063 
9064 // Register Or Long
9065 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9066   match(Set dst (OrL src1 src2));
9067   ins_cost(DEFAULT_COST);
9068 
9069   size(4);
9070   format %{ "OR      $dst, $src1, $src2 \t// long" %}
9071   ins_encode %{
9072     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9073     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9074   %}
9075   ins_pipe(pipe_class_default);
9076 %}
9077 
9078 // OrL + ConvL2I.
9079 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9080   match(Set dst (ConvL2I (OrL src1 src2)));
9081   ins_cost(DEFAULT_COST);
9082 
9083   format %{ "OR      $dst, $src1, $src2 \t// long + l2i" %}
9084   size(4);
9085   ins_encode %{
9086     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9087     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9088   %}
9089   ins_pipe(pipe_class_default);
9090 %}
9091 
9092 // Immediate Or long
9093 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9094   match(Set dst (OrL src1 con));
9095   ins_cost(DEFAULT_COST);
9096 
9097   format %{ "ORI     $dst, $src1, $con \t// long" %}
9098   size(4);
9099   ins_encode %{
9100     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9101     __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9102   %}
9103   ins_pipe(pipe_class_default);
9104 %}
9105 
9106 // Xor Instructions
9107 
9108 // Register Xor
9109 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9110   match(Set dst (XorI src1 src2));
9111   format %{ "XOR     $dst, $src1, $src2" %}
9112   size(4);
9113   ins_encode %{
9114     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9115     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9116   %}
9117   ins_pipe(pipe_class_default);
9118 %}
9119 
9120 // Expand does not work with above instruct. (??)
9121 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9122   // no match-rule
9123   effect(DEF dst, USE src1, USE src2);
9124   format %{ "XOR     $dst, $src1, $src2" %}
9125   size(4);
9126   ins_encode %{
9127     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9128     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9129   %}
9130   ins_pipe(pipe_class_default);
9131 %}
9132 
9133 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9134   match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
9135   ins_cost(DEFAULT_COST*3);
9136 
9137   expand %{
9138     // FIXME: we should do this in the ideal world.
9139     iRegIdst tmp1;
9140     iRegIdst tmp2;
9141     xorI_reg_reg(tmp1, src1, src2);
9142     xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
9143     xorI_reg_reg(dst, tmp1, tmp2);
9144   %}
9145 %}
9146 
9147 // Immediate Xor
9148 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9149   match(Set dst (XorI src1 src2));
9150   format %{ "XORI    $dst, $src1, $src2" %}
9151   size(4);
9152   ins_encode %{
9153     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9154     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9155   %}
9156   ins_pipe(pipe_class_default);
9157 %}
9158 
9159 // Register Xor Long
9160 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9161   match(Set dst (XorL src1 src2));
9162   ins_cost(DEFAULT_COST);
9163 
9164   format %{ "XOR     $dst, $src1, $src2 \t// long" %}
9165   size(4);
9166   ins_encode %{
9167     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9168     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9169   %}
9170   ins_pipe(pipe_class_default);
9171 %}
9172 
9173 // XorL + ConvL2I.
9174 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9175   match(Set dst (ConvL2I (XorL src1 src2)));
9176   ins_cost(DEFAULT_COST);
9177 
9178   format %{ "XOR     $dst, $src1, $src2 \t// long + l2i" %}
9179   size(4);
9180   ins_encode %{
9181     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9182     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9183   %}
9184   ins_pipe(pipe_class_default);
9185 %}
9186 
9187 // Immediate Xor Long
9188 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
9189   match(Set dst (XorL src1 src2));
9190   ins_cost(DEFAULT_COST);
9191 
9192   format %{ "XORI    $dst, $src1, $src2 \t// long" %}
9193   size(4);
9194   ins_encode %{
9195     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
9196     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
9197   %}
9198   ins_pipe(pipe_class_default);
9199 %}
9200 
9201 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
9202   match(Set dst (XorI src1 src2));
9203   ins_cost(DEFAULT_COST);
9204 
9205   format %{ "NOT     $dst, $src1 ($src2)" %}
9206   size(4);
9207   ins_encode %{
9208     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9209     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9210   %}
9211   ins_pipe(pipe_class_default);
9212 %}
9213 
9214 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
9215   match(Set dst (XorL src1 src2));
9216   ins_cost(DEFAULT_COST);
9217 
9218   format %{ "NOT     $dst, $src1 ($src2) \t// long" %}
9219   size(4);
9220   ins_encode %{
9221     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
9222     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
9223   %}
9224   ins_pipe(pipe_class_default);
9225 %}
9226 
9227 // And-complement
9228 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
9229   match(Set dst (AndI (XorI src1 src2) src3));
9230   ins_cost(DEFAULT_COST);
9231 
9232   format %{ "ANDW    $dst, xori($src1, $src2), $src3" %}
9233   size(4);
9234   ins_encode( enc_andc(dst, src3, src1) );
9235   ins_pipe(pipe_class_default);
9236 %}
9237 
9238 // And-complement
9239 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9240   // no match-rule, false predicate
9241   effect(DEF dst, USE src1, USE src2);
9242   predicate(false);
9243 
9244   format %{ "ANDC    $dst, $src1, $src2" %}
9245   size(4);
9246   ins_encode %{
9247     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
9248     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
9249   %}
9250   ins_pipe(pipe_class_default);
9251 %}
9252 
9253 //----------Moves between int/long and float/double----------------------------
9254 //
9255 // The following rules move values from int/long registers/stack-locations
9256 // to float/double registers/stack-locations and vice versa, without doing any
9257 // conversions. These rules are used to implement the bit-conversion methods
9258 // of java.lang.Float etc., e.g.
9259 //   int   floatToIntBits(float value)
9260 //   float intBitsToFloat(int bits)
9261 //
9262 // Notes on the implementation on ppc64:
9263 // We only provide rules which move between a register and a stack-location,
9264 // because we always have to go through memory when moving between a float
9265 // register and an integer register.
9266 
9267 //---------- Chain stack slots between similar types --------
9268 
9269 // These are needed so that the rules below can match.
9270 
9271 // Load integer from stack slot
9272 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
9273   match(Set dst src);
9274   ins_cost(MEMORY_REF_COST);
9275 
9276   format %{ "LWZ     $dst, $src" %}
9277   size(4);
9278   ins_encode( enc_lwz(dst, src) );
9279   ins_pipe(pipe_class_memory);
9280 %}
9281 
9282 // Store integer to stack slot
9283 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
9284   match(Set dst src);
9285   ins_cost(MEMORY_REF_COST);
9286 
9287   format %{ "STW     $src, $dst \t// stk" %}
9288   size(4);
9289   ins_encode( enc_stw(src, dst) ); // rs=rt
9290   ins_pipe(pipe_class_memory);
9291 %}
9292 
9293 // Load long from stack slot
9294 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
9295   match(Set dst src);
9296   ins_cost(MEMORY_REF_COST);
9297 
9298   format %{ "LD      $dst, $src \t// long" %}
9299   size(4);
9300   ins_encode( enc_ld(dst, src) );
9301   ins_pipe(pipe_class_memory);
9302 %}
9303 
9304 // Store long to stack slot
9305 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
9306   match(Set dst src);
9307   ins_cost(MEMORY_REF_COST);
9308 
9309   format %{ "STD     $src, $dst \t// long" %}
9310   size(4);
9311   ins_encode( enc_std(src, dst) ); // rs=rt
9312   ins_pipe(pipe_class_memory);
9313 %}
9314 
9315 //----------Moves between int and float
9316 
9317 // Move float value from float stack-location to integer register.
9318 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
9319   match(Set dst (MoveF2I src));
9320   ins_cost(MEMORY_REF_COST);
9321 
9322   format %{ "LWZ     $dst, $src \t// MoveF2I" %}
9323   size(4);
9324   ins_encode( enc_lwz(dst, src) );
9325   ins_pipe(pipe_class_memory);
9326 %}
9327 
9328 // Move float value from float register to integer stack-location.
9329 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
9330   match(Set dst (MoveF2I src));
9331   ins_cost(MEMORY_REF_COST);
9332 
9333   format %{ "STFS    $src, $dst \t// MoveF2I" %}
9334   size(4);
9335   ins_encode( enc_stfs(src, dst) );
9336   ins_pipe(pipe_class_memory);
9337 %}
9338 
9339 // Move integer value from integer stack-location to float register.
9340 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
9341   match(Set dst (MoveI2F src));
9342   ins_cost(MEMORY_REF_COST);
9343 
9344   format %{ "LFS     $dst, $src \t// MoveI2F" %}
9345   size(4);
9346   ins_encode %{
9347     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
9348     int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
9349     __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
9350   %}
9351   ins_pipe(pipe_class_memory);
9352 %}
9353 
9354 // Move integer value from integer register to float stack-location.
9355 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
9356   match(Set dst (MoveI2F src));
9357   ins_cost(MEMORY_REF_COST);
9358 
9359   format %{ "STW     $src, $dst \t// MoveI2F" %}
9360   size(4);
9361   ins_encode( enc_stw(src, dst) );
9362   ins_pipe(pipe_class_memory);
9363 %}
9364 
9365 //----------Moves between long and float
9366 
9367 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
9368   // no match-rule, false predicate
9369   effect(DEF dst, USE src);
9370   predicate(false);
9371 
9372   format %{ "storeD  $src, $dst \t// STACK" %}
9373   size(4);
9374   ins_encode( enc_stfd(src, dst) );
9375   ins_pipe(pipe_class_default);
9376 %}
9377 
9378 //----------Moves between long and double
9379 
9380 // Move double value from double stack-location to long register.
9381 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
9382   match(Set dst (MoveD2L src));
9383   ins_cost(MEMORY_REF_COST);
9384   size(4);
9385   format %{ "LD      $dst, $src \t// MoveD2L" %}
9386   ins_encode( enc_ld(dst, src) );
9387   ins_pipe(pipe_class_memory);
9388 %}
9389 
9390 // Move double value from double register to long stack-location.
9391 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
9392   match(Set dst (MoveD2L src));
9393   effect(DEF dst, USE src);
9394   ins_cost(MEMORY_REF_COST);
9395 
9396   format %{ "STFD    $src, $dst \t// MoveD2L" %}
9397   size(4);
9398   ins_encode( enc_stfd(src, dst) );
9399   ins_pipe(pipe_class_memory);
9400 %}
9401 
9402 // Move long value from long stack-location to double register.
9403 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
9404   match(Set dst (MoveL2D src));
9405   ins_cost(MEMORY_REF_COST);
9406 
9407   format %{ "LFD     $dst, $src \t// MoveL2D" %}
9408   size(4);
9409   ins_encode( enc_lfd(dst, src) );
9410   ins_pipe(pipe_class_memory);
9411 %}
9412 
9413 // Move long value from long register to double stack-location.
9414 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
9415   match(Set dst (MoveL2D src));
9416   ins_cost(MEMORY_REF_COST);
9417 
9418   format %{ "STD     $src, $dst \t// MoveL2D" %}
9419   size(4);
9420   ins_encode( enc_std(src, dst) );
9421   ins_pipe(pipe_class_memory);
9422 %}
9423 
9424 //----------Register Move Instructions-----------------------------------------
9425 
9426 // Replicate for Superword
9427 
9428 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
9429   predicate(false);
9430   effect(DEF dst, USE src);
9431 
9432   format %{ "MR      $dst, $src \t// replicate " %}
9433   // variable size, 0 or 4.
9434   ins_encode %{
9435     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9436     __ mr_if_needed($dst$$Register, $src$$Register);
9437   %}
9438   ins_pipe(pipe_class_default);
9439 %}
9440 
9441 //----------Cast instructions (Java-level type cast)---------------------------
9442 
9443 // Cast Long to Pointer for unsafe natives.
9444 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
9445   match(Set dst (CastX2P src));
9446 
9447   format %{ "MR      $dst, $src \t// Long->Ptr" %}
9448   // variable size, 0 or 4.
9449   ins_encode %{
9450     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9451     __ mr_if_needed($dst$$Register, $src$$Register);
9452   %}
9453  ins_pipe(pipe_class_default);
9454 %}
9455 
9456 // Cast Pointer to Long for unsafe natives.
9457 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
9458   match(Set dst (CastP2X src));
9459 
9460   format %{ "MR      $dst, $src \t// Ptr->Long" %}
9461   // variable size, 0 or 4.
9462   ins_encode %{
9463     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9464     __ mr_if_needed($dst$$Register, $src$$Register);
9465   %}
9466   ins_pipe(pipe_class_default);
9467 %}
9468 
9469 instruct castPP(iRegPdst dst) %{
9470   match(Set dst (CastPP dst));
9471   format %{ " -- \t// castPP of $dst" %}
9472   size(0);
9473   ins_encode( /*empty*/ );
9474   ins_pipe(pipe_class_default);
9475 %}
9476 
9477 instruct castII(iRegIdst dst) %{
9478   match(Set dst (CastII dst));
9479   format %{ " -- \t// castII of $dst" %}
9480   size(0);
9481   ins_encode( /*empty*/ );
9482   ins_pipe(pipe_class_default);
9483 %}
9484 
9485 instruct checkCastPP(iRegPdst dst) %{
9486   match(Set dst (CheckCastPP dst));
9487   format %{ " -- \t// checkcastPP of $dst" %}
9488   size(0);
9489   ins_encode( /*empty*/ );
9490   ins_pipe(pipe_class_default);
9491 %}
9492 
9493 //----------Convert instructions-----------------------------------------------
9494 
9495 // Convert to boolean.
9496 
9497 // int_to_bool(src) : { 1   if src != 0
9498 //                    { 0   else
9499 //
9500 // strategy:
9501 // 1) Count leading zeros of 32 bit-value src,
9502 //    this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
9503 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9504 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9505 
9506 // convI2Bool
9507 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
9508   match(Set dst (Conv2B src));
9509   predicate(UseCountLeadingZerosInstructionsPPC64);
9510   ins_cost(DEFAULT_COST);
9511 
9512   expand %{
9513     immI shiftAmount %{ 0x5 %}
9514     uimmI16 mask %{ 0x1 %}
9515     iRegIdst tmp1;
9516     iRegIdst tmp2;
9517     countLeadingZerosI(tmp1, src);
9518     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9519     xorI_reg_uimm16(dst, tmp2, mask);
9520   %}
9521 %}
9522 
9523 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
9524   match(Set dst (Conv2B src));
9525   effect(TEMP crx);
9526   predicate(!UseCountLeadingZerosInstructionsPPC64);
9527   ins_cost(DEFAULT_COST);
9528 
9529   format %{ "CMPWI   $crx, $src, #0 \t// convI2B"
9530             "LI      $dst, #0\n\t"
9531             "BEQ     $crx, done\n\t"
9532             "LI      $dst, #1\n"
9533             "done:" %}
9534   size(16);
9535   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
9536   ins_pipe(pipe_class_compare);
9537 %}
9538 
9539 // ConvI2B + XorI
9540 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
9541   match(Set dst (XorI (Conv2B src) mask));
9542   predicate(UseCountLeadingZerosInstructionsPPC64);
9543   ins_cost(DEFAULT_COST);
9544 
9545   expand %{
9546     immI shiftAmount %{ 0x5 %}
9547     iRegIdst tmp1;
9548     countLeadingZerosI(tmp1, src);
9549     urShiftI_reg_imm(dst, tmp1, shiftAmount);
9550   %}
9551 %}
9552 
9553 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
9554   match(Set dst (XorI (Conv2B src) mask));
9555   effect(TEMP crx);
9556   predicate(!UseCountLeadingZerosInstructionsPPC64);
9557   ins_cost(DEFAULT_COST);
9558 
9559   format %{ "CMPWI   $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
9560             "LI      $dst, #1\n\t"
9561             "BEQ     $crx, done\n\t"
9562             "LI      $dst, #0\n"
9563             "done:" %}
9564   size(16);
9565   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
9566   ins_pipe(pipe_class_compare);
9567 %}
9568 
9569 // AndI 0b0..010..0 + ConvI2B
9570 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
9571   match(Set dst (Conv2B (AndI src mask)));
9572   predicate(UseRotateAndMaskInstructionsPPC64);
9573   ins_cost(DEFAULT_COST);
9574 
9575   format %{ "RLWINM  $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
9576   size(4);
9577   ins_encode %{
9578     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9579     __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
9580   %}
9581   ins_pipe(pipe_class_default);
9582 %}
9583 
9584 // Convert pointer to boolean.
9585 //
9586 // ptr_to_bool(src) : { 1   if src != 0
9587 //                    { 0   else
9588 //
9589 // strategy:
9590 // 1) Count leading zeros of 64 bit-value src,
9591 //    this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
9592 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
9593 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
9594 
9595 // ConvP2B
9596 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
9597   match(Set dst (Conv2B src));
9598   predicate(UseCountLeadingZerosInstructionsPPC64);
9599   ins_cost(DEFAULT_COST);
9600 
9601   expand %{
9602     immI shiftAmount %{ 0x6 %}
9603     uimmI16 mask %{ 0x1 %}
9604     iRegIdst tmp1;
9605     iRegIdst tmp2;
9606     countLeadingZerosP(tmp1, src);
9607     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
9608     xorI_reg_uimm16(dst, tmp2, mask);
9609   %}
9610 %}
9611 
9612 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
9613   match(Set dst (Conv2B src));
9614   effect(TEMP crx);
9615   predicate(!UseCountLeadingZerosInstructionsPPC64);
9616   ins_cost(DEFAULT_COST);
9617 
9618   format %{ "CMPDI   $crx, $src, #0 \t// convP2B"
9619             "LI      $dst, #0\n\t"
9620             "BEQ     $crx, done\n\t"
9621             "LI      $dst, #1\n"
9622             "done:" %}
9623   size(16);
9624   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
9625   ins_pipe(pipe_class_compare);
9626 %}
9627 
9628 // ConvP2B + XorI
9629 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
9630   match(Set dst (XorI (Conv2B src) mask));
9631   predicate(UseCountLeadingZerosInstructionsPPC64);
9632   ins_cost(DEFAULT_COST);
9633 
9634   expand %{
9635     immI shiftAmount %{ 0x6 %}
9636     iRegIdst tmp1;
9637     countLeadingZerosP(tmp1, src);
9638     urShiftI_reg_imm(dst, tmp1, shiftAmount);
9639   %}
9640 %}
9641 
9642 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
9643   match(Set dst (XorI (Conv2B src) mask));
9644   effect(TEMP crx);
9645   predicate(!UseCountLeadingZerosInstructionsPPC64);
9646   ins_cost(DEFAULT_COST);
9647 
9648   format %{ "CMPDI   $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
9649             "LI      $dst, #1\n\t"
9650             "BEQ     $crx, done\n\t"
9651             "LI      $dst, #0\n"
9652             "done:" %}
9653   size(16);
9654   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
9655   ins_pipe(pipe_class_compare);
9656 %}
9657 
9658 // if src1 < src2, return -1 else return 0
9659 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9660   match(Set dst (CmpLTMask src1 src2));
9661   ins_cost(DEFAULT_COST*4);
9662 
9663   expand %{
9664     iRegLdst src1s;
9665     iRegLdst src2s;
9666     iRegLdst diff;
9667     convI2L_reg(src1s, src1); // Ensure proper sign extension.
9668     convI2L_reg(src2s, src2); // Ensure proper sign extension.
9669     subL_reg_reg(diff, src1s, src2s);
9670     // Need to consider >=33 bit result, therefore we need signmaskL.
9671     signmask64I_regL(dst, diff);
9672   %}
9673 %}
9674 
9675 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
9676   match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
9677   format %{ "SRAWI   $dst, $src1, $src2 \t// CmpLTMask" %}
9678   size(4);
9679   ins_encode %{
9680     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9681     __ srawi($dst$$Register, $src1$$Register, 0x1f);
9682   %}
9683   ins_pipe(pipe_class_default);
9684 %}
9685 
9686 //----------Arithmetic Conversion Instructions---------------------------------
9687 
9688 // Convert to Byte  -- nop
9689 // Convert to Short -- nop
9690 
9691 // Convert to Int
9692 
9693 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
9694   match(Set dst (RShiftI (LShiftI src amount) amount));
9695   format %{ "EXTSB   $dst, $src \t// byte->int" %}
9696   size(4);
9697   ins_encode %{
9698     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
9699     __ extsb($dst$$Register, $src$$Register);
9700   %}
9701   ins_pipe(pipe_class_default);
9702 %}
9703 
9704 // LShiftI 16 + RShiftI 16 converts short to int.
9705 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
9706   match(Set dst (RShiftI (LShiftI src amount) amount));
9707   format %{ "EXTSH   $dst, $src \t// short->int" %}
9708   size(4);
9709   ins_encode %{
9710     // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
9711     __ extsh($dst$$Register, $src$$Register);
9712   %}
9713   ins_pipe(pipe_class_default);
9714 %}
9715 
9716 // ConvL2I + ConvI2L: Sign extend int in long register.
9717 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
9718   match(Set dst (ConvI2L (ConvL2I src)));
9719 
9720   format %{ "EXTSW   $dst, $src \t// long->long" %}
9721   size(4);
9722   ins_encode %{
9723     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9724     __ extsw($dst$$Register, $src$$Register);
9725   %}
9726   ins_pipe(pipe_class_default);
9727 %}
9728 
9729 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
9730   match(Set dst (ConvL2I src));
9731   format %{ "MR      $dst, $src \t// long->int" %}
9732   // variable size, 0 or 4
9733   ins_encode %{
9734     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9735     __ mr_if_needed($dst$$Register, $src$$Register);
9736   %}
9737   ins_pipe(pipe_class_default);
9738 %}
9739 
9740 instruct convD2IRaw_regD(regD dst, regD src) %{
9741   // no match-rule, false predicate
9742   effect(DEF dst, USE src);
9743   predicate(false);
9744 
9745   format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
9746   size(4);
9747   ins_encode %{
9748     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
9749     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9750   %}
9751   ins_pipe(pipe_class_default);
9752 %}
9753 
9754 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
9755   // no match-rule, false predicate
9756   effect(DEF dst, USE crx, USE src);
9757   predicate(false);
9758 
9759   ins_variable_size_depending_on_alignment(true);
9760 
9761   format %{ "cmovI   $crx, $dst, $src" %}
9762   // Worst case is branch + move + stop, no stop without scheduler.
9763   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
9764   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9765   ins_pipe(pipe_class_default);
9766 %}
9767 
9768 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
9769   // no match-rule, false predicate
9770   effect(DEF dst, USE crx, USE mem);
9771   predicate(false);
9772 
9773   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
9774   postalloc_expand %{
9775     //
9776     // replaces
9777     //
9778     //   region  dst  crx  mem
9779     //    \       |    |   /
9780     //     dst=cmovI_bso_stackSlotL_conLvalue0
9781     //
9782     // with
9783     //
9784     //   region  dst
9785     //    \       /
9786     //     dst=loadConI16(0)
9787     //      |
9788     //      ^  region  dst  crx  mem
9789     //      |   \       |    |    /
9790     //      dst=cmovI_bso_stackSlotL
9791     //
9792 
9793     // Create new nodes.
9794     MachNode *m1 = new loadConI16Node();
9795     MachNode *m2 = new cmovI_bso_stackSlotLNode();
9796 
9797     // inputs for new nodes
9798     m1->add_req(n_region);
9799     m2->add_req(n_region, n_crx, n_mem);
9800 
9801     // precedences for new nodes
9802     m2->add_prec(m1);
9803 
9804     // operands for new nodes
9805     m1->_opnds[0] = op_dst;
9806     m1->_opnds[1] = new immI16Oper(0);
9807 
9808     m2->_opnds[0] = op_dst;
9809     m2->_opnds[1] = op_crx;
9810     m2->_opnds[2] = op_mem;
9811 
9812     // registers for new nodes
9813     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9814     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9815 
9816     // Insert new nodes.
9817     nodes->push(m1);
9818     nodes->push(m2);
9819   %}
9820 %}
9821 
9822 // Double to Int conversion, NaN is mapped to 0.
9823 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
9824   match(Set dst (ConvD2I src));
9825   ins_cost(DEFAULT_COST);
9826 
9827   expand %{
9828     regD tmpD;
9829     stackSlotL tmpS;
9830     flagsReg crx;
9831     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9832     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
9833     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
9834     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9835   %}
9836 %}
9837 
9838 instruct convF2IRaw_regF(regF dst, regF src) %{
9839   // no match-rule, false predicate
9840   effect(DEF dst, USE src);
9841   predicate(false);
9842 
9843   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
9844   size(4);
9845   ins_encode %{
9846     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9847     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
9848   %}
9849   ins_pipe(pipe_class_default);
9850 %}
9851 
9852 // Float to Int conversion, NaN is mapped to 0.
9853 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
9854   match(Set dst (ConvF2I src));
9855   ins_cost(DEFAULT_COST);
9856 
9857   expand %{
9858     regF tmpF;
9859     stackSlotL tmpS;
9860     flagsReg crx;
9861     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9862     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
9863     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
9864     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
9865   %}
9866 %}
9867 
9868 // Convert to Long
9869 
9870 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
9871   match(Set dst (ConvI2L src));
9872   format %{ "EXTSW   $dst, $src \t// int->long" %}
9873   size(4);
9874   ins_encode %{
9875     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9876     __ extsw($dst$$Register, $src$$Register);
9877   %}
9878   ins_pipe(pipe_class_default);
9879 %}
9880 
9881 // Zero-extend: convert unsigned int to long (convUI2L).
9882 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
9883   match(Set dst (AndL (ConvI2L src) mask));
9884   ins_cost(DEFAULT_COST);
9885 
9886   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
9887   size(4);
9888   ins_encode %{
9889     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9890     __ clrldi($dst$$Register, $src$$Register, 32);
9891   %}
9892   ins_pipe(pipe_class_default);
9893 %}
9894 
9895 // Zero-extend: convert unsigned int to long in long register.
9896 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
9897   match(Set dst (AndL src mask));
9898   ins_cost(DEFAULT_COST);
9899 
9900   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
9901   size(4);
9902   ins_encode %{
9903     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9904     __ clrldi($dst$$Register, $src$$Register, 32);
9905   %}
9906   ins_pipe(pipe_class_default);
9907 %}
9908 
9909 instruct convF2LRaw_regF(regF dst, regF src) %{
9910   // no match-rule, false predicate
9911   effect(DEF dst, USE src);
9912   predicate(false);
9913 
9914   format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
9915   size(4);
9916   ins_encode %{
9917     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
9918     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
9919   %}
9920   ins_pipe(pipe_class_default);
9921 %}
9922 
9923 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
9924   // no match-rule, false predicate
9925   effect(DEF dst, USE crx, USE src);
9926   predicate(false);
9927 
9928   ins_variable_size_depending_on_alignment(true);
9929 
9930   format %{ "cmovL   $crx, $dst, $src" %}
9931   // Worst case is branch + move + stop, no stop without scheduler.
9932   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
9933   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
9934   ins_pipe(pipe_class_default);
9935 %}
9936 
9937 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
9938   // no match-rule, false predicate
9939   effect(DEF dst, USE crx, USE mem);
9940   predicate(false);
9941 
9942   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
9943   postalloc_expand %{
9944     //
9945     // replaces
9946     //
9947     //   region  dst  crx  mem
9948     //    \       |    |   /
9949     //     dst=cmovL_bso_stackSlotL_conLvalue0
9950     //
9951     // with
9952     //
9953     //   region  dst
9954     //    \       /
9955     //     dst=loadConL16(0)
9956     //      |
9957     //      ^  region  dst  crx  mem
9958     //      |   \       |    |    /
9959     //      dst=cmovL_bso_stackSlotL
9960     //
9961 
9962     // Create new nodes.
9963     MachNode *m1 = new loadConL16Node();
9964     MachNode *m2 = new cmovL_bso_stackSlotLNode();
9965 
9966     // inputs for new nodes
9967     m1->add_req(n_region);
9968     m2->add_req(n_region, n_crx, n_mem);
9969     m2->add_prec(m1);
9970 
9971     // operands for new nodes
9972     m1->_opnds[0] = op_dst;
9973     m1->_opnds[1] = new immL16Oper(0);
9974     m2->_opnds[0] = op_dst;
9975     m2->_opnds[1] = op_crx;
9976     m2->_opnds[2] = op_mem;
9977 
9978     // registers for new nodes
9979     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9980     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
9981 
9982     // Insert new nodes.
9983     nodes->push(m1);
9984     nodes->push(m2);
9985   %}
9986 %}
9987 
9988 // Float to Long conversion, NaN is mapped to 0.
9989 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
9990   match(Set dst (ConvF2L src));
9991   ins_cost(DEFAULT_COST);
9992 
9993   expand %{
9994     regF tmpF;
9995     stackSlotL tmpS;
9996     flagsReg crx;
9997     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
9998     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
9999     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10000     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10001   %}
10002 %}
10003 
10004 instruct convD2LRaw_regD(regD dst, regD src) %{
10005   // no match-rule, false predicate
10006   effect(DEF dst, USE src);
10007   predicate(false);
10008 
10009   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10010   size(4);
10011   ins_encode %{
10012     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10013     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10014   %}
10015   ins_pipe(pipe_class_default);
10016 %}
10017 
10018 // Double to Long conversion, NaN is mapped to 0.
10019 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10020   match(Set dst (ConvD2L src));
10021   ins_cost(DEFAULT_COST);
10022 
10023   expand %{
10024     regD tmpD;
10025     stackSlotL tmpS;
10026     flagsReg crx;
10027     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10028     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
10029     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10030     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10031   %}
10032 %}
10033 
10034 // Convert to Float
10035 
10036 // Placed here as needed in expand.
10037 instruct convL2DRaw_regD(regD dst, regD src) %{
10038   // no match-rule, false predicate
10039   effect(DEF dst, USE src);
10040   predicate(false);
10041 
10042   format %{ "FCFID $dst, $src \t// convL2D" %}
10043   size(4);
10044   ins_encode %{
10045     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10046     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10047   %}
10048   ins_pipe(pipe_class_default);
10049 %}
10050 
10051 // Placed here as needed in expand.
10052 instruct convD2F_reg(regF dst, regD src) %{
10053   match(Set dst (ConvD2F src));
10054   format %{ "FRSP    $dst, $src \t// convD2F" %}
10055   size(4);
10056   ins_encode %{
10057     // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
10058     __ frsp($dst$$FloatRegister, $src$$FloatRegister);
10059   %}
10060   ins_pipe(pipe_class_default);
10061 %}
10062 
10063 // Integer to Float conversion.
10064 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
10065   match(Set dst (ConvI2F src));
10066   predicate(!VM_Version::has_fcfids());
10067   ins_cost(DEFAULT_COST);
10068 
10069   expand %{
10070     iRegLdst tmpL;
10071     stackSlotL tmpS;
10072     regD tmpD;
10073     regD tmpD2;
10074     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10075     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10076     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10077     convL2DRaw_regD(tmpD2, tmpD);        // Convert to double.
10078     convD2F_reg(dst, tmpD2);             // Convert double to float.
10079   %}
10080 %}
10081 
10082 instruct convL2FRaw_regF(regF dst, regD src) %{
10083   // no match-rule, false predicate
10084   effect(DEF dst, USE src);
10085   predicate(false);
10086 
10087   format %{ "FCFIDS $dst, $src \t// convL2F" %}
10088   size(4);
10089   ins_encode %{
10090     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10091     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10092   %}
10093   ins_pipe(pipe_class_default);
10094 %}
10095 
10096 // Integer to Float conversion. Special version for Power7.
10097 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10098   match(Set dst (ConvI2F src));
10099   predicate(VM_Version::has_fcfids());
10100   ins_cost(DEFAULT_COST);
10101 
10102   expand %{
10103     iRegLdst tmpL;
10104     stackSlotL tmpS;
10105     regD tmpD;
10106     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10107     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10108     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10109     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10110   %}
10111 %}
10112 
10113 // L2F to avoid runtime call.
10114 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10115   match(Set dst (ConvL2F src));
10116   predicate(VM_Version::has_fcfids());
10117   ins_cost(DEFAULT_COST);
10118 
10119   expand %{
10120     stackSlotL tmpS;
10121     regD tmpD;
10122     regL_to_stkL(tmpS, src);             // Store long to stack.
10123     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10124     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10125   %}
10126 %}
10127 
10128 // Moved up as used in expand.
10129 //instruct convD2F_reg(regF dst, regD src) %{%}
10130 
10131 // Convert to Double
10132 
10133 // Integer to Double conversion.
10134 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
10135   match(Set dst (ConvI2D src));
10136   ins_cost(DEFAULT_COST);
10137 
10138   expand %{
10139     iRegLdst tmpL;
10140     stackSlotL tmpS;
10141     regD tmpD;
10142     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10143     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10144     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10145     convL2DRaw_regD(dst, tmpD);          // Convert to double.
10146   %}
10147 %}
10148 
10149 // Long to Double conversion
10150 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
10151   match(Set dst (ConvL2D src));
10152   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10153 
10154   expand %{
10155     regD tmpD;
10156     moveL2D_stack_reg(tmpD, src);
10157     convL2DRaw_regD(dst, tmpD);
10158   %}
10159 %}
10160 
10161 instruct convF2D_reg(regD dst, regF src) %{
10162   match(Set dst (ConvF2D src));
10163   format %{ "FMR     $dst, $src \t// float->double" %}
10164   // variable size, 0 or 4
10165   ins_encode %{
10166     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
10167     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
10168   %}
10169   ins_pipe(pipe_class_default);
10170 %}
10171 
10172 //----------Control Flow Instructions------------------------------------------
10173 // Compare Instructions
10174 
10175 // Compare Integers
10176 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10177   match(Set crx (CmpI src1 src2));
10178   size(4);
10179   format %{ "CMPW    $crx, $src1, $src2" %}
10180   ins_encode %{
10181     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10182     __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10183   %}
10184   ins_pipe(pipe_class_compare);
10185 %}
10186 
10187 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
10188   match(Set crx (CmpI src1 src2));
10189   format %{ "CMPWI   $crx, $src1, $src2" %}
10190   size(4);
10191   ins_encode %{
10192     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10193     __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10194   %}
10195   ins_pipe(pipe_class_compare);
10196 %}
10197 
10198 // (src1 & src2) == 0?
10199 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
10200   match(Set cr0 (CmpI (AndI src1 src2) zero));
10201   // r0 is killed
10202   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
10203   size(4);
10204   ins_encode %{
10205     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10206     __ andi_(R0, $src1$$Register, $src2$$constant);
10207   %}
10208   ins_pipe(pipe_class_compare);
10209 %}
10210 
10211 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
10212   match(Set crx (CmpL src1 src2));
10213   format %{ "CMPD    $crx, $src1, $src2" %}
10214   size(4);
10215   ins_encode %{
10216     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
10217     __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
10218   %}
10219   ins_pipe(pipe_class_compare);
10220 %}
10221 
10222 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
10223   match(Set crx (CmpL src1 src2));
10224   format %{ "CMPDI   $crx, $src1, $src2" %}
10225   size(4);
10226   ins_encode %{
10227     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10228     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10229   %}
10230   ins_pipe(pipe_class_compare);
10231 %}
10232 
10233 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
10234   match(Set cr0 (CmpL (AndL src1 src2) zero));
10235   // r0 is killed
10236   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
10237   size(4);
10238   ins_encode %{
10239     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
10240     __ and_(R0, $src1$$Register, $src2$$Register);
10241   %}
10242   ins_pipe(pipe_class_compare);
10243 %}
10244 
10245 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
10246   match(Set cr0 (CmpL (AndL src1 src2) zero));
10247   // r0 is killed
10248   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
10249   size(4);
10250   ins_encode %{
10251     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
10252     __ andi_(R0, $src1$$Register, $src2$$constant);
10253   %}
10254   ins_pipe(pipe_class_compare);
10255 %}
10256 
10257 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
10258   // no match-rule, false predicate
10259   effect(DEF dst, USE crx);
10260   predicate(false);
10261 
10262   ins_variable_size_depending_on_alignment(true);
10263 
10264   format %{ "cmovI   $crx, $dst, -1, 0, +1" %}
10265   // Worst case is branch + move + branch + move + stop, no stop without scheduler.
10266   size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
10267   ins_encode %{
10268     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
10269     Label done;
10270     // li(Rdst, 0);              // equal -> 0
10271     __ beq($crx$$CondRegister, done);
10272     __ li($dst$$Register, 1);    // greater -> +1
10273     __ bgt($crx$$CondRegister, done);
10274     __ li($dst$$Register, -1);   // unordered or less -> -1
10275     // TODO: PPC port__ endgroup_if_needed(_size == 20);
10276     __ bind(done);
10277   %}
10278   ins_pipe(pipe_class_compare);
10279 %}
10280 
10281 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
10282   // no match-rule, false predicate
10283   effect(DEF dst, USE crx);
10284   predicate(false);
10285 
10286   format %{ "CmovI    $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
10287   postalloc_expand %{
10288     //
10289     // replaces
10290     //
10291     //   region  crx
10292     //    \       |
10293     //     dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
10294     //
10295     // with
10296     //
10297     //   region
10298     //    \
10299     //     dst=loadConI16(0)
10300     //      |
10301     //      ^  region  crx
10302     //      |   \       |
10303     //      dst=cmovI_conIvalueMinus1_conIvalue1
10304     //
10305 
10306     // Create new nodes.
10307     MachNode *m1 = new loadConI16Node();
10308     MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
10309 
10310     // inputs for new nodes
10311     m1->add_req(n_region);
10312     m2->add_req(n_region, n_crx);
10313     m2->add_prec(m1);
10314 
10315     // operands for new nodes
10316     m1->_opnds[0] = op_dst;
10317     m1->_opnds[1] = new immI16Oper(0);
10318     m2->_opnds[0] = op_dst;
10319     m2->_opnds[1] = op_crx;
10320 
10321     // registers for new nodes
10322     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10323     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10324 
10325     // Insert new nodes.
10326     nodes->push(m1);
10327     nodes->push(m2);
10328   %}
10329 %}
10330 
10331 // Manifest a CmpL3 result in an integer register. Very painful.
10332 // This is the test to avoid.
10333 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
10334 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10335   match(Set dst (CmpL3 src1 src2));
10336   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10337 
10338   expand %{
10339     flagsReg tmp1;
10340     cmpL_reg_reg(tmp1, src1, src2);
10341     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10342   %}
10343 %}
10344 
10345 // Implicit range checks.
10346 // A range check in the ideal world has one of the following shapes:
10347 //  - (If le (CmpU length index)), (IfTrue  throw exception)
10348 //  - (If lt (CmpU index length)), (IfFalse throw exception)
10349 //
10350 // Match range check 'If le (CmpU length index)'.
10351 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
10352   match(If cmp (CmpU src_length index));
10353   effect(USE labl);
10354   predicate(TrapBasedRangeChecks &&
10355             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
10356             PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
10357             (Matcher::branches_to_uncommon_trap(_leaf)));
10358 
10359   ins_is_TrapBasedCheckNode(true);
10360 
10361   format %{ "TWI     $index $cmp $src_length \t// RangeCheck => trap $labl" %}
10362   size(4);
10363   ins_encode %{
10364     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10365     if ($cmp$$cmpcode == 0x1 /* less_equal */) {
10366       __ trap_range_check_le($src_length$$Register, $index$$constant);
10367     } else {
10368       // Both successors are uncommon traps, probability is 0.
10369       // Node got flipped during fixup flow.
10370       assert($cmp$$cmpcode == 0x9, "must be greater");
10371       __ trap_range_check_g($src_length$$Register, $index$$constant);
10372     }
10373   %}
10374   ins_pipe(pipe_class_trap);
10375 %}
10376 
10377 // Match range check 'If lt (CmpU index length)'.
10378 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
10379   match(If cmp (CmpU src_index src_length));
10380   effect(USE labl);
10381   predicate(TrapBasedRangeChecks &&
10382             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10383             _leaf->as_If()->_prob >= PROB_ALWAYS &&
10384             (Matcher::branches_to_uncommon_trap(_leaf)));
10385 
10386   ins_is_TrapBasedCheckNode(true);
10387 
10388   format %{ "TW      $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
10389   size(4);
10390   ins_encode %{
10391     // TODO: PPC port $archOpcode(ppc64Opcode_tw);
10392     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10393       __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
10394     } else {
10395       // Both successors are uncommon traps, probability is 0.
10396       // Node got flipped during fixup flow.
10397       assert($cmp$$cmpcode == 0x8, "must be less");
10398       __ trap_range_check_l($src_index$$Register, $src_length$$Register);
10399     }
10400   %}
10401   ins_pipe(pipe_class_trap);
10402 %}
10403 
10404 // Match range check 'If lt (CmpU index length)'.
10405 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
10406   match(If cmp (CmpU src_index length));
10407   effect(USE labl);
10408   predicate(TrapBasedRangeChecks &&
10409             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
10410             _leaf->as_If()->_prob >= PROB_ALWAYS &&
10411             (Matcher::branches_to_uncommon_trap(_leaf)));
10412 
10413   ins_is_TrapBasedCheckNode(true);
10414 
10415   format %{ "TWI     $src_index $cmp $length \t// RangeCheck => trap $labl" %}
10416   size(4);
10417   ins_encode %{
10418     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
10419     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
10420       __ trap_range_check_ge($src_index$$Register, $length$$constant);
10421     } else {
10422       // Both successors are uncommon traps, probability is 0.
10423       // Node got flipped during fixup flow.
10424       assert($cmp$$cmpcode == 0x8, "must be less");
10425       __ trap_range_check_l($src_index$$Register, $length$$constant);
10426     }
10427   %}
10428   ins_pipe(pipe_class_trap);
10429 %}
10430 
10431 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
10432   match(Set crx (CmpU src1 src2));
10433   format %{ "CMPLW   $crx, $src1, $src2 \t// unsigned" %}
10434   size(4);
10435   ins_encode %{
10436     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10437     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10438   %}
10439   ins_pipe(pipe_class_compare);
10440 %}
10441 
10442 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
10443   match(Set crx (CmpU src1 src2));
10444   size(4);
10445   format %{ "CMPLWI  $crx, $src1, $src2" %}
10446   ins_encode %{
10447     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10448     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10449   %}
10450   ins_pipe(pipe_class_compare);
10451 %}
10452 
10453 // Implicit zero checks (more implicit null checks).
10454 // No constant pool entries required.
10455 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
10456   match(If cmp (CmpN value zero));
10457   effect(USE labl);
10458   predicate(TrapBasedNullChecks &&
10459             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10460             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10461             Matcher::branches_to_uncommon_trap(_leaf));
10462   ins_cost(1);
10463 
10464   ins_is_TrapBasedCheckNode(true);
10465 
10466   format %{ "TDI     $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
10467   size(4);
10468   ins_encode %{
10469     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10470     if ($cmp$$cmpcode == 0xA) {
10471       __ trap_null_check($value$$Register);
10472     } else {
10473       // Both successors are uncommon traps, probability is 0.
10474       // Node got flipped during fixup flow.
10475       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10476       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10477     }
10478   %}
10479   ins_pipe(pipe_class_trap);
10480 %}
10481 
10482 // Compare narrow oops.
10483 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
10484   match(Set crx (CmpN src1 src2));
10485 
10486   size(4);
10487   ins_cost(2);
10488   format %{ "CMPLW   $crx, $src1, $src2 \t// compressed ptr" %}
10489   ins_encode %{
10490     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10491     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
10492   %}
10493   ins_pipe(pipe_class_compare);
10494 %}
10495 
10496 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
10497   match(Set crx (CmpN src1 src2));
10498   // Make this more expensive than zeroCheckN_iReg_imm0.
10499   ins_cost(2);
10500 
10501   format %{ "CMPLWI  $crx, $src1, $src2 \t// compressed ptr" %}
10502   size(4);
10503   ins_encode %{
10504     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
10505     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10506   %}
10507   ins_pipe(pipe_class_compare);
10508 %}
10509 
10510 // Implicit zero checks (more implicit null checks).
10511 // No constant pool entries required.
10512 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
10513   match(If cmp (CmpP value zero));
10514   effect(USE labl);
10515   predicate(TrapBasedNullChecks &&
10516             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
10517             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
10518             Matcher::branches_to_uncommon_trap(_leaf));
10519   ins_cost(1); // Should not be cheaper than zeroCheckN.
10520 
10521   ins_is_TrapBasedCheckNode(true);
10522 
10523   format %{ "TDI     $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
10524   size(4);
10525   ins_encode %{
10526     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
10527     if ($cmp$$cmpcode == 0xA) {
10528       __ trap_null_check($value$$Register);
10529     } else {
10530       // Both successors are uncommon traps, probability is 0.
10531       // Node got flipped during fixup flow.
10532       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
10533       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
10534     }
10535   %}
10536   ins_pipe(pipe_class_trap);
10537 %}
10538 
10539 // Compare Pointers
10540 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
10541   match(Set crx (CmpP src1 src2));
10542   format %{ "CMPLD   $crx, $src1, $src2 \t// ptr" %}
10543   size(4);
10544   ins_encode %{
10545     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
10546     __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
10547   %}
10548   ins_pipe(pipe_class_compare);
10549 %}
10550 
10551 // Used in postalloc expand.
10552 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
10553   // This match rule prevents reordering of node before a safepoint.
10554   // This only makes sense if this instructions is used exclusively
10555   // for the expansion of EncodeP!
10556   match(Set crx (CmpP src1 src2));
10557   predicate(false);
10558 
10559   format %{ "CMPDI   $crx, $src1, $src2" %}
10560   size(4);
10561   ins_encode %{
10562     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
10563     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
10564   %}
10565   ins_pipe(pipe_class_compare);
10566 %}
10567 
10568 //----------Float Compares----------------------------------------------------
10569 
10570 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
10571   // Needs matchrule, see cmpDUnordered.
10572   match(Set crx (CmpF src1 src2));
10573   // no match-rule, false predicate
10574   predicate(false);
10575 
10576   format %{ "cmpFUrd $crx, $src1, $src2" %}
10577   size(4);
10578   ins_encode %{
10579     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10580     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10581   %}
10582   ins_pipe(pipe_class_default);
10583 %}
10584 
10585 instruct cmov_bns_less(flagsReg crx) %{
10586   // no match-rule, false predicate
10587   effect(DEF crx);
10588   predicate(false);
10589 
10590   ins_variable_size_depending_on_alignment(true);
10591 
10592   format %{ "cmov    $crx" %}
10593   // Worst case is branch + move + stop, no stop without scheduler.
10594   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
10595   ins_encode %{
10596     // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
10597     Label done;
10598     __ bns($crx$$CondRegister, done);        // not unordered -> keep crx
10599     __ li(R0, 0);
10600     __ cmpwi($crx$$CondRegister, R0, 1);     // unordered -> set crx to 'less'
10601     // TODO PPC port __ endgroup_if_needed(_size == 16);
10602     __ bind(done);
10603   %}
10604   ins_pipe(pipe_class_default);
10605 %}
10606 
10607 // Compare floating, generate condition code.
10608 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
10609   // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
10610   //
10611   // The following code sequence occurs a lot in mpegaudio:
10612   //
10613   // block BXX:
10614   // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
10615   //    cmpFUrd CCR6, F11, F9
10616   // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
10617   //    cmov CCR6
10618   // 8: instruct branchConSched:
10619   //    B_FARle CCR6, B56  P=0.500000 C=-1.000000
10620   match(Set crx (CmpF src1 src2));
10621   ins_cost(DEFAULT_COST+BRANCH_COST);
10622 
10623   format %{ "CmpF    $crx, $src1, $src2 \t// postalloc expanded" %}
10624   postalloc_expand %{
10625     //
10626     // replaces
10627     //
10628     //   region  src1  src2
10629     //    \       |     |
10630     //     crx=cmpF_reg_reg
10631     //
10632     // with
10633     //
10634     //   region  src1  src2
10635     //    \       |     |
10636     //     crx=cmpFUnordered_reg_reg
10637     //      |
10638     //      ^  region
10639     //      |   \
10640     //      crx=cmov_bns_less
10641     //
10642 
10643     // Create new nodes.
10644     MachNode *m1 = new cmpFUnordered_reg_regNode();
10645     MachNode *m2 = new cmov_bns_lessNode();
10646 
10647     // inputs for new nodes
10648     m1->add_req(n_region, n_src1, n_src2);
10649     m2->add_req(n_region);
10650     m2->add_prec(m1);
10651 
10652     // operands for new nodes
10653     m1->_opnds[0] = op_crx;
10654     m1->_opnds[1] = op_src1;
10655     m1->_opnds[2] = op_src2;
10656     m2->_opnds[0] = op_crx;
10657 
10658     // registers for new nodes
10659     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10660     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10661 
10662     // Insert new nodes.
10663     nodes->push(m1);
10664     nodes->push(m2);
10665   %}
10666 %}
10667 
10668 // Compare float, generate -1,0,1
10669 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
10670   match(Set dst (CmpF3 src1 src2));
10671   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10672 
10673   expand %{
10674     flagsReg tmp1;
10675     cmpFUnordered_reg_reg(tmp1, src1, src2);
10676     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10677   %}
10678 %}
10679 
10680 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
10681   // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
10682   // node right before the conditional move using it.
10683   // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
10684   // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
10685   // crashed in register allocation where the flags Reg between cmpDUnoredered and a
10686   // conditional move was supposed to be spilled.
10687   match(Set crx (CmpD src1 src2));
10688   // False predicate, shall not be matched.
10689   predicate(false);
10690 
10691   format %{ "cmpFUrd $crx, $src1, $src2" %}
10692   size(4);
10693   ins_encode %{
10694     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
10695     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
10696   %}
10697   ins_pipe(pipe_class_default);
10698 %}
10699 
10700 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
10701   match(Set crx (CmpD src1 src2));
10702   ins_cost(DEFAULT_COST+BRANCH_COST);
10703 
10704   format %{ "CmpD    $crx, $src1, $src2 \t// postalloc expanded" %}
10705   postalloc_expand %{
10706     //
10707     // replaces
10708     //
10709     //   region  src1  src2
10710     //    \       |     |
10711     //     crx=cmpD_reg_reg
10712     //
10713     // with
10714     //
10715     //   region  src1  src2
10716     //    \       |     |
10717     //     crx=cmpDUnordered_reg_reg
10718     //      |
10719     //      ^  region
10720     //      |   \
10721     //      crx=cmov_bns_less
10722     //
10723 
10724     // create new nodes
10725     MachNode *m1 = new cmpDUnordered_reg_regNode();
10726     MachNode *m2 = new cmov_bns_lessNode();
10727 
10728     // inputs for new nodes
10729     m1->add_req(n_region, n_src1, n_src2);
10730     m2->add_req(n_region);
10731     m2->add_prec(m1);
10732 
10733     // operands for new nodes
10734     m1->_opnds[0] = op_crx;
10735     m1->_opnds[1] = op_src1;
10736     m1->_opnds[2] = op_src2;
10737     m2->_opnds[0] = op_crx;
10738 
10739     // registers for new nodes
10740     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10741     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
10742 
10743     // Insert new nodes.
10744     nodes->push(m1);
10745     nodes->push(m2);
10746   %}
10747 %}
10748 
10749 // Compare double, generate -1,0,1
10750 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
10751   match(Set dst (CmpD3 src1 src2));
10752   ins_cost(DEFAULT_COST*5+BRANCH_COST);
10753 
10754   expand %{
10755     flagsReg tmp1;
10756     cmpDUnordered_reg_reg(tmp1, src1, src2);
10757     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
10758   %}
10759 %}
10760 
10761 //----------Branches---------------------------------------------------------
10762 // Jump
10763 
10764 // Direct Branch.
10765 instruct branch(label labl) %{
10766   match(Goto);
10767   effect(USE labl);
10768   ins_cost(BRANCH_COST);
10769 
10770   format %{ "B       $labl" %}
10771   size(4);
10772   ins_encode %{
10773     // TODO: PPC port $archOpcode(ppc64Opcode_b);
10774      Label d;    // dummy
10775      __ bind(d);
10776      Label* p = $labl$$label;
10777      // `p' is `NULL' when this encoding class is used only to
10778      // determine the size of the encoded instruction.
10779      Label& l = (NULL == p)? d : *(p);
10780      __ b(l);
10781   %}
10782   ins_pipe(pipe_class_default);
10783 %}
10784 
10785 // Conditional Near Branch
10786 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10787   // Same match rule as `branchConFar'.
10788   match(If cmp crx);
10789   effect(USE lbl);
10790   ins_cost(BRANCH_COST);
10791 
10792   // If set to 1 this indicates that the current instruction is a
10793   // short variant of a long branch. This avoids using this
10794   // instruction in first-pass matching. It will then only be used in
10795   // the `Shorten_branches' pass.
10796   ins_short_branch(1);
10797 
10798   format %{ "B$cmp     $crx, $lbl" %}
10799   size(4);
10800   ins_encode( enc_bc(crx, cmp, lbl) );
10801   ins_pipe(pipe_class_default);
10802 %}
10803 
10804 // This is for cases when the ppc64 `bc' instruction does not
10805 // reach far enough. So we emit a far branch here, which is more
10806 // expensive.
10807 //
10808 // Conditional Far Branch
10809 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10810   // Same match rule as `branchCon'.
10811   match(If cmp crx);
10812   effect(USE crx, USE lbl);
10813   predicate(!false /* TODO: PPC port HB_Schedule*/);
10814   // Higher cost than `branchCon'.
10815   ins_cost(5*BRANCH_COST);
10816 
10817   // This is not a short variant of a branch, but the long variant.
10818   ins_short_branch(0);
10819 
10820   format %{ "B_FAR$cmp $crx, $lbl" %}
10821   size(8);
10822   ins_encode( enc_bc_far(crx, cmp, lbl) );
10823   ins_pipe(pipe_class_default);
10824 %}
10825 
10826 // Conditional Branch used with Power6 scheduler (can be far or short).
10827 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
10828   // Same match rule as `branchCon'.
10829   match(If cmp crx);
10830   effect(USE crx, USE lbl);
10831   predicate(false /* TODO: PPC port HB_Schedule*/);
10832   // Higher cost than `branchCon'.
10833   ins_cost(5*BRANCH_COST);
10834 
10835   // Actually size doesn't depend on alignment but on shortening.
10836   ins_variable_size_depending_on_alignment(true);
10837   // long variant.
10838   ins_short_branch(0);
10839 
10840   format %{ "B_FAR$cmp $crx, $lbl" %}
10841   size(8); // worst case
10842   ins_encode( enc_bc_short_far(crx, cmp, lbl) );
10843   ins_pipe(pipe_class_default);
10844 %}
10845 
10846 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
10847   match(CountedLoopEnd cmp crx);
10848   effect(USE labl);
10849   ins_cost(BRANCH_COST);
10850 
10851   // short variant.
10852   ins_short_branch(1);
10853 
10854   format %{ "B$cmp     $crx, $labl \t// counted loop end" %}
10855   size(4);
10856   ins_encode( enc_bc(crx, cmp, labl) );
10857   ins_pipe(pipe_class_default);
10858 %}
10859 
10860 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
10861   match(CountedLoopEnd cmp crx);
10862   effect(USE labl);
10863   predicate(!false /* TODO: PPC port HB_Schedule */);
10864   ins_cost(BRANCH_COST);
10865 
10866   // Long variant.
10867   ins_short_branch(0);
10868 
10869   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10870   size(8);
10871   ins_encode( enc_bc_far(crx, cmp, labl) );
10872   ins_pipe(pipe_class_default);
10873 %}
10874 
10875 // Conditional Branch used with Power6 scheduler (can be far or short).
10876 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
10877   match(CountedLoopEnd cmp crx);
10878   effect(USE labl);
10879   predicate(false /* TODO: PPC port HB_Schedule */);
10880   // Higher cost than `branchCon'.
10881   ins_cost(5*BRANCH_COST);
10882 
10883   // Actually size doesn't depend on alignment but on shortening.
10884   ins_variable_size_depending_on_alignment(true);
10885   // Long variant.
10886   ins_short_branch(0);
10887 
10888   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
10889   size(8); // worst case
10890   ins_encode( enc_bc_short_far(crx, cmp, labl) );
10891   ins_pipe(pipe_class_default);
10892 %}
10893 
10894 // ============================================================================
10895 // Java runtime operations, intrinsics and other complex operations.
10896 
10897 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10898 // array for an instance of the superklass. Set a hidden internal cache on a
10899 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10900 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10901 //
10902 // GL TODO: Improve this.
10903 // - result should not be a TEMP
10904 // - Add match rule as on sparc avoiding additional Cmp.
10905 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
10906                              iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
10907   match(Set result (PartialSubtypeCheck subklass superklass));
10908   effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
10909   ins_cost(DEFAULT_COST*10);
10910 
10911   format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
10912   ins_encode %{
10913     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10914     __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
10915                                      $tmp_klass$$Register, NULL, $result$$Register);
10916   %}
10917   ins_pipe(pipe_class_default);
10918 %}
10919 
10920 // inlined locking and unlocking
10921 
10922 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{
10923   match(Set crx (FastLock oop box));
10924   effect(TEMP tmp1, TEMP tmp2);
10925   predicate(!Compile::current()->use_rtm());
10926 
10927   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2" %}
10928   ins_encode %{
10929     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10930     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10931                                  $tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0,
10932                                  UseBiasedLocking && !UseOptoBiasInlining);
10933     // If locking was successfull, crx should indicate 'EQ'.
10934     // The compiler generates a branch to the runtime call to
10935     // _complete_monitor_locking_Java for the case where crx is 'NE'.
10936   %}
10937   ins_pipe(pipe_class_compare);
10938 %}
10939 
10940 // Separate version for TM. Use bound register for box to enable USE_KILL.
10941 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10942   match(Set crx (FastLock oop box));
10943   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
10944   predicate(Compile::current()->use_rtm());
10945 
10946   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
10947   ins_encode %{
10948     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10949     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10950                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10951                                  /*Biased Locking*/ false,
10952                                  _rtm_counters, _stack_rtm_counters,
10953                                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
10954                                  /*TM*/ true, ra_->C->profile_rtm());
10955     // If locking was successfull, crx should indicate 'EQ'.
10956     // The compiler generates a branch to the runtime call to
10957     // _complete_monitor_locking_Java for the case where crx is 'NE'.
10958   %}
10959   ins_pipe(pipe_class_compare);
10960 %}
10961 
10962 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10963   match(Set crx (FastUnlock oop box));
10964   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10965   predicate(!Compile::current()->use_rtm());
10966 
10967   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2" %}
10968   ins_encode %{
10969     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10970     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10971                                    $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10972                                    UseBiasedLocking && !UseOptoBiasInlining,
10973                                    false);
10974     // If unlocking was successfull, crx should indicate 'EQ'.
10975     // The compiler generates a branch to the runtime call to
10976     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10977   %}
10978   ins_pipe(pipe_class_compare);
10979 %}
10980 
10981 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
10982   match(Set crx (FastUnlock oop box));
10983   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
10984   predicate(Compile::current()->use_rtm());
10985 
10986   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2 (TM)" %}
10987   ins_encode %{
10988     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
10989     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
10990                                    $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
10991                                    /*Biased Locking*/ false, /*TM*/ true);
10992     // If unlocking was successfull, crx should indicate 'EQ'.
10993     // The compiler generates a branch to the runtime call to
10994     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
10995   %}
10996   ins_pipe(pipe_class_compare);
10997 %}
10998 
10999 // Align address.
11000 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
11001   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
11002 
11003   format %{ "ANDDI   $dst, $src, $mask \t// next aligned address" %}
11004   size(4);
11005   ins_encode %{
11006     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
11007     __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
11008   %}
11009   ins_pipe(pipe_class_default);
11010 %}
11011 
11012 // Array size computation.
11013 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
11014   match(Set dst (SubL (CastP2X end) (CastP2X start)));
11015 
11016   format %{ "SUB     $dst, $end, $start \t// array size in bytes" %}
11017   size(4);
11018   ins_encode %{
11019     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
11020     __ subf($dst$$Register, $start$$Register, $end$$Register);
11021   %}
11022   ins_pipe(pipe_class_default);
11023 %}
11024 
11025 // Clear-array with dynamic array-size.
11026 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
11027   match(Set dummy (ClearArray cnt base));
11028   effect(USE_KILL cnt, USE_KILL base, KILL ctr);
11029   ins_cost(MEMORY_REF_COST);
11030 
11031   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11032 
11033   format %{ "ClearArray $cnt, $base" %}
11034   ins_encode %{
11035     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11036     __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0
11037   %}
11038   ins_pipe(pipe_class_default);
11039 %}
11040 
11041 instruct string_compareL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11042                          iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11043   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11044   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11045   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11046   ins_cost(300);
11047   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11048   ins_encode %{
11049     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11050     __ string_compare($str1$$Register, $str2$$Register,
11051                       $cnt1$$Register, $cnt2$$Register,
11052                       $tmp$$Register,
11053                       $result$$Register, StrIntrinsicNode::LL);
11054   %}
11055   ins_pipe(pipe_class_default);
11056 %}
11057 
11058 instruct string_compareU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11059                          iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11060   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11061   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11062   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11063   ins_cost(300);
11064   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11065   ins_encode %{
11066     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11067     __ string_compare($str1$$Register, $str2$$Register,
11068                       $cnt1$$Register, $cnt2$$Register,
11069                       $tmp$$Register,
11070                       $result$$Register, StrIntrinsicNode::UU);
11071   %}
11072   ins_pipe(pipe_class_default);
11073 %}
11074 
11075 instruct string_compareLU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11076                           iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11077   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11078   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11079   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11080   ins_cost(300);
11081   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11082   ins_encode %{
11083     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11084     __ string_compare($str1$$Register, $str2$$Register,
11085                       $cnt1$$Register, $cnt2$$Register,
11086                       $tmp$$Register,
11087                       $result$$Register, StrIntrinsicNode::LU);
11088   %}
11089   ins_pipe(pipe_class_default);
11090 %}
11091 
11092 instruct string_compareUL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11093                           iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11094   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11095   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11096   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
11097   ins_cost(300);
11098   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
11099   ins_encode %{
11100     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11101     __ string_compare($str2$$Register, $str1$$Register,
11102                       $cnt2$$Register, $cnt1$$Register,
11103                       $tmp$$Register,
11104                       $result$$Register, StrIntrinsicNode::UL);
11105   %}
11106   ins_pipe(pipe_class_default);
11107 %}
11108 
11109 instruct string_equalsL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
11110                         iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11111   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
11112   match(Set result (StrEquals (Binary str1 str2) cnt));
11113   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
11114   ins_cost(300);
11115   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
11116   ins_encode %{
11117     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11118     __ array_equals(false, $str1$$Register, $str2$$Register,
11119                     $cnt$$Register, $tmp$$Register,
11120                     $result$$Register, true /* byte */);
11121   %}
11122   ins_pipe(pipe_class_default);
11123 %}
11124 
11125 instruct string_equalsU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
11126                         iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
11127   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
11128   match(Set result (StrEquals (Binary str1 str2) cnt));
11129   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
11130   ins_cost(300);
11131   format %{ "String Equals char[]  $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
11132   ins_encode %{
11133     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11134     __ array_equals(false, $str1$$Register, $str2$$Register,
11135                     $cnt$$Register, $tmp$$Register,
11136                     $result$$Register, false /* byte */);
11137   %}
11138   ins_pipe(pipe_class_default);
11139 %}
11140 
11141 instruct array_equalsB(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
11142                        iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
11143   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11144   match(Set result (AryEq ary1 ary2));
11145   effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
11146   ins_cost(300);
11147   format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
11148   ins_encode %{
11149     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11150     __ array_equals(true, $ary1$$Register, $ary2$$Register,
11151                     $tmp1$$Register, $tmp2$$Register,
11152                     $result$$Register, true /* byte */);
11153   %}
11154   ins_pipe(pipe_class_default);
11155 %}
11156 
11157 instruct array_equalsC(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
11158                        iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
11159   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11160   match(Set result (AryEq ary1 ary2));
11161   effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
11162   ins_cost(300);
11163   format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
11164   ins_encode %{
11165     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11166     __ array_equals(true, $ary1$$Register, $ary2$$Register,
11167                     $tmp1$$Register, $tmp2$$Register,
11168                     $result$$Register, false /* byte */);
11169   %}
11170   ins_pipe(pipe_class_default);
11171 %}
11172 
11173 instruct indexOf_imm1_char_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11174                              immP needleImm, immL offsetImm, immI_1 needlecntImm,
11175                              iRegIdst tmp1, iRegIdst tmp2,
11176                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11177   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11178   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11179   // Required for EA: check if it is still a type_array.
11180   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11181   ins_cost(150);
11182 
11183   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11184             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11185 
11186   ins_encode %{
11187     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11188     immPOper *needleOper = (immPOper *)$needleImm;
11189     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11190     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
11191     jchar chr;
11192 #ifdef VM_LITTLE_ENDIAN
11193     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11194            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11195 #else
11196     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11197            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11198 #endif
11199     __ string_indexof_char($result$$Register,
11200                            $haystack$$Register, $haycnt$$Register,
11201                            R0, chr,
11202                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11203   %}
11204   ins_pipe(pipe_class_compare);
11205 %}
11206 
11207 instruct indexOf_imm1_char_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11208                              immP needleImm, immL offsetImm, immI_1 needlecntImm,
11209                              iRegIdst tmp1, iRegIdst tmp2,
11210                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11211   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11212   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11213   // Required for EA: check if it is still a type_array.
11214   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11215   ins_cost(150);
11216 
11217   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11218             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11219 
11220   ins_encode %{
11221     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11222     immPOper *needleOper = (immPOper *)$needleImm;
11223     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11224     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
11225     jchar chr = (jchar)needle_values->element_value(0).as_byte();
11226     __ string_indexof_char($result$$Register,
11227                            $haystack$$Register, $haycnt$$Register,
11228                            R0, chr,
11229                            $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
11230   %}
11231   ins_pipe(pipe_class_compare);
11232 %}
11233 
11234 instruct indexOf_imm1_char_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11235                               immP needleImm, immL offsetImm, immI_1 needlecntImm,
11236                               iRegIdst tmp1, iRegIdst tmp2,
11237                               flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11238   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11239   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11240   // Required for EA: check if it is still a type_array.
11241   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11242   ins_cost(150);
11243 
11244   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11245             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11246 
11247   ins_encode %{
11248     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11249     immPOper *needleOper = (immPOper *)$needleImm;
11250     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11251     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
11252     jchar chr = (jchar)needle_values->element_value(0).as_byte();
11253     __ string_indexof_char($result$$Register,
11254                            $haystack$$Register, $haycnt$$Register,
11255                            R0, chr,
11256                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11257   %}
11258   ins_pipe(pipe_class_compare);
11259 %}
11260 
11261 instruct indexOf_imm1_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11262                         rscratch2RegP needle, immI_1 needlecntImm,
11263                         iRegIdst tmp1, iRegIdst tmp2,
11264                         flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11265   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11266   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11267   // Required for EA: check if it is still a type_array.
11268   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
11269             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11270             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11271   ins_cost(180);
11272 
11273   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11274             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11275   ins_encode %{
11276     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11277     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11278     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11279     guarantee(needle_values, "sanity");
11280     jchar chr;
11281 #ifdef VM_LITTLE_ENDIAN
11282     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11283            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11284 #else
11285     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11286            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11287 #endif
11288     __ string_indexof_char($result$$Register,
11289                            $haystack$$Register, $haycnt$$Register,
11290                            R0, chr,
11291                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11292   %}
11293   ins_pipe(pipe_class_compare);
11294 %}
11295 
11296 instruct indexOf_imm1_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11297                         rscratch2RegP needle, immI_1 needlecntImm,
11298                         iRegIdst tmp1, iRegIdst tmp2,
11299                         flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11300   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11301   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11302   // Required for EA: check if it is still a type_array.
11303   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
11304             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11305             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11306   ins_cost(180);
11307 
11308   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11309             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11310   ins_encode %{
11311     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11312     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11313     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11314     guarantee(needle_values, "sanity");
11315     jchar chr = (jchar)needle_values->element_value(0).as_byte();
11316     __ string_indexof_char($result$$Register,
11317                            $haystack$$Register, $haycnt$$Register,
11318                            R0, chr,
11319                            $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
11320   %}
11321   ins_pipe(pipe_class_compare);
11322 %}
11323 
11324 instruct indexOf_imm1_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11325                          rscratch2RegP needle, immI_1 needlecntImm,
11326                          iRegIdst tmp1, iRegIdst tmp2,
11327                          flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11328   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11329   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11330   // Required for EA: check if it is still a type_array.
11331   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
11332             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11333             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11334   ins_cost(180);
11335 
11336   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11337             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11338   ins_encode %{
11339     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11340     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11341     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11342     guarantee(needle_values, "sanity");
11343     jchar chr = (jchar)needle_values->element_value(0).as_byte();
11344     __ string_indexof_char($result$$Register,
11345                            $haystack$$Register, $haycnt$$Register,
11346                            R0, chr,
11347                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11348   %}
11349   ins_pipe(pipe_class_compare);
11350 %}
11351 
11352 instruct indexOfChar_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11353                        iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
11354                        flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11355   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
11356   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11357   predicate(CompactStrings);
11358   ins_cost(180);
11359 
11360   format %{ "String IndexOfChar $haystack[0..$haycnt], $ch"
11361             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11362   ins_encode %{
11363     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11364     __ string_indexof_char($result$$Register,
11365                            $haystack$$Register, $haycnt$$Register,
11366                            $ch$$Register, 0 /* this is not used if the character is already in a register */,
11367                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
11368   %}
11369   ins_pipe(pipe_class_compare);
11370 %}
11371 
11372 instruct indexOf_imm_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11373                        iRegPsrc needle, uimmI15 needlecntImm,
11374                        iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11375                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11376   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11377   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11378          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11379   // Required for EA: check if it is still a type_array.
11380   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
11381             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11382             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11383   ins_cost(250);
11384 
11385   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11386             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11387   ins_encode %{
11388     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11389     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11390     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11391 
11392     __ string_indexof($result$$Register,
11393                       $haystack$$Register, $haycnt$$Register,
11394                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11395                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
11396   %}
11397   ins_pipe(pipe_class_compare);
11398 %}
11399 
11400 instruct indexOf_imm_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11401                        iRegPsrc needle, uimmI15 needlecntImm,
11402                        iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11403                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11404   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11405   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11406          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11407   // Required for EA: check if it is still a type_array.
11408   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
11409             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11410             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11411   ins_cost(250);
11412 
11413   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11414             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11415   ins_encode %{
11416     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11417     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11418     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11419 
11420     __ string_indexof($result$$Register,
11421                       $haystack$$Register, $haycnt$$Register,
11422                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11423                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
11424   %}
11425   ins_pipe(pipe_class_compare);
11426 %}
11427 
11428 instruct indexOf_imm_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11429                         iRegPsrc needle, uimmI15 needlecntImm,
11430                         iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11431                         flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11432   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11433   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11434          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11435   // Required for EA: check if it is still a type_array.
11436   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
11437             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11438             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11439   ins_cost(250);
11440 
11441   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11442             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11443   ins_encode %{
11444     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11445     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11446     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11447 
11448     __ string_indexof($result$$Register,
11449                       $haystack$$Register, $haycnt$$Register,
11450                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11451                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
11452   %}
11453   ins_pipe(pipe_class_compare);
11454 %}
11455 
11456 instruct indexOf_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11457                    iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11458                    flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11459   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11460   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11461          TEMP_DEF result,
11462          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11463   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
11464   ins_cost(300);
11465 
11466   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11467              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11468   ins_encode %{
11469     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11470     __ string_indexof($result$$Register,
11471                       $haystack$$Register, $haycnt$$Register,
11472                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
11473                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
11474   %}
11475   ins_pipe(pipe_class_compare);
11476 %}
11477 
11478 instruct indexOf_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11479                    iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11480                    flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11481   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11482   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11483          TEMP_DEF result,
11484          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11485   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
11486   ins_cost(300);
11487 
11488   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11489              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11490   ins_encode %{
11491     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11492     __ string_indexof($result$$Register,
11493                       $haystack$$Register, $haycnt$$Register,
11494                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
11495                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
11496   %}
11497   ins_pipe(pipe_class_compare);
11498 %}
11499 
11500 instruct indexOf_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11501                     iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11502                     flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11503   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11504   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11505          TEMP_DEF result,
11506          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11507   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
11508   ins_cost(300);
11509 
11510   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11511              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11512   ins_encode %{
11513     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11514     __ string_indexof($result$$Register,
11515                       $haystack$$Register, $haycnt$$Register,
11516                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
11517                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
11518   %}
11519   ins_pipe(pipe_class_compare);
11520 %}
11521 
11522 // char[] to byte[] compression
11523 instruct string_compress(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
11524                          iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11525   match(Set result (StrCompressedCopy src (Binary dst len)));
11526   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11527          USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11528   ins_cost(300);
11529   format %{ "String Compress $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11530   ins_encode %{
11531     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11532     Label Lskip, Ldone;
11533     __ li($result$$Register, 0);
11534     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
11535                           $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Ldone);
11536     __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
11537     __ beq(CCR0, Lskip);
11538     __ string_compress($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register, Ldone);
11539     __ bind(Lskip);
11540     __ mr($result$$Register, $len$$Register);
11541     __ bind(Ldone);
11542   %}
11543   ins_pipe(pipe_class_default);
11544 %}
11545 
11546 // byte[] to char[] inflation
11547 instruct string_inflate(Universe dummy, rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegLdst tmp1,
11548                         iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11549   match(Set dummy (StrInflatedCopy src (Binary dst len)));
11550   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11551   ins_cost(300);
11552   format %{ "String Inflate $src,$dst,$len \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11553   ins_encode %{
11554     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11555     Label Ldone;
11556     __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
11557                          $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11558     __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
11559     __ beq(CCR0, Ldone);
11560     __ string_inflate($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register);
11561     __ bind(Ldone);
11562   %}
11563   ins_pipe(pipe_class_default);
11564 %}
11565 
11566 // StringCoding.java intrinsics
11567 instruct has_negatives(rarg1RegP ary1, iRegIsrc len, iRegIdst result, iRegLdst tmp1, iRegLdst tmp2,
11568                        regCTR ctr, flagsRegCR0 cr0)
11569 %{
11570   match(Set result (HasNegatives ary1 len));
11571   effect(TEMP_DEF result, USE_KILL ary1, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0);
11572   ins_cost(300);
11573   format %{ "has negatives byte[] $ary1,$len -> $result \t// KILL $tmp1, $tmp2" %}
11574   ins_encode %{
11575     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11576     __ has_negatives($ary1$$Register, $len$$Register, $result$$Register,
11577                      $tmp1$$Register, $tmp2$$Register);
11578   %}
11579   ins_pipe(pipe_class_default);
11580 %}
11581 
11582 // encode char[] to byte[] in ISO_8859_1
11583 instruct encode_iso_array(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
11584                           iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
11585   match(Set result (EncodeISOArray src (Binary dst len)));
11586   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11587          USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
11588   ins_cost(300);
11589   format %{ "Encode array $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11590   ins_encode %{
11591     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11592     Label Lslow, Lfailure1, Lfailure2, Ldone;
11593     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
11594                           $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Lfailure1);
11595     __ rldicl_($result$$Register, $len$$Register, 0, 64-3); // Remaining characters.
11596     __ beq(CCR0, Ldone);
11597     __ bind(Lslow);
11598     __ string_compress($src$$Register, $dst$$Register, $result$$Register, $tmp2$$Register, Lfailure2);
11599     __ li($result$$Register, 0);
11600     __ b(Ldone);
11601 
11602     __ bind(Lfailure1);
11603     __ mr($result$$Register, $len$$Register);
11604     __ mfctr($tmp1$$Register);
11605     __ rldimi_($result$$Register, $tmp1$$Register, 3, 0); // Remaining characters.
11606     __ beq(CCR0, Ldone);
11607     __ b(Lslow);
11608 
11609     __ bind(Lfailure2);
11610     __ mfctr($result$$Register); // Remaining characters.
11611 
11612     __ bind(Ldone);
11613     __ subf($result$$Register, $result$$Register, $len$$Register);
11614   %}
11615   ins_pipe(pipe_class_default);
11616 %}
11617 
11618 
11619 // String_IndexOf for needle of length 1.
11620 //
11621 // Match needle into immediate operands: no loadConP node needed. Saves one
11622 // register and two instructions over string_indexOf_imm1Node.
11623 //
11624 // Assumes register result differs from all input registers.
11625 //
11626 // Preserves registers haystack, haycnt
11627 // Kills     registers tmp1, tmp2
11628 // Defines   registers result
11629 //
11630 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11631 //
11632 // Unfortunately this does not match too often. In many situations the AddP is used
11633 // by several nodes, even several StrIndexOf nodes, breaking the match tree.
11634 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11635                                   immP needleImm, immL offsetImm, immI_1 needlecntImm,
11636                                   iRegIdst tmp1, iRegIdst tmp2,
11637                                   flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11638   predicate(SpecialStringIndexOf && !CompactStrings);  // type check implicit by parameter type, See Matcher::match_rule_supported
11639   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
11640 
11641   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11642 
11643   ins_cost(150);
11644   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
11645             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11646 
11647   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted
11648   ins_encode %{
11649     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11650     immPOper *needleOper = (immPOper *)$needleImm;
11651     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
11652     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
11653     jchar chr;
11654     if (java_lang_String::has_coder_field()) {
11655       // New compact strings byte array strings
11656 #ifdef VM_LITTLE_ENDIAN
11657     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11658            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11659 #else
11660     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11661            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11662 #endif
11663     } else {
11664       // Old char array strings
11665       chr = needle_values->char_at(0);
11666     }
11667     __ string_indexof_1($result$$Register,
11668                         $haystack$$Register, $haycnt$$Register,
11669                         R0, chr,
11670                         $tmp1$$Register, $tmp2$$Register);
11671   %}
11672   ins_pipe(pipe_class_compare);
11673 %}
11674 
11675 // String_IndexOf for needle of length 1.
11676 //
11677 // Special case requires less registers and emits less instructions.
11678 //
11679 // Assumes register result differs from all input registers.
11680 //
11681 // Preserves registers haystack, haycnt
11682 // Kills     registers tmp1, tmp2, needle
11683 // Defines   registers result
11684 //
11685 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11686 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11687                              rscratch2RegP needle, immI_1 needlecntImm,
11688                              iRegIdst tmp1, iRegIdst tmp2,
11689                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11690   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11691   effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result,
11692          TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11693   // Required for EA: check if it is still a type_array.
11694   predicate(SpecialStringIndexOf && !CompactStrings &&
11695             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11696             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11697   ins_cost(180);
11698 
11699   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11700 
11701   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11702             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
11703   ins_encode %{
11704     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11705     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11706     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11707     guarantee(needle_values, "sanity");
11708     jchar chr;
11709     if (java_lang_String::has_coder_field()) {
11710       // New compact strings byte array strings
11711 #ifdef VM_LITTLE_ENDIAN
11712     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
11713            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
11714 #else
11715     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
11716            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
11717 #endif
11718     } else {
11719       // Old char array strings
11720       chr = needle_values->char_at(0);
11721     }
11722     __ string_indexof_1($result$$Register,
11723                         $haystack$$Register, $haycnt$$Register,
11724                         R0, chr,
11725                         $tmp1$$Register, $tmp2$$Register);
11726   %}
11727   ins_pipe(pipe_class_compare);
11728 %}
11729 
11730 // String_IndexOfChar
11731 //
11732 // Assumes register result differs from all input registers.
11733 //
11734 // Preserves registers haystack, haycnt
11735 // Kills     registers tmp1, tmp2
11736 // Defines   registers result
11737 //
11738 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11739 instruct string_indexOfChar(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
11740                             iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
11741                             flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
11742   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
11743   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
11744   predicate(SpecialStringIndexOf && !CompactStrings);
11745   ins_cost(180);
11746 
11747   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11748 
11749   format %{ "String IndexOfChar $haystack[0..$haycnt], $ch"
11750             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
11751   ins_encode %{
11752     __ string_indexof_1($result$$Register,
11753                         $haystack$$Register, $haycnt$$Register,
11754                         $ch$$Register, 0 /* this is not used if the character is already in a register */,
11755                         $tmp1$$Register, $tmp2$$Register);
11756   %}
11757   ins_pipe(pipe_class_compare);
11758 %}
11759 
11760 // String_IndexOf.
11761 //
11762 // Length of needle as immediate. This saves instruction loading constant needle
11763 // length.
11764 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle
11765 // completely or do it in vector instruction. This should save registers for
11766 // needlecnt and needle.
11767 //
11768 // Assumes register result differs from all input registers.
11769 // Overwrites haycnt, needlecnt.
11770 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11771 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
11772                             iRegPsrc needle, uimmI15 needlecntImm,
11773                             iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
11774                             flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11775   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
11776   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
11777          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11778   // Required for EA: check if it is still a type_array.
11779   predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
11780             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
11781   ins_cost(250);
11782 
11783   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11784 
11785   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
11786             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
11787   ins_encode %{
11788     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11789     Node *ndl = in(operand_index($needle));  // The node that defines needle.
11790     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
11791 
11792     __ string_indexof($result$$Register,
11793                       $haystack$$Register, $haycnt$$Register,
11794                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
11795                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11796   %}
11797   ins_pipe(pipe_class_compare);
11798 %}
11799 
11800 // StrIndexOf node.
11801 //
11802 // Assumes register result differs from all input registers.
11803 // Overwrites haycnt, needlecnt.
11804 // Use dst register classes if register gets killed, as it is the case for tmp registers!
11805 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
11806                         iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
11807                         flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11808   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
11809   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
11810          TEMP_DEF result,
11811          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11812   predicate(SpecialStringIndexOf && !CompactStrings);  // See Matcher::match_rule_supported.
11813   ins_cost(300);
11814 
11815   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11816 
11817   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
11818              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
11819   ins_encode %{
11820     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11821     __ string_indexof($result$$Register,
11822                       $haystack$$Register, $haycnt$$Register,
11823                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
11824                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register);
11825   %}
11826   ins_pipe(pipe_class_compare);
11827 %}
11828 
11829 // String equals with immediate.
11830 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result,
11831                            iRegPdst tmp1, iRegPdst tmp2,
11832                            flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{
11833   match(Set result (StrEquals (Binary str1 str2) cntImm));
11834   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2,
11835          KILL cr0, KILL cr6, KILL ctr);
11836   predicate(SpecialStringEquals && !CompactStrings);  // See Matcher::match_rule_supported.
11837   ins_cost(250);
11838 
11839   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11840 
11841   format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)"
11842             " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %}
11843   ins_encode %{
11844     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11845     __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant,
11846                              $result$$Register, $tmp1$$Register, $tmp2$$Register);
11847   %}
11848   ins_pipe(pipe_class_compare);
11849 %}
11850 
11851 // String equals.
11852 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11853 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result,
11854                        iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5,
11855                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
11856   match(Set result (StrEquals (Binary str1 str2) cnt));
11857   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
11858          KILL cr0, KILL cr1, KILL cr6, KILL ctr);
11859   predicate(SpecialStringEquals && !CompactStrings);  // See Matcher::match_rule_supported.
11860   ins_cost(300);
11861 
11862   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11863 
11864   format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result"
11865             " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
11866   ins_encode %{
11867     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11868     __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register,
11869                           $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
11870   %}
11871   ins_pipe(pipe_class_compare);
11872 %}
11873 
11874 // String compare.
11875 // Char[] pointers are passed in.
11876 // Use dst register classes if register gets killed, as it is the case for TEMP operands!
11877 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
11878                         iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{
11879   predicate(!CompactStrings);
11880   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11881   effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr);
11882   ins_cost(300);
11883 
11884   ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted.
11885 
11886   format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result"
11887             " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %}
11888   ins_encode %{
11889     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11890     __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register,
11891                       $result$$Register, $tmp$$Register);
11892   %}
11893   ins_pipe(pipe_class_compare);
11894 %}
11895 
11896 //---------- Min/Max Instructions ---------------------------------------------
11897 
11898 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11899   match(Set dst (MinI src1 src2));
11900   ins_cost(DEFAULT_COST*6);
11901 
11902   expand %{
11903     iRegLdst src1s;
11904     iRegLdst src2s;
11905     iRegLdst diff;
11906     iRegLdst sm;
11907     iRegLdst doz; // difference or zero
11908     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11909     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11910     subL_reg_reg(diff, src2s, src1s);
11911     // Need to consider >=33 bit result, therefore we need signmaskL.
11912     signmask64L_regL(sm, diff);
11913     andL_reg_reg(doz, diff, sm); // <=0
11914     addI_regL_regL(dst, doz, src1s);
11915   %}
11916 %}
11917 
11918 instruct minI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
11919   match(Set dst (MinI src1 src2));
11920   effect(KILL cr0);
11921   predicate(VM_Version::has_isel());
11922   ins_cost(DEFAULT_COST*2);
11923 
11924   ins_encode %{
11925     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11926     __ cmpw(CCR0, $src1$$Register, $src2$$Register);
11927     __ isel($dst$$Register, CCR0, Assembler::less, /*invert*/false, $src1$$Register, $src2$$Register);
11928   %}
11929   ins_pipe(pipe_class_default);
11930 %}
11931 
11932 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
11933   match(Set dst (MaxI src1 src2));
11934   ins_cost(DEFAULT_COST*6);
11935 
11936   expand %{
11937     iRegLdst src1s;
11938     iRegLdst src2s;
11939     iRegLdst diff;
11940     iRegLdst sm;
11941     iRegLdst doz; // difference or zero
11942     convI2L_reg(src1s, src1); // Ensure proper sign extension.
11943     convI2L_reg(src2s, src2); // Ensure proper sign extension.
11944     subL_reg_reg(diff, src2s, src1s);
11945     // Need to consider >=33 bit result, therefore we need signmaskL.
11946     signmask64L_regL(sm, diff);
11947     andcL_reg_reg(doz, diff, sm); // >=0
11948     addI_regL_regL(dst, doz, src1s);
11949   %}
11950 %}
11951 
11952 instruct maxI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
11953   match(Set dst (MaxI src1 src2));
11954   effect(KILL cr0);
11955   predicate(VM_Version::has_isel());
11956   ins_cost(DEFAULT_COST*2);
11957 
11958   ins_encode %{
11959     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
11960     __ cmpw(CCR0, $src1$$Register, $src2$$Register);
11961     __ isel($dst$$Register, CCR0, Assembler::greater, /*invert*/false, $src1$$Register, $src2$$Register);
11962   %}
11963   ins_pipe(pipe_class_default);
11964 %}
11965 
11966 //---------- Population Count Instructions ------------------------------------
11967 
11968 // Popcnt for Power7.
11969 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
11970   match(Set dst (PopCountI src));
11971   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11972   ins_cost(DEFAULT_COST);
11973 
11974   format %{ "POPCNTW $dst, $src" %}
11975   size(4);
11976   ins_encode %{
11977     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11978     __ popcntw($dst$$Register, $src$$Register);
11979   %}
11980   ins_pipe(pipe_class_default);
11981 %}
11982 
11983 // Popcnt for Power7.
11984 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
11985   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
11986   match(Set dst (PopCountL src));
11987   ins_cost(DEFAULT_COST);
11988 
11989   format %{ "POPCNTD $dst, $src" %}
11990   size(4);
11991   ins_encode %{
11992     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
11993     __ popcntd($dst$$Register, $src$$Register);
11994   %}
11995   ins_pipe(pipe_class_default);
11996 %}
11997 
11998 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
11999   match(Set dst (CountLeadingZerosI src));
12000   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
12001   ins_cost(DEFAULT_COST);
12002 
12003   format %{ "CNTLZW  $dst, $src" %}
12004   size(4);
12005   ins_encode %{
12006     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
12007     __ cntlzw($dst$$Register, $src$$Register);
12008   %}
12009   ins_pipe(pipe_class_default);
12010 %}
12011 
12012 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
12013   match(Set dst (CountLeadingZerosL src));
12014   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
12015   ins_cost(DEFAULT_COST);
12016 
12017   format %{ "CNTLZD  $dst, $src" %}
12018   size(4);
12019   ins_encode %{
12020     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
12021     __ cntlzd($dst$$Register, $src$$Register);
12022   %}
12023   ins_pipe(pipe_class_default);
12024 %}
12025 
12026 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
12027   // no match-rule, false predicate
12028   effect(DEF dst, USE src);
12029   predicate(false);
12030 
12031   format %{ "CNTLZD  $dst, $src" %}
12032   size(4);
12033   ins_encode %{
12034     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
12035     __ cntlzd($dst$$Register, $src$$Register);
12036   %}
12037   ins_pipe(pipe_class_default);
12038 %}
12039 
12040 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
12041   match(Set dst (CountTrailingZerosI src));
12042   predicate(UseCountLeadingZerosInstructionsPPC64);
12043   ins_cost(DEFAULT_COST);
12044 
12045   expand %{
12046     immI16 imm1 %{ (int)-1 %}
12047     immI16 imm2 %{ (int)32 %}
12048     immI_minus1 m1 %{ -1 %}
12049     iRegIdst tmpI1;
12050     iRegIdst tmpI2;
12051     iRegIdst tmpI3;
12052     addI_reg_imm16(tmpI1, src, imm1);
12053     andcI_reg_reg(tmpI2, src, m1, tmpI1);
12054     countLeadingZerosI(tmpI3, tmpI2);
12055     subI_imm16_reg(dst, imm2, tmpI3);
12056   %}
12057 %}
12058 
12059 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
12060   match(Set dst (CountTrailingZerosL src));
12061   predicate(UseCountLeadingZerosInstructionsPPC64);
12062   ins_cost(DEFAULT_COST);
12063 
12064   expand %{
12065     immL16 imm1 %{ (long)-1 %}
12066     immI16 imm2 %{ (int)64 %}
12067     iRegLdst tmpL1;
12068     iRegLdst tmpL2;
12069     iRegIdst tmpL3;
12070     addL_reg_imm16(tmpL1, src, imm1);
12071     andcL_reg_reg(tmpL2, tmpL1, src);
12072     countLeadingZerosL(tmpL3, tmpL2);
12073     subI_imm16_reg(dst, imm2, tmpL3);
12074  %}
12075 %}
12076 
12077 // Expand nodes for byte_reverse_int.
12078 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
12079   effect(DEF dst, USE src, USE pos, USE shift);
12080   predicate(false);
12081 
12082   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
12083   size(4);
12084   ins_encode %{
12085     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
12086     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
12087   %}
12088   ins_pipe(pipe_class_default);
12089 %}
12090 
12091 // As insrwi_a, but with USE_DEF.
12092 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
12093   effect(USE_DEF dst, USE src, USE pos, USE shift);
12094   predicate(false);
12095 
12096   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
12097   size(4);
12098   ins_encode %{
12099     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
12100     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
12101   %}
12102   ins_pipe(pipe_class_default);
12103 %}
12104 
12105 // Just slightly faster than java implementation.
12106 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
12107   match(Set dst (ReverseBytesI src));
12108   predicate(UseCountLeadingZerosInstructionsPPC64);
12109   ins_cost(DEFAULT_COST);
12110 
12111   expand %{
12112     immI16 imm24 %{ (int) 24 %}
12113     immI16 imm16 %{ (int) 16 %}
12114     immI16  imm8 %{ (int)  8 %}
12115     immI16  imm4 %{ (int)  4 %}
12116     immI16  imm0 %{ (int)  0 %}
12117     iRegLdst tmpI1;
12118     iRegLdst tmpI2;
12119     iRegLdst tmpI3;
12120 
12121     urShiftI_reg_imm(tmpI1, src, imm24);
12122     insrwi_a(dst, tmpI1, imm24, imm8);
12123     urShiftI_reg_imm(tmpI2, src, imm16);
12124     insrwi(dst, tmpI2, imm8, imm16);
12125     urShiftI_reg_imm(tmpI3, src, imm8);
12126     insrwi(dst, tmpI3, imm8, imm8);
12127     insrwi(dst, src, imm0, imm8);
12128   %}
12129 %}
12130 
12131 //---------- Replicate Vector Instructions ------------------------------------
12132 
12133 // Insrdi does replicate if src == dst.
12134 instruct repl32(iRegLdst dst) %{
12135   predicate(false);
12136   effect(USE_DEF dst);
12137 
12138   format %{ "INSRDI  $dst, #0, $dst, #32 \t// replicate" %}
12139   size(4);
12140   ins_encode %{
12141     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
12142     __ insrdi($dst$$Register, $dst$$Register, 32, 0);
12143   %}
12144   ins_pipe(pipe_class_default);
12145 %}
12146 
12147 // Insrdi does replicate if src == dst.
12148 instruct repl48(iRegLdst dst) %{
12149   predicate(false);
12150   effect(USE_DEF dst);
12151 
12152   format %{ "INSRDI  $dst, #0, $dst, #48 \t// replicate" %}
12153   size(4);
12154   ins_encode %{
12155     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
12156     __ insrdi($dst$$Register, $dst$$Register, 48, 0);
12157   %}
12158   ins_pipe(pipe_class_default);
12159 %}
12160 
12161 // Insrdi does replicate if src == dst.
12162 instruct repl56(iRegLdst dst) %{
12163   predicate(false);
12164   effect(USE_DEF dst);
12165 
12166   format %{ "INSRDI  $dst, #0, $dst, #56 \t// replicate" %}
12167   size(4);
12168   ins_encode %{
12169     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
12170     __ insrdi($dst$$Register, $dst$$Register, 56, 0);
12171   %}
12172   ins_pipe(pipe_class_default);
12173 %}
12174 
12175 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12176   match(Set dst (ReplicateB src));
12177   predicate(n->as_Vector()->length() == 8);
12178   expand %{
12179     moveReg(dst, src);
12180     repl56(dst);
12181     repl48(dst);
12182     repl32(dst);
12183   %}
12184 %}
12185 
12186 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
12187   match(Set dst (ReplicateB zero));
12188   predicate(n->as_Vector()->length() == 8);
12189   format %{ "LI      $dst, #0 \t// replicate8B" %}
12190   size(4);
12191   ins_encode %{
12192     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12193     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12194   %}
12195   ins_pipe(pipe_class_default);
12196 %}
12197 
12198 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
12199   match(Set dst (ReplicateB src));
12200   predicate(n->as_Vector()->length() == 8);
12201   format %{ "LI      $dst, #-1 \t// replicate8B" %}
12202   size(4);
12203   ins_encode %{
12204     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12205     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12206   %}
12207   ins_pipe(pipe_class_default);
12208 %}
12209 
12210 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12211   match(Set dst (ReplicateS src));
12212   predicate(n->as_Vector()->length() == 4);
12213   expand %{
12214     moveReg(dst, src);
12215     repl48(dst);
12216     repl32(dst);
12217   %}
12218 %}
12219 
12220 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
12221   match(Set dst (ReplicateS zero));
12222   predicate(n->as_Vector()->length() == 4);
12223   format %{ "LI      $dst, #0 \t// replicate4C" %}
12224   size(4);
12225   ins_encode %{
12226     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12227     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12228   %}
12229   ins_pipe(pipe_class_default);
12230 %}
12231 
12232 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
12233   match(Set dst (ReplicateS src));
12234   predicate(n->as_Vector()->length() == 4);
12235   format %{ "LI      $dst, -1 \t// replicate4C" %}
12236   size(4);
12237   ins_encode %{
12238     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12239     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12240   %}
12241   ins_pipe(pipe_class_default);
12242 %}
12243 
12244 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
12245   match(Set dst (ReplicateI src));
12246   predicate(n->as_Vector()->length() == 2);
12247   ins_cost(2 * DEFAULT_COST);
12248   expand %{
12249     moveReg(dst, src);
12250     repl32(dst);
12251   %}
12252 %}
12253 
12254 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
12255   match(Set dst (ReplicateI zero));
12256   predicate(n->as_Vector()->length() == 2);
12257   format %{ "LI      $dst, #0 \t// replicate4C" %}
12258   size(4);
12259   ins_encode %{
12260     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12261     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
12262   %}
12263   ins_pipe(pipe_class_default);
12264 %}
12265 
12266 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
12267   match(Set dst (ReplicateI src));
12268   predicate(n->as_Vector()->length() == 2);
12269   format %{ "LI      $dst, -1 \t// replicate4C" %}
12270   size(4);
12271   ins_encode %{
12272     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12273     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
12274   %}
12275   ins_pipe(pipe_class_default);
12276 %}
12277 
12278 // Move float to int register via stack, replicate.
12279 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
12280   match(Set dst (ReplicateF src));
12281   predicate(n->as_Vector()->length() == 2);
12282   ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
12283   expand %{
12284     stackSlotL tmpS;
12285     iRegIdst tmpI;
12286     moveF2I_reg_stack(tmpS, src);   // Move float to stack.
12287     moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
12288     moveReg(dst, tmpI);             // Move int to long reg.
12289     repl32(dst);                    // Replicate bitpattern.
12290   %}
12291 %}
12292 
12293 // Replicate scalar constant to packed float values in Double register
12294 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
12295   match(Set dst (ReplicateF src));
12296   predicate(n->as_Vector()->length() == 2);
12297   ins_cost(5 * DEFAULT_COST);
12298 
12299   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
12300   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
12301 %}
12302 
12303 // Replicate scalar zero constant to packed float values in Double register
12304 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
12305   match(Set dst (ReplicateF zero));
12306   predicate(n->as_Vector()->length() == 2);
12307 
12308   format %{ "LI      $dst, #0 \t// replicate2F" %}
12309   ins_encode %{
12310     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
12311     __ li($dst$$Register, 0x0);
12312   %}
12313   ins_pipe(pipe_class_default);
12314 %}
12315 
12316 
12317 //----------Overflow Math Instructions-----------------------------------------
12318 
12319 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
12320 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
12321 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
12322 
12323 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
12324   match(Set cr0 (OverflowAddL op1 op2));
12325 
12326   format %{ "add_    $op1, $op2\t# overflow check long" %}
12327   ins_encode %{
12328     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12329     __ li(R0, 0);
12330     __ mtxer(R0); // clear XER.SO
12331     __ addo_(R0, $op1$$Register, $op2$$Register);
12332   %}
12333   ins_pipe(pipe_class_default);
12334 %}
12335 
12336 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
12337   match(Set cr0 (OverflowSubL op1 op2));
12338 
12339   format %{ "subfo_  R0, $op2, $op1\t# overflow check long" %}
12340   ins_encode %{
12341     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12342     __ li(R0, 0);
12343     __ mtxer(R0); // clear XER.SO
12344     __ subfo_(R0, $op2$$Register, $op1$$Register);
12345   %}
12346   ins_pipe(pipe_class_default);
12347 %}
12348 
12349 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
12350   match(Set cr0 (OverflowSubL zero op2));
12351 
12352   format %{ "nego_   R0, $op2\t# overflow check long" %}
12353   ins_encode %{
12354     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12355     __ li(R0, 0);
12356     __ mtxer(R0); // clear XER.SO
12357     __ nego_(R0, $op2$$Register);
12358   %}
12359   ins_pipe(pipe_class_default);
12360 %}
12361 
12362 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
12363   match(Set cr0 (OverflowMulL op1 op2));
12364 
12365   format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
12366   ins_encode %{
12367     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12368     __ li(R0, 0);
12369     __ mtxer(R0); // clear XER.SO
12370     __ mulldo_(R0, $op1$$Register, $op2$$Register);
12371   %}
12372   ins_pipe(pipe_class_default);
12373 %}
12374 
12375 
12376 // ============================================================================
12377 // Safepoint Instruction
12378 
12379 instruct safePoint_poll(iRegPdst poll) %{
12380   match(SafePoint poll);
12381   predicate(LoadPollAddressFromThread);
12382 
12383   // It caused problems to add the effect that r0 is killed, but this
12384   // effect no longer needs to be mentioned, since r0 is not contained
12385   // in a reg_class.
12386 
12387   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
12388   size(4);
12389   ins_encode( enc_poll(0x0, poll) );
12390   ins_pipe(pipe_class_default);
12391 %}
12392 
12393 // Safepoint without per-thread support. Load address of page to poll
12394 // as constant.
12395 // Rscratch2RegP is R12.
12396 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
12397 // a seperate node so that the oop map is at the right location.
12398 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
12399   match(SafePoint poll);
12400   predicate(!LoadPollAddressFromThread);
12401 
12402   // It caused problems to add the effect that r0 is killed, but this
12403   // effect no longer needs to be mentioned, since r0 is not contained
12404   // in a reg_class.
12405 
12406   format %{ "LD      R0, #0, R12 \t// Safepoint poll for GC" %}
12407   ins_encode( enc_poll(0x0, poll) );
12408   ins_pipe(pipe_class_default);
12409 %}
12410 
12411 // ============================================================================
12412 // Call Instructions
12413 
12414 // Call Java Static Instruction
12415 
12416 // Schedulable version of call static node.
12417 instruct CallStaticJavaDirect(method meth) %{
12418   match(CallStaticJava);
12419   effect(USE meth);
12420   ins_cost(CALL_COST);
12421 
12422   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
12423 
12424   format %{ "CALL,static $meth \t// ==> " %}
12425   size(4);
12426   ins_encode( enc_java_static_call(meth) );
12427   ins_pipe(pipe_class_call);
12428 %}
12429 
12430 // Call Java Dynamic Instruction
12431 
12432 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
12433 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
12434 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
12435 // The call destination must still be placed in the constant pool.
12436 instruct CallDynamicJavaDirectSched(method meth) %{
12437   match(CallDynamicJava); // To get all the data fields we need ...
12438   effect(USE meth);
12439   predicate(false);       // ... but never match.
12440 
12441   ins_field_load_ic_hi_node(loadConL_hiNode*);
12442   ins_field_load_ic_node(loadConLNode*);
12443   ins_num_consts(1 /* 1 patchable constant: call destination */);
12444 
12445   format %{ "BL        \t// dynamic $meth ==> " %}
12446   size(4);
12447   ins_encode( enc_java_dynamic_call_sched(meth) );
12448   ins_pipe(pipe_class_call);
12449 %}
12450 
12451 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
12452 // We use postalloc expanded calls if we use inline caches
12453 // and do not update method data.
12454 //
12455 // This instruction has two constants: inline cache (IC) and call destination.
12456 // Loading the inline cache will be postalloc expanded, thus leaving a call with
12457 // one constant.
12458 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
12459   match(CallDynamicJava);
12460   effect(USE meth);
12461   predicate(UseInlineCaches);
12462   ins_cost(CALL_COST);
12463 
12464   ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
12465 
12466   format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
12467   postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
12468 %}
12469 
12470 // Compound version of call dynamic java
12471 // We use postalloc expanded calls if we use inline caches
12472 // and do not update method data.
12473 instruct CallDynamicJavaDirect(method meth) %{
12474   match(CallDynamicJava);
12475   effect(USE meth);
12476   predicate(!UseInlineCaches);
12477   ins_cost(CALL_COST);
12478 
12479   // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
12480   ins_num_consts(4);
12481 
12482   format %{ "CALL,dynamic $meth \t// ==> " %}
12483   ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
12484   ins_pipe(pipe_class_call);
12485 %}
12486 
12487 // Call Runtime Instruction
12488 
12489 instruct CallRuntimeDirect(method meth) %{
12490   match(CallRuntime);
12491   effect(USE meth);
12492   ins_cost(CALL_COST);
12493 
12494   // Enc_java_to_runtime_call needs up to 3 constants: call target,
12495   // env for callee, C-toc.
12496   ins_num_consts(3);
12497 
12498   format %{ "CALL,runtime" %}
12499   ins_encode( enc_java_to_runtime_call(meth) );
12500   ins_pipe(pipe_class_call);
12501 %}
12502 
12503 // Call Leaf
12504 
12505 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
12506 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
12507   effect(DEF dst, USE src);
12508 
12509   ins_num_consts(1);
12510 
12511   format %{ "MTCTR   $src" %}
12512   size(4);
12513   ins_encode( enc_leaf_call_mtctr(src) );
12514   ins_pipe(pipe_class_default);
12515 %}
12516 
12517 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
12518 instruct CallLeafDirect(method meth) %{
12519   match(CallLeaf);   // To get the data all the data fields we need ...
12520   effect(USE meth);
12521   predicate(false);  // but never match.
12522 
12523   format %{ "BCTRL     \t// leaf call $meth ==> " %}
12524   size(4);
12525   ins_encode %{
12526     // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
12527     __ bctrl();
12528   %}
12529   ins_pipe(pipe_class_call);
12530 %}
12531 
12532 // postalloc expand of CallLeafDirect.
12533 // Load adress to call from TOC, then bl to it.
12534 instruct CallLeafDirect_Ex(method meth) %{
12535   match(CallLeaf);
12536   effect(USE meth);
12537   ins_cost(CALL_COST);
12538 
12539   // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
12540   // env for callee, C-toc.
12541   ins_num_consts(3);
12542 
12543   format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
12544   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
12545 %}
12546 
12547 // Call runtime without safepoint - same as CallLeaf.
12548 // postalloc expand of CallLeafNoFPDirect.
12549 // Load adress to call from TOC, then bl to it.
12550 instruct CallLeafNoFPDirect_Ex(method meth) %{
12551   match(CallLeafNoFP);
12552   effect(USE meth);
12553   ins_cost(CALL_COST);
12554 
12555   // Enc_java_to_runtime_call needs up to 3 constants: call target,
12556   // env for callee, C-toc.
12557   ins_num_consts(3);
12558 
12559   format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
12560   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
12561 %}
12562 
12563 // Tail Call; Jump from runtime stub to Java code.
12564 // Also known as an 'interprocedural jump'.
12565 // Target of jump will eventually return to caller.
12566 // TailJump below removes the return address.
12567 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
12568   match(TailCall jump_target method_oop);
12569   ins_cost(CALL_COST);
12570 
12571   format %{ "MTCTR   $jump_target \t// $method_oop holds method oop\n\t"
12572             "BCTR         \t// tail call" %}
12573   size(8);
12574   ins_encode %{
12575     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12576     __ mtctr($jump_target$$Register);
12577     __ bctr();
12578   %}
12579   ins_pipe(pipe_class_call);
12580 %}
12581 
12582 // Return Instruction
12583 instruct Ret() %{
12584   match(Return);
12585   format %{ "BLR      \t// branch to link register" %}
12586   size(4);
12587   ins_encode %{
12588     // TODO: PPC port $archOpcode(ppc64Opcode_blr);
12589     // LR is restored in MachEpilogNode. Just do the RET here.
12590     __ blr();
12591   %}
12592   ins_pipe(pipe_class_default);
12593 %}
12594 
12595 // Tail Jump; remove the return address; jump to target.
12596 // TailCall above leaves the return address around.
12597 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
12598 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
12599 // "restore" before this instruction (in Epilogue), we need to materialize it
12600 // in %i0.
12601 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
12602   match(TailJump jump_target ex_oop);
12603   ins_cost(CALL_COST);
12604 
12605   format %{ "LD      R4_ARG2 = LR\n\t"
12606             "MTCTR   $jump_target\n\t"
12607             "BCTR     \t// TailJump, exception oop: $ex_oop" %}
12608   size(12);
12609   ins_encode %{
12610     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12611     __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
12612     __ mtctr($jump_target$$Register);
12613     __ bctr();
12614   %}
12615   ins_pipe(pipe_class_call);
12616 %}
12617 
12618 // Create exception oop: created by stack-crawling runtime code.
12619 // Created exception is now available to this handler, and is setup
12620 // just prior to jumping to this handler. No code emitted.
12621 instruct CreateException(rarg1RegP ex_oop) %{
12622   match(Set ex_oop (CreateEx));
12623   ins_cost(0);
12624 
12625   format %{ " -- \t// exception oop; no code emitted" %}
12626   size(0);
12627   ins_encode( /*empty*/ );
12628   ins_pipe(pipe_class_default);
12629 %}
12630 
12631 // Rethrow exception: The exception oop will come in the first
12632 // argument position. Then JUMP (not call) to the rethrow stub code.
12633 instruct RethrowException() %{
12634   match(Rethrow);
12635   ins_cost(CALL_COST);
12636 
12637   format %{ "Jmp     rethrow_stub" %}
12638   ins_encode %{
12639     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12640     cbuf.set_insts_mark();
12641     __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
12642   %}
12643   ins_pipe(pipe_class_call);
12644 %}
12645 
12646 // Die now.
12647 instruct ShouldNotReachHere() %{
12648   match(Halt);
12649   ins_cost(CALL_COST);
12650 
12651   format %{ "ShouldNotReachHere" %}
12652   size(4);
12653   ins_encode %{
12654     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
12655     __ trap_should_not_reach_here();
12656   %}
12657   ins_pipe(pipe_class_default);
12658 %}
12659 
12660 // This name is KNOWN by the ADLC and cannot be changed.  The ADLC
12661 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
12662 // Get a DEF on threadRegP, no costs, no encoding, use
12663 // 'ins_should_rematerialize(true)' to avoid spilling.
12664 instruct tlsLoadP(threadRegP dst) %{
12665   match(Set dst (ThreadLocal));
12666   ins_cost(0);
12667 
12668   ins_should_rematerialize(true);
12669 
12670   format %{ " -- \t// $dst=Thread::current(), empty" %}
12671   size(0);
12672   ins_encode( /*empty*/ );
12673   ins_pipe(pipe_class_empty);
12674 %}
12675 
12676 //---Some PPC specific nodes---------------------------------------------------
12677 
12678 // Stop a group.
12679 instruct endGroup() %{
12680   ins_cost(0);
12681 
12682   ins_is_nop(true);
12683 
12684   format %{ "End Bundle (ori r1, r1, 0)" %}
12685   size(4);
12686   ins_encode %{
12687     // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
12688     __ endgroup();
12689   %}
12690   ins_pipe(pipe_class_default);
12691 %}
12692 
12693 // Nop instructions
12694 
12695 instruct fxNop() %{
12696   ins_cost(0);
12697 
12698   ins_is_nop(true);
12699 
12700   format %{ "fxNop" %}
12701   size(4);
12702   ins_encode %{
12703     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12704     __ nop();
12705   %}
12706   ins_pipe(pipe_class_default);
12707 %}
12708 
12709 instruct fpNop0() %{
12710   ins_cost(0);
12711 
12712   ins_is_nop(true);
12713 
12714   format %{ "fpNop0" %}
12715   size(4);
12716   ins_encode %{
12717     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12718     __ fpnop0();
12719   %}
12720   ins_pipe(pipe_class_default);
12721 %}
12722 
12723 instruct fpNop1() %{
12724   ins_cost(0);
12725 
12726   ins_is_nop(true);
12727 
12728   format %{ "fpNop1" %}
12729   size(4);
12730   ins_encode %{
12731     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
12732     __ fpnop1();
12733   %}
12734   ins_pipe(pipe_class_default);
12735 %}
12736 
12737 instruct brNop0() %{
12738   ins_cost(0);
12739   size(4);
12740   format %{ "brNop0" %}
12741   ins_encode %{
12742     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12743     __ brnop0();
12744   %}
12745   ins_is_nop(true);
12746   ins_pipe(pipe_class_default);
12747 %}
12748 
12749 instruct brNop1() %{
12750   ins_cost(0);
12751 
12752   ins_is_nop(true);
12753 
12754   format %{ "brNop1" %}
12755   size(4);
12756   ins_encode %{
12757     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12758     __ brnop1();
12759   %}
12760   ins_pipe(pipe_class_default);
12761 %}
12762 
12763 instruct brNop2() %{
12764   ins_cost(0);
12765 
12766   ins_is_nop(true);
12767 
12768   format %{ "brNop2" %}
12769   size(4);
12770   ins_encode %{
12771     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
12772     __ brnop2();
12773   %}
12774   ins_pipe(pipe_class_default);
12775 %}
12776 
12777 //----------PEEPHOLE RULES-----------------------------------------------------
12778 // These must follow all instruction definitions as they use the names
12779 // defined in the instructions definitions.
12780 //
12781 // peepmatch ( root_instr_name [preceeding_instruction]* );
12782 //
12783 // peepconstraint %{
12784 // (instruction_number.operand_name relational_op instruction_number.operand_name
12785 //  [, ...] );
12786 // // instruction numbers are zero-based using left to right order in peepmatch
12787 //
12788 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12789 // // provide an instruction_number.operand_name for each operand that appears
12790 // // in the replacement instruction's match rule
12791 //
12792 // ---------VM FLAGS---------------------------------------------------------
12793 //
12794 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12795 //
12796 // Each peephole rule is given an identifying number starting with zero and
12797 // increasing by one in the order seen by the parser. An individual peephole
12798 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12799 // on the command-line.
12800 //
12801 // ---------CURRENT LIMITATIONS----------------------------------------------
12802 //
12803 // Only match adjacent instructions in same basic block
12804 // Only equality constraints
12805 // Only constraints between operands, not (0.dest_reg == EAX_enc)
12806 // Only one replacement instruction
12807 //
12808 // ---------EXAMPLE----------------------------------------------------------
12809 //
12810 // // pertinent parts of existing instructions in architecture description
12811 // instruct movI(eRegI dst, eRegI src) %{
12812 //   match(Set dst (CopyI src));
12813 // %}
12814 //
12815 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
12816 //   match(Set dst (AddI dst src));
12817 //   effect(KILL cr);
12818 // %}
12819 //
12820 // // Change (inc mov) to lea
12821 // peephole %{
12822 //   // increment preceeded by register-register move
12823 //   peepmatch ( incI_eReg movI );
12824 //   // require that the destination register of the increment
12825 //   // match the destination register of the move
12826 //   peepconstraint ( 0.dst == 1.dst );
12827 //   // construct a replacement instruction that sets
12828 //   // the destination to ( move's source register + one )
12829 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12830 // %}
12831 //
12832 // Implementation no longer uses movX instructions since
12833 // machine-independent system no longer uses CopyX nodes.
12834 //
12835 // peephole %{
12836 //   peepmatch ( incI_eReg movI );
12837 //   peepconstraint ( 0.dst == 1.dst );
12838 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12839 // %}
12840 //
12841 // peephole %{
12842 //   peepmatch ( decI_eReg movI );
12843 //   peepconstraint ( 0.dst == 1.dst );
12844 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12845 // %}
12846 //
12847 // peephole %{
12848 //   peepmatch ( addI_eReg_imm movI );
12849 //   peepconstraint ( 0.dst == 1.dst );
12850 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
12851 // %}
12852 //
12853 // peephole %{
12854 //   peepmatch ( addP_eReg_imm movP );
12855 //   peepconstraint ( 0.dst == 1.dst );
12856 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
12857 // %}
12858 
12859 // // Change load of spilled value to only a spill
12860 // instruct storeI(memory mem, eRegI src) %{
12861 //   match(Set mem (StoreI mem src));
12862 // %}
12863 //
12864 // instruct loadI(eRegI dst, memory mem) %{
12865 //   match(Set dst (LoadI mem));
12866 // %}
12867 //
12868 peephole %{
12869   peepmatch ( loadI storeI );
12870   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12871   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
12872 %}
12873 
12874 peephole %{
12875   peepmatch ( loadL storeL );
12876   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
12877   peepreplace ( storeL( 1.mem 1.mem 1.src ) );
12878 %}
12879 
12880 peephole %{
12881   peepmatch ( loadP storeP );
12882   peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
12883   peepreplace ( storeP( 1.dst 1.dst 1.src ) );
12884 %}
12885 
12886 //----------SMARTSPILL RULES---------------------------------------------------
12887 // These must follow all instruction definitions as they use the names
12888 // defined in the instructions definitions.