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src/cpu/ppc/vm/ppc.ad

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1828 
1829 #ifndef PRODUCT
1830 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1831   st->print("NOP \t// %d nops to pad for loops.", _count);
1832 }
1833 #endif
1834 
1835 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1836   MacroAssembler _masm(&cbuf);
1837   // _count contains the number of nops needed for padding.
1838   for (int i = 0; i < _count; i++) {
1839     __ nop();
1840   }
1841 }
1842 
1843 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1844   return _count * 4;
1845 }
1846 
1847 #ifndef PRODUCT














1848 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1849   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1850   char reg_str[128];
1851   ra_->dump_register(this, reg_str);
1852   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
1853 }
1854 #endif
1855 
1856 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1857   MacroAssembler _masm(&cbuf);
1858 
1859   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1860   int reg    = ra_->get_encode(this);
1861 
1862   if (Assembler::is_simm(offset, 16)) {
1863     __ addi(as_Register(reg), R1, offset);
1864   } else {
1865     ShouldNotReachHere();
1866   }
1867 }


2028   case Op_StrEquals:
2029     return SpecialStringEquals;
2030   case Op_StrIndexOf:
2031     return SpecialStringIndexOf;
2032   case Op_StrIndexOfChar:
2033     return SpecialStringIndexOf;
2034   }
2035 
2036   return true;  // Per default match rules are supported.
2037 }
2038 
2039 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2040 
2041   // TODO
2042   // identify extra cases that we might want to provide match rules for
2043   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2044   bool ret_value = match_rule_supported(opcode);
2045   // Add rules here.
2046 
2047   return ret_value;  // Per default match rules are supported.




2048 }
2049 
2050 const int Matcher::float_pressure(int default_pressure_threshold) {
2051   return default_pressure_threshold;
2052 }
2053 
2054 int Matcher::regnum_to_fpu_offset(int regnum) {
2055   // No user for this method?
2056   Unimplemented();
2057   return 999;
2058 }
2059 
2060 const bool Matcher::convL2FSupported(void) {
2061   // fcfids can do the conversion (>= Power7).
2062   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2063   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2064 }
2065 
2066 // Vector width in bytes.
2067 const int Matcher::vector_width_in_bytes(BasicType bt) {




1828 
1829 #ifndef PRODUCT
1830 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1831   st->print("NOP \t// %d nops to pad for loops.", _count);
1832 }
1833 #endif
1834 
1835 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1836   MacroAssembler _masm(&cbuf);
1837   // _count contains the number of nops needed for padding.
1838   for (int i = 0; i < _count; i++) {
1839     __ nop();
1840   }
1841 }
1842 
1843 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1844   return _count * 4;
1845 }
1846 
1847 #ifndef PRODUCT
1848 void MachMskNode::format(PhaseRegAlloc*, outputStream* st) const {
1849   // TBD
1850 }
1851 #endif
1852 
1853 void MachMskNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
1854   // TBD
1855 }
1856 
1857 uint MachMskNode::size(PhaseRegAlloc* ra_) const {
1858   return 0; // TBD
1859 }
1860 
1861 #ifndef PRODUCT
1862 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1863   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1864   char reg_str[128];
1865   ra_->dump_register(this, reg_str);
1866   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
1867 }
1868 #endif
1869 
1870 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1871   MacroAssembler _masm(&cbuf);
1872 
1873   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1874   int reg    = ra_->get_encode(this);
1875 
1876   if (Assembler::is_simm(offset, 16)) {
1877     __ addi(as_Register(reg), R1, offset);
1878   } else {
1879     ShouldNotReachHere();
1880   }
1881 }


2042   case Op_StrEquals:
2043     return SpecialStringEquals;
2044   case Op_StrIndexOf:
2045     return SpecialStringIndexOf;
2046   case Op_StrIndexOfChar:
2047     return SpecialStringIndexOf;
2048   }
2049 
2050   return true;  // Per default match rules are supported.
2051 }
2052 
2053 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2054 
2055   // TODO
2056   // identify extra cases that we might want to provide match rules for
2057   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2058   bool ret_value = match_rule_supported(opcode);
2059   // Add rules here.
2060 
2061   return ret_value;  // Per default match rules are supported.
2062 }
2063 
2064 const bool Matcher::has_predicated_vectors(void) {
2065   return false;
2066 }
2067 
2068 const int Matcher::float_pressure(int default_pressure_threshold) {
2069   return default_pressure_threshold;
2070 }
2071 
2072 int Matcher::regnum_to_fpu_offset(int regnum) {
2073   // No user for this method?
2074   Unimplemented();
2075   return 999;
2076 }
2077 
2078 const bool Matcher::convL2FSupported(void) {
2079   // fcfids can do the conversion (>= Power7).
2080   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2081   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2082 }
2083 
2084 // Vector width in bytes.
2085 const int Matcher::vector_width_in_bytes(BasicType bt) {


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