1 //
2 // Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
605 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr = (Assembler::ldst_op << 30)
952 | (dst_enc << 25)
953 | (primary << 19)
954 | (src1_enc << 14);
955
956 uint index = src2_enc;
957 int disp = disp32;
958
959 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
960 disp += STACK_BIAS;
961 // Check that stack offset fits, load into O7 if not
962 if (!Assembler::is_simm13(disp)) {
963 MacroAssembler _masm(&cbuf);
964 __ set(disp, O7);
965 if (index != R_G0_enc) {
966 __ add(O7, reg_to_register_object(index), O7);
967 }
968 index = R_O7_enc;
969 disp = 0;
970 }
971 }
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 if (VerifyOops) {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rspec);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1298 __ reserved_stack_check();
1299 }
1300
1301 // If this does safepoint polling, then do it here
1302 if(do_polling() && ra_->C->is_method_compilation()) {
1303 AddressLiteral polling_page(os::get_polling_page());
1304 __ sethi(polling_page, L0);
1305 __ relocate(relocInfo::poll_return_type);
1306 __ ld_ptr(L0, 0, G0);
1307 }
1308
1309 // If this is a return, then stuff the restore in the delay slot
1310 if(do_polling()) {
1311 if (UseCBCond && !ra_->C->is_method_compilation()) {
1312 // Insert extra padding for the case when the epilogue is preceded by
1313 // a cbcond jump, which can't be followed by a CTI instruction
1314 __ nop();
1315 }
1316 __ ret();
1317 __ delayed()->restore();
1318 } else {
1319 __ restore();
1320 }
1321 }
1322
1323 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1324 return MachNode::size(ra_);
1325 }
1326
1327 int MachEpilogNode::reloc() const {
1328 return 16; // a large enough number
1329 }
1330
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332 return MachNode::pipeline_class();
1333 }
1334
1335 int MachEpilogNode::safepoint_offset() const {
1336 assert( do_polling(), "no return for this epilog node");
1337 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339
1340 //=============================================================================
1341
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345 if (!OptoReg::is_valid(reg)) return rc_bad;
1346 if (OptoReg::is_stack(reg)) return rc_stack;
1347 VMReg r = OptoReg::as_VMReg(reg);
1348 if (r->is_Register()) return rc_int;
1349 assert(r->is_FloatRegister(), "must be");
1350 return rc_float;
1351 }
1352
1353 #ifndef PRODUCT
1354 ATTRIBUTE_PRINTF(2, 3)
1355 static void print_helper(outputStream* st, const char* format, ...) {
1356 if (st->position() > 0) {
1357 st->cr();
1358 st->sp();
1359 }
1360 va_list ap;
1361 va_start(ap, format);
1362 st->vprint(format, ap);
1363 va_end(ap);
1364 }
1365 #endif // !PRODUCT
1366
1367 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1368 if (cbuf) {
1369 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1370 }
1371 #ifndef PRODUCT
1372 else {
1373 if (is_load) {
1374 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1375 } else {
1376 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1377 }
1378 }
1379 #endif
1380 }
1381
1382 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1383 if (cbuf) {
1384 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1385 }
1386 #ifndef PRODUCT
1387 else {
1388 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1389 }
1390 #endif
1391 }
1392
1393 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1394 CodeBuffer *cbuf,
1395 PhaseRegAlloc *ra_,
1396 outputStream* st) {
1397 // Get registers to move
1398 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1399 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1400 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1401 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1402
1403 enum RC src_second_rc = rc_class(src_second);
1404 enum RC src_first_rc = rc_class(src_first);
1405 enum RC dst_second_rc = rc_class(dst_second);
1406 enum RC dst_first_rc = rc_class(dst_first);
1407
1408 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1409
1410 if (src_first == dst_first && src_second == dst_second) {
1411 return; // Self copy, no move
1412 }
1413
1414 // --------------------------------------
1415 // Check for mem-mem move. Load into unused float registers and fall into
1416 // the float-store case.
1417 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1418 int offset = ra_->reg2offset(src_first);
1419 // Further check for aligned-adjacent pair, so we can use a double load
1420 if ((src_first&1) == 0 && src_first+1 == src_second) {
1421 src_second = OptoReg::Name(R_F31_num);
1422 src_second_rc = rc_float;
1423 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1424 } else {
1425 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1426 }
1427 src_first = OptoReg::Name(R_F30_num);
1428 src_first_rc = rc_float;
1429 }
1430
1431 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1432 int offset = ra_->reg2offset(src_second);
1433 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1434 src_second = OptoReg::Name(R_F31_num);
1435 src_second_rc = rc_float;
1436 }
1437
1438 // --------------------------------------
1439 // Check for float->int copy; requires a trip through memory
1440 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1441 int offset = frame::register_save_words*wordSize;
1442 if (cbuf) {
1443 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1444 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1445 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1447 }
1448 #ifndef PRODUCT
1449 else {
1450 print_helper(st, "SUB R_SP,16,R_SP");
1451 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1452 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1453 print_helper(st, "ADD R_SP,16,R_SP");
1454 }
1455 #endif
1456 }
1457
1458 // Check for float->int copy on T4
1459 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1460 // Further check for aligned-adjacent pair, so we can use a double move
1461 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1463 return;
1464 }
1465 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1466 }
1467 // Check for int->float copy on T4
1468 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1469 // Further check for aligned-adjacent pair, so we can use a double move
1470 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1471 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1472 return;
1473 }
1474 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1475 }
1476
1477 // --------------------------------------
1478 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1479 // In such cases, I have to do the big-endian swap. For aligned targets, the
1480 // hardware does the flop for me. Doubles are always aligned, so no problem
1481 // there. Misaligned sources only come from native-long-returns (handled
1482 // special below).
1483 #ifndef _LP64
1484 if (src_first_rc == rc_int && // source is already big-endian
1485 src_second_rc != rc_bad && // 64-bit move
1486 ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1487 assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1488 // Do the big-endian flop.
1489 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1490 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1491 }
1492 #endif
1493
1494 // --------------------------------------
1495 // Check for integer reg-reg copy
1496 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1497 #ifndef _LP64
1498 if (src_first == R_O0_num && src_second == R_O1_num) { // Check for the evil O0/O1 native long-return case
1499 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1500 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1501 // operand contains the least significant word of the 64-bit value and vice versa.
1502 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1503 assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1504 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1505 if ( cbuf ) {
1506 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1507 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1508 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1509 #ifndef PRODUCT
1510 } else {
1511 print_helper(st, "SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1512 print_helper(st, "SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1513 print_helper(st, "OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1514 #endif
1515 }
1516 return;
1517 } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1518 // returning a long value in I0/I1
1519 // a SpillCopy must be able to target a return instruction's reg_class
1520 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1521 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1522 // operand contains the least significant word of the 64-bit value and vice versa.
1523 OptoReg::Name tdest = dst_first;
1524
1525 if (src_first == dst_first) {
1526 tdest = OptoReg::Name(R_O7_num);
1527 }
1528
1529 if (cbuf) {
1530 assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1531 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1532 // ShrL_reg_imm6
1533 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1534 // ShrR_reg_imm6 src, 0, dst
1535 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1536 if (tdest != dst_first) {
1537 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1538 }
1539 }
1540 #ifndef PRODUCT
1541 else {
1542 print_helper(st, "SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1543 print_helper(st, "SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1544 if (tdest != dst_first) {
1545 print_helper(st, "MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1546 }
1547 }
1548 #endif // PRODUCT
1549 return size+8;
1550 }
1551 #endif // !_LP64
1552 // Else normal reg-reg copy
1553 assert(src_second != dst_first, "smashed second before evacuating it");
1554 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1555 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1556 // This moves an aligned adjacent pair.
1557 // See if we are done.
1558 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1559 return;
1560 }
1561 }
1562
1563 // Check for integer store
1564 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1565 int offset = ra_->reg2offset(dst_first);
1566 // Further check for aligned-adjacent pair, so we can use a double store
1567 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1568 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1569 return;
1570 }
1571 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1572 }
1573
1574 // Check for integer load
1575 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1576 int offset = ra_->reg2offset(src_first);
1577 // Further check for aligned-adjacent pair, so we can use a double load
1578 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1579 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1580 return;
1581 }
1582 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1583 }
1584
1585 // Check for float reg-reg copy
1586 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1587 // Further check for aligned-adjacent pair, so we can use a double move
1588 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1589 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1590 return;
1591 }
1592 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1593 }
1594
1595 // Check for float store
1596 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1597 int offset = ra_->reg2offset(dst_first);
1598 // Further check for aligned-adjacent pair, so we can use a double store
1599 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1600 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1601 return;
1602 }
1603 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1604 }
1605
1606 // Check for float load
1607 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1608 int offset = ra_->reg2offset(src_first);
1609 // Further check for aligned-adjacent pair, so we can use a double load
1610 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1611 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1612 return;
1613 }
1614 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1615 }
1616
1617 // --------------------------------------------------------------------
1618 // Check for hi bits still needing moving. Only happens for misaligned
1619 // arguments to native calls.
1620 if (src_second == dst_second) {
1621 return; // Self copy; no move
1622 }
1623 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1624
1625 #ifndef _LP64
1626 // In the LP64 build, all registers can be moved as aligned/adjacent
1627 // pairs, so there's never any need to move the high bits separately.
1628 // The 32-bit builds have to deal with the 32-bit ABI which can force
1629 // all sorts of silly alignment problems.
1630
1631 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1632 // 32-bits of a 64-bit register, but are needed in low bits of another
1633 // register (else it's a hi-bits-to-hi-bits copy which should have
1634 // happened already as part of a 64-bit move)
1635 if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1636 assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1637 assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1638 // Shift src_second down to dst_second's low bits.
1639 if (cbuf) {
1640 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1641 #ifndef PRODUCT
1642 } else {
1643 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1644 #endif
1645 }
1646 return;
1647 }
1648
1649 // Check for high word integer store. Must down-shift the hi bits
1650 // into a temp register, then fall into the case of storing int bits.
1651 if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1652 // Shift src_second down to dst_second's low bits.
1653 if (cbuf) {
1654 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1655 #ifndef PRODUCT
1656 } else {
1657 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1658 #endif
1659 }
1660 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1661 }
1662
1663 // Check for high word integer load
1664 if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1665 return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1666
1667 // Check for high word integer store
1668 if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1669 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1670
1671 // Check for high word float store
1672 if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1673 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1674
1675 #endif // !_LP64
1676
1677 Unimplemented();
1678 }
1679
1680 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1681 PhaseRegAlloc *ra_,
1682 bool do_size,
1683 outputStream* st) const {
1684 assert(!do_size, "not supported");
1685 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1686 return 0;
1687 }
1688
1689 #ifndef PRODUCT
1690 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1691 implementation( NULL, ra_, false, st );
1692 }
1693 #endif
1694
1695 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1696 implementation( &cbuf, ra_, false, NULL );
1697 }
1698
1699 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1700 return MachNode::size(ra_);
1701 }
1702
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711 MacroAssembler _masm(&cbuf);
1712 for (int i = 0; i < _count; i += 1) {
1713 __ nop();
1714 }
1715 }
1716
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718 return 4 * _count;
1719 }
1720
1721 #ifndef PRODUCT
1722 void MachMskNode::format(PhaseRegAlloc*, outputStream* st) const {
1723 // TBD
1724 }
1725 #endif
1726
1727 void MachMskNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
1728 // TBD
1729 }
1730
1731 uint MachMskNode::size(PhaseRegAlloc* ra_) const {
1732 return 0; // TBD
1733 }
1734
1735 //=============================================================================
1736 #ifndef PRODUCT
1737 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1738 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1739 int reg = ra_->get_reg_first(this);
1740 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1741 }
1742 #endif
1743
1744 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1745 MacroAssembler _masm(&cbuf);
1746 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1747 int reg = ra_->get_encode(this);
1748
1749 if (Assembler::is_simm13(offset)) {
1750 __ add(SP, offset, reg_to_register_object(reg));
1751 } else {
1752 __ set(offset, O7);
1753 __ add(SP, O7, reg_to_register_object(reg));
1754 }
1755 }
1756
1757 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1758 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1759 assert(ra_ == ra_->C->regalloc(), "sanity");
1760 return ra_->C->scratch_emit_size(this);
1761 }
1762
1763 //=============================================================================
1764 #ifndef PRODUCT
1765 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1766 st->print_cr("\nUEP:");
1767 #ifdef _LP64
1768 if (UseCompressedClassPointers) {
1769 assert(Universe::heap() != NULL, "java heap should be initialized");
1770 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1771 if (Universe::narrow_klass_base() != 0) {
1772 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1773 if (Universe::narrow_klass_shift() != 0) {
1774 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1775 }
1776 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1777 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1778 } else {
1779 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1780 }
1781 } else {
1782 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1783 }
1784 st->print_cr("\tCMP R_G5,R_G3" );
1785 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1786 #else // _LP64
1787 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1788 st->print_cr("\tCMP R_G5,R_G3" );
1789 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1790 #endif // _LP64
1791 }
1792 #endif
1793
1794 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1795 MacroAssembler _masm(&cbuf);
1796 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1797 Register temp_reg = G3;
1798 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1799
1800 // Load klass from receiver
1801 __ load_klass(O0, temp_reg);
1802 // Compare against expected klass
1803 __ cmp(temp_reg, G5_ic_reg);
1804 // Branch to miss code, checks xcc or icc depending
1805 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1806 }
1807
1808 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1809 return MachNode::size(ra_);
1810 }
1811
1812
1813 //=============================================================================
1814
1815
1816 // Emit exception handler code.
1817 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1818 Register temp_reg = G3;
1819 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1820 MacroAssembler _masm(&cbuf);
1821
1822 address base = __ start_a_stub(size_exception_handler());
1823 if (base == NULL) {
1824 ciEnv::current()->record_failure("CodeCache is full");
1825 return 0; // CodeBuffer::expand failed
1826 }
1827
1828 int offset = __ offset();
1829
1830 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1831 __ delayed()->nop();
1832
1833 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1834
1835 __ end_a_stub();
1836
1837 return offset;
1838 }
1839
1840 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1841 // Can't use any of the current frame's registers as we may have deopted
1842 // at a poll and everything (including G3) can be live.
1843 Register temp_reg = L0;
1844 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1845 MacroAssembler _masm(&cbuf);
1846
1847 address base = __ start_a_stub(size_deopt_handler());
1848 if (base == NULL) {
1849 ciEnv::current()->record_failure("CodeCache is full");
1850 return 0; // CodeBuffer::expand failed
1851 }
1852
1853 int offset = __ offset();
1854 __ save_frame(0);
1855 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1856 __ delayed()->restore();
1857
1858 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1859
1860 __ end_a_stub();
1861 return offset;
1862
1863 }
1864
1865 // Given a register encoding, produce a Integer Register object
1866 static Register reg_to_register_object(int register_encoding) {
1867 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1868 return as_Register(register_encoding);
1869 }
1870
1871 // Given a register encoding, produce a single-precision Float Register object
1872 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1873 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1874 return as_SingleFloatRegister(register_encoding);
1875 }
1876
1877 // Given a register encoding, produce a double-precision Float Register object
1878 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1879 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1880 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1881 return as_DoubleFloatRegister(register_encoding);
1882 }
1883
1884 const bool Matcher::match_rule_supported(int opcode) {
1885 if (!has_match_rule(opcode))
1886 return false;
1887
1888 switch (opcode) {
1889 case Op_CountLeadingZerosI:
1890 case Op_CountLeadingZerosL:
1891 case Op_CountTrailingZerosI:
1892 case Op_CountTrailingZerosL:
1893 case Op_PopCountI:
1894 case Op_PopCountL:
1895 if (!UsePopCountInstruction)
1896 return false;
1897 case Op_CompareAndSwapL:
1898 #ifdef _LP64
1899 case Op_CompareAndSwapP:
1900 #endif
1901 if (!VM_Version::supports_cx8())
1902 return false;
1903 break;
1904 }
1905
1906 return true; // Per default match rules are supported.
1907 }
1908
1909 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1910
1911 // TODO
1912 // identify extra cases that we might want to provide match rules for
1913 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1914 bool ret_value = match_rule_supported(opcode);
1915 // Add rules here.
1916
1917 return ret_value; // Per default match rules are supported.
1918 }
1919
1920 const bool Matcher::has_predicated_vectors(void) {
1921 return false;
1922 }
1923
1924 const int Matcher::float_pressure(int default_pressure_threshold) {
1925 return default_pressure_threshold;
1926 }
1927
1928 int Matcher::regnum_to_fpu_offset(int regnum) {
1929 return regnum - 32; // The FP registers are in the second chunk
1930 }
1931
1932 #ifdef ASSERT
1933 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1934 #endif
1935
1936 // Vector width in bytes
1937 const int Matcher::vector_width_in_bytes(BasicType bt) {
1938 assert(MaxVectorSize == 8, "");
1939 return 8;
1940 }
1941
1942 // Vector ideal reg
1943 const int Matcher::vector_ideal_reg(int size) {
1944 assert(MaxVectorSize == 8, "");
1945 return Op_RegD;
1946 }
1947
1948 const int Matcher::vector_shift_count_ideal_reg(int size) {
1949 fatal("vector shift is not supported");
1950 return Node::NotAMachineReg;
1951 }
1952
1953 // Limits on vector size (number of elements) loaded into vector.
1954 const int Matcher::max_vector_size(const BasicType bt) {
1955 assert(is_java_primitive(bt), "only primitive type vectors");
1956 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1957 }
1958
1959 const int Matcher::min_vector_size(const BasicType bt) {
1960 return max_vector_size(bt); // Same as max.
1961 }
1962
1963 // SPARC doesn't support misaligned vectors store/load.
1964 const bool Matcher::misaligned_vectors_ok() {
1965 return false;
1966 }
1967
1968 // Current (2013) SPARC platforms need to read original key
1969 // to construct decryption expanded key
1970 const bool Matcher::pass_original_key_for_aes() {
1971 return true;
1972 }
1973
1974 // USII supports fxtof through the whole range of number, USIII doesn't
1975 const bool Matcher::convL2FSupported(void) {
1976 return VM_Version::has_fast_fxtof();
1977 }
1978
1979 // Is this branch offset short enough that a short branch can be used?
1980 //
1981 // NOTE: If the platform does not provide any short branch variants, then
1982 // this method should return false for offset 0.
1983 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1984 // The passed offset is relative to address of the branch.
1985 // Don't need to adjust the offset.
1986 return UseCBCond && Assembler::is_simm12(offset);
1987 }
1988
1989 const bool Matcher::isSimpleConstant64(jlong value) {
1990 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1991 // Depends on optimizations in MacroAssembler::setx.
1992 int hi = (int)(value >> 32);
1993 int lo = (int)(value & ~0);
1994 return (hi == 0) || (hi == -1) || (lo == 0);
1995 }
1996
1997 // No scaling for the parameter the ClearArray node.
1998 const bool Matcher::init_array_count_is_in_bytes = true;
1999
2000 // No additional cost for CMOVL.
2001 const int Matcher::long_cmove_cost() { return 0; }
2002
2003 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
2004 const int Matcher::float_cmove_cost() {
2005 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
2006 }
2007
2008 // Does the CPU require late expand (see block.cpp for description of late expand)?
2009 const bool Matcher::require_postalloc_expand = false;
2010
2011 // Should the Matcher clone shifts on addressing modes, expecting them to
2012 // be subsumed into complex addressing expressions or compute them into
2013 // registers? True for Intel but false for most RISCs
2014 const bool Matcher::clone_shift_expressions = false;
2015
2016 // Do we need to mask the count passed to shift instructions or does
2017 // the cpu only look at the lower 5/6 bits anyway?
2018 const bool Matcher::need_masked_shift_count = false;
2019
2020 bool Matcher::narrow_oop_use_complex_address() {
2021 NOT_LP64(ShouldNotCallThis());
2022 assert(UseCompressedOops, "only for compressed oops code");
2023 return false;
2024 }
2025
2026 bool Matcher::narrow_klass_use_complex_address() {
2027 NOT_LP64(ShouldNotCallThis());
2028 assert(UseCompressedClassPointers, "only for compressed klass code");
2029 return false;
2030 }
2031
2032 // Is it better to copy float constants, or load them directly from memory?
2033 // Intel can load a float constant from a direct address, requiring no
2034 // extra registers. Most RISCs will have to materialize an address into a
2035 // register first, so they would do better to copy the constant from stack.
2036 const bool Matcher::rematerialize_float_constants = false;
2037
2038 // If CPU can load and store mis-aligned doubles directly then no fixup is
2039 // needed. Else we split the double into 2 integer pieces and move it
2040 // piece-by-piece. Only happens when passing doubles into C code as the
2041 // Java calling convention forces doubles to be aligned.
2042 #ifdef _LP64
2043 const bool Matcher::misaligned_doubles_ok = true;
2044 #else
2045 const bool Matcher::misaligned_doubles_ok = false;
2046 #endif
2047
2048 // No-op on SPARC.
2049 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2050 }
2051
2052 // Advertise here if the CPU requires explicit rounding operations
2053 // to implement the UseStrictFP mode.
2054 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2055
2056 // Are floats converted to double when stored to stack during deoptimization?
2057 // Sparc does not handle callee-save floats.
2058 bool Matcher::float_in_double() { return false; }
2059
2060 // Do ints take an entire long register or just half?
2061 // Note that we if-def off of _LP64.
2062 // The relevant question is how the int is callee-saved. In _LP64
2063 // the whole long is written but de-opt'ing will have to extract
2064 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2065 #ifdef _LP64
2066 const bool Matcher::int_in_long = true;
2067 #else
2068 const bool Matcher::int_in_long = false;
2069 #endif
2070
2071 // Return whether or not this register is ever used as an argument. This
2072 // function is used on startup to build the trampoline stubs in generateOptoStub.
2073 // Registers not mentioned will be killed by the VM call in the trampoline, and
2074 // arguments in those registers not be available to the callee.
2075 bool Matcher::can_be_java_arg( int reg ) {
2076 // Standard sparc 6 args in registers
2077 if( reg == R_I0_num ||
2078 reg == R_I1_num ||
2079 reg == R_I2_num ||
2080 reg == R_I3_num ||
2081 reg == R_I4_num ||
2082 reg == R_I5_num ) return true;
2083 #ifdef _LP64
2084 // 64-bit builds can pass 64-bit pointers and longs in
2085 // the high I registers
2086 if( reg == R_I0H_num ||
2087 reg == R_I1H_num ||
2088 reg == R_I2H_num ||
2089 reg == R_I3H_num ||
2090 reg == R_I4H_num ||
2091 reg == R_I5H_num ) return true;
2092
2093 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2094 return true;
2095 }
2096
2097 #else
2098 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2099 // Longs cannot be passed in O regs, because O regs become I regs
2100 // after a 'save' and I regs get their high bits chopped off on
2101 // interrupt.
2102 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2103 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2104 #endif
2105 // A few float args in registers
2106 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2107
2108 return false;
2109 }
2110
2111 bool Matcher::is_spillable_arg( int reg ) {
2112 return can_be_java_arg(reg);
2113 }
2114
2115 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2116 // Use hardware SDIVX instruction when it is
2117 // faster than a code which use multiply.
2118 return VM_Version::has_fast_idiv();
2119 }
2120
2121 // Register for DIVI projection of divmodI
2122 RegMask Matcher::divI_proj_mask() {
2123 ShouldNotReachHere();
2124 return RegMask();
2125 }
2126
2127 // Register for MODI projection of divmodI
2128 RegMask Matcher::modI_proj_mask() {
2129 ShouldNotReachHere();
2130 return RegMask();
2131 }
2132
2133 // Register for DIVL projection of divmodL
2134 RegMask Matcher::divL_proj_mask() {
2135 ShouldNotReachHere();
2136 return RegMask();
2137 }
2138
2139 // Register for MODL projection of divmodL
2140 RegMask Matcher::modL_proj_mask() {
2141 ShouldNotReachHere();
2142 return RegMask();
2143 }
2144
2145 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2146 return L7_REGP_mask();
2147 }
2148
2149 %}
2150
2151
2152 // The intptr_t operand types, defined by textual substitution.
2153 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2154 #ifdef _LP64
2155 #define immX immL
2156 #define immX13 immL13
2157 #define immX13m7 immL13m7
2158 #define iRegX iRegL
2159 #define g1RegX g1RegL
2160 #else
2161 #define immX immI
2162 #define immX13 immI13
2163 #define immX13m7 immI13m7
2164 #define iRegX iRegI
2165 #define g1RegX g1RegI
2166 #endif
2167
2168 //----------ENCODING BLOCK-----------------------------------------------------
2169 // This block specifies the encoding classes used by the compiler to output
2170 // byte streams. Encoding classes are parameterized macros used by
2171 // Machine Instruction Nodes in order to generate the bit encoding of the
2172 // instruction. Operands specify their base encoding interface with the
2173 // interface keyword. There are currently supported four interfaces,
2174 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2175 // operand to generate a function which returns its register number when
2176 // queried. CONST_INTER causes an operand to generate a function which
2177 // returns the value of the constant when queried. MEMORY_INTER causes an
2178 // operand to generate four functions which return the Base Register, the
2179 // Index Register, the Scale Value, and the Offset Value of the operand when
2180 // queried. COND_INTER causes an operand to generate six functions which
2181 // return the encoding code (ie - encoding bits for the instruction)
2182 // associated with each basic boolean condition for a conditional instruction.
2183 //
2184 // Instructions specify two basic values for encoding. Again, a function
2185 // is available to check if the constant displacement is an oop. They use the
2186 // ins_encode keyword to specify their encoding classes (which must be
2187 // a sequence of enc_class names, and their parameters, specified in
2188 // the encoding block), and they use the
2189 // opcode keyword to specify, in order, their primary, secondary, and
2190 // tertiary opcode. Only the opcode sections which a particular instruction
2191 // needs for encoding need to be specified.
2192 encode %{
2193 enc_class enc_untested %{
2194 #ifdef ASSERT
2195 MacroAssembler _masm(&cbuf);
2196 __ untested("encoding");
2197 #endif
2198 %}
2199
2200 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2201 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2202 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2203 %}
2204
2205 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2206 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2207 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2208 %}
2209
2210 enc_class form3_mem_prefetch_read( memory mem ) %{
2211 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2212 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2213 %}
2214
2215 enc_class form3_mem_prefetch_write( memory mem ) %{
2216 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2217 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2218 %}
2219
2220 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2221 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2222 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2223 guarantee($mem$$index == R_G0_enc, "double index?");
2224 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2225 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2226 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2227 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2228 %}
2229
2230 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2231 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2232 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2233 guarantee($mem$$index == R_G0_enc, "double index?");
2234 // Load long with 2 instructions
2235 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2236 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2237 %}
2238
2239 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2240 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2241 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2242 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2243 %}
2244
2245 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2246 // Encode a reg-reg copy. If it is useless, then empty encoding.
2247 if( $rs2$$reg != $rd$$reg )
2248 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2249 %}
2250
2251 // Target lo half of long
2252 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2253 // Encode a reg-reg copy. If it is useless, then empty encoding.
2254 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2255 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2256 %}
2257
2258 // Source lo half of long
2259 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2260 // Encode a reg-reg copy. If it is useless, then empty encoding.
2261 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2262 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2263 %}
2264
2265 // Target hi half of long
2266 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2267 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2268 %}
2269
2270 // Source lo half of long, and leave it sign extended.
2271 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2272 // Sign extend low half
2273 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2274 %}
2275
2276 // Source hi half of long, and leave it sign extended.
2277 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2278 // Shift high half to low half
2279 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2280 %}
2281
2282 // Source hi half of long
2283 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2284 // Encode a reg-reg copy. If it is useless, then empty encoding.
2285 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2286 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2287 %}
2288
2289 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2290 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2291 %}
2292
2293 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2294 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2295 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2296 %}
2297
2298 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2299 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2300 // clear if nothing else is happening
2301 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2302 // blt,a,pn done
2303 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2304 // mov dst,-1 in delay slot
2305 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2306 %}
2307
2308 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2309 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2310 %}
2311
2312 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2313 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2314 %}
2315
2316 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2317 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2318 %}
2319
2320 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2321 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2322 %}
2323
2324 enc_class move_return_pc_to_o1() %{
2325 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2326 %}
2327
2328 #ifdef _LP64
2329 /* %%% merge with enc_to_bool */
2330 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2331 MacroAssembler _masm(&cbuf);
2332
2333 Register src_reg = reg_to_register_object($src$$reg);
2334 Register dst_reg = reg_to_register_object($dst$$reg);
2335 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2336 %}
2337 #endif
2338
2339 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2340 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2341 MacroAssembler _masm(&cbuf);
2342
2343 Register p_reg = reg_to_register_object($p$$reg);
2344 Register q_reg = reg_to_register_object($q$$reg);
2345 Register y_reg = reg_to_register_object($y$$reg);
2346 Register tmp_reg = reg_to_register_object($tmp$$reg);
2347
2348 __ subcc( p_reg, q_reg, p_reg );
2349 __ add ( p_reg, y_reg, tmp_reg );
2350 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2351 %}
2352
2353 enc_class form_d2i_helper(regD src, regF dst) %{
2354 // fcmp %fcc0,$src,$src
2355 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2356 // branch %fcc0 not-nan, predict taken
2357 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2358 // fdtoi $src,$dst
2359 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2360 // fitos $dst,$dst (if nan)
2361 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2362 // clear $dst (if nan)
2363 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2364 // carry on here...
2365 %}
2366
2367 enc_class form_d2l_helper(regD src, regD dst) %{
2368 // fcmp %fcc0,$src,$src check for NAN
2369 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2370 // branch %fcc0 not-nan, predict taken
2371 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2372 // fdtox $src,$dst convert in delay slot
2373 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2374 // fxtod $dst,$dst (if nan)
2375 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2376 // clear $dst (if nan)
2377 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2378 // carry on here...
2379 %}
2380
2381 enc_class form_f2i_helper(regF src, regF dst) %{
2382 // fcmps %fcc0,$src,$src
2383 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2384 // branch %fcc0 not-nan, predict taken
2385 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2386 // fstoi $src,$dst
2387 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2388 // fitos $dst,$dst (if nan)
2389 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2390 // clear $dst (if nan)
2391 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2392 // carry on here...
2393 %}
2394
2395 enc_class form_f2l_helper(regF src, regD dst) %{
2396 // fcmps %fcc0,$src,$src
2397 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2398 // branch %fcc0 not-nan, predict taken
2399 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2400 // fstox $src,$dst
2401 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2402 // fxtod $dst,$dst (if nan)
2403 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2404 // clear $dst (if nan)
2405 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2406 // carry on here...
2407 %}
2408
2409 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2410 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2411 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2412 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2413
2414 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2415
2416 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2417 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2418
2419 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2420 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2421 %}
2422
2423 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2424 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2425 %}
2426
2427 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2428 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2429 %}
2430
2431 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2432 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2433 %}
2434
2435 enc_class form3_convI2F(regF rs2, regF rd) %{
2436 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2437 %}
2438
2439 // Encloding class for traceable jumps
2440 enc_class form_jmpl(g3RegP dest) %{
2441 emit_jmpl(cbuf, $dest$$reg);
2442 %}
2443
2444 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2445 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2446 %}
2447
2448 enc_class form2_nop() %{
2449 emit_nop(cbuf);
2450 %}
2451
2452 enc_class form2_illtrap() %{
2453 emit_illtrap(cbuf);
2454 %}
2455
2456
2457 // Compare longs and convert into -1, 0, 1.
2458 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2459 // CMP $src1,$src2
2460 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2461 // blt,a,pn done
2462 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2463 // mov dst,-1 in delay slot
2464 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2465 // bgt,a,pn done
2466 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2467 // mov dst,1 in delay slot
2468 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2469 // CLR $dst
2470 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2471 %}
2472
2473 enc_class enc_PartialSubtypeCheck() %{
2474 MacroAssembler _masm(&cbuf);
2475 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2476 __ delayed()->nop();
2477 %}
2478
2479 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2480 MacroAssembler _masm(&cbuf);
2481 Label* L = $labl$$label;
2482 Assembler::Predict predict_taken =
2483 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2484
2485 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2486 __ delayed()->nop();
2487 %}
2488
2489 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2490 MacroAssembler _masm(&cbuf);
2491 Label* L = $labl$$label;
2492 Assembler::Predict predict_taken =
2493 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2494
2495 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2496 __ delayed()->nop();
2497 %}
2498
2499 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2500 int op = (Assembler::arith_op << 30) |
2501 ($dst$$reg << 25) |
2502 (Assembler::movcc_op3 << 19) |
2503 (1 << 18) | // cc2 bit for 'icc'
2504 ($cmp$$cmpcode << 14) |
2505 (0 << 13) | // select register move
2506 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2507 ($src$$reg << 0);
2508 cbuf.insts()->emit_int32(op);
2509 %}
2510
2511 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2512 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2513 int op = (Assembler::arith_op << 30) |
2514 ($dst$$reg << 25) |
2515 (Assembler::movcc_op3 << 19) |
2516 (1 << 18) | // cc2 bit for 'icc'
2517 ($cmp$$cmpcode << 14) |
2518 (1 << 13) | // select immediate move
2519 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2520 (simm11 << 0);
2521 cbuf.insts()->emit_int32(op);
2522 %}
2523
2524 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2525 int op = (Assembler::arith_op << 30) |
2526 ($dst$$reg << 25) |
2527 (Assembler::movcc_op3 << 19) |
2528 (0 << 18) | // cc2 bit for 'fccX'
2529 ($cmp$$cmpcode << 14) |
2530 (0 << 13) | // select register move
2531 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2532 ($src$$reg << 0);
2533 cbuf.insts()->emit_int32(op);
2534 %}
2535
2536 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2537 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2538 int op = (Assembler::arith_op << 30) |
2539 ($dst$$reg << 25) |
2540 (Assembler::movcc_op3 << 19) |
2541 (0 << 18) | // cc2 bit for 'fccX'
2542 ($cmp$$cmpcode << 14) |
2543 (1 << 13) | // select immediate move
2544 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2545 (simm11 << 0);
2546 cbuf.insts()->emit_int32(op);
2547 %}
2548
2549 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2550 int op = (Assembler::arith_op << 30) |
2551 ($dst$$reg << 25) |
2552 (Assembler::fpop2_op3 << 19) |
2553 (0 << 18) |
2554 ($cmp$$cmpcode << 14) |
2555 (1 << 13) | // select register move
2556 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2557 ($primary << 5) | // select single, double or quad
2558 ($src$$reg << 0);
2559 cbuf.insts()->emit_int32(op);
2560 %}
2561
2562 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2563 int op = (Assembler::arith_op << 30) |
2564 ($dst$$reg << 25) |
2565 (Assembler::fpop2_op3 << 19) |
2566 (0 << 18) |
2567 ($cmp$$cmpcode << 14) |
2568 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2569 ($primary << 5) | // select single, double or quad
2570 ($src$$reg << 0);
2571 cbuf.insts()->emit_int32(op);
2572 %}
2573
2574 // Used by the MIN/MAX encodings. Same as a CMOV, but
2575 // the condition comes from opcode-field instead of an argument.
2576 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2577 int op = (Assembler::arith_op << 30) |
2578 ($dst$$reg << 25) |
2579 (Assembler::movcc_op3 << 19) |
2580 (1 << 18) | // cc2 bit for 'icc'
2581 ($primary << 14) |
2582 (0 << 13) | // select register move
2583 (0 << 11) | // cc1, cc0 bits for 'icc'
2584 ($src$$reg << 0);
2585 cbuf.insts()->emit_int32(op);
2586 %}
2587
2588 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2589 int op = (Assembler::arith_op << 30) |
2590 ($dst$$reg << 25) |
2591 (Assembler::movcc_op3 << 19) |
2592 (6 << 16) | // cc2 bit for 'xcc'
2593 ($primary << 14) |
2594 (0 << 13) | // select register move
2595 (0 << 11) | // cc1, cc0 bits for 'icc'
2596 ($src$$reg << 0);
2597 cbuf.insts()->emit_int32(op);
2598 %}
2599
2600 enc_class Set13( immI13 src, iRegI rd ) %{
2601 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2602 %}
2603
2604 enc_class SetHi22( immI src, iRegI rd ) %{
2605 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2606 %}
2607
2608 enc_class Set32( immI src, iRegI rd ) %{
2609 MacroAssembler _masm(&cbuf);
2610 __ set($src$$constant, reg_to_register_object($rd$$reg));
2611 %}
2612
2613 enc_class call_epilog %{
2614 if( VerifyStackAtCalls ) {
2615 MacroAssembler _masm(&cbuf);
2616 int framesize = ra_->C->frame_size_in_bytes();
2617 Register temp_reg = G3;
2618 __ add(SP, framesize, temp_reg);
2619 __ cmp(temp_reg, FP);
2620 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2621 }
2622 %}
2623
2624 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2625 // to G1 so the register allocator will not have to deal with the misaligned register
2626 // pair.
2627 enc_class adjust_long_from_native_call %{
2628 #ifndef _LP64
2629 if (returns_long()) {
2630 // sllx O0,32,O0
2631 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2632 // srl O1,0,O1
2633 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2634 // or O0,O1,G1
2635 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2636 }
2637 #endif
2638 %}
2639
2640 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2641 // CALL directly to the runtime
2642 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2643 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2644 %}
2645
2646 enc_class preserve_SP %{
2647 MacroAssembler _masm(&cbuf);
2648 __ mov(SP, L7_mh_SP_save);
2649 %}
2650
2651 enc_class restore_SP %{
2652 MacroAssembler _masm(&cbuf);
2653 __ mov(L7_mh_SP_save, SP);
2654 %}
2655
2656 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2657 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2658 // who we intended to call.
2659 if (!_method) {
2660 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2661 } else {
2662 int method_index = resolved_method_index(cbuf);
2663 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2664 : static_call_Relocation::spec(method_index);
2665 emit_call_reloc(cbuf, $meth$$method, rspec);
2666
2667 // Emit stub for static call.
2668 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2669 // Stub does not fit into scratch buffer if TraceJumps is enabled
2670 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2671 ciEnv::current()->record_failure("CodeCache is full");
2672 return;
2673 }
2674 }
2675 %}
2676
2677 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2678 MacroAssembler _masm(&cbuf);
2679 __ set_inst_mark();
2680 int vtable_index = this->_vtable_index;
2681 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2682 if (vtable_index < 0) {
2683 // must be invalid_vtable_index, not nonvirtual_vtable_index
2684 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2685 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2686 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2687 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2688 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2689 } else {
2690 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2691 // Just go thru the vtable
2692 // get receiver klass (receiver already checked for non-null)
2693 // If we end up going thru a c2i adapter interpreter expects method in G5
2694 int off = __ offset();
2695 __ load_klass(O0, G3_scratch);
2696 int klass_load_size;
2697 if (UseCompressedClassPointers) {
2698 assert(Universe::heap() != NULL, "java heap should be initialized");
2699 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2700 } else {
2701 klass_load_size = 1*BytesPerInstWord;
2702 }
2703 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2704 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2705 if (Assembler::is_simm13(v_off)) {
2706 __ ld_ptr(G3, v_off, G5_method);
2707 } else {
2708 // Generate 2 instructions
2709 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2710 __ or3(G5_method, v_off & 0x3ff, G5_method);
2711 // ld_ptr, set_hi, set
2712 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2713 "Unexpected instruction size(s)");
2714 __ ld_ptr(G3, G5_method, G5_method);
2715 }
2716 // NOTE: for vtable dispatches, the vtable entry will never be null.
2717 // However it may very well end up in handle_wrong_method if the
2718 // method is abstract for the particular class.
2719 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2720 // jump to target (either compiled code or c2iadapter)
2721 __ jmpl(G3_scratch, G0, O7);
2722 __ delayed()->nop();
2723 }
2724 %}
2725
2726 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2727 MacroAssembler _masm(&cbuf);
2728
2729 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2730 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2731 // we might be calling a C2I adapter which needs it.
2732
2733 assert(temp_reg != G5_ic_reg, "conflicting registers");
2734 // Load nmethod
2735 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2736
2737 // CALL to compiled java, indirect the contents of G3
2738 __ set_inst_mark();
2739 __ callr(temp_reg, G0);
2740 __ delayed()->nop();
2741 %}
2742
2743 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2744 MacroAssembler _masm(&cbuf);
2745 Register Rdividend = reg_to_register_object($src1$$reg);
2746 Register Rdivisor = reg_to_register_object($src2$$reg);
2747 Register Rresult = reg_to_register_object($dst$$reg);
2748
2749 __ sra(Rdivisor, 0, Rdivisor);
2750 __ sra(Rdividend, 0, Rdividend);
2751 __ sdivx(Rdividend, Rdivisor, Rresult);
2752 %}
2753
2754 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2755 MacroAssembler _masm(&cbuf);
2756
2757 Register Rdividend = reg_to_register_object($src1$$reg);
2758 int divisor = $imm$$constant;
2759 Register Rresult = reg_to_register_object($dst$$reg);
2760
2761 __ sra(Rdividend, 0, Rdividend);
2762 __ sdivx(Rdividend, divisor, Rresult);
2763 %}
2764
2765 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2766 MacroAssembler _masm(&cbuf);
2767 Register Rsrc1 = reg_to_register_object($src1$$reg);
2768 Register Rsrc2 = reg_to_register_object($src2$$reg);
2769 Register Rdst = reg_to_register_object($dst$$reg);
2770
2771 __ sra( Rsrc1, 0, Rsrc1 );
2772 __ sra( Rsrc2, 0, Rsrc2 );
2773 __ mulx( Rsrc1, Rsrc2, Rdst );
2774 __ srlx( Rdst, 32, Rdst );
2775 %}
2776
2777 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2778 MacroAssembler _masm(&cbuf);
2779 Register Rdividend = reg_to_register_object($src1$$reg);
2780 Register Rdivisor = reg_to_register_object($src2$$reg);
2781 Register Rresult = reg_to_register_object($dst$$reg);
2782 Register Rscratch = reg_to_register_object($scratch$$reg);
2783
2784 assert(Rdividend != Rscratch, "");
2785 assert(Rdivisor != Rscratch, "");
2786
2787 __ sra(Rdividend, 0, Rdividend);
2788 __ sra(Rdivisor, 0, Rdivisor);
2789 __ sdivx(Rdividend, Rdivisor, Rscratch);
2790 __ mulx(Rscratch, Rdivisor, Rscratch);
2791 __ sub(Rdividend, Rscratch, Rresult);
2792 %}
2793
2794 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2795 MacroAssembler _masm(&cbuf);
2796
2797 Register Rdividend = reg_to_register_object($src1$$reg);
2798 int divisor = $imm$$constant;
2799 Register Rresult = reg_to_register_object($dst$$reg);
2800 Register Rscratch = reg_to_register_object($scratch$$reg);
2801
2802 assert(Rdividend != Rscratch, "");
2803
2804 __ sra(Rdividend, 0, Rdividend);
2805 __ sdivx(Rdividend, divisor, Rscratch);
2806 __ mulx(Rscratch, divisor, Rscratch);
2807 __ sub(Rdividend, Rscratch, Rresult);
2808 %}
2809
2810 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2811 MacroAssembler _masm(&cbuf);
2812
2813 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2814 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2815
2816 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2817 %}
2818
2819 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2820 MacroAssembler _masm(&cbuf);
2821
2822 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2823 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2824
2825 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2826 %}
2827
2828 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2829 MacroAssembler _masm(&cbuf);
2830
2831 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2832 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2833
2834 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2835 %}
2836
2837 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2838 MacroAssembler _masm(&cbuf);
2839
2840 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2841 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2842
2843 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2844 %}
2845
2846 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2847 MacroAssembler _masm(&cbuf);
2848
2849 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2850 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2851
2852 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2853 %}
2854
2855 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2856 MacroAssembler _masm(&cbuf);
2857
2858 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2859 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2860
2861 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2862 %}
2863
2864 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2865 MacroAssembler _masm(&cbuf);
2866
2867 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2868 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2869
2870 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2871 %}
2872
2873 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2874 MacroAssembler _masm(&cbuf);
2875
2876 Register Roop = reg_to_register_object($oop$$reg);
2877 Register Rbox = reg_to_register_object($box$$reg);
2878 Register Rscratch = reg_to_register_object($scratch$$reg);
2879 Register Rmark = reg_to_register_object($scratch2$$reg);
2880
2881 assert(Roop != Rscratch, "");
2882 assert(Roop != Rmark, "");
2883 assert(Rbox != Rscratch, "");
2884 assert(Rbox != Rmark, "");
2885
2886 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2887 %}
2888
2889 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2890 MacroAssembler _masm(&cbuf);
2891
2892 Register Roop = reg_to_register_object($oop$$reg);
2893 Register Rbox = reg_to_register_object($box$$reg);
2894 Register Rscratch = reg_to_register_object($scratch$$reg);
2895 Register Rmark = reg_to_register_object($scratch2$$reg);
2896
2897 assert(Roop != Rscratch, "");
2898 assert(Roop != Rmark, "");
2899 assert(Rbox != Rscratch, "");
2900 assert(Rbox != Rmark, "");
2901
2902 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2903 %}
2904
2905 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2906 MacroAssembler _masm(&cbuf);
2907 Register Rmem = reg_to_register_object($mem$$reg);
2908 Register Rold = reg_to_register_object($old$$reg);
2909 Register Rnew = reg_to_register_object($new$$reg);
2910
2911 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2912 __ cmp( Rold, Rnew );
2913 %}
2914
2915 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2916 Register Rmem = reg_to_register_object($mem$$reg);
2917 Register Rold = reg_to_register_object($old$$reg);
2918 Register Rnew = reg_to_register_object($new$$reg);
2919
2920 MacroAssembler _masm(&cbuf);
2921 __ mov(Rnew, O7);
2922 __ casx(Rmem, Rold, O7);
2923 __ cmp( Rold, O7 );
2924 %}
2925
2926 // raw int cas, used for compareAndSwap
2927 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2928 Register Rmem = reg_to_register_object($mem$$reg);
2929 Register Rold = reg_to_register_object($old$$reg);
2930 Register Rnew = reg_to_register_object($new$$reg);
2931
2932 MacroAssembler _masm(&cbuf);
2933 __ mov(Rnew, O7);
2934 __ cas(Rmem, Rold, O7);
2935 __ cmp( Rold, O7 );
2936 %}
2937
2938 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2939 Register Rres = reg_to_register_object($res$$reg);
2940
2941 MacroAssembler _masm(&cbuf);
2942 __ mov(1, Rres);
2943 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2944 %}
2945
2946 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2947 Register Rres = reg_to_register_object($res$$reg);
2948
2949 MacroAssembler _masm(&cbuf);
2950 __ mov(1, Rres);
2951 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2952 %}
2953
2954 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2955 MacroAssembler _masm(&cbuf);
2956 Register Rdst = reg_to_register_object($dst$$reg);
2957 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2958 : reg_to_DoubleFloatRegister_object($src1$$reg);
2959 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2960 : reg_to_DoubleFloatRegister_object($src2$$reg);
2961
2962 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2963 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2964 %}
2965
2966 enc_class enc_rethrow() %{
2967 cbuf.set_insts_mark();
2968 Register temp_reg = G3;
2969 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2970 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2971 MacroAssembler _masm(&cbuf);
2972 #ifdef ASSERT
2973 __ save_frame(0);
2974 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2975 __ sethi(last_rethrow_addrlit, L1);
2976 Address addr(L1, last_rethrow_addrlit.low10());
2977 __ rdpc(L2);
2978 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2979 __ st_ptr(L2, addr);
2980 __ restore();
2981 #endif
2982 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2983 __ delayed()->nop();
2984 %}
2985
2986 enc_class emit_mem_nop() %{
2987 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2988 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2989 %}
2990
2991 enc_class emit_fadd_nop() %{
2992 // Generates the instruction FMOVS f31,f31
2993 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2994 %}
2995
2996 enc_class emit_br_nop() %{
2997 // Generates the instruction BPN,PN .
2998 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2999 %}
3000
3001 enc_class enc_membar_acquire %{
3002 MacroAssembler _masm(&cbuf);
3003 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3004 %}
3005
3006 enc_class enc_membar_release %{
3007 MacroAssembler _masm(&cbuf);
3008 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3009 %}
3010
3011 enc_class enc_membar_volatile %{
3012 MacroAssembler _masm(&cbuf);
3013 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3014 %}
3015
3016 %}
3017
3018 //----------FRAME--------------------------------------------------------------
3019 // Definition of frame structure and management information.
3020 //
3021 // S T A C K L A Y O U T Allocators stack-slot number
3022 // | (to get allocators register number
3023 // G Owned by | | v add VMRegImpl::stack0)
3024 // r CALLER | |
3025 // o | +--------+ pad to even-align allocators stack-slot
3026 // w V | pad0 | numbers; owned by CALLER
3027 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3028 // h ^ | in | 5
3029 // | | args | 4 Holes in incoming args owned by SELF
3030 // | | | | 3
3031 // | | +--------+
3032 // V | | old out| Empty on Intel, window on Sparc
3033 // | old |preserve| Must be even aligned.
3034 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3035 // | | in | 3 area for Intel ret address
3036 // Owned by |preserve| Empty on Sparc.
3037 // SELF +--------+
3038 // | | pad2 | 2 pad to align old SP
3039 // | +--------+ 1
3040 // | | locks | 0
3041 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3042 // | | pad1 | 11 pad to align new SP
3043 // | +--------+
3044 // | | | 10
3045 // | | spills | 9 spills
3046 // V | | 8 (pad0 slot for callee)
3047 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3048 // ^ | out | 7
3049 // | | args | 6 Holes in outgoing args owned by CALLEE
3050 // Owned by +--------+
3051 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3052 // | new |preserve| Must be even-aligned.
3053 // | SP-+--------+----> Matcher::_new_SP, even aligned
3054 // | | |
3055 //
3056 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3057 // known from SELF's arguments and the Java calling convention.
3058 // Region 6-7 is determined per call site.
3059 // Note 2: If the calling convention leaves holes in the incoming argument
3060 // area, those holes are owned by SELF. Holes in the outgoing area
3061 // are owned by the CALLEE. Holes should not be nessecary in the
3062 // incoming area, as the Java calling convention is completely under
3063 // the control of the AD file. Doubles can be sorted and packed to
3064 // avoid holes. Holes in the outgoing arguments may be necessary for
3065 // varargs C calling conventions.
3066 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3067 // even aligned with pad0 as needed.
3068 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3069 // region 6-11 is even aligned; it may be padded out more so that
3070 // the region from SP to FP meets the minimum stack alignment.
3071
3072 frame %{
3073 // What direction does stack grow in (assumed to be same for native & Java)
3074 stack_direction(TOWARDS_LOW);
3075
3076 // These two registers define part of the calling convention
3077 // between compiled code and the interpreter.
3078 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3079 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3080
3081 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3082 cisc_spilling_operand_name(indOffset);
3083
3084 // Number of stack slots consumed by a Monitor enter
3085 #ifdef _LP64
3086 sync_stack_slots(2);
3087 #else
3088 sync_stack_slots(1);
3089 #endif
3090
3091 // Compiled code's Frame Pointer
3092 frame_pointer(R_SP);
3093
3094 // Stack alignment requirement
3095 stack_alignment(StackAlignmentInBytes);
3096 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3097 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3098
3099 // Number of stack slots between incoming argument block and the start of
3100 // a new frame. The PROLOG must add this many slots to the stack. The
3101 // EPILOG must remove this many slots.
3102 in_preserve_stack_slots(0);
3103
3104 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3105 // for calls to C. Supports the var-args backing area for register parms.
3106 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3107 #ifdef _LP64
3108 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3109 varargs_C_out_slots_killed(12);
3110 #else
3111 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3112 varargs_C_out_slots_killed( 7);
3113 #endif
3114
3115 // The after-PROLOG location of the return address. Location of
3116 // return address specifies a type (REG or STACK) and a number
3117 // representing the register number (i.e. - use a register name) or
3118 // stack slot.
3119 return_addr(REG R_I7); // Ret Addr is in register I7
3120
3121 // Body of function which returns an OptoRegs array locating
3122 // arguments either in registers or in stack slots for calling
3123 // java
3124 calling_convention %{
3125 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3126
3127 %}
3128
3129 // Body of function which returns an OptoRegs array locating
3130 // arguments either in registers or in stack slots for calling
3131 // C.
3132 c_calling_convention %{
3133 // This is obviously always outgoing
3134 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3135 %}
3136
3137 // Location of native (C/C++) and interpreter return values. This is specified to
3138 // be the same as Java. In the 32-bit VM, long values are actually returned from
3139 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3140 // to and from the register pairs is done by the appropriate call and epilog
3141 // opcodes. This simplifies the register allocator.
3142 c_return_value %{
3143 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3144 #ifdef _LP64
3145 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3146 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3147 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3148 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3149 #else // !_LP64
3150 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3151 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3152 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3153 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3154 #endif
3155 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3156 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3157 %}
3158
3159 // Location of compiled Java return values. Same as C
3160 return_value %{
3161 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3162 #ifdef _LP64
3163 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3164 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3165 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3166 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3167 #else // !_LP64
3168 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3169 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3170 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3171 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3172 #endif
3173 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3174 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3175 %}
3176
3177 %}
3178
3179
3180 //----------ATTRIBUTES---------------------------------------------------------
3181 //----------Operand Attributes-------------------------------------------------
3182 op_attrib op_cost(1); // Required cost attribute
3183
3184 //----------Instruction Attributes---------------------------------------------
3185 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3186 ins_attrib ins_size(32); // Required size attribute (in bits)
3187
3188 // avoid_back_to_back attribute is an expression that must return
3189 // one of the following values defined in MachNode:
3190 // AVOID_NONE - instruction can be placed anywhere
3191 // AVOID_BEFORE - instruction cannot be placed after an
3192 // instruction with MachNode::AVOID_AFTER
3193 // AVOID_AFTER - the next instruction cannot be the one
3194 // with MachNode::AVOID_BEFORE
3195 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3196 // the same time
3197 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3198
3199 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3200 // non-matching short branch variant of some
3201 // long branch?
3202
3203 //----------OPERANDS-----------------------------------------------------------
3204 // Operand definitions must precede instruction definitions for correct parsing
3205 // in the ADLC because operands constitute user defined types which are used in
3206 // instruction definitions.
3207
3208 //----------Simple Operands----------------------------------------------------
3209 // Immediate Operands
3210 // Integer Immediate: 32-bit
3211 operand immI() %{
3212 match(ConI);
3213
3214 op_cost(0);
3215 // formats are generated automatically for constants and base registers
3216 format %{ %}
3217 interface(CONST_INTER);
3218 %}
3219
3220 // Integer Immediate: 0-bit
3221 operand immI0() %{
3222 predicate(n->get_int() == 0);
3223 match(ConI);
3224 op_cost(0);
3225
3226 format %{ %}
3227 interface(CONST_INTER);
3228 %}
3229
3230 // Integer Immediate: 5-bit
3231 operand immI5() %{
3232 predicate(Assembler::is_simm5(n->get_int()));
3233 match(ConI);
3234 op_cost(0);
3235 format %{ %}
3236 interface(CONST_INTER);
3237 %}
3238
3239 // Integer Immediate: 8-bit
3240 operand immI8() %{
3241 predicate(Assembler::is_simm8(n->get_int()));
3242 match(ConI);
3243 op_cost(0);
3244 format %{ %}
3245 interface(CONST_INTER);
3246 %}
3247
3248 // Integer Immediate: the value 10
3249 operand immI10() %{
3250 predicate(n->get_int() == 10);
3251 match(ConI);
3252 op_cost(0);
3253
3254 format %{ %}
3255 interface(CONST_INTER);
3256 %}
3257
3258 // Integer Immediate: 11-bit
3259 operand immI11() %{
3260 predicate(Assembler::is_simm11(n->get_int()));
3261 match(ConI);
3262 op_cost(0);
3263 format %{ %}
3264 interface(CONST_INTER);
3265 %}
3266
3267 // Integer Immediate: 13-bit
3268 operand immI13() %{
3269 predicate(Assembler::is_simm13(n->get_int()));
3270 match(ConI);
3271 op_cost(0);
3272
3273 format %{ %}
3274 interface(CONST_INTER);
3275 %}
3276
3277 // Integer Immediate: 13-bit minus 7
3278 operand immI13m7() %{
3279 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3280 match(ConI);
3281 op_cost(0);
3282
3283 format %{ %}
3284 interface(CONST_INTER);
3285 %}
3286
3287 // Integer Immediate: 16-bit
3288 operand immI16() %{
3289 predicate(Assembler::is_simm16(n->get_int()));
3290 match(ConI);
3291 op_cost(0);
3292 format %{ %}
3293 interface(CONST_INTER);
3294 %}
3295
3296 // Integer Immediate: the values 1-31
3297 operand immI_1_31() %{
3298 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3299 match(ConI);
3300 op_cost(0);
3301
3302 format %{ %}
3303 interface(CONST_INTER);
3304 %}
3305
3306 // Integer Immediate: the values 32-63
3307 operand immI_32_63() %{
3308 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3309 match(ConI);
3310 op_cost(0);
3311
3312 format %{ %}
3313 interface(CONST_INTER);
3314 %}
3315
3316 // Immediates for special shifts (sign extend)
3317
3318 // Integer Immediate: the value 16
3319 operand immI_16() %{
3320 predicate(n->get_int() == 16);
3321 match(ConI);
3322 op_cost(0);
3323
3324 format %{ %}
3325 interface(CONST_INTER);
3326 %}
3327
3328 // Integer Immediate: the value 24
3329 operand immI_24() %{
3330 predicate(n->get_int() == 24);
3331 match(ConI);
3332 op_cost(0);
3333
3334 format %{ %}
3335 interface(CONST_INTER);
3336 %}
3337 // Integer Immediate: the value 255
3338 operand immI_255() %{
3339 predicate( n->get_int() == 255 );
3340 match(ConI);
3341 op_cost(0);
3342
3343 format %{ %}
3344 interface(CONST_INTER);
3345 %}
3346
3347 // Integer Immediate: the value 65535
3348 operand immI_65535() %{
3349 predicate(n->get_int() == 65535);
3350 match(ConI);
3351 op_cost(0);
3352
3353 format %{ %}
3354 interface(CONST_INTER);
3355 %}
3356
3357 // Integer Immediate: the values 0-31
3358 operand immU5() %{
3359 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3360 match(ConI);
3361 op_cost(0);
3362
3363 format %{ %}
3364 interface(CONST_INTER);
3365 %}
3366
3367 // Integer Immediate: 6-bit
3368 operand immU6() %{
3369 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3370 match(ConI);
3371 op_cost(0);
3372 format %{ %}
3373 interface(CONST_INTER);
3374 %}
3375
3376 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3377 operand immU12() %{
3378 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3379 match(ConI);
3380 op_cost(0);
3381
3382 format %{ %}
3383 interface(CONST_INTER);
3384 %}
3385
3386 // Integer Immediate non-negative
3387 operand immU31()
3388 %{
3389 predicate(n->get_int() >= 0);
3390 match(ConI);
3391
3392 op_cost(0);
3393 format %{ %}
3394 interface(CONST_INTER);
3395 %}
3396
3397 // Long Immediate: the value FF
3398 operand immL_FF() %{
3399 predicate( n->get_long() == 0xFFL );
3400 match(ConL);
3401 op_cost(0);
3402
3403 format %{ %}
3404 interface(CONST_INTER);
3405 %}
3406
3407 // Long Immediate: the value FFFF
3408 operand immL_FFFF() %{
3409 predicate( n->get_long() == 0xFFFFL );
3410 match(ConL);
3411 op_cost(0);
3412
3413 format %{ %}
3414 interface(CONST_INTER);
3415 %}
3416
3417 // Pointer Immediate: 32 or 64-bit
3418 operand immP() %{
3419 match(ConP);
3420
3421 op_cost(5);
3422 // formats are generated automatically for constants and base registers
3423 format %{ %}
3424 interface(CONST_INTER);
3425 %}
3426
3427 #ifdef _LP64
3428 // Pointer Immediate: 64-bit
3429 operand immP_set() %{
3430 predicate(!VM_Version::is_niagara_plus());
3431 match(ConP);
3432
3433 op_cost(5);
3434 // formats are generated automatically for constants and base registers
3435 format %{ %}
3436 interface(CONST_INTER);
3437 %}
3438
3439 // Pointer Immediate: 64-bit
3440 // From Niagara2 processors on a load should be better than materializing.
3441 operand immP_load() %{
3442 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3443 match(ConP);
3444
3445 op_cost(5);
3446 // formats are generated automatically for constants and base registers
3447 format %{ %}
3448 interface(CONST_INTER);
3449 %}
3450
3451 // Pointer Immediate: 64-bit
3452 operand immP_no_oop_cheap() %{
3453 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3454 match(ConP);
3455
3456 op_cost(5);
3457 // formats are generated automatically for constants and base registers
3458 format %{ %}
3459 interface(CONST_INTER);
3460 %}
3461 #endif
3462
3463 operand immP13() %{
3464 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3465 match(ConP);
3466 op_cost(0);
3467
3468 format %{ %}
3469 interface(CONST_INTER);
3470 %}
3471
3472 operand immP0() %{
3473 predicate(n->get_ptr() == 0);
3474 match(ConP);
3475 op_cost(0);
3476
3477 format %{ %}
3478 interface(CONST_INTER);
3479 %}
3480
3481 operand immP_poll() %{
3482 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3483 match(ConP);
3484
3485 // formats are generated automatically for constants and base registers
3486 format %{ %}
3487 interface(CONST_INTER);
3488 %}
3489
3490 // Pointer Immediate
3491 operand immN()
3492 %{
3493 match(ConN);
3494
3495 op_cost(10);
3496 format %{ %}
3497 interface(CONST_INTER);
3498 %}
3499
3500 operand immNKlass()
3501 %{
3502 match(ConNKlass);
3503
3504 op_cost(10);
3505 format %{ %}
3506 interface(CONST_INTER);
3507 %}
3508
3509 // NULL Pointer Immediate
3510 operand immN0()
3511 %{
3512 predicate(n->get_narrowcon() == 0);
3513 match(ConN);
3514
3515 op_cost(0);
3516 format %{ %}
3517 interface(CONST_INTER);
3518 %}
3519
3520 operand immL() %{
3521 match(ConL);
3522 op_cost(40);
3523 // formats are generated automatically for constants and base registers
3524 format %{ %}
3525 interface(CONST_INTER);
3526 %}
3527
3528 operand immL0() %{
3529 predicate(n->get_long() == 0L);
3530 match(ConL);
3531 op_cost(0);
3532 // formats are generated automatically for constants and base registers
3533 format %{ %}
3534 interface(CONST_INTER);
3535 %}
3536
3537 // Integer Immediate: 5-bit
3538 operand immL5() %{
3539 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3540 match(ConL);
3541 op_cost(0);
3542 format %{ %}
3543 interface(CONST_INTER);
3544 %}
3545
3546 // Long Immediate: 13-bit
3547 operand immL13() %{
3548 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3549 match(ConL);
3550 op_cost(0);
3551
3552 format %{ %}
3553 interface(CONST_INTER);
3554 %}
3555
3556 // Long Immediate: 13-bit minus 7
3557 operand immL13m7() %{
3558 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3559 match(ConL);
3560 op_cost(0);
3561
3562 format %{ %}
3563 interface(CONST_INTER);
3564 %}
3565
3566 // Long Immediate: low 32-bit mask
3567 operand immL_32bits() %{
3568 predicate(n->get_long() == 0xFFFFFFFFL);
3569 match(ConL);
3570 op_cost(0);
3571
3572 format %{ %}
3573 interface(CONST_INTER);
3574 %}
3575
3576 // Long Immediate: cheap (materialize in <= 3 instructions)
3577 operand immL_cheap() %{
3578 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3579 match(ConL);
3580 op_cost(0);
3581
3582 format %{ %}
3583 interface(CONST_INTER);
3584 %}
3585
3586 // Long Immediate: expensive (materialize in > 3 instructions)
3587 operand immL_expensive() %{
3588 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3589 match(ConL);
3590 op_cost(0);
3591
3592 format %{ %}
3593 interface(CONST_INTER);
3594 %}
3595
3596 // Double Immediate
3597 operand immD() %{
3598 match(ConD);
3599
3600 op_cost(40);
3601 format %{ %}
3602 interface(CONST_INTER);
3603 %}
3604
3605 // Double Immediate: +0.0d
3606 operand immD0() %{
3607 predicate(jlong_cast(n->getd()) == 0);
3608 match(ConD);
3609
3610 op_cost(0);
3611 format %{ %}
3612 interface(CONST_INTER);
3613 %}
3614
3615 // Float Immediate
3616 operand immF() %{
3617 match(ConF);
3618
3619 op_cost(20);
3620 format %{ %}
3621 interface(CONST_INTER);
3622 %}
3623
3624 // Float Immediate: +0.0f
3625 operand immF0() %{
3626 predicate(jint_cast(n->getf()) == 0);
3627 match(ConF);
3628
3629 op_cost(0);
3630 format %{ %}
3631 interface(CONST_INTER);
3632 %}
3633
3634 // Integer Register Operands
3635 // Integer Register
3636 operand iRegI() %{
3637 constraint(ALLOC_IN_RC(int_reg));
3638 match(RegI);
3639
3640 match(notemp_iRegI);
3641 match(g1RegI);
3642 match(o0RegI);
3643 match(iRegIsafe);
3644
3645 format %{ %}
3646 interface(REG_INTER);
3647 %}
3648
3649 operand notemp_iRegI() %{
3650 constraint(ALLOC_IN_RC(notemp_int_reg));
3651 match(RegI);
3652
3653 match(o0RegI);
3654
3655 format %{ %}
3656 interface(REG_INTER);
3657 %}
3658
3659 operand o0RegI() %{
3660 constraint(ALLOC_IN_RC(o0_regI));
3661 match(iRegI);
3662
3663 format %{ %}
3664 interface(REG_INTER);
3665 %}
3666
3667 // Pointer Register
3668 operand iRegP() %{
3669 constraint(ALLOC_IN_RC(ptr_reg));
3670 match(RegP);
3671
3672 match(lock_ptr_RegP);
3673 match(g1RegP);
3674 match(g2RegP);
3675 match(g3RegP);
3676 match(g4RegP);
3677 match(i0RegP);
3678 match(o0RegP);
3679 match(o1RegP);
3680 match(l7RegP);
3681
3682 format %{ %}
3683 interface(REG_INTER);
3684 %}
3685
3686 operand sp_ptr_RegP() %{
3687 constraint(ALLOC_IN_RC(sp_ptr_reg));
3688 match(RegP);
3689 match(iRegP);
3690
3691 format %{ %}
3692 interface(REG_INTER);
3693 %}
3694
3695 operand lock_ptr_RegP() %{
3696 constraint(ALLOC_IN_RC(lock_ptr_reg));
3697 match(RegP);
3698 match(i0RegP);
3699 match(o0RegP);
3700 match(o1RegP);
3701 match(l7RegP);
3702
3703 format %{ %}
3704 interface(REG_INTER);
3705 %}
3706
3707 operand g1RegP() %{
3708 constraint(ALLOC_IN_RC(g1_regP));
3709 match(iRegP);
3710
3711 format %{ %}
3712 interface(REG_INTER);
3713 %}
3714
3715 operand g2RegP() %{
3716 constraint(ALLOC_IN_RC(g2_regP));
3717 match(iRegP);
3718
3719 format %{ %}
3720 interface(REG_INTER);
3721 %}
3722
3723 operand g3RegP() %{
3724 constraint(ALLOC_IN_RC(g3_regP));
3725 match(iRegP);
3726
3727 format %{ %}
3728 interface(REG_INTER);
3729 %}
3730
3731 operand g1RegI() %{
3732 constraint(ALLOC_IN_RC(g1_regI));
3733 match(iRegI);
3734
3735 format %{ %}
3736 interface(REG_INTER);
3737 %}
3738
3739 operand g3RegI() %{
3740 constraint(ALLOC_IN_RC(g3_regI));
3741 match(iRegI);
3742
3743 format %{ %}
3744 interface(REG_INTER);
3745 %}
3746
3747 operand g4RegI() %{
3748 constraint(ALLOC_IN_RC(g4_regI));
3749 match(iRegI);
3750
3751 format %{ %}
3752 interface(REG_INTER);
3753 %}
3754
3755 operand g4RegP() %{
3756 constraint(ALLOC_IN_RC(g4_regP));
3757 match(iRegP);
3758
3759 format %{ %}
3760 interface(REG_INTER);
3761 %}
3762
3763 operand i0RegP() %{
3764 constraint(ALLOC_IN_RC(i0_regP));
3765 match(iRegP);
3766
3767 format %{ %}
3768 interface(REG_INTER);
3769 %}
3770
3771 operand o0RegP() %{
3772 constraint(ALLOC_IN_RC(o0_regP));
3773 match(iRegP);
3774
3775 format %{ %}
3776 interface(REG_INTER);
3777 %}
3778
3779 operand o1RegP() %{
3780 constraint(ALLOC_IN_RC(o1_regP));
3781 match(iRegP);
3782
3783 format %{ %}
3784 interface(REG_INTER);
3785 %}
3786
3787 operand o2RegP() %{
3788 constraint(ALLOC_IN_RC(o2_regP));
3789 match(iRegP);
3790
3791 format %{ %}
3792 interface(REG_INTER);
3793 %}
3794
3795 operand o7RegP() %{
3796 constraint(ALLOC_IN_RC(o7_regP));
3797 match(iRegP);
3798
3799 format %{ %}
3800 interface(REG_INTER);
3801 %}
3802
3803 operand l7RegP() %{
3804 constraint(ALLOC_IN_RC(l7_regP));
3805 match(iRegP);
3806
3807 format %{ %}
3808 interface(REG_INTER);
3809 %}
3810
3811 operand o7RegI() %{
3812 constraint(ALLOC_IN_RC(o7_regI));
3813 match(iRegI);
3814
3815 format %{ %}
3816 interface(REG_INTER);
3817 %}
3818
3819 operand iRegN() %{
3820 constraint(ALLOC_IN_RC(int_reg));
3821 match(RegN);
3822
3823 format %{ %}
3824 interface(REG_INTER);
3825 %}
3826
3827 // Long Register
3828 operand iRegL() %{
3829 constraint(ALLOC_IN_RC(long_reg));
3830 match(RegL);
3831
3832 format %{ %}
3833 interface(REG_INTER);
3834 %}
3835
3836 operand o2RegL() %{
3837 constraint(ALLOC_IN_RC(o2_regL));
3838 match(iRegL);
3839
3840 format %{ %}
3841 interface(REG_INTER);
3842 %}
3843
3844 operand o7RegL() %{
3845 constraint(ALLOC_IN_RC(o7_regL));
3846 match(iRegL);
3847
3848 format %{ %}
3849 interface(REG_INTER);
3850 %}
3851
3852 operand g1RegL() %{
3853 constraint(ALLOC_IN_RC(g1_regL));
3854 match(iRegL);
3855
3856 format %{ %}
3857 interface(REG_INTER);
3858 %}
3859
3860 operand g3RegL() %{
3861 constraint(ALLOC_IN_RC(g3_regL));
3862 match(iRegL);
3863
3864 format %{ %}
3865 interface(REG_INTER);
3866 %}
3867
3868 // Int Register safe
3869 // This is 64bit safe
3870 operand iRegIsafe() %{
3871 constraint(ALLOC_IN_RC(long_reg));
3872
3873 match(iRegI);
3874
3875 format %{ %}
3876 interface(REG_INTER);
3877 %}
3878
3879 // Condition Code Flag Register
3880 operand flagsReg() %{
3881 constraint(ALLOC_IN_RC(int_flags));
3882 match(RegFlags);
3883
3884 format %{ "ccr" %} // both ICC and XCC
3885 interface(REG_INTER);
3886 %}
3887
3888 // Condition Code Register, unsigned comparisons.
3889 operand flagsRegU() %{
3890 constraint(ALLOC_IN_RC(int_flags));
3891 match(RegFlags);
3892
3893 format %{ "icc_U" %}
3894 interface(REG_INTER);
3895 %}
3896
3897 // Condition Code Register, pointer comparisons.
3898 operand flagsRegP() %{
3899 constraint(ALLOC_IN_RC(int_flags));
3900 match(RegFlags);
3901
3902 #ifdef _LP64
3903 format %{ "xcc_P" %}
3904 #else
3905 format %{ "icc_P" %}
3906 #endif
3907 interface(REG_INTER);
3908 %}
3909
3910 // Condition Code Register, long comparisons.
3911 operand flagsRegL() %{
3912 constraint(ALLOC_IN_RC(int_flags));
3913 match(RegFlags);
3914
3915 format %{ "xcc_L" %}
3916 interface(REG_INTER);
3917 %}
3918
3919 // Condition Code Register, floating comparisons, unordered same as "less".
3920 operand flagsRegF() %{
3921 constraint(ALLOC_IN_RC(float_flags));
3922 match(RegFlags);
3923 match(flagsRegF0);
3924
3925 format %{ %}
3926 interface(REG_INTER);
3927 %}
3928
3929 operand flagsRegF0() %{
3930 constraint(ALLOC_IN_RC(float_flag0));
3931 match(RegFlags);
3932
3933 format %{ %}
3934 interface(REG_INTER);
3935 %}
3936
3937
3938 // Condition Code Flag Register used by long compare
3939 operand flagsReg_long_LTGE() %{
3940 constraint(ALLOC_IN_RC(int_flags));
3941 match(RegFlags);
3942 format %{ "icc_LTGE" %}
3943 interface(REG_INTER);
3944 %}
3945 operand flagsReg_long_EQNE() %{
3946 constraint(ALLOC_IN_RC(int_flags));
3947 match(RegFlags);
3948 format %{ "icc_EQNE" %}
3949 interface(REG_INTER);
3950 %}
3951 operand flagsReg_long_LEGT() %{
3952 constraint(ALLOC_IN_RC(int_flags));
3953 match(RegFlags);
3954 format %{ "icc_LEGT" %}
3955 interface(REG_INTER);
3956 %}
3957
3958
3959 operand regD() %{
3960 constraint(ALLOC_IN_RC(dflt_reg));
3961 match(RegD);
3962
3963 match(regD_low);
3964
3965 format %{ %}
3966 interface(REG_INTER);
3967 %}
3968
3969 operand regF() %{
3970 constraint(ALLOC_IN_RC(sflt_reg));
3971 match(RegF);
3972
3973 format %{ %}
3974 interface(REG_INTER);
3975 %}
3976
3977 operand regD_low() %{
3978 constraint(ALLOC_IN_RC(dflt_low_reg));
3979 match(regD);
3980
3981 format %{ %}
3982 interface(REG_INTER);
3983 %}
3984
3985 // Special Registers
3986
3987 // Method Register
3988 operand inline_cache_regP(iRegP reg) %{
3989 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3990 match(reg);
3991 format %{ %}
3992 interface(REG_INTER);
3993 %}
3994
3995 operand interpreter_method_oop_regP(iRegP reg) %{
3996 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3997 match(reg);
3998 format %{ %}
3999 interface(REG_INTER);
4000 %}
4001
4002
4003 //----------Complex Operands---------------------------------------------------
4004 // Indirect Memory Reference
4005 operand indirect(sp_ptr_RegP reg) %{
4006 constraint(ALLOC_IN_RC(sp_ptr_reg));
4007 match(reg);
4008
4009 op_cost(100);
4010 format %{ "[$reg]" %}
4011 interface(MEMORY_INTER) %{
4012 base($reg);
4013 index(0x0);
4014 scale(0x0);
4015 disp(0x0);
4016 %}
4017 %}
4018
4019 // Indirect with simm13 Offset
4020 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4021 constraint(ALLOC_IN_RC(sp_ptr_reg));
4022 match(AddP reg offset);
4023
4024 op_cost(100);
4025 format %{ "[$reg + $offset]" %}
4026 interface(MEMORY_INTER) %{
4027 base($reg);
4028 index(0x0);
4029 scale(0x0);
4030 disp($offset);
4031 %}
4032 %}
4033
4034 // Indirect with simm13 Offset minus 7
4035 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4036 constraint(ALLOC_IN_RC(sp_ptr_reg));
4037 match(AddP reg offset);
4038
4039 op_cost(100);
4040 format %{ "[$reg + $offset]" %}
4041 interface(MEMORY_INTER) %{
4042 base($reg);
4043 index(0x0);
4044 scale(0x0);
4045 disp($offset);
4046 %}
4047 %}
4048
4049 // Note: Intel has a swapped version also, like this:
4050 //operand indOffsetX(iRegI reg, immP offset) %{
4051 // constraint(ALLOC_IN_RC(int_reg));
4052 // match(AddP offset reg);
4053 //
4054 // op_cost(100);
4055 // format %{ "[$reg + $offset]" %}
4056 // interface(MEMORY_INTER) %{
4057 // base($reg);
4058 // index(0x0);
4059 // scale(0x0);
4060 // disp($offset);
4061 // %}
4062 //%}
4063 //// However, it doesn't make sense for SPARC, since
4064 // we have no particularly good way to embed oops in
4065 // single instructions.
4066
4067 // Indirect with Register Index
4068 operand indIndex(iRegP addr, iRegX index) %{
4069 constraint(ALLOC_IN_RC(ptr_reg));
4070 match(AddP addr index);
4071
4072 op_cost(100);
4073 format %{ "[$addr + $index]" %}
4074 interface(MEMORY_INTER) %{
4075 base($addr);
4076 index($index);
4077 scale(0x0);
4078 disp(0x0);
4079 %}
4080 %}
4081
4082 //----------Special Memory Operands--------------------------------------------
4083 // Stack Slot Operand - This operand is used for loading and storing temporary
4084 // values on the stack where a match requires a value to
4085 // flow through memory.
4086 operand stackSlotI(sRegI reg) %{
4087 constraint(ALLOC_IN_RC(stack_slots));
4088 op_cost(100);
4089 //match(RegI);
4090 format %{ "[$reg]" %}
4091 interface(MEMORY_INTER) %{
4092 base(0xE); // R_SP
4093 index(0x0);
4094 scale(0x0);
4095 disp($reg); // Stack Offset
4096 %}
4097 %}
4098
4099 operand stackSlotP(sRegP reg) %{
4100 constraint(ALLOC_IN_RC(stack_slots));
4101 op_cost(100);
4102 //match(RegP);
4103 format %{ "[$reg]" %}
4104 interface(MEMORY_INTER) %{
4105 base(0xE); // R_SP
4106 index(0x0);
4107 scale(0x0);
4108 disp($reg); // Stack Offset
4109 %}
4110 %}
4111
4112 operand stackSlotF(sRegF reg) %{
4113 constraint(ALLOC_IN_RC(stack_slots));
4114 op_cost(100);
4115 //match(RegF);
4116 format %{ "[$reg]" %}
4117 interface(MEMORY_INTER) %{
4118 base(0xE); // R_SP
4119 index(0x0);
4120 scale(0x0);
4121 disp($reg); // Stack Offset
4122 %}
4123 %}
4124 operand stackSlotD(sRegD reg) %{
4125 constraint(ALLOC_IN_RC(stack_slots));
4126 op_cost(100);
4127 //match(RegD);
4128 format %{ "[$reg]" %}
4129 interface(MEMORY_INTER) %{
4130 base(0xE); // R_SP
4131 index(0x0);
4132 scale(0x0);
4133 disp($reg); // Stack Offset
4134 %}
4135 %}
4136 operand stackSlotL(sRegL reg) %{
4137 constraint(ALLOC_IN_RC(stack_slots));
4138 op_cost(100);
4139 //match(RegL);
4140 format %{ "[$reg]" %}
4141 interface(MEMORY_INTER) %{
4142 base(0xE); // R_SP
4143 index(0x0);
4144 scale(0x0);
4145 disp($reg); // Stack Offset
4146 %}
4147 %}
4148
4149 // Operands for expressing Control Flow
4150 // NOTE: Label is a predefined operand which should not be redefined in
4151 // the AD file. It is generically handled within the ADLC.
4152
4153 //----------Conditional Branch Operands----------------------------------------
4154 // Comparison Op - This is the operation of the comparison, and is limited to
4155 // the following set of codes:
4156 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4157 //
4158 // Other attributes of the comparison, such as unsignedness, are specified
4159 // by the comparison instruction that sets a condition code flags register.
4160 // That result is represented by a flags operand whose subtype is appropriate
4161 // to the unsignedness (etc.) of the comparison.
4162 //
4163 // Later, the instruction which matches both the Comparison Op (a Bool) and
4164 // the flags (produced by the Cmp) specifies the coding of the comparison op
4165 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4166
4167 operand cmpOp() %{
4168 match(Bool);
4169
4170 format %{ "" %}
4171 interface(COND_INTER) %{
4172 equal(0x1);
4173 not_equal(0x9);
4174 less(0x3);
4175 greater_equal(0xB);
4176 less_equal(0x2);
4177 greater(0xA);
4178 overflow(0x7);
4179 no_overflow(0xF);
4180 %}
4181 %}
4182
4183 // Comparison Op, unsigned
4184 operand cmpOpU() %{
4185 match(Bool);
4186 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4187 n->as_Bool()->_test._test != BoolTest::no_overflow);
4188
4189 format %{ "u" %}
4190 interface(COND_INTER) %{
4191 equal(0x1);
4192 not_equal(0x9);
4193 less(0x5);
4194 greater_equal(0xD);
4195 less_equal(0x4);
4196 greater(0xC);
4197 overflow(0x7);
4198 no_overflow(0xF);
4199 %}
4200 %}
4201
4202 // Comparison Op, pointer (same as unsigned)
4203 operand cmpOpP() %{
4204 match(Bool);
4205 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4206 n->as_Bool()->_test._test != BoolTest::no_overflow);
4207
4208 format %{ "p" %}
4209 interface(COND_INTER) %{
4210 equal(0x1);
4211 not_equal(0x9);
4212 less(0x5);
4213 greater_equal(0xD);
4214 less_equal(0x4);
4215 greater(0xC);
4216 overflow(0x7);
4217 no_overflow(0xF);
4218 %}
4219 %}
4220
4221 // Comparison Op, branch-register encoding
4222 operand cmpOp_reg() %{
4223 match(Bool);
4224 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4225 n->as_Bool()->_test._test != BoolTest::no_overflow);
4226
4227 format %{ "" %}
4228 interface(COND_INTER) %{
4229 equal (0x1);
4230 not_equal (0x5);
4231 less (0x3);
4232 greater_equal(0x7);
4233 less_equal (0x2);
4234 greater (0x6);
4235 overflow(0x7); // not supported
4236 no_overflow(0xF); // not supported
4237 %}
4238 %}
4239
4240 // Comparison Code, floating, unordered same as less
4241 operand cmpOpF() %{
4242 match(Bool);
4243 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4244 n->as_Bool()->_test._test != BoolTest::no_overflow);
4245
4246 format %{ "fl" %}
4247 interface(COND_INTER) %{
4248 equal(0x9);
4249 not_equal(0x1);
4250 less(0x3);
4251 greater_equal(0xB);
4252 less_equal(0xE);
4253 greater(0x6);
4254
4255 overflow(0x7); // not supported
4256 no_overflow(0xF); // not supported
4257 %}
4258 %}
4259
4260 // Used by long compare
4261 operand cmpOp_commute() %{
4262 match(Bool);
4263 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4264 n->as_Bool()->_test._test != BoolTest::no_overflow);
4265
4266 format %{ "" %}
4267 interface(COND_INTER) %{
4268 equal(0x1);
4269 not_equal(0x9);
4270 less(0xA);
4271 greater_equal(0x2);
4272 less_equal(0xB);
4273 greater(0x3);
4274 overflow(0x7);
4275 no_overflow(0xF);
4276 %}
4277 %}
4278
4279 //----------OPERAND CLASSES----------------------------------------------------
4280 // Operand Classes are groups of operands that are used to simplify
4281 // instruction definitions by not requiring the AD writer to specify separate
4282 // instructions for every form of operand when the instruction accepts
4283 // multiple operand types with the same basic encoding and format. The classic
4284 // case of this is memory operands.
4285 opclass memory( indirect, indOffset13, indIndex );
4286 opclass indIndexMemory( indIndex );
4287
4288 //----------PIPELINE-----------------------------------------------------------
4289 pipeline %{
4290
4291 //----------ATTRIBUTES---------------------------------------------------------
4292 attributes %{
4293 fixed_size_instructions; // Fixed size instructions
4294 branch_has_delay_slot; // Branch has delay slot following
4295 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4296 instruction_unit_size = 4; // An instruction is 4 bytes long
4297 instruction_fetch_unit_size = 16; // The processor fetches one line
4298 instruction_fetch_units = 1; // of 16 bytes
4299
4300 // List of nop instructions
4301 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4302 %}
4303
4304 //----------RESOURCES----------------------------------------------------------
4305 // Resources are the functional units available to the machine
4306 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4307
4308 //----------PIPELINE DESCRIPTION-----------------------------------------------
4309 // Pipeline Description specifies the stages in the machine's pipeline
4310
4311 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4312
4313 //----------PIPELINE CLASSES---------------------------------------------------
4314 // Pipeline Classes describe the stages in which input and output are
4315 // referenced by the hardware pipeline.
4316
4317 // Integer ALU reg-reg operation
4318 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4319 single_instruction;
4320 dst : E(write);
4321 src1 : R(read);
4322 src2 : R(read);
4323 IALU : R;
4324 %}
4325
4326 // Integer ALU reg-reg long operation
4327 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4328 instruction_count(2);
4329 dst : E(write);
4330 src1 : R(read);
4331 src2 : R(read);
4332 IALU : R;
4333 IALU : R;
4334 %}
4335
4336 // Integer ALU reg-reg long dependent operation
4337 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4338 instruction_count(1); multiple_bundles;
4339 dst : E(write);
4340 src1 : R(read);
4341 src2 : R(read);
4342 cr : E(write);
4343 IALU : R(2);
4344 %}
4345
4346 // Integer ALU reg-imm operaion
4347 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4348 single_instruction;
4349 dst : E(write);
4350 src1 : R(read);
4351 IALU : R;
4352 %}
4353
4354 // Integer ALU reg-reg operation with condition code
4355 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4356 single_instruction;
4357 dst : E(write);
4358 cr : E(write);
4359 src1 : R(read);
4360 src2 : R(read);
4361 IALU : R;
4362 %}
4363
4364 // Integer ALU reg-imm operation with condition code
4365 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4366 single_instruction;
4367 dst : E(write);
4368 cr : E(write);
4369 src1 : R(read);
4370 IALU : R;
4371 %}
4372
4373 // Integer ALU zero-reg operation
4374 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4375 single_instruction;
4376 dst : E(write);
4377 src2 : R(read);
4378 IALU : R;
4379 %}
4380
4381 // Integer ALU zero-reg operation with condition code only
4382 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4383 single_instruction;
4384 cr : E(write);
4385 src : R(read);
4386 IALU : R;
4387 %}
4388
4389 // Integer ALU reg-reg operation with condition code only
4390 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4391 single_instruction;
4392 cr : E(write);
4393 src1 : R(read);
4394 src2 : R(read);
4395 IALU : R;
4396 %}
4397
4398 // Integer ALU reg-imm operation with condition code only
4399 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4400 single_instruction;
4401 cr : E(write);
4402 src1 : R(read);
4403 IALU : R;
4404 %}
4405
4406 // Integer ALU reg-reg-zero operation with condition code only
4407 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4408 single_instruction;
4409 cr : E(write);
4410 src1 : R(read);
4411 src2 : R(read);
4412 IALU : R;
4413 %}
4414
4415 // Integer ALU reg-imm-zero operation with condition code only
4416 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4417 single_instruction;
4418 cr : E(write);
4419 src1 : R(read);
4420 IALU : R;
4421 %}
4422
4423 // Integer ALU reg-reg operation with condition code, src1 modified
4424 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4425 single_instruction;
4426 cr : E(write);
4427 src1 : E(write);
4428 src1 : R(read);
4429 src2 : R(read);
4430 IALU : R;
4431 %}
4432
4433 // Integer ALU reg-imm operation with condition code, src1 modified
4434 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4435 single_instruction;
4436 cr : E(write);
4437 src1 : E(write);
4438 src1 : R(read);
4439 IALU : R;
4440 %}
4441
4442 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4443 multiple_bundles;
4444 dst : E(write)+4;
4445 cr : E(write);
4446 src1 : R(read);
4447 src2 : R(read);
4448 IALU : R(3);
4449 BR : R(2);
4450 %}
4451
4452 // Integer ALU operation
4453 pipe_class ialu_none(iRegI dst) %{
4454 single_instruction;
4455 dst : E(write);
4456 IALU : R;
4457 %}
4458
4459 // Integer ALU reg operation
4460 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4461 single_instruction; may_have_no_code;
4462 dst : E(write);
4463 src : R(read);
4464 IALU : R;
4465 %}
4466
4467 // Integer ALU reg conditional operation
4468 // This instruction has a 1 cycle stall, and cannot execute
4469 // in the same cycle as the instruction setting the condition
4470 // code. We kludge this by pretending to read the condition code
4471 // 1 cycle earlier, and by marking the functional units as busy
4472 // for 2 cycles with the result available 1 cycle later than
4473 // is really the case.
4474 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4475 single_instruction;
4476 op2_out : C(write);
4477 op1 : R(read);
4478 cr : R(read); // This is really E, with a 1 cycle stall
4479 BR : R(2);
4480 MS : R(2);
4481 %}
4482
4483 #ifdef _LP64
4484 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4485 instruction_count(1); multiple_bundles;
4486 dst : C(write)+1;
4487 src : R(read)+1;
4488 IALU : R(1);
4489 BR : E(2);
4490 MS : E(2);
4491 %}
4492 #endif
4493
4494 // Integer ALU reg operation
4495 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4496 single_instruction; may_have_no_code;
4497 dst : E(write);
4498 src : R(read);
4499 IALU : R;
4500 %}
4501 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4502 single_instruction; may_have_no_code;
4503 dst : E(write);
4504 src : R(read);
4505 IALU : R;
4506 %}
4507
4508 // Two integer ALU reg operations
4509 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4510 instruction_count(2);
4511 dst : E(write);
4512 src : R(read);
4513 A0 : R;
4514 A1 : R;
4515 %}
4516
4517 // Two integer ALU reg operations
4518 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4519 instruction_count(2); may_have_no_code;
4520 dst : E(write);
4521 src : R(read);
4522 A0 : R;
4523 A1 : R;
4524 %}
4525
4526 // Integer ALU imm operation
4527 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4528 single_instruction;
4529 dst : E(write);
4530 IALU : R;
4531 %}
4532
4533 // Integer ALU reg-reg with carry operation
4534 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4535 single_instruction;
4536 dst : E(write);
4537 src1 : R(read);
4538 src2 : R(read);
4539 IALU : R;
4540 %}
4541
4542 // Integer ALU cc operation
4543 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4544 single_instruction;
4545 dst : E(write);
4546 cc : R(read);
4547 IALU : R;
4548 %}
4549
4550 // Integer ALU cc / second IALU operation
4551 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4552 instruction_count(1); multiple_bundles;
4553 dst : E(write)+1;
4554 src : R(read);
4555 IALU : R;
4556 %}
4557
4558 // Integer ALU cc / second IALU operation
4559 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4560 instruction_count(1); multiple_bundles;
4561 dst : E(write)+1;
4562 p : R(read);
4563 q : R(read);
4564 IALU : R;
4565 %}
4566
4567 // Integer ALU hi-lo-reg operation
4568 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4569 instruction_count(1); multiple_bundles;
4570 dst : E(write)+1;
4571 IALU : R(2);
4572 %}
4573
4574 // Float ALU hi-lo-reg operation (with temp)
4575 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4576 instruction_count(1); multiple_bundles;
4577 dst : E(write)+1;
4578 IALU : R(2);
4579 %}
4580
4581 // Long Constant
4582 pipe_class loadConL( iRegL dst, immL src ) %{
4583 instruction_count(2); multiple_bundles;
4584 dst : E(write)+1;
4585 IALU : R(2);
4586 IALU : R(2);
4587 %}
4588
4589 // Pointer Constant
4590 pipe_class loadConP( iRegP dst, immP src ) %{
4591 instruction_count(0); multiple_bundles;
4592 fixed_latency(6);
4593 %}
4594
4595 // Polling Address
4596 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4597 #ifdef _LP64
4598 instruction_count(0); multiple_bundles;
4599 fixed_latency(6);
4600 #else
4601 dst : E(write);
4602 IALU : R;
4603 #endif
4604 %}
4605
4606 // Long Constant small
4607 pipe_class loadConLlo( iRegL dst, immL src ) %{
4608 instruction_count(2);
4609 dst : E(write);
4610 IALU : R;
4611 IALU : R;
4612 %}
4613
4614 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4615 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4616 instruction_count(1); multiple_bundles;
4617 src : R(read);
4618 dst : M(write)+1;
4619 IALU : R;
4620 MS : E;
4621 %}
4622
4623 // Integer ALU nop operation
4624 pipe_class ialu_nop() %{
4625 single_instruction;
4626 IALU : R;
4627 %}
4628
4629 // Integer ALU nop operation
4630 pipe_class ialu_nop_A0() %{
4631 single_instruction;
4632 A0 : R;
4633 %}
4634
4635 // Integer ALU nop operation
4636 pipe_class ialu_nop_A1() %{
4637 single_instruction;
4638 A1 : R;
4639 %}
4640
4641 // Integer Multiply reg-reg operation
4642 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4643 single_instruction;
4644 dst : E(write);
4645 src1 : R(read);
4646 src2 : R(read);
4647 MS : R(5);
4648 %}
4649
4650 // Integer Multiply reg-imm operation
4651 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4652 single_instruction;
4653 dst : E(write);
4654 src1 : R(read);
4655 MS : R(5);
4656 %}
4657
4658 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4659 single_instruction;
4660 dst : E(write)+4;
4661 src1 : R(read);
4662 src2 : R(read);
4663 MS : R(6);
4664 %}
4665
4666 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4667 single_instruction;
4668 dst : E(write)+4;
4669 src1 : R(read);
4670 MS : R(6);
4671 %}
4672
4673 // Integer Divide reg-reg
4674 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4675 instruction_count(1); multiple_bundles;
4676 dst : E(write);
4677 temp : E(write);
4678 src1 : R(read);
4679 src2 : R(read);
4680 temp : R(read);
4681 MS : R(38);
4682 %}
4683
4684 // Integer Divide reg-imm
4685 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4686 instruction_count(1); multiple_bundles;
4687 dst : E(write);
4688 temp : E(write);
4689 src1 : R(read);
4690 temp : R(read);
4691 MS : R(38);
4692 %}
4693
4694 // Long Divide
4695 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4696 dst : E(write)+71;
4697 src1 : R(read);
4698 src2 : R(read)+1;
4699 MS : R(70);
4700 %}
4701
4702 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4703 dst : E(write)+71;
4704 src1 : R(read);
4705 MS : R(70);
4706 %}
4707
4708 // Floating Point Add Float
4709 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4710 single_instruction;
4711 dst : X(write);
4712 src1 : E(read);
4713 src2 : E(read);
4714 FA : R;
4715 %}
4716
4717 // Floating Point Add Double
4718 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4719 single_instruction;
4720 dst : X(write);
4721 src1 : E(read);
4722 src2 : E(read);
4723 FA : R;
4724 %}
4725
4726 // Floating Point Conditional Move based on integer flags
4727 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4728 single_instruction;
4729 dst : X(write);
4730 src : E(read);
4731 cr : R(read);
4732 FA : R(2);
4733 BR : R(2);
4734 %}
4735
4736 // Floating Point Conditional Move based on integer flags
4737 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4738 single_instruction;
4739 dst : X(write);
4740 src : E(read);
4741 cr : R(read);
4742 FA : R(2);
4743 BR : R(2);
4744 %}
4745
4746 // Floating Point Multiply Float
4747 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4748 single_instruction;
4749 dst : X(write);
4750 src1 : E(read);
4751 src2 : E(read);
4752 FM : R;
4753 %}
4754
4755 // Floating Point Multiply Double
4756 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4757 single_instruction;
4758 dst : X(write);
4759 src1 : E(read);
4760 src2 : E(read);
4761 FM : R;
4762 %}
4763
4764 // Floating Point Divide Float
4765 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4766 single_instruction;
4767 dst : X(write);
4768 src1 : E(read);
4769 src2 : E(read);
4770 FM : R;
4771 FDIV : C(14);
4772 %}
4773
4774 // Floating Point Divide Double
4775 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4776 single_instruction;
4777 dst : X(write);
4778 src1 : E(read);
4779 src2 : E(read);
4780 FM : R;
4781 FDIV : C(17);
4782 %}
4783
4784 // Floating Point Move/Negate/Abs Float
4785 pipe_class faddF_reg(regF dst, regF src) %{
4786 single_instruction;
4787 dst : W(write);
4788 src : E(read);
4789 FA : R(1);
4790 %}
4791
4792 // Floating Point Move/Negate/Abs Double
4793 pipe_class faddD_reg(regD dst, regD src) %{
4794 single_instruction;
4795 dst : W(write);
4796 src : E(read);
4797 FA : R;
4798 %}
4799
4800 // Floating Point Convert F->D
4801 pipe_class fcvtF2D(regD dst, regF src) %{
4802 single_instruction;
4803 dst : X(write);
4804 src : E(read);
4805 FA : R;
4806 %}
4807
4808 // Floating Point Convert I->D
4809 pipe_class fcvtI2D(regD dst, regF src) %{
4810 single_instruction;
4811 dst : X(write);
4812 src : E(read);
4813 FA : R;
4814 %}
4815
4816 // Floating Point Convert LHi->D
4817 pipe_class fcvtLHi2D(regD dst, regD src) %{
4818 single_instruction;
4819 dst : X(write);
4820 src : E(read);
4821 FA : R;
4822 %}
4823
4824 // Floating Point Convert L->D
4825 pipe_class fcvtL2D(regD dst, regF src) %{
4826 single_instruction;
4827 dst : X(write);
4828 src : E(read);
4829 FA : R;
4830 %}
4831
4832 // Floating Point Convert L->F
4833 pipe_class fcvtL2F(regD dst, regF src) %{
4834 single_instruction;
4835 dst : X(write);
4836 src : E(read);
4837 FA : R;
4838 %}
4839
4840 // Floating Point Convert D->F
4841 pipe_class fcvtD2F(regD dst, regF src) %{
4842 single_instruction;
4843 dst : X(write);
4844 src : E(read);
4845 FA : R;
4846 %}
4847
4848 // Floating Point Convert I->L
4849 pipe_class fcvtI2L(regD dst, regF src) %{
4850 single_instruction;
4851 dst : X(write);
4852 src : E(read);
4853 FA : R;
4854 %}
4855
4856 // Floating Point Convert D->F
4857 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4858 instruction_count(1); multiple_bundles;
4859 dst : X(write)+6;
4860 src : E(read);
4861 FA : R;
4862 %}
4863
4864 // Floating Point Convert D->L
4865 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4866 instruction_count(1); multiple_bundles;
4867 dst : X(write)+6;
4868 src : E(read);
4869 FA : R;
4870 %}
4871
4872 // Floating Point Convert F->I
4873 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4874 instruction_count(1); multiple_bundles;
4875 dst : X(write)+6;
4876 src : E(read);
4877 FA : R;
4878 %}
4879
4880 // Floating Point Convert F->L
4881 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4882 instruction_count(1); multiple_bundles;
4883 dst : X(write)+6;
4884 src : E(read);
4885 FA : R;
4886 %}
4887
4888 // Floating Point Convert I->F
4889 pipe_class fcvtI2F(regF dst, regF src) %{
4890 single_instruction;
4891 dst : X(write);
4892 src : E(read);
4893 FA : R;
4894 %}
4895
4896 // Floating Point Compare
4897 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4898 single_instruction;
4899 cr : X(write);
4900 src1 : E(read);
4901 src2 : E(read);
4902 FA : R;
4903 %}
4904
4905 // Floating Point Compare
4906 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4907 single_instruction;
4908 cr : X(write);
4909 src1 : E(read);
4910 src2 : E(read);
4911 FA : R;
4912 %}
4913
4914 // Floating Add Nop
4915 pipe_class fadd_nop() %{
4916 single_instruction;
4917 FA : R;
4918 %}
4919
4920 // Integer Store to Memory
4921 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4922 single_instruction;
4923 mem : R(read);
4924 src : C(read);
4925 MS : R;
4926 %}
4927
4928 // Integer Store to Memory
4929 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4930 single_instruction;
4931 mem : R(read);
4932 src : C(read);
4933 MS : R;
4934 %}
4935
4936 // Integer Store Zero to Memory
4937 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4938 single_instruction;
4939 mem : R(read);
4940 MS : R;
4941 %}
4942
4943 // Special Stack Slot Store
4944 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4945 single_instruction;
4946 stkSlot : R(read);
4947 src : C(read);
4948 MS : R;
4949 %}
4950
4951 // Special Stack Slot Store
4952 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4953 instruction_count(2); multiple_bundles;
4954 stkSlot : R(read);
4955 src : C(read);
4956 MS : R(2);
4957 %}
4958
4959 // Float Store
4960 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4961 single_instruction;
4962 mem : R(read);
4963 src : C(read);
4964 MS : R;
4965 %}
4966
4967 // Float Store
4968 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4969 single_instruction;
4970 mem : R(read);
4971 MS : R;
4972 %}
4973
4974 // Double Store
4975 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4976 instruction_count(1);
4977 mem : R(read);
4978 src : C(read);
4979 MS : R;
4980 %}
4981
4982 // Double Store
4983 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4984 single_instruction;
4985 mem : R(read);
4986 MS : R;
4987 %}
4988
4989 // Special Stack Slot Float Store
4990 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4991 single_instruction;
4992 stkSlot : R(read);
4993 src : C(read);
4994 MS : R;
4995 %}
4996
4997 // Special Stack Slot Double Store
4998 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4999 single_instruction;
5000 stkSlot : R(read);
5001 src : C(read);
5002 MS : R;
5003 %}
5004
5005 // Integer Load (when sign bit propagation not needed)
5006 pipe_class iload_mem(iRegI dst, memory mem) %{
5007 single_instruction;
5008 mem : R(read);
5009 dst : C(write);
5010 MS : R;
5011 %}
5012
5013 // Integer Load from stack operand
5014 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5015 single_instruction;
5016 mem : R(read);
5017 dst : C(write);
5018 MS : R;
5019 %}
5020
5021 // Integer Load (when sign bit propagation or masking is needed)
5022 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5023 single_instruction;
5024 mem : R(read);
5025 dst : M(write);
5026 MS : R;
5027 %}
5028
5029 // Float Load
5030 pipe_class floadF_mem(regF dst, memory mem) %{
5031 single_instruction;
5032 mem : R(read);
5033 dst : M(write);
5034 MS : R;
5035 %}
5036
5037 // Float Load
5038 pipe_class floadD_mem(regD dst, memory mem) %{
5039 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5040 mem : R(read);
5041 dst : M(write);
5042 MS : R;
5043 %}
5044
5045 // Float Load
5046 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5047 single_instruction;
5048 stkSlot : R(read);
5049 dst : M(write);
5050 MS : R;
5051 %}
5052
5053 // Float Load
5054 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5055 single_instruction;
5056 stkSlot : R(read);
5057 dst : M(write);
5058 MS : R;
5059 %}
5060
5061 // Memory Nop
5062 pipe_class mem_nop() %{
5063 single_instruction;
5064 MS : R;
5065 %}
5066
5067 pipe_class sethi(iRegP dst, immI src) %{
5068 single_instruction;
5069 dst : E(write);
5070 IALU : R;
5071 %}
5072
5073 pipe_class loadPollP(iRegP poll) %{
5074 single_instruction;
5075 poll : R(read);
5076 MS : R;
5077 %}
5078
5079 pipe_class br(Universe br, label labl) %{
5080 single_instruction_with_delay_slot;
5081 BR : R;
5082 %}
5083
5084 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5085 single_instruction_with_delay_slot;
5086 cr : E(read);
5087 BR : R;
5088 %}
5089
5090 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5091 single_instruction_with_delay_slot;
5092 op1 : E(read);
5093 BR : R;
5094 MS : R;
5095 %}
5096
5097 // Compare and branch
5098 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5099 instruction_count(2); has_delay_slot;
5100 cr : E(write);
5101 src1 : R(read);
5102 src2 : R(read);
5103 IALU : R;
5104 BR : R;
5105 %}
5106
5107 // Compare and branch
5108 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5109 instruction_count(2); has_delay_slot;
5110 cr : E(write);
5111 src1 : R(read);
5112 IALU : R;
5113 BR : R;
5114 %}
5115
5116 // Compare and branch using cbcond
5117 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5118 single_instruction;
5119 src1 : E(read);
5120 src2 : E(read);
5121 IALU : R;
5122 BR : R;
5123 %}
5124
5125 // Compare and branch using cbcond
5126 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5127 single_instruction;
5128 src1 : E(read);
5129 IALU : R;
5130 BR : R;
5131 %}
5132
5133 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5134 single_instruction_with_delay_slot;
5135 cr : E(read);
5136 BR : R;
5137 %}
5138
5139 pipe_class br_nop() %{
5140 single_instruction;
5141 BR : R;
5142 %}
5143
5144 pipe_class simple_call(method meth) %{
5145 instruction_count(2); multiple_bundles; force_serialization;
5146 fixed_latency(100);
5147 BR : R(1);
5148 MS : R(1);
5149 A0 : R(1);
5150 %}
5151
5152 pipe_class compiled_call(method meth) %{
5153 instruction_count(1); multiple_bundles; force_serialization;
5154 fixed_latency(100);
5155 MS : R(1);
5156 %}
5157
5158 pipe_class call(method meth) %{
5159 instruction_count(0); multiple_bundles; force_serialization;
5160 fixed_latency(100);
5161 %}
5162
5163 pipe_class tail_call(Universe ignore, label labl) %{
5164 single_instruction; has_delay_slot;
5165 fixed_latency(100);
5166 BR : R(1);
5167 MS : R(1);
5168 %}
5169
5170 pipe_class ret(Universe ignore) %{
5171 single_instruction; has_delay_slot;
5172 BR : R(1);
5173 MS : R(1);
5174 %}
5175
5176 pipe_class ret_poll(g3RegP poll) %{
5177 instruction_count(3); has_delay_slot;
5178 poll : E(read);
5179 MS : R;
5180 %}
5181
5182 // The real do-nothing guy
5183 pipe_class empty( ) %{
5184 instruction_count(0);
5185 %}
5186
5187 pipe_class long_memory_op() %{
5188 instruction_count(0); multiple_bundles; force_serialization;
5189 fixed_latency(25);
5190 MS : R(1);
5191 %}
5192
5193 // Check-cast
5194 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5195 array : R(read);
5196 match : R(read);
5197 IALU : R(2);
5198 BR : R(2);
5199 MS : R;
5200 %}
5201
5202 // Convert FPU flags into +1,0,-1
5203 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5204 src1 : E(read);
5205 src2 : E(read);
5206 dst : E(write);
5207 FA : R;
5208 MS : R(2);
5209 BR : R(2);
5210 %}
5211
5212 // Compare for p < q, and conditionally add y
5213 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5214 p : E(read);
5215 q : E(read);
5216 y : E(read);
5217 IALU : R(3)
5218 %}
5219
5220 // Perform a compare, then move conditionally in a branch delay slot.
5221 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5222 src2 : E(read);
5223 srcdst : E(read);
5224 IALU : R;
5225 BR : R;
5226 %}
5227
5228 // Define the class for the Nop node
5229 define %{
5230 MachNop = ialu_nop;
5231 %}
5232
5233 %}
5234
5235 //----------INSTRUCTIONS-------------------------------------------------------
5236
5237 //------------Special Stack Slot instructions - no match rules-----------------
5238 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5239 // No match rule to avoid chain rule match.
5240 effect(DEF dst, USE src);
5241 ins_cost(MEMORY_REF_COST);
5242 format %{ "LDF $src,$dst\t! stkI to regF" %}
5243 opcode(Assembler::ldf_op3);
5244 ins_encode(simple_form3_mem_reg(src, dst));
5245 ins_pipe(floadF_stk);
5246 %}
5247
5248 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5249 // No match rule to avoid chain rule match.
5250 effect(DEF dst, USE src);
5251 ins_cost(MEMORY_REF_COST);
5252 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5253 opcode(Assembler::lddf_op3);
5254 ins_encode(simple_form3_mem_reg(src, dst));
5255 ins_pipe(floadD_stk);
5256 %}
5257
5258 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5259 // No match rule to avoid chain rule match.
5260 effect(DEF dst, USE src);
5261 ins_cost(MEMORY_REF_COST);
5262 format %{ "STF $src,$dst\t! regF to stkI" %}
5263 opcode(Assembler::stf_op3);
5264 ins_encode(simple_form3_mem_reg(dst, src));
5265 ins_pipe(fstoreF_stk_reg);
5266 %}
5267
5268 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5269 // No match rule to avoid chain rule match.
5270 effect(DEF dst, USE src);
5271 ins_cost(MEMORY_REF_COST);
5272 format %{ "STDF $src,$dst\t! regD to stkL" %}
5273 opcode(Assembler::stdf_op3);
5274 ins_encode(simple_form3_mem_reg(dst, src));
5275 ins_pipe(fstoreD_stk_reg);
5276 %}
5277
5278 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5279 effect(DEF dst, USE src);
5280 ins_cost(MEMORY_REF_COST*2);
5281 format %{ "STW $src,$dst.hi\t! long\n\t"
5282 "STW R_G0,$dst.lo" %}
5283 opcode(Assembler::stw_op3);
5284 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5285 ins_pipe(lstoreI_stk_reg);
5286 %}
5287
5288 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5289 // No match rule to avoid chain rule match.
5290 effect(DEF dst, USE src);
5291 ins_cost(MEMORY_REF_COST);
5292 format %{ "STX $src,$dst\t! regL to stkD" %}
5293 opcode(Assembler::stx_op3);
5294 ins_encode(simple_form3_mem_reg( dst, src ) );
5295 ins_pipe(istore_stk_reg);
5296 %}
5297
5298 //---------- Chain stack slots between similar types --------
5299
5300 // Load integer from stack slot
5301 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5302 match(Set dst src);
5303 ins_cost(MEMORY_REF_COST);
5304
5305 format %{ "LDUW $src,$dst\t!stk" %}
5306 opcode(Assembler::lduw_op3);
5307 ins_encode(simple_form3_mem_reg( src, dst ) );
5308 ins_pipe(iload_mem);
5309 %}
5310
5311 // Store integer to stack slot
5312 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5313 match(Set dst src);
5314 ins_cost(MEMORY_REF_COST);
5315
5316 format %{ "STW $src,$dst\t!stk" %}
5317 opcode(Assembler::stw_op3);
5318 ins_encode(simple_form3_mem_reg( dst, src ) );
5319 ins_pipe(istore_mem_reg);
5320 %}
5321
5322 // Load long from stack slot
5323 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5324 match(Set dst src);
5325
5326 ins_cost(MEMORY_REF_COST);
5327 format %{ "LDX $src,$dst\t! long" %}
5328 opcode(Assembler::ldx_op3);
5329 ins_encode(simple_form3_mem_reg( src, dst ) );
5330 ins_pipe(iload_mem);
5331 %}
5332
5333 // Store long to stack slot
5334 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5335 match(Set dst src);
5336
5337 ins_cost(MEMORY_REF_COST);
5338 format %{ "STX $src,$dst\t! long" %}
5339 opcode(Assembler::stx_op3);
5340 ins_encode(simple_form3_mem_reg( dst, src ) );
5341 ins_pipe(istore_mem_reg);
5342 %}
5343
5344 #ifdef _LP64
5345 // Load pointer from stack slot, 64-bit encoding
5346 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5347 match(Set dst src);
5348 ins_cost(MEMORY_REF_COST);
5349 format %{ "LDX $src,$dst\t!ptr" %}
5350 opcode(Assembler::ldx_op3);
5351 ins_encode(simple_form3_mem_reg( src, dst ) );
5352 ins_pipe(iload_mem);
5353 %}
5354
5355 // Store pointer to stack slot
5356 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5357 match(Set dst src);
5358 ins_cost(MEMORY_REF_COST);
5359 format %{ "STX $src,$dst\t!ptr" %}
5360 opcode(Assembler::stx_op3);
5361 ins_encode(simple_form3_mem_reg( dst, src ) );
5362 ins_pipe(istore_mem_reg);
5363 %}
5364 #else // _LP64
5365 // Load pointer from stack slot, 32-bit encoding
5366 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5367 match(Set dst src);
5368 ins_cost(MEMORY_REF_COST);
5369 format %{ "LDUW $src,$dst\t!ptr" %}
5370 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5371 ins_encode(simple_form3_mem_reg( src, dst ) );
5372 ins_pipe(iload_mem);
5373 %}
5374
5375 // Store pointer to stack slot
5376 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5377 match(Set dst src);
5378 ins_cost(MEMORY_REF_COST);
5379 format %{ "STW $src,$dst\t!ptr" %}
5380 opcode(Assembler::stw_op3, Assembler::ldst_op);
5381 ins_encode(simple_form3_mem_reg( dst, src ) );
5382 ins_pipe(istore_mem_reg);
5383 %}
5384 #endif // _LP64
5385
5386 //------------Special Nop instructions for bundling - no match rules-----------
5387 // Nop using the A0 functional unit
5388 instruct Nop_A0() %{
5389 ins_cost(0);
5390
5391 format %{ "NOP ! Alu Pipeline" %}
5392 opcode(Assembler::or_op3, Assembler::arith_op);
5393 ins_encode( form2_nop() );
5394 ins_pipe(ialu_nop_A0);
5395 %}
5396
5397 // Nop using the A1 functional unit
5398 instruct Nop_A1( ) %{
5399 ins_cost(0);
5400
5401 format %{ "NOP ! Alu Pipeline" %}
5402 opcode(Assembler::or_op3, Assembler::arith_op);
5403 ins_encode( form2_nop() );
5404 ins_pipe(ialu_nop_A1);
5405 %}
5406
5407 // Nop using the memory functional unit
5408 instruct Nop_MS( ) %{
5409 ins_cost(0);
5410
5411 format %{ "NOP ! Memory Pipeline" %}
5412 ins_encode( emit_mem_nop );
5413 ins_pipe(mem_nop);
5414 %}
5415
5416 // Nop using the floating add functional unit
5417 instruct Nop_FA( ) %{
5418 ins_cost(0);
5419
5420 format %{ "NOP ! Floating Add Pipeline" %}
5421 ins_encode( emit_fadd_nop );
5422 ins_pipe(fadd_nop);
5423 %}
5424
5425 // Nop using the branch functional unit
5426 instruct Nop_BR( ) %{
5427 ins_cost(0);
5428
5429 format %{ "NOP ! Branch Pipeline" %}
5430 ins_encode( emit_br_nop );
5431 ins_pipe(br_nop);
5432 %}
5433
5434 //----------Load/Store/Move Instructions---------------------------------------
5435 //----------Load Instructions--------------------------------------------------
5436 // Load Byte (8bit signed)
5437 instruct loadB(iRegI dst, memory mem) %{
5438 match(Set dst (LoadB mem));
5439 ins_cost(MEMORY_REF_COST);
5440
5441 size(4);
5442 format %{ "LDSB $mem,$dst\t! byte" %}
5443 ins_encode %{
5444 __ ldsb($mem$$Address, $dst$$Register);
5445 %}
5446 ins_pipe(iload_mask_mem);
5447 %}
5448
5449 // Load Byte (8bit signed) into a Long Register
5450 instruct loadB2L(iRegL dst, memory mem) %{
5451 match(Set dst (ConvI2L (LoadB mem)));
5452 ins_cost(MEMORY_REF_COST);
5453
5454 size(4);
5455 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5456 ins_encode %{
5457 __ ldsb($mem$$Address, $dst$$Register);
5458 %}
5459 ins_pipe(iload_mask_mem);
5460 %}
5461
5462 // Load Unsigned Byte (8bit UNsigned) into an int reg
5463 instruct loadUB(iRegI dst, memory mem) %{
5464 match(Set dst (LoadUB mem));
5465 ins_cost(MEMORY_REF_COST);
5466
5467 size(4);
5468 format %{ "LDUB $mem,$dst\t! ubyte" %}
5469 ins_encode %{
5470 __ ldub($mem$$Address, $dst$$Register);
5471 %}
5472 ins_pipe(iload_mem);
5473 %}
5474
5475 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5476 instruct loadUB2L(iRegL dst, memory mem) %{
5477 match(Set dst (ConvI2L (LoadUB mem)));
5478 ins_cost(MEMORY_REF_COST);
5479
5480 size(4);
5481 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5482 ins_encode %{
5483 __ ldub($mem$$Address, $dst$$Register);
5484 %}
5485 ins_pipe(iload_mem);
5486 %}
5487
5488 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5489 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5490 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5491 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5492
5493 size(2*4);
5494 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5495 "AND $dst,right_n_bits($mask, 8),$dst" %}
5496 ins_encode %{
5497 __ ldub($mem$$Address, $dst$$Register);
5498 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5499 %}
5500 ins_pipe(iload_mem);
5501 %}
5502
5503 // Load Short (16bit signed)
5504 instruct loadS(iRegI dst, memory mem) %{
5505 match(Set dst (LoadS mem));
5506 ins_cost(MEMORY_REF_COST);
5507
5508 size(4);
5509 format %{ "LDSH $mem,$dst\t! short" %}
5510 ins_encode %{
5511 __ ldsh($mem$$Address, $dst$$Register);
5512 %}
5513 ins_pipe(iload_mask_mem);
5514 %}
5515
5516 // Load Short (16 bit signed) to Byte (8 bit signed)
5517 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5518 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5519 ins_cost(MEMORY_REF_COST);
5520
5521 size(4);
5522
5523 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5524 ins_encode %{
5525 __ ldsb($mem$$Address, $dst$$Register, 1);
5526 %}
5527 ins_pipe(iload_mask_mem);
5528 %}
5529
5530 // Load Short (16bit signed) into a Long Register
5531 instruct loadS2L(iRegL dst, memory mem) %{
5532 match(Set dst (ConvI2L (LoadS mem)));
5533 ins_cost(MEMORY_REF_COST);
5534
5535 size(4);
5536 format %{ "LDSH $mem,$dst\t! short -> long" %}
5537 ins_encode %{
5538 __ ldsh($mem$$Address, $dst$$Register);
5539 %}
5540 ins_pipe(iload_mask_mem);
5541 %}
5542
5543 // Load Unsigned Short/Char (16bit UNsigned)
5544 instruct loadUS(iRegI dst, memory mem) %{
5545 match(Set dst (LoadUS mem));
5546 ins_cost(MEMORY_REF_COST);
5547
5548 size(4);
5549 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5550 ins_encode %{
5551 __ lduh($mem$$Address, $dst$$Register);
5552 %}
5553 ins_pipe(iload_mem);
5554 %}
5555
5556 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5557 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5558 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5559 ins_cost(MEMORY_REF_COST);
5560
5561 size(4);
5562 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5563 ins_encode %{
5564 __ ldsb($mem$$Address, $dst$$Register, 1);
5565 %}
5566 ins_pipe(iload_mask_mem);
5567 %}
5568
5569 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5570 instruct loadUS2L(iRegL dst, memory mem) %{
5571 match(Set dst (ConvI2L (LoadUS mem)));
5572 ins_cost(MEMORY_REF_COST);
5573
5574 size(4);
5575 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5576 ins_encode %{
5577 __ lduh($mem$$Address, $dst$$Register);
5578 %}
5579 ins_pipe(iload_mem);
5580 %}
5581
5582 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5583 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5584 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5585 ins_cost(MEMORY_REF_COST);
5586
5587 size(4);
5588 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5589 ins_encode %{
5590 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5591 %}
5592 ins_pipe(iload_mem);
5593 %}
5594
5595 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5596 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5597 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5598 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5599
5600 size(2*4);
5601 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5602 "AND $dst,$mask,$dst" %}
5603 ins_encode %{
5604 Register Rdst = $dst$$Register;
5605 __ lduh($mem$$Address, Rdst);
5606 __ and3(Rdst, $mask$$constant, Rdst);
5607 %}
5608 ins_pipe(iload_mem);
5609 %}
5610
5611 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5612 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5613 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5614 effect(TEMP dst, TEMP tmp);
5615 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5616
5617 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5618 "SET right_n_bits($mask, 16),$tmp\n\t"
5619 "AND $dst,$tmp,$dst" %}
5620 ins_encode %{
5621 Register Rdst = $dst$$Register;
5622 Register Rtmp = $tmp$$Register;
5623 __ lduh($mem$$Address, Rdst);
5624 __ set($mask$$constant & right_n_bits(16), Rtmp);
5625 __ and3(Rdst, Rtmp, Rdst);
5626 %}
5627 ins_pipe(iload_mem);
5628 %}
5629
5630 // Load Integer
5631 instruct loadI(iRegI dst, memory mem) %{
5632 match(Set dst (LoadI mem));
5633 ins_cost(MEMORY_REF_COST);
5634
5635 size(4);
5636 format %{ "LDUW $mem,$dst\t! int" %}
5637 ins_encode %{
5638 __ lduw($mem$$Address, $dst$$Register);
5639 %}
5640 ins_pipe(iload_mem);
5641 %}
5642
5643 // Load Integer to Byte (8 bit signed)
5644 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5645 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5646 ins_cost(MEMORY_REF_COST);
5647
5648 size(4);
5649
5650 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5651 ins_encode %{
5652 __ ldsb($mem$$Address, $dst$$Register, 3);
5653 %}
5654 ins_pipe(iload_mask_mem);
5655 %}
5656
5657 // Load Integer to Unsigned Byte (8 bit UNsigned)
5658 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5659 match(Set dst (AndI (LoadI mem) mask));
5660 ins_cost(MEMORY_REF_COST);
5661
5662 size(4);
5663
5664 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5665 ins_encode %{
5666 __ ldub($mem$$Address, $dst$$Register, 3);
5667 %}
5668 ins_pipe(iload_mask_mem);
5669 %}
5670
5671 // Load Integer to Short (16 bit signed)
5672 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5673 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5674 ins_cost(MEMORY_REF_COST);
5675
5676 size(4);
5677
5678 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5679 ins_encode %{
5680 __ ldsh($mem$$Address, $dst$$Register, 2);
5681 %}
5682 ins_pipe(iload_mask_mem);
5683 %}
5684
5685 // Load Integer to Unsigned Short (16 bit UNsigned)
5686 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5687 match(Set dst (AndI (LoadI mem) mask));
5688 ins_cost(MEMORY_REF_COST);
5689
5690 size(4);
5691
5692 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5693 ins_encode %{
5694 __ lduh($mem$$Address, $dst$$Register, 2);
5695 %}
5696 ins_pipe(iload_mask_mem);
5697 %}
5698
5699 // Load Integer into a Long Register
5700 instruct loadI2L(iRegL dst, memory mem) %{
5701 match(Set dst (ConvI2L (LoadI mem)));
5702 ins_cost(MEMORY_REF_COST);
5703
5704 size(4);
5705 format %{ "LDSW $mem,$dst\t! int -> long" %}
5706 ins_encode %{
5707 __ ldsw($mem$$Address, $dst$$Register);
5708 %}
5709 ins_pipe(iload_mask_mem);
5710 %}
5711
5712 // Load Integer with mask 0xFF into a Long Register
5713 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5714 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5715 ins_cost(MEMORY_REF_COST);
5716
5717 size(4);
5718 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5719 ins_encode %{
5720 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5721 %}
5722 ins_pipe(iload_mem);
5723 %}
5724
5725 // Load Integer with mask 0xFFFF into a Long Register
5726 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5727 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5728 ins_cost(MEMORY_REF_COST);
5729
5730 size(4);
5731 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5732 ins_encode %{
5733 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5734 %}
5735 ins_pipe(iload_mem);
5736 %}
5737
5738 // Load Integer with a 12-bit mask into a Long Register
5739 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5740 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5741 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5742
5743 size(2*4);
5744 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5745 "AND $dst,$mask,$dst" %}
5746 ins_encode %{
5747 Register Rdst = $dst$$Register;
5748 __ lduw($mem$$Address, Rdst);
5749 __ and3(Rdst, $mask$$constant, Rdst);
5750 %}
5751 ins_pipe(iload_mem);
5752 %}
5753
5754 // Load Integer with a 31-bit mask into a Long Register
5755 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5756 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5757 effect(TEMP dst, TEMP tmp);
5758 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5759
5760 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5761 "SET $mask,$tmp\n\t"
5762 "AND $dst,$tmp,$dst" %}
5763 ins_encode %{
5764 Register Rdst = $dst$$Register;
5765 Register Rtmp = $tmp$$Register;
5766 __ lduw($mem$$Address, Rdst);
5767 __ set($mask$$constant, Rtmp);
5768 __ and3(Rdst, Rtmp, Rdst);
5769 %}
5770 ins_pipe(iload_mem);
5771 %}
5772
5773 // Load Unsigned Integer into a Long Register
5774 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5775 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5776 ins_cost(MEMORY_REF_COST);
5777
5778 size(4);
5779 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5780 ins_encode %{
5781 __ lduw($mem$$Address, $dst$$Register);
5782 %}
5783 ins_pipe(iload_mem);
5784 %}
5785
5786 // Load Long - aligned
5787 instruct loadL(iRegL dst, memory mem ) %{
5788 match(Set dst (LoadL mem));
5789 ins_cost(MEMORY_REF_COST);
5790
5791 size(4);
5792 format %{ "LDX $mem,$dst\t! long" %}
5793 ins_encode %{
5794 __ ldx($mem$$Address, $dst$$Register);
5795 %}
5796 ins_pipe(iload_mem);
5797 %}
5798
5799 // Load Long - UNaligned
5800 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5801 match(Set dst (LoadL_unaligned mem));
5802 effect(KILL tmp);
5803 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5804 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5805 "\tLDUW $mem ,$dst\n"
5806 "\tSLLX #32, $dst, $dst\n"
5807 "\tOR $dst, R_O7, $dst" %}
5808 opcode(Assembler::lduw_op3);
5809 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5810 ins_pipe(iload_mem);
5811 %}
5812
5813 // Load Range
5814 instruct loadRange(iRegI dst, memory mem) %{
5815 match(Set dst (LoadRange mem));
5816 ins_cost(MEMORY_REF_COST);
5817
5818 format %{ "LDUW $mem,$dst\t! range" %}
5819 opcode(Assembler::lduw_op3);
5820 ins_encode(simple_form3_mem_reg( mem, dst ) );
5821 ins_pipe(iload_mem);
5822 %}
5823
5824 // Load Integer into %f register (for fitos/fitod)
5825 instruct loadI_freg(regF dst, memory mem) %{
5826 match(Set dst (LoadI mem));
5827 ins_cost(MEMORY_REF_COST);
5828
5829 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5830 opcode(Assembler::ldf_op3);
5831 ins_encode(simple_form3_mem_reg( mem, dst ) );
5832 ins_pipe(floadF_mem);
5833 %}
5834
5835 // Load Pointer
5836 instruct loadP(iRegP dst, memory mem) %{
5837 match(Set dst (LoadP mem));
5838 ins_cost(MEMORY_REF_COST);
5839 size(4);
5840
5841 #ifndef _LP64
5842 format %{ "LDUW $mem,$dst\t! ptr" %}
5843 ins_encode %{
5844 __ lduw($mem$$Address, $dst$$Register);
5845 %}
5846 #else
5847 format %{ "LDX $mem,$dst\t! ptr" %}
5848 ins_encode %{
5849 __ ldx($mem$$Address, $dst$$Register);
5850 %}
5851 #endif
5852 ins_pipe(iload_mem);
5853 %}
5854
5855 // Load Compressed Pointer
5856 instruct loadN(iRegN dst, memory mem) %{
5857 match(Set dst (LoadN mem));
5858 ins_cost(MEMORY_REF_COST);
5859 size(4);
5860
5861 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5862 ins_encode %{
5863 __ lduw($mem$$Address, $dst$$Register);
5864 %}
5865 ins_pipe(iload_mem);
5866 %}
5867
5868 // Load Klass Pointer
5869 instruct loadKlass(iRegP dst, memory mem) %{
5870 match(Set dst (LoadKlass mem));
5871 ins_cost(MEMORY_REF_COST);
5872 size(4);
5873
5874 #ifndef _LP64
5875 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5876 ins_encode %{
5877 __ lduw($mem$$Address, $dst$$Register);
5878 %}
5879 #else
5880 format %{ "LDX $mem,$dst\t! klass ptr" %}
5881 ins_encode %{
5882 __ ldx($mem$$Address, $dst$$Register);
5883 %}
5884 #endif
5885 ins_pipe(iload_mem);
5886 %}
5887
5888 // Load narrow Klass Pointer
5889 instruct loadNKlass(iRegN dst, memory mem) %{
5890 match(Set dst (LoadNKlass mem));
5891 ins_cost(MEMORY_REF_COST);
5892 size(4);
5893
5894 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5895 ins_encode %{
5896 __ lduw($mem$$Address, $dst$$Register);
5897 %}
5898 ins_pipe(iload_mem);
5899 %}
5900
5901 // Load Double
5902 instruct loadD(regD dst, memory mem) %{
5903 match(Set dst (LoadD mem));
5904 ins_cost(MEMORY_REF_COST);
5905
5906 format %{ "LDDF $mem,$dst" %}
5907 opcode(Assembler::lddf_op3);
5908 ins_encode(simple_form3_mem_reg( mem, dst ) );
5909 ins_pipe(floadD_mem);
5910 %}
5911
5912 // Load Double - UNaligned
5913 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5914 match(Set dst (LoadD_unaligned mem));
5915 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5916 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5917 "\tLDF $mem+4,$dst.lo\t!" %}
5918 opcode(Assembler::ldf_op3);
5919 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5920 ins_pipe(iload_mem);
5921 %}
5922
5923 // Load Float
5924 instruct loadF(regF dst, memory mem) %{
5925 match(Set dst (LoadF mem));
5926 ins_cost(MEMORY_REF_COST);
5927
5928 format %{ "LDF $mem,$dst" %}
5929 opcode(Assembler::ldf_op3);
5930 ins_encode(simple_form3_mem_reg( mem, dst ) );
5931 ins_pipe(floadF_mem);
5932 %}
5933
5934 // Load Constant
5935 instruct loadConI( iRegI dst, immI src ) %{
5936 match(Set dst src);
5937 ins_cost(DEFAULT_COST * 3/2);
5938 format %{ "SET $src,$dst" %}
5939 ins_encode( Set32(src, dst) );
5940 ins_pipe(ialu_hi_lo_reg);
5941 %}
5942
5943 instruct loadConI13( iRegI dst, immI13 src ) %{
5944 match(Set dst src);
5945
5946 size(4);
5947 format %{ "MOV $src,$dst" %}
5948 ins_encode( Set13( src, dst ) );
5949 ins_pipe(ialu_imm);
5950 %}
5951
5952 #ifndef _LP64
5953 instruct loadConP(iRegP dst, immP con) %{
5954 match(Set dst con);
5955 ins_cost(DEFAULT_COST * 3/2);
5956 format %{ "SET $con,$dst\t!ptr" %}
5957 ins_encode %{
5958 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5959 intptr_t val = $con$$constant;
5960 if (constant_reloc == relocInfo::oop_type) {
5961 __ set_oop_constant((jobject) val, $dst$$Register);
5962 } else if (constant_reloc == relocInfo::metadata_type) {
5963 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5964 } else { // non-oop pointers, e.g. card mark base, heap top
5965 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5966 __ set(val, $dst$$Register);
5967 }
5968 %}
5969 ins_pipe(loadConP);
5970 %}
5971 #else
5972 instruct loadConP_set(iRegP dst, immP_set con) %{
5973 match(Set dst con);
5974 ins_cost(DEFAULT_COST * 3/2);
5975 format %{ "SET $con,$dst\t! ptr" %}
5976 ins_encode %{
5977 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5978 intptr_t val = $con$$constant;
5979 if (constant_reloc == relocInfo::oop_type) {
5980 __ set_oop_constant((jobject) val, $dst$$Register);
5981 } else if (constant_reloc == relocInfo::metadata_type) {
5982 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5983 } else { // non-oop pointers, e.g. card mark base, heap top
5984 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5985 __ set(val, $dst$$Register);
5986 }
5987 %}
5988 ins_pipe(loadConP);
5989 %}
5990
5991 instruct loadConP_load(iRegP dst, immP_load con) %{
5992 match(Set dst con);
5993 ins_cost(MEMORY_REF_COST);
5994 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5995 ins_encode %{
5996 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5997 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5998 %}
5999 ins_pipe(loadConP);
6000 %}
6001
6002 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6003 match(Set dst con);
6004 ins_cost(DEFAULT_COST * 3/2);
6005 format %{ "SET $con,$dst\t! non-oop ptr" %}
6006 ins_encode %{
6007 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
6008 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
6009 } else {
6010 __ set($con$$constant, $dst$$Register);
6011 }
6012 %}
6013 ins_pipe(loadConP);
6014 %}
6015 #endif // _LP64
6016
6017 instruct loadConP0(iRegP dst, immP0 src) %{
6018 match(Set dst src);
6019
6020 size(4);
6021 format %{ "CLR $dst\t!ptr" %}
6022 ins_encode %{
6023 __ clr($dst$$Register);
6024 %}
6025 ins_pipe(ialu_imm);
6026 %}
6027
6028 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6029 match(Set dst src);
6030 ins_cost(DEFAULT_COST);
6031 format %{ "SET $src,$dst\t!ptr" %}
6032 ins_encode %{
6033 AddressLiteral polling_page(os::get_polling_page());
6034 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6035 %}
6036 ins_pipe(loadConP_poll);
6037 %}
6038
6039 instruct loadConN0(iRegN dst, immN0 src) %{
6040 match(Set dst src);
6041
6042 size(4);
6043 format %{ "CLR $dst\t! compressed NULL ptr" %}
6044 ins_encode %{
6045 __ clr($dst$$Register);
6046 %}
6047 ins_pipe(ialu_imm);
6048 %}
6049
6050 instruct loadConN(iRegN dst, immN src) %{
6051 match(Set dst src);
6052 ins_cost(DEFAULT_COST * 3/2);
6053 format %{ "SET $src,$dst\t! compressed ptr" %}
6054 ins_encode %{
6055 Register dst = $dst$$Register;
6056 __ set_narrow_oop((jobject)$src$$constant, dst);
6057 %}
6058 ins_pipe(ialu_hi_lo_reg);
6059 %}
6060
6061 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6062 match(Set dst src);
6063 ins_cost(DEFAULT_COST * 3/2);
6064 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6065 ins_encode %{
6066 Register dst = $dst$$Register;
6067 __ set_narrow_klass((Klass*)$src$$constant, dst);
6068 %}
6069 ins_pipe(ialu_hi_lo_reg);
6070 %}
6071
6072 // Materialize long value (predicated by immL_cheap).
6073 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6074 match(Set dst con);
6075 effect(KILL tmp);
6076 ins_cost(DEFAULT_COST * 3);
6077 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6078 ins_encode %{
6079 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6080 %}
6081 ins_pipe(loadConL);
6082 %}
6083
6084 // Load long value from constant table (predicated by immL_expensive).
6085 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6086 match(Set dst con);
6087 ins_cost(MEMORY_REF_COST);
6088 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6089 ins_encode %{
6090 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6091 __ ldx($constanttablebase, con_offset, $dst$$Register);
6092 %}
6093 ins_pipe(loadConL);
6094 %}
6095
6096 instruct loadConL0( iRegL dst, immL0 src ) %{
6097 match(Set dst src);
6098 ins_cost(DEFAULT_COST);
6099 size(4);
6100 format %{ "CLR $dst\t! long" %}
6101 ins_encode( Set13( src, dst ) );
6102 ins_pipe(ialu_imm);
6103 %}
6104
6105 instruct loadConL13( iRegL dst, immL13 src ) %{
6106 match(Set dst src);
6107 ins_cost(DEFAULT_COST * 2);
6108
6109 size(4);
6110 format %{ "MOV $src,$dst\t! long" %}
6111 ins_encode( Set13( src, dst ) );
6112 ins_pipe(ialu_imm);
6113 %}
6114
6115 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6116 match(Set dst con);
6117 effect(KILL tmp);
6118 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6119 ins_encode %{
6120 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6121 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6122 %}
6123 ins_pipe(loadConFD);
6124 %}
6125
6126 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6127 match(Set dst con);
6128 effect(KILL tmp);
6129 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6130 ins_encode %{
6131 // XXX This is a quick fix for 6833573.
6132 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6133 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6134 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6135 %}
6136 ins_pipe(loadConFD);
6137 %}
6138
6139 // Prefetch instructions for allocation.
6140 // Must be safe to execute with invalid address (cannot fault).
6141
6142 instruct prefetchAlloc( memory mem ) %{
6143 predicate(AllocatePrefetchInstr == 0);
6144 match( PrefetchAllocation mem );
6145 ins_cost(MEMORY_REF_COST);
6146
6147 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6148 opcode(Assembler::prefetch_op3);
6149 ins_encode( form3_mem_prefetch_write( mem ) );
6150 ins_pipe(iload_mem);
6151 %}
6152
6153 // Use BIS instruction to prefetch for allocation.
6154 // Could fault, need space at the end of TLAB.
6155 instruct prefetchAlloc_bis( iRegP dst ) %{
6156 predicate(AllocatePrefetchInstr == 1);
6157 match( PrefetchAllocation dst );
6158 ins_cost(MEMORY_REF_COST);
6159 size(4);
6160
6161 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6162 ins_encode %{
6163 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6164 %}
6165 ins_pipe(istore_mem_reg);
6166 %}
6167
6168 // Next code is used for finding next cache line address to prefetch.
6169 #ifndef _LP64
6170 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6171 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6172 ins_cost(DEFAULT_COST);
6173 size(4);
6174
6175 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6176 ins_encode %{
6177 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6178 %}
6179 ins_pipe(ialu_reg_imm);
6180 %}
6181 #else
6182 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6183 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6184 ins_cost(DEFAULT_COST);
6185 size(4);
6186
6187 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6188 ins_encode %{
6189 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6190 %}
6191 ins_pipe(ialu_reg_imm);
6192 %}
6193 #endif
6194
6195 //----------Store Instructions-------------------------------------------------
6196 // Store Byte
6197 instruct storeB(memory mem, iRegI src) %{
6198 match(Set mem (StoreB mem src));
6199 ins_cost(MEMORY_REF_COST);
6200
6201 format %{ "STB $src,$mem\t! byte" %}
6202 opcode(Assembler::stb_op3);
6203 ins_encode(simple_form3_mem_reg( mem, src ) );
6204 ins_pipe(istore_mem_reg);
6205 %}
6206
6207 instruct storeB0(memory mem, immI0 src) %{
6208 match(Set mem (StoreB mem src));
6209 ins_cost(MEMORY_REF_COST);
6210
6211 format %{ "STB $src,$mem\t! byte" %}
6212 opcode(Assembler::stb_op3);
6213 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6214 ins_pipe(istore_mem_zero);
6215 %}
6216
6217 instruct storeCM0(memory mem, immI0 src) %{
6218 match(Set mem (StoreCM mem src));
6219 ins_cost(MEMORY_REF_COST);
6220
6221 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6222 opcode(Assembler::stb_op3);
6223 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6224 ins_pipe(istore_mem_zero);
6225 %}
6226
6227 // Store Char/Short
6228 instruct storeC(memory mem, iRegI src) %{
6229 match(Set mem (StoreC mem src));
6230 ins_cost(MEMORY_REF_COST);
6231
6232 format %{ "STH $src,$mem\t! short" %}
6233 opcode(Assembler::sth_op3);
6234 ins_encode(simple_form3_mem_reg( mem, src ) );
6235 ins_pipe(istore_mem_reg);
6236 %}
6237
6238 instruct storeC0(memory mem, immI0 src) %{
6239 match(Set mem (StoreC mem src));
6240 ins_cost(MEMORY_REF_COST);
6241
6242 format %{ "STH $src,$mem\t! short" %}
6243 opcode(Assembler::sth_op3);
6244 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6245 ins_pipe(istore_mem_zero);
6246 %}
6247
6248 // Store Integer
6249 instruct storeI(memory mem, iRegI src) %{
6250 match(Set mem (StoreI mem src));
6251 ins_cost(MEMORY_REF_COST);
6252
6253 format %{ "STW $src,$mem" %}
6254 opcode(Assembler::stw_op3);
6255 ins_encode(simple_form3_mem_reg( mem, src ) );
6256 ins_pipe(istore_mem_reg);
6257 %}
6258
6259 // Store Long
6260 instruct storeL(memory mem, iRegL src) %{
6261 match(Set mem (StoreL mem src));
6262 ins_cost(MEMORY_REF_COST);
6263 format %{ "STX $src,$mem\t! long" %}
6264 opcode(Assembler::stx_op3);
6265 ins_encode(simple_form3_mem_reg( mem, src ) );
6266 ins_pipe(istore_mem_reg);
6267 %}
6268
6269 instruct storeI0(memory mem, immI0 src) %{
6270 match(Set mem (StoreI mem src));
6271 ins_cost(MEMORY_REF_COST);
6272
6273 format %{ "STW $src,$mem" %}
6274 opcode(Assembler::stw_op3);
6275 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6276 ins_pipe(istore_mem_zero);
6277 %}
6278
6279 instruct storeL0(memory mem, immL0 src) %{
6280 match(Set mem (StoreL mem src));
6281 ins_cost(MEMORY_REF_COST);
6282
6283 format %{ "STX $src,$mem" %}
6284 opcode(Assembler::stx_op3);
6285 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6286 ins_pipe(istore_mem_zero);
6287 %}
6288
6289 // Store Integer from float register (used after fstoi)
6290 instruct storeI_Freg(memory mem, regF src) %{
6291 match(Set mem (StoreI mem src));
6292 ins_cost(MEMORY_REF_COST);
6293
6294 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6295 opcode(Assembler::stf_op3);
6296 ins_encode(simple_form3_mem_reg( mem, src ) );
6297 ins_pipe(fstoreF_mem_reg);
6298 %}
6299
6300 // Store Pointer
6301 instruct storeP(memory dst, sp_ptr_RegP src) %{
6302 match(Set dst (StoreP dst src));
6303 ins_cost(MEMORY_REF_COST);
6304
6305 #ifndef _LP64
6306 format %{ "STW $src,$dst\t! ptr" %}
6307 opcode(Assembler::stw_op3, 0, REGP_OP);
6308 #else
6309 format %{ "STX $src,$dst\t! ptr" %}
6310 opcode(Assembler::stx_op3, 0, REGP_OP);
6311 #endif
6312 ins_encode( form3_mem_reg( dst, src ) );
6313 ins_pipe(istore_mem_spORreg);
6314 %}
6315
6316 instruct storeP0(memory dst, immP0 src) %{
6317 match(Set dst (StoreP dst src));
6318 ins_cost(MEMORY_REF_COST);
6319
6320 #ifndef _LP64
6321 format %{ "STW $src,$dst\t! ptr" %}
6322 opcode(Assembler::stw_op3, 0, REGP_OP);
6323 #else
6324 format %{ "STX $src,$dst\t! ptr" %}
6325 opcode(Assembler::stx_op3, 0, REGP_OP);
6326 #endif
6327 ins_encode( form3_mem_reg( dst, R_G0 ) );
6328 ins_pipe(istore_mem_zero);
6329 %}
6330
6331 // Store Compressed Pointer
6332 instruct storeN(memory dst, iRegN src) %{
6333 match(Set dst (StoreN dst src));
6334 ins_cost(MEMORY_REF_COST);
6335 size(4);
6336
6337 format %{ "STW $src,$dst\t! compressed ptr" %}
6338 ins_encode %{
6339 Register base = as_Register($dst$$base);
6340 Register index = as_Register($dst$$index);
6341 Register src = $src$$Register;
6342 if (index != G0) {
6343 __ stw(src, base, index);
6344 } else {
6345 __ stw(src, base, $dst$$disp);
6346 }
6347 %}
6348 ins_pipe(istore_mem_spORreg);
6349 %}
6350
6351 instruct storeNKlass(memory dst, iRegN src) %{
6352 match(Set dst (StoreNKlass dst src));
6353 ins_cost(MEMORY_REF_COST);
6354 size(4);
6355
6356 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6357 ins_encode %{
6358 Register base = as_Register($dst$$base);
6359 Register index = as_Register($dst$$index);
6360 Register src = $src$$Register;
6361 if (index != G0) {
6362 __ stw(src, base, index);
6363 } else {
6364 __ stw(src, base, $dst$$disp);
6365 }
6366 %}
6367 ins_pipe(istore_mem_spORreg);
6368 %}
6369
6370 instruct storeN0(memory dst, immN0 src) %{
6371 match(Set dst (StoreN dst src));
6372 ins_cost(MEMORY_REF_COST);
6373 size(4);
6374
6375 format %{ "STW $src,$dst\t! compressed ptr" %}
6376 ins_encode %{
6377 Register base = as_Register($dst$$base);
6378 Register index = as_Register($dst$$index);
6379 if (index != G0) {
6380 __ stw(0, base, index);
6381 } else {
6382 __ stw(0, base, $dst$$disp);
6383 }
6384 %}
6385 ins_pipe(istore_mem_zero);
6386 %}
6387
6388 // Store Double
6389 instruct storeD( memory mem, regD src) %{
6390 match(Set mem (StoreD mem src));
6391 ins_cost(MEMORY_REF_COST);
6392
6393 format %{ "STDF $src,$mem" %}
6394 opcode(Assembler::stdf_op3);
6395 ins_encode(simple_form3_mem_reg( mem, src ) );
6396 ins_pipe(fstoreD_mem_reg);
6397 %}
6398
6399 instruct storeD0( memory mem, immD0 src) %{
6400 match(Set mem (StoreD mem src));
6401 ins_cost(MEMORY_REF_COST);
6402
6403 format %{ "STX $src,$mem" %}
6404 opcode(Assembler::stx_op3);
6405 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6406 ins_pipe(fstoreD_mem_zero);
6407 %}
6408
6409 // Store Float
6410 instruct storeF( memory mem, regF src) %{
6411 match(Set mem (StoreF mem src));
6412 ins_cost(MEMORY_REF_COST);
6413
6414 format %{ "STF $src,$mem" %}
6415 opcode(Assembler::stf_op3);
6416 ins_encode(simple_form3_mem_reg( mem, src ) );
6417 ins_pipe(fstoreF_mem_reg);
6418 %}
6419
6420 instruct storeF0( memory mem, immF0 src) %{
6421 match(Set mem (StoreF mem src));
6422 ins_cost(MEMORY_REF_COST);
6423
6424 format %{ "STW $src,$mem\t! storeF0" %}
6425 opcode(Assembler::stw_op3);
6426 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6427 ins_pipe(fstoreF_mem_zero);
6428 %}
6429
6430 // Convert oop pointer into compressed form
6431 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6432 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6433 match(Set dst (EncodeP src));
6434 format %{ "encode_heap_oop $src, $dst" %}
6435 ins_encode %{
6436 __ encode_heap_oop($src$$Register, $dst$$Register);
6437 %}
6438 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6439 ins_pipe(ialu_reg);
6440 %}
6441
6442 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6443 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6444 match(Set dst (EncodeP src));
6445 format %{ "encode_heap_oop_not_null $src, $dst" %}
6446 ins_encode %{
6447 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6448 %}
6449 ins_pipe(ialu_reg);
6450 %}
6451
6452 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6453 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6454 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6455 match(Set dst (DecodeN src));
6456 format %{ "decode_heap_oop $src, $dst" %}
6457 ins_encode %{
6458 __ decode_heap_oop($src$$Register, $dst$$Register);
6459 %}
6460 ins_pipe(ialu_reg);
6461 %}
6462
6463 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6464 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6465 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6466 match(Set dst (DecodeN src));
6467 format %{ "decode_heap_oop_not_null $src, $dst" %}
6468 ins_encode %{
6469 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6470 %}
6471 ins_pipe(ialu_reg);
6472 %}
6473
6474 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6475 match(Set dst (EncodePKlass src));
6476 format %{ "encode_klass_not_null $src, $dst" %}
6477 ins_encode %{
6478 __ encode_klass_not_null($src$$Register, $dst$$Register);
6479 %}
6480 ins_pipe(ialu_reg);
6481 %}
6482
6483 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6484 match(Set dst (DecodeNKlass src));
6485 format %{ "decode_klass_not_null $src, $dst" %}
6486 ins_encode %{
6487 __ decode_klass_not_null($src$$Register, $dst$$Register);
6488 %}
6489 ins_pipe(ialu_reg);
6490 %}
6491
6492 //----------MemBar Instructions-----------------------------------------------
6493 // Memory barrier flavors
6494
6495 instruct membar_acquire() %{
6496 match(MemBarAcquire);
6497 match(LoadFence);
6498 ins_cost(4*MEMORY_REF_COST);
6499
6500 size(0);
6501 format %{ "MEMBAR-acquire" %}
6502 ins_encode( enc_membar_acquire );
6503 ins_pipe(long_memory_op);
6504 %}
6505
6506 instruct membar_acquire_lock() %{
6507 match(MemBarAcquireLock);
6508 ins_cost(0);
6509
6510 size(0);
6511 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6512 ins_encode( );
6513 ins_pipe(empty);
6514 %}
6515
6516 instruct membar_release() %{
6517 match(MemBarRelease);
6518 match(StoreFence);
6519 ins_cost(4*MEMORY_REF_COST);
6520
6521 size(0);
6522 format %{ "MEMBAR-release" %}
6523 ins_encode( enc_membar_release );
6524 ins_pipe(long_memory_op);
6525 %}
6526
6527 instruct membar_release_lock() %{
6528 match(MemBarReleaseLock);
6529 ins_cost(0);
6530
6531 size(0);
6532 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6533 ins_encode( );
6534 ins_pipe(empty);
6535 %}
6536
6537 instruct membar_volatile() %{
6538 match(MemBarVolatile);
6539 ins_cost(4*MEMORY_REF_COST);
6540
6541 size(4);
6542 format %{ "MEMBAR-volatile" %}
6543 ins_encode( enc_membar_volatile );
6544 ins_pipe(long_memory_op);
6545 %}
6546
6547 instruct unnecessary_membar_volatile() %{
6548 match(MemBarVolatile);
6549 predicate(Matcher::post_store_load_barrier(n));
6550 ins_cost(0);
6551
6552 size(0);
6553 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6554 ins_encode( );
6555 ins_pipe(empty);
6556 %}
6557
6558 instruct membar_storestore() %{
6559 match(MemBarStoreStore);
6560 ins_cost(0);
6561
6562 size(0);
6563 format %{ "!MEMBAR-storestore (empty encoding)" %}
6564 ins_encode( );
6565 ins_pipe(empty);
6566 %}
6567
6568 //----------Register Move Instructions-----------------------------------------
6569 instruct roundDouble_nop(regD dst) %{
6570 match(Set dst (RoundDouble dst));
6571 ins_cost(0);
6572 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6573 ins_encode( );
6574 ins_pipe(empty);
6575 %}
6576
6577
6578 instruct roundFloat_nop(regF dst) %{
6579 match(Set dst (RoundFloat dst));
6580 ins_cost(0);
6581 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6582 ins_encode( );
6583 ins_pipe(empty);
6584 %}
6585
6586
6587 // Cast Index to Pointer for unsafe natives
6588 instruct castX2P(iRegX src, iRegP dst) %{
6589 match(Set dst (CastX2P src));
6590
6591 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6592 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6593 ins_pipe(ialu_reg);
6594 %}
6595
6596 // Cast Pointer to Index for unsafe natives
6597 instruct castP2X(iRegP src, iRegX dst) %{
6598 match(Set dst (CastP2X src));
6599
6600 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6601 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6602 ins_pipe(ialu_reg);
6603 %}
6604
6605 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6606 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6607 match(Set stkSlot src); // chain rule
6608 ins_cost(MEMORY_REF_COST);
6609 format %{ "STDF $src,$stkSlot\t!stk" %}
6610 opcode(Assembler::stdf_op3);
6611 ins_encode(simple_form3_mem_reg(stkSlot, src));
6612 ins_pipe(fstoreD_stk_reg);
6613 %}
6614
6615 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6616 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6617 match(Set dst stkSlot); // chain rule
6618 ins_cost(MEMORY_REF_COST);
6619 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6620 opcode(Assembler::lddf_op3);
6621 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6622 ins_pipe(floadD_stk);
6623 %}
6624
6625 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6626 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6627 match(Set stkSlot src); // chain rule
6628 ins_cost(MEMORY_REF_COST);
6629 format %{ "STF $src,$stkSlot\t!stk" %}
6630 opcode(Assembler::stf_op3);
6631 ins_encode(simple_form3_mem_reg(stkSlot, src));
6632 ins_pipe(fstoreF_stk_reg);
6633 %}
6634
6635 //----------Conditional Move---------------------------------------------------
6636 // Conditional move
6637 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6638 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6639 ins_cost(150);
6640 format %{ "MOV$cmp $pcc,$src,$dst" %}
6641 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6642 ins_pipe(ialu_reg);
6643 %}
6644
6645 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6646 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6647 ins_cost(140);
6648 format %{ "MOV$cmp $pcc,$src,$dst" %}
6649 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6650 ins_pipe(ialu_imm);
6651 %}
6652
6653 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6654 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6655 ins_cost(150);
6656 size(4);
6657 format %{ "MOV$cmp $icc,$src,$dst" %}
6658 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6659 ins_pipe(ialu_reg);
6660 %}
6661
6662 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6663 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6664 ins_cost(140);
6665 size(4);
6666 format %{ "MOV$cmp $icc,$src,$dst" %}
6667 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6668 ins_pipe(ialu_imm);
6669 %}
6670
6671 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6672 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6673 ins_cost(150);
6674 size(4);
6675 format %{ "MOV$cmp $icc,$src,$dst" %}
6676 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6677 ins_pipe(ialu_reg);
6678 %}
6679
6680 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6681 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6682 ins_cost(140);
6683 size(4);
6684 format %{ "MOV$cmp $icc,$src,$dst" %}
6685 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6686 ins_pipe(ialu_imm);
6687 %}
6688
6689 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6690 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6691 ins_cost(150);
6692 size(4);
6693 format %{ "MOV$cmp $fcc,$src,$dst" %}
6694 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6695 ins_pipe(ialu_reg);
6696 %}
6697
6698 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6699 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6700 ins_cost(140);
6701 size(4);
6702 format %{ "MOV$cmp $fcc,$src,$dst" %}
6703 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6704 ins_pipe(ialu_imm);
6705 %}
6706
6707 // Conditional move for RegN. Only cmov(reg,reg).
6708 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6709 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6710 ins_cost(150);
6711 format %{ "MOV$cmp $pcc,$src,$dst" %}
6712 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6713 ins_pipe(ialu_reg);
6714 %}
6715
6716 // This instruction also works with CmpN so we don't need cmovNN_reg.
6717 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6718 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6719 ins_cost(150);
6720 size(4);
6721 format %{ "MOV$cmp $icc,$src,$dst" %}
6722 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6723 ins_pipe(ialu_reg);
6724 %}
6725
6726 // This instruction also works with CmpN so we don't need cmovNN_reg.
6727 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6728 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6729 ins_cost(150);
6730 size(4);
6731 format %{ "MOV$cmp $icc,$src,$dst" %}
6732 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6733 ins_pipe(ialu_reg);
6734 %}
6735
6736 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6737 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6738 ins_cost(150);
6739 size(4);
6740 format %{ "MOV$cmp $fcc,$src,$dst" %}
6741 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6742 ins_pipe(ialu_reg);
6743 %}
6744
6745 // Conditional move
6746 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6747 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6748 ins_cost(150);
6749 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6750 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6751 ins_pipe(ialu_reg);
6752 %}
6753
6754 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6755 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6756 ins_cost(140);
6757 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6758 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6759 ins_pipe(ialu_imm);
6760 %}
6761
6762 // This instruction also works with CmpN so we don't need cmovPN_reg.
6763 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6764 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6765 ins_cost(150);
6766
6767 size(4);
6768 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6769 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6770 ins_pipe(ialu_reg);
6771 %}
6772
6773 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6774 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6775 ins_cost(150);
6776
6777 size(4);
6778 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6779 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6780 ins_pipe(ialu_reg);
6781 %}
6782
6783 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6784 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6785 ins_cost(140);
6786
6787 size(4);
6788 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6789 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6790 ins_pipe(ialu_imm);
6791 %}
6792
6793 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6794 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6795 ins_cost(140);
6796
6797 size(4);
6798 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6799 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6800 ins_pipe(ialu_imm);
6801 %}
6802
6803 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6804 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6805 ins_cost(150);
6806 size(4);
6807 format %{ "MOV$cmp $fcc,$src,$dst" %}
6808 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6809 ins_pipe(ialu_imm);
6810 %}
6811
6812 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6813 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6814 ins_cost(140);
6815 size(4);
6816 format %{ "MOV$cmp $fcc,$src,$dst" %}
6817 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6818 ins_pipe(ialu_imm);
6819 %}
6820
6821 // Conditional move
6822 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6823 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6824 ins_cost(150);
6825 opcode(0x101);
6826 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6827 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6828 ins_pipe(int_conditional_float_move);
6829 %}
6830
6831 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6832 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6833 ins_cost(150);
6834
6835 size(4);
6836 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6837 opcode(0x101);
6838 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6839 ins_pipe(int_conditional_float_move);
6840 %}
6841
6842 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6843 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6844 ins_cost(150);
6845
6846 size(4);
6847 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6848 opcode(0x101);
6849 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6850 ins_pipe(int_conditional_float_move);
6851 %}
6852
6853 // Conditional move,
6854 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6855 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6856 ins_cost(150);
6857 size(4);
6858 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6859 opcode(0x1);
6860 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6861 ins_pipe(int_conditional_double_move);
6862 %}
6863
6864 // Conditional move
6865 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6866 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6867 ins_cost(150);
6868 size(4);
6869 opcode(0x102);
6870 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6871 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6872 ins_pipe(int_conditional_double_move);
6873 %}
6874
6875 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6876 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6877 ins_cost(150);
6878
6879 size(4);
6880 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6881 opcode(0x102);
6882 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6883 ins_pipe(int_conditional_double_move);
6884 %}
6885
6886 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6887 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6888 ins_cost(150);
6889
6890 size(4);
6891 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6892 opcode(0x102);
6893 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6894 ins_pipe(int_conditional_double_move);
6895 %}
6896
6897 // Conditional move,
6898 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6899 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6900 ins_cost(150);
6901 size(4);
6902 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6903 opcode(0x2);
6904 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6905 ins_pipe(int_conditional_double_move);
6906 %}
6907
6908 // Conditional move
6909 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6910 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6911 ins_cost(150);
6912 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6913 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6914 ins_pipe(ialu_reg);
6915 %}
6916
6917 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6918 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6919 ins_cost(140);
6920 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6921 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6922 ins_pipe(ialu_imm);
6923 %}
6924
6925 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6926 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6927 ins_cost(150);
6928
6929 size(4);
6930 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6931 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6932 ins_pipe(ialu_reg);
6933 %}
6934
6935
6936 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6937 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6938 ins_cost(150);
6939
6940 size(4);
6941 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6942 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6943 ins_pipe(ialu_reg);
6944 %}
6945
6946
6947 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6948 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6949 ins_cost(150);
6950
6951 size(4);
6952 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6953 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6954 ins_pipe(ialu_reg);
6955 %}
6956
6957
6958
6959 //----------OS and Locking Instructions----------------------------------------
6960
6961 // This name is KNOWN by the ADLC and cannot be changed.
6962 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6963 // for this guy.
6964 instruct tlsLoadP(g2RegP dst) %{
6965 match(Set dst (ThreadLocal));
6966
6967 size(0);
6968 ins_cost(0);
6969 format %{ "# TLS is in G2" %}
6970 ins_encode( /*empty encoding*/ );
6971 ins_pipe(ialu_none);
6972 %}
6973
6974 instruct checkCastPP( iRegP dst ) %{
6975 match(Set dst (CheckCastPP dst));
6976
6977 size(0);
6978 format %{ "# checkcastPP of $dst" %}
6979 ins_encode( /*empty encoding*/ );
6980 ins_pipe(empty);
6981 %}
6982
6983
6984 instruct castPP( iRegP dst ) %{
6985 match(Set dst (CastPP dst));
6986 format %{ "# castPP of $dst" %}
6987 ins_encode( /*empty encoding*/ );
6988 ins_pipe(empty);
6989 %}
6990
6991 instruct castII( iRegI dst ) %{
6992 match(Set dst (CastII dst));
6993 format %{ "# castII of $dst" %}
6994 ins_encode( /*empty encoding*/ );
6995 ins_cost(0);
6996 ins_pipe(empty);
6997 %}
6998
6999 //----------Arithmetic Instructions--------------------------------------------
7000 // Addition Instructions
7001 // Register Addition
7002 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7003 match(Set dst (AddI src1 src2));
7004
7005 size(4);
7006 format %{ "ADD $src1,$src2,$dst" %}
7007 ins_encode %{
7008 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7009 %}
7010 ins_pipe(ialu_reg_reg);
7011 %}
7012
7013 // Immediate Addition
7014 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7015 match(Set dst (AddI src1 src2));
7016
7017 size(4);
7018 format %{ "ADD $src1,$src2,$dst" %}
7019 opcode(Assembler::add_op3, Assembler::arith_op);
7020 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7021 ins_pipe(ialu_reg_imm);
7022 %}
7023
7024 // Pointer Register Addition
7025 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7026 match(Set dst (AddP src1 src2));
7027
7028 size(4);
7029 format %{ "ADD $src1,$src2,$dst" %}
7030 opcode(Assembler::add_op3, Assembler::arith_op);
7031 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7032 ins_pipe(ialu_reg_reg);
7033 %}
7034
7035 // Pointer Immediate Addition
7036 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7037 match(Set dst (AddP src1 src2));
7038
7039 size(4);
7040 format %{ "ADD $src1,$src2,$dst" %}
7041 opcode(Assembler::add_op3, Assembler::arith_op);
7042 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7043 ins_pipe(ialu_reg_imm);
7044 %}
7045
7046 // Long Addition
7047 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7048 match(Set dst (AddL src1 src2));
7049
7050 size(4);
7051 format %{ "ADD $src1,$src2,$dst\t! long" %}
7052 opcode(Assembler::add_op3, Assembler::arith_op);
7053 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7054 ins_pipe(ialu_reg_reg);
7055 %}
7056
7057 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7058 match(Set dst (AddL src1 con));
7059
7060 size(4);
7061 format %{ "ADD $src1,$con,$dst" %}
7062 opcode(Assembler::add_op3, Assembler::arith_op);
7063 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7064 ins_pipe(ialu_reg_imm);
7065 %}
7066
7067 //----------Conditional_store--------------------------------------------------
7068 // Conditional-store of the updated heap-top.
7069 // Used during allocation of the shared heap.
7070 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7071
7072 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7073 instruct loadPLocked(iRegP dst, memory mem) %{
7074 match(Set dst (LoadPLocked mem));
7075 ins_cost(MEMORY_REF_COST);
7076
7077 #ifndef _LP64
7078 format %{ "LDUW $mem,$dst\t! ptr" %}
7079 opcode(Assembler::lduw_op3, 0, REGP_OP);
7080 #else
7081 format %{ "LDX $mem,$dst\t! ptr" %}
7082 opcode(Assembler::ldx_op3, 0, REGP_OP);
7083 #endif
7084 ins_encode( form3_mem_reg( mem, dst ) );
7085 ins_pipe(iload_mem);
7086 %}
7087
7088 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7089 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7090 effect( KILL newval );
7091 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7092 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7093 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7094 ins_pipe( long_memory_op );
7095 %}
7096
7097 // Conditional-store of an int value.
7098 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7099 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7100 effect( KILL newval );
7101 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7102 "CMP $oldval,$newval\t\t! See if we made progress" %}
7103 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7104 ins_pipe( long_memory_op );
7105 %}
7106
7107 // Conditional-store of a long value.
7108 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7109 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7110 effect( KILL newval );
7111 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7112 "CMP $oldval,$newval\t\t! See if we made progress" %}
7113 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7114 ins_pipe( long_memory_op );
7115 %}
7116
7117 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7118
7119 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7120 predicate(VM_Version::supports_cx8());
7121 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7122 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7123 format %{
7124 "MOV $newval,O7\n\t"
7125 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7126 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7127 "MOV 1,$res\n\t"
7128 "MOVne xcc,R_G0,$res"
7129 %}
7130 ins_encode( enc_casx(mem_ptr, oldval, newval),
7131 enc_lflags_ne_to_boolean(res) );
7132 ins_pipe( long_memory_op );
7133 %}
7134
7135
7136 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7137 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7138 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7139 format %{
7140 "MOV $newval,O7\n\t"
7141 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7142 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7143 "MOV 1,$res\n\t"
7144 "MOVne icc,R_G0,$res"
7145 %}
7146 ins_encode( enc_casi(mem_ptr, oldval, newval),
7147 enc_iflags_ne_to_boolean(res) );
7148 ins_pipe( long_memory_op );
7149 %}
7150
7151 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7152 #ifdef _LP64
7153 predicate(VM_Version::supports_cx8());
7154 #endif
7155 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7156 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7157 format %{
7158 "MOV $newval,O7\n\t"
7159 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7160 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7161 "MOV 1,$res\n\t"
7162 "MOVne xcc,R_G0,$res"
7163 %}
7164 #ifdef _LP64
7165 ins_encode( enc_casx(mem_ptr, oldval, newval),
7166 enc_lflags_ne_to_boolean(res) );
7167 #else
7168 ins_encode( enc_casi(mem_ptr, oldval, newval),
7169 enc_iflags_ne_to_boolean(res) );
7170 #endif
7171 ins_pipe( long_memory_op );
7172 %}
7173
7174 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7175 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7176 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7177 format %{
7178 "MOV $newval,O7\n\t"
7179 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7180 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7181 "MOV 1,$res\n\t"
7182 "MOVne icc,R_G0,$res"
7183 %}
7184 ins_encode( enc_casi(mem_ptr, oldval, newval),
7185 enc_iflags_ne_to_boolean(res) );
7186 ins_pipe( long_memory_op );
7187 %}
7188
7189 instruct xchgI( memory mem, iRegI newval) %{
7190 match(Set newval (GetAndSetI mem newval));
7191 format %{ "SWAP [$mem],$newval" %}
7192 size(4);
7193 ins_encode %{
7194 __ swap($mem$$Address, $newval$$Register);
7195 %}
7196 ins_pipe( long_memory_op );
7197 %}
7198
7199 #ifndef _LP64
7200 instruct xchgP( memory mem, iRegP newval) %{
7201 match(Set newval (GetAndSetP mem newval));
7202 format %{ "SWAP [$mem],$newval" %}
7203 size(4);
7204 ins_encode %{
7205 __ swap($mem$$Address, $newval$$Register);
7206 %}
7207 ins_pipe( long_memory_op );
7208 %}
7209 #endif
7210
7211 instruct xchgN( memory mem, iRegN newval) %{
7212 match(Set newval (GetAndSetN mem newval));
7213 format %{ "SWAP [$mem],$newval" %}
7214 size(4);
7215 ins_encode %{
7216 __ swap($mem$$Address, $newval$$Register);
7217 %}
7218 ins_pipe( long_memory_op );
7219 %}
7220
7221 //---------------------
7222 // Subtraction Instructions
7223 // Register Subtraction
7224 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7225 match(Set dst (SubI src1 src2));
7226
7227 size(4);
7228 format %{ "SUB $src1,$src2,$dst" %}
7229 opcode(Assembler::sub_op3, Assembler::arith_op);
7230 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7231 ins_pipe(ialu_reg_reg);
7232 %}
7233
7234 // Immediate Subtraction
7235 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7236 match(Set dst (SubI src1 src2));
7237
7238 size(4);
7239 format %{ "SUB $src1,$src2,$dst" %}
7240 opcode(Assembler::sub_op3, Assembler::arith_op);
7241 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7242 ins_pipe(ialu_reg_imm);
7243 %}
7244
7245 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7246 match(Set dst (SubI zero src2));
7247
7248 size(4);
7249 format %{ "NEG $src2,$dst" %}
7250 opcode(Assembler::sub_op3, Assembler::arith_op);
7251 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7252 ins_pipe(ialu_zero_reg);
7253 %}
7254
7255 // Long subtraction
7256 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7257 match(Set dst (SubL src1 src2));
7258
7259 size(4);
7260 format %{ "SUB $src1,$src2,$dst\t! long" %}
7261 opcode(Assembler::sub_op3, Assembler::arith_op);
7262 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7263 ins_pipe(ialu_reg_reg);
7264 %}
7265
7266 // Immediate Subtraction
7267 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7268 match(Set dst (SubL src1 con));
7269
7270 size(4);
7271 format %{ "SUB $src1,$con,$dst\t! long" %}
7272 opcode(Assembler::sub_op3, Assembler::arith_op);
7273 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7274 ins_pipe(ialu_reg_imm);
7275 %}
7276
7277 // Long negation
7278 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7279 match(Set dst (SubL zero src2));
7280
7281 size(4);
7282 format %{ "NEG $src2,$dst\t! long" %}
7283 opcode(Assembler::sub_op3, Assembler::arith_op);
7284 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7285 ins_pipe(ialu_zero_reg);
7286 %}
7287
7288 // Multiplication Instructions
7289 // Integer Multiplication
7290 // Register Multiplication
7291 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7292 match(Set dst (MulI src1 src2));
7293
7294 size(4);
7295 format %{ "MULX $src1,$src2,$dst" %}
7296 opcode(Assembler::mulx_op3, Assembler::arith_op);
7297 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7298 ins_pipe(imul_reg_reg);
7299 %}
7300
7301 // Immediate Multiplication
7302 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7303 match(Set dst (MulI src1 src2));
7304
7305 size(4);
7306 format %{ "MULX $src1,$src2,$dst" %}
7307 opcode(Assembler::mulx_op3, Assembler::arith_op);
7308 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7309 ins_pipe(imul_reg_imm);
7310 %}
7311
7312 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7313 match(Set dst (MulL src1 src2));
7314 ins_cost(DEFAULT_COST * 5);
7315 size(4);
7316 format %{ "MULX $src1,$src2,$dst\t! long" %}
7317 opcode(Assembler::mulx_op3, Assembler::arith_op);
7318 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7319 ins_pipe(mulL_reg_reg);
7320 %}
7321
7322 // Immediate Multiplication
7323 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7324 match(Set dst (MulL src1 src2));
7325 ins_cost(DEFAULT_COST * 5);
7326 size(4);
7327 format %{ "MULX $src1,$src2,$dst" %}
7328 opcode(Assembler::mulx_op3, Assembler::arith_op);
7329 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7330 ins_pipe(mulL_reg_imm);
7331 %}
7332
7333 // Integer Division
7334 // Register Division
7335 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7336 match(Set dst (DivI src1 src2));
7337 ins_cost((2+71)*DEFAULT_COST);
7338
7339 format %{ "SRA $src2,0,$src2\n\t"
7340 "SRA $src1,0,$src1\n\t"
7341 "SDIVX $src1,$src2,$dst" %}
7342 ins_encode( idiv_reg( src1, src2, dst ) );
7343 ins_pipe(sdiv_reg_reg);
7344 %}
7345
7346 // Immediate Division
7347 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7348 match(Set dst (DivI src1 src2));
7349 ins_cost((2+71)*DEFAULT_COST);
7350
7351 format %{ "SRA $src1,0,$src1\n\t"
7352 "SDIVX $src1,$src2,$dst" %}
7353 ins_encode( idiv_imm( src1, src2, dst ) );
7354 ins_pipe(sdiv_reg_imm);
7355 %}
7356
7357 //----------Div-By-10-Expansion------------------------------------------------
7358 // Extract hi bits of a 32x32->64 bit multiply.
7359 // Expand rule only, not matched
7360 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7361 effect( DEF dst, USE src1, USE src2 );
7362 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7363 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7364 ins_encode( enc_mul_hi(dst,src1,src2));
7365 ins_pipe(sdiv_reg_reg);
7366 %}
7367
7368 // Magic constant, reciprocal of 10
7369 instruct loadConI_x66666667(iRegIsafe dst) %{
7370 effect( DEF dst );
7371
7372 size(8);
7373 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7374 ins_encode( Set32(0x66666667, dst) );
7375 ins_pipe(ialu_hi_lo_reg);
7376 %}
7377
7378 // Register Shift Right Arithmetic Long by 32-63
7379 instruct sra_31( iRegI dst, iRegI src ) %{
7380 effect( DEF dst, USE src );
7381 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7382 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7383 ins_pipe(ialu_reg_reg);
7384 %}
7385
7386 // Arithmetic Shift Right by 8-bit immediate
7387 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7388 effect( DEF dst, USE src );
7389 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7390 opcode(Assembler::sra_op3, Assembler::arith_op);
7391 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7392 ins_pipe(ialu_reg_imm);
7393 %}
7394
7395 // Integer DIV with 10
7396 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7397 match(Set dst (DivI src div));
7398 ins_cost((6+6)*DEFAULT_COST);
7399 expand %{
7400 iRegIsafe tmp1; // Killed temps;
7401 iRegIsafe tmp2; // Killed temps;
7402 iRegI tmp3; // Killed temps;
7403 iRegI tmp4; // Killed temps;
7404 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7405 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7406 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7407 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7408 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7409 %}
7410 %}
7411
7412 // Register Long Division
7413 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7414 match(Set dst (DivL src1 src2));
7415 ins_cost(DEFAULT_COST*71);
7416 size(4);
7417 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7418 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7419 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7420 ins_pipe(divL_reg_reg);
7421 %}
7422
7423 // Register Long Division
7424 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7425 match(Set dst (DivL src1 src2));
7426 ins_cost(DEFAULT_COST*71);
7427 size(4);
7428 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7429 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7430 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7431 ins_pipe(divL_reg_imm);
7432 %}
7433
7434 // Integer Remainder
7435 // Register Remainder
7436 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7437 match(Set dst (ModI src1 src2));
7438 effect( KILL ccr, KILL temp);
7439
7440 format %{ "SREM $src1,$src2,$dst" %}
7441 ins_encode( irem_reg(src1, src2, dst, temp) );
7442 ins_pipe(sdiv_reg_reg);
7443 %}
7444
7445 // Immediate Remainder
7446 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7447 match(Set dst (ModI src1 src2));
7448 effect( KILL ccr, KILL temp);
7449
7450 format %{ "SREM $src1,$src2,$dst" %}
7451 ins_encode( irem_imm(src1, src2, dst, temp) );
7452 ins_pipe(sdiv_reg_imm);
7453 %}
7454
7455 // Register Long Remainder
7456 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7457 effect(DEF dst, USE src1, USE src2);
7458 size(4);
7459 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7460 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7461 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7462 ins_pipe(divL_reg_reg);
7463 %}
7464
7465 // Register Long Division
7466 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7467 effect(DEF dst, USE src1, USE src2);
7468 size(4);
7469 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7470 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7471 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7472 ins_pipe(divL_reg_imm);
7473 %}
7474
7475 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7476 effect(DEF dst, USE src1, USE src2);
7477 size(4);
7478 format %{ "MULX $src1,$src2,$dst\t! long" %}
7479 opcode(Assembler::mulx_op3, Assembler::arith_op);
7480 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7481 ins_pipe(mulL_reg_reg);
7482 %}
7483
7484 // Immediate Multiplication
7485 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7486 effect(DEF dst, USE src1, USE src2);
7487 size(4);
7488 format %{ "MULX $src1,$src2,$dst" %}
7489 opcode(Assembler::mulx_op3, Assembler::arith_op);
7490 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7491 ins_pipe(mulL_reg_imm);
7492 %}
7493
7494 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7495 effect(DEF dst, USE src1, USE src2);
7496 size(4);
7497 format %{ "SUB $src1,$src2,$dst\t! long" %}
7498 opcode(Assembler::sub_op3, Assembler::arith_op);
7499 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7500 ins_pipe(ialu_reg_reg);
7501 %}
7502
7503 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7504 effect(DEF dst, USE src1, USE src2);
7505 size(4);
7506 format %{ "SUB $src1,$src2,$dst\t! long" %}
7507 opcode(Assembler::sub_op3, Assembler::arith_op);
7508 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7509 ins_pipe(ialu_reg_reg);
7510 %}
7511
7512 // Register Long Remainder
7513 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7514 match(Set dst (ModL src1 src2));
7515 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7516 expand %{
7517 iRegL tmp1;
7518 iRegL tmp2;
7519 divL_reg_reg_1(tmp1, src1, src2);
7520 mulL_reg_reg_1(tmp2, tmp1, src2);
7521 subL_reg_reg_1(dst, src1, tmp2);
7522 %}
7523 %}
7524
7525 // Register Long Remainder
7526 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7527 match(Set dst (ModL src1 src2));
7528 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7529 expand %{
7530 iRegL tmp1;
7531 iRegL tmp2;
7532 divL_reg_imm13_1(tmp1, src1, src2);
7533 mulL_reg_imm13_1(tmp2, tmp1, src2);
7534 subL_reg_reg_2 (dst, src1, tmp2);
7535 %}
7536 %}
7537
7538 // Integer Shift Instructions
7539 // Register Shift Left
7540 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7541 match(Set dst (LShiftI src1 src2));
7542
7543 size(4);
7544 format %{ "SLL $src1,$src2,$dst" %}
7545 opcode(Assembler::sll_op3, Assembler::arith_op);
7546 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7547 ins_pipe(ialu_reg_reg);
7548 %}
7549
7550 // Register Shift Left Immediate
7551 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7552 match(Set dst (LShiftI src1 src2));
7553
7554 size(4);
7555 format %{ "SLL $src1,$src2,$dst" %}
7556 opcode(Assembler::sll_op3, Assembler::arith_op);
7557 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7558 ins_pipe(ialu_reg_imm);
7559 %}
7560
7561 // Register Shift Left
7562 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7563 match(Set dst (LShiftL src1 src2));
7564
7565 size(4);
7566 format %{ "SLLX $src1,$src2,$dst" %}
7567 opcode(Assembler::sllx_op3, Assembler::arith_op);
7568 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7569 ins_pipe(ialu_reg_reg);
7570 %}
7571
7572 // Register Shift Left Immediate
7573 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7574 match(Set dst (LShiftL src1 src2));
7575
7576 size(4);
7577 format %{ "SLLX $src1,$src2,$dst" %}
7578 opcode(Assembler::sllx_op3, Assembler::arith_op);
7579 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7580 ins_pipe(ialu_reg_imm);
7581 %}
7582
7583 // Register Arithmetic Shift Right
7584 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7585 match(Set dst (RShiftI src1 src2));
7586 size(4);
7587 format %{ "SRA $src1,$src2,$dst" %}
7588 opcode(Assembler::sra_op3, Assembler::arith_op);
7589 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7590 ins_pipe(ialu_reg_reg);
7591 %}
7592
7593 // Register Arithmetic Shift Right Immediate
7594 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7595 match(Set dst (RShiftI src1 src2));
7596
7597 size(4);
7598 format %{ "SRA $src1,$src2,$dst" %}
7599 opcode(Assembler::sra_op3, Assembler::arith_op);
7600 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7601 ins_pipe(ialu_reg_imm);
7602 %}
7603
7604 // Register Shift Right Arithmatic Long
7605 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7606 match(Set dst (RShiftL src1 src2));
7607
7608 size(4);
7609 format %{ "SRAX $src1,$src2,$dst" %}
7610 opcode(Assembler::srax_op3, Assembler::arith_op);
7611 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7612 ins_pipe(ialu_reg_reg);
7613 %}
7614
7615 // Register Shift Left Immediate
7616 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7617 match(Set dst (RShiftL src1 src2));
7618
7619 size(4);
7620 format %{ "SRAX $src1,$src2,$dst" %}
7621 opcode(Assembler::srax_op3, Assembler::arith_op);
7622 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7623 ins_pipe(ialu_reg_imm);
7624 %}
7625
7626 // Register Shift Right
7627 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7628 match(Set dst (URShiftI src1 src2));
7629
7630 size(4);
7631 format %{ "SRL $src1,$src2,$dst" %}
7632 opcode(Assembler::srl_op3, Assembler::arith_op);
7633 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7634 ins_pipe(ialu_reg_reg);
7635 %}
7636
7637 // Register Shift Right Immediate
7638 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7639 match(Set dst (URShiftI src1 src2));
7640
7641 size(4);
7642 format %{ "SRL $src1,$src2,$dst" %}
7643 opcode(Assembler::srl_op3, Assembler::arith_op);
7644 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7645 ins_pipe(ialu_reg_imm);
7646 %}
7647
7648 // Register Shift Right
7649 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7650 match(Set dst (URShiftL src1 src2));
7651
7652 size(4);
7653 format %{ "SRLX $src1,$src2,$dst" %}
7654 opcode(Assembler::srlx_op3, Assembler::arith_op);
7655 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7656 ins_pipe(ialu_reg_reg);
7657 %}
7658
7659 // Register Shift Right Immediate
7660 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7661 match(Set dst (URShiftL src1 src2));
7662
7663 size(4);
7664 format %{ "SRLX $src1,$src2,$dst" %}
7665 opcode(Assembler::srlx_op3, Assembler::arith_op);
7666 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7667 ins_pipe(ialu_reg_imm);
7668 %}
7669
7670 // Register Shift Right Immediate with a CastP2X
7671 #ifdef _LP64
7672 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7673 match(Set dst (URShiftL (CastP2X src1) src2));
7674 size(4);
7675 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7676 opcode(Assembler::srlx_op3, Assembler::arith_op);
7677 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7678 ins_pipe(ialu_reg_imm);
7679 %}
7680 #else
7681 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7682 match(Set dst (URShiftI (CastP2X src1) src2));
7683 size(4);
7684 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7685 opcode(Assembler::srl_op3, Assembler::arith_op);
7686 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7687 ins_pipe(ialu_reg_imm);
7688 %}
7689 #endif
7690
7691
7692 //----------Floating Point Arithmetic Instructions-----------------------------
7693
7694 // Add float single precision
7695 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7696 match(Set dst (AddF src1 src2));
7697
7698 size(4);
7699 format %{ "FADDS $src1,$src2,$dst" %}
7700 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7701 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7702 ins_pipe(faddF_reg_reg);
7703 %}
7704
7705 // Add float double precision
7706 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7707 match(Set dst (AddD src1 src2));
7708
7709 size(4);
7710 format %{ "FADDD $src1,$src2,$dst" %}
7711 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7712 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7713 ins_pipe(faddD_reg_reg);
7714 %}
7715
7716 // Sub float single precision
7717 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7718 match(Set dst (SubF src1 src2));
7719
7720 size(4);
7721 format %{ "FSUBS $src1,$src2,$dst" %}
7722 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7723 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7724 ins_pipe(faddF_reg_reg);
7725 %}
7726
7727 // Sub float double precision
7728 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7729 match(Set dst (SubD src1 src2));
7730
7731 size(4);
7732 format %{ "FSUBD $src1,$src2,$dst" %}
7733 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7734 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7735 ins_pipe(faddD_reg_reg);
7736 %}
7737
7738 // Mul float single precision
7739 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7740 match(Set dst (MulF src1 src2));
7741
7742 size(4);
7743 format %{ "FMULS $src1,$src2,$dst" %}
7744 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7745 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7746 ins_pipe(fmulF_reg_reg);
7747 %}
7748
7749 // Mul float double precision
7750 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7751 match(Set dst (MulD src1 src2));
7752
7753 size(4);
7754 format %{ "FMULD $src1,$src2,$dst" %}
7755 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7756 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7757 ins_pipe(fmulD_reg_reg);
7758 %}
7759
7760 // Div float single precision
7761 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7762 match(Set dst (DivF src1 src2));
7763
7764 size(4);
7765 format %{ "FDIVS $src1,$src2,$dst" %}
7766 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7767 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7768 ins_pipe(fdivF_reg_reg);
7769 %}
7770
7771 // Div float double precision
7772 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7773 match(Set dst (DivD src1 src2));
7774
7775 size(4);
7776 format %{ "FDIVD $src1,$src2,$dst" %}
7777 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7778 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7779 ins_pipe(fdivD_reg_reg);
7780 %}
7781
7782 // Absolute float double precision
7783 instruct absD_reg(regD dst, regD src) %{
7784 match(Set dst (AbsD src));
7785
7786 format %{ "FABSd $src,$dst" %}
7787 ins_encode(fabsd(dst, src));
7788 ins_pipe(faddD_reg);
7789 %}
7790
7791 // Absolute float single precision
7792 instruct absF_reg(regF dst, regF src) %{
7793 match(Set dst (AbsF src));
7794
7795 format %{ "FABSs $src,$dst" %}
7796 ins_encode(fabss(dst, src));
7797 ins_pipe(faddF_reg);
7798 %}
7799
7800 instruct negF_reg(regF dst, regF src) %{
7801 match(Set dst (NegF src));
7802
7803 size(4);
7804 format %{ "FNEGs $src,$dst" %}
7805 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7806 ins_encode(form3_opf_rs2F_rdF(src, dst));
7807 ins_pipe(faddF_reg);
7808 %}
7809
7810 instruct negD_reg(regD dst, regD src) %{
7811 match(Set dst (NegD src));
7812
7813 format %{ "FNEGd $src,$dst" %}
7814 ins_encode(fnegd(dst, src));
7815 ins_pipe(faddD_reg);
7816 %}
7817
7818 // Sqrt float double precision
7819 instruct sqrtF_reg_reg(regF dst, regF src) %{
7820 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7821
7822 size(4);
7823 format %{ "FSQRTS $src,$dst" %}
7824 ins_encode(fsqrts(dst, src));
7825 ins_pipe(fdivF_reg_reg);
7826 %}
7827
7828 // Sqrt float double precision
7829 instruct sqrtD_reg_reg(regD dst, regD src) %{
7830 match(Set dst (SqrtD src));
7831
7832 size(4);
7833 format %{ "FSQRTD $src,$dst" %}
7834 ins_encode(fsqrtd(dst, src));
7835 ins_pipe(fdivD_reg_reg);
7836 %}
7837
7838 //----------Logical Instructions-----------------------------------------------
7839 // And Instructions
7840 // Register And
7841 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7842 match(Set dst (AndI src1 src2));
7843
7844 size(4);
7845 format %{ "AND $src1,$src2,$dst" %}
7846 opcode(Assembler::and_op3, Assembler::arith_op);
7847 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7848 ins_pipe(ialu_reg_reg);
7849 %}
7850
7851 // Immediate And
7852 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7853 match(Set dst (AndI src1 src2));
7854
7855 size(4);
7856 format %{ "AND $src1,$src2,$dst" %}
7857 opcode(Assembler::and_op3, Assembler::arith_op);
7858 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7859 ins_pipe(ialu_reg_imm);
7860 %}
7861
7862 // Register And Long
7863 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7864 match(Set dst (AndL src1 src2));
7865
7866 ins_cost(DEFAULT_COST);
7867 size(4);
7868 format %{ "AND $src1,$src2,$dst\t! long" %}
7869 opcode(Assembler::and_op3, Assembler::arith_op);
7870 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7871 ins_pipe(ialu_reg_reg);
7872 %}
7873
7874 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7875 match(Set dst (AndL src1 con));
7876
7877 ins_cost(DEFAULT_COST);
7878 size(4);
7879 format %{ "AND $src1,$con,$dst\t! long" %}
7880 opcode(Assembler::and_op3, Assembler::arith_op);
7881 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7882 ins_pipe(ialu_reg_imm);
7883 %}
7884
7885 // Or Instructions
7886 // Register Or
7887 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7888 match(Set dst (OrI src1 src2));
7889
7890 size(4);
7891 format %{ "OR $src1,$src2,$dst" %}
7892 opcode(Assembler::or_op3, Assembler::arith_op);
7893 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7894 ins_pipe(ialu_reg_reg);
7895 %}
7896
7897 // Immediate Or
7898 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7899 match(Set dst (OrI src1 src2));
7900
7901 size(4);
7902 format %{ "OR $src1,$src2,$dst" %}
7903 opcode(Assembler::or_op3, Assembler::arith_op);
7904 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7905 ins_pipe(ialu_reg_imm);
7906 %}
7907
7908 // Register Or Long
7909 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7910 match(Set dst (OrL src1 src2));
7911
7912 ins_cost(DEFAULT_COST);
7913 size(4);
7914 format %{ "OR $src1,$src2,$dst\t! long" %}
7915 opcode(Assembler::or_op3, Assembler::arith_op);
7916 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7917 ins_pipe(ialu_reg_reg);
7918 %}
7919
7920 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7921 match(Set dst (OrL src1 con));
7922 ins_cost(DEFAULT_COST*2);
7923
7924 ins_cost(DEFAULT_COST);
7925 size(4);
7926 format %{ "OR $src1,$con,$dst\t! long" %}
7927 opcode(Assembler::or_op3, Assembler::arith_op);
7928 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7929 ins_pipe(ialu_reg_imm);
7930 %}
7931
7932 #ifndef _LP64
7933
7934 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7935 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7936 match(Set dst (OrI src1 (CastP2X src2)));
7937
7938 size(4);
7939 format %{ "OR $src1,$src2,$dst" %}
7940 opcode(Assembler::or_op3, Assembler::arith_op);
7941 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7942 ins_pipe(ialu_reg_reg);
7943 %}
7944
7945 #else
7946
7947 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7948 match(Set dst (OrL src1 (CastP2X src2)));
7949
7950 ins_cost(DEFAULT_COST);
7951 size(4);
7952 format %{ "OR $src1,$src2,$dst\t! long" %}
7953 opcode(Assembler::or_op3, Assembler::arith_op);
7954 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7955 ins_pipe(ialu_reg_reg);
7956 %}
7957
7958 #endif
7959
7960 // Xor Instructions
7961 // Register Xor
7962 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7963 match(Set dst (XorI src1 src2));
7964
7965 size(4);
7966 format %{ "XOR $src1,$src2,$dst" %}
7967 opcode(Assembler::xor_op3, Assembler::arith_op);
7968 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7969 ins_pipe(ialu_reg_reg);
7970 %}
7971
7972 // Immediate Xor
7973 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7974 match(Set dst (XorI src1 src2));
7975
7976 size(4);
7977 format %{ "XOR $src1,$src2,$dst" %}
7978 opcode(Assembler::xor_op3, Assembler::arith_op);
7979 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7980 ins_pipe(ialu_reg_imm);
7981 %}
7982
7983 // Register Xor Long
7984 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7985 match(Set dst (XorL src1 src2));
7986
7987 ins_cost(DEFAULT_COST);
7988 size(4);
7989 format %{ "XOR $src1,$src2,$dst\t! long" %}
7990 opcode(Assembler::xor_op3, Assembler::arith_op);
7991 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7992 ins_pipe(ialu_reg_reg);
7993 %}
7994
7995 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7996 match(Set dst (XorL src1 con));
7997
7998 ins_cost(DEFAULT_COST);
7999 size(4);
8000 format %{ "XOR $src1,$con,$dst\t! long" %}
8001 opcode(Assembler::xor_op3, Assembler::arith_op);
8002 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8003 ins_pipe(ialu_reg_imm);
8004 %}
8005
8006 //----------Convert to Boolean-------------------------------------------------
8007 // Nice hack for 32-bit tests but doesn't work for
8008 // 64-bit pointers.
8009 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8010 match(Set dst (Conv2B src));
8011 effect( KILL ccr );
8012 ins_cost(DEFAULT_COST*2);
8013 format %{ "CMP R_G0,$src\n\t"
8014 "ADDX R_G0,0,$dst" %}
8015 ins_encode( enc_to_bool( src, dst ) );
8016 ins_pipe(ialu_reg_ialu);
8017 %}
8018
8019 #ifndef _LP64
8020 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8021 match(Set dst (Conv2B src));
8022 effect( KILL ccr );
8023 ins_cost(DEFAULT_COST*2);
8024 format %{ "CMP R_G0,$src\n\t"
8025 "ADDX R_G0,0,$dst" %}
8026 ins_encode( enc_to_bool( src, dst ) );
8027 ins_pipe(ialu_reg_ialu);
8028 %}
8029 #else
8030 instruct convP2B( iRegI dst, iRegP src ) %{
8031 match(Set dst (Conv2B src));
8032 ins_cost(DEFAULT_COST*2);
8033 format %{ "MOV $src,$dst\n\t"
8034 "MOVRNZ $src,1,$dst" %}
8035 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8036 ins_pipe(ialu_clr_and_mover);
8037 %}
8038 #endif
8039
8040 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8041 match(Set dst (CmpLTMask src zero));
8042 effect(KILL ccr);
8043 size(4);
8044 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8045 ins_encode %{
8046 __ sra($src$$Register, 31, $dst$$Register);
8047 %}
8048 ins_pipe(ialu_reg_imm);
8049 %}
8050
8051 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8052 match(Set dst (CmpLTMask p q));
8053 effect( KILL ccr );
8054 ins_cost(DEFAULT_COST*4);
8055 format %{ "CMP $p,$q\n\t"
8056 "MOV #0,$dst\n\t"
8057 "BLT,a .+8\n\t"
8058 "MOV #-1,$dst" %}
8059 ins_encode( enc_ltmask(p,q,dst) );
8060 ins_pipe(ialu_reg_reg_ialu);
8061 %}
8062
8063 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8064 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8065 effect(KILL ccr, TEMP tmp);
8066 ins_cost(DEFAULT_COST*3);
8067
8068 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8069 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8070 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8071 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8072 ins_pipe(cadd_cmpltmask);
8073 %}
8074
8075 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8076 match(Set p (AndI (CmpLTMask p q) y));
8077 effect(KILL ccr);
8078 ins_cost(DEFAULT_COST*3);
8079
8080 format %{ "CMP $p,$q\n\t"
8081 "MOV $y,$p\n\t"
8082 "MOVge G0,$p" %}
8083 ins_encode %{
8084 __ cmp($p$$Register, $q$$Register);
8085 __ mov($y$$Register, $p$$Register);
8086 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8087 %}
8088 ins_pipe(ialu_reg_reg_ialu);
8089 %}
8090
8091 //-----------------------------------------------------------------
8092 // Direct raw moves between float and general registers using VIS3.
8093
8094 // ins_pipe(faddF_reg);
8095 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8096 predicate(UseVIS >= 3);
8097 match(Set dst (MoveF2I src));
8098
8099 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8100 ins_encode %{
8101 __ movstouw($src$$FloatRegister, $dst$$Register);
8102 %}
8103 ins_pipe(ialu_reg_reg);
8104 %}
8105
8106 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8107 predicate(UseVIS >= 3);
8108 match(Set dst (MoveI2F src));
8109
8110 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8111 ins_encode %{
8112 __ movwtos($src$$Register, $dst$$FloatRegister);
8113 %}
8114 ins_pipe(ialu_reg_reg);
8115 %}
8116
8117 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8118 predicate(UseVIS >= 3);
8119 match(Set dst (MoveD2L src));
8120
8121 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8122 ins_encode %{
8123 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8124 %}
8125 ins_pipe(ialu_reg_reg);
8126 %}
8127
8128 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8129 predicate(UseVIS >= 3);
8130 match(Set dst (MoveL2D src));
8131
8132 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8133 ins_encode %{
8134 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8135 %}
8136 ins_pipe(ialu_reg_reg);
8137 %}
8138
8139
8140 // Raw moves between float and general registers using stack.
8141
8142 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8143 match(Set dst (MoveF2I src));
8144 effect(DEF dst, USE src);
8145 ins_cost(MEMORY_REF_COST);
8146
8147 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8148 opcode(Assembler::lduw_op3);
8149 ins_encode(simple_form3_mem_reg( src, dst ) );
8150 ins_pipe(iload_mem);
8151 %}
8152
8153 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8154 match(Set dst (MoveI2F src));
8155 effect(DEF dst, USE src);
8156 ins_cost(MEMORY_REF_COST);
8157
8158 format %{ "LDF $src,$dst\t! MoveI2F" %}
8159 opcode(Assembler::ldf_op3);
8160 ins_encode(simple_form3_mem_reg(src, dst));
8161 ins_pipe(floadF_stk);
8162 %}
8163
8164 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8165 match(Set dst (MoveD2L src));
8166 effect(DEF dst, USE src);
8167 ins_cost(MEMORY_REF_COST);
8168
8169 format %{ "LDX $src,$dst\t! MoveD2L" %}
8170 opcode(Assembler::ldx_op3);
8171 ins_encode(simple_form3_mem_reg( src, dst ) );
8172 ins_pipe(iload_mem);
8173 %}
8174
8175 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8176 match(Set dst (MoveL2D src));
8177 effect(DEF dst, USE src);
8178 ins_cost(MEMORY_REF_COST);
8179
8180 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8181 opcode(Assembler::lddf_op3);
8182 ins_encode(simple_form3_mem_reg(src, dst));
8183 ins_pipe(floadD_stk);
8184 %}
8185
8186 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8187 match(Set dst (MoveF2I src));
8188 effect(DEF dst, USE src);
8189 ins_cost(MEMORY_REF_COST);
8190
8191 format %{ "STF $src,$dst\t! MoveF2I" %}
8192 opcode(Assembler::stf_op3);
8193 ins_encode(simple_form3_mem_reg(dst, src));
8194 ins_pipe(fstoreF_stk_reg);
8195 %}
8196
8197 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8198 match(Set dst (MoveI2F src));
8199 effect(DEF dst, USE src);
8200 ins_cost(MEMORY_REF_COST);
8201
8202 format %{ "STW $src,$dst\t! MoveI2F" %}
8203 opcode(Assembler::stw_op3);
8204 ins_encode(simple_form3_mem_reg( dst, src ) );
8205 ins_pipe(istore_mem_reg);
8206 %}
8207
8208 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8209 match(Set dst (MoveD2L src));
8210 effect(DEF dst, USE src);
8211 ins_cost(MEMORY_REF_COST);
8212
8213 format %{ "STDF $src,$dst\t! MoveD2L" %}
8214 opcode(Assembler::stdf_op3);
8215 ins_encode(simple_form3_mem_reg(dst, src));
8216 ins_pipe(fstoreD_stk_reg);
8217 %}
8218
8219 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8220 match(Set dst (MoveL2D src));
8221 effect(DEF dst, USE src);
8222 ins_cost(MEMORY_REF_COST);
8223
8224 format %{ "STX $src,$dst\t! MoveL2D" %}
8225 opcode(Assembler::stx_op3);
8226 ins_encode(simple_form3_mem_reg( dst, src ) );
8227 ins_pipe(istore_mem_reg);
8228 %}
8229
8230
8231 //----------Arithmetic Conversion Instructions---------------------------------
8232 // The conversions operations are all Alpha sorted. Please keep it that way!
8233
8234 instruct convD2F_reg(regF dst, regD src) %{
8235 match(Set dst (ConvD2F src));
8236 size(4);
8237 format %{ "FDTOS $src,$dst" %}
8238 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8239 ins_encode(form3_opf_rs2D_rdF(src, dst));
8240 ins_pipe(fcvtD2F);
8241 %}
8242
8243
8244 // Convert a double to an int in a float register.
8245 // If the double is a NAN, stuff a zero in instead.
8246 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8247 effect(DEF dst, USE src, KILL fcc0);
8248 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8249 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8250 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8251 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8252 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8253 "skip:" %}
8254 ins_encode(form_d2i_helper(src,dst));
8255 ins_pipe(fcvtD2I);
8256 %}
8257
8258 instruct convD2I_stk(stackSlotI dst, regD src) %{
8259 match(Set dst (ConvD2I src));
8260 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8261 expand %{
8262 regF tmp;
8263 convD2I_helper(tmp, src);
8264 regF_to_stkI(dst, tmp);
8265 %}
8266 %}
8267
8268 instruct convD2I_reg(iRegI dst, regD src) %{
8269 predicate(UseVIS >= 3);
8270 match(Set dst (ConvD2I src));
8271 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8272 expand %{
8273 regF tmp;
8274 convD2I_helper(tmp, src);
8275 MoveF2I_reg_reg(dst, tmp);
8276 %}
8277 %}
8278
8279
8280 // Convert a double to a long in a double register.
8281 // If the double is a NAN, stuff a zero in instead.
8282 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8283 effect(DEF dst, USE src, KILL fcc0);
8284 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8285 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8286 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8287 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8288 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8289 "skip:" %}
8290 ins_encode(form_d2l_helper(src,dst));
8291 ins_pipe(fcvtD2L);
8292 %}
8293
8294 instruct convD2L_stk(stackSlotL dst, regD src) %{
8295 match(Set dst (ConvD2L src));
8296 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8297 expand %{
8298 regD tmp;
8299 convD2L_helper(tmp, src);
8300 regD_to_stkL(dst, tmp);
8301 %}
8302 %}
8303
8304 instruct convD2L_reg(iRegL dst, regD src) %{
8305 predicate(UseVIS >= 3);
8306 match(Set dst (ConvD2L src));
8307 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8308 expand %{
8309 regD tmp;
8310 convD2L_helper(tmp, src);
8311 MoveD2L_reg_reg(dst, tmp);
8312 %}
8313 %}
8314
8315
8316 instruct convF2D_reg(regD dst, regF src) %{
8317 match(Set dst (ConvF2D src));
8318 format %{ "FSTOD $src,$dst" %}
8319 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8320 ins_encode(form3_opf_rs2F_rdD(src, dst));
8321 ins_pipe(fcvtF2D);
8322 %}
8323
8324
8325 // Convert a float to an int in a float register.
8326 // If the float is a NAN, stuff a zero in instead.
8327 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8328 effect(DEF dst, USE src, KILL fcc0);
8329 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8330 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8331 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8332 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8333 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8334 "skip:" %}
8335 ins_encode(form_f2i_helper(src,dst));
8336 ins_pipe(fcvtF2I);
8337 %}
8338
8339 instruct convF2I_stk(stackSlotI dst, regF src) %{
8340 match(Set dst (ConvF2I src));
8341 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8342 expand %{
8343 regF tmp;
8344 convF2I_helper(tmp, src);
8345 regF_to_stkI(dst, tmp);
8346 %}
8347 %}
8348
8349 instruct convF2I_reg(iRegI dst, regF src) %{
8350 predicate(UseVIS >= 3);
8351 match(Set dst (ConvF2I src));
8352 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8353 expand %{
8354 regF tmp;
8355 convF2I_helper(tmp, src);
8356 MoveF2I_reg_reg(dst, tmp);
8357 %}
8358 %}
8359
8360
8361 // Convert a float to a long in a float register.
8362 // If the float is a NAN, stuff a zero in instead.
8363 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8364 effect(DEF dst, USE src, KILL fcc0);
8365 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8366 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8367 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8368 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8369 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8370 "skip:" %}
8371 ins_encode(form_f2l_helper(src,dst));
8372 ins_pipe(fcvtF2L);
8373 %}
8374
8375 instruct convF2L_stk(stackSlotL dst, regF src) %{
8376 match(Set dst (ConvF2L src));
8377 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8378 expand %{
8379 regD tmp;
8380 convF2L_helper(tmp, src);
8381 regD_to_stkL(dst, tmp);
8382 %}
8383 %}
8384
8385 instruct convF2L_reg(iRegL dst, regF src) %{
8386 predicate(UseVIS >= 3);
8387 match(Set dst (ConvF2L src));
8388 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8389 expand %{
8390 regD tmp;
8391 convF2L_helper(tmp, src);
8392 MoveD2L_reg_reg(dst, tmp);
8393 %}
8394 %}
8395
8396
8397 instruct convI2D_helper(regD dst, regF tmp) %{
8398 effect(USE tmp, DEF dst);
8399 format %{ "FITOD $tmp,$dst" %}
8400 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8401 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8402 ins_pipe(fcvtI2D);
8403 %}
8404
8405 instruct convI2D_stk(stackSlotI src, regD dst) %{
8406 match(Set dst (ConvI2D src));
8407 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8408 expand %{
8409 regF tmp;
8410 stkI_to_regF(tmp, src);
8411 convI2D_helper(dst, tmp);
8412 %}
8413 %}
8414
8415 instruct convI2D_reg(regD_low dst, iRegI src) %{
8416 predicate(UseVIS >= 3);
8417 match(Set dst (ConvI2D src));
8418 expand %{
8419 regF tmp;
8420 MoveI2F_reg_reg(tmp, src);
8421 convI2D_helper(dst, tmp);
8422 %}
8423 %}
8424
8425 instruct convI2D_mem(regD_low dst, memory mem) %{
8426 match(Set dst (ConvI2D (LoadI mem)));
8427 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8428 format %{ "LDF $mem,$dst\n\t"
8429 "FITOD $dst,$dst" %}
8430 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8431 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8432 ins_pipe(floadF_mem);
8433 %}
8434
8435
8436 instruct convI2F_helper(regF dst, regF tmp) %{
8437 effect(DEF dst, USE tmp);
8438 format %{ "FITOS $tmp,$dst" %}
8439 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8440 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8441 ins_pipe(fcvtI2F);
8442 %}
8443
8444 instruct convI2F_stk(regF dst, stackSlotI src) %{
8445 match(Set dst (ConvI2F src));
8446 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8447 expand %{
8448 regF tmp;
8449 stkI_to_regF(tmp,src);
8450 convI2F_helper(dst, tmp);
8451 %}
8452 %}
8453
8454 instruct convI2F_reg(regF dst, iRegI src) %{
8455 predicate(UseVIS >= 3);
8456 match(Set dst (ConvI2F src));
8457 ins_cost(DEFAULT_COST);
8458 expand %{
8459 regF tmp;
8460 MoveI2F_reg_reg(tmp, src);
8461 convI2F_helper(dst, tmp);
8462 %}
8463 %}
8464
8465 instruct convI2F_mem( regF dst, memory mem ) %{
8466 match(Set dst (ConvI2F (LoadI mem)));
8467 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8468 format %{ "LDF $mem,$dst\n\t"
8469 "FITOS $dst,$dst" %}
8470 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8471 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8472 ins_pipe(floadF_mem);
8473 %}
8474
8475
8476 instruct convI2L_reg(iRegL dst, iRegI src) %{
8477 match(Set dst (ConvI2L src));
8478 size(4);
8479 format %{ "SRA $src,0,$dst\t! int->long" %}
8480 opcode(Assembler::sra_op3, Assembler::arith_op);
8481 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8482 ins_pipe(ialu_reg_reg);
8483 %}
8484
8485 // Zero-extend convert int to long
8486 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8487 match(Set dst (AndL (ConvI2L src) mask) );
8488 size(4);
8489 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8490 opcode(Assembler::srl_op3, Assembler::arith_op);
8491 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8492 ins_pipe(ialu_reg_reg);
8493 %}
8494
8495 // Zero-extend long
8496 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8497 match(Set dst (AndL src mask) );
8498 size(4);
8499 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8500 opcode(Assembler::srl_op3, Assembler::arith_op);
8501 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8502 ins_pipe(ialu_reg_reg);
8503 %}
8504
8505
8506 //-----------
8507 // Long to Double conversion using V8 opcodes.
8508 // Still useful because cheetah traps and becomes
8509 // amazingly slow for some common numbers.
8510
8511 // Magic constant, 0x43300000
8512 instruct loadConI_x43300000(iRegI dst) %{
8513 effect(DEF dst);
8514 size(4);
8515 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8516 ins_encode(SetHi22(0x43300000, dst));
8517 ins_pipe(ialu_none);
8518 %}
8519
8520 // Magic constant, 0x41f00000
8521 instruct loadConI_x41f00000(iRegI dst) %{
8522 effect(DEF dst);
8523 size(4);
8524 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8525 ins_encode(SetHi22(0x41f00000, dst));
8526 ins_pipe(ialu_none);
8527 %}
8528
8529 // Construct a double from two float halves
8530 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8531 effect(DEF dst, USE src1, USE src2);
8532 size(8);
8533 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8534 "FMOVS $src2.lo,$dst.lo" %}
8535 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8536 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8537 ins_pipe(faddD_reg_reg);
8538 %}
8539
8540 // Convert integer in high half of a double register (in the lower half of
8541 // the double register file) to double
8542 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8543 effect(DEF dst, USE src);
8544 size(4);
8545 format %{ "FITOD $src,$dst" %}
8546 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8547 ins_encode(form3_opf_rs2D_rdD(src, dst));
8548 ins_pipe(fcvtLHi2D);
8549 %}
8550
8551 // Add float double precision
8552 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8553 effect(DEF dst, USE src1, USE src2);
8554 size(4);
8555 format %{ "FADDD $src1,$src2,$dst" %}
8556 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8557 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8558 ins_pipe(faddD_reg_reg);
8559 %}
8560
8561 // Sub float double precision
8562 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8563 effect(DEF dst, USE src1, USE src2);
8564 size(4);
8565 format %{ "FSUBD $src1,$src2,$dst" %}
8566 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8567 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8568 ins_pipe(faddD_reg_reg);
8569 %}
8570
8571 // Mul float double precision
8572 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8573 effect(DEF dst, USE src1, USE src2);
8574 size(4);
8575 format %{ "FMULD $src1,$src2,$dst" %}
8576 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8577 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8578 ins_pipe(fmulD_reg_reg);
8579 %}
8580
8581 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8582 match(Set dst (ConvL2D src));
8583 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8584
8585 expand %{
8586 regD_low tmpsrc;
8587 iRegI ix43300000;
8588 iRegI ix41f00000;
8589 stackSlotL lx43300000;
8590 stackSlotL lx41f00000;
8591 regD_low dx43300000;
8592 regD dx41f00000;
8593 regD tmp1;
8594 regD_low tmp2;
8595 regD tmp3;
8596 regD tmp4;
8597
8598 stkL_to_regD(tmpsrc, src);
8599
8600 loadConI_x43300000(ix43300000);
8601 loadConI_x41f00000(ix41f00000);
8602 regI_to_stkLHi(lx43300000, ix43300000);
8603 regI_to_stkLHi(lx41f00000, ix41f00000);
8604 stkL_to_regD(dx43300000, lx43300000);
8605 stkL_to_regD(dx41f00000, lx41f00000);
8606
8607 convI2D_regDHi_regD(tmp1, tmpsrc);
8608 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8609 subD_regD_regD(tmp3, tmp2, dx43300000);
8610 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8611 addD_regD_regD(dst, tmp3, tmp4);
8612 %}
8613 %}
8614
8615 // Long to Double conversion using fast fxtof
8616 instruct convL2D_helper(regD dst, regD tmp) %{
8617 effect(DEF dst, USE tmp);
8618 size(4);
8619 format %{ "FXTOD $tmp,$dst" %}
8620 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8621 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8622 ins_pipe(fcvtL2D);
8623 %}
8624
8625 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8626 predicate(VM_Version::has_fast_fxtof());
8627 match(Set dst (ConvL2D src));
8628 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8629 expand %{
8630 regD tmp;
8631 stkL_to_regD(tmp, src);
8632 convL2D_helper(dst, tmp);
8633 %}
8634 %}
8635
8636 instruct convL2D_reg(regD dst, iRegL src) %{
8637 predicate(UseVIS >= 3);
8638 match(Set dst (ConvL2D src));
8639 expand %{
8640 regD tmp;
8641 MoveL2D_reg_reg(tmp, src);
8642 convL2D_helper(dst, tmp);
8643 %}
8644 %}
8645
8646 // Long to Float conversion using fast fxtof
8647 instruct convL2F_helper(regF dst, regD tmp) %{
8648 effect(DEF dst, USE tmp);
8649 size(4);
8650 format %{ "FXTOS $tmp,$dst" %}
8651 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8652 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8653 ins_pipe(fcvtL2F);
8654 %}
8655
8656 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8657 match(Set dst (ConvL2F src));
8658 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8659 expand %{
8660 regD tmp;
8661 stkL_to_regD(tmp, src);
8662 convL2F_helper(dst, tmp);
8663 %}
8664 %}
8665
8666 instruct convL2F_reg(regF dst, iRegL src) %{
8667 predicate(UseVIS >= 3);
8668 match(Set dst (ConvL2F src));
8669 ins_cost(DEFAULT_COST);
8670 expand %{
8671 regD tmp;
8672 MoveL2D_reg_reg(tmp, src);
8673 convL2F_helper(dst, tmp);
8674 %}
8675 %}
8676
8677 //-----------
8678
8679 instruct convL2I_reg(iRegI dst, iRegL src) %{
8680 match(Set dst (ConvL2I src));
8681 #ifndef _LP64
8682 format %{ "MOV $src.lo,$dst\t! long->int" %}
8683 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8684 ins_pipe(ialu_move_reg_I_to_L);
8685 #else
8686 size(4);
8687 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8688 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8689 ins_pipe(ialu_reg);
8690 #endif
8691 %}
8692
8693 // Register Shift Right Immediate
8694 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8695 match(Set dst (ConvL2I (RShiftL src cnt)));
8696
8697 size(4);
8698 format %{ "SRAX $src,$cnt,$dst" %}
8699 opcode(Assembler::srax_op3, Assembler::arith_op);
8700 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8701 ins_pipe(ialu_reg_imm);
8702 %}
8703
8704 //----------Control Flow Instructions------------------------------------------
8705 // Compare Instructions
8706 // Compare Integers
8707 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8708 match(Set icc (CmpI op1 op2));
8709 effect( DEF icc, USE op1, USE op2 );
8710
8711 size(4);
8712 format %{ "CMP $op1,$op2" %}
8713 opcode(Assembler::subcc_op3, Assembler::arith_op);
8714 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8715 ins_pipe(ialu_cconly_reg_reg);
8716 %}
8717
8718 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8719 match(Set icc (CmpU op1 op2));
8720
8721 size(4);
8722 format %{ "CMP $op1,$op2\t! unsigned" %}
8723 opcode(Assembler::subcc_op3, Assembler::arith_op);
8724 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8725 ins_pipe(ialu_cconly_reg_reg);
8726 %}
8727
8728 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8729 match(Set icc (CmpI op1 op2));
8730 effect( DEF icc, USE op1 );
8731
8732 size(4);
8733 format %{ "CMP $op1,$op2" %}
8734 opcode(Assembler::subcc_op3, Assembler::arith_op);
8735 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8736 ins_pipe(ialu_cconly_reg_imm);
8737 %}
8738
8739 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8740 match(Set icc (CmpI (AndI op1 op2) zero));
8741
8742 size(4);
8743 format %{ "BTST $op2,$op1" %}
8744 opcode(Assembler::andcc_op3, Assembler::arith_op);
8745 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8746 ins_pipe(ialu_cconly_reg_reg_zero);
8747 %}
8748
8749 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8750 match(Set icc (CmpI (AndI op1 op2) zero));
8751
8752 size(4);
8753 format %{ "BTST $op2,$op1" %}
8754 opcode(Assembler::andcc_op3, Assembler::arith_op);
8755 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8756 ins_pipe(ialu_cconly_reg_imm_zero);
8757 %}
8758
8759 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8760 match(Set xcc (CmpL op1 op2));
8761 effect( DEF xcc, USE op1, USE op2 );
8762
8763 size(4);
8764 format %{ "CMP $op1,$op2\t\t! long" %}
8765 opcode(Assembler::subcc_op3, Assembler::arith_op);
8766 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8767 ins_pipe(ialu_cconly_reg_reg);
8768 %}
8769
8770 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8771 match(Set xcc (CmpL op1 con));
8772 effect( DEF xcc, USE op1, USE con );
8773
8774 size(4);
8775 format %{ "CMP $op1,$con\t\t! long" %}
8776 opcode(Assembler::subcc_op3, Assembler::arith_op);
8777 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8778 ins_pipe(ialu_cconly_reg_reg);
8779 %}
8780
8781 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8782 match(Set xcc (CmpL (AndL op1 op2) zero));
8783 effect( DEF xcc, USE op1, USE op2 );
8784
8785 size(4);
8786 format %{ "BTST $op1,$op2\t\t! long" %}
8787 opcode(Assembler::andcc_op3, Assembler::arith_op);
8788 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8789 ins_pipe(ialu_cconly_reg_reg);
8790 %}
8791
8792 // useful for checking the alignment of a pointer:
8793 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8794 match(Set xcc (CmpL (AndL op1 con) zero));
8795 effect( DEF xcc, USE op1, USE con );
8796
8797 size(4);
8798 format %{ "BTST $op1,$con\t\t! long" %}
8799 opcode(Assembler::andcc_op3, Assembler::arith_op);
8800 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8801 ins_pipe(ialu_cconly_reg_reg);
8802 %}
8803
8804 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8805 match(Set icc (CmpU op1 op2));
8806
8807 size(4);
8808 format %{ "CMP $op1,$op2\t! unsigned" %}
8809 opcode(Assembler::subcc_op3, Assembler::arith_op);
8810 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8811 ins_pipe(ialu_cconly_reg_imm);
8812 %}
8813
8814 // Compare Pointers
8815 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8816 match(Set pcc (CmpP op1 op2));
8817
8818 size(4);
8819 format %{ "CMP $op1,$op2\t! ptr" %}
8820 opcode(Assembler::subcc_op3, Assembler::arith_op);
8821 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8822 ins_pipe(ialu_cconly_reg_reg);
8823 %}
8824
8825 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8826 match(Set pcc (CmpP op1 op2));
8827
8828 size(4);
8829 format %{ "CMP $op1,$op2\t! ptr" %}
8830 opcode(Assembler::subcc_op3, Assembler::arith_op);
8831 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8832 ins_pipe(ialu_cconly_reg_imm);
8833 %}
8834
8835 // Compare Narrow oops
8836 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8837 match(Set icc (CmpN op1 op2));
8838
8839 size(4);
8840 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8841 opcode(Assembler::subcc_op3, Assembler::arith_op);
8842 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8843 ins_pipe(ialu_cconly_reg_reg);
8844 %}
8845
8846 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8847 match(Set icc (CmpN op1 op2));
8848
8849 size(4);
8850 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8851 opcode(Assembler::subcc_op3, Assembler::arith_op);
8852 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8853 ins_pipe(ialu_cconly_reg_imm);
8854 %}
8855
8856 //----------Max and Min--------------------------------------------------------
8857 // Min Instructions
8858 // Conditional move for min
8859 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8860 effect( USE_DEF op2, USE op1, USE icc );
8861
8862 size(4);
8863 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8864 opcode(Assembler::less);
8865 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8866 ins_pipe(ialu_reg_flags);
8867 %}
8868
8869 // Min Register with Register.
8870 instruct minI_eReg(iRegI op1, iRegI op2) %{
8871 match(Set op2 (MinI op1 op2));
8872 ins_cost(DEFAULT_COST*2);
8873 expand %{
8874 flagsReg icc;
8875 compI_iReg(icc,op1,op2);
8876 cmovI_reg_lt(op2,op1,icc);
8877 %}
8878 %}
8879
8880 // Max Instructions
8881 // Conditional move for max
8882 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8883 effect( USE_DEF op2, USE op1, USE icc );
8884 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8885 opcode(Assembler::greater);
8886 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8887 ins_pipe(ialu_reg_flags);
8888 %}
8889
8890 // Max Register with Register
8891 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8892 match(Set op2 (MaxI op1 op2));
8893 ins_cost(DEFAULT_COST*2);
8894 expand %{
8895 flagsReg icc;
8896 compI_iReg(icc,op1,op2);
8897 cmovI_reg_gt(op2,op1,icc);
8898 %}
8899 %}
8900
8901
8902 //----------Float Compares----------------------------------------------------
8903 // Compare floating, generate condition code
8904 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8905 match(Set fcc (CmpF src1 src2));
8906
8907 size(4);
8908 format %{ "FCMPs $fcc,$src1,$src2" %}
8909 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8910 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8911 ins_pipe(faddF_fcc_reg_reg_zero);
8912 %}
8913
8914 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8915 match(Set fcc (CmpD src1 src2));
8916
8917 size(4);
8918 format %{ "FCMPd $fcc,$src1,$src2" %}
8919 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8920 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8921 ins_pipe(faddD_fcc_reg_reg_zero);
8922 %}
8923
8924
8925 // Compare floating, generate -1,0,1
8926 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8927 match(Set dst (CmpF3 src1 src2));
8928 effect(KILL fcc0);
8929 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8930 format %{ "fcmpl $dst,$src1,$src2" %}
8931 // Primary = float
8932 opcode( true );
8933 ins_encode( floating_cmp( dst, src1, src2 ) );
8934 ins_pipe( floating_cmp );
8935 %}
8936
8937 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8938 match(Set dst (CmpD3 src1 src2));
8939 effect(KILL fcc0);
8940 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8941 format %{ "dcmpl $dst,$src1,$src2" %}
8942 // Primary = double (not float)
8943 opcode( false );
8944 ins_encode( floating_cmp( dst, src1, src2 ) );
8945 ins_pipe( floating_cmp );
8946 %}
8947
8948 //----------Branches---------------------------------------------------------
8949 // Jump
8950 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8951 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8952 match(Jump switch_val);
8953 effect(TEMP table);
8954
8955 ins_cost(350);
8956
8957 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8958 "LD [O7 + $switch_val], O7\n\t"
8959 "JUMP O7" %}
8960 ins_encode %{
8961 // Calculate table address into a register.
8962 Register table_reg;
8963 Register label_reg = O7;
8964 // If we are calculating the size of this instruction don't trust
8965 // zero offsets because they might change when
8966 // MachConstantBaseNode decides to optimize the constant table
8967 // base.
8968 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8969 table_reg = $constanttablebase;
8970 } else {
8971 table_reg = O7;
8972 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8973 __ add($constanttablebase, con_offset, table_reg);
8974 }
8975
8976 // Jump to base address + switch value
8977 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8978 __ jmp(label_reg, G0);
8979 __ delayed()->nop();
8980 %}
8981 ins_pipe(ialu_reg_reg);
8982 %}
8983
8984 // Direct Branch. Use V8 version with longer range.
8985 instruct branch(label labl) %{
8986 match(Goto);
8987 effect(USE labl);
8988
8989 size(8);
8990 ins_cost(BRANCH_COST);
8991 format %{ "BA $labl" %}
8992 ins_encode %{
8993 Label* L = $labl$$label;
8994 __ ba(*L);
8995 __ delayed()->nop();
8996 %}
8997 ins_avoid_back_to_back(AVOID_BEFORE);
8998 ins_pipe(br);
8999 %}
9000
9001 // Direct Branch, short with no delay slot
9002 instruct branch_short(label labl) %{
9003 match(Goto);
9004 predicate(UseCBCond);
9005 effect(USE labl);
9006
9007 size(4);
9008 ins_cost(BRANCH_COST);
9009 format %{ "BA $labl\t! short branch" %}
9010 ins_encode %{
9011 Label* L = $labl$$label;
9012 assert(__ use_cbcond(*L), "back to back cbcond");
9013 __ ba_short(*L);
9014 %}
9015 ins_short_branch(1);
9016 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9017 ins_pipe(cbcond_reg_imm);
9018 %}
9019
9020 // Conditional Direct Branch
9021 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9022 match(If cmp icc);
9023 effect(USE labl);
9024
9025 size(8);
9026 ins_cost(BRANCH_COST);
9027 format %{ "BP$cmp $icc,$labl" %}
9028 // Prim = bits 24-22, Secnd = bits 31-30
9029 ins_encode( enc_bp( labl, cmp, icc ) );
9030 ins_avoid_back_to_back(AVOID_BEFORE);
9031 ins_pipe(br_cc);
9032 %}
9033
9034 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9035 match(If cmp icc);
9036 effect(USE labl);
9037
9038 ins_cost(BRANCH_COST);
9039 format %{ "BP$cmp $icc,$labl" %}
9040 // Prim = bits 24-22, Secnd = bits 31-30
9041 ins_encode( enc_bp( labl, cmp, icc ) );
9042 ins_avoid_back_to_back(AVOID_BEFORE);
9043 ins_pipe(br_cc);
9044 %}
9045
9046 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9047 match(If cmp pcc);
9048 effect(USE labl);
9049
9050 size(8);
9051 ins_cost(BRANCH_COST);
9052 format %{ "BP$cmp $pcc,$labl" %}
9053 ins_encode %{
9054 Label* L = $labl$$label;
9055 Assembler::Predict predict_taken =
9056 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9057
9058 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9059 __ delayed()->nop();
9060 %}
9061 ins_avoid_back_to_back(AVOID_BEFORE);
9062 ins_pipe(br_cc);
9063 %}
9064
9065 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9066 match(If cmp fcc);
9067 effect(USE labl);
9068
9069 size(8);
9070 ins_cost(BRANCH_COST);
9071 format %{ "FBP$cmp $fcc,$labl" %}
9072 ins_encode %{
9073 Label* L = $labl$$label;
9074 Assembler::Predict predict_taken =
9075 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9076
9077 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9078 __ delayed()->nop();
9079 %}
9080 ins_avoid_back_to_back(AVOID_BEFORE);
9081 ins_pipe(br_fcc);
9082 %}
9083
9084 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9085 match(CountedLoopEnd cmp icc);
9086 effect(USE labl);
9087
9088 size(8);
9089 ins_cost(BRANCH_COST);
9090 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9091 // Prim = bits 24-22, Secnd = bits 31-30
9092 ins_encode( enc_bp( labl, cmp, icc ) );
9093 ins_avoid_back_to_back(AVOID_BEFORE);
9094 ins_pipe(br_cc);
9095 %}
9096
9097 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9098 match(CountedLoopEnd cmp icc);
9099 effect(USE labl);
9100
9101 size(8);
9102 ins_cost(BRANCH_COST);
9103 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9104 // Prim = bits 24-22, Secnd = bits 31-30
9105 ins_encode( enc_bp( labl, cmp, icc ) );
9106 ins_avoid_back_to_back(AVOID_BEFORE);
9107 ins_pipe(br_cc);
9108 %}
9109
9110 // Compare and branch instructions
9111 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9112 match(If cmp (CmpI op1 op2));
9113 effect(USE labl, KILL icc);
9114
9115 size(12);
9116 ins_cost(BRANCH_COST);
9117 format %{ "CMP $op1,$op2\t! int\n\t"
9118 "BP$cmp $labl" %}
9119 ins_encode %{
9120 Label* L = $labl$$label;
9121 Assembler::Predict predict_taken =
9122 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9123 __ cmp($op1$$Register, $op2$$Register);
9124 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9125 __ delayed()->nop();
9126 %}
9127 ins_pipe(cmp_br_reg_reg);
9128 %}
9129
9130 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9131 match(If cmp (CmpI op1 op2));
9132 effect(USE labl, KILL icc);
9133
9134 size(12);
9135 ins_cost(BRANCH_COST);
9136 format %{ "CMP $op1,$op2\t! int\n\t"
9137 "BP$cmp $labl" %}
9138 ins_encode %{
9139 Label* L = $labl$$label;
9140 Assembler::Predict predict_taken =
9141 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9142 __ cmp($op1$$Register, $op2$$constant);
9143 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9144 __ delayed()->nop();
9145 %}
9146 ins_pipe(cmp_br_reg_imm);
9147 %}
9148
9149 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9150 match(If cmp (CmpU op1 op2));
9151 effect(USE labl, KILL icc);
9152
9153 size(12);
9154 ins_cost(BRANCH_COST);
9155 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9156 "BP$cmp $labl" %}
9157 ins_encode %{
9158 Label* L = $labl$$label;
9159 Assembler::Predict predict_taken =
9160 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9161 __ cmp($op1$$Register, $op2$$Register);
9162 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9163 __ delayed()->nop();
9164 %}
9165 ins_pipe(cmp_br_reg_reg);
9166 %}
9167
9168 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9169 match(If cmp (CmpU op1 op2));
9170 effect(USE labl, KILL icc);
9171
9172 size(12);
9173 ins_cost(BRANCH_COST);
9174 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9175 "BP$cmp $labl" %}
9176 ins_encode %{
9177 Label* L = $labl$$label;
9178 Assembler::Predict predict_taken =
9179 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9180 __ cmp($op1$$Register, $op2$$constant);
9181 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9182 __ delayed()->nop();
9183 %}
9184 ins_pipe(cmp_br_reg_imm);
9185 %}
9186
9187 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9188 match(If cmp (CmpL op1 op2));
9189 effect(USE labl, KILL xcc);
9190
9191 size(12);
9192 ins_cost(BRANCH_COST);
9193 format %{ "CMP $op1,$op2\t! long\n\t"
9194 "BP$cmp $labl" %}
9195 ins_encode %{
9196 Label* L = $labl$$label;
9197 Assembler::Predict predict_taken =
9198 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9199 __ cmp($op1$$Register, $op2$$Register);
9200 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9201 __ delayed()->nop();
9202 %}
9203 ins_pipe(cmp_br_reg_reg);
9204 %}
9205
9206 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9207 match(If cmp (CmpL op1 op2));
9208 effect(USE labl, KILL xcc);
9209
9210 size(12);
9211 ins_cost(BRANCH_COST);
9212 format %{ "CMP $op1,$op2\t! long\n\t"
9213 "BP$cmp $labl" %}
9214 ins_encode %{
9215 Label* L = $labl$$label;
9216 Assembler::Predict predict_taken =
9217 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9218 __ cmp($op1$$Register, $op2$$constant);
9219 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9220 __ delayed()->nop();
9221 %}
9222 ins_pipe(cmp_br_reg_imm);
9223 %}
9224
9225 // Compare Pointers and branch
9226 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9227 match(If cmp (CmpP op1 op2));
9228 effect(USE labl, KILL pcc);
9229
9230 size(12);
9231 ins_cost(BRANCH_COST);
9232 format %{ "CMP $op1,$op2\t! ptr\n\t"
9233 "B$cmp $labl" %}
9234 ins_encode %{
9235 Label* L = $labl$$label;
9236 Assembler::Predict predict_taken =
9237 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9238 __ cmp($op1$$Register, $op2$$Register);
9239 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9240 __ delayed()->nop();
9241 %}
9242 ins_pipe(cmp_br_reg_reg);
9243 %}
9244
9245 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9246 match(If cmp (CmpP op1 null));
9247 effect(USE labl, KILL pcc);
9248
9249 size(12);
9250 ins_cost(BRANCH_COST);
9251 format %{ "CMP $op1,0\t! ptr\n\t"
9252 "B$cmp $labl" %}
9253 ins_encode %{
9254 Label* L = $labl$$label;
9255 Assembler::Predict predict_taken =
9256 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9257 __ cmp($op1$$Register, G0);
9258 // bpr() is not used here since it has shorter distance.
9259 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9260 __ delayed()->nop();
9261 %}
9262 ins_pipe(cmp_br_reg_reg);
9263 %}
9264
9265 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9266 match(If cmp (CmpN op1 op2));
9267 effect(USE labl, KILL icc);
9268
9269 size(12);
9270 ins_cost(BRANCH_COST);
9271 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9272 "BP$cmp $labl" %}
9273 ins_encode %{
9274 Label* L = $labl$$label;
9275 Assembler::Predict predict_taken =
9276 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9277 __ cmp($op1$$Register, $op2$$Register);
9278 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9279 __ delayed()->nop();
9280 %}
9281 ins_pipe(cmp_br_reg_reg);
9282 %}
9283
9284 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9285 match(If cmp (CmpN op1 null));
9286 effect(USE labl, KILL icc);
9287
9288 size(12);
9289 ins_cost(BRANCH_COST);
9290 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9291 "BP$cmp $labl" %}
9292 ins_encode %{
9293 Label* L = $labl$$label;
9294 Assembler::Predict predict_taken =
9295 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9296 __ cmp($op1$$Register, G0);
9297 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9298 __ delayed()->nop();
9299 %}
9300 ins_pipe(cmp_br_reg_reg);
9301 %}
9302
9303 // Loop back branch
9304 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9305 match(CountedLoopEnd cmp (CmpI op1 op2));
9306 effect(USE labl, KILL icc);
9307
9308 size(12);
9309 ins_cost(BRANCH_COST);
9310 format %{ "CMP $op1,$op2\t! int\n\t"
9311 "BP$cmp $labl\t! Loop end" %}
9312 ins_encode %{
9313 Label* L = $labl$$label;
9314 Assembler::Predict predict_taken =
9315 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9316 __ cmp($op1$$Register, $op2$$Register);
9317 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9318 __ delayed()->nop();
9319 %}
9320 ins_pipe(cmp_br_reg_reg);
9321 %}
9322
9323 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9324 match(CountedLoopEnd cmp (CmpI op1 op2));
9325 effect(USE labl, KILL icc);
9326
9327 size(12);
9328 ins_cost(BRANCH_COST);
9329 format %{ "CMP $op1,$op2\t! int\n\t"
9330 "BP$cmp $labl\t! Loop end" %}
9331 ins_encode %{
9332 Label* L = $labl$$label;
9333 Assembler::Predict predict_taken =
9334 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9335 __ cmp($op1$$Register, $op2$$constant);
9336 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9337 __ delayed()->nop();
9338 %}
9339 ins_pipe(cmp_br_reg_imm);
9340 %}
9341
9342 // Short compare and branch instructions
9343 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9344 match(If cmp (CmpI op1 op2));
9345 predicate(UseCBCond);
9346 effect(USE labl, KILL icc);
9347
9348 size(4);
9349 ins_cost(BRANCH_COST);
9350 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9351 ins_encode %{
9352 Label* L = $labl$$label;
9353 assert(__ use_cbcond(*L), "back to back cbcond");
9354 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9355 %}
9356 ins_short_branch(1);
9357 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9358 ins_pipe(cbcond_reg_reg);
9359 %}
9360
9361 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9362 match(If cmp (CmpI op1 op2));
9363 predicate(UseCBCond);
9364 effect(USE labl, KILL icc);
9365
9366 size(4);
9367 ins_cost(BRANCH_COST);
9368 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9369 ins_encode %{
9370 Label* L = $labl$$label;
9371 assert(__ use_cbcond(*L), "back to back cbcond");
9372 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9373 %}
9374 ins_short_branch(1);
9375 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9376 ins_pipe(cbcond_reg_imm);
9377 %}
9378
9379 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9380 match(If cmp (CmpU op1 op2));
9381 predicate(UseCBCond);
9382 effect(USE labl, KILL icc);
9383
9384 size(4);
9385 ins_cost(BRANCH_COST);
9386 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9387 ins_encode %{
9388 Label* L = $labl$$label;
9389 assert(__ use_cbcond(*L), "back to back cbcond");
9390 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9391 %}
9392 ins_short_branch(1);
9393 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9394 ins_pipe(cbcond_reg_reg);
9395 %}
9396
9397 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9398 match(If cmp (CmpU op1 op2));
9399 predicate(UseCBCond);
9400 effect(USE labl, KILL icc);
9401
9402 size(4);
9403 ins_cost(BRANCH_COST);
9404 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9405 ins_encode %{
9406 Label* L = $labl$$label;
9407 assert(__ use_cbcond(*L), "back to back cbcond");
9408 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9409 %}
9410 ins_short_branch(1);
9411 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9412 ins_pipe(cbcond_reg_imm);
9413 %}
9414
9415 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9416 match(If cmp (CmpL op1 op2));
9417 predicate(UseCBCond);
9418 effect(USE labl, KILL xcc);
9419
9420 size(4);
9421 ins_cost(BRANCH_COST);
9422 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9423 ins_encode %{
9424 Label* L = $labl$$label;
9425 assert(__ use_cbcond(*L), "back to back cbcond");
9426 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9427 %}
9428 ins_short_branch(1);
9429 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9430 ins_pipe(cbcond_reg_reg);
9431 %}
9432
9433 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9434 match(If cmp (CmpL op1 op2));
9435 predicate(UseCBCond);
9436 effect(USE labl, KILL xcc);
9437
9438 size(4);
9439 ins_cost(BRANCH_COST);
9440 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9441 ins_encode %{
9442 Label* L = $labl$$label;
9443 assert(__ use_cbcond(*L), "back to back cbcond");
9444 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9445 %}
9446 ins_short_branch(1);
9447 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9448 ins_pipe(cbcond_reg_imm);
9449 %}
9450
9451 // Compare Pointers and branch
9452 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9453 match(If cmp (CmpP op1 op2));
9454 predicate(UseCBCond);
9455 effect(USE labl, KILL pcc);
9456
9457 size(4);
9458 ins_cost(BRANCH_COST);
9459 #ifdef _LP64
9460 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9461 #else
9462 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9463 #endif
9464 ins_encode %{
9465 Label* L = $labl$$label;
9466 assert(__ use_cbcond(*L), "back to back cbcond");
9467 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9468 %}
9469 ins_short_branch(1);
9470 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9471 ins_pipe(cbcond_reg_reg);
9472 %}
9473
9474 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9475 match(If cmp (CmpP op1 null));
9476 predicate(UseCBCond);
9477 effect(USE labl, KILL pcc);
9478
9479 size(4);
9480 ins_cost(BRANCH_COST);
9481 #ifdef _LP64
9482 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9483 #else
9484 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9485 #endif
9486 ins_encode %{
9487 Label* L = $labl$$label;
9488 assert(__ use_cbcond(*L), "back to back cbcond");
9489 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9490 %}
9491 ins_short_branch(1);
9492 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9493 ins_pipe(cbcond_reg_reg);
9494 %}
9495
9496 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9497 match(If cmp (CmpN op1 op2));
9498 predicate(UseCBCond);
9499 effect(USE labl, KILL icc);
9500
9501 size(4);
9502 ins_cost(BRANCH_COST);
9503 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9504 ins_encode %{
9505 Label* L = $labl$$label;
9506 assert(__ use_cbcond(*L), "back to back cbcond");
9507 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9508 %}
9509 ins_short_branch(1);
9510 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9511 ins_pipe(cbcond_reg_reg);
9512 %}
9513
9514 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9515 match(If cmp (CmpN op1 null));
9516 predicate(UseCBCond);
9517 effect(USE labl, KILL icc);
9518
9519 size(4);
9520 ins_cost(BRANCH_COST);
9521 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9522 ins_encode %{
9523 Label* L = $labl$$label;
9524 assert(__ use_cbcond(*L), "back to back cbcond");
9525 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9526 %}
9527 ins_short_branch(1);
9528 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9529 ins_pipe(cbcond_reg_reg);
9530 %}
9531
9532 // Loop back branch
9533 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9534 match(CountedLoopEnd cmp (CmpI op1 op2));
9535 predicate(UseCBCond);
9536 effect(USE labl, KILL icc);
9537
9538 size(4);
9539 ins_cost(BRANCH_COST);
9540 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9541 ins_encode %{
9542 Label* L = $labl$$label;
9543 assert(__ use_cbcond(*L), "back to back cbcond");
9544 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9545 %}
9546 ins_short_branch(1);
9547 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9548 ins_pipe(cbcond_reg_reg);
9549 %}
9550
9551 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9552 match(CountedLoopEnd cmp (CmpI op1 op2));
9553 predicate(UseCBCond);
9554 effect(USE labl, KILL icc);
9555
9556 size(4);
9557 ins_cost(BRANCH_COST);
9558 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9559 ins_encode %{
9560 Label* L = $labl$$label;
9561 assert(__ use_cbcond(*L), "back to back cbcond");
9562 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9563 %}
9564 ins_short_branch(1);
9565 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9566 ins_pipe(cbcond_reg_imm);
9567 %}
9568
9569 // Branch-on-register tests all 64 bits. We assume that values
9570 // in 64-bit registers always remains zero or sign extended
9571 // unless our code munges the high bits. Interrupts can chop
9572 // the high order bits to zero or sign at any time.
9573 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9574 match(If cmp (CmpI op1 zero));
9575 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9576 effect(USE labl);
9577
9578 size(8);
9579 ins_cost(BRANCH_COST);
9580 format %{ "BR$cmp $op1,$labl" %}
9581 ins_encode( enc_bpr( labl, cmp, op1 ) );
9582 ins_avoid_back_to_back(AVOID_BEFORE);
9583 ins_pipe(br_reg);
9584 %}
9585
9586 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9587 match(If cmp (CmpP op1 null));
9588 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9589 effect(USE labl);
9590
9591 size(8);
9592 ins_cost(BRANCH_COST);
9593 format %{ "BR$cmp $op1,$labl" %}
9594 ins_encode( enc_bpr( labl, cmp, op1 ) );
9595 ins_avoid_back_to_back(AVOID_BEFORE);
9596 ins_pipe(br_reg);
9597 %}
9598
9599 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9600 match(If cmp (CmpL op1 zero));
9601 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9602 effect(USE labl);
9603
9604 size(8);
9605 ins_cost(BRANCH_COST);
9606 format %{ "BR$cmp $op1,$labl" %}
9607 ins_encode( enc_bpr( labl, cmp, op1 ) );
9608 ins_avoid_back_to_back(AVOID_BEFORE);
9609 ins_pipe(br_reg);
9610 %}
9611
9612
9613 // ============================================================================
9614 // Long Compare
9615 //
9616 // Currently we hold longs in 2 registers. Comparing such values efficiently
9617 // is tricky. The flavor of compare used depends on whether we are testing
9618 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9619 // The GE test is the negated LT test. The LE test can be had by commuting
9620 // the operands (yielding a GE test) and then negating; negate again for the
9621 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9622 // NE test is negated from that.
9623
9624 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9625 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9626 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9627 // are collapsed internally in the ADLC's dfa-gen code. The match for
9628 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9629 // foo match ends up with the wrong leaf. One fix is to not match both
9630 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9631 // both forms beat the trinary form of long-compare and both are very useful
9632 // on Intel which has so few registers.
9633
9634 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9635 match(If cmp xcc);
9636 effect(USE labl);
9637
9638 size(8);
9639 ins_cost(BRANCH_COST);
9640 format %{ "BP$cmp $xcc,$labl" %}
9641 ins_encode %{
9642 Label* L = $labl$$label;
9643 Assembler::Predict predict_taken =
9644 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9645
9646 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9647 __ delayed()->nop();
9648 %}
9649 ins_avoid_back_to_back(AVOID_BEFORE);
9650 ins_pipe(br_cc);
9651 %}
9652
9653 // Manifest a CmpL3 result in an integer register. Very painful.
9654 // This is the test to avoid.
9655 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9656 match(Set dst (CmpL3 src1 src2) );
9657 effect( KILL ccr );
9658 ins_cost(6*DEFAULT_COST);
9659 size(24);
9660 format %{ "CMP $src1,$src2\t\t! long\n"
9661 "\tBLT,a,pn done\n"
9662 "\tMOV -1,$dst\t! delay slot\n"
9663 "\tBGT,a,pn done\n"
9664 "\tMOV 1,$dst\t! delay slot\n"
9665 "\tCLR $dst\n"
9666 "done:" %}
9667 ins_encode( cmpl_flag(src1,src2,dst) );
9668 ins_pipe(cmpL_reg);
9669 %}
9670
9671 // Conditional move
9672 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9673 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9674 ins_cost(150);
9675 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9676 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9677 ins_pipe(ialu_reg);
9678 %}
9679
9680 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9681 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9682 ins_cost(140);
9683 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9684 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9685 ins_pipe(ialu_imm);
9686 %}
9687
9688 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9689 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9690 ins_cost(150);
9691 format %{ "MOV$cmp $xcc,$src,$dst" %}
9692 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9693 ins_pipe(ialu_reg);
9694 %}
9695
9696 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9697 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9698 ins_cost(140);
9699 format %{ "MOV$cmp $xcc,$src,$dst" %}
9700 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9701 ins_pipe(ialu_imm);
9702 %}
9703
9704 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9705 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9706 ins_cost(150);
9707 format %{ "MOV$cmp $xcc,$src,$dst" %}
9708 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9709 ins_pipe(ialu_reg);
9710 %}
9711
9712 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9713 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9714 ins_cost(150);
9715 format %{ "MOV$cmp $xcc,$src,$dst" %}
9716 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9717 ins_pipe(ialu_reg);
9718 %}
9719
9720 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9721 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9722 ins_cost(140);
9723 format %{ "MOV$cmp $xcc,$src,$dst" %}
9724 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9725 ins_pipe(ialu_imm);
9726 %}
9727
9728 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9729 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9730 ins_cost(150);
9731 opcode(0x101);
9732 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9733 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9734 ins_pipe(int_conditional_float_move);
9735 %}
9736
9737 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9738 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9739 ins_cost(150);
9740 opcode(0x102);
9741 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9742 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9743 ins_pipe(int_conditional_float_move);
9744 %}
9745
9746 // ============================================================================
9747 // Safepoint Instruction
9748 instruct safePoint_poll(iRegP poll) %{
9749 match(SafePoint poll);
9750 effect(USE poll);
9751
9752 size(4);
9753 #ifdef _LP64
9754 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9755 #else
9756 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9757 #endif
9758 ins_encode %{
9759 __ relocate(relocInfo::poll_type);
9760 __ ld_ptr($poll$$Register, 0, G0);
9761 %}
9762 ins_pipe(loadPollP);
9763 %}
9764
9765 // ============================================================================
9766 // Call Instructions
9767 // Call Java Static Instruction
9768 instruct CallStaticJavaDirect( method meth ) %{
9769 match(CallStaticJava);
9770 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9771 effect(USE meth);
9772
9773 size(8);
9774 ins_cost(CALL_COST);
9775 format %{ "CALL,static ; NOP ==> " %}
9776 ins_encode( Java_Static_Call( meth ), call_epilog );
9777 ins_avoid_back_to_back(AVOID_BEFORE);
9778 ins_pipe(simple_call);
9779 %}
9780
9781 // Call Java Static Instruction (method handle version)
9782 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9783 match(CallStaticJava);
9784 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9785 effect(USE meth, KILL l7_mh_SP_save);
9786
9787 size(16);
9788 ins_cost(CALL_COST);
9789 format %{ "CALL,static/MethodHandle" %}
9790 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9791 ins_pipe(simple_call);
9792 %}
9793
9794 // Call Java Dynamic Instruction
9795 instruct CallDynamicJavaDirect( method meth ) %{
9796 match(CallDynamicJava);
9797 effect(USE meth);
9798
9799 ins_cost(CALL_COST);
9800 format %{ "SET (empty),R_G5\n\t"
9801 "CALL,dynamic ; NOP ==> " %}
9802 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9803 ins_pipe(call);
9804 %}
9805
9806 // Call Runtime Instruction
9807 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9808 match(CallRuntime);
9809 effect(USE meth, KILL l7);
9810 ins_cost(CALL_COST);
9811 format %{ "CALL,runtime" %}
9812 ins_encode( Java_To_Runtime( meth ),
9813 call_epilog, adjust_long_from_native_call );
9814 ins_avoid_back_to_back(AVOID_BEFORE);
9815 ins_pipe(simple_call);
9816 %}
9817
9818 // Call runtime without safepoint - same as CallRuntime
9819 instruct CallLeafDirect(method meth, l7RegP l7) %{
9820 match(CallLeaf);
9821 effect(USE meth, KILL l7);
9822 ins_cost(CALL_COST);
9823 format %{ "CALL,runtime leaf" %}
9824 ins_encode( Java_To_Runtime( meth ),
9825 call_epilog,
9826 adjust_long_from_native_call );
9827 ins_avoid_back_to_back(AVOID_BEFORE);
9828 ins_pipe(simple_call);
9829 %}
9830
9831 // Call runtime without safepoint - same as CallLeaf
9832 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9833 match(CallLeafNoFP);
9834 effect(USE meth, KILL l7);
9835 ins_cost(CALL_COST);
9836 format %{ "CALL,runtime leaf nofp" %}
9837 ins_encode( Java_To_Runtime( meth ),
9838 call_epilog,
9839 adjust_long_from_native_call );
9840 ins_avoid_back_to_back(AVOID_BEFORE);
9841 ins_pipe(simple_call);
9842 %}
9843
9844 // Tail Call; Jump from runtime stub to Java code.
9845 // Also known as an 'interprocedural jump'.
9846 // Target of jump will eventually return to caller.
9847 // TailJump below removes the return address.
9848 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9849 match(TailCall jump_target method_oop );
9850
9851 ins_cost(CALL_COST);
9852 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9853 ins_encode(form_jmpl(jump_target));
9854 ins_avoid_back_to_back(AVOID_BEFORE);
9855 ins_pipe(tail_call);
9856 %}
9857
9858
9859 // Return Instruction
9860 instruct Ret() %{
9861 match(Return);
9862
9863 // The epilogue node did the ret already.
9864 size(0);
9865 format %{ "! return" %}
9866 ins_encode();
9867 ins_pipe(empty);
9868 %}
9869
9870
9871 // Tail Jump; remove the return address; jump to target.
9872 // TailCall above leaves the return address around.
9873 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9874 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9875 // "restore" before this instruction (in Epilogue), we need to materialize it
9876 // in %i0.
9877 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9878 match( TailJump jump_target ex_oop );
9879 ins_cost(CALL_COST);
9880 format %{ "! discard R_O7\n\t"
9881 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9882 ins_encode(form_jmpl_set_exception_pc(jump_target));
9883 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9884 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9885 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9886 ins_avoid_back_to_back(AVOID_BEFORE);
9887 ins_pipe(tail_call);
9888 %}
9889
9890 // Create exception oop: created by stack-crawling runtime code.
9891 // Created exception is now available to this handler, and is setup
9892 // just prior to jumping to this handler. No code emitted.
9893 instruct CreateException( o0RegP ex_oop )
9894 %{
9895 match(Set ex_oop (CreateEx));
9896 ins_cost(0);
9897
9898 size(0);
9899 // use the following format syntax
9900 format %{ "! exception oop is in R_O0; no code emitted" %}
9901 ins_encode();
9902 ins_pipe(empty);
9903 %}
9904
9905
9906 // Rethrow exception:
9907 // The exception oop will come in the first argument position.
9908 // Then JUMP (not call) to the rethrow stub code.
9909 instruct RethrowException()
9910 %{
9911 match(Rethrow);
9912 ins_cost(CALL_COST);
9913
9914 // use the following format syntax
9915 format %{ "Jmp rethrow_stub" %}
9916 ins_encode(enc_rethrow);
9917 ins_avoid_back_to_back(AVOID_BEFORE);
9918 ins_pipe(tail_call);
9919 %}
9920
9921
9922 // Die now
9923 instruct ShouldNotReachHere( )
9924 %{
9925 match(Halt);
9926 ins_cost(CALL_COST);
9927
9928 size(4);
9929 // Use the following format syntax
9930 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9931 ins_encode( form2_illtrap() );
9932 ins_pipe(tail_call);
9933 %}
9934
9935 // ============================================================================
9936 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9937 // array for an instance of the superklass. Set a hidden internal cache on a
9938 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9939 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9940 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9941 match(Set index (PartialSubtypeCheck sub super));
9942 effect( KILL pcc, KILL o7 );
9943 ins_cost(DEFAULT_COST*10);
9944 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9945 ins_encode( enc_PartialSubtypeCheck() );
9946 ins_avoid_back_to_back(AVOID_BEFORE);
9947 ins_pipe(partial_subtype_check_pipe);
9948 %}
9949
9950 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9951 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9952 effect( KILL idx, KILL o7 );
9953 ins_cost(DEFAULT_COST*10);
9954 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9955 ins_encode( enc_PartialSubtypeCheck() );
9956 ins_avoid_back_to_back(AVOID_BEFORE);
9957 ins_pipe(partial_subtype_check_pipe);
9958 %}
9959
9960
9961 // ============================================================================
9962 // inlined locking and unlocking
9963
9964 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9965 match(Set pcc (FastLock object box));
9966
9967 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9968 ins_cost(100);
9969
9970 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9971 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9972 ins_pipe(long_memory_op);
9973 %}
9974
9975
9976 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9977 match(Set pcc (FastUnlock object box));
9978 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9979 ins_cost(100);
9980
9981 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9982 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9983 ins_pipe(long_memory_op);
9984 %}
9985
9986 // The encodings are generic.
9987 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9988 predicate(!use_block_zeroing(n->in(2)) );
9989 match(Set dummy (ClearArray cnt base));
9990 effect(TEMP temp, KILL ccr);
9991 ins_cost(300);
9992 format %{ "MOV $cnt,$temp\n"
9993 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9994 " BRge loop\t\t! Clearing loop\n"
9995 " STX G0,[$base+$temp]\t! delay slot" %}
9996
9997 ins_encode %{
9998 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9999 Register nof_bytes_arg = $cnt$$Register;
10000 Register nof_bytes_tmp = $temp$$Register;
10001 Register base_pointer_arg = $base$$Register;
10002
10003 Label loop;
10004 __ mov(nof_bytes_arg, nof_bytes_tmp);
10005
10006 // Loop and clear, walking backwards through the array.
10007 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10008 __ bind(loop);
10009 __ deccc(nof_bytes_tmp, 8);
10010 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10011 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10012 // %%%% this mini-loop must not cross a cache boundary!
10013 %}
10014 ins_pipe(long_memory_op);
10015 %}
10016
10017 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10018 predicate(use_block_zeroing(n->in(2)));
10019 match(Set dummy (ClearArray cnt base));
10020 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10021 ins_cost(300);
10022 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10023
10024 ins_encode %{
10025
10026 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10027 Register to = $base$$Register;
10028 Register count = $cnt$$Register;
10029
10030 Label Ldone;
10031 __ nop(); // Separate short branches
10032 // Use BIS for zeroing (temp is not used).
10033 __ bis_zeroing(to, count, G0, Ldone);
10034 __ bind(Ldone);
10035
10036 %}
10037 ins_pipe(long_memory_op);
10038 %}
10039
10040 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10041 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10042 match(Set dummy (ClearArray cnt base));
10043 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10044 ins_cost(300);
10045 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10046
10047 ins_encode %{
10048
10049 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10050 Register to = $base$$Register;
10051 Register count = $cnt$$Register;
10052 Register temp = $tmp$$Register;
10053
10054 Label Ldone;
10055 __ nop(); // Separate short branches
10056 // Use BIS for zeroing
10057 __ bis_zeroing(to, count, temp, Ldone);
10058 __ bind(Ldone);
10059
10060 %}
10061 ins_pipe(long_memory_op);
10062 %}
10063
10064 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10065 o7RegI tmp, flagsReg ccr) %{
10066 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10067 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10068 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10069 ins_cost(300);
10070 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10071 ins_encode %{
10072 __ string_compare($str1$$Register, $str2$$Register,
10073 $cnt1$$Register, $cnt2$$Register,
10074 $tmp$$Register, $tmp$$Register,
10075 $result$$Register, StrIntrinsicNode::LL);
10076 %}
10077 ins_pipe(long_memory_op);
10078 %}
10079
10080 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10081 o7RegI tmp, flagsReg ccr) %{
10082 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10083 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10084 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10085 ins_cost(300);
10086 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10087 ins_encode %{
10088 __ string_compare($str1$$Register, $str2$$Register,
10089 $cnt1$$Register, $cnt2$$Register,
10090 $tmp$$Register, $tmp$$Register,
10091 $result$$Register, StrIntrinsicNode::UU);
10092 %}
10093 ins_pipe(long_memory_op);
10094 %}
10095
10096 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10097 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10098 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10099 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10100 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10101 ins_cost(300);
10102 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10103 ins_encode %{
10104 __ string_compare($str1$$Register, $str2$$Register,
10105 $cnt1$$Register, $cnt2$$Register,
10106 $tmp1$$Register, $tmp2$$Register,
10107 $result$$Register, StrIntrinsicNode::LU);
10108 %}
10109 ins_pipe(long_memory_op);
10110 %}
10111
10112 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10113 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10114 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10115 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10116 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10117 ins_cost(300);
10118 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10119 ins_encode %{
10120 __ string_compare($str2$$Register, $str1$$Register,
10121 $cnt2$$Register, $cnt1$$Register,
10122 $tmp1$$Register, $tmp2$$Register,
10123 $result$$Register, StrIntrinsicNode::UL);
10124 %}
10125 ins_pipe(long_memory_op);
10126 %}
10127
10128 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10129 o7RegI tmp, flagsReg ccr) %{
10130 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10131 match(Set result (StrEquals (Binary str1 str2) cnt));
10132 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10133 ins_cost(300);
10134 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10135 ins_encode %{
10136 __ array_equals(false, $str1$$Register, $str2$$Register,
10137 $cnt$$Register, $tmp$$Register,
10138 $result$$Register, true /* byte */);
10139 %}
10140 ins_pipe(long_memory_op);
10141 %}
10142
10143 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10144 o7RegI tmp, flagsReg ccr) %{
10145 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10146 match(Set result (StrEquals (Binary str1 str2) cnt));
10147 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10148 ins_cost(300);
10149 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10150 ins_encode %{
10151 __ array_equals(false, $str1$$Register, $str2$$Register,
10152 $cnt$$Register, $tmp$$Register,
10153 $result$$Register, false /* byte */);
10154 %}
10155 ins_pipe(long_memory_op);
10156 %}
10157
10158 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10159 o7RegI tmp2, flagsReg ccr) %{
10160 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10161 match(Set result (AryEq ary1 ary2));
10162 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10163 ins_cost(300);
10164 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10165 ins_encode %{
10166 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10167 $tmp1$$Register, $tmp2$$Register,
10168 $result$$Register, true /* byte */);
10169 %}
10170 ins_pipe(long_memory_op);
10171 %}
10172
10173 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10174 o7RegI tmp2, flagsReg ccr) %{
10175 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10176 match(Set result (AryEq ary1 ary2));
10177 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10178 ins_cost(300);
10179 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10180 ins_encode %{
10181 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10182 $tmp1$$Register, $tmp2$$Register,
10183 $result$$Register, false /* byte */);
10184 %}
10185 ins_pipe(long_memory_op);
10186 %}
10187
10188 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
10189 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
10190 flagsReg ccr)
10191 %{
10192 match(Set resultR (HasNegatives pAryR iSizeR));
10193 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
10194 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
10195 ins_encode %{
10196 __ has_negatives($pAryR$$Register, $iSizeR$$Register,
10197 $resultR$$Register,
10198 $tmp1L$$Register, $tmp2L$$Register,
10199 $tmp3L$$Register, $tmp4L$$Register);
10200 %}
10201 ins_pipe(long_memory_op);
10202 %}
10203
10204 // char[] to byte[] compression
10205 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10206 predicate(UseVIS < 3);
10207 match(Set result (StrCompressedCopy src (Binary dst len)));
10208 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10209 ins_cost(300);
10210 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10211 ins_encode %{
10212 Label Ldone;
10213 __ signx($len$$Register);
10214 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10215 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10216 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10217 __ bind(Ldone);
10218 %}
10219 ins_pipe(long_memory_op);
10220 %}
10221
10222 // fast char[] to byte[] compression using VIS instructions
10223 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10224 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10225 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10226 predicate(UseVIS >= 3);
10227 match(Set result (StrCompressedCopy src (Binary dst len)));
10228 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10229 ins_cost(300);
10230 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10231 ins_encode %{
10232 Label Ldone;
10233 __ signx($len$$Register);
10234 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10235 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10236 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10237 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10238 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10239 __ bind(Ldone);
10240 %}
10241 ins_pipe(long_memory_op);
10242 %}
10243
10244 // byte[] to char[] inflation
10245 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10246 iRegL tmp, flagsReg ccr) %{
10247 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10248 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10249 ins_cost(300);
10250 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10251 ins_encode %{
10252 Label Ldone;
10253 __ signx($len$$Register);
10254 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10255 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10256 __ bind(Ldone);
10257 %}
10258 ins_pipe(long_memory_op);
10259 %}
10260
10261 // fast byte[] to char[] inflation using VIS instructions
10262 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10263 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10264 predicate(UseVIS >= 3);
10265 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10266 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10267 ins_cost(300);
10268 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10269 ins_encode %{
10270 Label Ldone;
10271 __ signx($len$$Register);
10272 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10273 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10274 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10275 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10276 __ bind(Ldone);
10277 %}
10278 ins_pipe(long_memory_op);
10279 %}
10280
10281
10282 //---------- Zeros Count Instructions ------------------------------------------
10283
10284 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10285 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10286 match(Set dst (CountLeadingZerosI src));
10287 effect(TEMP dst, TEMP tmp, KILL cr);
10288
10289 // x |= (x >> 1);
10290 // x |= (x >> 2);
10291 // x |= (x >> 4);
10292 // x |= (x >> 8);
10293 // x |= (x >> 16);
10294 // return (WORDBITS - popc(x));
10295 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10296 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10297 "OR $dst,$tmp,$dst\n\t"
10298 "SRL $dst,2,$tmp\n\t"
10299 "OR $dst,$tmp,$dst\n\t"
10300 "SRL $dst,4,$tmp\n\t"
10301 "OR $dst,$tmp,$dst\n\t"
10302 "SRL $dst,8,$tmp\n\t"
10303 "OR $dst,$tmp,$dst\n\t"
10304 "SRL $dst,16,$tmp\n\t"
10305 "OR $dst,$tmp,$dst\n\t"
10306 "POPC $dst,$dst\n\t"
10307 "MOV 32,$tmp\n\t"
10308 "SUB $tmp,$dst,$dst" %}
10309 ins_encode %{
10310 Register Rdst = $dst$$Register;
10311 Register Rsrc = $src$$Register;
10312 Register Rtmp = $tmp$$Register;
10313 __ srl(Rsrc, 1, Rtmp);
10314 __ srl(Rsrc, 0, Rdst);
10315 __ or3(Rdst, Rtmp, Rdst);
10316 __ srl(Rdst, 2, Rtmp);
10317 __ or3(Rdst, Rtmp, Rdst);
10318 __ srl(Rdst, 4, Rtmp);
10319 __ or3(Rdst, Rtmp, Rdst);
10320 __ srl(Rdst, 8, Rtmp);
10321 __ or3(Rdst, Rtmp, Rdst);
10322 __ srl(Rdst, 16, Rtmp);
10323 __ or3(Rdst, Rtmp, Rdst);
10324 __ popc(Rdst, Rdst);
10325 __ mov(BitsPerInt, Rtmp);
10326 __ sub(Rtmp, Rdst, Rdst);
10327 %}
10328 ins_pipe(ialu_reg);
10329 %}
10330
10331 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10332 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10333 match(Set dst (CountLeadingZerosL src));
10334 effect(TEMP dst, TEMP tmp, KILL cr);
10335
10336 // x |= (x >> 1);
10337 // x |= (x >> 2);
10338 // x |= (x >> 4);
10339 // x |= (x >> 8);
10340 // x |= (x >> 16);
10341 // x |= (x >> 32);
10342 // return (WORDBITS - popc(x));
10343 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10344 "OR $src,$tmp,$dst\n\t"
10345 "SRLX $dst,2,$tmp\n\t"
10346 "OR $dst,$tmp,$dst\n\t"
10347 "SRLX $dst,4,$tmp\n\t"
10348 "OR $dst,$tmp,$dst\n\t"
10349 "SRLX $dst,8,$tmp\n\t"
10350 "OR $dst,$tmp,$dst\n\t"
10351 "SRLX $dst,16,$tmp\n\t"
10352 "OR $dst,$tmp,$dst\n\t"
10353 "SRLX $dst,32,$tmp\n\t"
10354 "OR $dst,$tmp,$dst\n\t"
10355 "POPC $dst,$dst\n\t"
10356 "MOV 64,$tmp\n\t"
10357 "SUB $tmp,$dst,$dst" %}
10358 ins_encode %{
10359 Register Rdst = $dst$$Register;
10360 Register Rsrc = $src$$Register;
10361 Register Rtmp = $tmp$$Register;
10362 __ srlx(Rsrc, 1, Rtmp);
10363 __ or3( Rsrc, Rtmp, Rdst);
10364 __ srlx(Rdst, 2, Rtmp);
10365 __ or3( Rdst, Rtmp, Rdst);
10366 __ srlx(Rdst, 4, Rtmp);
10367 __ or3( Rdst, Rtmp, Rdst);
10368 __ srlx(Rdst, 8, Rtmp);
10369 __ or3( Rdst, Rtmp, Rdst);
10370 __ srlx(Rdst, 16, Rtmp);
10371 __ or3( Rdst, Rtmp, Rdst);
10372 __ srlx(Rdst, 32, Rtmp);
10373 __ or3( Rdst, Rtmp, Rdst);
10374 __ popc(Rdst, Rdst);
10375 __ mov(BitsPerLong, Rtmp);
10376 __ sub(Rtmp, Rdst, Rdst);
10377 %}
10378 ins_pipe(ialu_reg);
10379 %}
10380
10381 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10382 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10383 match(Set dst (CountTrailingZerosI src));
10384 effect(TEMP dst, KILL cr);
10385
10386 // return popc(~x & (x - 1));
10387 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10388 "ANDN $dst,$src,$dst\n\t"
10389 "SRL $dst,R_G0,$dst\n\t"
10390 "POPC $dst,$dst" %}
10391 ins_encode %{
10392 Register Rdst = $dst$$Register;
10393 Register Rsrc = $src$$Register;
10394 __ sub(Rsrc, 1, Rdst);
10395 __ andn(Rdst, Rsrc, Rdst);
10396 __ srl(Rdst, G0, Rdst);
10397 __ popc(Rdst, Rdst);
10398 %}
10399 ins_pipe(ialu_reg);
10400 %}
10401
10402 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10403 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10404 match(Set dst (CountTrailingZerosL src));
10405 effect(TEMP dst, KILL cr);
10406
10407 // return popc(~x & (x - 1));
10408 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10409 "ANDN $dst,$src,$dst\n\t"
10410 "POPC $dst,$dst" %}
10411 ins_encode %{
10412 Register Rdst = $dst$$Register;
10413 Register Rsrc = $src$$Register;
10414 __ sub(Rsrc, 1, Rdst);
10415 __ andn(Rdst, Rsrc, Rdst);
10416 __ popc(Rdst, Rdst);
10417 %}
10418 ins_pipe(ialu_reg);
10419 %}
10420
10421
10422 //---------- Population Count Instructions -------------------------------------
10423
10424 instruct popCountI(iRegIsafe dst, iRegI src) %{
10425 predicate(UsePopCountInstruction);
10426 match(Set dst (PopCountI src));
10427
10428 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10429 "POPC $dst, $dst" %}
10430 ins_encode %{
10431 __ srl($src$$Register, G0, $dst$$Register);
10432 __ popc($dst$$Register, $dst$$Register);
10433 %}
10434 ins_pipe(ialu_reg);
10435 %}
10436
10437 // Note: Long.bitCount(long) returns an int.
10438 instruct popCountL(iRegIsafe dst, iRegL src) %{
10439 predicate(UsePopCountInstruction);
10440 match(Set dst (PopCountL src));
10441
10442 format %{ "POPC $src, $dst" %}
10443 ins_encode %{
10444 __ popc($src$$Register, $dst$$Register);
10445 %}
10446 ins_pipe(ialu_reg);
10447 %}
10448
10449
10450 // ============================================================================
10451 //------------Bytes reverse--------------------------------------------------
10452
10453 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10454 match(Set dst (ReverseBytesI src));
10455
10456 // Op cost is artificially doubled to make sure that load or store
10457 // instructions are preferred over this one which requires a spill
10458 // onto a stack slot.
10459 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10460 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10461
10462 ins_encode %{
10463 __ set($src$$disp + STACK_BIAS, O7);
10464 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10465 %}
10466 ins_pipe( iload_mem );
10467 %}
10468
10469 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10470 match(Set dst (ReverseBytesL src));
10471
10472 // Op cost is artificially doubled to make sure that load or store
10473 // instructions are preferred over this one which requires a spill
10474 // onto a stack slot.
10475 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10476 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10477
10478 ins_encode %{
10479 __ set($src$$disp + STACK_BIAS, O7);
10480 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10481 %}
10482 ins_pipe( iload_mem );
10483 %}
10484
10485 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10486 match(Set dst (ReverseBytesUS src));
10487
10488 // Op cost is artificially doubled to make sure that load or store
10489 // instructions are preferred over this one which requires a spill
10490 // onto a stack slot.
10491 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10492 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10493
10494 ins_encode %{
10495 // the value was spilled as an int so bias the load
10496 __ set($src$$disp + STACK_BIAS + 2, O7);
10497 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10498 %}
10499 ins_pipe( iload_mem );
10500 %}
10501
10502 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10503 match(Set dst (ReverseBytesS src));
10504
10505 // Op cost is artificially doubled to make sure that load or store
10506 // instructions are preferred over this one which requires a spill
10507 // onto a stack slot.
10508 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10509 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10510
10511 ins_encode %{
10512 // the value was spilled as an int so bias the load
10513 __ set($src$$disp + STACK_BIAS + 2, O7);
10514 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10515 %}
10516 ins_pipe( iload_mem );
10517 %}
10518
10519 // Load Integer reversed byte order
10520 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10521 match(Set dst (ReverseBytesI (LoadI src)));
10522
10523 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10524 size(4);
10525 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10526
10527 ins_encode %{
10528 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10529 %}
10530 ins_pipe(iload_mem);
10531 %}
10532
10533 // Load Long - aligned and reversed
10534 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10535 match(Set dst (ReverseBytesL (LoadL src)));
10536
10537 ins_cost(MEMORY_REF_COST);
10538 size(4);
10539 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10540
10541 ins_encode %{
10542 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10543 %}
10544 ins_pipe(iload_mem);
10545 %}
10546
10547 // Load unsigned short / char reversed byte order
10548 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10549 match(Set dst (ReverseBytesUS (LoadUS src)));
10550
10551 ins_cost(MEMORY_REF_COST);
10552 size(4);
10553 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10554
10555 ins_encode %{
10556 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10557 %}
10558 ins_pipe(iload_mem);
10559 %}
10560
10561 // Load short reversed byte order
10562 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10563 match(Set dst (ReverseBytesS (LoadS src)));
10564
10565 ins_cost(MEMORY_REF_COST);
10566 size(4);
10567 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10568
10569 ins_encode %{
10570 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10571 %}
10572 ins_pipe(iload_mem);
10573 %}
10574
10575 // Store Integer reversed byte order
10576 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10577 match(Set dst (StoreI dst (ReverseBytesI src)));
10578
10579 ins_cost(MEMORY_REF_COST);
10580 size(4);
10581 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10582
10583 ins_encode %{
10584 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10585 %}
10586 ins_pipe(istore_mem_reg);
10587 %}
10588
10589 // Store Long reversed byte order
10590 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10591 match(Set dst (StoreL dst (ReverseBytesL src)));
10592
10593 ins_cost(MEMORY_REF_COST);
10594 size(4);
10595 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10596
10597 ins_encode %{
10598 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10599 %}
10600 ins_pipe(istore_mem_reg);
10601 %}
10602
10603 // Store unsighed short/char reversed byte order
10604 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10605 match(Set dst (StoreC dst (ReverseBytesUS src)));
10606
10607 ins_cost(MEMORY_REF_COST);
10608 size(4);
10609 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10610
10611 ins_encode %{
10612 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10613 %}
10614 ins_pipe(istore_mem_reg);
10615 %}
10616
10617 // Store short reversed byte order
10618 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10619 match(Set dst (StoreC dst (ReverseBytesS src)));
10620
10621 ins_cost(MEMORY_REF_COST);
10622 size(4);
10623 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10624
10625 ins_encode %{
10626 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10627 %}
10628 ins_pipe(istore_mem_reg);
10629 %}
10630
10631 // ====================VECTOR INSTRUCTIONS=====================================
10632
10633 // Load Aligned Packed values into a Double Register
10634 instruct loadV8(regD dst, memory mem) %{
10635 predicate(n->as_LoadVector()->memory_size() == 8);
10636 match(Set dst (LoadVector mem));
10637 ins_cost(MEMORY_REF_COST);
10638 size(4);
10639 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10640 ins_encode %{
10641 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10642 %}
10643 ins_pipe(floadD_mem);
10644 %}
10645
10646 // Store Vector in Double register to memory
10647 instruct storeV8(memory mem, regD src) %{
10648 predicate(n->as_StoreVector()->memory_size() == 8);
10649 match(Set mem (StoreVector mem src));
10650 ins_cost(MEMORY_REF_COST);
10651 size(4);
10652 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10653 ins_encode %{
10654 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10655 %}
10656 ins_pipe(fstoreD_mem_reg);
10657 %}
10658
10659 // Store Zero into vector in memory
10660 instruct storeV8B_zero(memory mem, immI0 zero) %{
10661 predicate(n->as_StoreVector()->memory_size() == 8);
10662 match(Set mem (StoreVector mem (ReplicateB zero)));
10663 ins_cost(MEMORY_REF_COST);
10664 size(4);
10665 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10666 ins_encode %{
10667 __ stx(G0, $mem$$Address);
10668 %}
10669 ins_pipe(fstoreD_mem_zero);
10670 %}
10671
10672 instruct storeV4S_zero(memory mem, immI0 zero) %{
10673 predicate(n->as_StoreVector()->memory_size() == 8);
10674 match(Set mem (StoreVector mem (ReplicateS zero)));
10675 ins_cost(MEMORY_REF_COST);
10676 size(4);
10677 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10678 ins_encode %{
10679 __ stx(G0, $mem$$Address);
10680 %}
10681 ins_pipe(fstoreD_mem_zero);
10682 %}
10683
10684 instruct storeV2I_zero(memory mem, immI0 zero) %{
10685 predicate(n->as_StoreVector()->memory_size() == 8);
10686 match(Set mem (StoreVector mem (ReplicateI zero)));
10687 ins_cost(MEMORY_REF_COST);
10688 size(4);
10689 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10690 ins_encode %{
10691 __ stx(G0, $mem$$Address);
10692 %}
10693 ins_pipe(fstoreD_mem_zero);
10694 %}
10695
10696 instruct storeV2F_zero(memory mem, immF0 zero) %{
10697 predicate(n->as_StoreVector()->memory_size() == 8);
10698 match(Set mem (StoreVector mem (ReplicateF zero)));
10699 ins_cost(MEMORY_REF_COST);
10700 size(4);
10701 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10702 ins_encode %{
10703 __ stx(G0, $mem$$Address);
10704 %}
10705 ins_pipe(fstoreD_mem_zero);
10706 %}
10707
10708 // Replicate scalar to packed byte values into Double register
10709 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10710 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10711 match(Set dst (ReplicateB src));
10712 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10713 format %{ "SLLX $src,56,$tmp\n\t"
10714 "SRLX $tmp, 8,$tmp2\n\t"
10715 "OR $tmp,$tmp2,$tmp\n\t"
10716 "SRLX $tmp,16,$tmp2\n\t"
10717 "OR $tmp,$tmp2,$tmp\n\t"
10718 "SRLX $tmp,32,$tmp2\n\t"
10719 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10720 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10721 ins_encode %{
10722 Register Rsrc = $src$$Register;
10723 Register Rtmp = $tmp$$Register;
10724 Register Rtmp2 = $tmp2$$Register;
10725 __ sllx(Rsrc, 56, Rtmp);
10726 __ srlx(Rtmp, 8, Rtmp2);
10727 __ or3 (Rtmp, Rtmp2, Rtmp);
10728 __ srlx(Rtmp, 16, Rtmp2);
10729 __ or3 (Rtmp, Rtmp2, Rtmp);
10730 __ srlx(Rtmp, 32, Rtmp2);
10731 __ or3 (Rtmp, Rtmp2, Rtmp);
10732 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10733 %}
10734 ins_pipe(ialu_reg);
10735 %}
10736
10737 // Replicate scalar to packed byte values into Double stack
10738 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10739 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10740 match(Set dst (ReplicateB src));
10741 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10742 format %{ "SLLX $src,56,$tmp\n\t"
10743 "SRLX $tmp, 8,$tmp2\n\t"
10744 "OR $tmp,$tmp2,$tmp\n\t"
10745 "SRLX $tmp,16,$tmp2\n\t"
10746 "OR $tmp,$tmp2,$tmp\n\t"
10747 "SRLX $tmp,32,$tmp2\n\t"
10748 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10749 "STX $tmp,$dst\t! regL to stkD" %}
10750 ins_encode %{
10751 Register Rsrc = $src$$Register;
10752 Register Rtmp = $tmp$$Register;
10753 Register Rtmp2 = $tmp2$$Register;
10754 __ sllx(Rsrc, 56, Rtmp);
10755 __ srlx(Rtmp, 8, Rtmp2);
10756 __ or3 (Rtmp, Rtmp2, Rtmp);
10757 __ srlx(Rtmp, 16, Rtmp2);
10758 __ or3 (Rtmp, Rtmp2, Rtmp);
10759 __ srlx(Rtmp, 32, Rtmp2);
10760 __ or3 (Rtmp, Rtmp2, Rtmp);
10761 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10762 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10763 %}
10764 ins_pipe(ialu_reg);
10765 %}
10766
10767 // Replicate scalar constant to packed byte values in Double register
10768 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10769 predicate(n->as_Vector()->length() == 8);
10770 match(Set dst (ReplicateB con));
10771 effect(KILL tmp);
10772 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10773 ins_encode %{
10774 // XXX This is a quick fix for 6833573.
10775 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10776 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10777 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10778 %}
10779 ins_pipe(loadConFD);
10780 %}
10781
10782 // Replicate scalar to packed char/short values into Double register
10783 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10784 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10785 match(Set dst (ReplicateS src));
10786 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10787 format %{ "SLLX $src,48,$tmp\n\t"
10788 "SRLX $tmp,16,$tmp2\n\t"
10789 "OR $tmp,$tmp2,$tmp\n\t"
10790 "SRLX $tmp,32,$tmp2\n\t"
10791 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10792 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10793 ins_encode %{
10794 Register Rsrc = $src$$Register;
10795 Register Rtmp = $tmp$$Register;
10796 Register Rtmp2 = $tmp2$$Register;
10797 __ sllx(Rsrc, 48, Rtmp);
10798 __ srlx(Rtmp, 16, Rtmp2);
10799 __ or3 (Rtmp, Rtmp2, Rtmp);
10800 __ srlx(Rtmp, 32, Rtmp2);
10801 __ or3 (Rtmp, Rtmp2, Rtmp);
10802 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10803 %}
10804 ins_pipe(ialu_reg);
10805 %}
10806
10807 // Replicate scalar to packed char/short values into Double stack
10808 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10809 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10810 match(Set dst (ReplicateS src));
10811 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10812 format %{ "SLLX $src,48,$tmp\n\t"
10813 "SRLX $tmp,16,$tmp2\n\t"
10814 "OR $tmp,$tmp2,$tmp\n\t"
10815 "SRLX $tmp,32,$tmp2\n\t"
10816 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10817 "STX $tmp,$dst\t! regL to stkD" %}
10818 ins_encode %{
10819 Register Rsrc = $src$$Register;
10820 Register Rtmp = $tmp$$Register;
10821 Register Rtmp2 = $tmp2$$Register;
10822 __ sllx(Rsrc, 48, Rtmp);
10823 __ srlx(Rtmp, 16, Rtmp2);
10824 __ or3 (Rtmp, Rtmp2, Rtmp);
10825 __ srlx(Rtmp, 32, Rtmp2);
10826 __ or3 (Rtmp, Rtmp2, Rtmp);
10827 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10828 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10829 %}
10830 ins_pipe(ialu_reg);
10831 %}
10832
10833 // Replicate scalar constant to packed char/short values in Double register
10834 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10835 predicate(n->as_Vector()->length() == 4);
10836 match(Set dst (ReplicateS con));
10837 effect(KILL tmp);
10838 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10839 ins_encode %{
10840 // XXX This is a quick fix for 6833573.
10841 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10842 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10843 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10844 %}
10845 ins_pipe(loadConFD);
10846 %}
10847
10848 // Replicate scalar to packed int values into Double register
10849 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10850 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10851 match(Set dst (ReplicateI src));
10852 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10853 format %{ "SLLX $src,32,$tmp\n\t"
10854 "SRLX $tmp,32,$tmp2\n\t"
10855 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10856 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10857 ins_encode %{
10858 Register Rsrc = $src$$Register;
10859 Register Rtmp = $tmp$$Register;
10860 Register Rtmp2 = $tmp2$$Register;
10861 __ sllx(Rsrc, 32, Rtmp);
10862 __ srlx(Rtmp, 32, Rtmp2);
10863 __ or3 (Rtmp, Rtmp2, Rtmp);
10864 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10865 %}
10866 ins_pipe(ialu_reg);
10867 %}
10868
10869 // Replicate scalar to packed int values into Double stack
10870 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10871 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10872 match(Set dst (ReplicateI src));
10873 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10874 format %{ "SLLX $src,32,$tmp\n\t"
10875 "SRLX $tmp,32,$tmp2\n\t"
10876 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10877 "STX $tmp,$dst\t! regL to stkD" %}
10878 ins_encode %{
10879 Register Rsrc = $src$$Register;
10880 Register Rtmp = $tmp$$Register;
10881 Register Rtmp2 = $tmp2$$Register;
10882 __ sllx(Rsrc, 32, Rtmp);
10883 __ srlx(Rtmp, 32, Rtmp2);
10884 __ or3 (Rtmp, Rtmp2, Rtmp);
10885 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10886 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10887 %}
10888 ins_pipe(ialu_reg);
10889 %}
10890
10891 // Replicate scalar zero constant to packed int values in Double register
10892 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10893 predicate(n->as_Vector()->length() == 2);
10894 match(Set dst (ReplicateI con));
10895 effect(KILL tmp);
10896 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10897 ins_encode %{
10898 // XXX This is a quick fix for 6833573.
10899 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10900 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10901 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10902 %}
10903 ins_pipe(loadConFD);
10904 %}
10905
10906 // Replicate scalar to packed float values into Double stack
10907 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10908 predicate(n->as_Vector()->length() == 2);
10909 match(Set dst (ReplicateF src));
10910 ins_cost(MEMORY_REF_COST*2);
10911 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10912 "STF $src,$dst.lo" %}
10913 opcode(Assembler::stf_op3);
10914 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10915 ins_pipe(fstoreF_stk_reg);
10916 %}
10917
10918 // Replicate scalar zero constant to packed float values in Double register
10919 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10920 predicate(n->as_Vector()->length() == 2);
10921 match(Set dst (ReplicateF con));
10922 effect(KILL tmp);
10923 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10924 ins_encode %{
10925 // XXX This is a quick fix for 6833573.
10926 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10927 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10928 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10929 %}
10930 ins_pipe(loadConFD);
10931 %}
10932
10933 //----------PEEPHOLE RULES-----------------------------------------------------
10934 // These must follow all instruction definitions as they use the names
10935 // defined in the instructions definitions.
10936 //
10937 // peepmatch ( root_instr_name [preceding_instruction]* );
10938 //
10939 // peepconstraint %{
10940 // (instruction_number.operand_name relational_op instruction_number.operand_name
10941 // [, ...] );
10942 // // instruction numbers are zero-based using left to right order in peepmatch
10943 //
10944 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10945 // // provide an instruction_number.operand_name for each operand that appears
10946 // // in the replacement instruction's match rule
10947 //
10948 // ---------VM FLAGS---------------------------------------------------------
10949 //
10950 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10951 //
10952 // Each peephole rule is given an identifying number starting with zero and
10953 // increasing by one in the order seen by the parser. An individual peephole
10954 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10955 // on the command-line.
10956 //
10957 // ---------CURRENT LIMITATIONS----------------------------------------------
10958 //
10959 // Only match adjacent instructions in same basic block
10960 // Only equality constraints
10961 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10962 // Only one replacement instruction
10963 //
10964 // ---------EXAMPLE----------------------------------------------------------
10965 //
10966 // // pertinent parts of existing instructions in architecture description
10967 // instruct movI(eRegI dst, eRegI src) %{
10968 // match(Set dst (CopyI src));
10969 // %}
10970 //
10971 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10972 // match(Set dst (AddI dst src));
10973 // effect(KILL cr);
10974 // %}
10975 //
10976 // // Change (inc mov) to lea
10977 // peephole %{
10978 // // increment preceeded by register-register move
10979 // peepmatch ( incI_eReg movI );
10980 // // require that the destination register of the increment
10981 // // match the destination register of the move
10982 // peepconstraint ( 0.dst == 1.dst );
10983 // // construct a replacement instruction that sets
10984 // // the destination to ( move's source register + one )
10985 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10986 // %}
10987 //
10988
10989 // // Change load of spilled value to only a spill
10990 // instruct storeI(memory mem, eRegI src) %{
10991 // match(Set mem (StoreI mem src));
10992 // %}
10993 //
10994 // instruct loadI(eRegI dst, memory mem) %{
10995 // match(Set dst (LoadI mem));
10996 // %}
10997 //
10998 // peephole %{
10999 // peepmatch ( loadI storeI );
11000 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
11001 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
11002 // %}
11003
11004 //----------SMARTSPILL RULES---------------------------------------------------
11005 // These must follow all instruction definitions as they use the names
11006 // defined in the instructions definitions.
11007 //
11008 // SPARC will probably not have any of these rules due to RISC instruction set.
11009
11010 //----------PIPELINE-----------------------------------------------------------
11011 // Rules which define the behavior of the target architectures pipeline.