< prev index next >

src/cpu/sparc/vm/sparc.ad

Print this page




1701 }
1702 
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706   st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709 
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711   MacroAssembler _masm(&cbuf);
1712   for (int i = 0; i < _count; i += 1) {
1713     __ nop();
1714   }
1715 }
1716 
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718   return 4 * _count;
1719 }
1720 













1721 
1722 //=============================================================================
1723 #ifndef PRODUCT
1724 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1725   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1726   int reg = ra_->get_reg_first(this);
1727   st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1728 }
1729 #endif
1730 
1731 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1732   MacroAssembler _masm(&cbuf);
1733   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1734   int reg = ra_->get_encode(this);
1735 
1736   if (Assembler::is_simm13(offset)) {
1737      __ add(SP, offset, reg_to_register_object(reg));
1738   } else {
1739      __ set(offset, O7);
1740      __ add(SP, O7, reg_to_register_object(reg));


1885 #ifdef _LP64
1886   case Op_CompareAndSwapP:
1887 #endif
1888     if (!VM_Version::supports_cx8())
1889       return false;
1890     break;
1891   }
1892 
1893   return true;  // Per default match rules are supported.
1894 }
1895 
1896 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1897 
1898   // TODO
1899   // identify extra cases that we might want to provide match rules for
1900   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1901   bool ret_value = match_rule_supported(opcode);
1902   // Add rules here.
1903 
1904   return ret_value;  // Per default match rules are supported.




1905 }
1906 
1907 const int Matcher::float_pressure(int default_pressure_threshold) {
1908   return default_pressure_threshold;
1909 }
1910 
1911 int Matcher::regnum_to_fpu_offset(int regnum) {
1912   return regnum - 32; // The FP registers are in the second chunk
1913 }
1914 
1915 #ifdef ASSERT
1916 address last_rethrow = NULL;  // debugging aid for Rethrow encoding
1917 #endif
1918 
1919 // Vector width in bytes
1920 const int Matcher::vector_width_in_bytes(BasicType bt) {
1921   assert(MaxVectorSize == 8, "");
1922   return 8;
1923 }
1924 




1701 }
1702 
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706   st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709 
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711   MacroAssembler _masm(&cbuf);
1712   for (int i = 0; i < _count; i += 1) {
1713     __ nop();
1714   }
1715 }
1716 
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718   return 4 * _count;
1719 }
1720 
1721 #ifndef PRODUCT
1722 void MachMskNode::format(PhaseRegAlloc*, outputStream* st) const {
1723   // TBD
1724 }
1725 #endif
1726 
1727 void MachMskNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
1728   // TBD
1729 }
1730 
1731 uint MachMskNode::size(PhaseRegAlloc* ra_) const {
1732   return 0; // TBD
1733 }
1734 
1735 //=============================================================================
1736 #ifndef PRODUCT
1737 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1738   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1739   int reg = ra_->get_reg_first(this);
1740   st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1741 }
1742 #endif
1743 
1744 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1745   MacroAssembler _masm(&cbuf);
1746   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1747   int reg = ra_->get_encode(this);
1748 
1749   if (Assembler::is_simm13(offset)) {
1750      __ add(SP, offset, reg_to_register_object(reg));
1751   } else {
1752      __ set(offset, O7);
1753      __ add(SP, O7, reg_to_register_object(reg));


1898 #ifdef _LP64
1899   case Op_CompareAndSwapP:
1900 #endif
1901     if (!VM_Version::supports_cx8())
1902       return false;
1903     break;
1904   }
1905 
1906   return true;  // Per default match rules are supported.
1907 }
1908 
1909 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1910 
1911   // TODO
1912   // identify extra cases that we might want to provide match rules for
1913   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1914   bool ret_value = match_rule_supported(opcode);
1915   // Add rules here.
1916 
1917   return ret_value;  // Per default match rules are supported.
1918 }
1919 
1920 const bool Matcher::has_predicated_vectors(void) {
1921   return false;
1922 }
1923 
1924 const int Matcher::float_pressure(int default_pressure_threshold) {
1925   return default_pressure_threshold;
1926 }
1927 
1928 int Matcher::regnum_to_fpu_offset(int regnum) {
1929   return regnum - 32; // The FP registers are in the second chunk
1930 }
1931 
1932 #ifdef ASSERT
1933 address last_rethrow = NULL;  // debugging aid for Rethrow encoding
1934 #endif
1935 
1936 // Vector width in bytes
1937 const int Matcher::vector_width_in_bytes(BasicType bt) {
1938   assert(MaxVectorSize == 8, "");
1939   return 8;
1940 }
1941 


< prev index next >