1 /*
   2  * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 // MacroAssembler extends Assembler by frequently used macros.
  33 //
  34 // Instructions for which a 'better' code sequence exists depending
  35 // on arguments should also go in here.
  36 
  37 class MacroAssembler: public Assembler {
  38   friend class LIR_Assembler;
  39   friend class Runtime1;      // as_Address()
  40 
  41  protected:
  42 
  43   Address as_Address(AddressLiteral adr);
  44   Address as_Address(ArrayAddress adr);
  45 
  46   // Support for VM calls
  47   //
  48   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  49   // may customize this version by overriding it for its purposes (e.g., to save/restore
  50   // additional registers when doing a VM call).
  51 
  52   virtual void call_VM_leaf_base(
  53     address entry_point,               // the entry point
  54     int     number_of_arguments        // the number of arguments to pop after the call
  55   );
  56 
  57   // This is the base routine called by the different versions of call_VM. The interpreter
  58   // may customize this version by overriding it for its purposes (e.g., to save/restore
  59   // additional registers when doing a VM call).
  60   //
  61   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  62   // returns the register which contains the thread upon return. If a thread register has been
  63   // specified, the return value will correspond to that register. If no last_java_sp is specified
  64   // (noreg) than rsp will be used instead.
  65   virtual void call_VM_base(           // returns the register containing the thread upon return
  66     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  67     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  68     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  69     address  entry_point,              // the entry point
  70     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  71     bool     check_exceptions          // whether to check for pending exceptions after return
  72   );
  73 
  74   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  75   // The implementation is only non-empty for the InterpreterMacroAssembler,
  76   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  77   virtual void check_and_handle_popframe(Register java_thread);
  78   virtual void check_and_handle_earlyret(Register java_thread);
  79 
  80   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  81 
  82   // helpers for FPU flag access
  83   // tmp is a temporary register, if none is available use noreg
  84   void save_rax   (Register tmp);
  85   void restore_rax(Register tmp);
  86 
  87  public:
  88   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  89 
  90   // Support for NULL-checks
  91   //
  92   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  93   // If the accessed location is M[reg + offset] and the offset is known, provide the
  94   // offset. No explicit code generation is needed if the offset is within a certain
  95   // range (0 <= offset <= page_size).
  96 
  97   void null_check(Register reg, int offset = -1);
  98   static bool needs_explicit_null_check(intptr_t offset);
  99 
 100   // Required platform-specific helpers for Label::patch_instructions.
 101   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 102   void pd_patch_instruction(address branch, address target) {
 103     unsigned char op = branch[0];
 104     assert(op == 0xE8 /* call */ ||
 105         op == 0xE9 /* jmp */ ||
 106         op == 0xEB /* short jmp */ ||
 107         (op & 0xF0) == 0x70 /* short jcc */ ||
 108         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 109         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 110         "Invalid opcode at patch point");
 111 
 112     if (op == 0xEB || (op & 0xF0) == 0x70) {
 113       // short offset operators (jmp and jcc)
 114       char* disp = (char*) &branch[1];
 115       int imm8 = target - (address) &disp[1];
 116       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
 117       *disp = imm8;
 118     } else {
 119       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 120       int imm32 = target - (address) &disp[1];
 121       *disp = imm32;
 122     }
 123   }
 124 
 125   // The following 4 methods return the offset of the appropriate move instruction
 126 
 127   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 128   int load_unsigned_byte(Register dst, Address src);
 129   int load_unsigned_short(Register dst, Address src);
 130 
 131   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 132   int load_signed_byte(Register dst, Address src);
 133   int load_signed_short(Register dst, Address src);
 134 
 135   // Support for sign-extension (hi:lo = extend_sign(lo))
 136   void extend_sign(Register hi, Register lo);
 137 
 138   // Load and store values by size and signed-ness
 139   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 140   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 141 
 142   // Support for inc/dec with optimal instruction selection depending on value
 143 
 144   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 145   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 146 
 147   void decrementl(Address dst, int value = 1);
 148   void decrementl(Register reg, int value = 1);
 149 
 150   void decrementq(Register reg, int value = 1);
 151   void decrementq(Address dst, int value = 1);
 152 
 153   void incrementl(Address dst, int value = 1);
 154   void incrementl(Register reg, int value = 1);
 155 
 156   void incrementq(Register reg, int value = 1);
 157   void incrementq(Address dst, int value = 1);
 158 
 159   // special instructions for EVEX
 160   void createmsk(Register dst, Register src);
 161   void restoremsk();
 162 
 163   // Support optimal SSE move instructions.
 164   void movflt(XMMRegister dst, XMMRegister src) {
 165     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 166     else                       { movss (dst, src); return; }
 167   }
 168   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 169   void movflt(XMMRegister dst, AddressLiteral src);
 170   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 171 
 172   void movdbl(XMMRegister dst, XMMRegister src) {
 173     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 174     else                       { movsd (dst, src); return; }
 175   }
 176 
 177   void movdbl(XMMRegister dst, AddressLiteral src);
 178 
 179   void movdbl(XMMRegister dst, Address src) {
 180     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 181     else                         { movlpd(dst, src); return; }
 182   }
 183   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 184 
 185   void incrementl(AddressLiteral dst);
 186   void incrementl(ArrayAddress dst);
 187 
 188   void incrementq(AddressLiteral dst);
 189 
 190   // Alignment
 191   void align(int modulus);
 192   void align(int modulus, int target);
 193 
 194   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 195   void fat_nop();
 196 
 197   // Stack frame creation/removal
 198   void enter();
 199   void leave();
 200 
 201   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 202   // The pointer will be loaded into the thread register.
 203   void get_thread(Register thread);
 204 
 205 
 206   // Support for VM calls
 207   //
 208   // It is imperative that all calls into the VM are handled via the call_VM macros.
 209   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 210   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 211 
 212 
 213   void call_VM(Register oop_result,
 214                address entry_point,
 215                bool check_exceptions = true);
 216   void call_VM(Register oop_result,
 217                address entry_point,
 218                Register arg_1,
 219                bool check_exceptions = true);
 220   void call_VM(Register oop_result,
 221                address entry_point,
 222                Register arg_1, Register arg_2,
 223                bool check_exceptions = true);
 224   void call_VM(Register oop_result,
 225                address entry_point,
 226                Register arg_1, Register arg_2, Register arg_3,
 227                bool check_exceptions = true);
 228 
 229   // Overloadings with last_Java_sp
 230   void call_VM(Register oop_result,
 231                Register last_java_sp,
 232                address entry_point,
 233                int number_of_arguments = 0,
 234                bool check_exceptions = true);
 235   void call_VM(Register oop_result,
 236                Register last_java_sp,
 237                address entry_point,
 238                Register arg_1, bool
 239                check_exceptions = true);
 240   void call_VM(Register oop_result,
 241                Register last_java_sp,
 242                address entry_point,
 243                Register arg_1, Register arg_2,
 244                bool check_exceptions = true);
 245   void call_VM(Register oop_result,
 246                Register last_java_sp,
 247                address entry_point,
 248                Register arg_1, Register arg_2, Register arg_3,
 249                bool check_exceptions = true);
 250 
 251   void get_vm_result  (Register oop_result, Register thread);
 252   void get_vm_result_2(Register metadata_result, Register thread);
 253 
 254   // These always tightly bind to MacroAssembler::call_VM_base
 255   // bypassing the virtual implementation
 256   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 257   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 258   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 259   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 260   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 261 
 262   void call_VM_leaf(address entry_point,
 263                     int number_of_arguments = 0);
 264   void call_VM_leaf(address entry_point,
 265                     Register arg_1);
 266   void call_VM_leaf(address entry_point,
 267                     Register arg_1, Register arg_2);
 268   void call_VM_leaf(address entry_point,
 269                     Register arg_1, Register arg_2, Register arg_3);
 270 
 271   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 272   // bypassing the virtual implementation
 273   void super_call_VM_leaf(address entry_point);
 274   void super_call_VM_leaf(address entry_point, Register arg_1);
 275   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 276   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 277   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 278 
 279   // last Java Frame (fills frame anchor)
 280   void set_last_Java_frame(Register thread,
 281                            Register last_java_sp,
 282                            Register last_java_fp,
 283                            address last_java_pc);
 284 
 285   // thread in the default location (r15_thread on 64bit)
 286   void set_last_Java_frame(Register last_java_sp,
 287                            Register last_java_fp,
 288                            address last_java_pc);
 289 
 290   void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
 291 
 292   // thread in the default location (r15_thread on 64bit)
 293   void reset_last_Java_frame(bool clear_fp, bool clear_pc);
 294 
 295   // Stores
 296   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 297   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 298 
 299 #if INCLUDE_ALL_GCS
 300 
 301   void g1_write_barrier_pre(Register obj,
 302                             Register pre_val,
 303                             Register thread,
 304                             Register tmp,
 305                             bool tosca_live,
 306                             bool expand_call);
 307 
 308   void g1_write_barrier_post(Register store_addr,
 309                              Register new_val,
 310                              Register thread,
 311                              Register tmp,
 312                              Register tmp2);
 313 
 314 #endif // INCLUDE_ALL_GCS
 315 
 316   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 317   void c2bool(Register x);
 318 
 319   // C++ bool manipulation
 320 
 321   void movbool(Register dst, Address src);
 322   void movbool(Address dst, bool boolconst);
 323   void movbool(Address dst, Register src);
 324   void testbool(Register dst);
 325 
 326   // oop manipulations
 327   void load_klass(Register dst, Register src);
 328   void store_klass(Register dst, Register src);
 329 
 330   void load_heap_oop(Register dst, Address src);
 331   void load_heap_oop_not_null(Register dst, Address src);
 332   void store_heap_oop(Address dst, Register src);
 333   void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
 334 
 335   // Used for storing NULL. All other oop constants should be
 336   // stored using routines that take a jobject.
 337   void store_heap_oop_null(Address dst);
 338 
 339   void load_prototype_header(Register dst, Register src);
 340 
 341 #ifdef _LP64
 342   void store_klass_gap(Register dst, Register src);
 343 
 344   // This dummy is to prevent a call to store_heap_oop from
 345   // converting a zero (like NULL) into a Register by giving
 346   // the compiler two choices it can't resolve
 347 
 348   void store_heap_oop(Address dst, void* dummy);
 349 
 350   void encode_heap_oop(Register r);
 351   void decode_heap_oop(Register r);
 352   void encode_heap_oop_not_null(Register r);
 353   void decode_heap_oop_not_null(Register r);
 354   void encode_heap_oop_not_null(Register dst, Register src);
 355   void decode_heap_oop_not_null(Register dst, Register src);
 356 
 357   void set_narrow_oop(Register dst, jobject obj);
 358   void set_narrow_oop(Address dst, jobject obj);
 359   void cmp_narrow_oop(Register dst, jobject obj);
 360   void cmp_narrow_oop(Address dst, jobject obj);
 361 
 362   void encode_klass_not_null(Register r);
 363   void decode_klass_not_null(Register r);
 364   void encode_klass_not_null(Register dst, Register src);
 365   void decode_klass_not_null(Register dst, Register src);
 366   void set_narrow_klass(Register dst, Klass* k);
 367   void set_narrow_klass(Address dst, Klass* k);
 368   void cmp_narrow_klass(Register dst, Klass* k);
 369   void cmp_narrow_klass(Address dst, Klass* k);
 370 
 371   // Returns the byte size of the instructions generated by decode_klass_not_null()
 372   // when compressed klass pointers are being used.
 373   static int instr_size_for_decode_klass_not_null();
 374 
 375   // if heap base register is used - reinit it with the correct value
 376   void reinit_heapbase();
 377 
 378   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 379 
 380 #endif // _LP64
 381 
 382   // Int division/remainder for Java
 383   // (as idivl, but checks for special case as described in JVM spec.)
 384   // returns idivl instruction offset for implicit exception handling
 385   int corrected_idivl(Register reg);
 386 
 387   // Long division/remainder for Java
 388   // (as idivq, but checks for special case as described in JVM spec.)
 389   // returns idivq instruction offset for implicit exception handling
 390   int corrected_idivq(Register reg);
 391 
 392   void int3();
 393 
 394   // Long operation macros for a 32bit cpu
 395   // Long negation for Java
 396   void lneg(Register hi, Register lo);
 397 
 398   // Long multiplication for Java
 399   // (destroys contents of eax, ebx, ecx and edx)
 400   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 401 
 402   // Long shifts for Java
 403   // (semantics as described in JVM spec.)
 404   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 405   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 406 
 407   // Long compare for Java
 408   // (semantics as described in JVM spec.)
 409   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 410 
 411 
 412   // misc
 413 
 414   // Sign extension
 415   void sign_extend_short(Register reg);
 416   void sign_extend_byte(Register reg);
 417 
 418   // Division by power of 2, rounding towards 0
 419   void division_with_shift(Register reg, int shift_value);
 420 
 421   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 422   //
 423   // CF (corresponds to C0) if x < y
 424   // PF (corresponds to C2) if unordered
 425   // ZF (corresponds to C3) if x = y
 426   //
 427   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 428   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 429   void fcmp(Register tmp);
 430   // Variant of the above which allows y to be further down the stack
 431   // and which only pops x and y if specified. If pop_right is
 432   // specified then pop_left must also be specified.
 433   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 434 
 435   // Floating-point comparison for Java
 436   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 437   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 438   // (semantics as described in JVM spec.)
 439   void fcmp2int(Register dst, bool unordered_is_less);
 440   // Variant of the above which allows y to be further down the stack
 441   // and which only pops x and y if specified. If pop_right is
 442   // specified then pop_left must also be specified.
 443   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 444 
 445   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 446   // tmp is a temporary register, if none is available use noreg
 447   void fremr(Register tmp);
 448 
 449 
 450   // same as fcmp2int, but using SSE2
 451   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 452   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 453 
 454   // Inlined sin/cos generator for Java; must not use CPU instruction
 455   // directly on Intel as it does not have high enough precision
 456   // outside of the range [-pi/4, pi/4]. Extra argument indicate the
 457   // number of FPU stack slots in use; all but the topmost will
 458   // require saving if a slow case is necessary. Assumes argument is
 459   // on FP TOS; result is on FP TOS.  No cpu registers are changed by
 460   // this code.
 461   void trigfunc(char trig, int num_fpu_regs_in_use = 1);
 462 
 463   // branch to L if FPU flag C2 is set/not set
 464   // tmp is a temporary register, if none is available use noreg
 465   void jC2 (Register tmp, Label& L);
 466   void jnC2(Register tmp, Label& L);
 467 
 468   // Pop ST (ffree & fincstp combined)
 469   void fpop();
 470 
 471   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 472   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 473   void load_float(Address src);
 474 
 475   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 476   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 477   void store_float(Address dst);
 478 
 479   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 480   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 481   void load_double(Address src);
 482 
 483   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 484   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 485   void store_double(Address dst);
 486 
 487   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 488   void push_fTOS();
 489 
 490   // pops double TOS element from CPU stack and pushes on FPU stack
 491   void pop_fTOS();
 492 
 493   void empty_FPU_stack();
 494 
 495   void push_IU_state();
 496   void pop_IU_state();
 497 
 498   void push_FPU_state();
 499   void pop_FPU_state();
 500 
 501   void push_CPU_state();
 502   void pop_CPU_state();
 503 
 504   // Round up to a power of two
 505   void round_to(Register reg, int modulus);
 506 
 507   // Callee saved registers handling
 508   void push_callee_saved_registers();
 509   void pop_callee_saved_registers();
 510 
 511   // allocation
 512   void eden_allocate(
 513     Register obj,                      // result: pointer to object after successful allocation
 514     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 515     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 516     Register t1,                       // temp register
 517     Label&   slow_case                 // continuation point if fast allocation fails
 518   );
 519   void tlab_allocate(
 520     Register obj,                      // result: pointer to object after successful allocation
 521     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 522     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 523     Register t1,                       // temp register
 524     Register t2,                       // temp register
 525     Label&   slow_case                 // continuation point if fast allocation fails
 526   );
 527   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
 528   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 529 
 530   void incr_allocated_bytes(Register thread,
 531                             Register var_size_in_bytes, int con_size_in_bytes,
 532                             Register t1 = noreg);
 533 
 534   // interface method calling
 535   void lookup_interface_method(Register recv_klass,
 536                                Register intf_klass,
 537                                RegisterOrConstant itable_index,
 538                                Register method_result,
 539                                Register scan_temp,
 540                                Label& no_such_interface);
 541 
 542   // virtual method calling
 543   void lookup_virtual_method(Register recv_klass,
 544                              RegisterOrConstant vtable_index,
 545                              Register method_result);
 546 
 547   // Test sub_klass against super_klass, with fast and slow paths.
 548 
 549   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 550   // One of the three labels can be NULL, meaning take the fall-through.
 551   // If super_check_offset is -1, the value is loaded up from super_klass.
 552   // No registers are killed, except temp_reg.
 553   void check_klass_subtype_fast_path(Register sub_klass,
 554                                      Register super_klass,
 555                                      Register temp_reg,
 556                                      Label* L_success,
 557                                      Label* L_failure,
 558                                      Label* L_slow_path,
 559                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 560 
 561   // The rest of the type check; must be wired to a corresponding fast path.
 562   // It does not repeat the fast path logic, so don't use it standalone.
 563   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 564   // Updates the sub's secondary super cache as necessary.
 565   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 566   void check_klass_subtype_slow_path(Register sub_klass,
 567                                      Register super_klass,
 568                                      Register temp_reg,
 569                                      Register temp2_reg,
 570                                      Label* L_success,
 571                                      Label* L_failure,
 572                                      bool set_cond_codes = false);
 573 
 574   // Simplified, combined version, good for typical uses.
 575   // Falls through on failure.
 576   void check_klass_subtype(Register sub_klass,
 577                            Register super_klass,
 578                            Register temp_reg,
 579                            Label& L_success);
 580 
 581   // method handles (JSR 292)
 582   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 583 
 584   //----
 585   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 586 
 587   // Debugging
 588 
 589   // only if +VerifyOops
 590   // TODO: Make these macros with file and line like sparc version!
 591   void verify_oop(Register reg, const char* s = "broken oop");
 592   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 593 
 594   // TODO: verify method and klass metadata (compare against vptr?)
 595   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 596   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 597 
 598 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 599 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 600 
 601   // only if +VerifyFPU
 602   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 603 
 604   // Verify or restore cpu control state after JNI call
 605   void restore_cpu_control_state_after_jni();
 606 
 607   // prints msg, dumps registers and stops execution
 608   void stop(const char* msg);
 609 
 610   // prints msg and continues
 611   void warn(const char* msg);
 612 
 613   // dumps registers and other state
 614   void print_state();
 615 
 616   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 617   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 618   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 619   static void print_state64(int64_t pc, int64_t regs[]);
 620 
 621   void os_breakpoint();
 622 
 623   void untested()                                { stop("untested"); }
 624 
 625   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
 626 
 627   void should_not_reach_here()                   { stop("should not reach here"); }
 628 
 629   void print_CPU_state();
 630 
 631   // Stack overflow checking
 632   void bang_stack_with_offset(int offset) {
 633     // stack grows down, caller passes positive offset
 634     assert(offset > 0, "must bang with negative offset");
 635     movl(Address(rsp, (-offset)), rax);
 636   }
 637 
 638   // Writes to stack successive pages until offset reached to check for
 639   // stack overflow + shadow pages.  Also, clobbers tmp
 640   void bang_stack_size(Register size, Register tmp);
 641 
 642   // Check for reserved stack access in method being exited (for JIT)
 643   void reserved_stack_check();
 644 
 645   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 646                                                 Register tmp,
 647                                                 int offset);
 648 
 649   // Support for serializing memory accesses between threads
 650   void serialize_memory(Register thread, Register tmp);
 651 
 652   void verify_tlab();
 653 
 654   // Biased locking support
 655   // lock_reg and obj_reg must be loaded up with the appropriate values.
 656   // swap_reg must be rax, and is killed.
 657   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 658   // be killed; if not supplied, push/pop will be used internally to
 659   // allocate a temporary (inefficient, avoid if possible).
 660   // Optional slow case is for implementations (interpreter and C1) which branch to
 661   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 662   // Returns offset of first potentially-faulting instruction for null
 663   // check info (currently consumed only by C1). If
 664   // swap_reg_contains_mark is true then returns -1 as it is assumed
 665   // the calling code has already passed any potential faults.
 666   int biased_locking_enter(Register lock_reg, Register obj_reg,
 667                            Register swap_reg, Register tmp_reg,
 668                            bool swap_reg_contains_mark,
 669                            Label& done, Label* slow_case = NULL,
 670                            BiasedLockingCounters* counters = NULL);
 671   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 672 #ifdef COMPILER2
 673   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 674   // See full desription in macroAssembler_x86.cpp.
 675   void fast_lock(Register obj, Register box, Register tmp,
 676                  Register scr, Register cx1, Register cx2,
 677                  BiasedLockingCounters* counters,
 678                  RTMLockingCounters* rtm_counters,
 679                  RTMLockingCounters* stack_rtm_counters,
 680                  Metadata* method_data,
 681                  bool use_rtm, bool profile_rtm);
 682   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 683 #if INCLUDE_RTM_OPT
 684   void rtm_counters_update(Register abort_status, Register rtm_counters);
 685   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 686   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 687                                    RTMLockingCounters* rtm_counters,
 688                                    Metadata* method_data);
 689   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 690                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 691   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 692   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 693   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 694                          Register retry_on_abort_count,
 695                          RTMLockingCounters* stack_rtm_counters,
 696                          Metadata* method_data, bool profile_rtm,
 697                          Label& DONE_LABEL, Label& IsInflated);
 698   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 699                             Register scr, Register retry_on_busy_count,
 700                             Register retry_on_abort_count,
 701                             RTMLockingCounters* rtm_counters,
 702                             Metadata* method_data, bool profile_rtm,
 703                             Label& DONE_LABEL);
 704 #endif
 705 #endif
 706 
 707   Condition negate_condition(Condition cond);
 708 
 709   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 710   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 711   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 712   // here in MacroAssembler. The major exception to this rule is call
 713 
 714   // Arithmetics
 715 
 716 
 717   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 718   void addptr(Address dst, Register src);
 719 
 720   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 721   void addptr(Register dst, int32_t src);
 722   void addptr(Register dst, Register src);
 723   void addptr(Register dst, RegisterOrConstant src) {
 724     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 725     else                   addptr(dst,       src.as_register());
 726   }
 727 
 728   void andptr(Register dst, int32_t src);
 729   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 730 
 731   void cmp8(AddressLiteral src1, int imm);
 732 
 733   // renamed to drag out the casting of address to int32_t/intptr_t
 734   void cmp32(Register src1, int32_t imm);
 735 
 736   void cmp32(AddressLiteral src1, int32_t imm);
 737   // compare reg - mem, or reg - &mem
 738   void cmp32(Register src1, AddressLiteral src2);
 739 
 740   void cmp32(Register src1, Address src2);
 741 
 742 #ifndef _LP64
 743   void cmpklass(Address dst, Metadata* obj);
 744   void cmpklass(Register dst, Metadata* obj);
 745   void cmpoop(Address dst, jobject obj);
 746   void cmpoop(Register dst, jobject obj);
 747 #endif // _LP64
 748 
 749   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 750   void cmpptr(Address src1, AddressLiteral src2);
 751 
 752   void cmpptr(Register src1, AddressLiteral src2);
 753 
 754   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 755   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 756   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 757 
 758   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 759   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 760 
 761   // cmp64 to avoild hiding cmpq
 762   void cmp64(Register src1, AddressLiteral src);
 763 
 764   void cmpxchgptr(Register reg, Address adr);
 765 
 766   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 767 
 768 
 769   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 770   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 771 
 772 
 773   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 774 
 775   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 776 
 777   void shlptr(Register dst, int32_t shift);
 778   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 779 
 780   void shrptr(Register dst, int32_t shift);
 781   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 782 
 783   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 784   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 785 
 786   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 787 
 788   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 789   void subptr(Register dst, int32_t src);
 790   // Force generation of a 4 byte immediate value even if it fits into 8bit
 791   void subptr_imm32(Register dst, int32_t src);
 792   void subptr(Register dst, Register src);
 793   void subptr(Register dst, RegisterOrConstant src) {
 794     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 795     else                   subptr(dst,       src.as_register());
 796   }
 797 
 798   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 799   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 800 
 801   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 802   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 803 
 804   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 805 
 806 
 807 
 808   // Helper functions for statistics gathering.
 809   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 810   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 811   // Unconditional atomic increment.
 812   void atomic_incl(Address counter_addr);
 813   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 814 #ifdef _LP64
 815   void atomic_incq(Address counter_addr);
 816   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 817 #endif
 818   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 819   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 820 
 821   void lea(Register dst, AddressLiteral adr);
 822   void lea(Address dst, AddressLiteral adr);
 823   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 824 
 825   void leal32(Register dst, Address src) { leal(dst, src); }
 826 
 827   // Import other testl() methods from the parent class or else
 828   // they will be hidden by the following overriding declaration.
 829   using Assembler::testl;
 830   void testl(Register dst, AddressLiteral src);
 831 
 832   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 833   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 834   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 835   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 836 
 837   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 838   void testptr(Register src1, Register src2);
 839 
 840   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 841   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 842 
 843   // Calls
 844 
 845   void call(Label& L, relocInfo::relocType rtype);
 846   void call(Register entry);
 847 
 848   // NOTE: this call tranfers to the effective address of entry NOT
 849   // the address contained by entry. This is because this is more natural
 850   // for jumps/calls.
 851   void call(AddressLiteral entry);
 852 
 853   // Emit the CompiledIC call idiom
 854   void ic_call(address entry, jint method_index = 0);
 855 
 856   // Jumps
 857 
 858   // NOTE: these jumps tranfer to the effective address of dst NOT
 859   // the address contained by dst. This is because this is more natural
 860   // for jumps/calls.
 861   void jump(AddressLiteral dst);
 862   void jump_cc(Condition cc, AddressLiteral dst);
 863 
 864   // 32bit can do a case table jump in one instruction but we no longer allow the base
 865   // to be installed in the Address class. This jump will tranfers to the address
 866   // contained in the location described by entry (not the address of entry)
 867   void jump(ArrayAddress entry);
 868 
 869   // Floating
 870 
 871   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 872   void andpd(XMMRegister dst, AddressLiteral src);
 873   void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
 874 
 875   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 876   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 877   void andps(XMMRegister dst, AddressLiteral src);
 878 
 879   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 880   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 881   void comiss(XMMRegister dst, AddressLiteral src);
 882 
 883   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 884   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 885   void comisd(XMMRegister dst, AddressLiteral src);
 886 
 887   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 888   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 889 
 890   void fldcw(Address src) { Assembler::fldcw(src); }
 891   void fldcw(AddressLiteral src);
 892 
 893   void fld_s(int index)   { Assembler::fld_s(index); }
 894   void fld_s(Address src) { Assembler::fld_s(src); }
 895   void fld_s(AddressLiteral src);
 896 
 897   void fld_d(Address src) { Assembler::fld_d(src); }
 898   void fld_d(AddressLiteral src);
 899 
 900   void fld_x(Address src) { Assembler::fld_x(src); }
 901   void fld_x(AddressLiteral src);
 902 
 903   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 904   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 905 
 906   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 907   void ldmxcsr(AddressLiteral src);
 908 
 909   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
 910                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
 911                  Register buf, Register state, Register ofs, Register limit, Register rsp,
 912                  bool multi_block);
 913 
 914 #ifdef _LP64
 915   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 916                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 917                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 918                    bool multi_block, XMMRegister shuf_mask);
 919 #else
 920   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 921                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 922                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 923                    bool multi_block);
 924 #endif
 925 
 926   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 927                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 928                 Register rax, Register rcx, Register rdx, Register tmp);
 929 
 930 #ifdef _LP64
 931   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 932                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 933                 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
 934 
 935   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
 936                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
 937                 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
 938 
 939   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 940                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 941                 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
 942                 Register tmp3, Register tmp4);
 943 
 944   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 945                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 946                 Register rax, Register rcx, Register rdx, Register tmp1,
 947                 Register tmp2, Register tmp3, Register tmp4);
 948 #else
 949   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 950                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 951                 Register rax, Register rcx, Register rdx, Register tmp1);
 952 
 953   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
 954                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
 955                 Register rdx, Register tmp);
 956 
 957   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 958                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 959                 Register rax, Register rbx, Register rdx);
 960 
 961   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
 962                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 963                 Register rax, Register rcx, Register rdx, Register tmp);
 964 
 965   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
 966                         Register edx, Register ebx, Register esi, Register edi,
 967                         Register ebp, Register esp);
 968 
 969   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
 970                          Register esi, Register edi, Register ebp, Register esp);
 971 #endif
 972 
 973   void increase_precision();
 974   void restore_precision();
 975 
 976 private:
 977 
 978   // call runtime as a fallback for trig functions and pow/exp.
 979   void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
 980 
 981   // these are private because users should be doing movflt/movdbl
 982 
 983   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
 984   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
 985   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
 986   void movss(XMMRegister dst, AddressLiteral src);
 987 
 988   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
 989   void movlpd(XMMRegister dst, AddressLiteral src);
 990 
 991 public:
 992 
 993   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
 994   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
 995   void addsd(XMMRegister dst, AddressLiteral src);
 996 
 997   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
 998   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
 999   void addss(XMMRegister dst, AddressLiteral src);
1000 
1001   void addpd(XMMRegister dst, XMMRegister src)    { Assembler::addpd(dst, src); }
1002   void addpd(XMMRegister dst, Address src)        { Assembler::addpd(dst, src); }
1003   void addpd(XMMRegister dst, AddressLiteral src);
1004 
1005   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
1006   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
1007   void divsd(XMMRegister dst, AddressLiteral src);
1008 
1009   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
1010   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
1011   void divss(XMMRegister dst, AddressLiteral src);
1012 
1013   // Move Unaligned Double Quadword
1014   void movdqu(Address     dst, XMMRegister src);
1015   void movdqu(XMMRegister dst, Address src);
1016   void movdqu(XMMRegister dst, XMMRegister src);
1017   void movdqu(XMMRegister dst, AddressLiteral src);
1018   // AVX Unaligned forms
1019   void vmovdqu(Address     dst, XMMRegister src);
1020   void vmovdqu(XMMRegister dst, Address src);
1021   void vmovdqu(XMMRegister dst, XMMRegister src);
1022   void vmovdqu(XMMRegister dst, AddressLiteral src);
1023 
1024   // Move Aligned Double Quadword
1025   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
1026   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
1027   void movdqa(XMMRegister dst, AddressLiteral src);
1028 
1029   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1030   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
1031   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
1032   void movsd(XMMRegister dst, AddressLiteral src);
1033 
1034   void mulpd(XMMRegister dst, XMMRegister src)    { Assembler::mulpd(dst, src); }
1035   void mulpd(XMMRegister dst, Address src)        { Assembler::mulpd(dst, src); }
1036   void mulpd(XMMRegister dst, AddressLiteral src);
1037 
1038   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
1039   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
1040   void mulsd(XMMRegister dst, AddressLiteral src);
1041 
1042   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
1043   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
1044   void mulss(XMMRegister dst, AddressLiteral src);
1045 
1046   // Carry-Less Multiplication Quadword
1047   void pclmulldq(XMMRegister dst, XMMRegister src) {
1048     // 0x00 - multiply lower 64 bits [0:63]
1049     Assembler::pclmulqdq(dst, src, 0x00);
1050   }
1051   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1052     // 0x11 - multiply upper 64 bits [64:127]
1053     Assembler::pclmulqdq(dst, src, 0x11);
1054   }
1055 
1056   void pcmpeqb(XMMRegister dst, XMMRegister src);
1057   void pcmpeqw(XMMRegister dst, XMMRegister src);
1058 
1059   void pcmpestri(XMMRegister dst, Address src, int imm8);
1060   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1061 
1062   void pmovzxbw(XMMRegister dst, XMMRegister src);
1063   void pmovzxbw(XMMRegister dst, Address src);
1064 
1065   void pmovmskb(Register dst, XMMRegister src);
1066 
1067   void ptest(XMMRegister dst, XMMRegister src);
1068 
1069   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
1070   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
1071   void sqrtsd(XMMRegister dst, AddressLiteral src);
1072 
1073   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
1074   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
1075   void sqrtss(XMMRegister dst, AddressLiteral src);
1076 
1077   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
1078   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
1079   void subsd(XMMRegister dst, AddressLiteral src);
1080 
1081   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1082   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1083   void subss(XMMRegister dst, AddressLiteral src);
1084 
1085   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1086   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1087   void ucomiss(XMMRegister dst, AddressLiteral src);
1088 
1089   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1090   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1091   void ucomisd(XMMRegister dst, AddressLiteral src);
1092 
1093   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1094   void xorpd(XMMRegister dst, XMMRegister src);
1095   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1096   void xorpd(XMMRegister dst, AddressLiteral src);
1097 
1098   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1099   void xorps(XMMRegister dst, XMMRegister src);
1100   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1101   void xorps(XMMRegister dst, AddressLiteral src);
1102 
1103   // Shuffle Bytes
1104   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1105   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1106   void pshufb(XMMRegister dst, AddressLiteral src);
1107   // AVX 3-operands instructions
1108 
1109   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1110   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1111   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1112 
1113   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1114   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1115   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1116 
1117   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1118   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1119 
1120   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1121   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1122 
1123   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1124   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1125 
1126   void vpbroadcastw(XMMRegister dst, XMMRegister src);
1127 
1128   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1129   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1130 
1131   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1132   void vpmovmskb(Register dst, XMMRegister src);
1133 
1134   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1135   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1136 
1137   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1138   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1139 
1140   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1141   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1142 
1143   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1144   void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1145 
1146   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1147   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1148 
1149   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1150   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1151 
1152   void vptest(XMMRegister dst, XMMRegister src);
1153 
1154   void punpcklbw(XMMRegister dst, XMMRegister src);
1155   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1156 
1157   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1158   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1159 
1160   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1161   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandpd(dst, nds, src, vector_len); }
1162   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1163 
1164   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1165   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandps(dst, nds, src, vector_len); }
1166   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1167 
1168   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1169   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1170   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1171 
1172   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1173   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1174   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1175 
1176   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1177   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1178   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1179 
1180   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1181   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1182   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1183 
1184   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1185   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1186   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1187 
1188   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1189   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1190   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1191 
1192   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1193   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1194 
1195   // AVX Vector instructions
1196 
1197   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1198   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1199   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1200 
1201   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1202   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1203   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len);
1204 
1205   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1206     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1207       Assembler::vpxor(dst, nds, src, vector_len);
1208     else
1209       Assembler::vxorpd(dst, nds, src, vector_len);
1210   }
1211   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1212     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1213       Assembler::vpxor(dst, nds, src, vector_len);
1214     else
1215       Assembler::vxorpd(dst, nds, src, vector_len);
1216   }
1217 
1218   // Simple version for AVX2 256bit vectors
1219   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1220   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1221 
1222   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1223     if (UseAVX > 2) {
1224       Assembler::vinserti32x4(dst, dst, src, imm8);
1225     } else if (UseAVX > 1) {
1226       // vinserti128 is available only in AVX2
1227       Assembler::vinserti128(dst, nds, src, imm8);
1228     } else {
1229       Assembler::vinsertf128(dst, nds, src, imm8);
1230     }
1231   }
1232 
1233   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1234     if (UseAVX > 2) {
1235       Assembler::vinserti32x4(dst, dst, src, imm8);
1236     } else if (UseAVX > 1) {
1237       // vinserti128 is available only in AVX2
1238       Assembler::vinserti128(dst, nds, src, imm8);
1239     } else {
1240       Assembler::vinsertf128(dst, nds, src, imm8);
1241     }
1242   }
1243 
1244   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1245     if (UseAVX > 2) {
1246       Assembler::vextracti32x4(dst, src, imm8);
1247     } else if (UseAVX > 1) {
1248       // vextracti128 is available only in AVX2
1249       Assembler::vextracti128(dst, src, imm8);
1250     } else {
1251       Assembler::vextractf128(dst, src, imm8);
1252     }
1253   }
1254 
1255   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1256     if (UseAVX > 2) {
1257       Assembler::vextracti32x4(dst, src, imm8);
1258     } else if (UseAVX > 1) {
1259       // vextracti128 is available only in AVX2
1260       Assembler::vextracti128(dst, src, imm8);
1261     } else {
1262       Assembler::vextractf128(dst, src, imm8);
1263     }
1264   }
1265 
1266   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1267   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1268     vinserti128(dst, dst, src, 1);
1269   }
1270   void vinserti128_high(XMMRegister dst, Address src) {
1271     vinserti128(dst, dst, src, 1);
1272   }
1273   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1274     vextracti128(dst, src, 1);
1275   }
1276   void vextracti128_high(Address dst, XMMRegister src) {
1277     vextracti128(dst, src, 1);
1278   }
1279 
1280   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1281     if (UseAVX > 2) {
1282       Assembler::vinsertf32x4(dst, dst, src, 1);
1283     } else {
1284       Assembler::vinsertf128(dst, dst, src, 1);
1285     }
1286   }
1287 
1288   void vinsertf128_high(XMMRegister dst, Address src) {
1289     if (UseAVX > 2) {
1290       Assembler::vinsertf32x4(dst, dst, src, 1);
1291     } else {
1292       Assembler::vinsertf128(dst, dst, src, 1);
1293     }
1294   }
1295 
1296   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1297     if (UseAVX > 2) {
1298       Assembler::vextractf32x4(dst, src, 1);
1299     } else {
1300       Assembler::vextractf128(dst, src, 1);
1301     }
1302   }
1303 
1304   void vextractf128_high(Address dst, XMMRegister src) {
1305     if (UseAVX > 2) {
1306       Assembler::vextractf32x4(dst, src, 1);
1307     } else {
1308       Assembler::vextractf128(dst, src, 1);
1309     }
1310   }
1311 
1312   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1313   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1314     Assembler::vinserti64x4(dst, dst, src, 1);
1315   }
1316   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1317     Assembler::vinsertf64x4(dst, dst, src, 1);
1318   }
1319   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1320     Assembler::vextracti64x4(dst, src, 1);
1321   }
1322   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1323     Assembler::vextractf64x4(dst, src, 1);
1324   }
1325   void vextractf64x4_high(Address dst, XMMRegister src) {
1326     Assembler::vextractf64x4(dst, src, 1);
1327   }
1328   void vinsertf64x4_high(XMMRegister dst, Address src) {
1329     Assembler::vinsertf64x4(dst, dst, src, 1);
1330   }
1331 
1332   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1333   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1334     vinserti128(dst, dst, src, 0);
1335   }
1336   void vinserti128_low(XMMRegister dst, Address src) {
1337     vinserti128(dst, dst, src, 0);
1338   }
1339   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1340     vextracti128(dst, src, 0);
1341   }
1342   void vextracti128_low(Address dst, XMMRegister src) {
1343     vextracti128(dst, src, 0);
1344   }
1345 
1346   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1347     if (UseAVX > 2) {
1348       Assembler::vinsertf32x4(dst, dst, src, 0);
1349     } else {
1350       Assembler::vinsertf128(dst, dst, src, 0);
1351     }
1352   }
1353 
1354   void vinsertf128_low(XMMRegister dst, Address src) {
1355     if (UseAVX > 2) {
1356       Assembler::vinsertf32x4(dst, dst, src, 0);
1357     } else {
1358       Assembler::vinsertf128(dst, dst, src, 0);
1359     }
1360   }
1361 
1362   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1363     if (UseAVX > 2) {
1364       Assembler::vextractf32x4(dst, src, 0);
1365     } else {
1366       Assembler::vextractf128(dst, src, 0);
1367     }
1368   }
1369 
1370   void vextractf128_low(Address dst, XMMRegister src) {
1371     if (UseAVX > 2) {
1372       Assembler::vextractf32x4(dst, src, 0);
1373     } else {
1374       Assembler::vextractf128(dst, src, 0);
1375     }
1376   }
1377 
1378   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1379   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1380     Assembler::vinserti64x4(dst, dst, src, 0);
1381   }
1382   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1383     Assembler::vinsertf64x4(dst, dst, src, 0);
1384   }
1385   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1386     Assembler::vextracti64x4(dst, src, 0);
1387   }
1388   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1389     Assembler::vextractf64x4(dst, src, 0);
1390   }
1391   void vextractf64x4_low(Address dst, XMMRegister src) {
1392     Assembler::vextractf64x4(dst, src, 0);
1393   }
1394   void vinsertf64x4_low(XMMRegister dst, Address src) {
1395     Assembler::vinsertf64x4(dst, dst, src, 0);
1396   }
1397 
1398   // Carry-Less Multiplication Quadword
1399   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1400     // 0x00 - multiply lower 64 bits [0:63]
1401     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1402   }
1403   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1404     // 0x11 - multiply upper 64 bits [64:127]
1405     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1406   }
1407 
1408   // Data
1409 
1410   void cmov32( Condition cc, Register dst, Address  src);
1411   void cmov32( Condition cc, Register dst, Register src);
1412 
1413   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1414 
1415   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1416   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1417 
1418   void movoop(Register dst, jobject obj);
1419   void movoop(Address dst, jobject obj);
1420 
1421   void mov_metadata(Register dst, Metadata* obj);
1422   void mov_metadata(Address dst, Metadata* obj);
1423 
1424   void movptr(ArrayAddress dst, Register src);
1425   // can this do an lea?
1426   void movptr(Register dst, ArrayAddress src);
1427 
1428   void movptr(Register dst, Address src);
1429 
1430 #ifdef _LP64
1431   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1432 #else
1433   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1434 #endif
1435 
1436   void movptr(Register dst, intptr_t src);
1437   void movptr(Register dst, Register src);
1438   void movptr(Address dst, intptr_t src);
1439 
1440   void movptr(Address dst, Register src);
1441 
1442   void movptr(Register dst, RegisterOrConstant src) {
1443     if (src.is_constant()) movptr(dst, src.as_constant());
1444     else                   movptr(dst, src.as_register());
1445   }
1446 
1447 #ifdef _LP64
1448   // Generally the next two are only used for moving NULL
1449   // Although there are situations in initializing the mark word where
1450   // they could be used. They are dangerous.
1451 
1452   // They only exist on LP64 so that int32_t and intptr_t are not the same
1453   // and we have ambiguous declarations.
1454 
1455   void movptr(Address dst, int32_t imm32);
1456   void movptr(Register dst, int32_t imm32);
1457 #endif // _LP64
1458 
1459   // to avoid hiding movl
1460   void mov32(AddressLiteral dst, Register src);
1461   void mov32(Register dst, AddressLiteral src);
1462 
1463   // to avoid hiding movb
1464   void movbyte(ArrayAddress dst, int src);
1465 
1466   // Import other mov() methods from the parent class or else
1467   // they will be hidden by the following overriding declaration.
1468   using Assembler::movdl;
1469   using Assembler::movq;
1470   void movdl(XMMRegister dst, AddressLiteral src);
1471   void movq(XMMRegister dst, AddressLiteral src);
1472 
1473   // Can push value or effective address
1474   void pushptr(AddressLiteral src);
1475 
1476   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1477   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1478 
1479   void pushoop(jobject obj);
1480   void pushklass(Metadata* obj);
1481 
1482   // sign extend as need a l to ptr sized element
1483   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1484   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1485 
1486   // C2 compiled method's prolog code.
1487   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1488 
1489   // clear memory of size 'cnt' qwords, starting at 'base';
1490   // if 'is_large' is set, do not try to produce short loop
1491   void clear_mem(Register base, Register cnt, Register rtmp, bool is_large);
1492 
1493 #ifdef COMPILER2
1494   void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1495                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1496 
1497   // IndexOf strings.
1498   // Small strings are loaded through stack if they cross page boundary.
1499   void string_indexof(Register str1, Register str2,
1500                       Register cnt1, Register cnt2,
1501                       int int_cnt2,  Register result,
1502                       XMMRegister vec, Register tmp,
1503                       int ae);
1504 
1505   // IndexOf for constant substrings with size >= 8 elements
1506   // which don't need to be loaded through stack.
1507   void string_indexofC8(Register str1, Register str2,
1508                       Register cnt1, Register cnt2,
1509                       int int_cnt2,  Register result,
1510                       XMMRegister vec, Register tmp,
1511                       int ae);
1512 
1513     // Smallest code: we don't need to load through stack,
1514     // check string tail.
1515 
1516   // helper function for string_compare
1517   void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1518                           Address::ScaleFactor scale, Address::ScaleFactor scale1,
1519                           Address::ScaleFactor scale2, Register index, int ae);
1520   // Compare strings.
1521   void string_compare(Register str1, Register str2,
1522                       Register cnt1, Register cnt2, Register result,
1523                       XMMRegister vec1, int ae);
1524 
1525   // Search for Non-ASCII character (Negative byte value) in a byte array,
1526   // return true if it has any and false otherwise.
1527   void has_negatives(Register ary1, Register len,
1528                      Register result, Register tmp1,
1529                      XMMRegister vec1, XMMRegister vec2);
1530 
1531   // Compare char[] or byte[] arrays.
1532   void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1533                      Register limit, Register result, Register chr,
1534                      XMMRegister vec1, XMMRegister vec2, bool is_char);
1535 
1536 #endif
1537 
1538   // Fill primitive arrays
1539   void generate_fill(BasicType t, bool aligned,
1540                      Register to, Register value, Register count,
1541                      Register rtmp, XMMRegister xtmp);
1542 
1543   void encode_iso_array(Register src, Register dst, Register len,
1544                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1545                         XMMRegister tmp4, Register tmp5, Register result);
1546 
1547 #ifdef _LP64
1548   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1549   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1550                              Register y, Register y_idx, Register z,
1551                              Register carry, Register product,
1552                              Register idx, Register kdx);
1553   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1554                               Register yz_idx, Register idx,
1555                               Register carry, Register product, int offset);
1556   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1557                                     Register carry, Register carry2,
1558                                     Register idx, Register jdx,
1559                                     Register yz_idx1, Register yz_idx2,
1560                                     Register tmp, Register tmp3, Register tmp4);
1561   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1562                                Register yz_idx, Register idx, Register jdx,
1563                                Register carry, Register product,
1564                                Register carry2);
1565   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1566                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1567   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1568                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1569   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1570                             Register tmp2);
1571   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1572                        Register rdxReg, Register raxReg);
1573   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1574   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1575                        Register tmp3, Register tmp4);
1576   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1577                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1578 
1579   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1580                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1581                Register raxReg);
1582   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1583                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1584                Register raxReg);
1585   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1586                            Register result, Register tmp1, Register tmp2,
1587                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1588 #endif
1589 
1590   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1591   void update_byte_crc32(Register crc, Register val, Register table);
1592   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1593   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1594   // Note on a naming convention:
1595   // Prefix w = register only used on a Westmere+ architecture
1596   // Prefix n = register only used on a Nehalem architecture
1597 #ifdef _LP64
1598   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1599                        Register tmp1, Register tmp2, Register tmp3);
1600 #else
1601   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1602                        Register tmp1, Register tmp2, Register tmp3,
1603                        XMMRegister xtmp1, XMMRegister xtmp2);
1604 #endif
1605   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1606                         Register in_out,
1607                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1608                         XMMRegister w_xtmp2,
1609                         Register tmp1,
1610                         Register n_tmp2, Register n_tmp3);
1611   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1612                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1613                        Register tmp1, Register tmp2,
1614                        Register n_tmp3);
1615   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1616                          Register in_out1, Register in_out2, Register in_out3,
1617                          Register tmp1, Register tmp2, Register tmp3,
1618                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1619                          Register tmp4, Register tmp5,
1620                          Register n_tmp6);
1621   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1622                             Register tmp1, Register tmp2, Register tmp3,
1623                             Register tmp4, Register tmp5, Register tmp6,
1624                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1625                             bool is_pclmulqdq_supported);
1626   // Fold 128-bit data chunk
1627   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1628   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1629   // Fold 8-bit data
1630   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1631   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1632 
1633   // Compress char[] array to byte[].
1634   void char_array_compress(Register src, Register dst, Register len,
1635                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1636                            XMMRegister tmp4, Register tmp5, Register result);
1637 
1638   // Inflate byte[] array to char[].
1639   void byte_array_inflate(Register src, Register dst, Register len,
1640                           XMMRegister tmp1, Register tmp2);
1641 
1642 };
1643 
1644 /**
1645  * class SkipIfEqual:
1646  *
1647  * Instantiating this class will result in assembly code being output that will
1648  * jump around any code emitted between the creation of the instance and it's
1649  * automatic destruction at the end of a scope block, depending on the value of
1650  * the flag passed to the constructor, which will be checked at run-time.
1651  */
1652 class SkipIfEqual {
1653  private:
1654   MacroAssembler* _masm;
1655   Label _label;
1656 
1657  public:
1658    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1659    ~SkipIfEqual();
1660 };
1661 
1662 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP