--- old/src/cpu/x86/vm/x86.ad	2016-04-12 19:50:24.847635400 -0700
+++ new/src/cpu/x86/vm/x86.ad	2016-04-12 19:50:24.473635400 -0700
@@ -1754,6 +1754,22 @@
   return ret_value;  // Per default match rules are supported.
 }
 
+const bool Matcher::has_predicated_vectors(void) {
+  bool ret_value = false;
+  switch(UseAVX) {
+    case 0:
+    case 1:
+    case 2:
+      break;
+
+    case 3:
+      ret_value = VM_Version::supports_avx512vl();
+      break;
+  }
+
+  return ret_value;
+}
+
 const int Matcher::float_pressure(int default_pressure_threshold) {
   int float_pressure_threshold = default_pressure_threshold;
 #ifdef _LP64
@@ -1871,7 +1887,7 @@
       __ vmovdqu(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]));
       break;
     case Op_VecZ:
-      __ evmovdqul(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 2);
+      __ evmovdquq(as_XMMRegister(Matcher::_regEncode[dst_lo]), as_XMMRegister(Matcher::_regEncode[src_lo]), 2);
       break;
     default:
       ShouldNotReachHere();
@@ -1926,7 +1942,7 @@
         __ vmovdqu(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset));
         break;
       case Op_VecZ:
-        __ evmovdqul(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset), 2);
+        __ evmovdquq(as_XMMRegister(Matcher::_regEncode[reg]), Address(rsp, stack_offset), 2);
         break;
       default:
         ShouldNotReachHere();
@@ -1946,7 +1962,7 @@
         __ vmovdqu(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]));
         break;
       case Op_VecZ:
-        __ evmovdqul(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 2);
+        __ evmovdquq(Address(rsp, stack_offset), as_XMMRegister(Matcher::_regEncode[reg]), 2);
         break;
       default:
         ShouldNotReachHere();
@@ -2086,6 +2102,21 @@
     return _count;
   }
 
+  void MachMskNode::emit(CodeBuffer &cbuf, PhaseRegAlloc*) const {
+    MacroAssembler _masm(&cbuf);
+    __ restoremsk();
+  }
+
+  uint MachMskNode::size(PhaseRegAlloc* ra_) const {
+    return MachNode::size(ra_);
+  }
+
+#ifndef PRODUCT
+  void MachMskNode::format(PhaseRegAlloc*, outputStream* st) const {
+    st->print("restoremsk \t# mask restore for loops");
+  }
+#endif
+
 #ifndef PRODUCT
   void MachBreakpointNode::format(PhaseRegAlloc*, outputStream* st) const {
     st->print("# breakpoint");
@@ -2172,6 +2203,19 @@
   ins_pipe(pipe_slow);
 %}
 
+// =================================EVEX special===============================
+
+instruct set_mask(rRegI dst, rRegI src) %{
+  predicate(VM_Version::supports_avx512vl());
+  match(Set dst (MaskCreateI src));
+  effect(TEMP dst);
+  format %{ "createmsk   $dst, $src" %}
+  ins_encode %{
+    __ createmsk($dst$$Register, $src$$Register);
+  %}
+  ins_pipe(pipe_slow);
+%}
+
 // ============================================================================
 
 instruct addF_reg(regF dst, regF src) %{
@@ -3047,11 +3091,11 @@
 %}
 
 // Load vectors (64 bytes long)
-instruct loadV64(vecZ dst, memory mem) %{
-  predicate(n->as_LoadVector()->memory_size() == 64);
+instruct loadV64_dword(vecZ dst, memory mem) %{
+  predicate(n->as_LoadVector()->memory_size() == 64 && n->as_LoadVector()->element_size() <= 4);
   match(Set dst (LoadVector mem));
   ins_cost(125);
-  format %{ "vmovdqu $dst k0,$mem\t! load vector (64 bytes)" %}
+  format %{ "vmovdqul $dst k0,$mem\t! load vector (64 bytes)" %}
   ins_encode %{
     int vector_len = 2;
     __ evmovdqul($dst$$XMMRegister, $mem$$Address, vector_len);
@@ -3059,6 +3103,19 @@
   ins_pipe( pipe_slow );
 %}
 
+// Load vectors (64 bytes long)
+instruct loadV64_qword(vecZ dst, memory mem) %{
+  predicate(n->as_LoadVector()->memory_size() == 64 && n->as_LoadVector()->element_size() > 4);
+  match(Set dst (LoadVector mem));
+  ins_cost(125);
+  format %{ "vmovdquq $dst k0,$mem\t! load vector (64 bytes)" %}
+  ins_encode %{
+    int vector_len = 2;
+    __ evmovdquq($dst$$XMMRegister, $mem$$Address, vector_len);
+  %}
+  ins_pipe( pipe_slow );
+%}
+
 // Store vectors
 instruct storeV4(memory mem, vecS src) %{
   predicate(n->as_StoreVector()->memory_size() == 4);
@@ -3104,17 +3161,29 @@
   ins_pipe( pipe_slow );
 %}
 
-instruct storeV64(memory mem, vecZ src) %{
-  predicate(n->as_StoreVector()->memory_size() == 64);
+instruct storeV64_dword(memory mem, vecZ src) %{
+  predicate(n->as_StoreVector()->memory_size() == 64 && n->as_StoreVector()->element_size() <= 4);
   match(Set mem (StoreVector mem src));
   ins_cost(145);
-  format %{ "vmovdqu $mem k0,$src\t! store vector (64 bytes)" %}
+  format %{ "vmovdqul $mem k0,$src\t! store vector (64 bytes)" %}
   ins_encode %{
     int vector_len = 2;
     __ evmovdqul($mem$$Address, $src$$XMMRegister, vector_len);
   %}
   ins_pipe( pipe_slow );
 %}
+
+instruct storeV64_qword(memory mem, vecZ src) %{
+  predicate(n->as_StoreVector()->memory_size() == 64 && n->as_StoreVector()->element_size() > 4);
+  match(Set mem (StoreVector mem src));
+  ins_cost(145);
+  format %{ "vmovdquq $mem k0,$src\t! store vector (64 bytes)" %}
+  ins_encode %{
+    int vector_len = 2;
+    __ evmovdquq($mem$$Address, $src$$XMMRegister, vector_len);
+  %}
+  ins_pipe( pipe_slow );
+%}
 
 // ====================LEGACY REPLICATE=======================================