1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "gc/shared/cardTableModRefBS.hpp" 29 #include "gc/shared/collectedHeap.inline.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "memory/resourceArea.hpp" 32 #include "prims/methodHandles.hpp" 33 #include "runtime/biasedLocking.hpp" 34 #include "runtime/interfaceSupport.hpp" 35 #include "runtime/objectMonitor.hpp" 36 #include "runtime/os.hpp" 37 #include "runtime/sharedRuntime.hpp" 38 #include "runtime/stubRoutines.hpp" 39 #include "utilities/macros.hpp" 40 #if INCLUDE_ALL_GCS 41 #include "gc/g1/g1CollectedHeap.inline.hpp" 42 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 43 #include "gc/g1/heapRegion.hpp" 44 #endif // INCLUDE_ALL_GCS 45 46 #ifdef PRODUCT 47 #define BLOCK_COMMENT(str) /* nothing */ 48 #define STOP(error) stop(error) 49 #else 50 #define BLOCK_COMMENT(str) block_comment(str) 51 #define STOP(error) block_comment(error); stop(error) 52 #endif 53 54 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 55 // Implementation of AddressLiteral 56 57 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms. 58 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = { 59 // -----------------Table 4.5 -------------------- // 60 16, 32, 64, // EVEX_FV(0) 61 4, 4, 4, // EVEX_FV(1) - with Evex.b 62 16, 32, 64, // EVEX_FV(2) - with Evex.w 63 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b 64 8, 16, 32, // EVEX_HV(0) 65 4, 4, 4, // EVEX_HV(1) - with Evex.b 66 // -----------------Table 4.6 -------------------- // 67 16, 32, 64, // EVEX_FVM(0) 68 1, 1, 1, // EVEX_T1S(0) 69 2, 2, 2, // EVEX_T1S(1) 70 4, 4, 4, // EVEX_T1S(2) 71 8, 8, 8, // EVEX_T1S(3) 72 4, 4, 4, // EVEX_T1F(0) 73 8, 8, 8, // EVEX_T1F(1) 74 8, 8, 8, // EVEX_T2(0) 75 0, 16, 16, // EVEX_T2(1) 76 0, 16, 16, // EVEX_T4(0) 77 0, 0, 32, // EVEX_T4(1) 78 0, 0, 32, // EVEX_T8(0) 79 8, 16, 32, // EVEX_HVM(0) 80 4, 8, 16, // EVEX_QVM(0) 81 2, 4, 8, // EVEX_OVM(0) 82 16, 16, 16, // EVEX_M128(0) 83 8, 32, 64, // EVEX_DUP(0) 84 0, 0, 0 // EVEX_NTUP 85 }; 86 87 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) { 88 _is_lval = false; 89 _target = target; 90 switch (rtype) { 91 case relocInfo::oop_type: 92 case relocInfo::metadata_type: 93 // Oops are a special case. Normally they would be their own section 94 // but in cases like icBuffer they are literals in the code stream that 95 // we don't have a section for. We use none so that we get a literal address 96 // which is always patchable. 97 break; 98 case relocInfo::external_word_type: 99 _rspec = external_word_Relocation::spec(target); 100 break; 101 case relocInfo::internal_word_type: 102 _rspec = internal_word_Relocation::spec(target); 103 break; 104 case relocInfo::opt_virtual_call_type: 105 _rspec = opt_virtual_call_Relocation::spec(); 106 break; 107 case relocInfo::static_call_type: 108 _rspec = static_call_Relocation::spec(); 109 break; 110 case relocInfo::runtime_call_type: 111 _rspec = runtime_call_Relocation::spec(); 112 break; 113 case relocInfo::poll_type: 114 case relocInfo::poll_return_type: 115 _rspec = Relocation::spec_simple(rtype); 116 break; 117 case relocInfo::none: 118 break; 119 default: 120 ShouldNotReachHere(); 121 break; 122 } 123 } 124 125 // Implementation of Address 126 127 #ifdef _LP64 128 129 Address Address::make_array(ArrayAddress adr) { 130 // Not implementable on 64bit machines 131 // Should have been handled higher up the call chain. 132 ShouldNotReachHere(); 133 return Address(); 134 } 135 136 // exceedingly dangerous constructor 137 Address::Address(int disp, address loc, relocInfo::relocType rtype) { 138 _base = noreg; 139 _index = noreg; 140 _scale = no_scale; 141 _disp = disp; 142 switch (rtype) { 143 case relocInfo::external_word_type: 144 _rspec = external_word_Relocation::spec(loc); 145 break; 146 case relocInfo::internal_word_type: 147 _rspec = internal_word_Relocation::spec(loc); 148 break; 149 case relocInfo::runtime_call_type: 150 // HMM 151 _rspec = runtime_call_Relocation::spec(); 152 break; 153 case relocInfo::poll_type: 154 case relocInfo::poll_return_type: 155 _rspec = Relocation::spec_simple(rtype); 156 break; 157 case relocInfo::none: 158 break; 159 default: 160 ShouldNotReachHere(); 161 } 162 } 163 #else // LP64 164 165 Address Address::make_array(ArrayAddress adr) { 166 AddressLiteral base = adr.base(); 167 Address index = adr.index(); 168 assert(index._disp == 0, "must not have disp"); // maybe it can? 169 Address array(index._base, index._index, index._scale, (intptr_t) base.target()); 170 array._rspec = base._rspec; 171 return array; 172 } 173 174 // exceedingly dangerous constructor 175 Address::Address(address loc, RelocationHolder spec) { 176 _base = noreg; 177 _index = noreg; 178 _scale = no_scale; 179 _disp = (intptr_t) loc; 180 _rspec = spec; 181 } 182 183 #endif // _LP64 184 185 186 187 // Convert the raw encoding form into the form expected by the constructor for 188 // Address. An index of 4 (rsp) corresponds to having no index, so convert 189 // that to noreg for the Address constructor. 190 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) { 191 RelocationHolder rspec; 192 if (disp_reloc != relocInfo::none) { 193 rspec = Relocation::spec_simple(disp_reloc); 194 } 195 bool valid_index = index != rsp->encoding(); 196 if (valid_index) { 197 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp)); 198 madr._rspec = rspec; 199 return madr; 200 } else { 201 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp)); 202 madr._rspec = rspec; 203 return madr; 204 } 205 } 206 207 // Implementation of Assembler 208 209 int AbstractAssembler::code_fill_byte() { 210 return (u_char)'\xF4'; // hlt 211 } 212 213 // make this go away someday 214 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) { 215 if (rtype == relocInfo::none) 216 emit_int32(data); 217 else 218 emit_data(data, Relocation::spec_simple(rtype), format); 219 } 220 221 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) { 222 assert(imm_operand == 0, "default format must be immediate in this file"); 223 assert(inst_mark() != NULL, "must be inside InstructionMark"); 224 if (rspec.type() != relocInfo::none) { 225 #ifdef ASSERT 226 check_relocation(rspec, format); 227 #endif 228 // Do not use AbstractAssembler::relocate, which is not intended for 229 // embedded words. Instead, relocate to the enclosing instruction. 230 231 // hack. call32 is too wide for mask so use disp32 232 if (format == call32_operand) 233 code_section()->relocate(inst_mark(), rspec, disp32_operand); 234 else 235 code_section()->relocate(inst_mark(), rspec, format); 236 } 237 emit_int32(data); 238 } 239 240 static int encode(Register r) { 241 int enc = r->encoding(); 242 if (enc >= 8) { 243 enc -= 8; 244 } 245 return enc; 246 } 247 248 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) { 249 assert(dst->has_byte_register(), "must have byte register"); 250 assert(isByte(op1) && isByte(op2), "wrong opcode"); 251 assert(isByte(imm8), "not a byte"); 252 assert((op1 & 0x01) == 0, "should be 8bit operation"); 253 emit_int8(op1); 254 emit_int8(op2 | encode(dst)); 255 emit_int8(imm8); 256 } 257 258 259 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) { 260 assert(isByte(op1) && isByte(op2), "wrong opcode"); 261 assert((op1 & 0x01) == 1, "should be 32bit operation"); 262 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 263 if (is8bit(imm32)) { 264 emit_int8(op1 | 0x02); // set sign bit 265 emit_int8(op2 | encode(dst)); 266 emit_int8(imm32 & 0xFF); 267 } else { 268 emit_int8(op1); 269 emit_int8(op2 | encode(dst)); 270 emit_int32(imm32); 271 } 272 } 273 274 // Force generation of a 4 byte immediate value even if it fits into 8bit 275 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) { 276 assert(isByte(op1) && isByte(op2), "wrong opcode"); 277 assert((op1 & 0x01) == 1, "should be 32bit operation"); 278 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 279 emit_int8(op1); 280 emit_int8(op2 | encode(dst)); 281 emit_int32(imm32); 282 } 283 284 // immediate-to-memory forms 285 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) { 286 assert((op1 & 0x01) == 1, "should be 32bit operation"); 287 assert((op1 & 0x02) == 0, "sign-extension bit should not be set"); 288 if (is8bit(imm32)) { 289 emit_int8(op1 | 0x02); // set sign bit 290 emit_operand(rm, adr, 1); 291 emit_int8(imm32 & 0xFF); 292 } else { 293 emit_int8(op1); 294 emit_operand(rm, adr, 4); 295 emit_int32(imm32); 296 } 297 } 298 299 300 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) { 301 assert(isByte(op1) && isByte(op2), "wrong opcode"); 302 emit_int8(op1); 303 emit_int8(op2 | encode(dst) << 3 | encode(src)); 304 } 305 306 307 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, 308 int cur_tuple_type, int in_size_in_bits, int cur_encoding) { 309 int mod_idx = 0; 310 // We will test if the displacement fits the compressed format and if so 311 // apply the compression to the displacment iff the result is8bit. 312 if (VM_Version::supports_evex() && is_evex_inst) { 313 switch (cur_tuple_type) { 314 case EVEX_FV: 315 if ((cur_encoding & VEX_W) == VEX_W) { 316 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 317 } else { 318 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 319 } 320 break; 321 322 case EVEX_HV: 323 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 324 break; 325 326 case EVEX_FVM: 327 break; 328 329 case EVEX_T1S: 330 switch (in_size_in_bits) { 331 case EVEX_8bit: 332 break; 333 334 case EVEX_16bit: 335 mod_idx = 1; 336 break; 337 338 case EVEX_32bit: 339 mod_idx = 2; 340 break; 341 342 case EVEX_64bit: 343 mod_idx = 3; 344 break; 345 } 346 break; 347 348 case EVEX_T1F: 349 case EVEX_T2: 350 case EVEX_T4: 351 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0; 352 break; 353 354 case EVEX_T8: 355 break; 356 357 case EVEX_HVM: 358 break; 359 360 case EVEX_QVM: 361 break; 362 363 case EVEX_OVM: 364 break; 365 366 case EVEX_M128: 367 break; 368 369 case EVEX_DUP: 370 break; 371 372 default: 373 assert(0, "no valid evex tuple_table entry"); 374 break; 375 } 376 377 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 378 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len]; 379 if ((disp % disp_factor) == 0) { 380 int new_disp = disp / disp_factor; 381 if ((-0x80 <= new_disp && new_disp < 0x80)) { 382 disp = new_disp; 383 } 384 } else { 385 return false; 386 } 387 } 388 } 389 return (-0x80 <= disp && disp < 0x80); 390 } 391 392 393 bool Assembler::emit_compressed_disp_byte(int &disp) { 394 int mod_idx = 0; 395 // We will test if the displacement fits the compressed format and if so 396 // apply the compression to the displacment iff the result is8bit. 397 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) { 398 int evex_encoding = _attributes->get_evex_encoding(); 399 int tuple_type = _attributes->get_tuple_type(); 400 switch (tuple_type) { 401 case EVEX_FV: 402 if ((evex_encoding & VEX_W) == VEX_W) { 403 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2; 404 } else { 405 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 406 } 407 break; 408 409 case EVEX_HV: 410 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0; 411 break; 412 413 case EVEX_FVM: 414 break; 415 416 case EVEX_T1S: 417 switch (_attributes->get_input_size()) { 418 case EVEX_8bit: 419 break; 420 421 case EVEX_16bit: 422 mod_idx = 1; 423 break; 424 425 case EVEX_32bit: 426 mod_idx = 2; 427 break; 428 429 case EVEX_64bit: 430 mod_idx = 3; 431 break; 432 } 433 break; 434 435 case EVEX_T1F: 436 case EVEX_T2: 437 case EVEX_T4: 438 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0; 439 break; 440 441 case EVEX_T8: 442 break; 443 444 case EVEX_HVM: 445 break; 446 447 case EVEX_QVM: 448 break; 449 450 case EVEX_OVM: 451 break; 452 453 case EVEX_M128: 454 break; 455 456 case EVEX_DUP: 457 break; 458 459 default: 460 assert(0, "no valid evex tuple_table entry"); 461 break; 462 } 463 464 int vector_len = _attributes->get_vector_len(); 465 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) { 466 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len]; 467 if ((disp % disp_factor) == 0) { 468 int new_disp = disp / disp_factor; 469 if (is8bit(new_disp)) { 470 disp = new_disp; 471 } 472 } else { 473 return false; 474 } 475 } 476 } 477 return is8bit(disp); 478 } 479 480 481 void Assembler::emit_operand(Register reg, Register base, Register index, 482 Address::ScaleFactor scale, int disp, 483 RelocationHolder const& rspec, 484 int rip_relative_correction) { 485 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type(); 486 487 // Encode the registers as needed in the fields they are used in 488 489 int regenc = encode(reg) << 3; 490 int indexenc = index->is_valid() ? encode(index) << 3 : 0; 491 int baseenc = base->is_valid() ? encode(base) : 0; 492 493 if (base->is_valid()) { 494 if (index->is_valid()) { 495 assert(scale != Address::no_scale, "inconsistent address"); 496 // [base + index*scale + disp] 497 if (disp == 0 && rtype == relocInfo::none && 498 base != rbp LP64_ONLY(&& base != r13)) { 499 // [base + index*scale] 500 // [00 reg 100][ss index base] 501 assert(index != rsp, "illegal addressing mode"); 502 emit_int8(0x04 | regenc); 503 emit_int8(scale << 6 | indexenc | baseenc); 504 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 505 // [base + index*scale + imm8] 506 // [01 reg 100][ss index base] imm8 507 assert(index != rsp, "illegal addressing mode"); 508 emit_int8(0x44 | regenc); 509 emit_int8(scale << 6 | indexenc | baseenc); 510 emit_int8(disp & 0xFF); 511 } else { 512 // [base + index*scale + disp32] 513 // [10 reg 100][ss index base] disp32 514 assert(index != rsp, "illegal addressing mode"); 515 emit_int8(0x84 | regenc); 516 emit_int8(scale << 6 | indexenc | baseenc); 517 emit_data(disp, rspec, disp32_operand); 518 } 519 } else if (base == rsp LP64_ONLY(|| base == r12)) { 520 // [rsp + disp] 521 if (disp == 0 && rtype == relocInfo::none) { 522 // [rsp] 523 // [00 reg 100][00 100 100] 524 emit_int8(0x04 | regenc); 525 emit_int8(0x24); 526 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 527 // [rsp + imm8] 528 // [01 reg 100][00 100 100] disp8 529 emit_int8(0x44 | regenc); 530 emit_int8(0x24); 531 emit_int8(disp & 0xFF); 532 } else { 533 // [rsp + imm32] 534 // [10 reg 100][00 100 100] disp32 535 emit_int8(0x84 | regenc); 536 emit_int8(0x24); 537 emit_data(disp, rspec, disp32_operand); 538 } 539 } else { 540 // [base + disp] 541 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode"); 542 if (disp == 0 && rtype == relocInfo::none && 543 base != rbp LP64_ONLY(&& base != r13)) { 544 // [base] 545 // [00 reg base] 546 emit_int8(0x00 | regenc | baseenc); 547 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) { 548 // [base + disp8] 549 // [01 reg base] disp8 550 emit_int8(0x40 | regenc | baseenc); 551 emit_int8(disp & 0xFF); 552 } else { 553 // [base + disp32] 554 // [10 reg base] disp32 555 emit_int8(0x80 | regenc | baseenc); 556 emit_data(disp, rspec, disp32_operand); 557 } 558 } 559 } else { 560 if (index->is_valid()) { 561 assert(scale != Address::no_scale, "inconsistent address"); 562 // [index*scale + disp] 563 // [00 reg 100][ss index 101] disp32 564 assert(index != rsp, "illegal addressing mode"); 565 emit_int8(0x04 | regenc); 566 emit_int8(scale << 6 | indexenc | 0x05); 567 emit_data(disp, rspec, disp32_operand); 568 } else if (rtype != relocInfo::none ) { 569 // [disp] (64bit) RIP-RELATIVE (32bit) abs 570 // [00 000 101] disp32 571 572 emit_int8(0x05 | regenc); 573 // Note that the RIP-rel. correction applies to the generated 574 // disp field, but _not_ to the target address in the rspec. 575 576 // disp was created by converting the target address minus the pc 577 // at the start of the instruction. That needs more correction here. 578 // intptr_t disp = target - next_ip; 579 assert(inst_mark() != NULL, "must be inside InstructionMark"); 580 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction; 581 int64_t adjusted = disp; 582 // Do rip-rel adjustment for 64bit 583 LP64_ONLY(adjusted -= (next_ip - inst_mark())); 584 assert(is_simm32(adjusted), 585 "must be 32bit offset (RIP relative address)"); 586 emit_data((int32_t) adjusted, rspec, disp32_operand); 587 588 } else { 589 // 32bit never did this, did everything as the rip-rel/disp code above 590 // [disp] ABSOLUTE 591 // [00 reg 100][00 100 101] disp32 592 emit_int8(0x04 | regenc); 593 emit_int8(0x25); 594 emit_data(disp, rspec, disp32_operand); 595 } 596 } 597 } 598 599 void Assembler::emit_operand(XMMRegister reg, Register base, Register index, 600 Address::ScaleFactor scale, int disp, 601 RelocationHolder const& rspec) { 602 if (UseAVX > 2) { 603 int xreg_enc = reg->encoding(); 604 if (xreg_enc > 15) { 605 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf); 606 emit_operand((Register)new_reg, base, index, scale, disp, rspec); 607 return; 608 } 609 } 610 emit_operand((Register)reg, base, index, scale, disp, rspec); 611 } 612 613 // Secret local extension to Assembler::WhichOperand: 614 #define end_pc_operand (_WhichOperand_limit) 615 616 address Assembler::locate_operand(address inst, WhichOperand which) { 617 // Decode the given instruction, and return the address of 618 // an embedded 32-bit operand word. 619 620 // If "which" is disp32_operand, selects the displacement portion 621 // of an effective address specifier. 622 // If "which" is imm64_operand, selects the trailing immediate constant. 623 // If "which" is call32_operand, selects the displacement of a call or jump. 624 // Caller is responsible for ensuring that there is such an operand, 625 // and that it is 32/64 bits wide. 626 627 // If "which" is end_pc_operand, find the end of the instruction. 628 629 address ip = inst; 630 bool is_64bit = false; 631 632 debug_only(bool has_disp32 = false); 633 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn 634 635 again_after_prefix: 636 switch (0xFF & *ip++) { 637 638 // These convenience macros generate groups of "case" labels for the switch. 639 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3 640 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \ 641 case (x)+4: case (x)+5: case (x)+6: case (x)+7 642 #define REP16(x) REP8((x)+0): \ 643 case REP8((x)+8) 644 645 case CS_segment: 646 case SS_segment: 647 case DS_segment: 648 case ES_segment: 649 case FS_segment: 650 case GS_segment: 651 // Seems dubious 652 LP64_ONLY(assert(false, "shouldn't have that prefix")); 653 assert(ip == inst+1, "only one prefix allowed"); 654 goto again_after_prefix; 655 656 case 0x67: 657 case REX: 658 case REX_B: 659 case REX_X: 660 case REX_XB: 661 case REX_R: 662 case REX_RB: 663 case REX_RX: 664 case REX_RXB: 665 NOT_LP64(assert(false, "64bit prefixes")); 666 goto again_after_prefix; 667 668 case REX_W: 669 case REX_WB: 670 case REX_WX: 671 case REX_WXB: 672 case REX_WR: 673 case REX_WRB: 674 case REX_WRX: 675 case REX_WRXB: 676 NOT_LP64(assert(false, "64bit prefixes")); 677 is_64bit = true; 678 goto again_after_prefix; 679 680 case 0xFF: // pushq a; decl a; incl a; call a; jmp a 681 case 0x88: // movb a, r 682 case 0x89: // movl a, r 683 case 0x8A: // movb r, a 684 case 0x8B: // movl r, a 685 case 0x8F: // popl a 686 debug_only(has_disp32 = true); 687 break; 688 689 case 0x68: // pushq #32 690 if (which == end_pc_operand) { 691 return ip + 4; 692 } 693 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate"); 694 return ip; // not produced by emit_operand 695 696 case 0x66: // movw ... (size prefix) 697 again_after_size_prefix2: 698 switch (0xFF & *ip++) { 699 case REX: 700 case REX_B: 701 case REX_X: 702 case REX_XB: 703 case REX_R: 704 case REX_RB: 705 case REX_RX: 706 case REX_RXB: 707 case REX_W: 708 case REX_WB: 709 case REX_WX: 710 case REX_WXB: 711 case REX_WR: 712 case REX_WRB: 713 case REX_WRX: 714 case REX_WRXB: 715 NOT_LP64(assert(false, "64bit prefix found")); 716 goto again_after_size_prefix2; 717 case 0x8B: // movw r, a 718 case 0x89: // movw a, r 719 debug_only(has_disp32 = true); 720 break; 721 case 0xC7: // movw a, #16 722 debug_only(has_disp32 = true); 723 tail_size = 2; // the imm16 724 break; 725 case 0x0F: // several SSE/SSE2 variants 726 ip--; // reparse the 0x0F 727 goto again_after_prefix; 728 default: 729 ShouldNotReachHere(); 730 } 731 break; 732 733 case REP8(0xB8): // movl/q r, #32/#64(oop?) 734 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4); 735 // these asserts are somewhat nonsensical 736 #ifndef _LP64 737 assert(which == imm_operand || which == disp32_operand, 738 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 739 #else 740 assert((which == call32_operand || which == imm_operand) && is_64bit || 741 which == narrow_oop_operand && !is_64bit, 742 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip)); 743 #endif // _LP64 744 return ip; 745 746 case 0x69: // imul r, a, #32 747 case 0xC7: // movl a, #32(oop?) 748 tail_size = 4; 749 debug_only(has_disp32 = true); // has both kinds of operands! 750 break; 751 752 case 0x0F: // movx..., etc. 753 switch (0xFF & *ip++) { 754 case 0x3A: // pcmpestri 755 tail_size = 1; 756 case 0x38: // ptest, pmovzxbw 757 ip++; // skip opcode 758 debug_only(has_disp32 = true); // has both kinds of operands! 759 break; 760 761 case 0x70: // pshufd r, r/a, #8 762 debug_only(has_disp32 = true); // has both kinds of operands! 763 case 0x73: // psrldq r, #8 764 tail_size = 1; 765 break; 766 767 case 0x12: // movlps 768 case 0x28: // movaps 769 case 0x2E: // ucomiss 770 case 0x2F: // comiss 771 case 0x54: // andps 772 case 0x55: // andnps 773 case 0x56: // orps 774 case 0x57: // xorps 775 case 0x58: // addpd 776 case 0x59: // mulpd 777 case 0x6E: // movd 778 case 0x7E: // movd 779 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush 780 case 0xFE: // paddd 781 debug_only(has_disp32 = true); 782 break; 783 784 case 0xAD: // shrd r, a, %cl 785 case 0xAF: // imul r, a 786 case 0xBE: // movsbl r, a (movsxb) 787 case 0xBF: // movswl r, a (movsxw) 788 case 0xB6: // movzbl r, a (movzxb) 789 case 0xB7: // movzwl r, a (movzxw) 790 case REP16(0x40): // cmovl cc, r, a 791 case 0xB0: // cmpxchgb 792 case 0xB1: // cmpxchg 793 case 0xC1: // xaddl 794 case 0xC7: // cmpxchg8 795 case REP16(0x90): // setcc a 796 debug_only(has_disp32 = true); 797 // fall out of the switch to decode the address 798 break; 799 800 case 0xC4: // pinsrw r, a, #8 801 debug_only(has_disp32 = true); 802 case 0xC5: // pextrw r, r, #8 803 tail_size = 1; // the imm8 804 break; 805 806 case 0xAC: // shrd r, a, #8 807 debug_only(has_disp32 = true); 808 tail_size = 1; // the imm8 809 break; 810 811 case REP16(0x80): // jcc rdisp32 812 if (which == end_pc_operand) return ip + 4; 813 assert(which == call32_operand, "jcc has no disp32 or imm"); 814 return ip; 815 default: 816 ShouldNotReachHere(); 817 } 818 break; 819 820 case 0x81: // addl a, #32; addl r, #32 821 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 822 // on 32bit in the case of cmpl, the imm might be an oop 823 tail_size = 4; 824 debug_only(has_disp32 = true); // has both kinds of operands! 825 break; 826 827 case 0x83: // addl a, #8; addl r, #8 828 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl 829 debug_only(has_disp32 = true); // has both kinds of operands! 830 tail_size = 1; 831 break; 832 833 case 0x9B: 834 switch (0xFF & *ip++) { 835 case 0xD9: // fnstcw a 836 debug_only(has_disp32 = true); 837 break; 838 default: 839 ShouldNotReachHere(); 840 } 841 break; 842 843 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a 844 case REP4(0x10): // adc... 845 case REP4(0x20): // and... 846 case REP4(0x30): // xor... 847 case REP4(0x08): // or... 848 case REP4(0x18): // sbb... 849 case REP4(0x28): // sub... 850 case 0xF7: // mull a 851 case 0x8D: // lea r, a 852 case 0x87: // xchg r, a 853 case REP4(0x38): // cmp... 854 case 0x85: // test r, a 855 debug_only(has_disp32 = true); // has both kinds of operands! 856 break; 857 858 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8 859 case 0xC6: // movb a, #8 860 case 0x80: // cmpb a, #8 861 case 0x6B: // imul r, a, #8 862 debug_only(has_disp32 = true); // has both kinds of operands! 863 tail_size = 1; // the imm8 864 break; 865 866 case 0xC4: // VEX_3bytes 867 case 0xC5: // VEX_2bytes 868 assert((UseAVX > 0), "shouldn't have VEX prefix"); 869 assert(ip == inst+1, "no prefixes allowed"); 870 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions 871 // but they have prefix 0x0F and processed when 0x0F processed above. 872 // 873 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES 874 // instructions (these instructions are not supported in 64-bit mode). 875 // To distinguish them bits [7:6] are set in the VEX second byte since 876 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set 877 // those VEX bits REX and vvvv bits are inverted. 878 // 879 // Fortunately C2 doesn't generate these instructions so we don't need 880 // to check for them in product version. 881 882 // Check second byte 883 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions")); 884 885 int vex_opcode; 886 // First byte 887 if ((0xFF & *inst) == VEX_3bytes) { 888 vex_opcode = VEX_OPCODE_MASK & *ip; 889 ip++; // third byte 890 is_64bit = ((VEX_W & *ip) == VEX_W); 891 } else { 892 vex_opcode = VEX_OPCODE_0F; 893 } 894 ip++; // opcode 895 // To find the end of instruction (which == end_pc_operand). 896 switch (vex_opcode) { 897 case VEX_OPCODE_0F: 898 switch (0xFF & *ip) { 899 case 0x70: // pshufd r, r/a, #8 900 case 0x71: // ps[rl|ra|ll]w r, #8 901 case 0x72: // ps[rl|ra|ll]d r, #8 902 case 0x73: // ps[rl|ra|ll]q r, #8 903 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8 904 case 0xC4: // pinsrw r, r, r/a, #8 905 case 0xC5: // pextrw r/a, r, #8 906 case 0xC6: // shufp[s|d] r, r, r/a, #8 907 tail_size = 1; // the imm8 908 break; 909 } 910 break; 911 case VEX_OPCODE_0F_3A: 912 tail_size = 1; 913 break; 914 } 915 ip++; // skip opcode 916 debug_only(has_disp32 = true); // has both kinds of operands! 917 break; 918 919 case 0x62: // EVEX_4bytes 920 assert((UseAVX > 0), "shouldn't have EVEX prefix"); 921 assert(ip == inst+1, "no prefixes allowed"); 922 // no EVEX collisions, all instructions that have 0x62 opcodes 923 // have EVEX versions and are subopcodes of 0x66 924 ip++; // skip P0 and exmaine W in P1 925 is_64bit = ((VEX_W & *ip) == VEX_W); 926 ip++; // move to P2 927 ip++; // skip P2, move to opcode 928 // To find the end of instruction (which == end_pc_operand). 929 switch (0xFF & *ip) { 930 case 0x22: // pinsrd r, r/a, #8 931 case 0x61: // pcmpestri r, r/a, #8 932 case 0x70: // pshufd r, r/a, #8 933 case 0x73: // psrldq r, #8 934 tail_size = 1; // the imm8 935 break; 936 default: 937 break; 938 } 939 ip++; // skip opcode 940 debug_only(has_disp32 = true); // has both kinds of operands! 941 break; 942 943 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1 944 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl 945 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a 946 case 0xDD: // fld_d a; fst_d a; fstp_d a 947 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a 948 case 0xDF: // fild_d a; fistp_d a 949 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a 950 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a 951 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a 952 debug_only(has_disp32 = true); 953 break; 954 955 case 0xE8: // call rdisp32 956 case 0xE9: // jmp rdisp32 957 if (which == end_pc_operand) return ip + 4; 958 assert(which == call32_operand, "call has no disp32 or imm"); 959 return ip; 960 961 case 0xF0: // Lock 962 assert(os::is_MP(), "only on MP"); 963 goto again_after_prefix; 964 965 case 0xF3: // For SSE 966 case 0xF2: // For SSE2 967 switch (0xFF & *ip++) { 968 case REX: 969 case REX_B: 970 case REX_X: 971 case REX_XB: 972 case REX_R: 973 case REX_RB: 974 case REX_RX: 975 case REX_RXB: 976 case REX_W: 977 case REX_WB: 978 case REX_WX: 979 case REX_WXB: 980 case REX_WR: 981 case REX_WRB: 982 case REX_WRX: 983 case REX_WRXB: 984 NOT_LP64(assert(false, "found 64bit prefix")); 985 ip++; 986 default: 987 ip++; 988 } 989 debug_only(has_disp32 = true); // has both kinds of operands! 990 break; 991 992 default: 993 ShouldNotReachHere(); 994 995 #undef REP8 996 #undef REP16 997 } 998 999 assert(which != call32_operand, "instruction is not a call, jmp, or jcc"); 1000 #ifdef _LP64 1001 assert(which != imm_operand, "instruction is not a movq reg, imm64"); 1002 #else 1003 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field"); 1004 assert(which != imm_operand || has_disp32, "instruction has no imm32 field"); 1005 #endif // LP64 1006 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field"); 1007 1008 // parse the output of emit_operand 1009 int op2 = 0xFF & *ip++; 1010 int base = op2 & 0x07; 1011 int op3 = -1; 1012 const int b100 = 4; 1013 const int b101 = 5; 1014 if (base == b100 && (op2 >> 6) != 3) { 1015 op3 = 0xFF & *ip++; 1016 base = op3 & 0x07; // refetch the base 1017 } 1018 // now ip points at the disp (if any) 1019 1020 switch (op2 >> 6) { 1021 case 0: 1022 // [00 reg 100][ss index base] 1023 // [00 reg 100][00 100 esp] 1024 // [00 reg base] 1025 // [00 reg 100][ss index 101][disp32] 1026 // [00 reg 101] [disp32] 1027 1028 if (base == b101) { 1029 if (which == disp32_operand) 1030 return ip; // caller wants the disp32 1031 ip += 4; // skip the disp32 1032 } 1033 break; 1034 1035 case 1: 1036 // [01 reg 100][ss index base][disp8] 1037 // [01 reg 100][00 100 esp][disp8] 1038 // [01 reg base] [disp8] 1039 ip += 1; // skip the disp8 1040 break; 1041 1042 case 2: 1043 // [10 reg 100][ss index base][disp32] 1044 // [10 reg 100][00 100 esp][disp32] 1045 // [10 reg base] [disp32] 1046 if (which == disp32_operand) 1047 return ip; // caller wants the disp32 1048 ip += 4; // skip the disp32 1049 break; 1050 1051 case 3: 1052 // [11 reg base] (not a memory addressing mode) 1053 break; 1054 } 1055 1056 if (which == end_pc_operand) { 1057 return ip + tail_size; 1058 } 1059 1060 #ifdef _LP64 1061 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32"); 1062 #else 1063 assert(which == imm_operand, "instruction has only an imm field"); 1064 #endif // LP64 1065 return ip; 1066 } 1067 1068 address Assembler::locate_next_instruction(address inst) { 1069 // Secretly share code with locate_operand: 1070 return locate_operand(inst, end_pc_operand); 1071 } 1072 1073 1074 #ifdef ASSERT 1075 void Assembler::check_relocation(RelocationHolder const& rspec, int format) { 1076 address inst = inst_mark(); 1077 assert(inst != NULL && inst < pc(), "must point to beginning of instruction"); 1078 address opnd; 1079 1080 Relocation* r = rspec.reloc(); 1081 if (r->type() == relocInfo::none) { 1082 return; 1083 } else if (r->is_call() || format == call32_operand) { 1084 // assert(format == imm32_operand, "cannot specify a nonzero format"); 1085 opnd = locate_operand(inst, call32_operand); 1086 } else if (r->is_data()) { 1087 assert(format == imm_operand || format == disp32_operand 1088 LP64_ONLY(|| format == narrow_oop_operand), "format ok"); 1089 opnd = locate_operand(inst, (WhichOperand)format); 1090 } else { 1091 assert(format == imm_operand, "cannot specify a format"); 1092 return; 1093 } 1094 assert(opnd == pc(), "must put operand where relocs can find it"); 1095 } 1096 #endif // ASSERT 1097 1098 void Assembler::emit_operand32(Register reg, Address adr) { 1099 assert(reg->encoding() < 8, "no extended registers"); 1100 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1101 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1102 adr._rspec); 1103 } 1104 1105 void Assembler::emit_operand(Register reg, Address adr, 1106 int rip_relative_correction) { 1107 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1108 adr._rspec, 1109 rip_relative_correction); 1110 } 1111 1112 void Assembler::emit_operand(XMMRegister reg, Address adr) { 1113 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, 1114 adr._rspec); 1115 } 1116 1117 // MMX operations 1118 void Assembler::emit_operand(MMXRegister reg, Address adr) { 1119 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1120 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1121 } 1122 1123 // work around gcc (3.2.1-7a) bug 1124 void Assembler::emit_operand(Address adr, MMXRegister reg) { 1125 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers"); 1126 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec); 1127 } 1128 1129 1130 void Assembler::emit_farith(int b1, int b2, int i) { 1131 assert(isByte(b1) && isByte(b2), "wrong opcode"); 1132 assert(0 <= i && i < 8, "illegal stack offset"); 1133 emit_int8(b1); 1134 emit_int8(b2 + i); 1135 } 1136 1137 1138 // Now the Assembler instructions (identical for 32/64 bits) 1139 1140 void Assembler::adcl(Address dst, int32_t imm32) { 1141 InstructionMark im(this); 1142 prefix(dst); 1143 emit_arith_operand(0x81, rdx, dst, imm32); 1144 } 1145 1146 void Assembler::adcl(Address dst, Register src) { 1147 InstructionMark im(this); 1148 prefix(dst, src); 1149 emit_int8(0x11); 1150 emit_operand(src, dst); 1151 } 1152 1153 void Assembler::adcl(Register dst, int32_t imm32) { 1154 prefix(dst); 1155 emit_arith(0x81, 0xD0, dst, imm32); 1156 } 1157 1158 void Assembler::adcl(Register dst, Address src) { 1159 InstructionMark im(this); 1160 prefix(src, dst); 1161 emit_int8(0x13); 1162 emit_operand(dst, src); 1163 } 1164 1165 void Assembler::adcl(Register dst, Register src) { 1166 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1167 emit_arith(0x13, 0xC0, dst, src); 1168 } 1169 1170 void Assembler::addl(Address dst, int32_t imm32) { 1171 InstructionMark im(this); 1172 prefix(dst); 1173 emit_arith_operand(0x81, rax, dst, imm32); 1174 } 1175 1176 void Assembler::addb(Address dst, int imm8) { 1177 InstructionMark im(this); 1178 prefix(dst); 1179 emit_int8((unsigned char)0x80); 1180 emit_operand(rax, dst, 1); 1181 emit_int8(imm8); 1182 } 1183 1184 void Assembler::addw(Address dst, int imm16) { 1185 InstructionMark im(this); 1186 emit_int8(0x66); 1187 prefix(dst); 1188 emit_int8((unsigned char)0x81); 1189 emit_operand(rax, dst, 2); 1190 emit_int16(imm16); 1191 } 1192 1193 void Assembler::addl(Address dst, Register src) { 1194 InstructionMark im(this); 1195 prefix(dst, src); 1196 emit_int8(0x01); 1197 emit_operand(src, dst); 1198 } 1199 1200 void Assembler::addl(Register dst, int32_t imm32) { 1201 prefix(dst); 1202 emit_arith(0x81, 0xC0, dst, imm32); 1203 } 1204 1205 void Assembler::addl(Register dst, Address src) { 1206 InstructionMark im(this); 1207 prefix(src, dst); 1208 emit_int8(0x03); 1209 emit_operand(dst, src); 1210 } 1211 1212 void Assembler::addl(Register dst, Register src) { 1213 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1214 emit_arith(0x03, 0xC0, dst, src); 1215 } 1216 1217 void Assembler::addr_nop_4() { 1218 assert(UseAddressNop, "no CPU support"); 1219 // 4 bytes: NOP DWORD PTR [EAX+0] 1220 emit_int8(0x0F); 1221 emit_int8(0x1F); 1222 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc); 1223 emit_int8(0); // 8-bits offset (1 byte) 1224 } 1225 1226 void Assembler::addr_nop_5() { 1227 assert(UseAddressNop, "no CPU support"); 1228 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset 1229 emit_int8(0x0F); 1230 emit_int8(0x1F); 1231 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4); 1232 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1233 emit_int8(0); // 8-bits offset (1 byte) 1234 } 1235 1236 void Assembler::addr_nop_7() { 1237 assert(UseAddressNop, "no CPU support"); 1238 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset 1239 emit_int8(0x0F); 1240 emit_int8(0x1F); 1241 emit_int8((unsigned char)0x80); 1242 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc); 1243 emit_int32(0); // 32-bits offset (4 bytes) 1244 } 1245 1246 void Assembler::addr_nop_8() { 1247 assert(UseAddressNop, "no CPU support"); 1248 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset 1249 emit_int8(0x0F); 1250 emit_int8(0x1F); 1251 emit_int8((unsigned char)0x84); 1252 // emit_rm(cbuf, 0x2, EAX_enc, 0x4); 1253 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc); 1254 emit_int32(0); // 32-bits offset (4 bytes) 1255 } 1256 1257 void Assembler::addsd(XMMRegister dst, XMMRegister src) { 1258 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1259 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1260 attributes.set_rex_vex_w_reverted(); 1261 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1262 emit_int8(0x58); 1263 emit_int8((unsigned char)(0xC0 | encode)); 1264 } 1265 1266 void Assembler::addsd(XMMRegister dst, Address src) { 1267 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1268 InstructionMark im(this); 1269 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1270 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1271 attributes.set_rex_vex_w_reverted(); 1272 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1273 emit_int8(0x58); 1274 emit_operand(dst, src); 1275 } 1276 1277 void Assembler::addss(XMMRegister dst, XMMRegister src) { 1278 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1279 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1280 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1281 emit_int8(0x58); 1282 emit_int8((unsigned char)(0xC0 | encode)); 1283 } 1284 1285 void Assembler::addss(XMMRegister dst, Address src) { 1286 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1287 InstructionMark im(this); 1288 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1289 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1290 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1291 emit_int8(0x58); 1292 emit_operand(dst, src); 1293 } 1294 1295 void Assembler::aesdec(XMMRegister dst, Address src) { 1296 assert(VM_Version::supports_aes(), ""); 1297 InstructionMark im(this); 1298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1299 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1300 emit_int8((unsigned char)0xDE); 1301 emit_operand(dst, src); 1302 } 1303 1304 void Assembler::aesdec(XMMRegister dst, XMMRegister src) { 1305 assert(VM_Version::supports_aes(), ""); 1306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1307 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1308 emit_int8((unsigned char)0xDE); 1309 emit_int8(0xC0 | encode); 1310 } 1311 1312 void Assembler::aesdeclast(XMMRegister dst, Address src) { 1313 assert(VM_Version::supports_aes(), ""); 1314 InstructionMark im(this); 1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1316 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1317 emit_int8((unsigned char)0xDF); 1318 emit_operand(dst, src); 1319 } 1320 1321 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) { 1322 assert(VM_Version::supports_aes(), ""); 1323 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1324 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1325 emit_int8((unsigned char)0xDF); 1326 emit_int8((unsigned char)(0xC0 | encode)); 1327 } 1328 1329 void Assembler::aesenc(XMMRegister dst, Address src) { 1330 assert(VM_Version::supports_aes(), ""); 1331 InstructionMark im(this); 1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1333 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1334 emit_int8((unsigned char)0xDC); 1335 emit_operand(dst, src); 1336 } 1337 1338 void Assembler::aesenc(XMMRegister dst, XMMRegister src) { 1339 assert(VM_Version::supports_aes(), ""); 1340 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1341 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1342 emit_int8((unsigned char)0xDC); 1343 emit_int8(0xC0 | encode); 1344 } 1345 1346 void Assembler::aesenclast(XMMRegister dst, Address src) { 1347 assert(VM_Version::supports_aes(), ""); 1348 InstructionMark im(this); 1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1350 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1351 emit_int8((unsigned char)0xDD); 1352 emit_operand(dst, src); 1353 } 1354 1355 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) { 1356 assert(VM_Version::supports_aes(), ""); 1357 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1358 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 1359 emit_int8((unsigned char)0xDD); 1360 emit_int8((unsigned char)(0xC0 | encode)); 1361 } 1362 1363 void Assembler::andl(Address dst, int32_t imm32) { 1364 InstructionMark im(this); 1365 prefix(dst); 1366 emit_int8((unsigned char)0x81); 1367 emit_operand(rsp, dst, 4); 1368 emit_int32(imm32); 1369 } 1370 1371 void Assembler::andl(Register dst, int32_t imm32) { 1372 prefix(dst); 1373 emit_arith(0x81, 0xE0, dst, imm32); 1374 } 1375 1376 void Assembler::andl(Register dst, Address src) { 1377 InstructionMark im(this); 1378 prefix(src, dst); 1379 emit_int8(0x23); 1380 emit_operand(dst, src); 1381 } 1382 1383 void Assembler::andl(Register dst, Register src) { 1384 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1385 emit_arith(0x23, 0xC0, dst, src); 1386 } 1387 1388 void Assembler::andnl(Register dst, Register src1, Register src2) { 1389 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1390 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1391 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1392 emit_int8((unsigned char)0xF2); 1393 emit_int8((unsigned char)(0xC0 | encode)); 1394 } 1395 1396 void Assembler::andnl(Register dst, Register src1, Address src2) { 1397 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1398 InstructionMark im(this); 1399 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1400 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1401 emit_int8((unsigned char)0xF2); 1402 emit_operand(dst, src2); 1403 } 1404 1405 void Assembler::bsfl(Register dst, Register src) { 1406 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1407 emit_int8(0x0F); 1408 emit_int8((unsigned char)0xBC); 1409 emit_int8((unsigned char)(0xC0 | encode)); 1410 } 1411 1412 void Assembler::bsrl(Register dst, Register src) { 1413 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1414 emit_int8(0x0F); 1415 emit_int8((unsigned char)0xBD); 1416 emit_int8((unsigned char)(0xC0 | encode)); 1417 } 1418 1419 void Assembler::bswapl(Register reg) { // bswap 1420 int encode = prefix_and_encode(reg->encoding()); 1421 emit_int8(0x0F); 1422 emit_int8((unsigned char)(0xC8 | encode)); 1423 } 1424 1425 void Assembler::blsil(Register dst, Register src) { 1426 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1427 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1428 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1429 emit_int8((unsigned char)0xF3); 1430 emit_int8((unsigned char)(0xC0 | encode)); 1431 } 1432 1433 void Assembler::blsil(Register dst, Address src) { 1434 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1435 InstructionMark im(this); 1436 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1437 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1438 emit_int8((unsigned char)0xF3); 1439 emit_operand(rbx, src); 1440 } 1441 1442 void Assembler::blsmskl(Register dst, Register src) { 1443 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1444 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1445 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1446 emit_int8((unsigned char)0xF3); 1447 emit_int8((unsigned char)(0xC0 | encode)); 1448 } 1449 1450 void Assembler::blsmskl(Register dst, Address src) { 1451 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1452 InstructionMark im(this); 1453 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1454 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1455 emit_int8((unsigned char)0xF3); 1456 emit_operand(rdx, src); 1457 } 1458 1459 void Assembler::blsrl(Register dst, Register src) { 1460 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1461 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1462 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1463 emit_int8((unsigned char)0xF3); 1464 emit_int8((unsigned char)(0xC0 | encode)); 1465 } 1466 1467 void Assembler::blsrl(Register dst, Address src) { 1468 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 1469 InstructionMark im(this); 1470 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 1471 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 1472 emit_int8((unsigned char)0xF3); 1473 emit_operand(rcx, src); 1474 } 1475 1476 void Assembler::call(Label& L, relocInfo::relocType rtype) { 1477 // suspect disp32 is always good 1478 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand); 1479 1480 if (L.is_bound()) { 1481 const int long_size = 5; 1482 int offs = (int)( target(L) - pc() ); 1483 assert(offs <= 0, "assembler error"); 1484 InstructionMark im(this); 1485 // 1110 1000 #32-bit disp 1486 emit_int8((unsigned char)0xE8); 1487 emit_data(offs - long_size, rtype, operand); 1488 } else { 1489 InstructionMark im(this); 1490 // 1110 1000 #32-bit disp 1491 L.add_patch_at(code(), locator()); 1492 1493 emit_int8((unsigned char)0xE8); 1494 emit_data(int(0), rtype, operand); 1495 } 1496 } 1497 1498 void Assembler::call(Register dst) { 1499 int encode = prefix_and_encode(dst->encoding()); 1500 emit_int8((unsigned char)0xFF); 1501 emit_int8((unsigned char)(0xD0 | encode)); 1502 } 1503 1504 1505 void Assembler::call(Address adr) { 1506 InstructionMark im(this); 1507 prefix(adr); 1508 emit_int8((unsigned char)0xFF); 1509 emit_operand(rdx, adr); 1510 } 1511 1512 void Assembler::call_literal(address entry, RelocationHolder const& rspec) { 1513 assert(entry != NULL, "call most probably wrong"); 1514 InstructionMark im(this); 1515 emit_int8((unsigned char)0xE8); 1516 intptr_t disp = entry - (pc() + sizeof(int32_t)); 1517 assert(is_simm32(disp), "must be 32bit offset (call2)"); 1518 // Technically, should use call32_operand, but this format is 1519 // implied by the fact that we're emitting a call instruction. 1520 1521 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand); 1522 emit_data((int) disp, rspec, operand); 1523 } 1524 1525 void Assembler::cdql() { 1526 emit_int8((unsigned char)0x99); 1527 } 1528 1529 void Assembler::cld() { 1530 emit_int8((unsigned char)0xFC); 1531 } 1532 1533 void Assembler::cmovl(Condition cc, Register dst, Register src) { 1534 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1535 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1536 emit_int8(0x0F); 1537 emit_int8(0x40 | cc); 1538 emit_int8((unsigned char)(0xC0 | encode)); 1539 } 1540 1541 1542 void Assembler::cmovl(Condition cc, Register dst, Address src) { 1543 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction")); 1544 prefix(src, dst); 1545 emit_int8(0x0F); 1546 emit_int8(0x40 | cc); 1547 emit_operand(dst, src); 1548 } 1549 1550 void Assembler::cmpb(Address dst, int imm8) { 1551 InstructionMark im(this); 1552 prefix(dst); 1553 emit_int8((unsigned char)0x80); 1554 emit_operand(rdi, dst, 1); 1555 emit_int8(imm8); 1556 } 1557 1558 void Assembler::cmpl(Address dst, int32_t imm32) { 1559 InstructionMark im(this); 1560 prefix(dst); 1561 emit_int8((unsigned char)0x81); 1562 emit_operand(rdi, dst, 4); 1563 emit_int32(imm32); 1564 } 1565 1566 void Assembler::cmpl(Register dst, int32_t imm32) { 1567 prefix(dst); 1568 emit_arith(0x81, 0xF8, dst, imm32); 1569 } 1570 1571 void Assembler::cmpl(Register dst, Register src) { 1572 (void) prefix_and_encode(dst->encoding(), src->encoding()); 1573 emit_arith(0x3B, 0xC0, dst, src); 1574 } 1575 1576 void Assembler::cmpl(Register dst, Address src) { 1577 InstructionMark im(this); 1578 prefix(src, dst); 1579 emit_int8((unsigned char)0x3B); 1580 emit_operand(dst, src); 1581 } 1582 1583 void Assembler::cmpw(Address dst, int imm16) { 1584 InstructionMark im(this); 1585 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers"); 1586 emit_int8(0x66); 1587 emit_int8((unsigned char)0x81); 1588 emit_operand(rdi, dst, 2); 1589 emit_int16(imm16); 1590 } 1591 1592 // The 32-bit cmpxchg compares the value at adr with the contents of rax, 1593 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1594 // The ZF is set if the compared values were equal, and cleared otherwise. 1595 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg 1596 InstructionMark im(this); 1597 prefix(adr, reg); 1598 emit_int8(0x0F); 1599 emit_int8((unsigned char)0xB1); 1600 emit_operand(reg, adr); 1601 } 1602 1603 // The 8-bit cmpxchg compares the value at adr with the contents of rax, 1604 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,. 1605 // The ZF is set if the compared values were equal, and cleared otherwise. 1606 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg 1607 InstructionMark im(this); 1608 prefix(adr, reg, true); 1609 emit_int8(0x0F); 1610 emit_int8((unsigned char)0xB0); 1611 emit_operand(reg, adr); 1612 } 1613 1614 void Assembler::comisd(XMMRegister dst, Address src) { 1615 // NOTE: dbx seems to decode this as comiss even though the 1616 // 0x66 is there. Strangly ucomisd comes out correct 1617 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1618 InstructionMark im(this); 1619 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);; 1620 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1621 attributes.set_rex_vex_w_reverted(); 1622 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1623 emit_int8(0x2F); 1624 emit_operand(dst, src); 1625 } 1626 1627 void Assembler::comisd(XMMRegister dst, XMMRegister src) { 1628 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1629 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1630 attributes.set_rex_vex_w_reverted(); 1631 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1632 emit_int8(0x2F); 1633 emit_int8((unsigned char)(0xC0 | encode)); 1634 } 1635 1636 void Assembler::comiss(XMMRegister dst, Address src) { 1637 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1638 InstructionMark im(this); 1639 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1640 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1641 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1642 emit_int8(0x2F); 1643 emit_operand(dst, src); 1644 } 1645 1646 void Assembler::comiss(XMMRegister dst, XMMRegister src) { 1647 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1649 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1650 emit_int8(0x2F); 1651 emit_int8((unsigned char)(0xC0 | encode)); 1652 } 1653 1654 void Assembler::cpuid() { 1655 emit_int8(0x0F); 1656 emit_int8((unsigned char)0xA2); 1657 } 1658 1659 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented 1660 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v 1661 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. - 1662 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. - 1663 // 1664 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v 1665 // 1666 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v 1667 // 1668 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v 1669 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) { 1670 assert(VM_Version::supports_sse4_2(), ""); 1671 int8_t w = 0x01; 1672 Prefix p = Prefix_EMPTY; 1673 1674 emit_int8((int8_t)0xF2); 1675 switch (sizeInBytes) { 1676 case 1: 1677 w = 0; 1678 break; 1679 case 2: 1680 case 4: 1681 break; 1682 LP64_ONLY(case 8:) 1683 // This instruction is not valid in 32 bits 1684 // Note: 1685 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf 1686 // 1687 // Page B - 72 Vol. 2C says 1688 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2 1689 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m 1690 // F0!!! 1691 // while 3 - 208 Vol. 2A 1692 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64. 1693 // 1694 // the 0 on a last bit is reserved for a different flavor of this instruction : 1695 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8. 1696 p = REX_W; 1697 break; 1698 default: 1699 assert(0, "Unsupported value for a sizeInBytes argument"); 1700 break; 1701 } 1702 LP64_ONLY(prefix(crc, v, p);) 1703 emit_int8((int8_t)0x0F); 1704 emit_int8(0x38); 1705 emit_int8((int8_t)(0xF0 | w)); 1706 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7)); 1707 } 1708 1709 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) { 1710 assert(VM_Version::supports_sse4_2(), ""); 1711 InstructionMark im(this); 1712 int8_t w = 0x01; 1713 Prefix p = Prefix_EMPTY; 1714 1715 emit_int8((int8_t)0xF2); 1716 switch (sizeInBytes) { 1717 case 1: 1718 w = 0; 1719 break; 1720 case 2: 1721 case 4: 1722 break; 1723 LP64_ONLY(case 8:) 1724 // This instruction is not valid in 32 bits 1725 p = REX_W; 1726 break; 1727 default: 1728 assert(0, "Unsupported value for a sizeInBytes argument"); 1729 break; 1730 } 1731 LP64_ONLY(prefix(crc, adr, p);) 1732 emit_int8((int8_t)0x0F); 1733 emit_int8(0x38); 1734 emit_int8((int8_t)(0xF0 | w)); 1735 emit_operand(crc, adr); 1736 } 1737 1738 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) { 1739 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1740 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1741 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1742 emit_int8((unsigned char)0xE6); 1743 emit_int8((unsigned char)(0xC0 | encode)); 1744 } 1745 1746 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) { 1747 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1748 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1749 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 1750 emit_int8(0x5B); 1751 emit_int8((unsigned char)(0xC0 | encode)); 1752 } 1753 1754 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) { 1755 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1756 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1757 attributes.set_rex_vex_w_reverted(); 1758 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1759 emit_int8(0x5A); 1760 emit_int8((unsigned char)(0xC0 | encode)); 1761 } 1762 1763 void Assembler::cvtsd2ss(XMMRegister dst, Address src) { 1764 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1765 InstructionMark im(this); 1766 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1767 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1768 attributes.set_rex_vex_w_reverted(); 1769 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1770 emit_int8(0x5A); 1771 emit_operand(dst, src); 1772 } 1773 1774 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) { 1775 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1776 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1777 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1778 emit_int8(0x2A); 1779 emit_int8((unsigned char)(0xC0 | encode)); 1780 } 1781 1782 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) { 1783 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1784 InstructionMark im(this); 1785 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1787 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1788 emit_int8(0x2A); 1789 emit_operand(dst, src); 1790 } 1791 1792 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) { 1793 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1794 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1795 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1796 emit_int8(0x2A); 1797 emit_int8((unsigned char)(0xC0 | encode)); 1798 } 1799 1800 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) { 1801 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1802 InstructionMark im(this); 1803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1804 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1805 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1806 emit_int8(0x2A); 1807 emit_operand(dst, src); 1808 } 1809 1810 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) { 1811 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1812 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1813 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1814 emit_int8(0x2A); 1815 emit_int8((unsigned char)(0xC0 | encode)); 1816 } 1817 1818 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) { 1819 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1820 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1821 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1822 emit_int8(0x5A); 1823 emit_int8((unsigned char)(0xC0 | encode)); 1824 } 1825 1826 void Assembler::cvtss2sd(XMMRegister dst, Address src) { 1827 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1828 InstructionMark im(this); 1829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1830 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1831 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1832 emit_int8(0x5A); 1833 emit_operand(dst, src); 1834 } 1835 1836 1837 void Assembler::cvttsd2sil(Register dst, XMMRegister src) { 1838 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1840 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1841 emit_int8(0x2C); 1842 emit_int8((unsigned char)(0xC0 | encode)); 1843 } 1844 1845 void Assembler::cvttss2sil(Register dst, XMMRegister src) { 1846 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1847 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 1848 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1849 emit_int8(0x2C); 1850 emit_int8((unsigned char)(0xC0 | encode)); 1851 } 1852 1853 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) { 1854 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1855 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 1856 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 1857 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 1858 emit_int8((unsigned char)0xE6); 1859 emit_int8((unsigned char)(0xC0 | encode)); 1860 } 1861 1862 void Assembler::decl(Address dst) { 1863 // Don't use it directly. Use MacroAssembler::decrement() instead. 1864 InstructionMark im(this); 1865 prefix(dst); 1866 emit_int8((unsigned char)0xFF); 1867 emit_operand(rcx, dst); 1868 } 1869 1870 void Assembler::divsd(XMMRegister dst, Address src) { 1871 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1872 InstructionMark im(this); 1873 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 1875 attributes.set_rex_vex_w_reverted(); 1876 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1877 emit_int8(0x5E); 1878 emit_operand(dst, src); 1879 } 1880 1881 void Assembler::divsd(XMMRegister dst, XMMRegister src) { 1882 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 1883 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1884 attributes.set_rex_vex_w_reverted(); 1885 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 1886 emit_int8(0x5E); 1887 emit_int8((unsigned char)(0xC0 | encode)); 1888 } 1889 1890 void Assembler::divss(XMMRegister dst, Address src) { 1891 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1892 InstructionMark im(this); 1893 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1894 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 1895 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1896 emit_int8(0x5E); 1897 emit_operand(dst, src); 1898 } 1899 1900 void Assembler::divss(XMMRegister dst, XMMRegister src) { 1901 NOT_LP64(assert(VM_Version::supports_sse(), "")); 1902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 1903 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 1904 emit_int8(0x5E); 1905 emit_int8((unsigned char)(0xC0 | encode)); 1906 } 1907 1908 void Assembler::emms() { 1909 NOT_LP64(assert(VM_Version::supports_mmx(), "")); 1910 emit_int8(0x0F); 1911 emit_int8(0x77); 1912 } 1913 1914 void Assembler::hlt() { 1915 emit_int8((unsigned char)0xF4); 1916 } 1917 1918 void Assembler::idivl(Register src) { 1919 int encode = prefix_and_encode(src->encoding()); 1920 emit_int8((unsigned char)0xF7); 1921 emit_int8((unsigned char)(0xF8 | encode)); 1922 } 1923 1924 void Assembler::divl(Register src) { // Unsigned 1925 int encode = prefix_and_encode(src->encoding()); 1926 emit_int8((unsigned char)0xF7); 1927 emit_int8((unsigned char)(0xF0 | encode)); 1928 } 1929 1930 void Assembler::imull(Register src) { 1931 int encode = prefix_and_encode(src->encoding()); 1932 emit_int8((unsigned char)0xF7); 1933 emit_int8((unsigned char)(0xE8 | encode)); 1934 } 1935 1936 void Assembler::imull(Register dst, Register src) { 1937 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1938 emit_int8(0x0F); 1939 emit_int8((unsigned char)0xAF); 1940 emit_int8((unsigned char)(0xC0 | encode)); 1941 } 1942 1943 1944 void Assembler::imull(Register dst, Register src, int value) { 1945 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 1946 if (is8bit(value)) { 1947 emit_int8(0x6B); 1948 emit_int8((unsigned char)(0xC0 | encode)); 1949 emit_int8(value & 0xFF); 1950 } else { 1951 emit_int8(0x69); 1952 emit_int8((unsigned char)(0xC0 | encode)); 1953 emit_int32(value); 1954 } 1955 } 1956 1957 void Assembler::imull(Register dst, Address src) { 1958 InstructionMark im(this); 1959 prefix(src, dst); 1960 emit_int8(0x0F); 1961 emit_int8((unsigned char) 0xAF); 1962 emit_operand(dst, src); 1963 } 1964 1965 1966 void Assembler::incl(Address dst) { 1967 // Don't use it directly. Use MacroAssembler::increment() instead. 1968 InstructionMark im(this); 1969 prefix(dst); 1970 emit_int8((unsigned char)0xFF); 1971 emit_operand(rax, dst); 1972 } 1973 1974 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) { 1975 InstructionMark im(this); 1976 assert((0 <= cc) && (cc < 16), "illegal cc"); 1977 if (L.is_bound()) { 1978 address dst = target(L); 1979 assert(dst != NULL, "jcc most probably wrong"); 1980 1981 const int short_size = 2; 1982 const int long_size = 6; 1983 intptr_t offs = (intptr_t)dst - (intptr_t)pc(); 1984 if (maybe_short && is8bit(offs - short_size)) { 1985 // 0111 tttn #8-bit disp 1986 emit_int8(0x70 | cc); 1987 emit_int8((offs - short_size) & 0xFF); 1988 } else { 1989 // 0000 1111 1000 tttn #32-bit disp 1990 assert(is_simm32(offs - long_size), 1991 "must be 32bit offset (call4)"); 1992 emit_int8(0x0F); 1993 emit_int8((unsigned char)(0x80 | cc)); 1994 emit_int32(offs - long_size); 1995 } 1996 } else { 1997 // Note: could eliminate cond. jumps to this jump if condition 1998 // is the same however, seems to be rather unlikely case. 1999 // Note: use jccb() if label to be bound is very close to get 2000 // an 8-bit displacement 2001 L.add_patch_at(code(), locator()); 2002 emit_int8(0x0F); 2003 emit_int8((unsigned char)(0x80 | cc)); 2004 emit_int32(0); 2005 } 2006 } 2007 2008 void Assembler::jccb(Condition cc, Label& L) { 2009 if (L.is_bound()) { 2010 const int short_size = 2; 2011 address entry = target(L); 2012 #ifdef ASSERT 2013 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2014 intptr_t delta = short_branch_delta(); 2015 if (delta != 0) { 2016 dist += (dist < 0 ? (-delta) :delta); 2017 } 2018 assert(is8bit(dist), "Dispacement too large for a short jmp"); 2019 #endif 2020 intptr_t offs = (intptr_t)entry - (intptr_t)pc(); 2021 // 0111 tttn #8-bit disp 2022 emit_int8(0x70 | cc); 2023 emit_int8((offs - short_size) & 0xFF); 2024 } else { 2025 InstructionMark im(this); 2026 L.add_patch_at(code(), locator()); 2027 emit_int8(0x70 | cc); 2028 emit_int8(0); 2029 } 2030 } 2031 2032 void Assembler::jmp(Address adr) { 2033 InstructionMark im(this); 2034 prefix(adr); 2035 emit_int8((unsigned char)0xFF); 2036 emit_operand(rsp, adr); 2037 } 2038 2039 void Assembler::jmp(Label& L, bool maybe_short) { 2040 if (L.is_bound()) { 2041 address entry = target(L); 2042 assert(entry != NULL, "jmp most probably wrong"); 2043 InstructionMark im(this); 2044 const int short_size = 2; 2045 const int long_size = 5; 2046 intptr_t offs = entry - pc(); 2047 if (maybe_short && is8bit(offs - short_size)) { 2048 emit_int8((unsigned char)0xEB); 2049 emit_int8((offs - short_size) & 0xFF); 2050 } else { 2051 emit_int8((unsigned char)0xE9); 2052 emit_int32(offs - long_size); 2053 } 2054 } else { 2055 // By default, forward jumps are always 32-bit displacements, since 2056 // we can't yet know where the label will be bound. If you're sure that 2057 // the forward jump will not run beyond 256 bytes, use jmpb to 2058 // force an 8-bit displacement. 2059 InstructionMark im(this); 2060 L.add_patch_at(code(), locator()); 2061 emit_int8((unsigned char)0xE9); 2062 emit_int32(0); 2063 } 2064 } 2065 2066 void Assembler::jmp(Register entry) { 2067 int encode = prefix_and_encode(entry->encoding()); 2068 emit_int8((unsigned char)0xFF); 2069 emit_int8((unsigned char)(0xE0 | encode)); 2070 } 2071 2072 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) { 2073 InstructionMark im(this); 2074 emit_int8((unsigned char)0xE9); 2075 assert(dest != NULL, "must have a target"); 2076 intptr_t disp = dest - (pc() + sizeof(int32_t)); 2077 assert(is_simm32(disp), "must be 32bit offset (jmp)"); 2078 emit_data(disp, rspec.reloc(), call32_operand); 2079 } 2080 2081 void Assembler::jmpb(Label& L) { 2082 if (L.is_bound()) { 2083 const int short_size = 2; 2084 address entry = target(L); 2085 assert(entry != NULL, "jmp most probably wrong"); 2086 #ifdef ASSERT 2087 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size); 2088 intptr_t delta = short_branch_delta(); 2089 if (delta != 0) { 2090 dist += (dist < 0 ? (-delta) :delta); 2091 } 2092 assert(is8bit(dist), "Dispacement too large for a short jmp"); 2093 #endif 2094 intptr_t offs = entry - pc(); 2095 emit_int8((unsigned char)0xEB); 2096 emit_int8((offs - short_size) & 0xFF); 2097 } else { 2098 InstructionMark im(this); 2099 L.add_patch_at(code(), locator()); 2100 emit_int8((unsigned char)0xEB); 2101 emit_int8(0); 2102 } 2103 } 2104 2105 void Assembler::ldmxcsr( Address src) { 2106 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2107 InstructionMark im(this); 2108 prefix(src); 2109 emit_int8(0x0F); 2110 emit_int8((unsigned char)0xAE); 2111 emit_operand(as_Register(2), src); 2112 } 2113 2114 void Assembler::leal(Register dst, Address src) { 2115 InstructionMark im(this); 2116 #ifdef _LP64 2117 emit_int8(0x67); // addr32 2118 prefix(src, dst); 2119 #endif // LP64 2120 emit_int8((unsigned char)0x8D); 2121 emit_operand(dst, src); 2122 } 2123 2124 void Assembler::lfence() { 2125 emit_int8(0x0F); 2126 emit_int8((unsigned char)0xAE); 2127 emit_int8((unsigned char)0xE8); 2128 } 2129 2130 void Assembler::lock() { 2131 emit_int8((unsigned char)0xF0); 2132 } 2133 2134 void Assembler::lzcntl(Register dst, Register src) { 2135 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 2136 emit_int8((unsigned char)0xF3); 2137 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2138 emit_int8(0x0F); 2139 emit_int8((unsigned char)0xBD); 2140 emit_int8((unsigned char)(0xC0 | encode)); 2141 } 2142 2143 // Emit mfence instruction 2144 void Assembler::mfence() { 2145 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");) 2146 emit_int8(0x0F); 2147 emit_int8((unsigned char)0xAE); 2148 emit_int8((unsigned char)0xF0); 2149 } 2150 2151 void Assembler::mov(Register dst, Register src) { 2152 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2153 } 2154 2155 void Assembler::movapd(XMMRegister dst, XMMRegister src) { 2156 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2157 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2158 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2159 attributes.set_rex_vex_w_reverted(); 2160 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2161 emit_int8(0x28); 2162 emit_int8((unsigned char)(0xC0 | encode)); 2163 } 2164 2165 void Assembler::movaps(XMMRegister dst, XMMRegister src) { 2166 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2167 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2168 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2169 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2170 emit_int8(0x28); 2171 emit_int8((unsigned char)(0xC0 | encode)); 2172 } 2173 2174 void Assembler::movlhps(XMMRegister dst, XMMRegister src) { 2175 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2176 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2177 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2178 emit_int8(0x16); 2179 emit_int8((unsigned char)(0xC0 | encode)); 2180 } 2181 2182 void Assembler::movb(Register dst, Address src) { 2183 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 2184 InstructionMark im(this); 2185 prefix(src, dst, true); 2186 emit_int8((unsigned char)0x8A); 2187 emit_operand(dst, src); 2188 } 2189 2190 void Assembler::movddup(XMMRegister dst, XMMRegister src) { 2191 NOT_LP64(assert(VM_Version::supports_sse3(), "")); 2192 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2193 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2194 attributes.set_rex_vex_w_reverted(); 2195 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2196 emit_int8(0x12); 2197 emit_int8(0xC0 | encode); 2198 } 2199 2200 void Assembler::kmovbl(KRegister dst, Register src) { 2201 assert(VM_Version::supports_avx512dq(), ""); 2202 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2203 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2204 emit_int8((unsigned char)0x92); 2205 emit_int8((unsigned char)(0xC0 | encode)); 2206 } 2207 2208 void Assembler::kmovbl(Register dst, KRegister src) { 2209 assert(VM_Version::supports_avx512dq(), ""); 2210 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2211 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2212 emit_int8((unsigned char)0x93); 2213 emit_int8((unsigned char)(0xC0 | encode)); 2214 } 2215 2216 void Assembler::kmovwl(KRegister dst, Register src) { 2217 assert(VM_Version::supports_evex(), ""); 2218 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2219 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2220 emit_int8((unsigned char)0x92); 2221 emit_int8((unsigned char)(0xC0 | encode)); 2222 } 2223 2224 void Assembler::kmovwl(Register dst, KRegister src) { 2225 assert(VM_Version::supports_evex(), ""); 2226 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2228 emit_int8((unsigned char)0x93); 2229 emit_int8((unsigned char)(0xC0 | encode)); 2230 } 2231 2232 void Assembler::kmovwl(KRegister dst, Address src) { 2233 assert(VM_Version::supports_evex(), ""); 2234 InstructionMark im(this); 2235 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2236 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2237 emit_int8((unsigned char)0x90); 2238 emit_operand((Register)dst, src); 2239 } 2240 2241 void Assembler::kmovdl(KRegister dst, Register src) { 2242 assert(VM_Version::supports_avx512bw(), ""); 2243 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2244 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2245 emit_int8((unsigned char)0x92); 2246 emit_int8((unsigned char)(0xC0 | encode)); 2247 } 2248 2249 void Assembler::kmovdl(Register dst, KRegister src) { 2250 assert(VM_Version::supports_avx512bw(), ""); 2251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2252 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2253 emit_int8((unsigned char)0x93); 2254 emit_int8((unsigned char)(0xC0 | encode)); 2255 } 2256 2257 void Assembler::kmovql(KRegister dst, KRegister src) { 2258 assert(VM_Version::supports_avx512bw(), ""); 2259 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2260 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2261 emit_int8((unsigned char)0x90); 2262 emit_int8((unsigned char)(0xC0 | encode)); 2263 } 2264 2265 void Assembler::kmovql(KRegister dst, Address src) { 2266 assert(VM_Version::supports_avx512bw(), ""); 2267 InstructionMark im(this); 2268 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2269 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2270 emit_int8((unsigned char)0x90); 2271 emit_operand((Register)dst, src); 2272 } 2273 2274 void Assembler::kmovql(Address dst, KRegister src) { 2275 assert(VM_Version::supports_avx512bw(), ""); 2276 InstructionMark im(this); 2277 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2278 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2279 emit_int8((unsigned char)0x90); 2280 emit_operand((Register)src, dst); 2281 } 2282 2283 void Assembler::kmovql(KRegister dst, Register src) { 2284 assert(VM_Version::supports_avx512bw(), ""); 2285 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2286 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2287 emit_int8((unsigned char)0x92); 2288 emit_int8((unsigned char)(0xC0 | encode)); 2289 } 2290 2291 void Assembler::kmovql(Register dst, KRegister src) { 2292 assert(VM_Version::supports_avx512bw(), ""); 2293 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2294 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2295 emit_int8((unsigned char)0x93); 2296 emit_int8((unsigned char)(0xC0 | encode)); 2297 } 2298 2299 void Assembler::knotwl(KRegister dst, KRegister src) { 2300 assert(VM_Version::supports_evex(), ""); 2301 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2302 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2303 emit_int8((unsigned char)0x44); 2304 emit_int8((unsigned char)(0xC0 | encode)); 2305 } 2306 2307 // This instruction produces ZF or CF flags 2308 void Assembler::kortestbl(KRegister src1, KRegister src2) { 2309 assert(VM_Version::supports_avx512dq(), ""); 2310 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2311 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2312 emit_int8((unsigned char)0x98); 2313 emit_int8((unsigned char)(0xC0 | encode)); 2314 } 2315 2316 // This instruction produces ZF or CF flags 2317 void Assembler::kortestwl(KRegister src1, KRegister src2) { 2318 assert(VM_Version::supports_evex(), ""); 2319 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2320 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2321 emit_int8((unsigned char)0x98); 2322 emit_int8((unsigned char)(0xC0 | encode)); 2323 } 2324 2325 // This instruction produces ZF or CF flags 2326 void Assembler::kortestdl(KRegister src1, KRegister src2) { 2327 assert(VM_Version::supports_avx512bw(), ""); 2328 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2329 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2330 emit_int8((unsigned char)0x98); 2331 emit_int8((unsigned char)(0xC0 | encode)); 2332 } 2333 2334 // This instruction produces ZF or CF flags 2335 void Assembler::kortestql(KRegister src1, KRegister src2) { 2336 assert(VM_Version::supports_avx512bw(), ""); 2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2338 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2339 emit_int8((unsigned char)0x98); 2340 emit_int8((unsigned char)(0xC0 | encode)); 2341 } 2342 2343 // This instruction produces ZF or CF flags 2344 void Assembler::ktestql(KRegister src1, KRegister src2) { 2345 assert(VM_Version::supports_avx512bw(), ""); 2346 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2347 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2348 emit_int8((unsigned char)0x99); 2349 emit_int8((unsigned char)(0xC0 | encode)); 2350 } 2351 2352 void Assembler::ktestq(KRegister src1, KRegister src2) { 2353 assert(VM_Version::supports_avx512bw(), ""); 2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2355 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 2356 emit_int8((unsigned char)0x99); 2357 emit_int8((unsigned char)(0xC0 | encode)); 2358 } 2359 2360 void Assembler::ktestd(KRegister src1, KRegister src2) { 2361 assert(VM_Version::supports_avx512bw(), ""); 2362 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false); 2363 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2364 emit_int8((unsigned char)0x99); 2365 emit_int8((unsigned char)(0xC0 | encode)); 2366 } 2367 2368 void Assembler::movb(Address dst, int imm8) { 2369 InstructionMark im(this); 2370 prefix(dst); 2371 emit_int8((unsigned char)0xC6); 2372 emit_operand(rax, dst, 1); 2373 emit_int8(imm8); 2374 } 2375 2376 2377 void Assembler::movb(Address dst, Register src) { 2378 assert(src->has_byte_register(), "must have byte register"); 2379 InstructionMark im(this); 2380 prefix(dst, src, true); 2381 emit_int8((unsigned char)0x88); 2382 emit_operand(src, dst); 2383 } 2384 2385 void Assembler::movdl(XMMRegister dst, Register src) { 2386 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2387 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2388 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2389 emit_int8(0x6E); 2390 emit_int8((unsigned char)(0xC0 | encode)); 2391 } 2392 2393 void Assembler::movdl(Register dst, XMMRegister src) { 2394 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2396 // swap src/dst to get correct prefix 2397 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2398 emit_int8(0x7E); 2399 emit_int8((unsigned char)(0xC0 | encode)); 2400 } 2401 2402 void Assembler::movdl(XMMRegister dst, Address src) { 2403 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2404 InstructionMark im(this); 2405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2406 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2407 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2408 emit_int8(0x6E); 2409 emit_operand(dst, src); 2410 } 2411 2412 void Assembler::movdl(Address dst, XMMRegister src) { 2413 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2414 InstructionMark im(this); 2415 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2416 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2417 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2418 emit_int8(0x7E); 2419 emit_operand(src, dst); 2420 } 2421 2422 void Assembler::movdqa(XMMRegister dst, XMMRegister src) { 2423 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2424 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 2425 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2426 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2427 emit_int8(0x6F); 2428 emit_int8((unsigned char)(0xC0 | encode)); 2429 } 2430 2431 void Assembler::movdqa(XMMRegister dst, Address src) { 2432 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2433 InstructionMark im(this); 2434 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2435 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2436 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2437 emit_int8(0x6F); 2438 emit_operand(dst, src); 2439 } 2440 2441 void Assembler::movdqu(XMMRegister dst, Address src) { 2442 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2443 InstructionMark im(this); 2444 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2445 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2446 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2447 emit_int8(0x6F); 2448 emit_operand(dst, src); 2449 } 2450 2451 void Assembler::movdqu(XMMRegister dst, XMMRegister src) { 2452 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2454 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2455 emit_int8(0x6F); 2456 emit_int8((unsigned char)(0xC0 | encode)); 2457 } 2458 2459 void Assembler::movdqu(Address dst, XMMRegister src) { 2460 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2461 InstructionMark im(this); 2462 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2463 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2464 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2465 emit_int8(0x7F); 2466 emit_operand(src, dst); 2467 } 2468 2469 // Move Unaligned 256bit Vector 2470 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2471 assert(UseAVX > 0, ""); 2472 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2473 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2474 emit_int8(0x6F); 2475 emit_int8((unsigned char)(0xC0 | encode)); 2476 } 2477 2478 void Assembler::vmovdqu(XMMRegister dst, Address src) { 2479 assert(UseAVX > 0, ""); 2480 InstructionMark im(this); 2481 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2482 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2483 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2484 emit_int8(0x6F); 2485 emit_operand(dst, src); 2486 } 2487 2488 void Assembler::vmovdqu(Address dst, XMMRegister src) { 2489 assert(UseAVX > 0, ""); 2490 InstructionMark im(this); 2491 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2492 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2493 // swap src<->dst for encoding 2494 assert(src != xnoreg, "sanity"); 2495 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2496 emit_int8(0x7F); 2497 emit_operand(src, dst); 2498 } 2499 2500 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64) 2501 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { 2502 assert(VM_Version::supports_evex(), ""); 2503 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2504 attributes.set_is_evex_instruction(); 2505 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2506 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2507 emit_int8(0x6F); 2508 emit_int8((unsigned char)(0xC0 | encode)); 2509 } 2510 2511 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) { 2512 assert(VM_Version::supports_evex(), ""); 2513 InstructionMark im(this); 2514 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2515 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2516 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2517 attributes.set_is_evex_instruction(); 2518 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2519 emit_int8(0x6F); 2520 emit_operand(dst, src); 2521 } 2522 2523 void Assembler::evmovdqub(Address dst, XMMRegister src, int vector_len) { 2524 assert(VM_Version::supports_evex(), ""); 2525 assert(src != xnoreg, "sanity"); 2526 InstructionMark im(this); 2527 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2528 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2529 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2530 attributes.set_is_evex_instruction(); 2531 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2532 emit_int8(0x7F); 2533 emit_operand(src, dst); 2534 } 2535 2536 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2537 assert(VM_Version::supports_avx512vlbw(), ""); 2538 assert(is_vector_masking(), ""); // For stub code use only 2539 InstructionMark im(this); 2540 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 2541 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2542 attributes.set_embedded_opmask_register_specifier(mask); 2543 attributes.set_is_evex_instruction(); 2544 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2545 emit_int8(0x6F); 2546 emit_operand(dst, src); 2547 } 2548 2549 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) { 2550 assert(VM_Version::supports_evex(), ""); 2551 InstructionMark im(this); 2552 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2553 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2554 attributes.set_is_evex_instruction(); 2555 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2556 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2557 emit_int8(0x6F); 2558 emit_operand(dst, src); 2559 } 2560 2561 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 2562 assert(is_vector_masking(), ""); 2563 assert(VM_Version::supports_avx512vlbw(), ""); 2564 InstructionMark im(this); 2565 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 2566 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2567 attributes.set_embedded_opmask_register_specifier(mask); 2568 attributes.set_is_evex_instruction(); 2569 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2570 emit_int8(0x6F); 2571 emit_operand(dst, src); 2572 } 2573 2574 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) { 2575 assert(VM_Version::supports_evex(), ""); 2576 assert(src != xnoreg, "sanity"); 2577 InstructionMark im(this); 2578 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 2579 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2580 attributes.set_is_evex_instruction(); 2581 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3; 2582 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes); 2583 emit_int8(0x7F); 2584 emit_operand(src, dst); 2585 } 2586 2587 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, int vector_len) { 2588 assert(VM_Version::supports_avx512vlbw(), ""); 2589 assert(src != xnoreg, "sanity"); 2590 InstructionMark im(this); 2591 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2592 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2593 attributes.set_embedded_opmask_register_specifier(mask); 2594 attributes.set_is_evex_instruction(); 2595 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2596 emit_int8(0x7F); 2597 emit_operand(src, dst); 2598 } 2599 2600 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) { 2601 assert(VM_Version::supports_evex(), ""); 2602 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2603 attributes.set_is_evex_instruction(); 2604 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2605 emit_int8(0x6F); 2606 emit_int8((unsigned char)(0xC0 | encode)); 2607 } 2608 2609 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) { 2610 assert(VM_Version::supports_evex(), ""); 2611 InstructionMark im(this); 2612 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true); 2613 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2614 attributes.set_is_evex_instruction(); 2615 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2616 emit_int8(0x6F); 2617 emit_operand(dst, src); 2618 } 2619 2620 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) { 2621 assert(VM_Version::supports_evex(), ""); 2622 assert(src != xnoreg, "sanity"); 2623 InstructionMark im(this); 2624 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2625 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2626 attributes.set_is_evex_instruction(); 2627 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2628 emit_int8(0x7F); 2629 emit_operand(src, dst); 2630 } 2631 2632 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { 2633 assert(VM_Version::supports_evex(), ""); 2634 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2635 attributes.set_is_evex_instruction(); 2636 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2637 emit_int8(0x6F); 2638 emit_int8((unsigned char)(0xC0 | encode)); 2639 } 2640 2641 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) { 2642 assert(VM_Version::supports_evex(), ""); 2643 InstructionMark im(this); 2644 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2645 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2646 attributes.set_is_evex_instruction(); 2647 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2648 emit_int8(0x6F); 2649 emit_operand(dst, src); 2650 } 2651 2652 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) { 2653 assert(VM_Version::supports_evex(), ""); 2654 assert(src != xnoreg, "sanity"); 2655 InstructionMark im(this); 2656 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 2657 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 2658 attributes.set_is_evex_instruction(); 2659 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2660 emit_int8(0x7F); 2661 emit_operand(src, dst); 2662 } 2663 2664 // Uses zero extension on 64bit 2665 2666 void Assembler::movl(Register dst, int32_t imm32) { 2667 int encode = prefix_and_encode(dst->encoding()); 2668 emit_int8((unsigned char)(0xB8 | encode)); 2669 emit_int32(imm32); 2670 } 2671 2672 void Assembler::movl(Register dst, Register src) { 2673 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2674 emit_int8((unsigned char)0x8B); 2675 emit_int8((unsigned char)(0xC0 | encode)); 2676 } 2677 2678 void Assembler::movl(Register dst, Address src) { 2679 InstructionMark im(this); 2680 prefix(src, dst); 2681 emit_int8((unsigned char)0x8B); 2682 emit_operand(dst, src); 2683 } 2684 2685 void Assembler::movl(Address dst, int32_t imm32) { 2686 InstructionMark im(this); 2687 prefix(dst); 2688 emit_int8((unsigned char)0xC7); 2689 emit_operand(rax, dst, 4); 2690 emit_int32(imm32); 2691 } 2692 2693 void Assembler::movl(Address dst, Register src) { 2694 InstructionMark im(this); 2695 prefix(dst, src); 2696 emit_int8((unsigned char)0x89); 2697 emit_operand(src, dst); 2698 } 2699 2700 // New cpus require to use movsd and movss to avoid partial register stall 2701 // when loading from memory. But for old Opteron use movlpd instead of movsd. 2702 // The selection is done in MacroAssembler::movdbl() and movflt(). 2703 void Assembler::movlpd(XMMRegister dst, Address src) { 2704 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2705 InstructionMark im(this); 2706 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2707 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2708 attributes.set_rex_vex_w_reverted(); 2709 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2710 emit_int8(0x12); 2711 emit_operand(dst, src); 2712 } 2713 2714 void Assembler::movq( MMXRegister dst, Address src ) { 2715 assert( VM_Version::supports_mmx(), "" ); 2716 emit_int8(0x0F); 2717 emit_int8(0x6F); 2718 emit_operand(dst, src); 2719 } 2720 2721 void Assembler::movq( Address dst, MMXRegister src ) { 2722 assert( VM_Version::supports_mmx(), "" ); 2723 emit_int8(0x0F); 2724 emit_int8(0x7F); 2725 // workaround gcc (3.2.1-7a) bug 2726 // In that version of gcc with only an emit_operand(MMX, Address) 2727 // gcc will tail jump and try and reverse the parameters completely 2728 // obliterating dst in the process. By having a version available 2729 // that doesn't need to swap the args at the tail jump the bug is 2730 // avoided. 2731 emit_operand(dst, src); 2732 } 2733 2734 void Assembler::movq(XMMRegister dst, Address src) { 2735 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2736 InstructionMark im(this); 2737 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2738 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2739 attributes.set_rex_vex_w_reverted(); 2740 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2741 emit_int8(0x7E); 2742 emit_operand(dst, src); 2743 } 2744 2745 void Assembler::movq(Address dst, XMMRegister src) { 2746 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2747 InstructionMark im(this); 2748 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 2749 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2750 attributes.set_rex_vex_w_reverted(); 2751 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 2752 emit_int8((unsigned char)0xD6); 2753 emit_operand(src, dst); 2754 } 2755 2756 void Assembler::movsbl(Register dst, Address src) { // movsxb 2757 InstructionMark im(this); 2758 prefix(src, dst); 2759 emit_int8(0x0F); 2760 emit_int8((unsigned char)0xBE); 2761 emit_operand(dst, src); 2762 } 2763 2764 void Assembler::movsbl(Register dst, Register src) { // movsxb 2765 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2766 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2767 emit_int8(0x0F); 2768 emit_int8((unsigned char)0xBE); 2769 emit_int8((unsigned char)(0xC0 | encode)); 2770 } 2771 2772 void Assembler::movsd(XMMRegister dst, XMMRegister src) { 2773 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2774 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2775 attributes.set_rex_vex_w_reverted(); 2776 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2777 emit_int8(0x10); 2778 emit_int8((unsigned char)(0xC0 | encode)); 2779 } 2780 2781 void Assembler::movsd(XMMRegister dst, Address src) { 2782 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2783 InstructionMark im(this); 2784 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2785 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2786 attributes.set_rex_vex_w_reverted(); 2787 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2788 emit_int8(0x10); 2789 emit_operand(dst, src); 2790 } 2791 2792 void Assembler::movsd(Address dst, XMMRegister src) { 2793 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2794 InstructionMark im(this); 2795 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2796 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2797 attributes.set_rex_vex_w_reverted(); 2798 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2799 emit_int8(0x11); 2800 emit_operand(src, dst); 2801 } 2802 2803 void Assembler::movss(XMMRegister dst, XMMRegister src) { 2804 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2805 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2806 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2807 emit_int8(0x10); 2808 emit_int8((unsigned char)(0xC0 | encode)); 2809 } 2810 2811 void Assembler::movss(XMMRegister dst, Address src) { 2812 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2813 InstructionMark im(this); 2814 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2815 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2816 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2817 emit_int8(0x10); 2818 emit_operand(dst, src); 2819 } 2820 2821 void Assembler::movss(Address dst, XMMRegister src) { 2822 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2823 InstructionMark im(this); 2824 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2825 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2826 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2827 emit_int8(0x11); 2828 emit_operand(src, dst); 2829 } 2830 2831 void Assembler::movswl(Register dst, Address src) { // movsxw 2832 InstructionMark im(this); 2833 prefix(src, dst); 2834 emit_int8(0x0F); 2835 emit_int8((unsigned char)0xBF); 2836 emit_operand(dst, src); 2837 } 2838 2839 void Assembler::movswl(Register dst, Register src) { // movsxw 2840 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2841 emit_int8(0x0F); 2842 emit_int8((unsigned char)0xBF); 2843 emit_int8((unsigned char)(0xC0 | encode)); 2844 } 2845 2846 void Assembler::movw(Address dst, int imm16) { 2847 InstructionMark im(this); 2848 2849 emit_int8(0x66); // switch to 16-bit mode 2850 prefix(dst); 2851 emit_int8((unsigned char)0xC7); 2852 emit_operand(rax, dst, 2); 2853 emit_int16(imm16); 2854 } 2855 2856 void Assembler::movw(Register dst, Address src) { 2857 InstructionMark im(this); 2858 emit_int8(0x66); 2859 prefix(src, dst); 2860 emit_int8((unsigned char)0x8B); 2861 emit_operand(dst, src); 2862 } 2863 2864 void Assembler::movw(Address dst, Register src) { 2865 InstructionMark im(this); 2866 emit_int8(0x66); 2867 prefix(dst, src); 2868 emit_int8((unsigned char)0x89); 2869 emit_operand(src, dst); 2870 } 2871 2872 void Assembler::movzbl(Register dst, Address src) { // movzxb 2873 InstructionMark im(this); 2874 prefix(src, dst); 2875 emit_int8(0x0F); 2876 emit_int8((unsigned char)0xB6); 2877 emit_operand(dst, src); 2878 } 2879 2880 void Assembler::movzbl(Register dst, Register src) { // movzxb 2881 NOT_LP64(assert(src->has_byte_register(), "must have byte register")); 2882 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true); 2883 emit_int8(0x0F); 2884 emit_int8((unsigned char)0xB6); 2885 emit_int8(0xC0 | encode); 2886 } 2887 2888 void Assembler::movzwl(Register dst, Address src) { // movzxw 2889 InstructionMark im(this); 2890 prefix(src, dst); 2891 emit_int8(0x0F); 2892 emit_int8((unsigned char)0xB7); 2893 emit_operand(dst, src); 2894 } 2895 2896 void Assembler::movzwl(Register dst, Register src) { // movzxw 2897 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 2898 emit_int8(0x0F); 2899 emit_int8((unsigned char)0xB7); 2900 emit_int8(0xC0 | encode); 2901 } 2902 2903 void Assembler::mull(Address src) { 2904 InstructionMark im(this); 2905 prefix(src); 2906 emit_int8((unsigned char)0xF7); 2907 emit_operand(rsp, src); 2908 } 2909 2910 void Assembler::mull(Register src) { 2911 int encode = prefix_and_encode(src->encoding()); 2912 emit_int8((unsigned char)0xF7); 2913 emit_int8((unsigned char)(0xE0 | encode)); 2914 } 2915 2916 void Assembler::mulsd(XMMRegister dst, Address src) { 2917 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2918 InstructionMark im(this); 2919 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2920 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 2921 attributes.set_rex_vex_w_reverted(); 2922 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2923 emit_int8(0x59); 2924 emit_operand(dst, src); 2925 } 2926 2927 void Assembler::mulsd(XMMRegister dst, XMMRegister src) { 2928 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 2929 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2930 attributes.set_rex_vex_w_reverted(); 2931 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 2932 emit_int8(0x59); 2933 emit_int8((unsigned char)(0xC0 | encode)); 2934 } 2935 2936 void Assembler::mulss(XMMRegister dst, Address src) { 2937 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2938 InstructionMark im(this); 2939 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2940 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 2941 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2942 emit_int8(0x59); 2943 emit_operand(dst, src); 2944 } 2945 2946 void Assembler::mulss(XMMRegister dst, XMMRegister src) { 2947 NOT_LP64(assert(VM_Version::supports_sse(), "")); 2948 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 2949 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 2950 emit_int8(0x59); 2951 emit_int8((unsigned char)(0xC0 | encode)); 2952 } 2953 2954 void Assembler::negl(Register dst) { 2955 int encode = prefix_and_encode(dst->encoding()); 2956 emit_int8((unsigned char)0xF7); 2957 emit_int8((unsigned char)(0xD8 | encode)); 2958 } 2959 2960 void Assembler::nop(int i) { 2961 #ifdef ASSERT 2962 assert(i > 0, " "); 2963 // The fancy nops aren't currently recognized by debuggers making it a 2964 // pain to disassemble code while debugging. If asserts are on clearly 2965 // speed is not an issue so simply use the single byte traditional nop 2966 // to do alignment. 2967 2968 for (; i > 0 ; i--) emit_int8((unsigned char)0x90); 2969 return; 2970 2971 #endif // ASSERT 2972 2973 if (UseAddressNop && VM_Version::is_intel()) { 2974 // 2975 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel 2976 // 1: 0x90 2977 // 2: 0x66 0x90 2978 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 2979 // 4: 0x0F 0x1F 0x40 0x00 2980 // 5: 0x0F 0x1F 0x44 0x00 0x00 2981 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 2982 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 2983 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2984 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2985 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2986 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 2987 2988 // The rest coding is Intel specific - don't use consecutive address nops 2989 2990 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2991 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2992 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2993 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90 2994 2995 while(i >= 15) { 2996 // For Intel don't generate consecutive addess nops (mix with regular nops) 2997 i -= 15; 2998 emit_int8(0x66); // size prefix 2999 emit_int8(0x66); // size prefix 3000 emit_int8(0x66); // size prefix 3001 addr_nop_8(); 3002 emit_int8(0x66); // size prefix 3003 emit_int8(0x66); // size prefix 3004 emit_int8(0x66); // size prefix 3005 emit_int8((unsigned char)0x90); 3006 // nop 3007 } 3008 switch (i) { 3009 case 14: 3010 emit_int8(0x66); // size prefix 3011 case 13: 3012 emit_int8(0x66); // size prefix 3013 case 12: 3014 addr_nop_8(); 3015 emit_int8(0x66); // size prefix 3016 emit_int8(0x66); // size prefix 3017 emit_int8(0x66); // size prefix 3018 emit_int8((unsigned char)0x90); 3019 // nop 3020 break; 3021 case 11: 3022 emit_int8(0x66); // size prefix 3023 case 10: 3024 emit_int8(0x66); // size prefix 3025 case 9: 3026 emit_int8(0x66); // size prefix 3027 case 8: 3028 addr_nop_8(); 3029 break; 3030 case 7: 3031 addr_nop_7(); 3032 break; 3033 case 6: 3034 emit_int8(0x66); // size prefix 3035 case 5: 3036 addr_nop_5(); 3037 break; 3038 case 4: 3039 addr_nop_4(); 3040 break; 3041 case 3: 3042 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3043 emit_int8(0x66); // size prefix 3044 case 2: 3045 emit_int8(0x66); // size prefix 3046 case 1: 3047 emit_int8((unsigned char)0x90); 3048 // nop 3049 break; 3050 default: 3051 assert(i == 0, " "); 3052 } 3053 return; 3054 } 3055 if (UseAddressNop && VM_Version::is_amd()) { 3056 // 3057 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD. 3058 // 1: 0x90 3059 // 2: 0x66 0x90 3060 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding) 3061 // 4: 0x0F 0x1F 0x40 0x00 3062 // 5: 0x0F 0x1F 0x44 0x00 0x00 3063 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00 3064 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3065 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3066 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3067 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3068 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3069 3070 // The rest coding is AMD specific - use consecutive address nops 3071 3072 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3073 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00 3074 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3075 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 3076 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 3077 // Size prefixes (0x66) are added for larger sizes 3078 3079 while(i >= 22) { 3080 i -= 11; 3081 emit_int8(0x66); // size prefix 3082 emit_int8(0x66); // size prefix 3083 emit_int8(0x66); // size prefix 3084 addr_nop_8(); 3085 } 3086 // Generate first nop for size between 21-12 3087 switch (i) { 3088 case 21: 3089 i -= 1; 3090 emit_int8(0x66); // size prefix 3091 case 20: 3092 case 19: 3093 i -= 1; 3094 emit_int8(0x66); // size prefix 3095 case 18: 3096 case 17: 3097 i -= 1; 3098 emit_int8(0x66); // size prefix 3099 case 16: 3100 case 15: 3101 i -= 8; 3102 addr_nop_8(); 3103 break; 3104 case 14: 3105 case 13: 3106 i -= 7; 3107 addr_nop_7(); 3108 break; 3109 case 12: 3110 i -= 6; 3111 emit_int8(0x66); // size prefix 3112 addr_nop_5(); 3113 break; 3114 default: 3115 assert(i < 12, " "); 3116 } 3117 3118 // Generate second nop for size between 11-1 3119 switch (i) { 3120 case 11: 3121 emit_int8(0x66); // size prefix 3122 case 10: 3123 emit_int8(0x66); // size prefix 3124 case 9: 3125 emit_int8(0x66); // size prefix 3126 case 8: 3127 addr_nop_8(); 3128 break; 3129 case 7: 3130 addr_nop_7(); 3131 break; 3132 case 6: 3133 emit_int8(0x66); // size prefix 3134 case 5: 3135 addr_nop_5(); 3136 break; 3137 case 4: 3138 addr_nop_4(); 3139 break; 3140 case 3: 3141 // Don't use "0x0F 0x1F 0x00" - need patching safe padding 3142 emit_int8(0x66); // size prefix 3143 case 2: 3144 emit_int8(0x66); // size prefix 3145 case 1: 3146 emit_int8((unsigned char)0x90); 3147 // nop 3148 break; 3149 default: 3150 assert(i == 0, " "); 3151 } 3152 return; 3153 } 3154 3155 // Using nops with size prefixes "0x66 0x90". 3156 // From AMD Optimization Guide: 3157 // 1: 0x90 3158 // 2: 0x66 0x90 3159 // 3: 0x66 0x66 0x90 3160 // 4: 0x66 0x66 0x66 0x90 3161 // 5: 0x66 0x66 0x90 0x66 0x90 3162 // 6: 0x66 0x66 0x90 0x66 0x66 0x90 3163 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 3164 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90 3165 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3166 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90 3167 // 3168 while(i > 12) { 3169 i -= 4; 3170 emit_int8(0x66); // size prefix 3171 emit_int8(0x66); 3172 emit_int8(0x66); 3173 emit_int8((unsigned char)0x90); 3174 // nop 3175 } 3176 // 1 - 12 nops 3177 if(i > 8) { 3178 if(i > 9) { 3179 i -= 1; 3180 emit_int8(0x66); 3181 } 3182 i -= 3; 3183 emit_int8(0x66); 3184 emit_int8(0x66); 3185 emit_int8((unsigned char)0x90); 3186 } 3187 // 1 - 8 nops 3188 if(i > 4) { 3189 if(i > 6) { 3190 i -= 1; 3191 emit_int8(0x66); 3192 } 3193 i -= 3; 3194 emit_int8(0x66); 3195 emit_int8(0x66); 3196 emit_int8((unsigned char)0x90); 3197 } 3198 switch (i) { 3199 case 4: 3200 emit_int8(0x66); 3201 case 3: 3202 emit_int8(0x66); 3203 case 2: 3204 emit_int8(0x66); 3205 case 1: 3206 emit_int8((unsigned char)0x90); 3207 break; 3208 default: 3209 assert(i == 0, " "); 3210 } 3211 } 3212 3213 void Assembler::notl(Register dst) { 3214 int encode = prefix_and_encode(dst->encoding()); 3215 emit_int8((unsigned char)0xF7); 3216 emit_int8((unsigned char)(0xD0 | encode)); 3217 } 3218 3219 void Assembler::orl(Address dst, int32_t imm32) { 3220 InstructionMark im(this); 3221 prefix(dst); 3222 emit_arith_operand(0x81, rcx, dst, imm32); 3223 } 3224 3225 void Assembler::orl(Register dst, int32_t imm32) { 3226 prefix(dst); 3227 emit_arith(0x81, 0xC8, dst, imm32); 3228 } 3229 3230 void Assembler::orl(Register dst, Address src) { 3231 InstructionMark im(this); 3232 prefix(src, dst); 3233 emit_int8(0x0B); 3234 emit_operand(dst, src); 3235 } 3236 3237 void Assembler::orl(Register dst, Register src) { 3238 (void) prefix_and_encode(dst->encoding(), src->encoding()); 3239 emit_arith(0x0B, 0xC0, dst, src); 3240 } 3241 3242 void Assembler::orl(Address dst, Register src) { 3243 InstructionMark im(this); 3244 prefix(dst, src); 3245 emit_int8(0x09); 3246 emit_operand(src, dst); 3247 } 3248 3249 void Assembler::packuswb(XMMRegister dst, Address src) { 3250 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3251 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3252 InstructionMark im(this); 3253 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3254 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3255 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3256 emit_int8(0x67); 3257 emit_operand(dst, src); 3258 } 3259 3260 void Assembler::packuswb(XMMRegister dst, XMMRegister src) { 3261 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3264 emit_int8(0x67); 3265 emit_int8((unsigned char)(0xC0 | encode)); 3266 } 3267 3268 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3269 assert(UseAVX > 0, "some form of AVX must be enabled"); 3270 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3271 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3272 emit_int8(0x67); 3273 emit_int8((unsigned char)(0xC0 | encode)); 3274 } 3275 3276 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) { 3277 assert(VM_Version::supports_avx2(), ""); 3278 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3279 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3280 emit_int8(0x00); 3281 emit_int8(0xC0 | encode); 3282 emit_int8(imm8); 3283 } 3284 3285 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) { 3286 assert(VM_Version::supports_avx2(), ""); 3287 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3288 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3289 emit_int8(0x46); 3290 emit_int8(0xC0 | encode); 3291 emit_int8(imm8); 3292 } 3293 3294 3295 void Assembler::pause() { 3296 emit_int8((unsigned char)0xF3); 3297 emit_int8((unsigned char)0x90); 3298 } 3299 3300 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3301 assert(VM_Version::supports_sse4_2(), ""); 3302 InstructionMark im(this); 3303 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3304 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3305 emit_int8(0x61); 3306 emit_operand(dst, src); 3307 emit_int8(imm8); 3308 } 3309 3310 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3311 assert(VM_Version::supports_sse4_2(), ""); 3312 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3313 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3314 emit_int8(0x61); 3315 emit_int8((unsigned char)(0xC0 | encode)); 3316 emit_int8(imm8); 3317 } 3318 3319 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3320 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3321 assert(VM_Version::supports_sse2(), ""); 3322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3324 emit_int8(0x74); 3325 emit_int8((unsigned char)(0xC0 | encode)); 3326 } 3327 3328 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3329 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3330 assert(VM_Version::supports_avx(), ""); 3331 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3332 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3333 emit_int8(0x74); 3334 emit_int8((unsigned char)(0xC0 | encode)); 3335 } 3336 3337 // In this context, kdst is written the mask used to process the equal components 3338 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3339 assert(VM_Version::supports_avx512bw(), ""); 3340 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3341 attributes.set_is_evex_instruction(); 3342 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3343 emit_int8(0x74); 3344 emit_int8((unsigned char)(0xC0 | encode)); 3345 } 3346 3347 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3348 assert(VM_Version::supports_avx512vlbw(), ""); 3349 InstructionMark im(this); 3350 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3351 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3352 attributes.set_is_evex_instruction(); 3353 int dst_enc = kdst->encoding(); 3354 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3355 emit_int8(0x64); 3356 emit_operand(as_Register(dst_enc), src); 3357 } 3358 3359 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3360 assert(is_vector_masking(), ""); 3361 assert(VM_Version::supports_avx512vlbw(), ""); 3362 InstructionMark im(this); 3363 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3364 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3365 attributes.set_embedded_opmask_register_specifier(mask); 3366 attributes.set_is_evex_instruction(); 3367 int dst_enc = kdst->encoding(); 3368 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3369 emit_int8(0x64); 3370 emit_operand(as_Register(dst_enc), src); 3371 } 3372 3373 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3374 assert(VM_Version::supports_avx512vlbw(), ""); 3375 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3376 attributes.set_is_evex_instruction(); 3377 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3378 emit_int8(0x3E); 3379 emit_int8((unsigned char)(0xC0 | encode)); 3380 emit_int8(vcc); 3381 } 3382 3383 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) { 3384 assert(is_vector_masking(), ""); 3385 assert(VM_Version::supports_avx512vlbw(), ""); 3386 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3387 attributes.set_embedded_opmask_register_specifier(mask); 3388 attributes.set_is_evex_instruction(); 3389 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3390 emit_int8(0x3E); 3391 emit_int8((unsigned char)(0xC0 | encode)); 3392 emit_int8(vcc); 3393 } 3394 3395 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) { 3396 assert(VM_Version::supports_avx512vlbw(), ""); 3397 InstructionMark im(this); 3398 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3399 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3400 attributes.set_is_evex_instruction(); 3401 int dst_enc = kdst->encoding(); 3402 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3403 emit_int8(0x3E); 3404 emit_operand(as_Register(dst_enc), src); 3405 emit_int8(vcc); 3406 } 3407 3408 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3409 assert(VM_Version::supports_avx512bw(), ""); 3410 InstructionMark im(this); 3411 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3412 attributes.set_is_evex_instruction(); 3413 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3414 int dst_enc = kdst->encoding(); 3415 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3416 emit_int8(0x74); 3417 emit_operand(as_Register(dst_enc), src); 3418 } 3419 3420 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) { 3421 assert(VM_Version::supports_avx512vlbw(), ""); 3422 assert(is_vector_masking(), ""); // For stub code use only 3423 InstructionMark im(this); 3424 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false); 3425 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3426 attributes.set_embedded_opmask_register_specifier(mask); 3427 attributes.set_is_evex_instruction(); 3428 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3429 emit_int8(0x74); 3430 emit_operand(as_Register(kdst->encoding()), src); 3431 } 3432 3433 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3434 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3435 assert(VM_Version::supports_sse2(), ""); 3436 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3437 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3438 emit_int8(0x75); 3439 emit_int8((unsigned char)(0xC0 | encode)); 3440 } 3441 3442 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3443 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3444 assert(VM_Version::supports_avx(), ""); 3445 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3446 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3447 emit_int8(0x75); 3448 emit_int8((unsigned char)(0xC0 | encode)); 3449 } 3450 3451 // In this context, kdst is written the mask used to process the equal components 3452 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3453 assert(VM_Version::supports_avx512bw(), ""); 3454 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3455 attributes.set_is_evex_instruction(); 3456 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3457 emit_int8(0x75); 3458 emit_int8((unsigned char)(0xC0 | encode)); 3459 } 3460 3461 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3462 assert(VM_Version::supports_avx512bw(), ""); 3463 InstructionMark im(this); 3464 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true); 3465 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3466 attributes.set_is_evex_instruction(); 3467 int dst_enc = kdst->encoding(); 3468 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3469 emit_int8(0x75); 3470 emit_operand(as_Register(dst_enc), src); 3471 } 3472 3473 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3474 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) { 3475 assert(VM_Version::supports_sse2(), ""); 3476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3477 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3478 emit_int8(0x76); 3479 emit_int8((unsigned char)(0xC0 | encode)); 3480 } 3481 3482 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3483 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3484 assert(VM_Version::supports_avx(), ""); 3485 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3486 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3487 emit_int8(0x76); 3488 emit_int8((unsigned char)(0xC0 | encode)); 3489 } 3490 3491 // In this context, kdst is written the mask used to process the equal components 3492 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3493 assert(VM_Version::supports_evex(), ""); 3494 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3495 attributes.set_is_evex_instruction(); 3496 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3497 emit_int8(0x76); 3498 emit_int8((unsigned char)(0xC0 | encode)); 3499 } 3500 3501 void Assembler::evpcmpeqd(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3502 assert(VM_Version::supports_evex(), ""); 3503 InstructionMark im(this); 3504 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3505 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3506 attributes.set_is_evex_instruction(); 3507 int dst_enc = kdst->encoding(); 3508 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3509 emit_int8(0x76); 3510 emit_operand(as_Register(dst_enc), src); 3511 } 3512 3513 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3514 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) { 3515 assert(VM_Version::supports_sse4_1(), ""); 3516 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3517 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3518 emit_int8(0x29); 3519 emit_int8((unsigned char)(0xC0 | encode)); 3520 } 3521 3522 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst 3523 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3524 assert(VM_Version::supports_avx(), ""); 3525 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3526 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3527 emit_int8(0x29); 3528 emit_int8((unsigned char)(0xC0 | encode)); 3529 } 3530 3531 // In this context, kdst is written the mask used to process the equal components 3532 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) { 3533 assert(VM_Version::supports_evex(), ""); 3534 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3535 attributes.set_is_evex_instruction(); 3536 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3537 emit_int8(0x29); 3538 emit_int8((unsigned char)(0xC0 | encode)); 3539 } 3540 3541 // In this context, kdst is written the mask used to process the equal components 3542 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) { 3543 assert(VM_Version::supports_evex(), ""); 3544 InstructionMark im(this); 3545 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3546 attributes.set_is_evex_instruction(); 3547 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 3548 int dst_enc = kdst->encoding(); 3549 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3550 emit_int8(0x29); 3551 emit_operand(as_Register(dst_enc), src); 3552 } 3553 3554 void Assembler::pmovmskb(Register dst, XMMRegister src) { 3555 assert(VM_Version::supports_sse2(), ""); 3556 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3557 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3558 emit_int8((unsigned char)0xD7); 3559 emit_int8((unsigned char)(0xC0 | encode)); 3560 } 3561 3562 void Assembler::vpmovmskb(Register dst, XMMRegister src) { 3563 assert(VM_Version::supports_avx2(), ""); 3564 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3565 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3566 emit_int8((unsigned char)0xD7); 3567 emit_int8((unsigned char)(0xC0 | encode)); 3568 } 3569 3570 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) { 3571 assert(VM_Version::supports_sse4_1(), ""); 3572 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3573 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3574 emit_int8(0x16); 3575 emit_int8((unsigned char)(0xC0 | encode)); 3576 emit_int8(imm8); 3577 } 3578 3579 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) { 3580 assert(VM_Version::supports_sse4_1(), ""); 3581 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3582 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3583 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3584 emit_int8(0x16); 3585 emit_operand(src, dst); 3586 emit_int8(imm8); 3587 } 3588 3589 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) { 3590 assert(VM_Version::supports_sse4_1(), ""); 3591 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3592 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3593 emit_int8(0x16); 3594 emit_int8((unsigned char)(0xC0 | encode)); 3595 emit_int8(imm8); 3596 } 3597 3598 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) { 3599 assert(VM_Version::supports_sse4_1(), ""); 3600 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3601 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3602 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3603 emit_int8(0x16); 3604 emit_operand(src, dst); 3605 emit_int8(imm8); 3606 } 3607 3608 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) { 3609 assert(VM_Version::supports_sse2(), ""); 3610 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3611 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3612 emit_int8((unsigned char)0xC5); 3613 emit_int8((unsigned char)(0xC0 | encode)); 3614 emit_int8(imm8); 3615 } 3616 3617 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) { 3618 assert(VM_Version::supports_sse4_1(), ""); 3619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3620 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3621 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3622 emit_int8((unsigned char)0x15); 3623 emit_operand(src, dst); 3624 emit_int8(imm8); 3625 } 3626 3627 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) { 3628 assert(VM_Version::supports_sse4_1(), ""); 3629 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3630 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3631 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3632 emit_int8(0x14); 3633 emit_operand(src, dst); 3634 emit_int8(imm8); 3635 } 3636 3637 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) { 3638 assert(VM_Version::supports_sse4_1(), ""); 3639 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3640 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3641 emit_int8(0x22); 3642 emit_int8((unsigned char)(0xC0 | encode)); 3643 emit_int8(imm8); 3644 } 3645 3646 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) { 3647 assert(VM_Version::supports_sse4_1(), ""); 3648 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3649 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 3650 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3651 emit_int8(0x22); 3652 emit_operand(dst,src); 3653 emit_int8(imm8); 3654 } 3655 3656 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) { 3657 assert(VM_Version::supports_sse4_1(), ""); 3658 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3659 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3660 emit_int8(0x22); 3661 emit_int8((unsigned char)(0xC0 | encode)); 3662 emit_int8(imm8); 3663 } 3664 3665 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) { 3666 assert(VM_Version::supports_sse4_1(), ""); 3667 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false); 3668 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 3669 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3670 emit_int8(0x22); 3671 emit_operand(dst, src); 3672 emit_int8(imm8); 3673 } 3674 3675 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) { 3676 assert(VM_Version::supports_sse2(), ""); 3677 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3678 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3679 emit_int8((unsigned char)0xC4); 3680 emit_int8((unsigned char)(0xC0 | encode)); 3681 emit_int8(imm8); 3682 } 3683 3684 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) { 3685 assert(VM_Version::supports_sse2(), ""); 3686 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3687 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 3688 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3689 emit_int8((unsigned char)0xC4); 3690 emit_operand(dst, src); 3691 emit_int8(imm8); 3692 } 3693 3694 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) { 3695 assert(VM_Version::supports_sse4_1(), ""); 3696 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3697 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 3698 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 3699 emit_int8(0x20); 3700 emit_operand(dst, src); 3701 emit_int8(imm8); 3702 } 3703 3704 void Assembler::pmovzxbw(XMMRegister dst, Address src) { 3705 assert(VM_Version::supports_sse4_1(), ""); 3706 InstructionMark im(this); 3707 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3708 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3709 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3710 emit_int8(0x30); 3711 emit_operand(dst, src); 3712 } 3713 3714 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3715 assert(VM_Version::supports_sse4_1(), ""); 3716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3717 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3718 emit_int8(0x30); 3719 emit_int8((unsigned char)(0xC0 | encode)); 3720 } 3721 3722 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 3723 assert(VM_Version::supports_avx(), ""); 3724 InstructionMark im(this); 3725 assert(dst != xnoreg, "sanity"); 3726 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3727 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3728 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3729 emit_int8(0x30); 3730 emit_operand(dst, src); 3731 } 3732 3733 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) { 3734 assert(is_vector_masking(), ""); 3735 assert(VM_Version::supports_avx512vlbw(), ""); 3736 assert(dst != xnoreg, "sanity"); 3737 InstructionMark im(this); 3738 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3739 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3740 attributes.set_embedded_opmask_register_specifier(mask); 3741 attributes.set_is_evex_instruction(); 3742 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3743 emit_int8(0x30); 3744 emit_operand(dst, src); 3745 } 3746 3747 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) { 3748 assert(VM_Version::supports_avx512vlbw(), ""); 3749 assert(src != xnoreg, "sanity"); 3750 InstructionMark im(this); 3751 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 3752 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3753 attributes.set_is_evex_instruction(); 3754 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3755 emit_int8(0x30); 3756 emit_operand(src, dst); 3757 } 3758 3759 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) { 3760 assert(is_vector_masking(), ""); 3761 assert(VM_Version::supports_avx512vlbw(), ""); 3762 assert(src != xnoreg, "sanity"); 3763 InstructionMark im(this); 3764 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 3765 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit); 3766 attributes.set_embedded_opmask_register_specifier(mask); 3767 attributes.set_is_evex_instruction(); 3768 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes); 3769 emit_int8(0x30); 3770 emit_operand(src, dst); 3771 } 3772 3773 // generic 3774 void Assembler::pop(Register dst) { 3775 int encode = prefix_and_encode(dst->encoding()); 3776 emit_int8(0x58 | encode); 3777 } 3778 3779 void Assembler::popcntl(Register dst, Address src) { 3780 assert(VM_Version::supports_popcnt(), "must support"); 3781 InstructionMark im(this); 3782 emit_int8((unsigned char)0xF3); 3783 prefix(src, dst); 3784 emit_int8(0x0F); 3785 emit_int8((unsigned char)0xB8); 3786 emit_operand(dst, src); 3787 } 3788 3789 void Assembler::popcntl(Register dst, Register src) { 3790 assert(VM_Version::supports_popcnt(), "must support"); 3791 emit_int8((unsigned char)0xF3); 3792 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 3793 emit_int8(0x0F); 3794 emit_int8((unsigned char)0xB8); 3795 emit_int8((unsigned char)(0xC0 | encode)); 3796 } 3797 3798 void Assembler::popf() { 3799 emit_int8((unsigned char)0x9D); 3800 } 3801 3802 #ifndef _LP64 // no 32bit push/pop on amd64 3803 void Assembler::popl(Address dst) { 3804 // NOTE: this will adjust stack by 8byte on 64bits 3805 InstructionMark im(this); 3806 prefix(dst); 3807 emit_int8((unsigned char)0x8F); 3808 emit_operand(rax, dst); 3809 } 3810 #endif 3811 3812 void Assembler::prefetch_prefix(Address src) { 3813 prefix(src); 3814 emit_int8(0x0F); 3815 } 3816 3817 void Assembler::prefetchnta(Address src) { 3818 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3819 InstructionMark im(this); 3820 prefetch_prefix(src); 3821 emit_int8(0x18); 3822 emit_operand(rax, src); // 0, src 3823 } 3824 3825 void Assembler::prefetchr(Address src) { 3826 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 3827 InstructionMark im(this); 3828 prefetch_prefix(src); 3829 emit_int8(0x0D); 3830 emit_operand(rax, src); // 0, src 3831 } 3832 3833 void Assembler::prefetcht0(Address src) { 3834 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3835 InstructionMark im(this); 3836 prefetch_prefix(src); 3837 emit_int8(0x18); 3838 emit_operand(rcx, src); // 1, src 3839 } 3840 3841 void Assembler::prefetcht1(Address src) { 3842 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3843 InstructionMark im(this); 3844 prefetch_prefix(src); 3845 emit_int8(0x18); 3846 emit_operand(rdx, src); // 2, src 3847 } 3848 3849 void Assembler::prefetcht2(Address src) { 3850 NOT_LP64(assert(VM_Version::supports_sse(), "must support")); 3851 InstructionMark im(this); 3852 prefetch_prefix(src); 3853 emit_int8(0x18); 3854 emit_operand(rbx, src); // 3, src 3855 } 3856 3857 void Assembler::prefetchw(Address src) { 3858 assert(VM_Version::supports_3dnow_prefetch(), "must support"); 3859 InstructionMark im(this); 3860 prefetch_prefix(src); 3861 emit_int8(0x0D); 3862 emit_operand(rcx, src); // 1, src 3863 } 3864 3865 void Assembler::prefix(Prefix p) { 3866 emit_int8(p); 3867 } 3868 3869 void Assembler::pshufb(XMMRegister dst, XMMRegister src) { 3870 assert(VM_Version::supports_ssse3(), ""); 3871 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3872 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3873 emit_int8(0x00); 3874 emit_int8((unsigned char)(0xC0 | encode)); 3875 } 3876 3877 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3878 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 3879 vector_len == AVX_256bit? VM_Version::supports_avx2() : 3880 0, ""); 3881 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 3882 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3883 emit_int8(0x00); 3884 emit_int8((unsigned char)(0xC0 | encode)); 3885 } 3886 3887 void Assembler::pshufb(XMMRegister dst, Address src) { 3888 assert(VM_Version::supports_ssse3(), ""); 3889 InstructionMark im(this); 3890 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3891 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3892 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3893 emit_int8(0x00); 3894 emit_operand(dst, src); 3895 } 3896 3897 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) { 3898 assert(isByte(mode), "invalid value"); 3899 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3900 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit; 3901 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3902 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3903 emit_int8(0x70); 3904 emit_int8((unsigned char)(0xC0 | encode)); 3905 emit_int8(mode & 0xFF); 3906 } 3907 3908 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) { 3909 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 3910 vector_len == AVX_256bit? VM_Version::supports_avx2() : 3911 0, ""); 3912 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3913 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3914 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3915 emit_int8(0x70); 3916 emit_int8((unsigned char)(0xC0 | encode)); 3917 emit_int8(mode & 0xFF); 3918 } 3919 3920 void Assembler::pshufd(XMMRegister dst, Address src, int mode) { 3921 assert(isByte(mode), "invalid value"); 3922 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3923 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3924 InstructionMark im(this); 3925 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 3926 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 3927 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3928 emit_int8(0x70); 3929 emit_operand(dst, src); 3930 emit_int8(mode & 0xFF); 3931 } 3932 3933 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 3934 assert(isByte(mode), "invalid value"); 3935 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3936 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3937 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 3938 emit_int8(0x70); 3939 emit_int8((unsigned char)(0xC0 | encode)); 3940 emit_int8(mode & 0xFF); 3941 } 3942 3943 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) { 3944 assert(isByte(mode), "invalid value"); 3945 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3946 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3947 InstructionMark im(this); 3948 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3949 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 3950 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 3951 emit_int8(0x70); 3952 emit_operand(dst, src); 3953 emit_int8(mode & 0xFF); 3954 } 3955 3956 void Assembler::psrldq(XMMRegister dst, int shift) { 3957 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 3958 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3959 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3960 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3961 emit_int8(0x73); 3962 emit_int8((unsigned char)(0xC0 | encode)); 3963 emit_int8(shift); 3964 } 3965 3966 void Assembler::pslldq(XMMRegister dst, int shift) { 3967 // Shift left 128 bit value in dst XMMRegister by shift number of bytes. 3968 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 3969 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false); 3970 // XMM7 is for /7 encoding: 66 0F 73 /7 ib 3971 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 3972 emit_int8(0x73); 3973 emit_int8((unsigned char)(0xC0 | encode)); 3974 emit_int8(shift); 3975 } 3976 3977 void Assembler::ptest(XMMRegister dst, Address src) { 3978 assert(VM_Version::supports_sse4_1(), ""); 3979 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 3980 InstructionMark im(this); 3981 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3982 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3983 emit_int8(0x17); 3984 emit_operand(dst, src); 3985 } 3986 3987 void Assembler::ptest(XMMRegister dst, XMMRegister src) { 3988 assert(VM_Version::supports_sse4_1(), ""); 3989 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3990 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 3991 emit_int8(0x17); 3992 emit_int8((unsigned char)(0xC0 | encode)); 3993 } 3994 3995 void Assembler::vptest(XMMRegister dst, Address src) { 3996 assert(VM_Version::supports_avx(), ""); 3997 InstructionMark im(this); 3998 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 3999 assert(dst != xnoreg, "sanity"); 4000 // swap src<->dst for encoding 4001 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4002 emit_int8(0x17); 4003 emit_operand(dst, src); 4004 } 4005 4006 void Assembler::vptest(XMMRegister dst, XMMRegister src) { 4007 assert(VM_Version::supports_avx(), ""); 4008 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4009 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 4010 emit_int8(0x17); 4011 emit_int8((unsigned char)(0xC0 | encode)); 4012 } 4013 4014 void Assembler::punpcklbw(XMMRegister dst, Address src) { 4015 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4016 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4017 InstructionMark im(this); 4018 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true); 4019 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 4020 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4021 emit_int8(0x60); 4022 emit_operand(dst, src); 4023 } 4024 4025 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4026 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4027 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true); 4028 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4029 emit_int8(0x60); 4030 emit_int8((unsigned char)(0xC0 | encode)); 4031 } 4032 4033 void Assembler::punpckldq(XMMRegister dst, Address src) { 4034 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4035 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes"); 4036 InstructionMark im(this); 4037 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4038 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4039 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4040 emit_int8(0x62); 4041 emit_operand(dst, src); 4042 } 4043 4044 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) { 4045 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4046 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4047 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4048 emit_int8(0x62); 4049 emit_int8((unsigned char)(0xC0 | encode)); 4050 } 4051 4052 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) { 4053 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4054 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4055 attributes.set_rex_vex_w_reverted(); 4056 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4057 emit_int8(0x6C); 4058 emit_int8((unsigned char)(0xC0 | encode)); 4059 } 4060 4061 void Assembler::push(int32_t imm32) { 4062 // in 64bits we push 64bits onto the stack but only 4063 // take a 32bit immediate 4064 emit_int8(0x68); 4065 emit_int32(imm32); 4066 } 4067 4068 void Assembler::push(Register src) { 4069 int encode = prefix_and_encode(src->encoding()); 4070 4071 emit_int8(0x50 | encode); 4072 } 4073 4074 void Assembler::pushf() { 4075 emit_int8((unsigned char)0x9C); 4076 } 4077 4078 #ifndef _LP64 // no 32bit push/pop on amd64 4079 void Assembler::pushl(Address src) { 4080 // Note this will push 64bit on 64bit 4081 InstructionMark im(this); 4082 prefix(src); 4083 emit_int8((unsigned char)0xFF); 4084 emit_operand(rsi, src); 4085 } 4086 #endif 4087 4088 void Assembler::rcll(Register dst, int imm8) { 4089 assert(isShiftCount(imm8), "illegal shift count"); 4090 int encode = prefix_and_encode(dst->encoding()); 4091 if (imm8 == 1) { 4092 emit_int8((unsigned char)0xD1); 4093 emit_int8((unsigned char)(0xD0 | encode)); 4094 } else { 4095 emit_int8((unsigned char)0xC1); 4096 emit_int8((unsigned char)0xD0 | encode); 4097 emit_int8(imm8); 4098 } 4099 } 4100 4101 void Assembler::rcpps(XMMRegister dst, XMMRegister src) { 4102 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4103 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4104 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4105 emit_int8(0x53); 4106 emit_int8((unsigned char)(0xC0 | encode)); 4107 } 4108 4109 void Assembler::rcpss(XMMRegister dst, XMMRegister src) { 4110 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4111 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4112 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4113 emit_int8(0x53); 4114 emit_int8((unsigned char)(0xC0 | encode)); 4115 } 4116 4117 void Assembler::rdtsc() { 4118 emit_int8((unsigned char)0x0F); 4119 emit_int8((unsigned char)0x31); 4120 } 4121 4122 // copies data from [esi] to [edi] using rcx pointer sized words 4123 // generic 4124 void Assembler::rep_mov() { 4125 emit_int8((unsigned char)0xF3); 4126 // MOVSQ 4127 LP64_ONLY(prefix(REX_W)); 4128 emit_int8((unsigned char)0xA5); 4129 } 4130 4131 // sets rcx bytes with rax, value at [edi] 4132 void Assembler::rep_stosb() { 4133 emit_int8((unsigned char)0xF3); // REP 4134 LP64_ONLY(prefix(REX_W)); 4135 emit_int8((unsigned char)0xAA); // STOSB 4136 } 4137 4138 // sets rcx pointer sized words with rax, value at [edi] 4139 // generic 4140 void Assembler::rep_stos() { 4141 emit_int8((unsigned char)0xF3); // REP 4142 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD 4143 emit_int8((unsigned char)0xAB); 4144 } 4145 4146 // scans rcx pointer sized words at [edi] for occurance of rax, 4147 // generic 4148 void Assembler::repne_scan() { // repne_scan 4149 emit_int8((unsigned char)0xF2); 4150 // SCASQ 4151 LP64_ONLY(prefix(REX_W)); 4152 emit_int8((unsigned char)0xAF); 4153 } 4154 4155 #ifdef _LP64 4156 // scans rcx 4 byte words at [edi] for occurance of rax, 4157 // generic 4158 void Assembler::repne_scanl() { // repne_scan 4159 emit_int8((unsigned char)0xF2); 4160 // SCASL 4161 emit_int8((unsigned char)0xAF); 4162 } 4163 #endif 4164 4165 void Assembler::ret(int imm16) { 4166 if (imm16 == 0) { 4167 emit_int8((unsigned char)0xC3); 4168 } else { 4169 emit_int8((unsigned char)0xC2); 4170 emit_int16(imm16); 4171 } 4172 } 4173 4174 void Assembler::sahf() { 4175 #ifdef _LP64 4176 // Not supported in 64bit mode 4177 ShouldNotReachHere(); 4178 #endif 4179 emit_int8((unsigned char)0x9E); 4180 } 4181 4182 void Assembler::sarl(Register dst, int imm8) { 4183 int encode = prefix_and_encode(dst->encoding()); 4184 assert(isShiftCount(imm8), "illegal shift count"); 4185 if (imm8 == 1) { 4186 emit_int8((unsigned char)0xD1); 4187 emit_int8((unsigned char)(0xF8 | encode)); 4188 } else { 4189 emit_int8((unsigned char)0xC1); 4190 emit_int8((unsigned char)(0xF8 | encode)); 4191 emit_int8(imm8); 4192 } 4193 } 4194 4195 void Assembler::sarl(Register dst) { 4196 int encode = prefix_and_encode(dst->encoding()); 4197 emit_int8((unsigned char)0xD3); 4198 emit_int8((unsigned char)(0xF8 | encode)); 4199 } 4200 4201 void Assembler::sbbl(Address dst, int32_t imm32) { 4202 InstructionMark im(this); 4203 prefix(dst); 4204 emit_arith_operand(0x81, rbx, dst, imm32); 4205 } 4206 4207 void Assembler::sbbl(Register dst, int32_t imm32) { 4208 prefix(dst); 4209 emit_arith(0x81, 0xD8, dst, imm32); 4210 } 4211 4212 4213 void Assembler::sbbl(Register dst, Address src) { 4214 InstructionMark im(this); 4215 prefix(src, dst); 4216 emit_int8(0x1B); 4217 emit_operand(dst, src); 4218 } 4219 4220 void Assembler::sbbl(Register dst, Register src) { 4221 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4222 emit_arith(0x1B, 0xC0, dst, src); 4223 } 4224 4225 void Assembler::setb(Condition cc, Register dst) { 4226 assert(0 <= cc && cc < 16, "illegal cc"); 4227 int encode = prefix_and_encode(dst->encoding(), true); 4228 emit_int8(0x0F); 4229 emit_int8((unsigned char)0x90 | cc); 4230 emit_int8((unsigned char)(0xC0 | encode)); 4231 } 4232 4233 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) { 4234 assert(VM_Version::supports_ssse3(), ""); 4235 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false); 4236 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4237 emit_int8((unsigned char)0x0F); 4238 emit_int8((unsigned char)(0xC0 | encode)); 4239 emit_int8(imm8); 4240 } 4241 4242 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) { 4243 assert(vector_len == AVX_128bit? VM_Version::supports_avx() : 4244 vector_len == AVX_256bit? VM_Version::supports_avx2() : 4245 0, ""); 4246 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true); 4247 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4248 emit_int8((unsigned char)0x0F); 4249 emit_int8((unsigned char)(0xC0 | encode)); 4250 emit_int8(imm8); 4251 } 4252 4253 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) { 4254 assert(VM_Version::supports_sse4_1(), ""); 4255 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 4256 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 4257 emit_int8((unsigned char)0x0E); 4258 emit_int8((unsigned char)(0xC0 | encode)); 4259 emit_int8(imm8); 4260 } 4261 4262 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) { 4263 assert(VM_Version::supports_sha(), ""); 4264 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4265 emit_int8((unsigned char)0x0F); 4266 emit_int8((unsigned char)0x3A); 4267 emit_int8((unsigned char)0xCC); 4268 emit_int8((unsigned char)(0xC0 | encode)); 4269 emit_int8((unsigned char)imm8); 4270 } 4271 4272 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) { 4273 assert(VM_Version::supports_sha(), ""); 4274 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4275 emit_int8((unsigned char)0x0F); 4276 emit_int8((unsigned char)0x38); 4277 emit_int8((unsigned char)0xC8); 4278 emit_int8((unsigned char)(0xC0 | encode)); 4279 } 4280 4281 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) { 4282 assert(VM_Version::supports_sha(), ""); 4283 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4284 emit_int8((unsigned char)0x0F); 4285 emit_int8((unsigned char)0x38); 4286 emit_int8((unsigned char)0xC9); 4287 emit_int8((unsigned char)(0xC0 | encode)); 4288 } 4289 4290 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) { 4291 assert(VM_Version::supports_sha(), ""); 4292 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4293 emit_int8((unsigned char)0x0F); 4294 emit_int8((unsigned char)0x38); 4295 emit_int8((unsigned char)0xCA); 4296 emit_int8((unsigned char)(0xC0 | encode)); 4297 } 4298 4299 // xmm0 is implicit additional source to this instruction. 4300 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) { 4301 assert(VM_Version::supports_sha(), ""); 4302 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4303 emit_int8((unsigned char)0x0F); 4304 emit_int8((unsigned char)0x38); 4305 emit_int8((unsigned char)0xCB); 4306 emit_int8((unsigned char)(0xC0 | encode)); 4307 } 4308 4309 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) { 4310 assert(VM_Version::supports_sha(), ""); 4311 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4312 emit_int8((unsigned char)0x0F); 4313 emit_int8((unsigned char)0x38); 4314 emit_int8((unsigned char)0xCC); 4315 emit_int8((unsigned char)(0xC0 | encode)); 4316 } 4317 4318 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) { 4319 assert(VM_Version::supports_sha(), ""); 4320 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4321 emit_int8((unsigned char)0x0F); 4322 emit_int8((unsigned char)0x38); 4323 emit_int8((unsigned char)0xCD); 4324 emit_int8((unsigned char)(0xC0 | encode)); 4325 } 4326 4327 4328 void Assembler::shll(Register dst, int imm8) { 4329 assert(isShiftCount(imm8), "illegal shift count"); 4330 int encode = prefix_and_encode(dst->encoding()); 4331 if (imm8 == 1 ) { 4332 emit_int8((unsigned char)0xD1); 4333 emit_int8((unsigned char)(0xE0 | encode)); 4334 } else { 4335 emit_int8((unsigned char)0xC1); 4336 emit_int8((unsigned char)(0xE0 | encode)); 4337 emit_int8(imm8); 4338 } 4339 } 4340 4341 void Assembler::shll(Register dst) { 4342 int encode = prefix_and_encode(dst->encoding()); 4343 emit_int8((unsigned char)0xD3); 4344 emit_int8((unsigned char)(0xE0 | encode)); 4345 } 4346 4347 void Assembler::shrl(Register dst, int imm8) { 4348 assert(isShiftCount(imm8), "illegal shift count"); 4349 int encode = prefix_and_encode(dst->encoding()); 4350 emit_int8((unsigned char)0xC1); 4351 emit_int8((unsigned char)(0xE8 | encode)); 4352 emit_int8(imm8); 4353 } 4354 4355 void Assembler::shrl(Register dst) { 4356 int encode = prefix_and_encode(dst->encoding()); 4357 emit_int8((unsigned char)0xD3); 4358 emit_int8((unsigned char)(0xE8 | encode)); 4359 } 4360 4361 // copies a single word from [esi] to [edi] 4362 void Assembler::smovl() { 4363 emit_int8((unsigned char)0xA5); 4364 } 4365 4366 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) { 4367 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4368 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4369 attributes.set_rex_vex_w_reverted(); 4370 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4371 emit_int8(0x51); 4372 emit_int8((unsigned char)(0xC0 | encode)); 4373 } 4374 4375 void Assembler::sqrtsd(XMMRegister dst, Address src) { 4376 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4377 InstructionMark im(this); 4378 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4379 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4380 attributes.set_rex_vex_w_reverted(); 4381 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4382 emit_int8(0x51); 4383 emit_operand(dst, src); 4384 } 4385 4386 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) { 4387 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4388 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4389 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4390 emit_int8(0x51); 4391 emit_int8((unsigned char)(0xC0 | encode)); 4392 } 4393 4394 void Assembler::std() { 4395 emit_int8((unsigned char)0xFD); 4396 } 4397 4398 void Assembler::sqrtss(XMMRegister dst, Address src) { 4399 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4400 InstructionMark im(this); 4401 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4402 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4403 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4404 emit_int8(0x51); 4405 emit_operand(dst, src); 4406 } 4407 4408 void Assembler::stmxcsr( Address dst) { 4409 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4410 InstructionMark im(this); 4411 prefix(dst); 4412 emit_int8(0x0F); 4413 emit_int8((unsigned char)0xAE); 4414 emit_operand(as_Register(3), dst); 4415 } 4416 4417 void Assembler::subl(Address dst, int32_t imm32) { 4418 InstructionMark im(this); 4419 prefix(dst); 4420 emit_arith_operand(0x81, rbp, dst, imm32); 4421 } 4422 4423 void Assembler::subl(Address dst, Register src) { 4424 InstructionMark im(this); 4425 prefix(dst, src); 4426 emit_int8(0x29); 4427 emit_operand(src, dst); 4428 } 4429 4430 void Assembler::subl(Register dst, int32_t imm32) { 4431 prefix(dst); 4432 emit_arith(0x81, 0xE8, dst, imm32); 4433 } 4434 4435 // Force generation of a 4 byte immediate value even if it fits into 8bit 4436 void Assembler::subl_imm32(Register dst, int32_t imm32) { 4437 prefix(dst); 4438 emit_arith_imm32(0x81, 0xE8, dst, imm32); 4439 } 4440 4441 void Assembler::subl(Register dst, Address src) { 4442 InstructionMark im(this); 4443 prefix(src, dst); 4444 emit_int8(0x2B); 4445 emit_operand(dst, src); 4446 } 4447 4448 void Assembler::subl(Register dst, Register src) { 4449 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4450 emit_arith(0x2B, 0xC0, dst, src); 4451 } 4452 4453 void Assembler::subsd(XMMRegister dst, XMMRegister src) { 4454 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4455 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4456 attributes.set_rex_vex_w_reverted(); 4457 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4458 emit_int8(0x5C); 4459 emit_int8((unsigned char)(0xC0 | encode)); 4460 } 4461 4462 void Assembler::subsd(XMMRegister dst, Address src) { 4463 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4464 InstructionMark im(this); 4465 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4466 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4467 attributes.set_rex_vex_w_reverted(); 4468 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4469 emit_int8(0x5C); 4470 emit_operand(dst, src); 4471 } 4472 4473 void Assembler::subss(XMMRegister dst, XMMRegister src) { 4474 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4475 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ false); 4476 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4477 emit_int8(0x5C); 4478 emit_int8((unsigned char)(0xC0 | encode)); 4479 } 4480 4481 void Assembler::subss(XMMRegister dst, Address src) { 4482 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4483 InstructionMark im(this); 4484 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4485 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4486 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4487 emit_int8(0x5C); 4488 emit_operand(dst, src); 4489 } 4490 4491 void Assembler::testb(Register dst, int imm8) { 4492 NOT_LP64(assert(dst->has_byte_register(), "must have byte register")); 4493 (void) prefix_and_encode(dst->encoding(), true); 4494 emit_arith_b(0xF6, 0xC0, dst, imm8); 4495 } 4496 4497 void Assembler::testb(Address dst, int imm8) { 4498 InstructionMark im(this); 4499 prefix(dst); 4500 emit_int8((unsigned char)0xF6); 4501 emit_operand(rax, dst, 1); 4502 emit_int8(imm8); 4503 } 4504 4505 void Assembler::testl(Register dst, int32_t imm32) { 4506 // not using emit_arith because test 4507 // doesn't support sign-extension of 4508 // 8bit operands 4509 int encode = dst->encoding(); 4510 if (encode == 0) { 4511 emit_int8((unsigned char)0xA9); 4512 } else { 4513 encode = prefix_and_encode(encode); 4514 emit_int8((unsigned char)0xF7); 4515 emit_int8((unsigned char)(0xC0 | encode)); 4516 } 4517 emit_int32(imm32); 4518 } 4519 4520 void Assembler::testl(Register dst, Register src) { 4521 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4522 emit_arith(0x85, 0xC0, dst, src); 4523 } 4524 4525 void Assembler::testl(Register dst, Address src) { 4526 InstructionMark im(this); 4527 prefix(src, dst); 4528 emit_int8((unsigned char)0x85); 4529 emit_operand(dst, src); 4530 } 4531 4532 void Assembler::tzcntl(Register dst, Register src) { 4533 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4534 emit_int8((unsigned char)0xF3); 4535 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4536 emit_int8(0x0F); 4537 emit_int8((unsigned char)0xBC); 4538 emit_int8((unsigned char)0xC0 | encode); 4539 } 4540 4541 void Assembler::tzcntq(Register dst, Register src) { 4542 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported"); 4543 emit_int8((unsigned char)0xF3); 4544 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 4545 emit_int8(0x0F); 4546 emit_int8((unsigned char)0xBC); 4547 emit_int8((unsigned char)(0xC0 | encode)); 4548 } 4549 4550 void Assembler::ucomisd(XMMRegister dst, Address src) { 4551 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4552 InstructionMark im(this); 4553 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4554 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4555 attributes.set_rex_vex_w_reverted(); 4556 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4557 emit_int8(0x2E); 4558 emit_operand(dst, src); 4559 } 4560 4561 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) { 4562 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4563 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4564 attributes.set_rex_vex_w_reverted(); 4565 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4566 emit_int8(0x2E); 4567 emit_int8((unsigned char)(0xC0 | encode)); 4568 } 4569 4570 void Assembler::ucomiss(XMMRegister dst, Address src) { 4571 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4572 InstructionMark im(this); 4573 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4574 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4575 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4576 emit_int8(0x2E); 4577 emit_operand(dst, src); 4578 } 4579 4580 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) { 4581 NOT_LP64(assert(VM_Version::supports_sse(), "")); 4582 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 4583 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4584 emit_int8(0x2E); 4585 emit_int8((unsigned char)(0xC0 | encode)); 4586 } 4587 4588 void Assembler::xabort(int8_t imm8) { 4589 emit_int8((unsigned char)0xC6); 4590 emit_int8((unsigned char)0xF8); 4591 emit_int8((unsigned char)(imm8 & 0xFF)); 4592 } 4593 4594 void Assembler::xaddb(Address dst, Register src) { 4595 InstructionMark im(this); 4596 prefix(dst, src, true); 4597 emit_int8(0x0F); 4598 emit_int8((unsigned char)0xC0); 4599 emit_operand(src, dst); 4600 } 4601 4602 void Assembler::xaddw(Address dst, Register src) { 4603 InstructionMark im(this); 4604 emit_int8(0x66); 4605 prefix(dst, src); 4606 emit_int8(0x0F); 4607 emit_int8((unsigned char)0xC1); 4608 emit_operand(src, dst); 4609 } 4610 4611 void Assembler::xaddl(Address dst, Register src) { 4612 InstructionMark im(this); 4613 prefix(dst, src); 4614 emit_int8(0x0F); 4615 emit_int8((unsigned char)0xC1); 4616 emit_operand(src, dst); 4617 } 4618 4619 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) { 4620 InstructionMark im(this); 4621 relocate(rtype); 4622 if (abort.is_bound()) { 4623 address entry = target(abort); 4624 assert(entry != NULL, "abort entry NULL"); 4625 intptr_t offset = entry - pc(); 4626 emit_int8((unsigned char)0xC7); 4627 emit_int8((unsigned char)0xF8); 4628 emit_int32(offset - 6); // 2 opcode + 4 address 4629 } else { 4630 abort.add_patch_at(code(), locator()); 4631 emit_int8((unsigned char)0xC7); 4632 emit_int8((unsigned char)0xF8); 4633 emit_int32(0); 4634 } 4635 } 4636 4637 void Assembler::xchgb(Register dst, Address src) { // xchg 4638 InstructionMark im(this); 4639 prefix(src, dst, true); 4640 emit_int8((unsigned char)0x86); 4641 emit_operand(dst, src); 4642 } 4643 4644 void Assembler::xchgw(Register dst, Address src) { // xchg 4645 InstructionMark im(this); 4646 emit_int8(0x66); 4647 prefix(src, dst); 4648 emit_int8((unsigned char)0x87); 4649 emit_operand(dst, src); 4650 } 4651 4652 void Assembler::xchgl(Register dst, Address src) { // xchg 4653 InstructionMark im(this); 4654 prefix(src, dst); 4655 emit_int8((unsigned char)0x87); 4656 emit_operand(dst, src); 4657 } 4658 4659 void Assembler::xchgl(Register dst, Register src) { 4660 int encode = prefix_and_encode(dst->encoding(), src->encoding()); 4661 emit_int8((unsigned char)0x87); 4662 emit_int8((unsigned char)(0xC0 | encode)); 4663 } 4664 4665 void Assembler::xend() { 4666 emit_int8((unsigned char)0x0F); 4667 emit_int8((unsigned char)0x01); 4668 emit_int8((unsigned char)0xD5); 4669 } 4670 4671 void Assembler::xgetbv() { 4672 emit_int8(0x0F); 4673 emit_int8(0x01); 4674 emit_int8((unsigned char)0xD0); 4675 } 4676 4677 void Assembler::xorl(Register dst, int32_t imm32) { 4678 prefix(dst); 4679 emit_arith(0x81, 0xF0, dst, imm32); 4680 } 4681 4682 void Assembler::xorl(Register dst, Address src) { 4683 InstructionMark im(this); 4684 prefix(src, dst); 4685 emit_int8(0x33); 4686 emit_operand(dst, src); 4687 } 4688 4689 void Assembler::xorl(Register dst, Register src) { 4690 (void) prefix_and_encode(dst->encoding(), src->encoding()); 4691 emit_arith(0x33, 0xC0, dst, src); 4692 } 4693 4694 void Assembler::xorb(Register dst, Address src) { 4695 InstructionMark im(this); 4696 prefix(src, dst); 4697 emit_int8(0x32); 4698 emit_operand(dst, src); 4699 } 4700 4701 // AVX 3-operands scalar float-point arithmetic instructions 4702 4703 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) { 4704 assert(VM_Version::supports_avx(), ""); 4705 InstructionMark im(this); 4706 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4707 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4708 attributes.set_rex_vex_w_reverted(); 4709 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4710 emit_int8(0x58); 4711 emit_operand(dst, src); 4712 } 4713 4714 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4715 assert(VM_Version::supports_avx(), ""); 4716 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4717 attributes.set_rex_vex_w_reverted(); 4718 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4719 emit_int8(0x58); 4720 emit_int8((unsigned char)(0xC0 | encode)); 4721 } 4722 4723 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) { 4724 assert(VM_Version::supports_avx(), ""); 4725 InstructionMark im(this); 4726 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4727 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4728 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4729 emit_int8(0x58); 4730 emit_operand(dst, src); 4731 } 4732 4733 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4734 assert(VM_Version::supports_avx(), ""); 4735 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4736 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4737 emit_int8(0x58); 4738 emit_int8((unsigned char)(0xC0 | encode)); 4739 } 4740 4741 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) { 4742 assert(VM_Version::supports_avx(), ""); 4743 InstructionMark im(this); 4744 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4745 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4746 attributes.set_rex_vex_w_reverted(); 4747 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4748 emit_int8(0x5E); 4749 emit_operand(dst, src); 4750 } 4751 4752 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4753 assert(VM_Version::supports_avx(), ""); 4754 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4755 attributes.set_rex_vex_w_reverted(); 4756 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4757 emit_int8(0x5E); 4758 emit_int8((unsigned char)(0xC0 | encode)); 4759 } 4760 4761 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) { 4762 assert(VM_Version::supports_avx(), ""); 4763 InstructionMark im(this); 4764 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4765 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4766 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4767 emit_int8(0x5E); 4768 emit_operand(dst, src); 4769 } 4770 4771 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4772 assert(VM_Version::supports_avx(), ""); 4773 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4774 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4775 emit_int8(0x5E); 4776 emit_int8((unsigned char)(0xC0 | encode)); 4777 } 4778 4779 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) { 4780 assert(VM_Version::supports_avx(), ""); 4781 InstructionMark im(this); 4782 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4783 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4784 attributes.set_rex_vex_w_reverted(); 4785 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4786 emit_int8(0x59); 4787 emit_operand(dst, src); 4788 } 4789 4790 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4791 assert(VM_Version::supports_avx(), ""); 4792 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4793 attributes.set_rex_vex_w_reverted(); 4794 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4795 emit_int8(0x59); 4796 emit_int8((unsigned char)(0xC0 | encode)); 4797 } 4798 4799 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) { 4800 assert(VM_Version::supports_avx(), ""); 4801 InstructionMark im(this); 4802 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4803 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4804 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4805 emit_int8(0x59); 4806 emit_operand(dst, src); 4807 } 4808 4809 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4810 assert(VM_Version::supports_avx(), ""); 4811 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4812 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4813 emit_int8(0x59); 4814 emit_int8((unsigned char)(0xC0 | encode)); 4815 } 4816 4817 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) { 4818 assert(VM_Version::supports_avx(), ""); 4819 InstructionMark im(this); 4820 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4821 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 4822 attributes.set_rex_vex_w_reverted(); 4823 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4824 emit_int8(0x5C); 4825 emit_operand(dst, src); 4826 } 4827 4828 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4829 assert(VM_Version::supports_avx(), ""); 4830 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4831 attributes.set_rex_vex_w_reverted(); 4832 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 4833 emit_int8(0x5C); 4834 emit_int8((unsigned char)(0xC0 | encode)); 4835 } 4836 4837 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) { 4838 assert(VM_Version::supports_avx(), ""); 4839 InstructionMark im(this); 4840 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4841 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 4842 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4843 emit_int8(0x5C); 4844 emit_operand(dst, src); 4845 } 4846 4847 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { 4848 assert(VM_Version::supports_avx(), ""); 4849 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 4850 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 4851 emit_int8(0x5C); 4852 emit_int8((unsigned char)(0xC0 | encode)); 4853 } 4854 4855 //====================VECTOR ARITHMETIC===================================== 4856 4857 // Float-point vector arithmetic 4858 4859 void Assembler::addpd(XMMRegister dst, XMMRegister src) { 4860 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4861 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4862 attributes.set_rex_vex_w_reverted(); 4863 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4864 emit_int8(0x58); 4865 emit_int8((unsigned char)(0xC0 | encode)); 4866 } 4867 4868 void Assembler::addpd(XMMRegister dst, Address src) { 4869 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4870 InstructionMark im(this); 4871 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4872 attributes.set_rex_vex_w_reverted(); 4873 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4874 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4875 emit_int8(0x58); 4876 emit_operand(dst, src); 4877 } 4878 4879 4880 void Assembler::addps(XMMRegister dst, XMMRegister src) { 4881 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4882 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4883 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4884 emit_int8(0x58); 4885 emit_int8((unsigned char)(0xC0 | encode)); 4886 } 4887 4888 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4889 assert(VM_Version::supports_avx(), ""); 4890 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4891 attributes.set_rex_vex_w_reverted(); 4892 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4893 emit_int8(0x58); 4894 emit_int8((unsigned char)(0xC0 | encode)); 4895 } 4896 4897 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4898 assert(VM_Version::supports_avx(), ""); 4899 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4900 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4901 emit_int8(0x58); 4902 emit_int8((unsigned char)(0xC0 | encode)); 4903 } 4904 4905 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4906 assert(VM_Version::supports_avx(), ""); 4907 InstructionMark im(this); 4908 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4909 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4910 attributes.set_rex_vex_w_reverted(); 4911 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4912 emit_int8(0x58); 4913 emit_operand(dst, src); 4914 } 4915 4916 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4917 assert(VM_Version::supports_avx(), ""); 4918 InstructionMark im(this); 4919 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4920 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4921 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4922 emit_int8(0x58); 4923 emit_operand(dst, src); 4924 } 4925 4926 void Assembler::subpd(XMMRegister dst, XMMRegister src) { 4927 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4928 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4929 attributes.set_rex_vex_w_reverted(); 4930 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4931 emit_int8(0x5C); 4932 emit_int8((unsigned char)(0xC0 | encode)); 4933 } 4934 4935 void Assembler::subps(XMMRegister dst, XMMRegister src) { 4936 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4937 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4938 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4939 emit_int8(0x5C); 4940 emit_int8((unsigned char)(0xC0 | encode)); 4941 } 4942 4943 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4944 assert(VM_Version::supports_avx(), ""); 4945 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4946 attributes.set_rex_vex_w_reverted(); 4947 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4948 emit_int8(0x5C); 4949 emit_int8((unsigned char)(0xC0 | encode)); 4950 } 4951 4952 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4953 assert(VM_Version::supports_avx(), ""); 4954 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4955 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4956 emit_int8(0x5C); 4957 emit_int8((unsigned char)(0xC0 | encode)); 4958 } 4959 4960 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4961 assert(VM_Version::supports_avx(), ""); 4962 InstructionMark im(this); 4963 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4964 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4965 attributes.set_rex_vex_w_reverted(); 4966 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4967 emit_int8(0x5C); 4968 emit_operand(dst, src); 4969 } 4970 4971 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4972 assert(VM_Version::supports_avx(), ""); 4973 InstructionMark im(this); 4974 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4975 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 4976 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 4977 emit_int8(0x5C); 4978 emit_operand(dst, src); 4979 } 4980 4981 void Assembler::mulpd(XMMRegister dst, XMMRegister src) { 4982 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4983 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4984 attributes.set_rex_vex_w_reverted(); 4985 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4986 emit_int8(0x59); 4987 emit_int8((unsigned char)(0xC0 | encode)); 4988 } 4989 4990 void Assembler::mulpd(XMMRegister dst, Address src) { 4991 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 4992 InstructionMark im(this); 4993 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 4994 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 4995 attributes.set_rex_vex_w_reverted(); 4996 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 4997 emit_int8(0x59); 4998 emit_operand(dst, src); 4999 } 5000 5001 void Assembler::mulps(XMMRegister dst, XMMRegister src) { 5002 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5003 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5004 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5005 emit_int8(0x59); 5006 emit_int8((unsigned char)(0xC0 | encode)); 5007 } 5008 5009 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5010 assert(VM_Version::supports_avx(), ""); 5011 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5012 attributes.set_rex_vex_w_reverted(); 5013 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5014 emit_int8(0x59); 5015 emit_int8((unsigned char)(0xC0 | encode)); 5016 } 5017 5018 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5019 assert(VM_Version::supports_avx(), ""); 5020 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5021 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5022 emit_int8(0x59); 5023 emit_int8((unsigned char)(0xC0 | encode)); 5024 } 5025 5026 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5027 assert(VM_Version::supports_avx(), ""); 5028 InstructionMark im(this); 5029 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5030 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5031 attributes.set_rex_vex_w_reverted(); 5032 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5033 emit_int8(0x59); 5034 emit_operand(dst, src); 5035 } 5036 5037 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5038 assert(VM_Version::supports_avx(), ""); 5039 InstructionMark im(this); 5040 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5041 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5042 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5043 emit_int8(0x59); 5044 emit_operand(dst, src); 5045 } 5046 5047 void Assembler::divpd(XMMRegister dst, XMMRegister src) { 5048 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5049 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5050 attributes.set_rex_vex_w_reverted(); 5051 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5052 emit_int8(0x5E); 5053 emit_int8((unsigned char)(0xC0 | encode)); 5054 } 5055 5056 void Assembler::divps(XMMRegister dst, XMMRegister src) { 5057 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5058 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5059 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5060 emit_int8(0x5E); 5061 emit_int8((unsigned char)(0xC0 | encode)); 5062 } 5063 5064 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5065 assert(VM_Version::supports_avx(), ""); 5066 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5067 attributes.set_rex_vex_w_reverted(); 5068 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5069 emit_int8(0x5E); 5070 emit_int8((unsigned char)(0xC0 | encode)); 5071 } 5072 5073 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5074 assert(VM_Version::supports_avx(), ""); 5075 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5076 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5077 emit_int8(0x5E); 5078 emit_int8((unsigned char)(0xC0 | encode)); 5079 } 5080 5081 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5082 assert(VM_Version::supports_avx(), ""); 5083 InstructionMark im(this); 5084 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5085 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5086 attributes.set_rex_vex_w_reverted(); 5087 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5088 emit_int8(0x5E); 5089 emit_operand(dst, src); 5090 } 5091 5092 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5093 assert(VM_Version::supports_avx(), ""); 5094 InstructionMark im(this); 5095 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5096 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5097 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5098 emit_int8(0x5E); 5099 emit_operand(dst, src); 5100 } 5101 5102 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) { 5103 assert(VM_Version::supports_avx(), ""); 5104 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5105 attributes.set_rex_vex_w_reverted(); 5106 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5107 emit_int8(0x51); 5108 emit_int8((unsigned char)(0xC0 | encode)); 5109 } 5110 5111 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) { 5112 assert(VM_Version::supports_avx(), ""); 5113 InstructionMark im(this); 5114 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5115 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5116 attributes.set_rex_vex_w_reverted(); 5117 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5118 emit_int8(0x51); 5119 emit_operand(dst, src); 5120 } 5121 5122 void Assembler::andpd(XMMRegister dst, XMMRegister src) { 5123 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5124 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5125 attributes.set_rex_vex_w_reverted(); 5126 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5127 emit_int8(0x54); 5128 emit_int8((unsigned char)(0xC0 | encode)); 5129 } 5130 5131 void Assembler::andps(XMMRegister dst, XMMRegister src) { 5132 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5133 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5134 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5135 emit_int8(0x54); 5136 emit_int8((unsigned char)(0xC0 | encode)); 5137 } 5138 5139 void Assembler::andps(XMMRegister dst, Address src) { 5140 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5141 InstructionMark im(this); 5142 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5143 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5144 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5145 emit_int8(0x54); 5146 emit_operand(dst, src); 5147 } 5148 5149 void Assembler::andpd(XMMRegister dst, Address src) { 5150 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5151 InstructionMark im(this); 5152 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5153 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5154 attributes.set_rex_vex_w_reverted(); 5155 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5156 emit_int8(0x54); 5157 emit_operand(dst, src); 5158 } 5159 5160 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5161 assert(VM_Version::supports_avx(), ""); 5162 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5163 attributes.set_rex_vex_w_reverted(); 5164 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5165 emit_int8(0x54); 5166 emit_int8((unsigned char)(0xC0 | encode)); 5167 } 5168 5169 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5170 assert(VM_Version::supports_avx(), ""); 5171 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5172 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5173 emit_int8(0x54); 5174 emit_int8((unsigned char)(0xC0 | encode)); 5175 } 5176 5177 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5178 assert(VM_Version::supports_avx(), ""); 5179 InstructionMark im(this); 5180 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5181 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5182 attributes.set_rex_vex_w_reverted(); 5183 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5184 emit_int8(0x54); 5185 emit_operand(dst, src); 5186 } 5187 5188 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5189 assert(VM_Version::supports_avx(), ""); 5190 InstructionMark im(this); 5191 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5192 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5193 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5194 emit_int8(0x54); 5195 emit_operand(dst, src); 5196 } 5197 5198 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) { 5199 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5200 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5201 attributes.set_rex_vex_w_reverted(); 5202 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5203 emit_int8(0x15); 5204 emit_int8((unsigned char)(0xC0 | encode)); 5205 } 5206 5207 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) { 5208 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5209 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5210 attributes.set_rex_vex_w_reverted(); 5211 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5212 emit_int8(0x14); 5213 emit_int8((unsigned char)(0xC0 | encode)); 5214 } 5215 5216 void Assembler::xorpd(XMMRegister dst, XMMRegister src) { 5217 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5218 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5219 attributes.set_rex_vex_w_reverted(); 5220 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5221 emit_int8(0x57); 5222 emit_int8((unsigned char)(0xC0 | encode)); 5223 } 5224 5225 void Assembler::xorps(XMMRegister dst, XMMRegister src) { 5226 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5227 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5228 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5229 emit_int8(0x57); 5230 emit_int8((unsigned char)(0xC0 | encode)); 5231 } 5232 5233 void Assembler::xorpd(XMMRegister dst, Address src) { 5234 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5235 InstructionMark im(this); 5236 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5237 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5238 attributes.set_rex_vex_w_reverted(); 5239 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5240 emit_int8(0x57); 5241 emit_operand(dst, src); 5242 } 5243 5244 void Assembler::xorps(XMMRegister dst, Address src) { 5245 NOT_LP64(assert(VM_Version::supports_sse(), "")); 5246 InstructionMark im(this); 5247 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5248 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5249 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5250 emit_int8(0x57); 5251 emit_operand(dst, src); 5252 } 5253 5254 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5255 assert(VM_Version::supports_avx(), ""); 5256 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5257 attributes.set_rex_vex_w_reverted(); 5258 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5259 emit_int8(0x57); 5260 emit_int8((unsigned char)(0xC0 | encode)); 5261 } 5262 5263 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5264 assert(VM_Version::supports_avx(), ""); 5265 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5266 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5267 emit_int8(0x57); 5268 emit_int8((unsigned char)(0xC0 | encode)); 5269 } 5270 5271 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5272 assert(VM_Version::supports_avx(), ""); 5273 InstructionMark im(this); 5274 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5275 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5276 attributes.set_rex_vex_w_reverted(); 5277 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5278 emit_int8(0x57); 5279 emit_operand(dst, src); 5280 } 5281 5282 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5283 assert(VM_Version::supports_avx(), ""); 5284 InstructionMark im(this); 5285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5286 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5287 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 5288 emit_int8(0x57); 5289 emit_operand(dst, src); 5290 } 5291 5292 // Integer vector arithmetic 5293 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5294 assert(VM_Version::supports_avx() && (vector_len == 0) || 5295 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5296 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5297 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5298 emit_int8(0x01); 5299 emit_int8((unsigned char)(0xC0 | encode)); 5300 } 5301 5302 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5303 assert(VM_Version::supports_avx() && (vector_len == 0) || 5304 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2"); 5305 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5306 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5307 emit_int8(0x02); 5308 emit_int8((unsigned char)(0xC0 | encode)); 5309 } 5310 5311 void Assembler::paddb(XMMRegister dst, XMMRegister src) { 5312 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5313 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5314 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5315 emit_int8((unsigned char)0xFC); 5316 emit_int8((unsigned char)(0xC0 | encode)); 5317 } 5318 5319 void Assembler::paddw(XMMRegister dst, XMMRegister src) { 5320 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5321 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5322 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5323 emit_int8((unsigned char)0xFD); 5324 emit_int8((unsigned char)(0xC0 | encode)); 5325 } 5326 5327 void Assembler::paddd(XMMRegister dst, XMMRegister src) { 5328 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5329 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5330 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5331 emit_int8((unsigned char)0xFE); 5332 emit_int8((unsigned char)(0xC0 | encode)); 5333 } 5334 5335 void Assembler::paddd(XMMRegister dst, Address src) { 5336 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5337 InstructionMark im(this); 5338 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5339 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5340 emit_int8((unsigned char)0xFE); 5341 emit_operand(dst, src); 5342 } 5343 5344 void Assembler::paddq(XMMRegister dst, XMMRegister src) { 5345 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5346 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5347 attributes.set_rex_vex_w_reverted(); 5348 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5349 emit_int8((unsigned char)0xD4); 5350 emit_int8((unsigned char)(0xC0 | encode)); 5351 } 5352 5353 void Assembler::phaddw(XMMRegister dst, XMMRegister src) { 5354 assert(VM_Version::supports_sse3(), ""); 5355 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5356 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5357 emit_int8(0x01); 5358 emit_int8((unsigned char)(0xC0 | encode)); 5359 } 5360 5361 void Assembler::phaddd(XMMRegister dst, XMMRegister src) { 5362 assert(VM_Version::supports_sse3(), ""); 5363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 5364 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5365 emit_int8(0x02); 5366 emit_int8((unsigned char)(0xC0 | encode)); 5367 } 5368 5369 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5370 assert(UseAVX > 0, "requires some form of AVX"); 5371 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5372 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5373 emit_int8((unsigned char)0xFC); 5374 emit_int8((unsigned char)(0xC0 | encode)); 5375 } 5376 5377 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5378 assert(UseAVX > 0, "requires some form of AVX"); 5379 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5380 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5381 emit_int8((unsigned char)0xFD); 5382 emit_int8((unsigned char)(0xC0 | encode)); 5383 } 5384 5385 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5386 assert(UseAVX > 0, "requires some form of AVX"); 5387 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5388 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5389 emit_int8((unsigned char)0xFE); 5390 emit_int8((unsigned char)(0xC0 | encode)); 5391 } 5392 5393 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5394 assert(UseAVX > 0, "requires some form of AVX"); 5395 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5396 attributes.set_rex_vex_w_reverted(); 5397 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5398 emit_int8((unsigned char)0xD4); 5399 emit_int8((unsigned char)(0xC0 | encode)); 5400 } 5401 5402 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5403 assert(UseAVX > 0, "requires some form of AVX"); 5404 InstructionMark im(this); 5405 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5406 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5407 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5408 emit_int8((unsigned char)0xFC); 5409 emit_operand(dst, src); 5410 } 5411 5412 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5413 assert(UseAVX > 0, "requires some form of AVX"); 5414 InstructionMark im(this); 5415 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5416 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5417 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5418 emit_int8((unsigned char)0xFD); 5419 emit_operand(dst, src); 5420 } 5421 5422 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5423 assert(UseAVX > 0, "requires some form of AVX"); 5424 InstructionMark im(this); 5425 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5426 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5427 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5428 emit_int8((unsigned char)0xFE); 5429 emit_operand(dst, src); 5430 } 5431 5432 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5433 assert(UseAVX > 0, "requires some form of AVX"); 5434 InstructionMark im(this); 5435 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5436 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5437 attributes.set_rex_vex_w_reverted(); 5438 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5439 emit_int8((unsigned char)0xD4); 5440 emit_operand(dst, src); 5441 } 5442 5443 void Assembler::psubb(XMMRegister dst, XMMRegister src) { 5444 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5445 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5446 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5447 emit_int8((unsigned char)0xF8); 5448 emit_int8((unsigned char)(0xC0 | encode)); 5449 } 5450 5451 void Assembler::psubw(XMMRegister dst, XMMRegister src) { 5452 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5454 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5455 emit_int8((unsigned char)0xF9); 5456 emit_int8((unsigned char)(0xC0 | encode)); 5457 } 5458 5459 void Assembler::psubd(XMMRegister dst, XMMRegister src) { 5460 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5461 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5462 emit_int8((unsigned char)0xFA); 5463 emit_int8((unsigned char)(0xC0 | encode)); 5464 } 5465 5466 void Assembler::psubq(XMMRegister dst, XMMRegister src) { 5467 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5468 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5469 attributes.set_rex_vex_w_reverted(); 5470 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5471 emit_int8((unsigned char)0xFB); 5472 emit_int8((unsigned char)(0xC0 | encode)); 5473 } 5474 5475 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5476 assert(UseAVX > 0, "requires some form of AVX"); 5477 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5478 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5479 emit_int8((unsigned char)0xF8); 5480 emit_int8((unsigned char)(0xC0 | encode)); 5481 } 5482 5483 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5484 assert(UseAVX > 0, "requires some form of AVX"); 5485 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5486 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5487 emit_int8((unsigned char)0xF9); 5488 emit_int8((unsigned char)(0xC0 | encode)); 5489 } 5490 5491 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5492 assert(UseAVX > 0, "requires some form of AVX"); 5493 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5494 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5495 emit_int8((unsigned char)0xFA); 5496 emit_int8((unsigned char)(0xC0 | encode)); 5497 } 5498 5499 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5500 assert(UseAVX > 0, "requires some form of AVX"); 5501 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5502 attributes.set_rex_vex_w_reverted(); 5503 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5504 emit_int8((unsigned char)0xFB); 5505 emit_int8((unsigned char)(0xC0 | encode)); 5506 } 5507 5508 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5509 assert(UseAVX > 0, "requires some form of AVX"); 5510 InstructionMark im(this); 5511 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5512 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5513 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5514 emit_int8((unsigned char)0xF8); 5515 emit_operand(dst, src); 5516 } 5517 5518 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5519 assert(UseAVX > 0, "requires some form of AVX"); 5520 InstructionMark im(this); 5521 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5522 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5523 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5524 emit_int8((unsigned char)0xF9); 5525 emit_operand(dst, src); 5526 } 5527 5528 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5529 assert(UseAVX > 0, "requires some form of AVX"); 5530 InstructionMark im(this); 5531 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5532 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5533 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5534 emit_int8((unsigned char)0xFA); 5535 emit_operand(dst, src); 5536 } 5537 5538 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5539 assert(UseAVX > 0, "requires some form of AVX"); 5540 InstructionMark im(this); 5541 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5542 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5543 attributes.set_rex_vex_w_reverted(); 5544 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5545 emit_int8((unsigned char)0xFB); 5546 emit_operand(dst, src); 5547 } 5548 5549 void Assembler::pmullw(XMMRegister dst, XMMRegister src) { 5550 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5551 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5552 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5553 emit_int8((unsigned char)0xD5); 5554 emit_int8((unsigned char)(0xC0 | encode)); 5555 } 5556 5557 void Assembler::pmulld(XMMRegister dst, XMMRegister src) { 5558 assert(VM_Version::supports_sse4_1(), ""); 5559 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5560 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5561 emit_int8(0x40); 5562 emit_int8((unsigned char)(0xC0 | encode)); 5563 } 5564 5565 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5566 assert(UseAVX > 0, "requires some form of AVX"); 5567 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5568 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5569 emit_int8((unsigned char)0xD5); 5570 emit_int8((unsigned char)(0xC0 | encode)); 5571 } 5572 5573 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5574 assert(UseAVX > 0, "requires some form of AVX"); 5575 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5576 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5577 emit_int8(0x40); 5578 emit_int8((unsigned char)(0xC0 | encode)); 5579 } 5580 5581 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5582 assert(UseAVX > 2, "requires some form of EVEX"); 5583 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5584 attributes.set_is_evex_instruction(); 5585 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5586 emit_int8(0x40); 5587 emit_int8((unsigned char)(0xC0 | encode)); 5588 } 5589 5590 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5591 assert(UseAVX > 0, "requires some form of AVX"); 5592 InstructionMark im(this); 5593 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5594 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit); 5595 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5596 emit_int8((unsigned char)0xD5); 5597 emit_operand(dst, src); 5598 } 5599 5600 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5601 assert(UseAVX > 0, "requires some form of AVX"); 5602 InstructionMark im(this); 5603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5604 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5605 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5606 emit_int8(0x40); 5607 emit_operand(dst, src); 5608 } 5609 5610 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5611 assert(UseAVX > 2, "requires some form of EVEX"); 5612 InstructionMark im(this); 5613 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true); 5614 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit); 5615 attributes.set_is_evex_instruction(); 5616 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 5617 emit_int8(0x40); 5618 emit_operand(dst, src); 5619 } 5620 5621 // Shift packed integers left by specified number of bits. 5622 void Assembler::psllw(XMMRegister dst, int shift) { 5623 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5624 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5625 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 5626 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5627 emit_int8(0x71); 5628 emit_int8((unsigned char)(0xC0 | encode)); 5629 emit_int8(shift & 0xFF); 5630 } 5631 5632 void Assembler::pslld(XMMRegister dst, int shift) { 5633 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5634 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5635 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 5636 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5637 emit_int8(0x72); 5638 emit_int8((unsigned char)(0xC0 | encode)); 5639 emit_int8(shift & 0xFF); 5640 } 5641 5642 void Assembler::psllq(XMMRegister dst, int shift) { 5643 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5644 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5645 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 5646 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5647 emit_int8(0x73); 5648 emit_int8((unsigned char)(0xC0 | encode)); 5649 emit_int8(shift & 0xFF); 5650 } 5651 5652 void Assembler::psllw(XMMRegister dst, XMMRegister shift) { 5653 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5654 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5655 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5656 emit_int8((unsigned char)0xF1); 5657 emit_int8((unsigned char)(0xC0 | encode)); 5658 } 5659 5660 void Assembler::pslld(XMMRegister dst, XMMRegister shift) { 5661 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5662 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5663 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5664 emit_int8((unsigned char)0xF2); 5665 emit_int8((unsigned char)(0xC0 | encode)); 5666 } 5667 5668 void Assembler::psllq(XMMRegister dst, XMMRegister shift) { 5669 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5670 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5671 attributes.set_rex_vex_w_reverted(); 5672 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5673 emit_int8((unsigned char)0xF3); 5674 emit_int8((unsigned char)(0xC0 | encode)); 5675 } 5676 5677 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5678 assert(UseAVX > 0, "requires some form of AVX"); 5679 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5680 // XMM6 is for /6 encoding: 66 0F 71 /6 ib 5681 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5682 emit_int8(0x71); 5683 emit_int8((unsigned char)(0xC0 | encode)); 5684 emit_int8(shift & 0xFF); 5685 } 5686 5687 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5688 assert(UseAVX > 0, "requires some form of AVX"); 5689 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5690 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5691 // XMM6 is for /6 encoding: 66 0F 72 /6 ib 5692 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5693 emit_int8(0x72); 5694 emit_int8((unsigned char)(0xC0 | encode)); 5695 emit_int8(shift & 0xFF); 5696 } 5697 5698 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5699 assert(UseAVX > 0, "requires some form of AVX"); 5700 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5701 attributes.set_rex_vex_w_reverted(); 5702 // XMM6 is for /6 encoding: 66 0F 73 /6 ib 5703 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5704 emit_int8(0x73); 5705 emit_int8((unsigned char)(0xC0 | encode)); 5706 emit_int8(shift & 0xFF); 5707 } 5708 5709 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5710 assert(UseAVX > 0, "requires some form of AVX"); 5711 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5712 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5713 emit_int8((unsigned char)0xF1); 5714 emit_int8((unsigned char)(0xC0 | encode)); 5715 } 5716 5717 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5718 assert(UseAVX > 0, "requires some form of AVX"); 5719 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5720 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5721 emit_int8((unsigned char)0xF2); 5722 emit_int8((unsigned char)(0xC0 | encode)); 5723 } 5724 5725 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5726 assert(UseAVX > 0, "requires some form of AVX"); 5727 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5728 attributes.set_rex_vex_w_reverted(); 5729 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5730 emit_int8((unsigned char)0xF3); 5731 emit_int8((unsigned char)(0xC0 | encode)); 5732 } 5733 5734 // Shift packed integers logically right by specified number of bits. 5735 void Assembler::psrlw(XMMRegister dst, int shift) { 5736 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5737 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5738 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 5739 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5740 emit_int8(0x71); 5741 emit_int8((unsigned char)(0xC0 | encode)); 5742 emit_int8(shift & 0xFF); 5743 } 5744 5745 void Assembler::psrld(XMMRegister dst, int shift) { 5746 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5748 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 5749 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5750 emit_int8(0x72); 5751 emit_int8((unsigned char)(0xC0 | encode)); 5752 emit_int8(shift & 0xFF); 5753 } 5754 5755 void Assembler::psrlq(XMMRegister dst, int shift) { 5756 // Do not confuse it with psrldq SSE2 instruction which 5757 // shifts 128 bit value in xmm register by number of bytes. 5758 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5759 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5760 attributes.set_rex_vex_w_reverted(); 5761 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 5762 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5763 emit_int8(0x73); 5764 emit_int8((unsigned char)(0xC0 | encode)); 5765 emit_int8(shift & 0xFF); 5766 } 5767 5768 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) { 5769 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5770 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5771 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5772 emit_int8((unsigned char)0xD1); 5773 emit_int8((unsigned char)(0xC0 | encode)); 5774 } 5775 5776 void Assembler::psrld(XMMRegister dst, XMMRegister shift) { 5777 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5778 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5779 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5780 emit_int8((unsigned char)0xD2); 5781 emit_int8((unsigned char)(0xC0 | encode)); 5782 } 5783 5784 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) { 5785 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5786 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5787 attributes.set_rex_vex_w_reverted(); 5788 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5789 emit_int8((unsigned char)0xD3); 5790 emit_int8((unsigned char)(0xC0 | encode)); 5791 } 5792 5793 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5794 assert(UseAVX > 0, "requires some form of AVX"); 5795 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5796 // XMM2 is for /2 encoding: 66 0F 71 /2 ib 5797 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5798 emit_int8(0x71); 5799 emit_int8((unsigned char)(0xC0 | encode)); 5800 emit_int8(shift & 0xFF); 5801 } 5802 5803 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5804 assert(UseAVX > 0, "requires some form of AVX"); 5805 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5806 // XMM2 is for /2 encoding: 66 0F 72 /2 ib 5807 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5808 emit_int8(0x72); 5809 emit_int8((unsigned char)(0xC0 | encode)); 5810 emit_int8(shift & 0xFF); 5811 } 5812 5813 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5814 assert(UseAVX > 0, "requires some form of AVX"); 5815 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5816 attributes.set_rex_vex_w_reverted(); 5817 // XMM2 is for /2 encoding: 66 0F 73 /2 ib 5818 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5819 emit_int8(0x73); 5820 emit_int8((unsigned char)(0xC0 | encode)); 5821 emit_int8(shift & 0xFF); 5822 } 5823 5824 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5825 assert(UseAVX > 0, "requires some form of AVX"); 5826 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5827 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5828 emit_int8((unsigned char)0xD1); 5829 emit_int8((unsigned char)(0xC0 | encode)); 5830 } 5831 5832 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5833 assert(UseAVX > 0, "requires some form of AVX"); 5834 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5835 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5836 emit_int8((unsigned char)0xD2); 5837 emit_int8((unsigned char)(0xC0 | encode)); 5838 } 5839 5840 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5841 assert(UseAVX > 0, "requires some form of AVX"); 5842 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5843 attributes.set_rex_vex_w_reverted(); 5844 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5845 emit_int8((unsigned char)0xD3); 5846 emit_int8((unsigned char)(0xC0 | encode)); 5847 } 5848 5849 // Shift packed integers arithmetically right by specified number of bits. 5850 void Assembler::psraw(XMMRegister dst, int shift) { 5851 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5852 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5853 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5854 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5855 emit_int8(0x71); 5856 emit_int8((unsigned char)(0xC0 | encode)); 5857 emit_int8(shift & 0xFF); 5858 } 5859 5860 void Assembler::psrad(XMMRegister dst, int shift) { 5861 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5862 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5863 // XMM4 is for /4 encoding: 66 0F 72 /4 ib 5864 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5865 emit_int8(0x72); 5866 emit_int8((unsigned char)(0xC0 | encode)); 5867 emit_int8(shift & 0xFF); 5868 } 5869 5870 void Assembler::psraw(XMMRegister dst, XMMRegister shift) { 5871 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5872 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5873 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5874 emit_int8((unsigned char)0xE1); 5875 emit_int8((unsigned char)(0xC0 | encode)); 5876 } 5877 5878 void Assembler::psrad(XMMRegister dst, XMMRegister shift) { 5879 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5880 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5881 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5882 emit_int8((unsigned char)0xE2); 5883 emit_int8((unsigned char)(0xC0 | encode)); 5884 } 5885 5886 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5887 assert(UseAVX > 0, "requires some form of AVX"); 5888 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5889 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5890 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5891 emit_int8(0x71); 5892 emit_int8((unsigned char)(0xC0 | encode)); 5893 emit_int8(shift & 0xFF); 5894 } 5895 5896 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) { 5897 assert(UseAVX > 0, "requires some form of AVX"); 5898 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5899 // XMM4 is for /4 encoding: 66 0F 71 /4 ib 5900 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5901 emit_int8(0x72); 5902 emit_int8((unsigned char)(0xC0 | encode)); 5903 emit_int8(shift & 0xFF); 5904 } 5905 5906 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5907 assert(UseAVX > 0, "requires some form of AVX"); 5908 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 5909 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5910 emit_int8((unsigned char)0xE1); 5911 emit_int8((unsigned char)(0xC0 | encode)); 5912 } 5913 5914 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) { 5915 assert(UseAVX > 0, "requires some form of AVX"); 5916 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5917 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5918 emit_int8((unsigned char)0xE2); 5919 emit_int8((unsigned char)(0xC0 | encode)); 5920 } 5921 5922 5923 // logical operations packed integers 5924 void Assembler::pand(XMMRegister dst, XMMRegister src) { 5925 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5926 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5927 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5928 emit_int8((unsigned char)0xDB); 5929 emit_int8((unsigned char)(0xC0 | encode)); 5930 } 5931 5932 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5933 assert(UseAVX > 0, "requires some form of AVX"); 5934 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5935 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5936 emit_int8((unsigned char)0xDB); 5937 emit_int8((unsigned char)(0xC0 | encode)); 5938 } 5939 5940 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5941 assert(UseAVX > 0, "requires some form of AVX"); 5942 InstructionMark im(this); 5943 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5944 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5945 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5946 emit_int8((unsigned char)0xDB); 5947 emit_operand(dst, src); 5948 } 5949 5950 void Assembler::pandn(XMMRegister dst, XMMRegister src) { 5951 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5952 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5953 attributes.set_rex_vex_w_reverted(); 5954 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5955 emit_int8((unsigned char)0xDF); 5956 emit_int8((unsigned char)(0xC0 | encode)); 5957 } 5958 5959 void Assembler::por(XMMRegister dst, XMMRegister src) { 5960 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5961 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5962 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5963 emit_int8((unsigned char)0xEB); 5964 emit_int8((unsigned char)(0xC0 | encode)); 5965 } 5966 5967 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5968 assert(UseAVX > 0, "requires some form of AVX"); 5969 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5970 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5971 emit_int8((unsigned char)0xEB); 5972 emit_int8((unsigned char)(0xC0 | encode)); 5973 } 5974 5975 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 5976 assert(UseAVX > 0, "requires some form of AVX"); 5977 InstructionMark im(this); 5978 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5979 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 5980 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5981 emit_int8((unsigned char)0xEB); 5982 emit_operand(dst, src); 5983 } 5984 5985 void Assembler::pxor(XMMRegister dst, XMMRegister src) { 5986 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 5987 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5988 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5989 emit_int8((unsigned char)0xEF); 5990 emit_int8((unsigned char)(0xC0 | encode)); 5991 } 5992 5993 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 5994 assert(UseAVX > 0, "requires some form of AVX"); 5995 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 5996 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 5997 emit_int8((unsigned char)0xEF); 5998 emit_int8((unsigned char)(0xC0 | encode)); 5999 } 6000 6001 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 6002 assert(UseAVX > 0, "requires some form of AVX"); 6003 InstructionMark im(this); 6004 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6005 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit); 6006 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 6007 emit_int8((unsigned char)0xEF); 6008 emit_operand(dst, src); 6009 } 6010 6011 6012 // vinserti forms 6013 6014 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6015 assert(VM_Version::supports_avx2(), ""); 6016 assert(imm8 <= 0x01, "imm8: %u", imm8); 6017 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6018 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6019 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6020 emit_int8(0x38); 6021 emit_int8((unsigned char)(0xC0 | encode)); 6022 // 0x00 - insert into lower 128 bits 6023 // 0x01 - insert into upper 128 bits 6024 emit_int8(imm8 & 0x01); 6025 } 6026 6027 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6028 assert(VM_Version::supports_avx2(), ""); 6029 assert(dst != xnoreg, "sanity"); 6030 assert(imm8 <= 0x01, "imm8: %u", imm8); 6031 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6032 InstructionMark im(this); 6033 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6034 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6035 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6036 emit_int8(0x38); 6037 emit_operand(dst, src); 6038 // 0x00 - insert into lower 128 bits 6039 // 0x01 - insert into upper 128 bits 6040 emit_int8(imm8 & 0x01); 6041 } 6042 6043 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6044 assert(VM_Version::supports_evex(), ""); 6045 assert(imm8 <= 0x03, "imm8: %u", imm8); 6046 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6047 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6048 emit_int8(0x38); 6049 emit_int8((unsigned char)(0xC0 | encode)); 6050 // 0x00 - insert into q0 128 bits (0..127) 6051 // 0x01 - insert into q1 128 bits (128..255) 6052 // 0x02 - insert into q2 128 bits (256..383) 6053 // 0x03 - insert into q3 128 bits (384..511) 6054 emit_int8(imm8 & 0x03); 6055 } 6056 6057 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6058 assert(VM_Version::supports_avx(), ""); 6059 assert(dst != xnoreg, "sanity"); 6060 assert(imm8 <= 0x03, "imm8: %u", imm8); 6061 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6062 InstructionMark im(this); 6063 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6064 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6065 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6066 emit_int8(0x18); 6067 emit_operand(dst, src); 6068 // 0x00 - insert into q0 128 bits (0..127) 6069 // 0x01 - insert into q1 128 bits (128..255) 6070 // 0x02 - insert into q2 128 bits (256..383) 6071 // 0x03 - insert into q3 128 bits (384..511) 6072 emit_int8(imm8 & 0x03); 6073 } 6074 6075 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6076 assert(VM_Version::supports_evex(), ""); 6077 assert(imm8 <= 0x01, "imm8: %u", imm8); 6078 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6079 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6080 emit_int8(0x38); 6081 emit_int8((unsigned char)(0xC0 | encode)); 6082 // 0x00 - insert into lower 256 bits 6083 // 0x01 - insert into upper 256 bits 6084 emit_int8(imm8 & 0x01); 6085 } 6086 6087 6088 // vinsertf forms 6089 6090 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6091 assert(VM_Version::supports_avx(), ""); 6092 assert(imm8 <= 0x01, "imm8: %u", imm8); 6093 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6094 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6095 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6096 emit_int8(0x18); 6097 emit_int8((unsigned char)(0xC0 | encode)); 6098 // 0x00 - insert into lower 128 bits 6099 // 0x01 - insert into upper 128 bits 6100 emit_int8(imm8 & 0x01); 6101 } 6102 6103 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6104 assert(VM_Version::supports_avx(), ""); 6105 assert(dst != xnoreg, "sanity"); 6106 assert(imm8 <= 0x01, "imm8: %u", imm8); 6107 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6108 InstructionMark im(this); 6109 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6110 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6111 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6112 emit_int8(0x18); 6113 emit_operand(dst, src); 6114 // 0x00 - insert into lower 128 bits 6115 // 0x01 - insert into upper 128 bits 6116 emit_int8(imm8 & 0x01); 6117 } 6118 6119 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6120 assert(VM_Version::supports_evex(), ""); 6121 assert(imm8 <= 0x03, "imm8: %u", imm8); 6122 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6123 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6124 emit_int8(0x18); 6125 emit_int8((unsigned char)(0xC0 | encode)); 6126 // 0x00 - insert into q0 128 bits (0..127) 6127 // 0x01 - insert into q1 128 bits (128..255) 6128 // 0x02 - insert into q2 128 bits (256..383) 6129 // 0x03 - insert into q3 128 bits (384..511) 6130 emit_int8(imm8 & 0x03); 6131 } 6132 6133 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6134 assert(VM_Version::supports_avx(), ""); 6135 assert(dst != xnoreg, "sanity"); 6136 assert(imm8 <= 0x03, "imm8: %u", imm8); 6137 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6138 InstructionMark im(this); 6139 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6140 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6141 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6142 emit_int8(0x18); 6143 emit_operand(dst, src); 6144 // 0x00 - insert into q0 128 bits (0..127) 6145 // 0x01 - insert into q1 128 bits (128..255) 6146 // 0x02 - insert into q2 128 bits (256..383) 6147 // 0x03 - insert into q3 128 bits (384..511) 6148 emit_int8(imm8 & 0x03); 6149 } 6150 6151 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) { 6152 assert(VM_Version::supports_evex(), ""); 6153 assert(imm8 <= 0x01, "imm8: %u", imm8); 6154 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6155 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6156 emit_int8(0x1A); 6157 emit_int8((unsigned char)(0xC0 | encode)); 6158 // 0x00 - insert into lower 256 bits 6159 // 0x01 - insert into upper 256 bits 6160 emit_int8(imm8 & 0x01); 6161 } 6162 6163 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) { 6164 assert(VM_Version::supports_evex(), ""); 6165 assert(dst != xnoreg, "sanity"); 6166 assert(imm8 <= 0x01, "imm8: %u", imm8); 6167 InstructionMark im(this); 6168 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6169 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit); 6170 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6171 emit_int8(0x1A); 6172 emit_operand(dst, src); 6173 // 0x00 - insert into lower 256 bits 6174 // 0x01 - insert into upper 256 bits 6175 emit_int8(imm8 & 0x01); 6176 } 6177 6178 6179 // vextracti forms 6180 6181 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6182 assert(VM_Version::supports_avx(), ""); 6183 assert(imm8 <= 0x01, "imm8: %u", imm8); 6184 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6185 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6186 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6187 emit_int8(0x39); 6188 emit_int8((unsigned char)(0xC0 | encode)); 6189 // 0x00 - extract from lower 128 bits 6190 // 0x01 - extract from upper 128 bits 6191 emit_int8(imm8 & 0x01); 6192 } 6193 6194 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) { 6195 assert(VM_Version::supports_avx2(), ""); 6196 assert(src != xnoreg, "sanity"); 6197 assert(imm8 <= 0x01, "imm8: %u", imm8); 6198 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6199 InstructionMark im(this); 6200 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6201 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6202 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6203 emit_int8(0x39); 6204 emit_operand(src, dst); 6205 // 0x00 - extract from lower 128 bits 6206 // 0x01 - extract from upper 128 bits 6207 emit_int8(imm8 & 0x01); 6208 } 6209 6210 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6211 assert(VM_Version::supports_avx(), ""); 6212 assert(imm8 <= 0x03, "imm8: %u", imm8); 6213 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6214 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6215 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6216 emit_int8(0x39); 6217 emit_int8((unsigned char)(0xC0 | encode)); 6218 // 0x00 - extract from bits 127:0 6219 // 0x01 - extract from bits 255:128 6220 // 0x02 - extract from bits 383:256 6221 // 0x03 - extract from bits 511:384 6222 emit_int8(imm8 & 0x03); 6223 } 6224 6225 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) { 6226 assert(VM_Version::supports_evex(), ""); 6227 assert(src != xnoreg, "sanity"); 6228 assert(imm8 <= 0x03, "imm8: %u", imm8); 6229 InstructionMark im(this); 6230 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6231 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6232 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6233 emit_int8(0x39); 6234 emit_operand(src, dst); 6235 // 0x00 - extract from bits 127:0 6236 // 0x01 - extract from bits 255:128 6237 // 0x02 - extract from bits 383:256 6238 // 0x03 - extract from bits 511:384 6239 emit_int8(imm8 & 0x03); 6240 } 6241 6242 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6243 assert(VM_Version::supports_avx512dq(), ""); 6244 assert(imm8 <= 0x03, "imm8: %u", imm8); 6245 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6246 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6247 emit_int8(0x39); 6248 emit_int8((unsigned char)(0xC0 | encode)); 6249 // 0x00 - extract from bits 127:0 6250 // 0x01 - extract from bits 255:128 6251 // 0x02 - extract from bits 383:256 6252 // 0x03 - extract from bits 511:384 6253 emit_int8(imm8 & 0x03); 6254 } 6255 6256 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6257 assert(VM_Version::supports_evex(), ""); 6258 assert(imm8 <= 0x01, "imm8: %u", imm8); 6259 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6260 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6261 emit_int8(0x3B); 6262 emit_int8((unsigned char)(0xC0 | encode)); 6263 // 0x00 - extract from lower 256 bits 6264 // 0x01 - extract from upper 256 bits 6265 emit_int8(imm8 & 0x01); 6266 } 6267 6268 6269 // vextractf forms 6270 6271 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6272 assert(VM_Version::supports_avx(), ""); 6273 assert(imm8 <= 0x01, "imm8: %u", imm8); 6274 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6275 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6276 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6277 emit_int8(0x19); 6278 emit_int8((unsigned char)(0xC0 | encode)); 6279 // 0x00 - extract from lower 128 bits 6280 // 0x01 - extract from upper 128 bits 6281 emit_int8(imm8 & 0x01); 6282 } 6283 6284 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) { 6285 assert(VM_Version::supports_avx(), ""); 6286 assert(src != xnoreg, "sanity"); 6287 assert(imm8 <= 0x01, "imm8: %u", imm8); 6288 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit; 6289 InstructionMark im(this); 6290 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6291 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6292 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6293 emit_int8(0x19); 6294 emit_operand(src, dst); 6295 // 0x00 - extract from lower 128 bits 6296 // 0x01 - extract from upper 128 bits 6297 emit_int8(imm8 & 0x01); 6298 } 6299 6300 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6301 assert(VM_Version::supports_avx(), ""); 6302 assert(imm8 <= 0x03, "imm8: %u", imm8); 6303 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit; 6304 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6305 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6306 emit_int8(0x19); 6307 emit_int8((unsigned char)(0xC0 | encode)); 6308 // 0x00 - extract from bits 127:0 6309 // 0x01 - extract from bits 255:128 6310 // 0x02 - extract from bits 383:256 6311 // 0x03 - extract from bits 511:384 6312 emit_int8(imm8 & 0x03); 6313 } 6314 6315 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) { 6316 assert(VM_Version::supports_evex(), ""); 6317 assert(src != xnoreg, "sanity"); 6318 assert(imm8 <= 0x03, "imm8: %u", imm8); 6319 InstructionMark im(this); 6320 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6321 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit); 6322 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6323 emit_int8(0x19); 6324 emit_operand(src, dst); 6325 // 0x00 - extract from bits 127:0 6326 // 0x01 - extract from bits 255:128 6327 // 0x02 - extract from bits 383:256 6328 // 0x03 - extract from bits 511:384 6329 emit_int8(imm8 & 0x03); 6330 } 6331 6332 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6333 assert(VM_Version::supports_avx512dq(), ""); 6334 assert(imm8 <= 0x03, "imm8: %u", imm8); 6335 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6336 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6337 emit_int8(0x19); 6338 emit_int8((unsigned char)(0xC0 | encode)); 6339 // 0x00 - extract from bits 127:0 6340 // 0x01 - extract from bits 255:128 6341 // 0x02 - extract from bits 383:256 6342 // 0x03 - extract from bits 511:384 6343 emit_int8(imm8 & 0x03); 6344 } 6345 6346 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) { 6347 assert(VM_Version::supports_evex(), ""); 6348 assert(imm8 <= 0x01, "imm8: %u", imm8); 6349 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6350 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6351 emit_int8(0x1B); 6352 emit_int8((unsigned char)(0xC0 | encode)); 6353 // 0x00 - extract from lower 256 bits 6354 // 0x01 - extract from upper 256 bits 6355 emit_int8(imm8 & 0x01); 6356 } 6357 6358 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) { 6359 assert(VM_Version::supports_evex(), ""); 6360 assert(src != xnoreg, "sanity"); 6361 assert(imm8 <= 0x01, "imm8: %u", imm8); 6362 InstructionMark im(this); 6363 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false); 6364 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit); 6365 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6366 emit_int8(0x1B); 6367 emit_operand(src, dst); 6368 // 0x00 - extract from lower 256 bits 6369 // 0x01 - extract from upper 256 bits 6370 emit_int8(imm8 & 0x01); 6371 } 6372 6373 6374 // legacy word/dword replicate 6375 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 6376 assert(VM_Version::supports_avx2(), ""); 6377 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6378 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6379 emit_int8(0x79); 6380 emit_int8((unsigned char)(0xC0 | encode)); 6381 } 6382 6383 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) { 6384 assert(VM_Version::supports_avx2(), ""); 6385 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6386 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6387 emit_int8(0x58); 6388 emit_int8((unsigned char)(0xC0 | encode)); 6389 } 6390 6391 6392 // xmm/mem sourced byte/word/dword/qword replicate 6393 6394 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6395 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) { 6396 assert(VM_Version::supports_evex(), ""); 6397 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6398 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6399 emit_int8(0x78); 6400 emit_int8((unsigned char)(0xC0 | encode)); 6401 } 6402 6403 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) { 6404 assert(VM_Version::supports_evex(), ""); 6405 assert(dst != xnoreg, "sanity"); 6406 InstructionMark im(this); 6407 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6408 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit); 6409 // swap src<->dst for encoding 6410 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6411 emit_int8(0x78); 6412 emit_operand(dst, src); 6413 } 6414 6415 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6416 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) { 6417 assert(VM_Version::supports_evex(), ""); 6418 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6419 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6420 emit_int8(0x79); 6421 emit_int8((unsigned char)(0xC0 | encode)); 6422 } 6423 6424 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) { 6425 assert(VM_Version::supports_evex(), ""); 6426 assert(dst != xnoreg, "sanity"); 6427 InstructionMark im(this); 6428 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6429 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit); 6430 // swap src<->dst for encoding 6431 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6432 emit_int8(0x79); 6433 emit_operand(dst, src); 6434 } 6435 6436 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 6437 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) { 6438 assert(VM_Version::supports_evex(), ""); 6439 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6440 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6441 emit_int8(0x58); 6442 emit_int8((unsigned char)(0xC0 | encode)); 6443 } 6444 6445 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) { 6446 assert(VM_Version::supports_evex(), ""); 6447 assert(dst != xnoreg, "sanity"); 6448 InstructionMark im(this); 6449 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6450 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 6451 // swap src<->dst for encoding 6452 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6453 emit_int8(0x58); 6454 emit_operand(dst, src); 6455 } 6456 6457 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 6458 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) { 6459 assert(VM_Version::supports_evex(), ""); 6460 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6461 attributes.set_rex_vex_w_reverted(); 6462 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6463 emit_int8(0x59); 6464 emit_int8((unsigned char)(0xC0 | encode)); 6465 } 6466 6467 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) { 6468 assert(VM_Version::supports_evex(), ""); 6469 assert(dst != xnoreg, "sanity"); 6470 InstructionMark im(this); 6471 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6472 attributes.set_rex_vex_w_reverted(); 6473 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6474 // swap src<->dst for encoding 6475 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6476 emit_int8(0x59); 6477 emit_operand(dst, src); 6478 } 6479 6480 6481 // scalar single/double precision replicate 6482 6483 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL 6484 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) { 6485 assert(VM_Version::supports_evex(), ""); 6486 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6487 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6488 emit_int8(0x18); 6489 emit_int8((unsigned char)(0xC0 | encode)); 6490 } 6491 6492 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) { 6493 assert(VM_Version::supports_evex(), ""); 6494 assert(dst != xnoreg, "sanity"); 6495 InstructionMark im(this); 6496 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6497 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit); 6498 // swap src<->dst for encoding 6499 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6500 emit_int8(0x18); 6501 emit_operand(dst, src); 6502 } 6503 6504 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL 6505 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) { 6506 assert(VM_Version::supports_evex(), ""); 6507 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6508 attributes.set_rex_vex_w_reverted(); 6509 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6510 emit_int8(0x19); 6511 emit_int8((unsigned char)(0xC0 | encode)); 6512 } 6513 6514 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) { 6515 assert(VM_Version::supports_evex(), ""); 6516 assert(dst != xnoreg, "sanity"); 6517 InstructionMark im(this); 6518 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6519 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 6520 attributes.set_rex_vex_w_reverted(); 6521 // swap src<->dst for encoding 6522 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6523 emit_int8(0x19); 6524 emit_operand(dst, src); 6525 } 6526 6527 6528 // gpr source broadcast forms 6529 6530 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6531 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) { 6532 assert(VM_Version::supports_evex(), ""); 6533 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6534 attributes.set_is_evex_instruction(); 6535 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6536 emit_int8(0x7A); 6537 emit_int8((unsigned char)(0xC0 | encode)); 6538 } 6539 6540 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL 6541 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) { 6542 assert(VM_Version::supports_evex(), ""); 6543 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true); 6544 attributes.set_is_evex_instruction(); 6545 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6546 emit_int8(0x7B); 6547 emit_int8((unsigned char)(0xC0 | encode)); 6548 } 6549 6550 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL 6551 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) { 6552 assert(VM_Version::supports_evex(), ""); 6553 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6554 attributes.set_is_evex_instruction(); 6555 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6556 emit_int8(0x7C); 6557 emit_int8((unsigned char)(0xC0 | encode)); 6558 } 6559 6560 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL 6561 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) { 6562 assert(VM_Version::supports_evex(), ""); 6563 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true); 6564 attributes.set_is_evex_instruction(); 6565 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 6566 emit_int8(0x7C); 6567 emit_int8((unsigned char)(0xC0 | encode)); 6568 } 6569 6570 6571 // Carry-Less Multiplication Quadword 6572 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) { 6573 assert(VM_Version::supports_clmul(), ""); 6574 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 6575 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6576 emit_int8(0x44); 6577 emit_int8((unsigned char)(0xC0 | encode)); 6578 emit_int8((unsigned char)mask); 6579 } 6580 6581 // Carry-Less Multiplication Quadword 6582 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) { 6583 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), ""); 6584 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 6585 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 6586 emit_int8(0x44); 6587 emit_int8((unsigned char)(0xC0 | encode)); 6588 emit_int8((unsigned char)mask); 6589 } 6590 6591 void Assembler::vzeroupper() { 6592 assert(VM_Version::supports_avx(), ""); 6593 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 6594 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes); 6595 emit_int8(0x77); 6596 } 6597 6598 #ifndef _LP64 6599 // 32bit only pieces of the assembler 6600 6601 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) { 6602 // NO PREFIX AS NEVER 64BIT 6603 InstructionMark im(this); 6604 emit_int8((unsigned char)0x81); 6605 emit_int8((unsigned char)(0xF8 | src1->encoding())); 6606 emit_data(imm32, rspec, 0); 6607 } 6608 6609 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) { 6610 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs 6611 InstructionMark im(this); 6612 emit_int8((unsigned char)0x81); 6613 emit_operand(rdi, src1); 6614 emit_data(imm32, rspec, 0); 6615 } 6616 6617 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax, 6618 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded 6619 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise. 6620 void Assembler::cmpxchg8(Address adr) { 6621 InstructionMark im(this); 6622 emit_int8(0x0F); 6623 emit_int8((unsigned char)0xC7); 6624 emit_operand(rcx, adr); 6625 } 6626 6627 void Assembler::decl(Register dst) { 6628 // Don't use it directly. Use MacroAssembler::decrementl() instead. 6629 emit_int8(0x48 | dst->encoding()); 6630 } 6631 6632 #endif // _LP64 6633 6634 // 64bit typically doesn't use the x87 but needs to for the trig funcs 6635 6636 void Assembler::fabs() { 6637 emit_int8((unsigned char)0xD9); 6638 emit_int8((unsigned char)0xE1); 6639 } 6640 6641 void Assembler::fadd(int i) { 6642 emit_farith(0xD8, 0xC0, i); 6643 } 6644 6645 void Assembler::fadd_d(Address src) { 6646 InstructionMark im(this); 6647 emit_int8((unsigned char)0xDC); 6648 emit_operand32(rax, src); 6649 } 6650 6651 void Assembler::fadd_s(Address src) { 6652 InstructionMark im(this); 6653 emit_int8((unsigned char)0xD8); 6654 emit_operand32(rax, src); 6655 } 6656 6657 void Assembler::fadda(int i) { 6658 emit_farith(0xDC, 0xC0, i); 6659 } 6660 6661 void Assembler::faddp(int i) { 6662 emit_farith(0xDE, 0xC0, i); 6663 } 6664 6665 void Assembler::fchs() { 6666 emit_int8((unsigned char)0xD9); 6667 emit_int8((unsigned char)0xE0); 6668 } 6669 6670 void Assembler::fcom(int i) { 6671 emit_farith(0xD8, 0xD0, i); 6672 } 6673 6674 void Assembler::fcomp(int i) { 6675 emit_farith(0xD8, 0xD8, i); 6676 } 6677 6678 void Assembler::fcomp_d(Address src) { 6679 InstructionMark im(this); 6680 emit_int8((unsigned char)0xDC); 6681 emit_operand32(rbx, src); 6682 } 6683 6684 void Assembler::fcomp_s(Address src) { 6685 InstructionMark im(this); 6686 emit_int8((unsigned char)0xD8); 6687 emit_operand32(rbx, src); 6688 } 6689 6690 void Assembler::fcompp() { 6691 emit_int8((unsigned char)0xDE); 6692 emit_int8((unsigned char)0xD9); 6693 } 6694 6695 void Assembler::fcos() { 6696 emit_int8((unsigned char)0xD9); 6697 emit_int8((unsigned char)0xFF); 6698 } 6699 6700 void Assembler::fdecstp() { 6701 emit_int8((unsigned char)0xD9); 6702 emit_int8((unsigned char)0xF6); 6703 } 6704 6705 void Assembler::fdiv(int i) { 6706 emit_farith(0xD8, 0xF0, i); 6707 } 6708 6709 void Assembler::fdiv_d(Address src) { 6710 InstructionMark im(this); 6711 emit_int8((unsigned char)0xDC); 6712 emit_operand32(rsi, src); 6713 } 6714 6715 void Assembler::fdiv_s(Address src) { 6716 InstructionMark im(this); 6717 emit_int8((unsigned char)0xD8); 6718 emit_operand32(rsi, src); 6719 } 6720 6721 void Assembler::fdiva(int i) { 6722 emit_farith(0xDC, 0xF8, i); 6723 } 6724 6725 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994) 6726 // is erroneous for some of the floating-point instructions below. 6727 6728 void Assembler::fdivp(int i) { 6729 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong) 6730 } 6731 6732 void Assembler::fdivr(int i) { 6733 emit_farith(0xD8, 0xF8, i); 6734 } 6735 6736 void Assembler::fdivr_d(Address src) { 6737 InstructionMark im(this); 6738 emit_int8((unsigned char)0xDC); 6739 emit_operand32(rdi, src); 6740 } 6741 6742 void Assembler::fdivr_s(Address src) { 6743 InstructionMark im(this); 6744 emit_int8((unsigned char)0xD8); 6745 emit_operand32(rdi, src); 6746 } 6747 6748 void Assembler::fdivra(int i) { 6749 emit_farith(0xDC, 0xF0, i); 6750 } 6751 6752 void Assembler::fdivrp(int i) { 6753 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong) 6754 } 6755 6756 void Assembler::ffree(int i) { 6757 emit_farith(0xDD, 0xC0, i); 6758 } 6759 6760 void Assembler::fild_d(Address adr) { 6761 InstructionMark im(this); 6762 emit_int8((unsigned char)0xDF); 6763 emit_operand32(rbp, adr); 6764 } 6765 6766 void Assembler::fild_s(Address adr) { 6767 InstructionMark im(this); 6768 emit_int8((unsigned char)0xDB); 6769 emit_operand32(rax, adr); 6770 } 6771 6772 void Assembler::fincstp() { 6773 emit_int8((unsigned char)0xD9); 6774 emit_int8((unsigned char)0xF7); 6775 } 6776 6777 void Assembler::finit() { 6778 emit_int8((unsigned char)0x9B); 6779 emit_int8((unsigned char)0xDB); 6780 emit_int8((unsigned char)0xE3); 6781 } 6782 6783 void Assembler::fist_s(Address adr) { 6784 InstructionMark im(this); 6785 emit_int8((unsigned char)0xDB); 6786 emit_operand32(rdx, adr); 6787 } 6788 6789 void Assembler::fistp_d(Address adr) { 6790 InstructionMark im(this); 6791 emit_int8((unsigned char)0xDF); 6792 emit_operand32(rdi, adr); 6793 } 6794 6795 void Assembler::fistp_s(Address adr) { 6796 InstructionMark im(this); 6797 emit_int8((unsigned char)0xDB); 6798 emit_operand32(rbx, adr); 6799 } 6800 6801 void Assembler::fld1() { 6802 emit_int8((unsigned char)0xD9); 6803 emit_int8((unsigned char)0xE8); 6804 } 6805 6806 void Assembler::fld_d(Address adr) { 6807 InstructionMark im(this); 6808 emit_int8((unsigned char)0xDD); 6809 emit_operand32(rax, adr); 6810 } 6811 6812 void Assembler::fld_s(Address adr) { 6813 InstructionMark im(this); 6814 emit_int8((unsigned char)0xD9); 6815 emit_operand32(rax, adr); 6816 } 6817 6818 6819 void Assembler::fld_s(int index) { 6820 emit_farith(0xD9, 0xC0, index); 6821 } 6822 6823 void Assembler::fld_x(Address adr) { 6824 InstructionMark im(this); 6825 emit_int8((unsigned char)0xDB); 6826 emit_operand32(rbp, adr); 6827 } 6828 6829 void Assembler::fldcw(Address src) { 6830 InstructionMark im(this); 6831 emit_int8((unsigned char)0xD9); 6832 emit_operand32(rbp, src); 6833 } 6834 6835 void Assembler::fldenv(Address src) { 6836 InstructionMark im(this); 6837 emit_int8((unsigned char)0xD9); 6838 emit_operand32(rsp, src); 6839 } 6840 6841 void Assembler::fldlg2() { 6842 emit_int8((unsigned char)0xD9); 6843 emit_int8((unsigned char)0xEC); 6844 } 6845 6846 void Assembler::fldln2() { 6847 emit_int8((unsigned char)0xD9); 6848 emit_int8((unsigned char)0xED); 6849 } 6850 6851 void Assembler::fldz() { 6852 emit_int8((unsigned char)0xD9); 6853 emit_int8((unsigned char)0xEE); 6854 } 6855 6856 void Assembler::flog() { 6857 fldln2(); 6858 fxch(); 6859 fyl2x(); 6860 } 6861 6862 void Assembler::flog10() { 6863 fldlg2(); 6864 fxch(); 6865 fyl2x(); 6866 } 6867 6868 void Assembler::fmul(int i) { 6869 emit_farith(0xD8, 0xC8, i); 6870 } 6871 6872 void Assembler::fmul_d(Address src) { 6873 InstructionMark im(this); 6874 emit_int8((unsigned char)0xDC); 6875 emit_operand32(rcx, src); 6876 } 6877 6878 void Assembler::fmul_s(Address src) { 6879 InstructionMark im(this); 6880 emit_int8((unsigned char)0xD8); 6881 emit_operand32(rcx, src); 6882 } 6883 6884 void Assembler::fmula(int i) { 6885 emit_farith(0xDC, 0xC8, i); 6886 } 6887 6888 void Assembler::fmulp(int i) { 6889 emit_farith(0xDE, 0xC8, i); 6890 } 6891 6892 void Assembler::fnsave(Address dst) { 6893 InstructionMark im(this); 6894 emit_int8((unsigned char)0xDD); 6895 emit_operand32(rsi, dst); 6896 } 6897 6898 void Assembler::fnstcw(Address src) { 6899 InstructionMark im(this); 6900 emit_int8((unsigned char)0x9B); 6901 emit_int8((unsigned char)0xD9); 6902 emit_operand32(rdi, src); 6903 } 6904 6905 void Assembler::fnstsw_ax() { 6906 emit_int8((unsigned char)0xDF); 6907 emit_int8((unsigned char)0xE0); 6908 } 6909 6910 void Assembler::fprem() { 6911 emit_int8((unsigned char)0xD9); 6912 emit_int8((unsigned char)0xF8); 6913 } 6914 6915 void Assembler::fprem1() { 6916 emit_int8((unsigned char)0xD9); 6917 emit_int8((unsigned char)0xF5); 6918 } 6919 6920 void Assembler::frstor(Address src) { 6921 InstructionMark im(this); 6922 emit_int8((unsigned char)0xDD); 6923 emit_operand32(rsp, src); 6924 } 6925 6926 void Assembler::fsin() { 6927 emit_int8((unsigned char)0xD9); 6928 emit_int8((unsigned char)0xFE); 6929 } 6930 6931 void Assembler::fsqrt() { 6932 emit_int8((unsigned char)0xD9); 6933 emit_int8((unsigned char)0xFA); 6934 } 6935 6936 void Assembler::fst_d(Address adr) { 6937 InstructionMark im(this); 6938 emit_int8((unsigned char)0xDD); 6939 emit_operand32(rdx, adr); 6940 } 6941 6942 void Assembler::fst_s(Address adr) { 6943 InstructionMark im(this); 6944 emit_int8((unsigned char)0xD9); 6945 emit_operand32(rdx, adr); 6946 } 6947 6948 void Assembler::fstp_d(Address adr) { 6949 InstructionMark im(this); 6950 emit_int8((unsigned char)0xDD); 6951 emit_operand32(rbx, adr); 6952 } 6953 6954 void Assembler::fstp_d(int index) { 6955 emit_farith(0xDD, 0xD8, index); 6956 } 6957 6958 void Assembler::fstp_s(Address adr) { 6959 InstructionMark im(this); 6960 emit_int8((unsigned char)0xD9); 6961 emit_operand32(rbx, adr); 6962 } 6963 6964 void Assembler::fstp_x(Address adr) { 6965 InstructionMark im(this); 6966 emit_int8((unsigned char)0xDB); 6967 emit_operand32(rdi, adr); 6968 } 6969 6970 void Assembler::fsub(int i) { 6971 emit_farith(0xD8, 0xE0, i); 6972 } 6973 6974 void Assembler::fsub_d(Address src) { 6975 InstructionMark im(this); 6976 emit_int8((unsigned char)0xDC); 6977 emit_operand32(rsp, src); 6978 } 6979 6980 void Assembler::fsub_s(Address src) { 6981 InstructionMark im(this); 6982 emit_int8((unsigned char)0xD8); 6983 emit_operand32(rsp, src); 6984 } 6985 6986 void Assembler::fsuba(int i) { 6987 emit_farith(0xDC, 0xE8, i); 6988 } 6989 6990 void Assembler::fsubp(int i) { 6991 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong) 6992 } 6993 6994 void Assembler::fsubr(int i) { 6995 emit_farith(0xD8, 0xE8, i); 6996 } 6997 6998 void Assembler::fsubr_d(Address src) { 6999 InstructionMark im(this); 7000 emit_int8((unsigned char)0xDC); 7001 emit_operand32(rbp, src); 7002 } 7003 7004 void Assembler::fsubr_s(Address src) { 7005 InstructionMark im(this); 7006 emit_int8((unsigned char)0xD8); 7007 emit_operand32(rbp, src); 7008 } 7009 7010 void Assembler::fsubra(int i) { 7011 emit_farith(0xDC, 0xE0, i); 7012 } 7013 7014 void Assembler::fsubrp(int i) { 7015 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong) 7016 } 7017 7018 void Assembler::ftan() { 7019 emit_int8((unsigned char)0xD9); 7020 emit_int8((unsigned char)0xF2); 7021 emit_int8((unsigned char)0xDD); 7022 emit_int8((unsigned char)0xD8); 7023 } 7024 7025 void Assembler::ftst() { 7026 emit_int8((unsigned char)0xD9); 7027 emit_int8((unsigned char)0xE4); 7028 } 7029 7030 void Assembler::fucomi(int i) { 7031 // make sure the instruction is supported (introduced for P6, together with cmov) 7032 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7033 emit_farith(0xDB, 0xE8, i); 7034 } 7035 7036 void Assembler::fucomip(int i) { 7037 // make sure the instruction is supported (introduced for P6, together with cmov) 7038 guarantee(VM_Version::supports_cmov(), "illegal instruction"); 7039 emit_farith(0xDF, 0xE8, i); 7040 } 7041 7042 void Assembler::fwait() { 7043 emit_int8((unsigned char)0x9B); 7044 } 7045 7046 void Assembler::fxch(int i) { 7047 emit_farith(0xD9, 0xC8, i); 7048 } 7049 7050 void Assembler::fyl2x() { 7051 emit_int8((unsigned char)0xD9); 7052 emit_int8((unsigned char)0xF1); 7053 } 7054 7055 void Assembler::frndint() { 7056 emit_int8((unsigned char)0xD9); 7057 emit_int8((unsigned char)0xFC); 7058 } 7059 7060 void Assembler::f2xm1() { 7061 emit_int8((unsigned char)0xD9); 7062 emit_int8((unsigned char)0xF0); 7063 } 7064 7065 void Assembler::fldl2e() { 7066 emit_int8((unsigned char)0xD9); 7067 emit_int8((unsigned char)0xEA); 7068 } 7069 7070 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding. 7071 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 }; 7072 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding. 7073 static int simd_opc[4] = { 0, 0, 0x38, 0x3A }; 7074 7075 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding. 7076 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7077 if (pre > 0) { 7078 emit_int8(simd_pre[pre]); 7079 } 7080 if (rex_w) { 7081 prefixq(adr, xreg); 7082 } else { 7083 prefix(adr, xreg); 7084 } 7085 if (opc > 0) { 7086 emit_int8(0x0F); 7087 int opc2 = simd_opc[opc]; 7088 if (opc2 > 0) { 7089 emit_int8(opc2); 7090 } 7091 } 7092 } 7093 7094 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) { 7095 if (pre > 0) { 7096 emit_int8(simd_pre[pre]); 7097 } 7098 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc); 7099 if (opc > 0) { 7100 emit_int8(0x0F); 7101 int opc2 = simd_opc[opc]; 7102 if (opc2 > 0) { 7103 emit_int8(opc2); 7104 } 7105 } 7106 return encode; 7107 } 7108 7109 7110 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) { 7111 int vector_len = _attributes->get_vector_len(); 7112 bool vex_w = _attributes->is_rex_vex_w(); 7113 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) { 7114 prefix(VEX_3bytes); 7115 7116 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0); 7117 byte1 = (~byte1) & 0xE0; 7118 byte1 |= opc; 7119 emit_int8(byte1); 7120 7121 int byte2 = ((~nds_enc) & 0xf) << 3; 7122 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre; 7123 emit_int8(byte2); 7124 } else { 7125 prefix(VEX_2bytes); 7126 7127 int byte1 = vex_r ? VEX_R : 0; 7128 byte1 = (~byte1) & 0x80; 7129 byte1 |= ((~nds_enc) & 0xf) << 3; 7130 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre; 7131 emit_int8(byte1); 7132 } 7133 } 7134 7135 // This is a 4 byte encoding 7136 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){ 7137 // EVEX 0x62 prefix 7138 prefix(EVEX_4bytes); 7139 bool vex_w = _attributes->is_rex_vex_w(); 7140 int evex_encoding = (vex_w ? VEX_W : 0); 7141 // EVEX.b is not currently used for broadcast of single element or data rounding modes 7142 _attributes->set_evex_encoding(evex_encoding); 7143 7144 // P0: byte 2, initialized to RXBR`00mm 7145 // instead of not'd 7146 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0); 7147 byte2 = (~byte2) & 0xF0; 7148 // confine opc opcode extensions in mm bits to lower two bits 7149 // of form {0F, 0F_38, 0F_3A} 7150 byte2 |= opc; 7151 emit_int8(byte2); 7152 7153 // P1: byte 3 as Wvvvv1pp 7154 int byte3 = ((~nds_enc) & 0xf) << 3; 7155 // p[10] is always 1 7156 byte3 |= EVEX_F; 7157 byte3 |= (vex_w & 1) << 7; 7158 // confine pre opcode extensions in pp bits to lower two bits 7159 // of form {66, F3, F2} 7160 byte3 |= pre; 7161 emit_int8(byte3); 7162 7163 // P2: byte 4 as zL'Lbv'aaa 7164 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now) 7165 int byte4 = (_attributes->is_no_reg_mask()) ? 7166 0 : 7167 _attributes->get_embedded_opmask_register_specifier(); 7168 // EVEX.v` for extending EVEX.vvvv or VIDX 7169 byte4 |= (evex_v ? 0: EVEX_V); 7170 // third EXEC.b for broadcast actions 7171 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0); 7172 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024 7173 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5; 7174 // last is EVEX.z for zero/merge actions 7175 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0); 7176 emit_int8(byte4); 7177 } 7178 7179 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7180 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0; 7181 bool vex_b = adr.base_needs_rex(); 7182 bool vex_x = adr.index_needs_rex(); 7183 set_attributes(attributes); 7184 attributes->set_current_assembler(this); 7185 7186 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit 7187 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) { 7188 switch (attributes->get_vector_len()) { 7189 case AVX_128bit: 7190 case AVX_256bit: 7191 attributes->set_is_legacy_mode(); 7192 break; 7193 } 7194 } 7195 7196 // For pure EVEX check and see if this instruction 7197 // is allowed in legacy mode and has resources which will 7198 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition, 7199 // else that field is set when we encode to EVEX 7200 if (UseAVX > 2 && !attributes->is_legacy_mode() && 7201 !_is_managed && !attributes->is_evex_instruction()) { 7202 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) { 7203 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false); 7204 if (check_register_bank) { 7205 // check nds_enc and xreg_enc for upper bank usage 7206 if (nds_enc < 16 && xreg_enc < 16) { 7207 attributes->set_is_legacy_mode(); 7208 } 7209 } else { 7210 attributes->set_is_legacy_mode(); 7211 } 7212 } 7213 } 7214 7215 _is_managed = false; 7216 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7217 { 7218 bool evex_r = (xreg_enc >= 16); 7219 bool evex_v = (nds_enc >= 16); 7220 attributes->set_is_evex_instruction(); 7221 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7222 } else { 7223 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7224 attributes->set_rex_vex_w(false); 7225 } 7226 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7227 } 7228 } 7229 7230 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) { 7231 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0; 7232 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0; 7233 bool vex_x = false; 7234 set_attributes(attributes); 7235 attributes->set_current_assembler(this); 7236 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false); 7237 7238 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit 7239 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) { 7240 switch (attributes->get_vector_len()) { 7241 case AVX_128bit: 7242 case AVX_256bit: 7243 if (check_register_bank) { 7244 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) { 7245 // up propagate arithmetic instructions to meet RA requirements 7246 attributes->set_vector_len(AVX_512bit); 7247 } else { 7248 attributes->set_is_legacy_mode(); 7249 } 7250 } else { 7251 attributes->set_is_legacy_mode(); 7252 } 7253 break; 7254 } 7255 } 7256 7257 // For pure EVEX check and see if this instruction 7258 // is allowed in legacy mode and has resources which will 7259 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition, 7260 // else that field is set when we encode to EVEX 7261 if (UseAVX > 2 && !attributes->is_legacy_mode() && 7262 !_is_managed && !attributes->is_evex_instruction()) { 7263 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) { 7264 if (check_register_bank) { 7265 // check dst_enc, nds_enc and src_enc for upper bank usage 7266 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) { 7267 attributes->set_is_legacy_mode(); 7268 } 7269 } else { 7270 attributes->set_is_legacy_mode(); 7271 } 7272 } 7273 } 7274 7275 _is_managed = false; 7276 if (UseAVX > 2 && !attributes->is_legacy_mode()) 7277 { 7278 bool evex_r = (dst_enc >= 16); 7279 bool evex_v = (nds_enc >= 16); 7280 // can use vex_x as bank extender on rm encoding 7281 vex_x = (src_enc >= 16); 7282 attributes->set_is_evex_instruction(); 7283 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc); 7284 } else { 7285 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) { 7286 attributes->set_rex_vex_w(false); 7287 } 7288 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc); 7289 } 7290 7291 // return modrm byte components for operands 7292 return (((dst_enc & 7) << 3) | (src_enc & 7)); 7293 } 7294 7295 7296 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, 7297 VexOpcode opc, InstructionAttr *attributes) { 7298 if (UseAVX > 0) { 7299 int xreg_enc = xreg->encoding(); 7300 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7301 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes); 7302 } else { 7303 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding"); 7304 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w()); 7305 } 7306 } 7307 7308 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, 7309 VexOpcode opc, InstructionAttr *attributes) { 7310 int dst_enc = dst->encoding(); 7311 int src_enc = src->encoding(); 7312 if (UseAVX > 0) { 7313 int nds_enc = nds->is_valid() ? nds->encoding() : 0; 7314 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes); 7315 } else { 7316 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding"); 7317 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w()); 7318 } 7319 } 7320 7321 void Assembler::cmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) { 7322 assert(VM_Version::supports_avx(), ""); 7323 assert(!VM_Version::supports_evex(), ""); 7324 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7325 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 7326 emit_int8((unsigned char)0xC2); 7327 emit_int8((unsigned char)(0xC0 | encode)); 7328 emit_int8((unsigned char)(0xF & cop)); 7329 } 7330 7331 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) { 7332 assert(VM_Version::supports_avx(), ""); 7333 assert(!VM_Version::supports_evex(), ""); 7334 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7335 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes); 7336 emit_int8((unsigned char)0x4B); 7337 emit_int8((unsigned char)(0xC0 | encode)); 7338 int src2_enc = src2->encoding(); 7339 emit_int8((unsigned char)(0xF0 & src2_enc<<4)); 7340 } 7341 7342 void Assembler::shlxl(Register dst, Register src1, Register src2) { 7343 assert(VM_Version::supports_bmi2(), ""); 7344 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7345 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7346 emit_int8((unsigned char)0xF7); 7347 emit_int8((unsigned char)(0xC0 | encode)); 7348 } 7349 7350 void Assembler::shlxq(Register dst, Register src1, Register src2) { 7351 assert(VM_Version::supports_bmi2(), ""); 7352 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7353 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes); 7354 emit_int8((unsigned char)0xF7); 7355 emit_int8((unsigned char)(0xC0 | encode)); 7356 } 7357 7358 #ifndef _LP64 7359 7360 void Assembler::incl(Register dst) { 7361 // Don't use it directly. Use MacroAssembler::incrementl() instead. 7362 emit_int8(0x40 | dst->encoding()); 7363 } 7364 7365 void Assembler::lea(Register dst, Address src) { 7366 leal(dst, src); 7367 } 7368 7369 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) { 7370 InstructionMark im(this); 7371 emit_int8((unsigned char)0xC7); 7372 emit_operand(rax, dst); 7373 emit_data((int)imm32, rspec, 0); 7374 } 7375 7376 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) { 7377 InstructionMark im(this); 7378 int encode = prefix_and_encode(dst->encoding()); 7379 emit_int8((unsigned char)(0xB8 | encode)); 7380 emit_data((int)imm32, rspec, 0); 7381 } 7382 7383 void Assembler::popa() { // 32bit 7384 emit_int8(0x61); 7385 } 7386 7387 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) { 7388 InstructionMark im(this); 7389 emit_int8(0x68); 7390 emit_data(imm32, rspec, 0); 7391 } 7392 7393 void Assembler::pusha() { // 32bit 7394 emit_int8(0x60); 7395 } 7396 7397 void Assembler::set_byte_if_not_zero(Register dst) { 7398 emit_int8(0x0F); 7399 emit_int8((unsigned char)0x95); 7400 emit_int8((unsigned char)(0xE0 | dst->encoding())); 7401 } 7402 7403 void Assembler::shldl(Register dst, Register src) { 7404 emit_int8(0x0F); 7405 emit_int8((unsigned char)0xA5); 7406 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7407 } 7408 7409 // 0F A4 / r ib 7410 void Assembler::shldl(Register dst, Register src, int8_t imm8) { 7411 emit_int8(0x0F); 7412 emit_int8((unsigned char)0xA4); 7413 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7414 emit_int8(imm8); 7415 } 7416 7417 void Assembler::shrdl(Register dst, Register src) { 7418 emit_int8(0x0F); 7419 emit_int8((unsigned char)0xAD); 7420 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding())); 7421 } 7422 7423 #else // LP64 7424 7425 void Assembler::set_byte_if_not_zero(Register dst) { 7426 int enc = prefix_and_encode(dst->encoding(), true); 7427 emit_int8(0x0F); 7428 emit_int8((unsigned char)0x95); 7429 emit_int8((unsigned char)(0xE0 | enc)); 7430 } 7431 7432 // 64bit only pieces of the assembler 7433 // This should only be used by 64bit instructions that can use rip-relative 7434 // it cannot be used by instructions that want an immediate value. 7435 7436 bool Assembler::reachable(AddressLiteral adr) { 7437 int64_t disp; 7438 // None will force a 64bit literal to the code stream. Likely a placeholder 7439 // for something that will be patched later and we need to certain it will 7440 // always be reachable. 7441 if (adr.reloc() == relocInfo::none) { 7442 return false; 7443 } 7444 if (adr.reloc() == relocInfo::internal_word_type) { 7445 // This should be rip relative and easily reachable. 7446 return true; 7447 } 7448 if (adr.reloc() == relocInfo::virtual_call_type || 7449 adr.reloc() == relocInfo::opt_virtual_call_type || 7450 adr.reloc() == relocInfo::static_call_type || 7451 adr.reloc() == relocInfo::static_stub_type ) { 7452 // This should be rip relative within the code cache and easily 7453 // reachable until we get huge code caches. (At which point 7454 // ic code is going to have issues). 7455 return true; 7456 } 7457 if (adr.reloc() != relocInfo::external_word_type && 7458 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special 7459 adr.reloc() != relocInfo::poll_type && // relocs to identify them 7460 adr.reloc() != relocInfo::runtime_call_type ) { 7461 return false; 7462 } 7463 7464 // Stress the correction code 7465 if (ForceUnreachable) { 7466 // Must be runtimecall reloc, see if it is in the codecache 7467 // Flipping stuff in the codecache to be unreachable causes issues 7468 // with things like inline caches where the additional instructions 7469 // are not handled. 7470 if (CodeCache::find_blob(adr._target) == NULL) { 7471 return false; 7472 } 7473 } 7474 // For external_word_type/runtime_call_type if it is reachable from where we 7475 // are now (possibly a temp buffer) and where we might end up 7476 // anywhere in the codeCache then we are always reachable. 7477 // This would have to change if we ever save/restore shared code 7478 // to be more pessimistic. 7479 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int)); 7480 if (!is_simm32(disp)) return false; 7481 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int)); 7482 if (!is_simm32(disp)) return false; 7483 7484 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int)); 7485 7486 // Because rip relative is a disp + address_of_next_instruction and we 7487 // don't know the value of address_of_next_instruction we apply a fudge factor 7488 // to make sure we will be ok no matter the size of the instruction we get placed into. 7489 // We don't have to fudge the checks above here because they are already worst case. 7490 7491 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal 7492 // + 4 because better safe than sorry. 7493 const int fudge = 12 + 4; 7494 if (disp < 0) { 7495 disp -= fudge; 7496 } else { 7497 disp += fudge; 7498 } 7499 return is_simm32(disp); 7500 } 7501 7502 // Check if the polling page is not reachable from the code cache using rip-relative 7503 // addressing. 7504 bool Assembler::is_polling_page_far() { 7505 intptr_t addr = (intptr_t)os::get_polling_page(); 7506 return ForceUnreachable || 7507 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) || 7508 !is_simm32(addr - (intptr_t)CodeCache::high_bound()); 7509 } 7510 7511 void Assembler::emit_data64(jlong data, 7512 relocInfo::relocType rtype, 7513 int format) { 7514 if (rtype == relocInfo::none) { 7515 emit_int64(data); 7516 } else { 7517 emit_data64(data, Relocation::spec_simple(rtype), format); 7518 } 7519 } 7520 7521 void Assembler::emit_data64(jlong data, 7522 RelocationHolder const& rspec, 7523 int format) { 7524 assert(imm_operand == 0, "default format must be immediate in this file"); 7525 assert(imm_operand == format, "must be immediate"); 7526 assert(inst_mark() != NULL, "must be inside InstructionMark"); 7527 // Do not use AbstractAssembler::relocate, which is not intended for 7528 // embedded words. Instead, relocate to the enclosing instruction. 7529 code_section()->relocate(inst_mark(), rspec, format); 7530 #ifdef ASSERT 7531 check_relocation(rspec, format); 7532 #endif 7533 emit_int64(data); 7534 } 7535 7536 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) { 7537 if (reg_enc >= 8) { 7538 prefix(REX_B); 7539 reg_enc -= 8; 7540 } else if (byteinst && reg_enc >= 4) { 7541 prefix(REX); 7542 } 7543 return reg_enc; 7544 } 7545 7546 int Assembler::prefixq_and_encode(int reg_enc) { 7547 if (reg_enc < 8) { 7548 prefix(REX_W); 7549 } else { 7550 prefix(REX_WB); 7551 reg_enc -= 8; 7552 } 7553 return reg_enc; 7554 } 7555 7556 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) { 7557 if (dst_enc < 8) { 7558 if (src_enc >= 8) { 7559 prefix(REX_B); 7560 src_enc -= 8; 7561 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) { 7562 prefix(REX); 7563 } 7564 } else { 7565 if (src_enc < 8) { 7566 prefix(REX_R); 7567 } else { 7568 prefix(REX_RB); 7569 src_enc -= 8; 7570 } 7571 dst_enc -= 8; 7572 } 7573 return dst_enc << 3 | src_enc; 7574 } 7575 7576 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) { 7577 if (dst_enc < 8) { 7578 if (src_enc < 8) { 7579 prefix(REX_W); 7580 } else { 7581 prefix(REX_WB); 7582 src_enc -= 8; 7583 } 7584 } else { 7585 if (src_enc < 8) { 7586 prefix(REX_WR); 7587 } else { 7588 prefix(REX_WRB); 7589 src_enc -= 8; 7590 } 7591 dst_enc -= 8; 7592 } 7593 return dst_enc << 3 | src_enc; 7594 } 7595 7596 void Assembler::prefix(Register reg) { 7597 if (reg->encoding() >= 8) { 7598 prefix(REX_B); 7599 } 7600 } 7601 7602 void Assembler::prefix(Register dst, Register src, Prefix p) { 7603 if (src->encoding() >= 8) { 7604 p = (Prefix)(p | REX_B); 7605 } 7606 if (dst->encoding() >= 8) { 7607 p = (Prefix)( p | REX_R); 7608 } 7609 if (p != Prefix_EMPTY) { 7610 // do not generate an empty prefix 7611 prefix(p); 7612 } 7613 } 7614 7615 void Assembler::prefix(Register dst, Address adr, Prefix p) { 7616 if (adr.base_needs_rex()) { 7617 if (adr.index_needs_rex()) { 7618 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 7619 } else { 7620 prefix(REX_B); 7621 } 7622 } else { 7623 if (adr.index_needs_rex()) { 7624 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X"); 7625 } 7626 } 7627 if (dst->encoding() >= 8) { 7628 p = (Prefix)(p | REX_R); 7629 } 7630 if (p != Prefix_EMPTY) { 7631 // do not generate an empty prefix 7632 prefix(p); 7633 } 7634 } 7635 7636 void Assembler::prefix(Address adr) { 7637 if (adr.base_needs_rex()) { 7638 if (adr.index_needs_rex()) { 7639 prefix(REX_XB); 7640 } else { 7641 prefix(REX_B); 7642 } 7643 } else { 7644 if (adr.index_needs_rex()) { 7645 prefix(REX_X); 7646 } 7647 } 7648 } 7649 7650 void Assembler::prefixq(Address adr) { 7651 if (adr.base_needs_rex()) { 7652 if (adr.index_needs_rex()) { 7653 prefix(REX_WXB); 7654 } else { 7655 prefix(REX_WB); 7656 } 7657 } else { 7658 if (adr.index_needs_rex()) { 7659 prefix(REX_WX); 7660 } else { 7661 prefix(REX_W); 7662 } 7663 } 7664 } 7665 7666 7667 void Assembler::prefix(Address adr, Register reg, bool byteinst) { 7668 if (reg->encoding() < 8) { 7669 if (adr.base_needs_rex()) { 7670 if (adr.index_needs_rex()) { 7671 prefix(REX_XB); 7672 } else { 7673 prefix(REX_B); 7674 } 7675 } else { 7676 if (adr.index_needs_rex()) { 7677 prefix(REX_X); 7678 } else if (byteinst && reg->encoding() >= 4 ) { 7679 prefix(REX); 7680 } 7681 } 7682 } else { 7683 if (adr.base_needs_rex()) { 7684 if (adr.index_needs_rex()) { 7685 prefix(REX_RXB); 7686 } else { 7687 prefix(REX_RB); 7688 } 7689 } else { 7690 if (adr.index_needs_rex()) { 7691 prefix(REX_RX); 7692 } else { 7693 prefix(REX_R); 7694 } 7695 } 7696 } 7697 } 7698 7699 void Assembler::prefixq(Address adr, Register src) { 7700 if (src->encoding() < 8) { 7701 if (adr.base_needs_rex()) { 7702 if (adr.index_needs_rex()) { 7703 prefix(REX_WXB); 7704 } else { 7705 prefix(REX_WB); 7706 } 7707 } else { 7708 if (adr.index_needs_rex()) { 7709 prefix(REX_WX); 7710 } else { 7711 prefix(REX_W); 7712 } 7713 } 7714 } else { 7715 if (adr.base_needs_rex()) { 7716 if (adr.index_needs_rex()) { 7717 prefix(REX_WRXB); 7718 } else { 7719 prefix(REX_WRB); 7720 } 7721 } else { 7722 if (adr.index_needs_rex()) { 7723 prefix(REX_WRX); 7724 } else { 7725 prefix(REX_WR); 7726 } 7727 } 7728 } 7729 } 7730 7731 void Assembler::prefix(Address adr, XMMRegister reg) { 7732 if (reg->encoding() < 8) { 7733 if (adr.base_needs_rex()) { 7734 if (adr.index_needs_rex()) { 7735 prefix(REX_XB); 7736 } else { 7737 prefix(REX_B); 7738 } 7739 } else { 7740 if (adr.index_needs_rex()) { 7741 prefix(REX_X); 7742 } 7743 } 7744 } else { 7745 if (adr.base_needs_rex()) { 7746 if (adr.index_needs_rex()) { 7747 prefix(REX_RXB); 7748 } else { 7749 prefix(REX_RB); 7750 } 7751 } else { 7752 if (adr.index_needs_rex()) { 7753 prefix(REX_RX); 7754 } else { 7755 prefix(REX_R); 7756 } 7757 } 7758 } 7759 } 7760 7761 void Assembler::prefixq(Address adr, XMMRegister src) { 7762 if (src->encoding() < 8) { 7763 if (adr.base_needs_rex()) { 7764 if (adr.index_needs_rex()) { 7765 prefix(REX_WXB); 7766 } else { 7767 prefix(REX_WB); 7768 } 7769 } else { 7770 if (adr.index_needs_rex()) { 7771 prefix(REX_WX); 7772 } else { 7773 prefix(REX_W); 7774 } 7775 } 7776 } else { 7777 if (adr.base_needs_rex()) { 7778 if (adr.index_needs_rex()) { 7779 prefix(REX_WRXB); 7780 } else { 7781 prefix(REX_WRB); 7782 } 7783 } else { 7784 if (adr.index_needs_rex()) { 7785 prefix(REX_WRX); 7786 } else { 7787 prefix(REX_WR); 7788 } 7789 } 7790 } 7791 } 7792 7793 void Assembler::adcq(Register dst, int32_t imm32) { 7794 (void) prefixq_and_encode(dst->encoding()); 7795 emit_arith(0x81, 0xD0, dst, imm32); 7796 } 7797 7798 void Assembler::adcq(Register dst, Address src) { 7799 InstructionMark im(this); 7800 prefixq(src, dst); 7801 emit_int8(0x13); 7802 emit_operand(dst, src); 7803 } 7804 7805 void Assembler::adcq(Register dst, Register src) { 7806 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7807 emit_arith(0x13, 0xC0, dst, src); 7808 } 7809 7810 void Assembler::addq(Address dst, int32_t imm32) { 7811 InstructionMark im(this); 7812 prefixq(dst); 7813 emit_arith_operand(0x81, rax, dst,imm32); 7814 } 7815 7816 void Assembler::addq(Address dst, Register src) { 7817 InstructionMark im(this); 7818 prefixq(dst, src); 7819 emit_int8(0x01); 7820 emit_operand(src, dst); 7821 } 7822 7823 void Assembler::addq(Register dst, int32_t imm32) { 7824 (void) prefixq_and_encode(dst->encoding()); 7825 emit_arith(0x81, 0xC0, dst, imm32); 7826 } 7827 7828 void Assembler::addq(Register dst, Address src) { 7829 InstructionMark im(this); 7830 prefixq(src, dst); 7831 emit_int8(0x03); 7832 emit_operand(dst, src); 7833 } 7834 7835 void Assembler::addq(Register dst, Register src) { 7836 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7837 emit_arith(0x03, 0xC0, dst, src); 7838 } 7839 7840 void Assembler::adcxq(Register dst, Register src) { 7841 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 7842 emit_int8((unsigned char)0x66); 7843 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7844 emit_int8(0x0F); 7845 emit_int8(0x38); 7846 emit_int8((unsigned char)0xF6); 7847 emit_int8((unsigned char)(0xC0 | encode)); 7848 } 7849 7850 void Assembler::adoxq(Register dst, Register src) { 7851 //assert(VM_Version::supports_adx(), "adx instructions not supported"); 7852 emit_int8((unsigned char)0xF3); 7853 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7854 emit_int8(0x0F); 7855 emit_int8(0x38); 7856 emit_int8((unsigned char)0xF6); 7857 emit_int8((unsigned char)(0xC0 | encode)); 7858 } 7859 7860 void Assembler::andq(Address dst, int32_t imm32) { 7861 InstructionMark im(this); 7862 prefixq(dst); 7863 emit_int8((unsigned char)0x81); 7864 emit_operand(rsp, dst, 4); 7865 emit_int32(imm32); 7866 } 7867 7868 void Assembler::andq(Register dst, int32_t imm32) { 7869 (void) prefixq_and_encode(dst->encoding()); 7870 emit_arith(0x81, 0xE0, dst, imm32); 7871 } 7872 7873 void Assembler::andq(Register dst, Address src) { 7874 InstructionMark im(this); 7875 prefixq(src, dst); 7876 emit_int8(0x23); 7877 emit_operand(dst, src); 7878 } 7879 7880 void Assembler::andq(Register dst, Register src) { 7881 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 7882 emit_arith(0x23, 0xC0, dst, src); 7883 } 7884 7885 void Assembler::andnq(Register dst, Register src1, Register src2) { 7886 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7887 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7888 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7889 emit_int8((unsigned char)0xF2); 7890 emit_int8((unsigned char)(0xC0 | encode)); 7891 } 7892 7893 void Assembler::andnq(Register dst, Register src1, Address src2) { 7894 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7895 InstructionMark im(this); 7896 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7897 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7898 emit_int8((unsigned char)0xF2); 7899 emit_operand(dst, src2); 7900 } 7901 7902 void Assembler::bsfq(Register dst, Register src) { 7903 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7904 emit_int8(0x0F); 7905 emit_int8((unsigned char)0xBC); 7906 emit_int8((unsigned char)(0xC0 | encode)); 7907 } 7908 7909 void Assembler::bsrq(Register dst, Register src) { 7910 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7911 emit_int8(0x0F); 7912 emit_int8((unsigned char)0xBD); 7913 emit_int8((unsigned char)(0xC0 | encode)); 7914 } 7915 7916 void Assembler::bswapq(Register reg) { 7917 int encode = prefixq_and_encode(reg->encoding()); 7918 emit_int8(0x0F); 7919 emit_int8((unsigned char)(0xC8 | encode)); 7920 } 7921 7922 void Assembler::blsiq(Register dst, Register src) { 7923 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7924 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7925 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7926 emit_int8((unsigned char)0xF3); 7927 emit_int8((unsigned char)(0xC0 | encode)); 7928 } 7929 7930 void Assembler::blsiq(Register dst, Address src) { 7931 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7932 InstructionMark im(this); 7933 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7934 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7935 emit_int8((unsigned char)0xF3); 7936 emit_operand(rbx, src); 7937 } 7938 7939 void Assembler::blsmskq(Register dst, Register src) { 7940 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7941 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7942 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7943 emit_int8((unsigned char)0xF3); 7944 emit_int8((unsigned char)(0xC0 | encode)); 7945 } 7946 7947 void Assembler::blsmskq(Register dst, Address src) { 7948 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7949 InstructionMark im(this); 7950 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7951 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7952 emit_int8((unsigned char)0xF3); 7953 emit_operand(rdx, src); 7954 } 7955 7956 void Assembler::blsrq(Register dst, Register src) { 7957 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7958 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7959 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7960 emit_int8((unsigned char)0xF3); 7961 emit_int8((unsigned char)(0xC0 | encode)); 7962 } 7963 7964 void Assembler::blsrq(Register dst, Address src) { 7965 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported"); 7966 InstructionMark im(this); 7967 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 7968 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes); 7969 emit_int8((unsigned char)0xF3); 7970 emit_operand(rcx, src); 7971 } 7972 7973 void Assembler::cdqq() { 7974 prefix(REX_W); 7975 emit_int8((unsigned char)0x99); 7976 } 7977 7978 void Assembler::clflush(Address adr) { 7979 prefix(adr); 7980 emit_int8(0x0F); 7981 emit_int8((unsigned char)0xAE); 7982 emit_operand(rdi, adr); 7983 } 7984 7985 void Assembler::cmovq(Condition cc, Register dst, Register src) { 7986 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 7987 emit_int8(0x0F); 7988 emit_int8(0x40 | cc); 7989 emit_int8((unsigned char)(0xC0 | encode)); 7990 } 7991 7992 void Assembler::cmovq(Condition cc, Register dst, Address src) { 7993 InstructionMark im(this); 7994 prefixq(src, dst); 7995 emit_int8(0x0F); 7996 emit_int8(0x40 | cc); 7997 emit_operand(dst, src); 7998 } 7999 8000 void Assembler::cmpq(Address dst, int32_t imm32) { 8001 InstructionMark im(this); 8002 prefixq(dst); 8003 emit_int8((unsigned char)0x81); 8004 emit_operand(rdi, dst, 4); 8005 emit_int32(imm32); 8006 } 8007 8008 void Assembler::cmpq(Register dst, int32_t imm32) { 8009 (void) prefixq_and_encode(dst->encoding()); 8010 emit_arith(0x81, 0xF8, dst, imm32); 8011 } 8012 8013 void Assembler::cmpq(Address dst, Register src) { 8014 InstructionMark im(this); 8015 prefixq(dst, src); 8016 emit_int8(0x3B); 8017 emit_operand(src, dst); 8018 } 8019 8020 void Assembler::cmpq(Register dst, Register src) { 8021 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8022 emit_arith(0x3B, 0xC0, dst, src); 8023 } 8024 8025 void Assembler::cmpq(Register dst, Address src) { 8026 InstructionMark im(this); 8027 prefixq(src, dst); 8028 emit_int8(0x3B); 8029 emit_operand(dst, src); 8030 } 8031 8032 void Assembler::cmpxchgq(Register reg, Address adr) { 8033 InstructionMark im(this); 8034 prefixq(adr, reg); 8035 emit_int8(0x0F); 8036 emit_int8((unsigned char)0xB1); 8037 emit_operand(reg, adr); 8038 } 8039 8040 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) { 8041 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8042 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8043 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8044 emit_int8(0x2A); 8045 emit_int8((unsigned char)(0xC0 | encode)); 8046 } 8047 8048 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) { 8049 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8050 InstructionMark im(this); 8051 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8052 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8053 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8054 emit_int8(0x2A); 8055 emit_operand(dst, src); 8056 } 8057 8058 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) { 8059 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8060 InstructionMark im(this); 8061 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8062 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit); 8063 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8064 emit_int8(0x2A); 8065 emit_operand(dst, src); 8066 } 8067 8068 void Assembler::cvttsd2siq(Register dst, XMMRegister src) { 8069 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8070 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8071 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes); 8072 emit_int8(0x2C); 8073 emit_int8((unsigned char)(0xC0 | encode)); 8074 } 8075 8076 void Assembler::cvttss2siq(Register dst, XMMRegister src) { 8077 NOT_LP64(assert(VM_Version::supports_sse(), "")); 8078 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8079 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes); 8080 emit_int8(0x2C); 8081 emit_int8((unsigned char)(0xC0 | encode)); 8082 } 8083 8084 void Assembler::decl(Register dst) { 8085 // Don't use it directly. Use MacroAssembler::decrementl() instead. 8086 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode) 8087 int encode = prefix_and_encode(dst->encoding()); 8088 emit_int8((unsigned char)0xFF); 8089 emit_int8((unsigned char)(0xC8 | encode)); 8090 } 8091 8092 void Assembler::decq(Register dst) { 8093 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8094 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8095 int encode = prefixq_and_encode(dst->encoding()); 8096 emit_int8((unsigned char)0xFF); 8097 emit_int8(0xC8 | encode); 8098 } 8099 8100 void Assembler::decq(Address dst) { 8101 // Don't use it directly. Use MacroAssembler::decrementq() instead. 8102 InstructionMark im(this); 8103 prefixq(dst); 8104 emit_int8((unsigned char)0xFF); 8105 emit_operand(rcx, dst); 8106 } 8107 8108 void Assembler::fxrstor(Address src) { 8109 prefixq(src); 8110 emit_int8(0x0F); 8111 emit_int8((unsigned char)0xAE); 8112 emit_operand(as_Register(1), src); 8113 } 8114 8115 void Assembler::xrstor(Address src) { 8116 prefixq(src); 8117 emit_int8(0x0F); 8118 emit_int8((unsigned char)0xAE); 8119 emit_operand(as_Register(5), src); 8120 } 8121 8122 void Assembler::fxsave(Address dst) { 8123 prefixq(dst); 8124 emit_int8(0x0F); 8125 emit_int8((unsigned char)0xAE); 8126 emit_operand(as_Register(0), dst); 8127 } 8128 8129 void Assembler::xsave(Address dst) { 8130 prefixq(dst); 8131 emit_int8(0x0F); 8132 emit_int8((unsigned char)0xAE); 8133 emit_operand(as_Register(4), dst); 8134 } 8135 8136 void Assembler::idivq(Register src) { 8137 int encode = prefixq_and_encode(src->encoding()); 8138 emit_int8((unsigned char)0xF7); 8139 emit_int8((unsigned char)(0xF8 | encode)); 8140 } 8141 8142 void Assembler::imulq(Register dst, Register src) { 8143 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8144 emit_int8(0x0F); 8145 emit_int8((unsigned char)0xAF); 8146 emit_int8((unsigned char)(0xC0 | encode)); 8147 } 8148 8149 void Assembler::imulq(Register dst, Register src, int value) { 8150 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8151 if (is8bit(value)) { 8152 emit_int8(0x6B); 8153 emit_int8((unsigned char)(0xC0 | encode)); 8154 emit_int8(value & 0xFF); 8155 } else { 8156 emit_int8(0x69); 8157 emit_int8((unsigned char)(0xC0 | encode)); 8158 emit_int32(value); 8159 } 8160 } 8161 8162 void Assembler::imulq(Register dst, Address src) { 8163 InstructionMark im(this); 8164 prefixq(src, dst); 8165 emit_int8(0x0F); 8166 emit_int8((unsigned char) 0xAF); 8167 emit_operand(dst, src); 8168 } 8169 8170 void Assembler::incl(Register dst) { 8171 // Don't use it directly. Use MacroAssembler::incrementl() instead. 8172 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8173 int encode = prefix_and_encode(dst->encoding()); 8174 emit_int8((unsigned char)0xFF); 8175 emit_int8((unsigned char)(0xC0 | encode)); 8176 } 8177 8178 void Assembler::incq(Register dst) { 8179 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8180 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode) 8181 int encode = prefixq_and_encode(dst->encoding()); 8182 emit_int8((unsigned char)0xFF); 8183 emit_int8((unsigned char)(0xC0 | encode)); 8184 } 8185 8186 void Assembler::incq(Address dst) { 8187 // Don't use it directly. Use MacroAssembler::incrementq() instead. 8188 InstructionMark im(this); 8189 prefixq(dst); 8190 emit_int8((unsigned char)0xFF); 8191 emit_operand(rax, dst); 8192 } 8193 8194 void Assembler::lea(Register dst, Address src) { 8195 leaq(dst, src); 8196 } 8197 8198 void Assembler::leaq(Register dst, Address src) { 8199 InstructionMark im(this); 8200 prefixq(src, dst); 8201 emit_int8((unsigned char)0x8D); 8202 emit_operand(dst, src); 8203 } 8204 8205 void Assembler::mov64(Register dst, int64_t imm64) { 8206 InstructionMark im(this); 8207 int encode = prefixq_and_encode(dst->encoding()); 8208 emit_int8((unsigned char)(0xB8 | encode)); 8209 emit_int64(imm64); 8210 } 8211 8212 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) { 8213 InstructionMark im(this); 8214 int encode = prefixq_and_encode(dst->encoding()); 8215 emit_int8(0xB8 | encode); 8216 emit_data64(imm64, rspec); 8217 } 8218 8219 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) { 8220 InstructionMark im(this); 8221 int encode = prefix_and_encode(dst->encoding()); 8222 emit_int8((unsigned char)(0xB8 | encode)); 8223 emit_data((int)imm32, rspec, narrow_oop_operand); 8224 } 8225 8226 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) { 8227 InstructionMark im(this); 8228 prefix(dst); 8229 emit_int8((unsigned char)0xC7); 8230 emit_operand(rax, dst, 4); 8231 emit_data((int)imm32, rspec, narrow_oop_operand); 8232 } 8233 8234 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) { 8235 InstructionMark im(this); 8236 int encode = prefix_and_encode(src1->encoding()); 8237 emit_int8((unsigned char)0x81); 8238 emit_int8((unsigned char)(0xF8 | encode)); 8239 emit_data((int)imm32, rspec, narrow_oop_operand); 8240 } 8241 8242 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) { 8243 InstructionMark im(this); 8244 prefix(src1); 8245 emit_int8((unsigned char)0x81); 8246 emit_operand(rax, src1, 4); 8247 emit_data((int)imm32, rspec, narrow_oop_operand); 8248 } 8249 8250 void Assembler::lzcntq(Register dst, Register src) { 8251 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR"); 8252 emit_int8((unsigned char)0xF3); 8253 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8254 emit_int8(0x0F); 8255 emit_int8((unsigned char)0xBD); 8256 emit_int8((unsigned char)(0xC0 | encode)); 8257 } 8258 8259 void Assembler::movdq(XMMRegister dst, Register src) { 8260 // table D-1 says MMX/SSE2 8261 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8262 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8263 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8264 emit_int8(0x6E); 8265 emit_int8((unsigned char)(0xC0 | encode)); 8266 } 8267 8268 void Assembler::movdq(Register dst, XMMRegister src) { 8269 // table D-1 says MMX/SSE2 8270 NOT_LP64(assert(VM_Version::supports_sse2(), "")); 8271 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false); 8272 // swap src/dst to get correct prefix 8273 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes); 8274 emit_int8(0x7E); 8275 emit_int8((unsigned char)(0xC0 | encode)); 8276 } 8277 8278 void Assembler::movq(Register dst, Register src) { 8279 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8280 emit_int8((unsigned char)0x8B); 8281 emit_int8((unsigned char)(0xC0 | encode)); 8282 } 8283 8284 void Assembler::movq(Register dst, Address src) { 8285 InstructionMark im(this); 8286 prefixq(src, dst); 8287 emit_int8((unsigned char)0x8B); 8288 emit_operand(dst, src); 8289 } 8290 8291 void Assembler::movq(Address dst, Register src) { 8292 InstructionMark im(this); 8293 prefixq(dst, src); 8294 emit_int8((unsigned char)0x89); 8295 emit_operand(src, dst); 8296 } 8297 8298 void Assembler::movsbq(Register dst, Address src) { 8299 InstructionMark im(this); 8300 prefixq(src, dst); 8301 emit_int8(0x0F); 8302 emit_int8((unsigned char)0xBE); 8303 emit_operand(dst, src); 8304 } 8305 8306 void Assembler::movsbq(Register dst, Register src) { 8307 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8308 emit_int8(0x0F); 8309 emit_int8((unsigned char)0xBE); 8310 emit_int8((unsigned char)(0xC0 | encode)); 8311 } 8312 8313 void Assembler::movslq(Register dst, int32_t imm32) { 8314 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx) 8315 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx) 8316 // as a result we shouldn't use until tested at runtime... 8317 ShouldNotReachHere(); 8318 InstructionMark im(this); 8319 int encode = prefixq_and_encode(dst->encoding()); 8320 emit_int8((unsigned char)(0xC7 | encode)); 8321 emit_int32(imm32); 8322 } 8323 8324 void Assembler::movslq(Address dst, int32_t imm32) { 8325 assert(is_simm32(imm32), "lost bits"); 8326 InstructionMark im(this); 8327 prefixq(dst); 8328 emit_int8((unsigned char)0xC7); 8329 emit_operand(rax, dst, 4); 8330 emit_int32(imm32); 8331 } 8332 8333 void Assembler::movslq(Register dst, Address src) { 8334 InstructionMark im(this); 8335 prefixq(src, dst); 8336 emit_int8(0x63); 8337 emit_operand(dst, src); 8338 } 8339 8340 void Assembler::movslq(Register dst, Register src) { 8341 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8342 emit_int8(0x63); 8343 emit_int8((unsigned char)(0xC0 | encode)); 8344 } 8345 8346 void Assembler::movswq(Register dst, Address src) { 8347 InstructionMark im(this); 8348 prefixq(src, dst); 8349 emit_int8(0x0F); 8350 emit_int8((unsigned char)0xBF); 8351 emit_operand(dst, src); 8352 } 8353 8354 void Assembler::movswq(Register dst, Register src) { 8355 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8356 emit_int8((unsigned char)0x0F); 8357 emit_int8((unsigned char)0xBF); 8358 emit_int8((unsigned char)(0xC0 | encode)); 8359 } 8360 8361 void Assembler::movzbq(Register dst, Address src) { 8362 InstructionMark im(this); 8363 prefixq(src, dst); 8364 emit_int8((unsigned char)0x0F); 8365 emit_int8((unsigned char)0xB6); 8366 emit_operand(dst, src); 8367 } 8368 8369 void Assembler::movzbq(Register dst, Register src) { 8370 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8371 emit_int8(0x0F); 8372 emit_int8((unsigned char)0xB6); 8373 emit_int8(0xC0 | encode); 8374 } 8375 8376 void Assembler::movzwq(Register dst, Address src) { 8377 InstructionMark im(this); 8378 prefixq(src, dst); 8379 emit_int8((unsigned char)0x0F); 8380 emit_int8((unsigned char)0xB7); 8381 emit_operand(dst, src); 8382 } 8383 8384 void Assembler::movzwq(Register dst, Register src) { 8385 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8386 emit_int8((unsigned char)0x0F); 8387 emit_int8((unsigned char)0xB7); 8388 emit_int8((unsigned char)(0xC0 | encode)); 8389 } 8390 8391 void Assembler::mulq(Address src) { 8392 InstructionMark im(this); 8393 prefixq(src); 8394 emit_int8((unsigned char)0xF7); 8395 emit_operand(rsp, src); 8396 } 8397 8398 void Assembler::mulq(Register src) { 8399 int encode = prefixq_and_encode(src->encoding()); 8400 emit_int8((unsigned char)0xF7); 8401 emit_int8((unsigned char)(0xE0 | encode)); 8402 } 8403 8404 void Assembler::mulxq(Register dst1, Register dst2, Register src) { 8405 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8406 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8407 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes); 8408 emit_int8((unsigned char)0xF6); 8409 emit_int8((unsigned char)(0xC0 | encode)); 8410 } 8411 8412 void Assembler::negq(Register dst) { 8413 int encode = prefixq_and_encode(dst->encoding()); 8414 emit_int8((unsigned char)0xF7); 8415 emit_int8((unsigned char)(0xD8 | encode)); 8416 } 8417 8418 void Assembler::notq(Register dst) { 8419 int encode = prefixq_and_encode(dst->encoding()); 8420 emit_int8((unsigned char)0xF7); 8421 emit_int8((unsigned char)(0xD0 | encode)); 8422 } 8423 8424 void Assembler::orq(Address dst, int32_t imm32) { 8425 InstructionMark im(this); 8426 prefixq(dst); 8427 emit_int8((unsigned char)0x81); 8428 emit_operand(rcx, dst, 4); 8429 emit_int32(imm32); 8430 } 8431 8432 void Assembler::orq(Register dst, int32_t imm32) { 8433 (void) prefixq_and_encode(dst->encoding()); 8434 emit_arith(0x81, 0xC8, dst, imm32); 8435 } 8436 8437 void Assembler::orq(Register dst, Address src) { 8438 InstructionMark im(this); 8439 prefixq(src, dst); 8440 emit_int8(0x0B); 8441 emit_operand(dst, src); 8442 } 8443 8444 void Assembler::orq(Register dst, Register src) { 8445 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8446 emit_arith(0x0B, 0xC0, dst, src); 8447 } 8448 8449 void Assembler::popa() { // 64bit 8450 movq(r15, Address(rsp, 0)); 8451 movq(r14, Address(rsp, wordSize)); 8452 movq(r13, Address(rsp, 2 * wordSize)); 8453 movq(r12, Address(rsp, 3 * wordSize)); 8454 movq(r11, Address(rsp, 4 * wordSize)); 8455 movq(r10, Address(rsp, 5 * wordSize)); 8456 movq(r9, Address(rsp, 6 * wordSize)); 8457 movq(r8, Address(rsp, 7 * wordSize)); 8458 movq(rdi, Address(rsp, 8 * wordSize)); 8459 movq(rsi, Address(rsp, 9 * wordSize)); 8460 movq(rbp, Address(rsp, 10 * wordSize)); 8461 // skip rsp 8462 movq(rbx, Address(rsp, 12 * wordSize)); 8463 movq(rdx, Address(rsp, 13 * wordSize)); 8464 movq(rcx, Address(rsp, 14 * wordSize)); 8465 movq(rax, Address(rsp, 15 * wordSize)); 8466 8467 addq(rsp, 16 * wordSize); 8468 } 8469 8470 void Assembler::popcntq(Register dst, Address src) { 8471 assert(VM_Version::supports_popcnt(), "must support"); 8472 InstructionMark im(this); 8473 emit_int8((unsigned char)0xF3); 8474 prefixq(src, dst); 8475 emit_int8((unsigned char)0x0F); 8476 emit_int8((unsigned char)0xB8); 8477 emit_operand(dst, src); 8478 } 8479 8480 void Assembler::popcntq(Register dst, Register src) { 8481 assert(VM_Version::supports_popcnt(), "must support"); 8482 emit_int8((unsigned char)0xF3); 8483 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8484 emit_int8((unsigned char)0x0F); 8485 emit_int8((unsigned char)0xB8); 8486 emit_int8((unsigned char)(0xC0 | encode)); 8487 } 8488 8489 void Assembler::popq(Address dst) { 8490 InstructionMark im(this); 8491 prefixq(dst); 8492 emit_int8((unsigned char)0x8F); 8493 emit_operand(rax, dst); 8494 } 8495 8496 void Assembler::pusha() { // 64bit 8497 // we have to store original rsp. ABI says that 128 bytes 8498 // below rsp are local scratch. 8499 movq(Address(rsp, -5 * wordSize), rsp); 8500 8501 subq(rsp, 16 * wordSize); 8502 8503 movq(Address(rsp, 15 * wordSize), rax); 8504 movq(Address(rsp, 14 * wordSize), rcx); 8505 movq(Address(rsp, 13 * wordSize), rdx); 8506 movq(Address(rsp, 12 * wordSize), rbx); 8507 // skip rsp 8508 movq(Address(rsp, 10 * wordSize), rbp); 8509 movq(Address(rsp, 9 * wordSize), rsi); 8510 movq(Address(rsp, 8 * wordSize), rdi); 8511 movq(Address(rsp, 7 * wordSize), r8); 8512 movq(Address(rsp, 6 * wordSize), r9); 8513 movq(Address(rsp, 5 * wordSize), r10); 8514 movq(Address(rsp, 4 * wordSize), r11); 8515 movq(Address(rsp, 3 * wordSize), r12); 8516 movq(Address(rsp, 2 * wordSize), r13); 8517 movq(Address(rsp, wordSize), r14); 8518 movq(Address(rsp, 0), r15); 8519 } 8520 8521 void Assembler::pushq(Address src) { 8522 InstructionMark im(this); 8523 prefixq(src); 8524 emit_int8((unsigned char)0xFF); 8525 emit_operand(rsi, src); 8526 } 8527 8528 void Assembler::rclq(Register dst, int imm8) { 8529 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8530 int encode = prefixq_and_encode(dst->encoding()); 8531 if (imm8 == 1) { 8532 emit_int8((unsigned char)0xD1); 8533 emit_int8((unsigned char)(0xD0 | encode)); 8534 } else { 8535 emit_int8((unsigned char)0xC1); 8536 emit_int8((unsigned char)(0xD0 | encode)); 8537 emit_int8(imm8); 8538 } 8539 } 8540 8541 void Assembler::rcrq(Register dst, int imm8) { 8542 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8543 int encode = prefixq_and_encode(dst->encoding()); 8544 if (imm8 == 1) { 8545 emit_int8((unsigned char)0xD1); 8546 emit_int8((unsigned char)(0xD8 | encode)); 8547 } else { 8548 emit_int8((unsigned char)0xC1); 8549 emit_int8((unsigned char)(0xD8 | encode)); 8550 emit_int8(imm8); 8551 } 8552 } 8553 8554 void Assembler::rorq(Register dst, int imm8) { 8555 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8556 int encode = prefixq_and_encode(dst->encoding()); 8557 if (imm8 == 1) { 8558 emit_int8((unsigned char)0xD1); 8559 emit_int8((unsigned char)(0xC8 | encode)); 8560 } else { 8561 emit_int8((unsigned char)0xC1); 8562 emit_int8((unsigned char)(0xc8 | encode)); 8563 emit_int8(imm8); 8564 } 8565 } 8566 8567 void Assembler::rorxq(Register dst, Register src, int imm8) { 8568 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8569 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8570 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 8571 emit_int8((unsigned char)0xF0); 8572 emit_int8((unsigned char)(0xC0 | encode)); 8573 emit_int8(imm8); 8574 } 8575 8576 void Assembler::rorxd(Register dst, Register src, int imm8) { 8577 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported"); 8578 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false); 8579 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes); 8580 emit_int8((unsigned char)0xF0); 8581 emit_int8((unsigned char)(0xC0 | encode)); 8582 emit_int8(imm8); 8583 } 8584 8585 void Assembler::sarq(Register dst, int imm8) { 8586 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8587 int encode = prefixq_and_encode(dst->encoding()); 8588 if (imm8 == 1) { 8589 emit_int8((unsigned char)0xD1); 8590 emit_int8((unsigned char)(0xF8 | encode)); 8591 } else { 8592 emit_int8((unsigned char)0xC1); 8593 emit_int8((unsigned char)(0xF8 | encode)); 8594 emit_int8(imm8); 8595 } 8596 } 8597 8598 void Assembler::sarq(Register dst) { 8599 int encode = prefixq_and_encode(dst->encoding()); 8600 emit_int8((unsigned char)0xD3); 8601 emit_int8((unsigned char)(0xF8 | encode)); 8602 } 8603 8604 void Assembler::sbbq(Address dst, int32_t imm32) { 8605 InstructionMark im(this); 8606 prefixq(dst); 8607 emit_arith_operand(0x81, rbx, dst, imm32); 8608 } 8609 8610 void Assembler::sbbq(Register dst, int32_t imm32) { 8611 (void) prefixq_and_encode(dst->encoding()); 8612 emit_arith(0x81, 0xD8, dst, imm32); 8613 } 8614 8615 void Assembler::sbbq(Register dst, Address src) { 8616 InstructionMark im(this); 8617 prefixq(src, dst); 8618 emit_int8(0x1B); 8619 emit_operand(dst, src); 8620 } 8621 8622 void Assembler::sbbq(Register dst, Register src) { 8623 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8624 emit_arith(0x1B, 0xC0, dst, src); 8625 } 8626 8627 void Assembler::shlq(Register dst, int imm8) { 8628 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8629 int encode = prefixq_and_encode(dst->encoding()); 8630 if (imm8 == 1) { 8631 emit_int8((unsigned char)0xD1); 8632 emit_int8((unsigned char)(0xE0 | encode)); 8633 } else { 8634 emit_int8((unsigned char)0xC1); 8635 emit_int8((unsigned char)(0xE0 | encode)); 8636 emit_int8(imm8); 8637 } 8638 } 8639 8640 void Assembler::shlq(Register dst) { 8641 int encode = prefixq_and_encode(dst->encoding()); 8642 emit_int8((unsigned char)0xD3); 8643 emit_int8((unsigned char)(0xE0 | encode)); 8644 } 8645 8646 void Assembler::shrq(Register dst, int imm8) { 8647 assert(isShiftCount(imm8 >> 1), "illegal shift count"); 8648 int encode = prefixq_and_encode(dst->encoding()); 8649 emit_int8((unsigned char)0xC1); 8650 emit_int8((unsigned char)(0xE8 | encode)); 8651 emit_int8(imm8); 8652 } 8653 8654 void Assembler::shrq(Register dst) { 8655 int encode = prefixq_and_encode(dst->encoding()); 8656 emit_int8((unsigned char)0xD3); 8657 emit_int8(0xE8 | encode); 8658 } 8659 8660 void Assembler::subq(Address dst, int32_t imm32) { 8661 InstructionMark im(this); 8662 prefixq(dst); 8663 emit_arith_operand(0x81, rbp, dst, imm32); 8664 } 8665 8666 void Assembler::subq(Address dst, Register src) { 8667 InstructionMark im(this); 8668 prefixq(dst, src); 8669 emit_int8(0x29); 8670 emit_operand(src, dst); 8671 } 8672 8673 void Assembler::subq(Register dst, int32_t imm32) { 8674 (void) prefixq_and_encode(dst->encoding()); 8675 emit_arith(0x81, 0xE8, dst, imm32); 8676 } 8677 8678 // Force generation of a 4 byte immediate value even if it fits into 8bit 8679 void Assembler::subq_imm32(Register dst, int32_t imm32) { 8680 (void) prefixq_and_encode(dst->encoding()); 8681 emit_arith_imm32(0x81, 0xE8, dst, imm32); 8682 } 8683 8684 void Assembler::subq(Register dst, Address src) { 8685 InstructionMark im(this); 8686 prefixq(src, dst); 8687 emit_int8(0x2B); 8688 emit_operand(dst, src); 8689 } 8690 8691 void Assembler::subq(Register dst, Register src) { 8692 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8693 emit_arith(0x2B, 0xC0, dst, src); 8694 } 8695 8696 void Assembler::testq(Register dst, int32_t imm32) { 8697 // not using emit_arith because test 8698 // doesn't support sign-extension of 8699 // 8bit operands 8700 int encode = dst->encoding(); 8701 if (encode == 0) { 8702 prefix(REX_W); 8703 emit_int8((unsigned char)0xA9); 8704 } else { 8705 encode = prefixq_and_encode(encode); 8706 emit_int8((unsigned char)0xF7); 8707 emit_int8((unsigned char)(0xC0 | encode)); 8708 } 8709 emit_int32(imm32); 8710 } 8711 8712 void Assembler::testq(Register dst, Register src) { 8713 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8714 emit_arith(0x85, 0xC0, dst, src); 8715 } 8716 8717 void Assembler::xaddq(Address dst, Register src) { 8718 InstructionMark im(this); 8719 prefixq(dst, src); 8720 emit_int8(0x0F); 8721 emit_int8((unsigned char)0xC1); 8722 emit_operand(src, dst); 8723 } 8724 8725 void Assembler::xchgq(Register dst, Address src) { 8726 InstructionMark im(this); 8727 prefixq(src, dst); 8728 emit_int8((unsigned char)0x87); 8729 emit_operand(dst, src); 8730 } 8731 8732 void Assembler::xchgq(Register dst, Register src) { 8733 int encode = prefixq_and_encode(dst->encoding(), src->encoding()); 8734 emit_int8((unsigned char)0x87); 8735 emit_int8((unsigned char)(0xc0 | encode)); 8736 } 8737 8738 void Assembler::xorq(Register dst, Register src) { 8739 (void) prefixq_and_encode(dst->encoding(), src->encoding()); 8740 emit_arith(0x33, 0xC0, dst, src); 8741 } 8742 8743 void Assembler::xorq(Register dst, Address src) { 8744 InstructionMark im(this); 8745 prefixq(src, dst); 8746 emit_int8(0x33); 8747 emit_operand(dst, src); 8748 } 8749 8750 #endif // !LP64