4244 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4245 0, "");
4246 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4247 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4248 emit_int8((unsigned char)0x0F);
4249 emit_int8((unsigned char)(0xC0 | encode));
4250 emit_int8(imm8);
4251 }
4252
4253 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4254 assert(VM_Version::supports_sse4_1(), "");
4255 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4256 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4257 emit_int8((unsigned char)0x0E);
4258 emit_int8((unsigned char)(0xC0 | encode));
4259 emit_int8(imm8);
4260 }
4261
4262 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4263 assert(VM_Version::supports_sha(), "");
4264 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4265 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_3A, &attributes);
4266 emit_int8((unsigned char)0xCC);
4267 emit_int8((unsigned char)(0xC0 | encode));
4268 emit_int8((unsigned char)imm8);
4269 }
4270
4271 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4272 assert(VM_Version::supports_sha(), "");
4273 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4274 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4275 emit_int8((unsigned char)0xC8);
4276 emit_int8((unsigned char)(0xC0 | encode));
4277 }
4278
4279 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4280 assert(VM_Version::supports_sha(), "");
4281 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4282 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4283 emit_int8((unsigned char)0xC9);
4284 emit_int8((unsigned char)(0xC0 | encode));
4285 }
4286
4287 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4288 assert(VM_Version::supports_sha(), "");
4289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4290 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4291 emit_int8((unsigned char)0xCA);
4292 emit_int8((unsigned char)(0xC0 | encode));
4293 }
4294
4295 // xmm0 is implicit additional source to this instruction.
4296 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4297 assert(VM_Version::supports_sha(), "");
4298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4299 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4300 emit_int8((unsigned char)0xCB);
4301 emit_int8((unsigned char)(0xC0 | encode));
4302 }
4303
4304 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4305 assert(VM_Version::supports_sha(), "");
4306 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4307 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4308 emit_int8((unsigned char)0xCC);
4309 emit_int8((unsigned char)(0xC0 | encode));
4310 }
4311
4312 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4313 assert(VM_Version::supports_sha(), "");
4314 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4315 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
4316 emit_int8((unsigned char)0xCD);
4317 emit_int8((unsigned char)(0xC0 | encode));
4318 }
4319
4320
4321 void Assembler::shll(Register dst, int imm8) {
4322 assert(isShiftCount(imm8), "illegal shift count");
4323 int encode = prefix_and_encode(dst->encoding());
4324 if (imm8 == 1 ) {
4325 emit_int8((unsigned char)0xD1);
4326 emit_int8((unsigned char)(0xE0 | encode));
4327 } else {
4328 emit_int8((unsigned char)0xC1);
4329 emit_int8((unsigned char)(0xE0 | encode));
4330 emit_int8(imm8);
4331 }
4332 }
4333
4334 void Assembler::shll(Register dst) {
4335 int encode = prefix_and_encode(dst->encoding());
|
4244 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4245 0, "");
4246 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4247 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4248 emit_int8((unsigned char)0x0F);
4249 emit_int8((unsigned char)(0xC0 | encode));
4250 emit_int8(imm8);
4251 }
4252
4253 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4254 assert(VM_Version::supports_sse4_1(), "");
4255 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4256 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4257 emit_int8((unsigned char)0x0E);
4258 emit_int8((unsigned char)(0xC0 | encode));
4259 emit_int8(imm8);
4260 }
4261
4262 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4263 assert(VM_Version::supports_sha(), "");
4264 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4265 emit_int8((unsigned char)0x0F);
4266 emit_int8((unsigned char)0x3A);
4267 emit_int8((unsigned char)0xCC);
4268 emit_int8((unsigned char)(0xC0 | encode));
4269 emit_int8((unsigned char)imm8);
4270 }
4271
4272 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4273 assert(VM_Version::supports_sha(), "");
4274 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4275 emit_int8((unsigned char)0x0F);
4276 emit_int8((unsigned char)0x38);
4277 emit_int8((unsigned char)0xC8);
4278 emit_int8((unsigned char)(0xC0 | encode));
4279 }
4280
4281 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4282 assert(VM_Version::supports_sha(), "");
4283 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4284 emit_int8((unsigned char)0x0F);
4285 emit_int8((unsigned char)0x38);
4286 emit_int8((unsigned char)0xC9);
4287 emit_int8((unsigned char)(0xC0 | encode));
4288 }
4289
4290 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4291 assert(VM_Version::supports_sha(), "");
4292 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4293 emit_int8((unsigned char)0x0F);
4294 emit_int8((unsigned char)0x38);
4295 emit_int8((unsigned char)0xCA);
4296 emit_int8((unsigned char)(0xC0 | encode));
4297 }
4298
4299 // xmm0 is implicit additional source to this instruction.
4300 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4301 assert(VM_Version::supports_sha(), "");
4302 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4303 emit_int8((unsigned char)0x0F);
4304 emit_int8((unsigned char)0x38);
4305 emit_int8((unsigned char)0xCB);
4306 emit_int8((unsigned char)(0xC0 | encode));
4307 }
4308
4309 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4310 assert(VM_Version::supports_sha(), "");
4311 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4312 emit_int8((unsigned char)0x0F);
4313 emit_int8((unsigned char)0x38);
4314 emit_int8((unsigned char)0xCC);
4315 emit_int8((unsigned char)(0xC0 | encode));
4316 }
4317
4318 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4319 assert(VM_Version::supports_sha(), "");
4320 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4321 emit_int8((unsigned char)0x0F);
4322 emit_int8((unsigned char)0x38);
4323 emit_int8((unsigned char)0xCD);
4324 emit_int8((unsigned char)(0xC0 | encode));
4325 }
4326
4327
4328 void Assembler::shll(Register dst, int imm8) {
4329 assert(isShiftCount(imm8), "illegal shift count");
4330 int encode = prefix_and_encode(dst->encoding());
4331 if (imm8 == 1 ) {
4332 emit_int8((unsigned char)0xD1);
4333 emit_int8((unsigned char)(0xE0 | encode));
4334 } else {
4335 emit_int8((unsigned char)0xC1);
4336 emit_int8((unsigned char)(0xE0 | encode));
4337 emit_int8(imm8);
4338 }
4339 }
4340
4341 void Assembler::shll(Register dst) {
4342 int encode = prefix_and_encode(dst->encoding());
|