1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.hpp" 27 #include "asm/macroAssembler.inline.hpp" 28 #include "logging/log.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "runtime/java.hpp" 31 #include "runtime/os.hpp" 32 #include "runtime/stubCodeGenerator.hpp" 33 #include "vm_version_x86.hpp" 34 35 36 int VM_Version::_cpu; 37 int VM_Version::_model; 38 int VM_Version::_stepping; 39 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, }; 40 41 // Address of instruction which causes SEGV 42 address VM_Version::_cpuinfo_segv_addr = 0; 43 // Address of instruction after the one which causes SEGV 44 address VM_Version::_cpuinfo_cont_addr = 0; 45 46 static BufferBlob* stub_blob; 47 static const int stub_size = 1000; 48 49 extern "C" { 50 typedef void (*get_cpu_info_stub_t)(void*); 51 } 52 static get_cpu_info_stub_t get_cpu_info_stub = NULL; 53 54 55 class VM_Version_StubGenerator: public StubCodeGenerator { 56 public: 57 58 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {} 59 60 address generate_get_cpu_info() { 61 // Flags to test CPU type. 62 const uint32_t HS_EFL_AC = 0x40000; 63 const uint32_t HS_EFL_ID = 0x200000; 64 // Values for when we don't have a CPUID instruction. 65 const int CPU_FAMILY_SHIFT = 8; 66 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT); 67 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT); 68 69 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4; 70 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, done, wrapup; 71 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check; 72 73 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub"); 74 # define __ _masm-> 75 76 address start = __ pc(); 77 78 // 79 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info); 80 // 81 // LP64: rcx and rdx are first and second argument registers on windows 82 83 __ push(rbp); 84 #ifdef _LP64 85 __ mov(rbp, c_rarg0); // cpuid_info address 86 #else 87 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address 88 #endif 89 __ push(rbx); 90 __ push(rsi); 91 __ pushf(); // preserve rbx, and flags 92 __ pop(rax); 93 __ push(rax); 94 __ mov(rcx, rax); 95 // 96 // if we are unable to change the AC flag, we have a 386 97 // 98 __ xorl(rax, HS_EFL_AC); 99 __ push(rax); 100 __ popf(); 101 __ pushf(); 102 __ pop(rax); 103 __ cmpptr(rax, rcx); 104 __ jccb(Assembler::notEqual, detect_486); 105 106 __ movl(rax, CPU_FAMILY_386); 107 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); 108 __ jmp(done); 109 110 // 111 // If we are unable to change the ID flag, we have a 486 which does 112 // not support the "cpuid" instruction. 113 // 114 __ bind(detect_486); 115 __ mov(rax, rcx); 116 __ xorl(rax, HS_EFL_ID); 117 __ push(rax); 118 __ popf(); 119 __ pushf(); 120 __ pop(rax); 121 __ cmpptr(rcx, rax); 122 __ jccb(Assembler::notEqual, detect_586); 123 124 __ bind(cpu486); 125 __ movl(rax, CPU_FAMILY_486); 126 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax); 127 __ jmp(done); 128 129 // 130 // At this point, we have a chip which supports the "cpuid" instruction 131 // 132 __ bind(detect_586); 133 __ xorl(rax, rax); 134 __ cpuid(); 135 __ orl(rax, rax); 136 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input 137 // value of at least 1, we give up and 138 // assume a 486 139 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); 140 __ movl(Address(rsi, 0), rax); 141 __ movl(Address(rsi, 4), rbx); 142 __ movl(Address(rsi, 8), rcx); 143 __ movl(Address(rsi,12), rdx); 144 145 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported? 146 __ jccb(Assembler::belowEqual, std_cpuid4); 147 148 // 149 // cpuid(0xB) Processor Topology 150 // 151 __ movl(rax, 0xb); 152 __ xorl(rcx, rcx); // Threads level 153 __ cpuid(); 154 155 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset()))); 156 __ movl(Address(rsi, 0), rax); 157 __ movl(Address(rsi, 4), rbx); 158 __ movl(Address(rsi, 8), rcx); 159 __ movl(Address(rsi,12), rdx); 160 161 __ movl(rax, 0xb); 162 __ movl(rcx, 1); // Cores level 163 __ cpuid(); 164 __ push(rax); 165 __ andl(rax, 0x1f); // Determine if valid topology level 166 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level 167 __ andl(rax, 0xffff); 168 __ pop(rax); 169 __ jccb(Assembler::equal, std_cpuid4); 170 171 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset()))); 172 __ movl(Address(rsi, 0), rax); 173 __ movl(Address(rsi, 4), rbx); 174 __ movl(Address(rsi, 8), rcx); 175 __ movl(Address(rsi,12), rdx); 176 177 __ movl(rax, 0xb); 178 __ movl(rcx, 2); // Packages level 179 __ cpuid(); 180 __ push(rax); 181 __ andl(rax, 0x1f); // Determine if valid topology level 182 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level 183 __ andl(rax, 0xffff); 184 __ pop(rax); 185 __ jccb(Assembler::equal, std_cpuid4); 186 187 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset()))); 188 __ movl(Address(rsi, 0), rax); 189 __ movl(Address(rsi, 4), rbx); 190 __ movl(Address(rsi, 8), rcx); 191 __ movl(Address(rsi,12), rdx); 192 193 // 194 // cpuid(0x4) Deterministic cache params 195 // 196 __ bind(std_cpuid4); 197 __ movl(rax, 4); 198 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported? 199 __ jccb(Assembler::greater, std_cpuid1); 200 201 __ xorl(rcx, rcx); // L1 cache 202 __ cpuid(); 203 __ push(rax); 204 __ andl(rax, 0x1f); // Determine if valid cache parameters used 205 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache 206 __ pop(rax); 207 __ jccb(Assembler::equal, std_cpuid1); 208 209 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset()))); 210 __ movl(Address(rsi, 0), rax); 211 __ movl(Address(rsi, 4), rbx); 212 __ movl(Address(rsi, 8), rcx); 213 __ movl(Address(rsi,12), rdx); 214 215 // 216 // Standard cpuid(0x1) 217 // 218 __ bind(std_cpuid1); 219 __ movl(rax, 1); 220 __ cpuid(); 221 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); 222 __ movl(Address(rsi, 0), rax); 223 __ movl(Address(rsi, 4), rbx); 224 __ movl(Address(rsi, 8), rcx); 225 __ movl(Address(rsi,12), rdx); 226 227 // 228 // Check if OS has enabled XGETBV instruction to access XCR0 229 // (OSXSAVE feature flag) and CPU supports AVX 230 // 231 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx 232 __ cmpl(rcx, 0x18000000); 233 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported 234 235 // 236 // XCR0, XFEATURE_ENABLED_MASK register 237 // 238 __ xorl(rcx, rcx); // zero for XCR0 register 239 __ xgetbv(); 240 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); 241 __ movl(Address(rsi, 0), rax); 242 __ movl(Address(rsi, 4), rdx); 243 244 // 245 // cpuid(0x7) Structured Extended Features 246 // 247 __ bind(sef_cpuid); 248 __ movl(rax, 7); 249 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported? 250 __ jccb(Assembler::greater, ext_cpuid); 251 252 __ xorl(rcx, rcx); 253 __ cpuid(); 254 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 255 __ movl(Address(rsi, 0), rax); 256 __ movl(Address(rsi, 4), rbx); 257 258 // 259 // Extended cpuid(0x80000000) 260 // 261 __ bind(ext_cpuid); 262 __ movl(rax, 0x80000000); 263 __ cpuid(); 264 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported? 265 __ jcc(Assembler::belowEqual, done); 266 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported? 267 __ jccb(Assembler::belowEqual, ext_cpuid1); 268 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported? 269 __ jccb(Assembler::belowEqual, ext_cpuid5); 270 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported? 271 __ jccb(Assembler::belowEqual, ext_cpuid7); 272 // 273 // Extended cpuid(0x80000008) 274 // 275 __ movl(rax, 0x80000008); 276 __ cpuid(); 277 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset()))); 278 __ movl(Address(rsi, 0), rax); 279 __ movl(Address(rsi, 4), rbx); 280 __ movl(Address(rsi, 8), rcx); 281 __ movl(Address(rsi,12), rdx); 282 283 // 284 // Extended cpuid(0x80000007) 285 // 286 __ bind(ext_cpuid7); 287 __ movl(rax, 0x80000007); 288 __ cpuid(); 289 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset()))); 290 __ movl(Address(rsi, 0), rax); 291 __ movl(Address(rsi, 4), rbx); 292 __ movl(Address(rsi, 8), rcx); 293 __ movl(Address(rsi,12), rdx); 294 295 // 296 // Extended cpuid(0x80000005) 297 // 298 __ bind(ext_cpuid5); 299 __ movl(rax, 0x80000005); 300 __ cpuid(); 301 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset()))); 302 __ movl(Address(rsi, 0), rax); 303 __ movl(Address(rsi, 4), rbx); 304 __ movl(Address(rsi, 8), rcx); 305 __ movl(Address(rsi,12), rdx); 306 307 // 308 // Extended cpuid(0x80000001) 309 // 310 __ bind(ext_cpuid1); 311 __ movl(rax, 0x80000001); 312 __ cpuid(); 313 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset()))); 314 __ movl(Address(rsi, 0), rax); 315 __ movl(Address(rsi, 4), rbx); 316 __ movl(Address(rsi, 8), rcx); 317 __ movl(Address(rsi,12), rdx); 318 319 // 320 // Check if OS has enabled XGETBV instruction to access XCR0 321 // (OSXSAVE feature flag) and CPU supports AVX 322 // 323 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset()))); 324 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx 325 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx 326 __ cmpl(rcx, 0x18000000); 327 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported 328 329 __ movl(rax, 0x6); 330 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 331 __ cmpl(rax, 0x6); 332 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported 333 334 // we need to bridge farther than imm8, so we use this island as a thunk 335 __ bind(done); 336 __ jmp(wrapup); 337 338 __ bind(start_simd_check); 339 // 340 // Some OSs have a bug when upper 128/256bits of YMM/ZMM 341 // registers are not restored after a signal processing. 342 // Generate SEGV here (reference through NULL) 343 // and check upper YMM/ZMM bits after it. 344 // 345 intx saved_useavx = UseAVX; 346 intx saved_usesse = UseSSE; 347 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f 348 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 349 __ movl(rax, 0x10000); 350 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm 351 __ cmpl(rax, 0x10000); 352 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported 353 // check _cpuid_info.xem_xcr0_eax.bits.opmask 354 // check _cpuid_info.xem_xcr0_eax.bits.zmm512 355 // check _cpuid_info.xem_xcr0_eax.bits.zmm32 356 __ movl(rax, 0xE0); 357 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 358 __ cmpl(rax, 0xE0); 359 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported 360 361 // EVEX setup: run in lowest evex mode 362 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts 363 UseAVX = 3; 364 UseSSE = 2; 365 #ifdef _WINDOWS 366 // xmm5-xmm15 are not preserved by caller on windows 367 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx 368 __ subptr(rsp, 64); 369 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit); 370 #ifdef _LP64 371 __ subptr(rsp, 64); 372 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit); 373 __ subptr(rsp, 64); 374 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit); 375 #endif // _LP64 376 #endif // _WINDOWS 377 378 // load value into all 64 bytes of zmm7 register 379 __ movl(rcx, VM_Version::ymm_test_value()); 380 __ movdl(xmm0, rcx); 381 __ movl(rcx, 0xffff); 382 __ kmovwl(k1, rcx); 383 __ evpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit); 384 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit); 385 #ifdef _LP64 386 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit); 387 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit); 388 #endif 389 VM_Version::clean_cpuFeatures(); 390 __ jmp(save_restore_except); 391 392 __ bind(legacy_setup); 393 // AVX setup 394 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts 395 UseAVX = 1; 396 UseSSE = 2; 397 #ifdef _WINDOWS 398 __ subptr(rsp, 32); 399 __ vmovdqu(Address(rsp, 0), xmm7); 400 #ifdef _LP64 401 __ subptr(rsp, 32); 402 __ vmovdqu(Address(rsp, 0), xmm8); 403 __ subptr(rsp, 32); 404 __ vmovdqu(Address(rsp, 0), xmm15); 405 #endif // _LP64 406 #endif // _WINDOWS 407 408 // load value into all 32 bytes of ymm7 register 409 __ movl(rcx, VM_Version::ymm_test_value()); 410 411 __ movdl(xmm0, rcx); 412 __ pshufd(xmm0, xmm0, 0x00); 413 __ vinsertf128_high(xmm0, xmm0); 414 __ vmovdqu(xmm7, xmm0); 415 #ifdef _LP64 416 __ vmovdqu(xmm8, xmm0); 417 __ vmovdqu(xmm15, xmm0); 418 #endif 419 VM_Version::clean_cpuFeatures(); 420 421 __ bind(save_restore_except); 422 __ xorl(rsi, rsi); 423 VM_Version::set_cpuinfo_segv_addr(__ pc()); 424 // Generate SEGV 425 __ movl(rax, Address(rsi, 0)); 426 427 VM_Version::set_cpuinfo_cont_addr(__ pc()); 428 // Returns here after signal. Save xmm0 to check it later. 429 430 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f 431 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset()))); 432 __ movl(rax, 0x10000); 433 __ andl(rax, Address(rsi, 4)); 434 __ cmpl(rax, 0x10000); 435 __ jccb(Assembler::notEqual, legacy_save_restore); 436 // check _cpuid_info.xem_xcr0_eax.bits.opmask 437 // check _cpuid_info.xem_xcr0_eax.bits.zmm512 438 // check _cpuid_info.xem_xcr0_eax.bits.zmm32 439 __ movl(rax, 0xE0); 440 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm 441 __ cmpl(rax, 0xE0); 442 __ jccb(Assembler::notEqual, legacy_save_restore); 443 444 // EVEX check: run in lowest evex mode 445 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts 446 UseAVX = 3; 447 UseSSE = 2; 448 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset()))); 449 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit); 450 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit); 451 #ifdef _LP64 452 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit); 453 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit); 454 #endif 455 456 #ifdef _WINDOWS 457 #ifdef _LP64 458 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit); 459 __ addptr(rsp, 64); 460 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit); 461 __ addptr(rsp, 64); 462 #endif // _LP64 463 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit); 464 __ addptr(rsp, 64); 465 #endif // _WINDOWS 466 VM_Version::clean_cpuFeatures(); 467 UseAVX = saved_useavx; 468 UseSSE = saved_usesse; 469 __ jmp(wrapup); 470 471 __ bind(legacy_save_restore); 472 // AVX check 473 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts 474 UseAVX = 1; 475 UseSSE = 2; 476 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset()))); 477 __ vmovdqu(Address(rsi, 0), xmm0); 478 __ vmovdqu(Address(rsi, 32), xmm7); 479 #ifdef _LP64 480 __ vmovdqu(Address(rsi, 64), xmm8); 481 __ vmovdqu(Address(rsi, 96), xmm15); 482 #endif 483 484 #ifdef _WINDOWS 485 #ifdef _LP64 486 __ vmovdqu(xmm15, Address(rsp, 0)); 487 __ addptr(rsp, 32); 488 __ vmovdqu(xmm8, Address(rsp, 0)); 489 __ addptr(rsp, 32); 490 #endif // _LP64 491 __ vmovdqu(xmm7, Address(rsp, 0)); 492 __ addptr(rsp, 32); 493 #endif // _WINDOWS 494 VM_Version::clean_cpuFeatures(); 495 UseAVX = saved_useavx; 496 UseSSE = saved_usesse; 497 498 __ bind(wrapup); 499 __ popf(); 500 __ pop(rsi); 501 __ pop(rbx); 502 __ pop(rbp); 503 __ ret(0); 504 505 # undef __ 506 507 return start; 508 }; 509 }; 510 511 void VM_Version::get_processor_features() { 512 513 _cpu = 4; // 486 by default 514 _model = 0; 515 _stepping = 0; 516 _features = 0; 517 _logical_processors_per_package = 1; 518 // i486 internal cache is both I&D and has a 16-byte line size 519 _L1_data_cache_line_size = 16; 520 521 // Get raw processor info 522 523 get_cpu_info_stub(&_cpuid_info); 524 525 assert_is_initialized(); 526 _cpu = extended_cpu_family(); 527 _model = extended_cpu_model(); 528 _stepping = cpu_stepping(); 529 530 if (cpu_family() > 4) { // it supports CPUID 531 _features = feature_flags(); 532 // Logical processors are only available on P4s and above, 533 // and only if hyperthreading is available. 534 _logical_processors_per_package = logical_processor_count(); 535 _L1_data_cache_line_size = L1_line_size(); 536 } 537 538 _supports_cx8 = supports_cmpxchg8(); 539 // xchg and xadd instructions 540 _supports_atomic_getset4 = true; 541 _supports_atomic_getadd4 = true; 542 LP64_ONLY(_supports_atomic_getset8 = true); 543 LP64_ONLY(_supports_atomic_getadd8 = true); 544 545 #ifdef _LP64 546 // OS should support SSE for x64 and hardware should support at least SSE2. 547 if (!VM_Version::supports_sse2()) { 548 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported"); 549 } 550 // in 64 bit the use of SSE2 is the minimum 551 if (UseSSE < 2) UseSSE = 2; 552 #endif 553 554 #ifdef AMD64 555 // flush_icache_stub have to be generated first. 556 // That is why Icache line size is hard coded in ICache class, 557 // see icache_x86.hpp. It is also the reason why we can't use 558 // clflush instruction in 32-bit VM since it could be running 559 // on CPU which does not support it. 560 // 561 // The only thing we can do is to verify that flushed 562 // ICache::line_size has correct value. 563 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported"); 564 // clflush_size is size in quadwords (8 bytes). 565 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported"); 566 #endif 567 568 // If the OS doesn't support SSE, we can't use this feature even if the HW does 569 if (!os::supports_sse()) 570 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2); 571 572 if (UseSSE < 4) { 573 _features &= ~CPU_SSE4_1; 574 _features &= ~CPU_SSE4_2; 575 } 576 577 if (UseSSE < 3) { 578 _features &= ~CPU_SSE3; 579 _features &= ~CPU_SSSE3; 580 _features &= ~CPU_SSE4A; 581 } 582 583 if (UseSSE < 2) 584 _features &= ~CPU_SSE2; 585 586 if (UseSSE < 1) 587 _features &= ~CPU_SSE; 588 589 // first try initial setting and detect what we can support 590 if (UseAVX > 0) { 591 if (UseAVX > 2 && supports_evex()) { 592 UseAVX = 3; 593 } else if (UseAVX > 1 && supports_avx2()) { 594 UseAVX = 2; 595 } else if (UseAVX > 0 && supports_avx()) { 596 UseAVX = 1; 597 } else { 598 UseAVX = 0; 599 } 600 } else if (UseAVX < 0) { 601 UseAVX = 0; 602 } 603 604 if (UseAVX < 3) { 605 _features &= ~CPU_AVX512F; 606 _features &= ~CPU_AVX512DQ; 607 _features &= ~CPU_AVX512CD; 608 _features &= ~CPU_AVX512BW; 609 _features &= ~CPU_AVX512VL; 610 } 611 612 if (UseAVX < 2) 613 _features &= ~CPU_AVX2; 614 615 if (UseAVX < 1) 616 _features &= ~CPU_AVX; 617 618 if (!UseAES && !FLAG_IS_DEFAULT(UseAES)) 619 _features &= ~CPU_AES; 620 621 if (logical_processors_per_package() == 1) { 622 // HT processor could be installed on a system which doesn't support HT. 623 _features &= ~CPU_HT; 624 } 625 626 char buf[256]; 627 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 628 cores_per_cpu(), threads_per_core(), 629 cpu_family(), _model, _stepping, 630 (supports_cmov() ? ", cmov" : ""), 631 (supports_cmpxchg8() ? ", cx8" : ""), 632 (supports_fxsr() ? ", fxsr" : ""), 633 (supports_mmx() ? ", mmx" : ""), 634 (supports_sse() ? ", sse" : ""), 635 (supports_sse2() ? ", sse2" : ""), 636 (supports_sse3() ? ", sse3" : ""), 637 (supports_ssse3()? ", ssse3": ""), 638 (supports_sse4_1() ? ", sse4.1" : ""), 639 (supports_sse4_2() ? ", sse4.2" : ""), 640 (supports_popcnt() ? ", popcnt" : ""), 641 (supports_avx() ? ", avx" : ""), 642 (supports_avx2() ? ", avx2" : ""), 643 (supports_aes() ? ", aes" : ""), 644 (supports_clmul() ? ", clmul" : ""), 645 (supports_erms() ? ", erms" : ""), 646 (supports_rtm() ? ", rtm" : ""), 647 (supports_mmx_ext() ? ", mmxext" : ""), 648 (supports_3dnow_prefetch() ? ", 3dnowpref" : ""), 649 (supports_lzcnt() ? ", lzcnt": ""), 650 (supports_sse4a() ? ", sse4a": ""), 651 (supports_ht() ? ", ht": ""), 652 (supports_tsc() ? ", tsc": ""), 653 (supports_tscinv_bit() ? ", tscinvbit": ""), 654 (supports_tscinv() ? ", tscinv": ""), 655 (supports_bmi1() ? ", bmi1" : ""), 656 (supports_bmi2() ? ", bmi2" : ""), 657 (supports_adx() ? ", adx" : ""), 658 (supports_evex() ? ", evex" : ""), 659 (supports_sha() ? ", sha" : ""), 660 (supports_fma() ? ", fma" : "")); 661 _features_string = os::strdup(buf); 662 663 // UseSSE is set to the smaller of what hardware supports and what 664 // the command line requires. I.e., you cannot set UseSSE to 2 on 665 // older Pentiums which do not support it. 666 if (UseSSE > 4) UseSSE=4; 667 if (UseSSE < 0) UseSSE=0; 668 if (!supports_sse4_1()) // Drop to 3 if no SSE4 support 669 UseSSE = MIN2((intx)3,UseSSE); 670 if (!supports_sse3()) // Drop to 2 if no SSE3 support 671 UseSSE = MIN2((intx)2,UseSSE); 672 if (!supports_sse2()) // Drop to 1 if no SSE2 support 673 UseSSE = MIN2((intx)1,UseSSE); 674 if (!supports_sse ()) // Drop to 0 if no SSE support 675 UseSSE = 0; 676 677 // Use AES instructions if available. 678 if (supports_aes()) { 679 if (FLAG_IS_DEFAULT(UseAES)) { 680 FLAG_SET_DEFAULT(UseAES, true); 681 } 682 if (!UseAES) { 683 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 684 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled."); 685 } 686 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 687 } else { 688 if (UseSSE > 2) { 689 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 690 FLAG_SET_DEFAULT(UseAESIntrinsics, true); 691 } 692 } else { 693 // The AES intrinsic stubs require AES instruction support (of course) 694 // but also require sse3 mode or higher for instructions it use. 695 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 696 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled."); 697 } 698 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 699 } 700 701 // --AES-CTR begins-- 702 if (!UseAESIntrinsics) { 703 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { 704 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled."); 705 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 706 } 707 } else { 708 if(supports_sse4_1()) { 709 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { 710 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true); 711 } 712 } else { 713 // The AES-CTR intrinsic stubs require AES instruction support (of course) 714 // but also require sse4.1 mode or higher for instructions it use. 715 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { 716 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled."); 717 } 718 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 719 } 720 } 721 // --AES-CTR ends-- 722 } 723 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) { 724 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) { 725 warning("AES instructions are not available on this CPU"); 726 FLAG_SET_DEFAULT(UseAES, false); 727 } 728 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 729 warning("AES intrinsics are not available on this CPU"); 730 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 731 } 732 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) { 733 warning("AES-CTR intrinsics are not available on this CPU"); 734 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 735 } 736 } 737 738 // Use CLMUL instructions if available. 739 if (supports_clmul()) { 740 if (FLAG_IS_DEFAULT(UseCLMUL)) { 741 UseCLMUL = true; 742 } 743 } else if (UseCLMUL) { 744 if (!FLAG_IS_DEFAULT(UseCLMUL)) 745 warning("CLMUL instructions not available on this CPU (AVX may also be required)"); 746 FLAG_SET_DEFAULT(UseCLMUL, false); 747 } 748 749 if (UseCLMUL && (UseSSE > 2)) { 750 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 751 UseCRC32Intrinsics = true; 752 } 753 } else if (UseCRC32Intrinsics) { 754 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics)) 755 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)"); 756 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false); 757 } 758 759 if (supports_sse4_2()) { 760 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 761 UseCRC32CIntrinsics = true; 762 } 763 } 764 else if (UseCRC32CIntrinsics) { 765 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) { 766 warning("CRC32C intrinsics are not available on this CPU"); 767 } 768 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 769 } 770 771 // GHASH/GCM intrinsics 772 if (UseCLMUL && (UseSSE > 2)) { 773 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) { 774 UseGHASHIntrinsics = true; 775 } 776 } else if (UseGHASHIntrinsics) { 777 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics)) 778 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU"); 779 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 780 } 781 782 if (supports_fma() && UseSSE >= 2) { 783 if (FLAG_IS_DEFAULT(UseFMA)) { 784 UseFMA = true; 785 } 786 } else if (UseFMA) { 787 warning("FMA instructions are not available on this CPU"); 788 FLAG_SET_DEFAULT(UseFMA, false); 789 } 790 791 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) { 792 if (FLAG_IS_DEFAULT(UseSHA)) { 793 UseSHA = true; 794 } 795 } else if (UseSHA) { 796 warning("SHA instructions are not available on this CPU"); 797 FLAG_SET_DEFAULT(UseSHA, false); 798 } 799 800 if (supports_sha() && UseSHA) { 801 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) { 802 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true); 803 } 804 } else if (UseSHA1Intrinsics) { 805 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU."); 806 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 807 } 808 809 if (UseSHA) { 810 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) { 811 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true); 812 } 813 } else if (UseSHA256Intrinsics) { 814 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU."); 815 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 816 } 817 818 if (UseSHA) { 819 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) { 820 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true); 821 } 822 } else if (UseSHA512Intrinsics) { 823 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU."); 824 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 825 } 826 827 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) { 828 FLAG_SET_DEFAULT(UseSHA, false); 829 } 830 831 if (UseAdler32Intrinsics) { 832 warning("Adler32Intrinsics not available on this CPU."); 833 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 834 } 835 836 if (!supports_rtm() && UseRTMLocking) { 837 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 838 // setting during arguments processing. See use_biased_locking(). 839 // VM_Version_init() is executed after UseBiasedLocking is used 840 // in Thread::allocate(). 841 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 842 } 843 844 #if INCLUDE_RTM_OPT 845 if (UseRTMLocking) { 846 if (is_intel_family_core()) { 847 if ((_model == CPU_MODEL_HASWELL_E3) || 848 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) || 849 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) { 850 // currently a collision between SKL and HSW_E3 851 if (!UnlockExperimentalVMOptions && UseAVX < 3) { 852 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 853 } else { 854 warning("UseRTMLocking is only available as experimental option on this platform."); 855 } 856 } 857 } 858 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 859 // RTM locking should be used only for applications with 860 // high lock contention. For now we do not use it by default. 861 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 862 } 863 if (!is_power_of_2(RTMTotalCountIncrRate)) { 864 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 865 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 866 } 867 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 868 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 869 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 870 } 871 } else { // !UseRTMLocking 872 if (UseRTMForStackLocks) { 873 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 874 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 875 } 876 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 877 } 878 if (UseRTMDeopt) { 879 FLAG_SET_DEFAULT(UseRTMDeopt, false); 880 } 881 if (PrintPreciseRTMLockingStatistics) { 882 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 883 } 884 } 885 #else 886 if (UseRTMLocking) { 887 // Only C2 does RTM locking optimization. 888 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 889 // setting during arguments processing. See use_biased_locking(). 890 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 891 } 892 #endif 893 894 #ifdef COMPILER2 895 if (UseFPUForSpilling) { 896 if (UseSSE < 2) { 897 // Only supported with SSE2+ 898 FLAG_SET_DEFAULT(UseFPUForSpilling, false); 899 } 900 } 901 #endif 902 #if defined(COMPILER2) || INCLUDE_JVMCI 903 if (MaxVectorSize > 0) { 904 if (!is_power_of_2(MaxVectorSize)) { 905 warning("MaxVectorSize must be a power of 2"); 906 FLAG_SET_DEFAULT(MaxVectorSize, 64); 907 } 908 if (MaxVectorSize > 64) { 909 FLAG_SET_DEFAULT(MaxVectorSize, 64); 910 } 911 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) { 912 // 32 bytes vectors (in YMM) are only supported with AVX+ 913 FLAG_SET_DEFAULT(MaxVectorSize, 16); 914 } 915 if (UseSSE < 2) { 916 // Vectors (in XMM) are only supported with SSE2+ 917 FLAG_SET_DEFAULT(MaxVectorSize, 0); 918 } 919 #if defined(COMPILER2) && defined(ASSERT) 920 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) { 921 tty->print_cr("State of YMM registers after signal handle:"); 922 int nreg = 2 LP64_ONLY(+2); 923 const char* ymm_name[4] = {"0", "7", "8", "15"}; 924 for (int i = 0; i < nreg; i++) { 925 tty->print("YMM%s:", ymm_name[i]); 926 for (int j = 7; j >=0; j--) { 927 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]); 928 } 929 tty->cr(); 930 } 931 } 932 #endif // COMPILER2 && ASSERT 933 } 934 #endif // COMPILER2 || INCLUDE_JVMCI 935 936 #ifdef COMPILER2 937 #ifdef _LP64 938 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 939 UseMultiplyToLenIntrinsic = true; 940 } 941 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 942 UseSquareToLenIntrinsic = true; 943 } 944 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 945 UseMulAddIntrinsic = true; 946 } 947 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 948 UseMontgomeryMultiplyIntrinsic = true; 949 } 950 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 951 UseMontgomerySquareIntrinsic = true; 952 } 953 #else 954 if (UseMultiplyToLenIntrinsic) { 955 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 956 warning("multiplyToLen intrinsic is not available in 32-bit VM"); 957 } 958 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false); 959 } 960 if (UseMontgomeryMultiplyIntrinsic) { 961 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 962 warning("montgomeryMultiply intrinsic is not available in 32-bit VM"); 963 } 964 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false); 965 } 966 if (UseMontgomerySquareIntrinsic) { 967 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 968 warning("montgomerySquare intrinsic is not available in 32-bit VM"); 969 } 970 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false); 971 } 972 if (UseSquareToLenIntrinsic) { 973 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) { 974 warning("squareToLen intrinsic is not available in 32-bit VM"); 975 } 976 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false); 977 } 978 if (UseMulAddIntrinsic) { 979 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) { 980 warning("mulAdd intrinsic is not available in 32-bit VM"); 981 } 982 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false); 983 } 984 #endif 985 #endif // COMPILER2 986 987 // On new cpus instructions which update whole XMM register should be used 988 // to prevent partial register stall due to dependencies on high half. 989 // 990 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem) 991 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem) 992 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm). 993 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm). 994 995 if( is_amd() ) { // AMD cpus specific settings 996 if( supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop) ) { 997 // Use it on new AMD cpus starting from Opteron. 998 UseAddressNop = true; 999 } 1000 if( supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift) ) { 1001 // Use it on new AMD cpus starting from Opteron. 1002 UseNewLongLShift = true; 1003 } 1004 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { 1005 if (supports_sse4a()) { 1006 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron 1007 } else { 1008 UseXmmLoadAndClearUpper = false; 1009 } 1010 } 1011 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { 1012 if( supports_sse4a() ) { 1013 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h' 1014 } else { 1015 UseXmmRegToRegMoveAll = false; 1016 } 1017 } 1018 if( FLAG_IS_DEFAULT(UseXmmI2F) ) { 1019 if( supports_sse4a() ) { 1020 UseXmmI2F = true; 1021 } else { 1022 UseXmmI2F = false; 1023 } 1024 } 1025 if( FLAG_IS_DEFAULT(UseXmmI2D) ) { 1026 if( supports_sse4a() ) { 1027 UseXmmI2D = true; 1028 } else { 1029 UseXmmI2D = false; 1030 } 1031 } 1032 if (supports_sse4_2()) { 1033 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { 1034 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); 1035 } 1036 } else { 1037 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 1038 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); 1039 } 1040 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); 1041 } 1042 1043 // some defaults for AMD family 15h 1044 if ( cpu_family() == 0x15 ) { 1045 // On family 15h processors default is no sw prefetch 1046 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) { 1047 AllocatePrefetchStyle = 0; 1048 } 1049 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW 1050 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) { 1051 AllocatePrefetchInstr = 3; 1052 } 1053 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy 1054 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { 1055 UseXMMForArrayCopy = true; 1056 } 1057 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 1058 UseUnalignedLoadStores = true; 1059 } 1060 } 1061 1062 #ifdef COMPILER2 1063 if (MaxVectorSize > 16) { 1064 // Limit vectors size to 16 bytes on current AMD cpus. 1065 FLAG_SET_DEFAULT(MaxVectorSize, 16); 1066 } 1067 #endif // COMPILER2 1068 } 1069 1070 if( is_intel() ) { // Intel cpus specific settings 1071 if( FLAG_IS_DEFAULT(UseStoreImmI16) ) { 1072 UseStoreImmI16 = false; // don't use it on Intel cpus 1073 } 1074 if( cpu_family() == 6 || cpu_family() == 15 ) { 1075 if( FLAG_IS_DEFAULT(UseAddressNop) ) { 1076 // Use it on all Intel cpus starting from PentiumPro 1077 UseAddressNop = true; 1078 } 1079 } 1080 if( FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper) ) { 1081 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus 1082 } 1083 if( FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll) ) { 1084 if( supports_sse3() ) { 1085 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus 1086 } else { 1087 UseXmmRegToRegMoveAll = false; 1088 } 1089 } 1090 if( cpu_family() == 6 && supports_sse3() ) { // New Intel cpus 1091 #ifdef COMPILER2 1092 if( FLAG_IS_DEFAULT(MaxLoopPad) ) { 1093 // For new Intel cpus do the next optimization: 1094 // don't align the beginning of a loop if there are enough instructions 1095 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp) 1096 // in current fetch line (OptoLoopAlignment) or the padding 1097 // is big (> MaxLoopPad). 1098 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of 1099 // generated NOP instructions. 11 is the largest size of one 1100 // address NOP instruction '0F 1F' (see Assembler::nop(i)). 1101 MaxLoopPad = 11; 1102 } 1103 #endif // COMPILER2 1104 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) { 1105 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus 1106 } 1107 if (supports_sse4_2() && supports_ht()) { // Newest Intel cpus 1108 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 1109 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus 1110 } 1111 } 1112 if (supports_sse4_2()) { 1113 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) { 1114 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true); 1115 } 1116 } else { 1117 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) { 1118 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled."); 1119 } 1120 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false); 1121 } 1122 } 1123 if ((cpu_family() == 0x06) && 1124 ((extended_cpu_model() == 0x36) || // Centerton 1125 (extended_cpu_model() == 0x37) || // Silvermont 1126 (extended_cpu_model() == 0x4D))) { 1127 #ifdef COMPILER2 1128 if (FLAG_IS_DEFAULT(OptoScheduling)) { 1129 OptoScheduling = true; 1130 } 1131 #endif 1132 if (supports_sse4_2()) { // Silvermont 1133 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) { 1134 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus 1135 } 1136 } 1137 } 1138 if(FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) { 1139 AllocatePrefetchInstr = 3; 1140 } 1141 } 1142 1143 #ifdef _LP64 1144 if (UseSSE42Intrinsics) { 1145 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) { 1146 UseVectorizedMismatchIntrinsic = true; 1147 } 1148 } else if (UseVectorizedMismatchIntrinsic) { 1149 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) 1150 warning("vectorizedMismatch intrinsics are not available on this CPU"); 1151 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 1152 } 1153 #else 1154 if (UseVectorizedMismatchIntrinsic) { 1155 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) { 1156 warning("vectorizedMismatch intrinsic is not available in 32-bit VM"); 1157 } 1158 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 1159 } 1160 #endif // _LP64 1161 1162 // Use count leading zeros count instruction if available. 1163 if (supports_lzcnt()) { 1164 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) { 1165 UseCountLeadingZerosInstruction = true; 1166 } 1167 } else if (UseCountLeadingZerosInstruction) { 1168 warning("lzcnt instruction is not available on this CPU"); 1169 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false); 1170 } 1171 1172 // Use count trailing zeros instruction if available 1173 if (supports_bmi1()) { 1174 // tzcnt does not require VEX prefix 1175 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) { 1176 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) { 1177 // Don't use tzcnt if BMI1 is switched off on command line. 1178 UseCountTrailingZerosInstruction = false; 1179 } else { 1180 UseCountTrailingZerosInstruction = true; 1181 } 1182 } 1183 } else if (UseCountTrailingZerosInstruction) { 1184 warning("tzcnt instruction is not available on this CPU"); 1185 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false); 1186 } 1187 1188 // BMI instructions (except tzcnt) use an encoding with VEX prefix. 1189 // VEX prefix is generated only when AVX > 0. 1190 if (supports_bmi1() && supports_avx()) { 1191 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) { 1192 UseBMI1Instructions = true; 1193 } 1194 } else if (UseBMI1Instructions) { 1195 warning("BMI1 instructions are not available on this CPU (AVX is also required)"); 1196 FLAG_SET_DEFAULT(UseBMI1Instructions, false); 1197 } 1198 1199 if (supports_bmi2() && supports_avx()) { 1200 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) { 1201 UseBMI2Instructions = true; 1202 } 1203 } else if (UseBMI2Instructions) { 1204 warning("BMI2 instructions are not available on this CPU (AVX is also required)"); 1205 FLAG_SET_DEFAULT(UseBMI2Instructions, false); 1206 } 1207 1208 // Use population count instruction if available. 1209 if (supports_popcnt()) { 1210 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) { 1211 UsePopCountInstruction = true; 1212 } 1213 } else if (UsePopCountInstruction) { 1214 warning("POPCNT instruction is not available on this CPU"); 1215 FLAG_SET_DEFAULT(UsePopCountInstruction, false); 1216 } 1217 1218 // Use fast-string operations if available. 1219 if (supports_erms()) { 1220 if (FLAG_IS_DEFAULT(UseFastStosb)) { 1221 UseFastStosb = true; 1222 } 1223 } else if (UseFastStosb) { 1224 warning("fast-string operations are not available on this CPU"); 1225 FLAG_SET_DEFAULT(UseFastStosb, false); 1226 } 1227 1228 #ifdef COMPILER2 1229 if (FLAG_IS_DEFAULT(AlignVector)) { 1230 // Modern processors allow misaligned memory operations for vectors. 1231 AlignVector = !UseUnalignedLoadStores; 1232 } 1233 #endif // COMPILER2 1234 1235 if( AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch() ) AllocatePrefetchInstr=0; 1236 if( !supports_sse() && supports_3dnow_prefetch() ) AllocatePrefetchInstr = 3; 1237 1238 // Allocation prefetch settings 1239 intx cache_line_size = prefetch_data_size(); 1240 if( cache_line_size > AllocatePrefetchStepSize ) 1241 AllocatePrefetchStepSize = cache_line_size; 1242 1243 AllocatePrefetchDistance = allocate_prefetch_distance(); 1244 AllocatePrefetchStyle = allocate_prefetch_style(); 1245 1246 if (is_intel() && cpu_family() == 6 && supports_sse3()) { 1247 if (AllocatePrefetchStyle == 2) { // watermark prefetching on Core 1248 #ifdef _LP64 1249 AllocatePrefetchDistance = 384; 1250 #else 1251 AllocatePrefetchDistance = 320; 1252 #endif 1253 } 1254 if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus 1255 AllocatePrefetchDistance = 192; 1256 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) { 1257 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4); 1258 } 1259 } 1260 #ifdef COMPILER2 1261 if (supports_sse4_2()) { 1262 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) { 1263 FLAG_SET_DEFAULT(UseFPUForSpilling, true); 1264 } 1265 } 1266 #endif 1267 } 1268 1269 #ifdef _LP64 1270 // Prefetch settings 1271 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes(); 1272 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes(); 1273 PrefetchFieldsAhead = prefetch_fields_ahead(); 1274 #endif 1275 1276 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) && 1277 (cache_line_size > ContendedPaddingWidth)) 1278 ContendedPaddingWidth = cache_line_size; 1279 1280 // This machine allows unaligned memory accesses 1281 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 1282 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 1283 } 1284 1285 #ifndef PRODUCT 1286 if (log_is_enabled(Info, os, cpu)) { 1287 outputStream* log = Log(os, cpu)::info_stream(); 1288 log->print_cr("Logical CPUs per core: %u", 1289 logical_processors_per_package()); 1290 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size()); 1291 log->print("UseSSE=%d", (int) UseSSE); 1292 if (UseAVX > 0) { 1293 log->print(" UseAVX=%d", (int) UseAVX); 1294 } 1295 if (UseAES) { 1296 log->print(" UseAES=1"); 1297 } 1298 #ifdef COMPILER2 1299 if (MaxVectorSize > 0) { 1300 log->print(" MaxVectorSize=%d", (int) MaxVectorSize); 1301 } 1302 #endif 1303 log->cr(); 1304 log->print("Allocation"); 1305 if (AllocatePrefetchStyle <= 0 || UseSSE == 0 && !supports_3dnow_prefetch()) { 1306 log->print_cr(": no prefetching"); 1307 } else { 1308 log->print(" prefetching: "); 1309 if (UseSSE == 0 && supports_3dnow_prefetch()) { 1310 log->print("PREFETCHW"); 1311 } else if (UseSSE >= 1) { 1312 if (AllocatePrefetchInstr == 0) { 1313 log->print("PREFETCHNTA"); 1314 } else if (AllocatePrefetchInstr == 1) { 1315 log->print("PREFETCHT0"); 1316 } else if (AllocatePrefetchInstr == 2) { 1317 log->print("PREFETCHT2"); 1318 } else if (AllocatePrefetchInstr == 3) { 1319 log->print("PREFETCHW"); 1320 } 1321 } 1322 if (AllocatePrefetchLines > 1) { 1323 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize); 1324 } else { 1325 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize); 1326 } 1327 } 1328 1329 if (PrefetchCopyIntervalInBytes > 0) { 1330 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes); 1331 } 1332 if (PrefetchScanIntervalInBytes > 0) { 1333 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes); 1334 } 1335 if (PrefetchFieldsAhead > 0) { 1336 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead); 1337 } 1338 if (ContendedPaddingWidth > 0) { 1339 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth); 1340 } 1341 } 1342 #endif // !PRODUCT 1343 } 1344 1345 bool VM_Version::use_biased_locking() { 1346 #if INCLUDE_RTM_OPT 1347 // RTM locking is most useful when there is high lock contention and 1348 // low data contention. With high lock contention the lock is usually 1349 // inflated and biased locking is not suitable for that case. 1350 // RTM locking code requires that biased locking is off. 1351 // Note: we can't switch off UseBiasedLocking in get_processor_features() 1352 // because it is used by Thread::allocate() which is called before 1353 // VM_Version::initialize(). 1354 if (UseRTMLocking && UseBiasedLocking) { 1355 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 1356 FLAG_SET_DEFAULT(UseBiasedLocking, false); 1357 } else { 1358 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 1359 UseBiasedLocking = false; 1360 } 1361 } 1362 #endif 1363 return UseBiasedLocking; 1364 } 1365 1366 void VM_Version::initialize() { 1367 ResourceMark rm; 1368 // Making this stub must be FIRST use of assembler 1369 1370 stub_blob = BufferBlob::create("get_cpu_info_stub", stub_size); 1371 if (stub_blob == NULL) { 1372 vm_exit_during_initialization("Unable to allocate get_cpu_info_stub"); 1373 } 1374 CodeBuffer c(stub_blob); 1375 VM_Version_StubGenerator g(&c); 1376 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t, 1377 g.generate_get_cpu_info()); 1378 1379 get_processor_features(); 1380 }