1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "compiler/disassembler.hpp"
29 #include "gc/shared/cardTableModRefBS.hpp"
30 #include "gc/shared/collectedHeap.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "oops/klass.inline.hpp"
35 #include "prims/methodHandles.hpp"
36 #include "runtime/biasedLocking.hpp"
37 #include "runtime/interfaceSupport.hpp"
38 #include "runtime/objectMonitor.hpp"
39 #include "runtime/os.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/stubRoutines.hpp"
42 #include "runtime/thread.hpp"
43 #include "utilities/macros.hpp"
44 #if INCLUDE_ALL_GCS
45 #include "gc/g1/g1CollectedHeap.inline.hpp"
46 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
47 #include "gc/g1/heapRegion.hpp"
48 #endif // INCLUDE_ALL_GCS
49 #include "crc32c.h"
50 #ifdef COMPILER2
51 #include "opto/intrinsicnode.hpp"
52 #endif
53
54 #ifdef PRODUCT
55 #define BLOCK_COMMENT(str) /* nothing */
56 #define STOP(error) stop(error)
57 #else
58 #define BLOCK_COMMENT(str) block_comment(str)
59 #define STOP(error) block_comment(error); stop(error)
60 #endif
61
62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
63
64 #ifdef ASSERT
65 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
66 #endif
67
68 static Assembler::Condition reverse[] = {
69 Assembler::noOverflow /* overflow = 0x0 */ ,
70 Assembler::overflow /* noOverflow = 0x1 */ ,
71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
75 Assembler::above /* belowEqual = 0x6 */ ,
76 Assembler::belowEqual /* above = 0x7 */ ,
77 Assembler::positive /* negative = 0x8 */ ,
78 Assembler::negative /* positive = 0x9 */ ,
79 Assembler::noParity /* parity = 0xa */ ,
80 Assembler::parity /* noParity = 0xb */ ,
81 Assembler::greaterEqual /* less = 0xc */ ,
82 Assembler::less /* greaterEqual = 0xd */ ,
83 Assembler::greater /* lessEqual = 0xe */ ,
84 Assembler::lessEqual /* greater = 0xf, */
85
86 };
87
88
89 // Implementation of MacroAssembler
90
91 // First all the versions that have distinct versions depending on 32/64 bit
92 // Unless the difference is trivial (1 line or so).
93
94 #ifndef _LP64
95
96 // 32bit versions
97
98 Address MacroAssembler::as_Address(AddressLiteral adr) {
99 return Address(adr.target(), adr.rspec());
100 }
101
102 Address MacroAssembler::as_Address(ArrayAddress adr) {
103 return Address::make_array(adr);
104 }
105
106 void MacroAssembler::call_VM_leaf_base(address entry_point,
107 int number_of_arguments) {
108 call(RuntimeAddress(entry_point));
109 increment(rsp, number_of_arguments * wordSize);
110 }
111
112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
114 }
115
116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
118 }
119
120 void MacroAssembler::cmpoop(Address src1, jobject obj) {
121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
122 }
123
124 void MacroAssembler::cmpoop(Register src1, jobject obj) {
125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
126 }
127
128 void MacroAssembler::extend_sign(Register hi, Register lo) {
129 // According to Intel Doc. AP-526, "Integer Divide", p.18.
130 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
131 cdql();
132 } else {
133 movl(hi, lo);
134 sarl(hi, 31);
135 }
136 }
137
138 void MacroAssembler::jC2(Register tmp, Label& L) {
139 // set parity bit if FPU flag C2 is set (via rax)
140 save_rax(tmp);
141 fwait(); fnstsw_ax();
142 sahf();
143 restore_rax(tmp);
144 // branch
145 jcc(Assembler::parity, L);
146 }
147
148 void MacroAssembler::jnC2(Register tmp, Label& L) {
149 // set parity bit if FPU flag C2 is set (via rax)
150 save_rax(tmp);
151 fwait(); fnstsw_ax();
152 sahf();
153 restore_rax(tmp);
154 // branch
155 jcc(Assembler::noParity, L);
156 }
157
158 // 32bit can do a case table jump in one instruction but we no longer allow the base
159 // to be installed in the Address class
160 void MacroAssembler::jump(ArrayAddress entry) {
161 jmp(as_Address(entry));
162 }
163
164 // Note: y_lo will be destroyed
165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
166 // Long compare for Java (semantics as described in JVM spec.)
167 Label high, low, done;
168
169 cmpl(x_hi, y_hi);
170 jcc(Assembler::less, low);
171 jcc(Assembler::greater, high);
172 // x_hi is the return register
173 xorl(x_hi, x_hi);
174 cmpl(x_lo, y_lo);
175 jcc(Assembler::below, low);
176 jcc(Assembler::equal, done);
177
178 bind(high);
179 xorl(x_hi, x_hi);
180 increment(x_hi);
181 jmp(done);
182
183 bind(low);
184 xorl(x_hi, x_hi);
185 decrementl(x_hi);
186
187 bind(done);
188 }
189
190 void MacroAssembler::lea(Register dst, AddressLiteral src) {
191 mov_literal32(dst, (int32_t)src.target(), src.rspec());
192 }
193
194 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
195 // leal(dst, as_Address(adr));
196 // see note in movl as to why we must use a move
197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
198 }
199
200 void MacroAssembler::leave() {
201 mov(rsp, rbp);
202 pop(rbp);
203 }
204
205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
206 // Multiplication of two Java long values stored on the stack
207 // as illustrated below. Result is in rdx:rax.
208 //
209 // rsp ---> [ ?? ] \ \
210 // .... | y_rsp_offset |
211 // [ y_lo ] / (in bytes) | x_rsp_offset
212 // [ y_hi ] | (in bytes)
213 // .... |
214 // [ x_lo ] /
215 // [ x_hi ]
216 // ....
217 //
218 // Basic idea: lo(result) = lo(x_lo * y_lo)
219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
222 Label quick;
223 // load x_hi, y_hi and check if quick
224 // multiplication is possible
225 movl(rbx, x_hi);
226 movl(rcx, y_hi);
227 movl(rax, rbx);
228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
230 // do full multiplication
231 // 1st step
232 mull(y_lo); // x_hi * y_lo
233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
234 // 2nd step
235 movl(rax, x_lo);
236 mull(rcx); // x_lo * y_hi
237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
238 // 3rd step
239 bind(quick); // note: rbx, = 0 if quick multiply!
240 movl(rax, x_lo);
241 mull(y_lo); // x_lo * y_lo
242 addl(rdx, rbx); // correct hi(x_lo * y_lo)
243 }
244
245 void MacroAssembler::lneg(Register hi, Register lo) {
246 negl(lo);
247 adcl(hi, 0);
248 negl(hi);
249 }
250
251 void MacroAssembler::lshl(Register hi, Register lo) {
252 // Java shift left long support (semantics as described in JVM spec., p.305)
253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
254 // shift value is in rcx !
255 assert(hi != rcx, "must not use rcx");
256 assert(lo != rcx, "must not use rcx");
257 const Register s = rcx; // shift count
258 const int n = BitsPerWord;
259 Label L;
260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
261 cmpl(s, n); // if (s < n)
262 jcc(Assembler::less, L); // else (s >= n)
263 movl(hi, lo); // x := x << n
264 xorl(lo, lo);
265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
266 bind(L); // s (mod n) < n
267 shldl(hi, lo); // x := x << s
268 shll(lo);
269 }
270
271
272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
275 assert(hi != rcx, "must not use rcx");
276 assert(lo != rcx, "must not use rcx");
277 const Register s = rcx; // shift count
278 const int n = BitsPerWord;
279 Label L;
280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
281 cmpl(s, n); // if (s < n)
282 jcc(Assembler::less, L); // else (s >= n)
283 movl(lo, hi); // x := x >> n
284 if (sign_extension) sarl(hi, 31);
285 else xorl(hi, hi);
286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
287 bind(L); // s (mod n) < n
288 shrdl(lo, hi); // x := x >> s
289 if (sign_extension) sarl(hi);
290 else shrl(hi);
291 }
292
293 void MacroAssembler::movoop(Register dst, jobject obj) {
294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
295 }
296
297 void MacroAssembler::movoop(Address dst, jobject obj) {
298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
299 }
300
301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
303 }
304
305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
307 }
308
309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
310 // scratch register is not used,
311 // it is defined to match parameters of 64-bit version of this method.
312 if (src.is_lval()) {
313 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
314 } else {
315 movl(dst, as_Address(src));
316 }
317 }
318
319 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
320 movl(as_Address(dst), src);
321 }
322
323 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
324 movl(dst, as_Address(src));
325 }
326
327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
328 void MacroAssembler::movptr(Address dst, intptr_t src) {
329 movl(dst, src);
330 }
331
332
333 void MacroAssembler::pop_callee_saved_registers() {
334 pop(rcx);
335 pop(rdx);
336 pop(rdi);
337 pop(rsi);
338 }
339
340 void MacroAssembler::pop_fTOS() {
341 fld_d(Address(rsp, 0));
342 addl(rsp, 2 * wordSize);
343 }
344
345 void MacroAssembler::push_callee_saved_registers() {
346 push(rsi);
347 push(rdi);
348 push(rdx);
349 push(rcx);
350 }
351
352 void MacroAssembler::push_fTOS() {
353 subl(rsp, 2 * wordSize);
354 fstp_d(Address(rsp, 0));
355 }
356
357
358 void MacroAssembler::pushoop(jobject obj) {
359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
360 }
361
362 void MacroAssembler::pushklass(Metadata* obj) {
363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
364 }
365
366 void MacroAssembler::pushptr(AddressLiteral src) {
367 if (src.is_lval()) {
368 push_literal32((int32_t)src.target(), src.rspec());
369 } else {
370 pushl(as_Address(src));
371 }
372 }
373
374 void MacroAssembler::set_word_if_not_zero(Register dst) {
375 xorl(dst, dst);
376 set_byte_if_not_zero(dst);
377 }
378
379 static void pass_arg0(MacroAssembler* masm, Register arg) {
380 masm->push(arg);
381 }
382
383 static void pass_arg1(MacroAssembler* masm, Register arg) {
384 masm->push(arg);
385 }
386
387 static void pass_arg2(MacroAssembler* masm, Register arg) {
388 masm->push(arg);
389 }
390
391 static void pass_arg3(MacroAssembler* masm, Register arg) {
392 masm->push(arg);
393 }
394
395 #ifndef PRODUCT
396 extern "C" void findpc(intptr_t x);
397 #endif
398
399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
400 // In order to get locks to work, we need to fake a in_VM state
401 JavaThread* thread = JavaThread::current();
402 JavaThreadState saved_state = thread->thread_state();
403 thread->set_thread_state(_thread_in_vm);
404 if (ShowMessageBoxOnError) {
405 JavaThread* thread = JavaThread::current();
406 JavaThreadState saved_state = thread->thread_state();
407 thread->set_thread_state(_thread_in_vm);
408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
409 ttyLocker ttyl;
410 BytecodeCounter::print();
411 }
412 // To see where a verify_oop failed, get $ebx+40/X for this frame.
413 // This is the value of eip which points to where verify_oop will return.
414 if (os::message_box(msg, "Execution stopped, print registers?")) {
415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
416 BREAKPOINT;
417 }
418 } else {
419 ttyLocker ttyl;
420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg);
421 }
422 // Don't assert holding the ttyLock
423 assert(false, "DEBUG MESSAGE: %s", msg);
424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
425 }
426
427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
428 ttyLocker ttyl;
429 FlagSetting fs(Debugging, true);
430 tty->print_cr("eip = 0x%08x", eip);
431 #ifndef PRODUCT
432 if ((WizardMode || Verbose) && PrintMiscellaneous) {
433 tty->cr();
434 findpc(eip);
435 tty->cr();
436 }
437 #endif
438 #define PRINT_REG(rax) \
439 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
440 PRINT_REG(rax);
441 PRINT_REG(rbx);
442 PRINT_REG(rcx);
443 PRINT_REG(rdx);
444 PRINT_REG(rdi);
445 PRINT_REG(rsi);
446 PRINT_REG(rbp);
447 PRINT_REG(rsp);
448 #undef PRINT_REG
449 // Print some words near top of staack.
450 int* dump_sp = (int*) rsp;
451 for (int col1 = 0; col1 < 8; col1++) {
452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
453 os::print_location(tty, *dump_sp++);
454 }
455 for (int row = 0; row < 16; row++) {
456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
457 for (int col = 0; col < 8; col++) {
458 tty->print(" 0x%08x", *dump_sp++);
459 }
460 tty->cr();
461 }
462 // Print some instructions around pc:
463 Disassembler::decode((address)eip-64, (address)eip);
464 tty->print_cr("--------");
465 Disassembler::decode((address)eip, (address)eip+32);
466 }
467
468 void MacroAssembler::stop(const char* msg) {
469 ExternalAddress message((address)msg);
470 // push address of message
471 pushptr(message.addr());
472 { Label L; call(L, relocInfo::none); bind(L); } // push eip
473 pusha(); // push registers
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
475 hlt();
476 }
477
478 void MacroAssembler::warn(const char* msg) {
479 push_CPU_state();
480
481 ExternalAddress message((address) msg);
482 // push address of message
483 pushptr(message.addr());
484
485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
486 addl(rsp, wordSize); // discard argument
487 pop_CPU_state();
488 }
489
490 void MacroAssembler::print_state() {
491 { Label L; call(L, relocInfo::none); bind(L); } // push eip
492 pusha(); // push registers
493
494 push_CPU_state();
495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
496 pop_CPU_state();
497
498 popa();
499 addl(rsp, wordSize);
500 }
501
502 #else // _LP64
503
504 // 64 bit versions
505
506 Address MacroAssembler::as_Address(AddressLiteral adr) {
507 // amd64 always does this as a pc-rel
508 // we can be absolute or disp based on the instruction type
509 // jmp/call are displacements others are absolute
510 assert(!adr.is_lval(), "must be rval");
511 assert(reachable(adr), "must be");
512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
513
514 }
515
516 Address MacroAssembler::as_Address(ArrayAddress adr) {
517 AddressLiteral base = adr.base();
518 lea(rscratch1, base);
519 Address index = adr.index();
520 assert(index._disp == 0, "must not have disp"); // maybe it can?
521 Address array(rscratch1, index._index, index._scale, index._disp);
522 return array;
523 }
524
525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
526 Label L, E;
527
528 #ifdef _WIN64
529 // Windows always allocates space for it's register args
530 assert(num_args <= 4, "only register arguments supported");
531 subq(rsp, frame::arg_reg_save_area_bytes);
532 #endif
533
534 // Align stack if necessary
535 testl(rsp, 15);
536 jcc(Assembler::zero, L);
537
538 subq(rsp, 8);
539 {
540 call(RuntimeAddress(entry_point));
541 }
542 addq(rsp, 8);
543 jmp(E);
544
545 bind(L);
546 {
547 call(RuntimeAddress(entry_point));
548 }
549
550 bind(E);
551
552 #ifdef _WIN64
553 // restore stack pointer
554 addq(rsp, frame::arg_reg_save_area_bytes);
555 #endif
556
557 }
558
559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
560 assert(!src2.is_lval(), "should use cmpptr");
561
562 if (reachable(src2)) {
563 cmpq(src1, as_Address(src2));
564 } else {
565 lea(rscratch1, src2);
566 Assembler::cmpq(src1, Address(rscratch1, 0));
567 }
568 }
569
570 int MacroAssembler::corrected_idivq(Register reg) {
571 // Full implementation of Java ldiv and lrem; checks for special
572 // case as described in JVM spec., p.243 & p.271. The function
573 // returns the (pc) offset of the idivl instruction - may be needed
574 // for implicit exceptions.
575 //
576 // normal case special case
577 //
578 // input : rax: dividend min_long
579 // reg: divisor (may not be eax/edx) -1
580 //
581 // output: rax: quotient (= rax idiv reg) min_long
582 // rdx: remainder (= rax irem reg) 0
583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
584 static const int64_t min_long = 0x8000000000000000;
585 Label normal_case, special_case;
586
587 // check for special case
588 cmp64(rax, ExternalAddress((address) &min_long));
589 jcc(Assembler::notEqual, normal_case);
590 xorl(rdx, rdx); // prepare rdx for possible special case (where
591 // remainder = 0)
592 cmpq(reg, -1);
593 jcc(Assembler::equal, special_case);
594
595 // handle normal case
596 bind(normal_case);
597 cdqq();
598 int idivq_offset = offset();
599 idivq(reg);
600
601 // normal and special case exit
602 bind(special_case);
603
604 return idivq_offset;
605 }
606
607 void MacroAssembler::decrementq(Register reg, int value) {
608 if (value == min_jint) { subq(reg, value); return; }
609 if (value < 0) { incrementq(reg, -value); return; }
610 if (value == 0) { ; return; }
611 if (value == 1 && UseIncDec) { decq(reg) ; return; }
612 /* else */ { subq(reg, value) ; return; }
613 }
614
615 void MacroAssembler::decrementq(Address dst, int value) {
616 if (value == min_jint) { subq(dst, value); return; }
617 if (value < 0) { incrementq(dst, -value); return; }
618 if (value == 0) { ; return; }
619 if (value == 1 && UseIncDec) { decq(dst) ; return; }
620 /* else */ { subq(dst, value) ; return; }
621 }
622
623 void MacroAssembler::incrementq(AddressLiteral dst) {
624 if (reachable(dst)) {
625 incrementq(as_Address(dst));
626 } else {
627 lea(rscratch1, dst);
628 incrementq(Address(rscratch1, 0));
629 }
630 }
631
632 void MacroAssembler::incrementq(Register reg, int value) {
633 if (value == min_jint) { addq(reg, value); return; }
634 if (value < 0) { decrementq(reg, -value); return; }
635 if (value == 0) { ; return; }
636 if (value == 1 && UseIncDec) { incq(reg) ; return; }
637 /* else */ { addq(reg, value) ; return; }
638 }
639
640 void MacroAssembler::incrementq(Address dst, int value) {
641 if (value == min_jint) { addq(dst, value); return; }
642 if (value < 0) { decrementq(dst, -value); return; }
643 if (value == 0) { ; return; }
644 if (value == 1 && UseIncDec) { incq(dst) ; return; }
645 /* else */ { addq(dst, value) ; return; }
646 }
647
648 // 32bit can do a case table jump in one instruction but we no longer allow the base
649 // to be installed in the Address class
650 void MacroAssembler::jump(ArrayAddress entry) {
651 lea(rscratch1, entry.base());
652 Address dispatch = entry.index();
653 assert(dispatch._base == noreg, "must be");
654 dispatch._base = rscratch1;
655 jmp(dispatch);
656 }
657
658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
659 ShouldNotReachHere(); // 64bit doesn't use two regs
660 cmpq(x_lo, y_lo);
661 }
662
663 void MacroAssembler::lea(Register dst, AddressLiteral src) {
664 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
665 }
666
667 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
669 movptr(dst, rscratch1);
670 }
671
672 void MacroAssembler::leave() {
673 // %%% is this really better? Why not on 32bit too?
674 emit_int8((unsigned char)0xC9); // LEAVE
675 }
676
677 void MacroAssembler::lneg(Register hi, Register lo) {
678 ShouldNotReachHere(); // 64bit doesn't use two regs
679 negq(lo);
680 }
681
682 void MacroAssembler::movoop(Register dst, jobject obj) {
683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
684 }
685
686 void MacroAssembler::movoop(Address dst, jobject obj) {
687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
688 movq(dst, rscratch1);
689 }
690
691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
693 }
694
695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
697 movq(dst, rscratch1);
698 }
699
700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
701 if (src.is_lval()) {
702 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
703 } else {
704 if (reachable(src)) {
705 movq(dst, as_Address(src));
706 } else {
707 lea(scratch, src);
708 movq(dst, Address(scratch, 0));
709 }
710 }
711 }
712
713 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
714 movq(as_Address(dst), src);
715 }
716
717 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
718 movq(dst, as_Address(src));
719 }
720
721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
722 void MacroAssembler::movptr(Address dst, intptr_t src) {
723 mov64(rscratch1, src);
724 movq(dst, rscratch1);
725 }
726
727 // These are mostly for initializing NULL
728 void MacroAssembler::movptr(Address dst, int32_t src) {
729 movslq(dst, src);
730 }
731
732 void MacroAssembler::movptr(Register dst, int32_t src) {
733 mov64(dst, (intptr_t)src);
734 }
735
736 void MacroAssembler::pushoop(jobject obj) {
737 movoop(rscratch1, obj);
738 push(rscratch1);
739 }
740
741 void MacroAssembler::pushklass(Metadata* obj) {
742 mov_metadata(rscratch1, obj);
743 push(rscratch1);
744 }
745
746 void MacroAssembler::pushptr(AddressLiteral src) {
747 lea(rscratch1, src);
748 if (src.is_lval()) {
749 push(rscratch1);
750 } else {
751 pushq(Address(rscratch1, 0));
752 }
753 }
754
755 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
756 // we must set sp to zero to clear frame
757 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
758 // must clear fp, so that compiled frames are not confused; it is
759 // possible that we need it only for debugging
760 if (clear_fp) {
761 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
762 }
763
764 // Always clear the pc because it could have been set by make_walkable()
765 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
766 }
767
768 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
769 Register last_java_fp,
770 address last_java_pc) {
771 // determine last_java_sp register
772 if (!last_java_sp->is_valid()) {
773 last_java_sp = rsp;
774 }
775
776 // last_java_fp is optional
777 if (last_java_fp->is_valid()) {
778 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
779 last_java_fp);
780 }
781
782 // last_java_pc is optional
783 if (last_java_pc != NULL) {
784 Address java_pc(r15_thread,
785 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
786 lea(rscratch1, InternalAddress(last_java_pc));
787 movptr(java_pc, rscratch1);
788 }
789
790 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
791 }
792
793 static void pass_arg0(MacroAssembler* masm, Register arg) {
794 if (c_rarg0 != arg ) {
795 masm->mov(c_rarg0, arg);
796 }
797 }
798
799 static void pass_arg1(MacroAssembler* masm, Register arg) {
800 if (c_rarg1 != arg ) {
801 masm->mov(c_rarg1, arg);
802 }
803 }
804
805 static void pass_arg2(MacroAssembler* masm, Register arg) {
806 if (c_rarg2 != arg ) {
807 masm->mov(c_rarg2, arg);
808 }
809 }
810
811 static void pass_arg3(MacroAssembler* masm, Register arg) {
812 if (c_rarg3 != arg ) {
813 masm->mov(c_rarg3, arg);
814 }
815 }
816
817 void MacroAssembler::stop(const char* msg) {
818 address rip = pc();
819 pusha(); // get regs on stack
820 lea(c_rarg0, ExternalAddress((address) msg));
821 lea(c_rarg1, InternalAddress(rip));
822 movq(c_rarg2, rsp); // pass pointer to regs array
823 andq(rsp, -16); // align stack as required by ABI
824 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
825 hlt();
826 }
827
828 void MacroAssembler::warn(const char* msg) {
829 push(rbp);
830 movq(rbp, rsp);
831 andq(rsp, -16); // align stack as required by push_CPU_state and call
832 push_CPU_state(); // keeps alignment at 16 bytes
833 lea(c_rarg0, ExternalAddress((address) msg));
834 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0);
835 pop_CPU_state();
836 mov(rsp, rbp);
837 pop(rbp);
838 }
839
840 void MacroAssembler::print_state() {
841 address rip = pc();
842 pusha(); // get regs on stack
843 push(rbp);
844 movq(rbp, rsp);
845 andq(rsp, -16); // align stack as required by push_CPU_state and call
846 push_CPU_state(); // keeps alignment at 16 bytes
847
848 lea(c_rarg0, InternalAddress(rip));
849 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
850 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
851
852 pop_CPU_state();
853 mov(rsp, rbp);
854 pop(rbp);
855 popa();
856 }
857
858 #ifndef PRODUCT
859 extern "C" void findpc(intptr_t x);
860 #endif
861
862 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
863 // In order to get locks to work, we need to fake a in_VM state
864 if (ShowMessageBoxOnError) {
865 JavaThread* thread = JavaThread::current();
866 JavaThreadState saved_state = thread->thread_state();
867 thread->set_thread_state(_thread_in_vm);
868 #ifndef PRODUCT
869 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
870 ttyLocker ttyl;
871 BytecodeCounter::print();
872 }
873 #endif
874 // To see where a verify_oop failed, get $ebx+40/X for this frame.
875 // XXX correct this offset for amd64
876 // This is the value of eip which points to where verify_oop will return.
877 if (os::message_box(msg, "Execution stopped, print registers?")) {
878 print_state64(pc, regs);
879 BREAKPOINT;
880 assert(false, "start up GDB");
881 }
882 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state);
883 } else {
884 ttyLocker ttyl;
885 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n",
886 msg);
887 assert(false, "DEBUG MESSAGE: %s", msg);
888 }
889 }
890
891 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
892 ttyLocker ttyl;
893 FlagSetting fs(Debugging, true);
894 tty->print_cr("rip = 0x%016lx", pc);
895 #ifndef PRODUCT
896 tty->cr();
897 findpc(pc);
898 tty->cr();
899 #endif
900 #define PRINT_REG(rax, value) \
901 { tty->print("%s = ", #rax); os::print_location(tty, value); }
902 PRINT_REG(rax, regs[15]);
903 PRINT_REG(rbx, regs[12]);
904 PRINT_REG(rcx, regs[14]);
905 PRINT_REG(rdx, regs[13]);
906 PRINT_REG(rdi, regs[8]);
907 PRINT_REG(rsi, regs[9]);
908 PRINT_REG(rbp, regs[10]);
909 PRINT_REG(rsp, regs[11]);
910 PRINT_REG(r8 , regs[7]);
911 PRINT_REG(r9 , regs[6]);
912 PRINT_REG(r10, regs[5]);
913 PRINT_REG(r11, regs[4]);
914 PRINT_REG(r12, regs[3]);
915 PRINT_REG(r13, regs[2]);
916 PRINT_REG(r14, regs[1]);
917 PRINT_REG(r15, regs[0]);
918 #undef PRINT_REG
919 // Print some words near top of staack.
920 int64_t* rsp = (int64_t*) regs[11];
921 int64_t* dump_sp = rsp;
922 for (int col1 = 0; col1 < 8; col1++) {
923 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
924 os::print_location(tty, *dump_sp++);
925 }
926 for (int row = 0; row < 25; row++) {
927 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp);
928 for (int col = 0; col < 4; col++) {
929 tty->print(" 0x%016lx", *dump_sp++);
930 }
931 tty->cr();
932 }
933 // Print some instructions around pc:
934 Disassembler::decode((address)pc-64, (address)pc);
935 tty->print_cr("--------");
936 Disassembler::decode((address)pc, (address)pc+32);
937 }
938
939 #endif // _LP64
940
941 // Now versions that are common to 32/64 bit
942
943 void MacroAssembler::addptr(Register dst, int32_t imm32) {
944 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
945 }
946
947 void MacroAssembler::addptr(Register dst, Register src) {
948 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
949 }
950
951 void MacroAssembler::addptr(Address dst, Register src) {
952 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
953 }
954
955 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
956 if (reachable(src)) {
957 Assembler::addsd(dst, as_Address(src));
958 } else {
959 lea(rscratch1, src);
960 Assembler::addsd(dst, Address(rscratch1, 0));
961 }
962 }
963
964 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
965 if (reachable(src)) {
966 addss(dst, as_Address(src));
967 } else {
968 lea(rscratch1, src);
969 addss(dst, Address(rscratch1, 0));
970 }
971 }
972
973 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
974 if (reachable(src)) {
975 Assembler::addpd(dst, as_Address(src));
976 } else {
977 lea(rscratch1, src);
978 Assembler::addpd(dst, Address(rscratch1, 0));
979 }
980 }
981
982 void MacroAssembler::align(int modulus) {
983 align(modulus, offset());
984 }
985
986 void MacroAssembler::align(int modulus, int target) {
987 if (target % modulus != 0) {
988 nop(modulus - (target % modulus));
989 }
990 }
991
992 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) {
993 // Used in sign-masking with aligned address.
994 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
995 if (reachable(src)) {
996 Assembler::andpd(dst, as_Address(src));
997 } else {
998 lea(rscratch1, src);
999 Assembler::andpd(dst, Address(rscratch1, 0));
1000 }
1001 }
1002
1003 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) {
1004 // Used in sign-masking with aligned address.
1005 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1006 if (reachable(src)) {
1007 Assembler::andps(dst, as_Address(src));
1008 } else {
1009 lea(rscratch1, src);
1010 Assembler::andps(dst, Address(rscratch1, 0));
1011 }
1012 }
1013
1014 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1015 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1016 }
1017
1018 void MacroAssembler::atomic_incl(Address counter_addr) {
1019 if (os::is_MP())
1020 lock();
1021 incrementl(counter_addr);
1022 }
1023
1024 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1025 if (reachable(counter_addr)) {
1026 atomic_incl(as_Address(counter_addr));
1027 } else {
1028 lea(scr, counter_addr);
1029 atomic_incl(Address(scr, 0));
1030 }
1031 }
1032
1033 #ifdef _LP64
1034 void MacroAssembler::atomic_incq(Address counter_addr) {
1035 if (os::is_MP())
1036 lock();
1037 incrementq(counter_addr);
1038 }
1039
1040 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1041 if (reachable(counter_addr)) {
1042 atomic_incq(as_Address(counter_addr));
1043 } else {
1044 lea(scr, counter_addr);
1045 atomic_incq(Address(scr, 0));
1046 }
1047 }
1048 #endif
1049
1050 // Writes to stack successive pages until offset reached to check for
1051 // stack overflow + shadow pages. This clobbers tmp.
1052 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1053 movptr(tmp, rsp);
1054 // Bang stack for total size given plus shadow page size.
1055 // Bang one page at a time because large size can bang beyond yellow and
1056 // red zones.
1057 Label loop;
1058 bind(loop);
1059 movl(Address(tmp, (-os::vm_page_size())), size );
1060 subptr(tmp, os::vm_page_size());
1061 subl(size, os::vm_page_size());
1062 jcc(Assembler::greater, loop);
1063
1064 // Bang down shadow pages too.
1065 // At this point, (tmp-0) is the last address touched, so don't
1066 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1067 // was post-decremented.) Skip this address by starting at i=1, and
1068 // touch a few more pages below. N.B. It is important to touch all
1069 // the way down including all pages in the shadow zone.
1070 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1071 // this could be any sized move but this is can be a debugging crumb
1072 // so the bigger the better.
1073 movptr(Address(tmp, (-i*os::vm_page_size())), size );
1074 }
1075 }
1076
1077 void MacroAssembler::reserved_stack_check() {
1078 // testing if reserved zone needs to be enabled
1079 Label no_reserved_zone_enabling;
1080 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1081 NOT_LP64(get_thread(rsi);)
1082
1083 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1084 jcc(Assembler::below, no_reserved_zone_enabling);
1085
1086 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1087 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1088 should_not_reach_here();
1089
1090 bind(no_reserved_zone_enabling);
1091 }
1092
1093 int MacroAssembler::biased_locking_enter(Register lock_reg,
1094 Register obj_reg,
1095 Register swap_reg,
1096 Register tmp_reg,
1097 bool swap_reg_contains_mark,
1098 Label& done,
1099 Label* slow_case,
1100 BiasedLockingCounters* counters) {
1101 assert(UseBiasedLocking, "why call this otherwise?");
1102 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq");
1103 assert(tmp_reg != noreg, "tmp_reg must be supplied");
1104 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg);
1105 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout");
1106 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes());
1107 NOT_LP64( Address saved_mark_addr(lock_reg, 0); )
1108
1109 if (PrintBiasedLockingStatistics && counters == NULL) {
1110 counters = BiasedLocking::counters();
1111 }
1112 // Biased locking
1113 // See whether the lock is currently biased toward our thread and
1114 // whether the epoch is still valid
1115 // Note that the runtime guarantees sufficient alignment of JavaThread
1116 // pointers to allow age to be placed into low bits
1117 // First check to see whether biasing is even enabled for this object
1118 Label cas_label;
1119 int null_check_offset = -1;
1120 if (!swap_reg_contains_mark) {
1121 null_check_offset = offset();
1122 movptr(swap_reg, mark_addr);
1123 }
1124 movptr(tmp_reg, swap_reg);
1125 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place);
1126 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern);
1127 jcc(Assembler::notEqual, cas_label);
1128 // The bias pattern is present in the object's header. Need to check
1129 // whether the bias owner and the epoch are both still current.
1130 #ifndef _LP64
1131 // Note that because there is no current thread register on x86_32 we
1132 // need to store off the mark word we read out of the object to
1133 // avoid reloading it and needing to recheck invariants below. This
1134 // store is unfortunate but it makes the overall code shorter and
1135 // simpler.
1136 movptr(saved_mark_addr, swap_reg);
1137 #endif
1138 if (swap_reg_contains_mark) {
1139 null_check_offset = offset();
1140 }
1141 load_prototype_header(tmp_reg, obj_reg);
1142 #ifdef _LP64
1143 orptr(tmp_reg, r15_thread);
1144 xorptr(tmp_reg, swap_reg);
1145 Register header_reg = tmp_reg;
1146 #else
1147 xorptr(tmp_reg, swap_reg);
1148 get_thread(swap_reg);
1149 xorptr(swap_reg, tmp_reg);
1150 Register header_reg = swap_reg;
1151 #endif
1152 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place));
1153 if (counters != NULL) {
1154 cond_inc32(Assembler::zero,
1155 ExternalAddress((address) counters->biased_lock_entry_count_addr()));
1156 }
1157 jcc(Assembler::equal, done);
1158
1159 Label try_revoke_bias;
1160 Label try_rebias;
1161
1162 // At this point we know that the header has the bias pattern and
1163 // that we are not the bias owner in the current epoch. We need to
1164 // figure out more details about the state of the header in order to
1165 // know what operations can be legally performed on the object's
1166 // header.
1167
1168 // If the low three bits in the xor result aren't clear, that means
1169 // the prototype header is no longer biased and we have to revoke
1170 // the bias on this object.
1171 testptr(header_reg, markOopDesc::biased_lock_mask_in_place);
1172 jccb(Assembler::notZero, try_revoke_bias);
1173
1174 // Biasing is still enabled for this data type. See whether the
1175 // epoch of the current bias is still valid, meaning that the epoch
1176 // bits of the mark word are equal to the epoch bits of the
1177 // prototype header. (Note that the prototype header's epoch bits
1178 // only change at a safepoint.) If not, attempt to rebias the object
1179 // toward the current thread. Note that we must be absolutely sure
1180 // that the current epoch is invalid in order to do this because
1181 // otherwise the manipulations it performs on the mark word are
1182 // illegal.
1183 testptr(header_reg, markOopDesc::epoch_mask_in_place);
1184 jccb(Assembler::notZero, try_rebias);
1185
1186 // The epoch of the current bias is still valid but we know nothing
1187 // about the owner; it might be set or it might be clear. Try to
1188 // acquire the bias of the object using an atomic operation. If this
1189 // fails we will go in to the runtime to revoke the object's bias.
1190 // Note that we first construct the presumed unbiased header so we
1191 // don't accidentally blow away another thread's valid bias.
1192 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1193 andptr(swap_reg,
1194 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
1195 #ifdef _LP64
1196 movptr(tmp_reg, swap_reg);
1197 orptr(tmp_reg, r15_thread);
1198 #else
1199 get_thread(tmp_reg);
1200 orptr(tmp_reg, swap_reg);
1201 #endif
1202 if (os::is_MP()) {
1203 lock();
1204 }
1205 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1206 // If the biasing toward our thread failed, this means that
1207 // another thread succeeded in biasing it toward itself and we
1208 // need to revoke that bias. The revocation will occur in the
1209 // interpreter runtime in the slow case.
1210 if (counters != NULL) {
1211 cond_inc32(Assembler::zero,
1212 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr()));
1213 }
1214 if (slow_case != NULL) {
1215 jcc(Assembler::notZero, *slow_case);
1216 }
1217 jmp(done);
1218
1219 bind(try_rebias);
1220 // At this point we know the epoch has expired, meaning that the
1221 // current "bias owner", if any, is actually invalid. Under these
1222 // circumstances _only_, we are allowed to use the current header's
1223 // value as the comparison value when doing the cas to acquire the
1224 // bias in the current epoch. In other words, we allow transfer of
1225 // the bias from one thread to another directly in this situation.
1226 //
1227 // FIXME: due to a lack of registers we currently blow away the age
1228 // bits in this situation. Should attempt to preserve them.
1229 load_prototype_header(tmp_reg, obj_reg);
1230 #ifdef _LP64
1231 orptr(tmp_reg, r15_thread);
1232 #else
1233 get_thread(swap_reg);
1234 orptr(tmp_reg, swap_reg);
1235 movptr(swap_reg, saved_mark_addr);
1236 #endif
1237 if (os::is_MP()) {
1238 lock();
1239 }
1240 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1241 // If the biasing toward our thread failed, then another thread
1242 // succeeded in biasing it toward itself and we need to revoke that
1243 // bias. The revocation will occur in the runtime in the slow case.
1244 if (counters != NULL) {
1245 cond_inc32(Assembler::zero,
1246 ExternalAddress((address) counters->rebiased_lock_entry_count_addr()));
1247 }
1248 if (slow_case != NULL) {
1249 jcc(Assembler::notZero, *slow_case);
1250 }
1251 jmp(done);
1252
1253 bind(try_revoke_bias);
1254 // The prototype mark in the klass doesn't have the bias bit set any
1255 // more, indicating that objects of this data type are not supposed
1256 // to be biased any more. We are going to try to reset the mark of
1257 // this object to the prototype value and fall through to the
1258 // CAS-based locking scheme. Note that if our CAS fails, it means
1259 // that another thread raced us for the privilege of revoking the
1260 // bias of this particular object, so it's okay to continue in the
1261 // normal locking code.
1262 //
1263 // FIXME: due to a lack of registers we currently blow away the age
1264 // bits in this situation. Should attempt to preserve them.
1265 NOT_LP64( movptr(swap_reg, saved_mark_addr); )
1266 load_prototype_header(tmp_reg, obj_reg);
1267 if (os::is_MP()) {
1268 lock();
1269 }
1270 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg
1271 // Fall through to the normal CAS-based lock, because no matter what
1272 // the result of the above CAS, some thread must have succeeded in
1273 // removing the bias bit from the object's header.
1274 if (counters != NULL) {
1275 cond_inc32(Assembler::zero,
1276 ExternalAddress((address) counters->revoked_lock_entry_count_addr()));
1277 }
1278
1279 bind(cas_label);
1280
1281 return null_check_offset;
1282 }
1283
1284 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) {
1285 assert(UseBiasedLocking, "why call this otherwise?");
1286
1287 // Check for biased locking unlock case, which is a no-op
1288 // Note: we do not have to check the thread ID for two reasons.
1289 // First, the interpreter checks for IllegalMonitorStateException at
1290 // a higher level. Second, if the bias was revoked while we held the
1291 // lock, the object could not be rebiased toward another thread, so
1292 // the bias bit would be clear.
1293 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
1294 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place);
1295 cmpptr(temp_reg, markOopDesc::biased_lock_pattern);
1296 jcc(Assembler::equal, done);
1297 }
1298
1299 #ifdef COMPILER2
1300
1301 #if INCLUDE_RTM_OPT
1302
1303 // Update rtm_counters based on abort status
1304 // input: abort_status
1305 // rtm_counters (RTMLockingCounters*)
1306 // flags are killed
1307 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) {
1308
1309 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset()));
1310 if (PrintPreciseRTMLockingStatistics) {
1311 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) {
1312 Label check_abort;
1313 testl(abort_status, (1<<i));
1314 jccb(Assembler::equal, check_abort);
1315 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx))));
1316 bind(check_abort);
1317 }
1318 }
1319 }
1320
1321 // Branch if (random & (count-1) != 0), count is 2^n
1322 // tmp, scr and flags are killed
1323 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) {
1324 assert(tmp == rax, "");
1325 assert(scr == rdx, "");
1326 rdtsc(); // modifies EDX:EAX
1327 andptr(tmp, count-1);
1328 jccb(Assembler::notZero, brLabel);
1329 }
1330
1331 // Perform abort ratio calculation, set no_rtm bit if high ratio
1332 // input: rtm_counters_Reg (RTMLockingCounters* address)
1333 // tmpReg, rtm_counters_Reg and flags are killed
1334 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg,
1335 Register rtm_counters_Reg,
1336 RTMLockingCounters* rtm_counters,
1337 Metadata* method_data) {
1338 Label L_done, L_check_always_rtm1, L_check_always_rtm2;
1339
1340 if (RTMLockingCalculationDelay > 0) {
1341 // Delay calculation
1342 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg);
1343 testptr(tmpReg, tmpReg);
1344 jccb(Assembler::equal, L_done);
1345 }
1346 // Abort ratio calculation only if abort_count > RTMAbortThreshold
1347 // Aborted transactions = abort_count * 100
1348 // All transactions = total_count * RTMTotalCountIncrRate
1349 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio)
1350
1351 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset()));
1352 cmpptr(tmpReg, RTMAbortThreshold);
1353 jccb(Assembler::below, L_check_always_rtm2);
1354 imulptr(tmpReg, tmpReg, 100);
1355
1356 Register scrReg = rtm_counters_Reg;
1357 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1358 imulptr(scrReg, scrReg, RTMTotalCountIncrRate);
1359 imulptr(scrReg, scrReg, RTMAbortRatio);
1360 cmpptr(tmpReg, scrReg);
1361 jccb(Assembler::below, L_check_always_rtm1);
1362 if (method_data != NULL) {
1363 // set rtm_state to "no rtm" in MDO
1364 mov_metadata(tmpReg, method_data);
1365 if (os::is_MP()) {
1366 lock();
1367 }
1368 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM);
1369 }
1370 jmpb(L_done);
1371 bind(L_check_always_rtm1);
1372 // Reload RTMLockingCounters* address
1373 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1374 bind(L_check_always_rtm2);
1375 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset()));
1376 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate);
1377 jccb(Assembler::below, L_done);
1378 if (method_data != NULL) {
1379 // set rtm_state to "always rtm" in MDO
1380 mov_metadata(tmpReg, method_data);
1381 if (os::is_MP()) {
1382 lock();
1383 }
1384 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM);
1385 }
1386 bind(L_done);
1387 }
1388
1389 // Update counters and perform abort ratio calculation
1390 // input: abort_status_Reg
1391 // rtm_counters_Reg, flags are killed
1392 void MacroAssembler::rtm_profiling(Register abort_status_Reg,
1393 Register rtm_counters_Reg,
1394 RTMLockingCounters* rtm_counters,
1395 Metadata* method_data,
1396 bool profile_rtm) {
1397
1398 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1399 // update rtm counters based on rax value at abort
1400 // reads abort_status_Reg, updates flags
1401 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters));
1402 rtm_counters_update(abort_status_Reg, rtm_counters_Reg);
1403 if (profile_rtm) {
1404 // Save abort status because abort_status_Reg is used by following code.
1405 if (RTMRetryCount > 0) {
1406 push(abort_status_Reg);
1407 }
1408 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1409 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data);
1410 // restore abort status
1411 if (RTMRetryCount > 0) {
1412 pop(abort_status_Reg);
1413 }
1414 }
1415 }
1416
1417 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4)
1418 // inputs: retry_count_Reg
1419 // : abort_status_Reg
1420 // output: retry_count_Reg decremented by 1
1421 // flags are killed
1422 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) {
1423 Label doneRetry;
1424 assert(abort_status_Reg == rax, "");
1425 // The abort reason bits are in eax (see all states in rtmLocking.hpp)
1426 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4)
1427 // if reason is in 0x6 and retry count != 0 then retry
1428 andptr(abort_status_Reg, 0x6);
1429 jccb(Assembler::zero, doneRetry);
1430 testl(retry_count_Reg, retry_count_Reg);
1431 jccb(Assembler::zero, doneRetry);
1432 pause();
1433 decrementl(retry_count_Reg);
1434 jmp(retryLabel);
1435 bind(doneRetry);
1436 }
1437
1438 // Spin and retry if lock is busy,
1439 // inputs: box_Reg (monitor address)
1440 // : retry_count_Reg
1441 // output: retry_count_Reg decremented by 1
1442 // : clear z flag if retry count exceeded
1443 // tmp_Reg, scr_Reg, flags are killed
1444 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg,
1445 Register tmp_Reg, Register scr_Reg, Label& retryLabel) {
1446 Label SpinLoop, SpinExit, doneRetry;
1447 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1448
1449 testl(retry_count_Reg, retry_count_Reg);
1450 jccb(Assembler::zero, doneRetry);
1451 decrementl(retry_count_Reg);
1452 movptr(scr_Reg, RTMSpinLoopCount);
1453
1454 bind(SpinLoop);
1455 pause();
1456 decrementl(scr_Reg);
1457 jccb(Assembler::lessEqual, SpinExit);
1458 movptr(tmp_Reg, Address(box_Reg, owner_offset));
1459 testptr(tmp_Reg, tmp_Reg);
1460 jccb(Assembler::notZero, SpinLoop);
1461
1462 bind(SpinExit);
1463 jmp(retryLabel);
1464 bind(doneRetry);
1465 incrementl(retry_count_Reg); // clear z flag
1466 }
1467
1468 // Use RTM for normal stack locks
1469 // Input: objReg (object to lock)
1470 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg,
1471 Register retry_on_abort_count_Reg,
1472 RTMLockingCounters* stack_rtm_counters,
1473 Metadata* method_data, bool profile_rtm,
1474 Label& DONE_LABEL, Label& IsInflated) {
1475 assert(UseRTMForStackLocks, "why call this otherwise?");
1476 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1477 assert(tmpReg == rax, "");
1478 assert(scrReg == rdx, "");
1479 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1480
1481 if (RTMRetryCount > 0) {
1482 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1483 bind(L_rtm_retry);
1484 }
1485 movptr(tmpReg, Address(objReg, 0));
1486 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1487 jcc(Assembler::notZero, IsInflated);
1488
1489 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1490 Label L_noincrement;
1491 if (RTMTotalCountIncrRate > 1) {
1492 // tmpReg, scrReg and flags are killed
1493 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1494 }
1495 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM");
1496 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg);
1497 bind(L_noincrement);
1498 }
1499 xbegin(L_on_abort);
1500 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1501 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1502 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1503 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked
1504
1505 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1506 if (UseRTMXendForLockBusy) {
1507 xend();
1508 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry)
1509 jmp(L_decrement_retry);
1510 }
1511 else {
1512 xabort(0);
1513 }
1514 bind(L_on_abort);
1515 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1516 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm);
1517 }
1518 bind(L_decrement_retry);
1519 if (RTMRetryCount > 0) {
1520 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1521 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1522 }
1523 }
1524
1525 // Use RTM for inflating locks
1526 // inputs: objReg (object to lock)
1527 // boxReg (on-stack box address (displaced header location) - KILLED)
1528 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value)
1529 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg,
1530 Register scrReg, Register retry_on_busy_count_Reg,
1531 Register retry_on_abort_count_Reg,
1532 RTMLockingCounters* rtm_counters,
1533 Metadata* method_data, bool profile_rtm,
1534 Label& DONE_LABEL) {
1535 assert(UseRTMLocking, "why call this otherwise?");
1536 assert(tmpReg == rax, "");
1537 assert(scrReg == rdx, "");
1538 Label L_rtm_retry, L_decrement_retry, L_on_abort;
1539 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
1540
1541 // Without cast to int32_t a movptr will destroy r10 which is typically obj
1542 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1543 movptr(boxReg, tmpReg); // Save ObjectMonitor address
1544
1545 if (RTMRetryCount > 0) {
1546 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy
1547 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort
1548 bind(L_rtm_retry);
1549 }
1550 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1551 Label L_noincrement;
1552 if (RTMTotalCountIncrRate > 1) {
1553 // tmpReg, scrReg and flags are killed
1554 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement);
1555 }
1556 assert(rtm_counters != NULL, "should not be NULL when profiling RTM");
1557 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg);
1558 bind(L_noincrement);
1559 }
1560 xbegin(L_on_abort);
1561 movptr(tmpReg, Address(objReg, 0));
1562 movptr(tmpReg, Address(tmpReg, owner_offset));
1563 testptr(tmpReg, tmpReg);
1564 jcc(Assembler::zero, DONE_LABEL);
1565 if (UseRTMXendForLockBusy) {
1566 xend();
1567 jmp(L_decrement_retry);
1568 }
1569 else {
1570 xabort(0);
1571 }
1572 bind(L_on_abort);
1573 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX
1574 if (PrintPreciseRTMLockingStatistics || profile_rtm) {
1575 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm);
1576 }
1577 if (RTMRetryCount > 0) {
1578 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4)
1579 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry);
1580 }
1581
1582 movptr(tmpReg, Address(boxReg, owner_offset)) ;
1583 testptr(tmpReg, tmpReg) ;
1584 jccb(Assembler::notZero, L_decrement_retry) ;
1585
1586 // Appears unlocked - try to swing _owner from null to non-null.
1587 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1588 #ifdef _LP64
1589 Register threadReg = r15_thread;
1590 #else
1591 get_thread(scrReg);
1592 Register threadReg = scrReg;
1593 #endif
1594 if (os::is_MP()) {
1595 lock();
1596 }
1597 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg
1598
1599 if (RTMRetryCount > 0) {
1600 // success done else retry
1601 jccb(Assembler::equal, DONE_LABEL) ;
1602 bind(L_decrement_retry);
1603 // Spin and retry if lock is busy.
1604 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry);
1605 }
1606 else {
1607 bind(L_decrement_retry);
1608 }
1609 }
1610
1611 #endif // INCLUDE_RTM_OPT
1612
1613 // Fast_Lock and Fast_Unlock used by C2
1614
1615 // Because the transitions from emitted code to the runtime
1616 // monitorenter/exit helper stubs are so slow it's critical that
1617 // we inline both the stack-locking fast-path and the inflated fast path.
1618 //
1619 // See also: cmpFastLock and cmpFastUnlock.
1620 //
1621 // What follows is a specialized inline transliteration of the code
1622 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat
1623 // another option would be to emit TrySlowEnter and TrySlowExit methods
1624 // at startup-time. These methods would accept arguments as
1625 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure
1626 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply
1627 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit.
1628 // In practice, however, the # of lock sites is bounded and is usually small.
1629 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer
1630 // if the processor uses simple bimodal branch predictors keyed by EIP
1631 // Since the helper routines would be called from multiple synchronization
1632 // sites.
1633 //
1634 // An even better approach would be write "MonitorEnter()" and "MonitorExit()"
1635 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites
1636 // to those specialized methods. That'd give us a mostly platform-independent
1637 // implementation that the JITs could optimize and inline at their pleasure.
1638 // Done correctly, the only time we'd need to cross to native could would be
1639 // to park() or unpark() threads. We'd also need a few more unsafe operators
1640 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and
1641 // (b) explicit barriers or fence operations.
1642 //
1643 // TODO:
1644 //
1645 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr).
1646 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals.
1647 // Given TLAB allocation, Self is usually manifested in a register, so passing it into
1648 // the lock operators would typically be faster than reifying Self.
1649 //
1650 // * Ideally I'd define the primitives as:
1651 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED.
1652 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED
1653 // Unfortunately ADLC bugs prevent us from expressing the ideal form.
1654 // Instead, we're stuck with a rather awkward and brittle register assignments below.
1655 // Furthermore the register assignments are overconstrained, possibly resulting in
1656 // sub-optimal code near the synchronization site.
1657 //
1658 // * Eliminate the sp-proximity tests and just use "== Self" tests instead.
1659 // Alternately, use a better sp-proximity test.
1660 //
1661 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value.
1662 // Either one is sufficient to uniquely identify a thread.
1663 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead.
1664 //
1665 // * Intrinsify notify() and notifyAll() for the common cases where the
1666 // object is locked by the calling thread but the waitlist is empty.
1667 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll().
1668 //
1669 // * use jccb and jmpb instead of jcc and jmp to improve code density.
1670 // But beware of excessive branch density on AMD Opterons.
1671 //
1672 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success
1673 // or failure of the fast-path. If the fast-path fails then we pass
1674 // control to the slow-path, typically in C. In Fast_Lock and
1675 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2
1676 // will emit a conditional branch immediately after the node.
1677 // So we have branches to branches and lots of ICC.ZF games.
1678 // Instead, it might be better to have C2 pass a "FailureLabel"
1679 // into Fast_Lock and Fast_Unlock. In the case of success, control
1680 // will drop through the node. ICC.ZF is undefined at exit.
1681 // In the case of failure, the node will branch directly to the
1682 // FailureLabel
1683
1684
1685 // obj: object to lock
1686 // box: on-stack box address (displaced header location) - KILLED
1687 // rax,: tmp -- KILLED
1688 // scr: tmp -- KILLED
1689 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg,
1690 Register scrReg, Register cx1Reg, Register cx2Reg,
1691 BiasedLockingCounters* counters,
1692 RTMLockingCounters* rtm_counters,
1693 RTMLockingCounters* stack_rtm_counters,
1694 Metadata* method_data,
1695 bool use_rtm, bool profile_rtm) {
1696 // Ensure the register assignments are disjoint
1697 assert(tmpReg == rax, "");
1698
1699 if (use_rtm) {
1700 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg);
1701 } else {
1702 assert(cx1Reg == noreg, "");
1703 assert(cx2Reg == noreg, "");
1704 assert_different_registers(objReg, boxReg, tmpReg, scrReg);
1705 }
1706
1707 if (counters != NULL) {
1708 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg);
1709 }
1710 if (EmitSync & 1) {
1711 // set box->dhw = markOopDesc::unused_mark()
1712 // Force all sync thru slow-path: slow_enter() and slow_exit()
1713 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1714 cmpptr (rsp, (int32_t)NULL_WORD);
1715 } else {
1716 // Possible cases that we'll encounter in fast_lock
1717 // ------------------------------------------------
1718 // * Inflated
1719 // -- unlocked
1720 // -- Locked
1721 // = by self
1722 // = by other
1723 // * biased
1724 // -- by Self
1725 // -- by other
1726 // * neutral
1727 // * stack-locked
1728 // -- by self
1729 // = sp-proximity test hits
1730 // = sp-proximity test generates false-negative
1731 // -- by other
1732 //
1733
1734 Label IsInflated, DONE_LABEL;
1735
1736 // it's stack-locked, biased or neutral
1737 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage
1738 // order to reduce the number of conditional branches in the most common cases.
1739 // Beware -- there's a subtle invariant that fetch of the markword
1740 // at [FETCH], below, will never observe a biased encoding (*101b).
1741 // If this invariant is not held we risk exclusion (safety) failure.
1742 if (UseBiasedLocking && !UseOptoBiasInlining) {
1743 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters);
1744 }
1745
1746 #if INCLUDE_RTM_OPT
1747 if (UseRTMForStackLocks && use_rtm) {
1748 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg,
1749 stack_rtm_counters, method_data, profile_rtm,
1750 DONE_LABEL, IsInflated);
1751 }
1752 #endif // INCLUDE_RTM_OPT
1753
1754 movptr(tmpReg, Address(objReg, 0)); // [FETCH]
1755 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased
1756 jccb(Assembler::notZero, IsInflated);
1757
1758 // Attempt stack-locking ...
1759 orptr (tmpReg, markOopDesc::unlocked_value);
1760 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS
1761 if (os::is_MP()) {
1762 lock();
1763 }
1764 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg
1765 if (counters != NULL) {
1766 cond_inc32(Assembler::equal,
1767 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1768 }
1769 jcc(Assembler::equal, DONE_LABEL); // Success
1770
1771 // Recursive locking.
1772 // The object is stack-locked: markword contains stack pointer to BasicLock.
1773 // Locked by current thread if difference with current SP is less than one page.
1774 subptr(tmpReg, rsp);
1775 // Next instruction set ZFlag == 1 (Success) if difference is less then one page.
1776 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) );
1777 movptr(Address(boxReg, 0), tmpReg);
1778 if (counters != NULL) {
1779 cond_inc32(Assembler::equal,
1780 ExternalAddress((address)counters->fast_path_entry_count_addr()));
1781 }
1782 jmp(DONE_LABEL);
1783
1784 bind(IsInflated);
1785 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value
1786
1787 #if INCLUDE_RTM_OPT
1788 // Use the same RTM locking code in 32- and 64-bit VM.
1789 if (use_rtm) {
1790 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg,
1791 rtm_counters, method_data, profile_rtm, DONE_LABEL);
1792 } else {
1793 #endif // INCLUDE_RTM_OPT
1794
1795 #ifndef _LP64
1796 // The object is inflated.
1797
1798 // boxReg refers to the on-stack BasicLock in the current frame.
1799 // We'd like to write:
1800 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices.
1801 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers
1802 // additional latency as we have another ST in the store buffer that must drain.
1803
1804 if (EmitSync & 8192) {
1805 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty
1806 get_thread (scrReg);
1807 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1808 movptr(tmpReg, NULL_WORD); // consider: xor vs mov
1809 if (os::is_MP()) {
1810 lock();
1811 }
1812 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1813 } else
1814 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS
1815 // register juggle because we need tmpReg for cmpxchgptr below
1816 movptr(scrReg, boxReg);
1817 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2]
1818
1819 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1820 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1821 // prefetchw [eax + Offset(_owner)-2]
1822 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1823 }
1824
1825 if ((EmitSync & 64) == 0) {
1826 // Optimistic form: consider XORL tmpReg,tmpReg
1827 movptr(tmpReg, NULL_WORD);
1828 } else {
1829 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1830 // Test-And-CAS instead of CAS
1831 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1832 testptr(tmpReg, tmpReg); // Locked ?
1833 jccb (Assembler::notZero, DONE_LABEL);
1834 }
1835
1836 // Appears unlocked - try to swing _owner from null to non-null.
1837 // Ideally, I'd manifest "Self" with get_thread and then attempt
1838 // to CAS the register containing Self into m->Owner.
1839 // But we don't have enough registers, so instead we can either try to CAS
1840 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds
1841 // we later store "Self" into m->Owner. Transiently storing a stack address
1842 // (rsp or the address of the box) into m->owner is harmless.
1843 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1844 if (os::is_MP()) {
1845 lock();
1846 }
1847 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1848 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3
1849 // If we weren't able to swing _owner from NULL to the BasicLock
1850 // then take the slow path.
1851 jccb (Assembler::notZero, DONE_LABEL);
1852 // update _owner from BasicLock to thread
1853 get_thread (scrReg); // beware: clobbers ICCs
1854 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg);
1855 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success
1856
1857 // If the CAS fails we can either retry or pass control to the slow-path.
1858 // We use the latter tactic.
1859 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1860 // If the CAS was successful ...
1861 // Self has acquired the lock
1862 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1863 // Intentional fall-through into DONE_LABEL ...
1864 } else {
1865 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty
1866 movptr(boxReg, tmpReg);
1867
1868 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes
1869 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
1870 // prefetchw [eax + Offset(_owner)-2]
1871 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1872 }
1873
1874 if ((EmitSync & 64) == 0) {
1875 // Optimistic form
1876 xorptr (tmpReg, tmpReg);
1877 } else {
1878 // Can suffer RTS->RTO upgrades on shared or cold $ lines
1879 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner
1880 testptr(tmpReg, tmpReg); // Locked ?
1881 jccb (Assembler::notZero, DONE_LABEL);
1882 }
1883
1884 // Appears unlocked - try to swing _owner from null to non-null.
1885 // Use either "Self" (in scr) or rsp as thread identity in _owner.
1886 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand.
1887 get_thread (scrReg);
1888 if (os::is_MP()) {
1889 lock();
1890 }
1891 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1892
1893 // If the CAS fails we can either retry or pass control to the slow-path.
1894 // We use the latter tactic.
1895 // Pass the CAS result in the icc.ZFlag into DONE_LABEL
1896 // If the CAS was successful ...
1897 // Self has acquired the lock
1898 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it.
1899 // Intentional fall-through into DONE_LABEL ...
1900 }
1901 #else // _LP64
1902 // It's inflated
1903 movq(scrReg, tmpReg);
1904 xorq(tmpReg, tmpReg);
1905
1906 if (os::is_MP()) {
1907 lock();
1908 }
1909 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
1910 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark().
1911 // Without cast to int32_t movptr will destroy r10 which is typically obj.
1912 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark()));
1913 // Intentional fall-through into DONE_LABEL ...
1914 // Propagate ICC.ZF from CAS above into DONE_LABEL.
1915 #endif // _LP64
1916 #if INCLUDE_RTM_OPT
1917 } // use_rtm()
1918 #endif
1919 // DONE_LABEL is a hot target - we'd really like to place it at the
1920 // start of cache line by padding with NOPs.
1921 // See the AMD and Intel software optimization manuals for the
1922 // most efficient "long" NOP encodings.
1923 // Unfortunately none of our alignment mechanisms suffice.
1924 bind(DONE_LABEL);
1925
1926 // At DONE_LABEL the icc ZFlag is set as follows ...
1927 // Fast_Unlock uses the same protocol.
1928 // ZFlag == 1 -> Success
1929 // ZFlag == 0 -> Failure - force control through the slow-path
1930 }
1931 }
1932
1933 // obj: object to unlock
1934 // box: box address (displaced header location), killed. Must be EAX.
1935 // tmp: killed, cannot be obj nor box.
1936 //
1937 // Some commentary on balanced locking:
1938 //
1939 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites.
1940 // Methods that don't have provably balanced locking are forced to run in the
1941 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock.
1942 // The interpreter provides two properties:
1943 // I1: At return-time the interpreter automatically and quietly unlocks any
1944 // objects acquired the current activation (frame). Recall that the
1945 // interpreter maintains an on-stack list of locks currently held by
1946 // a frame.
1947 // I2: If a method attempts to unlock an object that is not held by the
1948 // the frame the interpreter throws IMSX.
1949 //
1950 // Lets say A(), which has provably balanced locking, acquires O and then calls B().
1951 // B() doesn't have provably balanced locking so it runs in the interpreter.
1952 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O
1953 // is still locked by A().
1954 //
1955 // The only other source of unbalanced locking would be JNI. The "Java Native Interface:
1956 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter
1957 // should not be unlocked by "normal" java-level locking and vice-versa. The specification
1958 // doesn't specify what will occur if a program engages in such mixed-mode locking, however.
1959 // Arguably given that the spec legislates the JNI case as undefined our implementation
1960 // could reasonably *avoid* checking owner in Fast_Unlock().
1961 // In the interest of performance we elide m->Owner==Self check in unlock.
1962 // A perfectly viable alternative is to elide the owner check except when
1963 // Xcheck:jni is enabled.
1964
1965 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) {
1966 assert(boxReg == rax, "");
1967 assert_different_registers(objReg, boxReg, tmpReg);
1968
1969 if (EmitSync & 4) {
1970 // Disable - inhibit all inlining. Force control through the slow-path
1971 cmpptr (rsp, 0);
1972 } else {
1973 Label DONE_LABEL, Stacked, CheckSucc;
1974
1975 // Critically, the biased locking test must have precedence over
1976 // and appear before the (box->dhw == 0) recursive stack-lock test.
1977 if (UseBiasedLocking && !UseOptoBiasInlining) {
1978 biased_locking_exit(objReg, tmpReg, DONE_LABEL);
1979 }
1980
1981 #if INCLUDE_RTM_OPT
1982 if (UseRTMForStackLocks && use_rtm) {
1983 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking");
1984 Label L_regular_unlock;
1985 movptr(tmpReg, Address(objReg, 0)); // fetch markword
1986 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits
1987 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked
1988 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock
1989 xend(); // otherwise end...
1990 jmp(DONE_LABEL); // ... and we're done
1991 bind(L_regular_unlock);
1992 }
1993 #endif
1994
1995 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header
1996 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock
1997 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword
1998 testptr(tmpReg, markOopDesc::monitor_value); // Inflated?
1999 jccb (Assembler::zero, Stacked);
2000
2001 // It's inflated.
2002 #if INCLUDE_RTM_OPT
2003 if (use_rtm) {
2004 Label L_regular_inflated_unlock;
2005 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner);
2006 movptr(boxReg, Address(tmpReg, owner_offset));
2007 testptr(boxReg, boxReg);
2008 jccb(Assembler::notZero, L_regular_inflated_unlock);
2009 xend();
2010 jmpb(DONE_LABEL);
2011 bind(L_regular_inflated_unlock);
2012 }
2013 #endif
2014
2015 // Despite our balanced locking property we still check that m->_owner == Self
2016 // as java routines or native JNI code called by this thread might
2017 // have released the lock.
2018 // Refer to the comments in synchronizer.cpp for how we might encode extra
2019 // state in _succ so we can avoid fetching EntryList|cxq.
2020 //
2021 // I'd like to add more cases in fast_lock() and fast_unlock() --
2022 // such as recursive enter and exit -- but we have to be wary of
2023 // I$ bloat, T$ effects and BP$ effects.
2024 //
2025 // If there's no contention try a 1-0 exit. That is, exit without
2026 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how
2027 // we detect and recover from the race that the 1-0 exit admits.
2028 //
2029 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier
2030 // before it STs null into _owner, releasing the lock. Updates
2031 // to data protected by the critical section must be visible before
2032 // we drop the lock (and thus before any other thread could acquire
2033 // the lock and observe the fields protected by the lock).
2034 // IA32's memory-model is SPO, so STs are ordered with respect to
2035 // each other and there's no need for an explicit barrier (fence).
2036 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html.
2037 #ifndef _LP64
2038 get_thread (boxReg);
2039 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) {
2040 // prefetchw [ebx + Offset(_owner)-2]
2041 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2042 }
2043
2044 // Note that we could employ various encoding schemes to reduce
2045 // the number of loads below (currently 4) to just 2 or 3.
2046 // Refer to the comments in synchronizer.cpp.
2047 // In practice the chain of fetches doesn't seem to impact performance, however.
2048 xorptr(boxReg, boxReg);
2049 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) {
2050 // Attempt to reduce branch density - AMD's branch predictor.
2051 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2052 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2054 jccb (Assembler::notZero, DONE_LABEL);
2055 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2056 jmpb (DONE_LABEL);
2057 } else {
2058 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2059 jccb (Assembler::notZero, DONE_LABEL);
2060 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2061 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2062 jccb (Assembler::notZero, CheckSucc);
2063 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2064 jmpb (DONE_LABEL);
2065 }
2066
2067 // The Following code fragment (EmitSync & 65536) improves the performance of
2068 // contended applications and contended synchronization microbenchmarks.
2069 // Unfortunately the emission of the code - even though not executed - causes regressions
2070 // in scimark and jetstream, evidently because of $ effects. Replacing the code
2071 // with an equal number of never-executed NOPs results in the same regression.
2072 // We leave it off by default.
2073
2074 if ((EmitSync & 65536) != 0) {
2075 Label LSuccess, LGoSlowPath ;
2076
2077 bind (CheckSucc);
2078
2079 // Optional pre-test ... it's safe to elide this
2080 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2081 jccb(Assembler::zero, LGoSlowPath);
2082
2083 // We have a classic Dekker-style idiom:
2084 // ST m->_owner = 0 ; MEMBAR; LD m->_succ
2085 // There are a number of ways to implement the barrier:
2086 // (1) lock:andl &m->_owner, 0
2087 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form.
2088 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0
2089 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8
2090 // (2) If supported, an explicit MFENCE is appealing.
2091 // In older IA32 processors MFENCE is slower than lock:add or xchg
2092 // particularly if the write-buffer is full as might be the case if
2093 // if stores closely precede the fence or fence-equivalent instruction.
2094 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2095 // as the situation has changed with Nehalem and Shanghai.
2096 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack
2097 // The $lines underlying the top-of-stack should be in M-state.
2098 // The locked add instruction is serializing, of course.
2099 // (4) Use xchg, which is serializing
2100 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works
2101 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0.
2102 // The integer condition codes will tell us if succ was 0.
2103 // Since _succ and _owner should reside in the same $line and
2104 // we just stored into _owner, it's likely that the $line
2105 // remains in M-state for the lock:orl.
2106 //
2107 // We currently use (3), although it's likely that switching to (2)
2108 // is correct for the future.
2109
2110 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD);
2111 if (os::is_MP()) {
2112 lock(); addptr(Address(rsp, 0), 0);
2113 }
2114 // Ratify _succ remains non-null
2115 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0);
2116 jccb (Assembler::notZero, LSuccess);
2117
2118 xorptr(boxReg, boxReg); // box is really EAX
2119 if (os::is_MP()) { lock(); }
2120 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2121 // There's no successor so we tried to regrab the lock with the
2122 // placeholder value. If that didn't work, then another thread
2123 // grabbed the lock so we're done (and exit was a success).
2124 jccb (Assembler::notEqual, LSuccess);
2125 // Since we're low on registers we installed rsp as a placeholding in _owner.
2126 // Now install Self over rsp. This is safe as we're transitioning from
2127 // non-null to non=null
2128 get_thread (boxReg);
2129 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg);
2130 // Intentional fall-through into LGoSlowPath ...
2131
2132 bind (LGoSlowPath);
2133 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure
2134 jmpb (DONE_LABEL);
2135
2136 bind (LSuccess);
2137 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success
2138 jmpb (DONE_LABEL);
2139 }
2140
2141 bind (Stacked);
2142 // It's not inflated and it's not recursively stack-locked and it's not biased.
2143 // It must be stack-locked.
2144 // Try to reset the header to displaced header.
2145 // The "box" value on the stack is stable, so we can reload
2146 // and be assured we observe the same value as above.
2147 movptr(tmpReg, Address(boxReg, 0));
2148 if (os::is_MP()) {
2149 lock();
2150 }
2151 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2152 // Intention fall-thru into DONE_LABEL
2153
2154 // DONE_LABEL is a hot target - we'd really like to place it at the
2155 // start of cache line by padding with NOPs.
2156 // See the AMD and Intel software optimization manuals for the
2157 // most efficient "long" NOP encodings.
2158 // Unfortunately none of our alignment mechanisms suffice.
2159 if ((EmitSync & 65536) == 0) {
2160 bind (CheckSucc);
2161 }
2162 #else // _LP64
2163 // It's inflated
2164 if (EmitSync & 1024) {
2165 // Emit code to check that _owner == Self
2166 // We could fold the _owner test into subsequent code more efficiently
2167 // than using a stand-alone check, but since _owner checking is off by
2168 // default we don't bother. We also might consider predicating the
2169 // _owner==Self check on Xcheck:jni or running on a debug build.
2170 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2171 xorptr(boxReg, r15_thread);
2172 } else {
2173 xorptr(boxReg, boxReg);
2174 }
2175 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
2176 jccb (Assembler::notZero, DONE_LABEL);
2177 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
2178 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
2179 jccb (Assembler::notZero, CheckSucc);
2180 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2181 jmpb (DONE_LABEL);
2182
2183 if ((EmitSync & 65536) == 0) {
2184 // Try to avoid passing control into the slow_path ...
2185 Label LSuccess, LGoSlowPath ;
2186 bind (CheckSucc);
2187
2188 // The following optional optimization can be elided if necessary
2189 // Effectively: if (succ == null) goto SlowPath
2190 // The code reduces the window for a race, however,
2191 // and thus benefits performance.
2192 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2193 jccb (Assembler::zero, LGoSlowPath);
2194
2195 xorptr(boxReg, boxReg);
2196 if ((EmitSync & 16) && os::is_MP()) {
2197 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2198 } else {
2199 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD);
2200 if (os::is_MP()) {
2201 // Memory barrier/fence
2202 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ
2203 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack.
2204 // This is faster on Nehalem and AMD Shanghai/Barcelona.
2205 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences
2206 // We might also restructure (ST Owner=0;barrier;LD _Succ) to
2207 // (mov box,0; xchgq box, &m->Owner; LD _succ) .
2208 lock(); addl(Address(rsp, 0), 0);
2209 }
2210 }
2211 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD);
2212 jccb (Assembler::notZero, LSuccess);
2213
2214 // Rare inopportune interleaving - race.
2215 // The successor vanished in the small window above.
2216 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor.
2217 // We need to ensure progress and succession.
2218 // Try to reacquire the lock.
2219 // If that fails then the new owner is responsible for succession and this
2220 // thread needs to take no further action and can exit via the fast path (success).
2221 // If the re-acquire succeeds then pass control into the slow path.
2222 // As implemented, this latter mode is horrible because we generated more
2223 // coherence traffic on the lock *and* artifically extended the critical section
2224 // length while by virtue of passing control into the slow path.
2225
2226 // box is really RAX -- the following CMPXCHG depends on that binding
2227 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R)
2228 if (os::is_MP()) { lock(); }
2229 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
2230 // There's no successor so we tried to regrab the lock.
2231 // If that didn't work, then another thread grabbed the
2232 // lock so we're done (and exit was a success).
2233 jccb (Assembler::notEqual, LSuccess);
2234 // Intentional fall-through into slow-path
2235
2236 bind (LGoSlowPath);
2237 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure
2238 jmpb (DONE_LABEL);
2239
2240 bind (LSuccess);
2241 testl (boxReg, 0); // set ICC.ZF=1 to indicate success
2242 jmpb (DONE_LABEL);
2243 }
2244
2245 bind (Stacked);
2246 movptr(tmpReg, Address (boxReg, 0)); // re-fetch
2247 if (os::is_MP()) { lock(); }
2248 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box
2249
2250 if (EmitSync & 65536) {
2251 bind (CheckSucc);
2252 }
2253 #endif
2254 bind(DONE_LABEL);
2255 }
2256 }
2257 #endif // COMPILER2
2258
2259 void MacroAssembler::c2bool(Register x) {
2260 // implements x == 0 ? 0 : 1
2261 // note: must only look at least-significant byte of x
2262 // since C-style booleans are stored in one byte
2263 // only! (was bug)
2264 andl(x, 0xFF);
2265 setb(Assembler::notZero, x);
2266 }
2267
2268 // Wouldn't need if AddressLiteral version had new name
2269 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
2270 Assembler::call(L, rtype);
2271 }
2272
2273 void MacroAssembler::call(Register entry) {
2274 Assembler::call(entry);
2275 }
2276
2277 void MacroAssembler::call(AddressLiteral entry) {
2278 if (reachable(entry)) {
2279 Assembler::call_literal(entry.target(), entry.rspec());
2280 } else {
2281 lea(rscratch1, entry);
2282 Assembler::call(rscratch1);
2283 }
2284 }
2285
2286 void MacroAssembler::ic_call(address entry, jint method_index) {
2287 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
2288 movptr(rax, (intptr_t)Universe::non_oop_word());
2289 call(AddressLiteral(entry, rh));
2290 }
2291
2292 // Implementation of call_VM versions
2293
2294 void MacroAssembler::call_VM(Register oop_result,
2295 address entry_point,
2296 bool check_exceptions) {
2297 Label C, E;
2298 call(C, relocInfo::none);
2299 jmp(E);
2300
2301 bind(C);
2302 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
2303 ret(0);
2304
2305 bind(E);
2306 }
2307
2308 void MacroAssembler::call_VM(Register oop_result,
2309 address entry_point,
2310 Register arg_1,
2311 bool check_exceptions) {
2312 Label C, E;
2313 call(C, relocInfo::none);
2314 jmp(E);
2315
2316 bind(C);
2317 pass_arg1(this, arg_1);
2318 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
2319 ret(0);
2320
2321 bind(E);
2322 }
2323
2324 void MacroAssembler::call_VM(Register oop_result,
2325 address entry_point,
2326 Register arg_1,
2327 Register arg_2,
2328 bool check_exceptions) {
2329 Label C, E;
2330 call(C, relocInfo::none);
2331 jmp(E);
2332
2333 bind(C);
2334
2335 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2336
2337 pass_arg2(this, arg_2);
2338 pass_arg1(this, arg_1);
2339 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
2340 ret(0);
2341
2342 bind(E);
2343 }
2344
2345 void MacroAssembler::call_VM(Register oop_result,
2346 address entry_point,
2347 Register arg_1,
2348 Register arg_2,
2349 Register arg_3,
2350 bool check_exceptions) {
2351 Label C, E;
2352 call(C, relocInfo::none);
2353 jmp(E);
2354
2355 bind(C);
2356
2357 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2358 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2359 pass_arg3(this, arg_3);
2360
2361 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2362 pass_arg2(this, arg_2);
2363
2364 pass_arg1(this, arg_1);
2365 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
2366 ret(0);
2367
2368 bind(E);
2369 }
2370
2371 void MacroAssembler::call_VM(Register oop_result,
2372 Register last_java_sp,
2373 address entry_point,
2374 int number_of_arguments,
2375 bool check_exceptions) {
2376 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2377 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2378 }
2379
2380 void MacroAssembler::call_VM(Register oop_result,
2381 Register last_java_sp,
2382 address entry_point,
2383 Register arg_1,
2384 bool check_exceptions) {
2385 pass_arg1(this, arg_1);
2386 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2387 }
2388
2389 void MacroAssembler::call_VM(Register oop_result,
2390 Register last_java_sp,
2391 address entry_point,
2392 Register arg_1,
2393 Register arg_2,
2394 bool check_exceptions) {
2395
2396 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2397 pass_arg2(this, arg_2);
2398 pass_arg1(this, arg_1);
2399 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2400 }
2401
2402 void MacroAssembler::call_VM(Register oop_result,
2403 Register last_java_sp,
2404 address entry_point,
2405 Register arg_1,
2406 Register arg_2,
2407 Register arg_3,
2408 bool check_exceptions) {
2409 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2410 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2411 pass_arg3(this, arg_3);
2412 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2413 pass_arg2(this, arg_2);
2414 pass_arg1(this, arg_1);
2415 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2416 }
2417
2418 void MacroAssembler::super_call_VM(Register oop_result,
2419 Register last_java_sp,
2420 address entry_point,
2421 int number_of_arguments,
2422 bool check_exceptions) {
2423 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
2424 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
2425 }
2426
2427 void MacroAssembler::super_call_VM(Register oop_result,
2428 Register last_java_sp,
2429 address entry_point,
2430 Register arg_1,
2431 bool check_exceptions) {
2432 pass_arg1(this, arg_1);
2433 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
2434 }
2435
2436 void MacroAssembler::super_call_VM(Register oop_result,
2437 Register last_java_sp,
2438 address entry_point,
2439 Register arg_1,
2440 Register arg_2,
2441 bool check_exceptions) {
2442
2443 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2444 pass_arg2(this, arg_2);
2445 pass_arg1(this, arg_1);
2446 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
2447 }
2448
2449 void MacroAssembler::super_call_VM(Register oop_result,
2450 Register last_java_sp,
2451 address entry_point,
2452 Register arg_1,
2453 Register arg_2,
2454 Register arg_3,
2455 bool check_exceptions) {
2456 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2457 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2458 pass_arg3(this, arg_3);
2459 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2460 pass_arg2(this, arg_2);
2461 pass_arg1(this, arg_1);
2462 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
2463 }
2464
2465 void MacroAssembler::call_VM_base(Register oop_result,
2466 Register java_thread,
2467 Register last_java_sp,
2468 address entry_point,
2469 int number_of_arguments,
2470 bool check_exceptions) {
2471 // determine java_thread register
2472 if (!java_thread->is_valid()) {
2473 #ifdef _LP64
2474 java_thread = r15_thread;
2475 #else
2476 java_thread = rdi;
2477 get_thread(java_thread);
2478 #endif // LP64
2479 }
2480 // determine last_java_sp register
2481 if (!last_java_sp->is_valid()) {
2482 last_java_sp = rsp;
2483 }
2484 // debugging support
2485 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
2486 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
2487 #ifdef ASSERT
2488 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
2489 // r12 is the heapbase.
2490 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
2491 #endif // ASSERT
2492
2493 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
2494 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
2495
2496 // push java thread (becomes first argument of C function)
2497
2498 NOT_LP64(push(java_thread); number_of_arguments++);
2499 LP64_ONLY(mov(c_rarg0, r15_thread));
2500
2501 // set last Java frame before call
2502 assert(last_java_sp != rbp, "can't use ebp/rbp");
2503
2504 // Only interpreter should have to set fp
2505 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
2506
2507 // do the call, remove parameters
2508 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
2509
2510 // restore the thread (cannot use the pushed argument since arguments
2511 // may be overwritten by C code generated by an optimizing compiler);
2512 // however can use the register value directly if it is callee saved.
2513 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
2514 // rdi & rsi (also r15) are callee saved -> nothing to do
2515 #ifdef ASSERT
2516 guarantee(java_thread != rax, "change this code");
2517 push(rax);
2518 { Label L;
2519 get_thread(rax);
2520 cmpptr(java_thread, rax);
2521 jcc(Assembler::equal, L);
2522 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
2523 bind(L);
2524 }
2525 pop(rax);
2526 #endif
2527 } else {
2528 get_thread(java_thread);
2529 }
2530 // reset last Java frame
2531 // Only interpreter should have to clear fp
2532 reset_last_Java_frame(java_thread, true);
2533
2534 // C++ interp handles this in the interpreter
2535 check_and_handle_popframe(java_thread);
2536 check_and_handle_earlyret(java_thread);
2537
2538 if (check_exceptions) {
2539 // check for pending exceptions (java_thread is set upon return)
2540 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
2541 #ifndef _LP64
2542 jump_cc(Assembler::notEqual,
2543 RuntimeAddress(StubRoutines::forward_exception_entry()));
2544 #else
2545 // This used to conditionally jump to forward_exception however it is
2546 // possible if we relocate that the branch will not reach. So we must jump
2547 // around so we can always reach
2548
2549 Label ok;
2550 jcc(Assembler::equal, ok);
2551 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2552 bind(ok);
2553 #endif // LP64
2554 }
2555
2556 // get oop result if there is one and reset the value in the thread
2557 if (oop_result->is_valid()) {
2558 get_vm_result(oop_result, java_thread);
2559 }
2560 }
2561
2562 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
2563
2564 // Calculate the value for last_Java_sp
2565 // somewhat subtle. call_VM does an intermediate call
2566 // which places a return address on the stack just under the
2567 // stack pointer as the user finsihed with it. This allows
2568 // use to retrieve last_Java_pc from last_Java_sp[-1].
2569 // On 32bit we then have to push additional args on the stack to accomplish
2570 // the actual requested call. On 64bit call_VM only can use register args
2571 // so the only extra space is the return address that call_VM created.
2572 // This hopefully explains the calculations here.
2573
2574 #ifdef _LP64
2575 // We've pushed one address, correct last_Java_sp
2576 lea(rax, Address(rsp, wordSize));
2577 #else
2578 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
2579 #endif // LP64
2580
2581 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
2582
2583 }
2584
2585 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
2586 void MacroAssembler::call_VM_leaf0(address entry_point) {
2587 MacroAssembler::call_VM_leaf_base(entry_point, 0);
2588 }
2589
2590 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2591 call_VM_leaf_base(entry_point, number_of_arguments);
2592 }
2593
2594 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2595 pass_arg0(this, arg_0);
2596 call_VM_leaf(entry_point, 1);
2597 }
2598
2599 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2600
2601 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2602 pass_arg1(this, arg_1);
2603 pass_arg0(this, arg_0);
2604 call_VM_leaf(entry_point, 2);
2605 }
2606
2607 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2608 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2609 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2610 pass_arg2(this, arg_2);
2611 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2612 pass_arg1(this, arg_1);
2613 pass_arg0(this, arg_0);
2614 call_VM_leaf(entry_point, 3);
2615 }
2616
2617 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2618 pass_arg0(this, arg_0);
2619 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2620 }
2621
2622 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2623
2624 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2625 pass_arg1(this, arg_1);
2626 pass_arg0(this, arg_0);
2627 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2628 }
2629
2630 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2631 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2632 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2633 pass_arg2(this, arg_2);
2634 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2635 pass_arg1(this, arg_1);
2636 pass_arg0(this, arg_0);
2637 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2638 }
2639
2640 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2641 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
2642 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
2643 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
2644 pass_arg3(this, arg_3);
2645 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
2646 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
2647 pass_arg2(this, arg_2);
2648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
2649 pass_arg1(this, arg_1);
2650 pass_arg0(this, arg_0);
2651 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2652 }
2653
2654 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
2655 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
2656 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
2657 verify_oop(oop_result, "broken oop in call_VM_base");
2658 }
2659
2660 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
2661 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
2662 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
2663 }
2664
2665 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2666 }
2667
2668 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2669 }
2670
2671 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
2672 if (reachable(src1)) {
2673 cmpl(as_Address(src1), imm);
2674 } else {
2675 lea(rscratch1, src1);
2676 cmpl(Address(rscratch1, 0), imm);
2677 }
2678 }
2679
2680 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
2681 assert(!src2.is_lval(), "use cmpptr");
2682 if (reachable(src2)) {
2683 cmpl(src1, as_Address(src2));
2684 } else {
2685 lea(rscratch1, src2);
2686 cmpl(src1, Address(rscratch1, 0));
2687 }
2688 }
2689
2690 void MacroAssembler::cmp32(Register src1, int32_t imm) {
2691 Assembler::cmpl(src1, imm);
2692 }
2693
2694 void MacroAssembler::cmp32(Register src1, Address src2) {
2695 Assembler::cmpl(src1, src2);
2696 }
2697
2698 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2699 ucomisd(opr1, opr2);
2700
2701 Label L;
2702 if (unordered_is_less) {
2703 movl(dst, -1);
2704 jcc(Assembler::parity, L);
2705 jcc(Assembler::below , L);
2706 movl(dst, 0);
2707 jcc(Assembler::equal , L);
2708 increment(dst);
2709 } else { // unordered is greater
2710 movl(dst, 1);
2711 jcc(Assembler::parity, L);
2712 jcc(Assembler::above , L);
2713 movl(dst, 0);
2714 jcc(Assembler::equal , L);
2715 decrementl(dst);
2716 }
2717 bind(L);
2718 }
2719
2720 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
2721 ucomiss(opr1, opr2);
2722
2723 Label L;
2724 if (unordered_is_less) {
2725 movl(dst, -1);
2726 jcc(Assembler::parity, L);
2727 jcc(Assembler::below , L);
2728 movl(dst, 0);
2729 jcc(Assembler::equal , L);
2730 increment(dst);
2731 } else { // unordered is greater
2732 movl(dst, 1);
2733 jcc(Assembler::parity, L);
2734 jcc(Assembler::above , L);
2735 movl(dst, 0);
2736 jcc(Assembler::equal , L);
2737 decrementl(dst);
2738 }
2739 bind(L);
2740 }
2741
2742
2743 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
2744 if (reachable(src1)) {
2745 cmpb(as_Address(src1), imm);
2746 } else {
2747 lea(rscratch1, src1);
2748 cmpb(Address(rscratch1, 0), imm);
2749 }
2750 }
2751
2752 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
2753 #ifdef _LP64
2754 if (src2.is_lval()) {
2755 movptr(rscratch1, src2);
2756 Assembler::cmpq(src1, rscratch1);
2757 } else if (reachable(src2)) {
2758 cmpq(src1, as_Address(src2));
2759 } else {
2760 lea(rscratch1, src2);
2761 Assembler::cmpq(src1, Address(rscratch1, 0));
2762 }
2763 #else
2764 if (src2.is_lval()) {
2765 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2766 } else {
2767 cmpl(src1, as_Address(src2));
2768 }
2769 #endif // _LP64
2770 }
2771
2772 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
2773 assert(src2.is_lval(), "not a mem-mem compare");
2774 #ifdef _LP64
2775 // moves src2's literal address
2776 movptr(rscratch1, src2);
2777 Assembler::cmpq(src1, rscratch1);
2778 #else
2779 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
2780 #endif // _LP64
2781 }
2782
2783 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
2784 if (reachable(adr)) {
2785 if (os::is_MP())
2786 lock();
2787 cmpxchgptr(reg, as_Address(adr));
2788 } else {
2789 lea(rscratch1, adr);
2790 if (os::is_MP())
2791 lock();
2792 cmpxchgptr(reg, Address(rscratch1, 0));
2793 }
2794 }
2795
2796 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
2797 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
2798 }
2799
2800 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
2801 if (reachable(src)) {
2802 Assembler::comisd(dst, as_Address(src));
2803 } else {
2804 lea(rscratch1, src);
2805 Assembler::comisd(dst, Address(rscratch1, 0));
2806 }
2807 }
2808
2809 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
2810 if (reachable(src)) {
2811 Assembler::comiss(dst, as_Address(src));
2812 } else {
2813 lea(rscratch1, src);
2814 Assembler::comiss(dst, Address(rscratch1, 0));
2815 }
2816 }
2817
2818
2819 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
2820 Condition negated_cond = negate_condition(cond);
2821 Label L;
2822 jcc(negated_cond, L);
2823 pushf(); // Preserve flags
2824 atomic_incl(counter_addr);
2825 popf();
2826 bind(L);
2827 }
2828
2829 int MacroAssembler::corrected_idivl(Register reg) {
2830 // Full implementation of Java idiv and irem; checks for
2831 // special case as described in JVM spec., p.243 & p.271.
2832 // The function returns the (pc) offset of the idivl
2833 // instruction - may be needed for implicit exceptions.
2834 //
2835 // normal case special case
2836 //
2837 // input : rax,: dividend min_int
2838 // reg: divisor (may not be rax,/rdx) -1
2839 //
2840 // output: rax,: quotient (= rax, idiv reg) min_int
2841 // rdx: remainder (= rax, irem reg) 0
2842 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
2843 const int min_int = 0x80000000;
2844 Label normal_case, special_case;
2845
2846 // check for special case
2847 cmpl(rax, min_int);
2848 jcc(Assembler::notEqual, normal_case);
2849 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
2850 cmpl(reg, -1);
2851 jcc(Assembler::equal, special_case);
2852
2853 // handle normal case
2854 bind(normal_case);
2855 cdql();
2856 int idivl_offset = offset();
2857 idivl(reg);
2858
2859 // normal and special case exit
2860 bind(special_case);
2861
2862 return idivl_offset;
2863 }
2864
2865
2866
2867 void MacroAssembler::decrementl(Register reg, int value) {
2868 if (value == min_jint) {subl(reg, value) ; return; }
2869 if (value < 0) { incrementl(reg, -value); return; }
2870 if (value == 0) { ; return; }
2871 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2872 /* else */ { subl(reg, value) ; return; }
2873 }
2874
2875 void MacroAssembler::decrementl(Address dst, int value) {
2876 if (value == min_jint) {subl(dst, value) ; return; }
2877 if (value < 0) { incrementl(dst, -value); return; }
2878 if (value == 0) { ; return; }
2879 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2880 /* else */ { subl(dst, value) ; return; }
2881 }
2882
2883 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2884 assert (shift_value > 0, "illegal shift value");
2885 Label _is_positive;
2886 testl (reg, reg);
2887 jcc (Assembler::positive, _is_positive);
2888 int offset = (1 << shift_value) - 1 ;
2889
2890 if (offset == 1) {
2891 incrementl(reg);
2892 } else {
2893 addl(reg, offset);
2894 }
2895
2896 bind (_is_positive);
2897 sarl(reg, shift_value);
2898 }
2899
2900 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2901 if (reachable(src)) {
2902 Assembler::divsd(dst, as_Address(src));
2903 } else {
2904 lea(rscratch1, src);
2905 Assembler::divsd(dst, Address(rscratch1, 0));
2906 }
2907 }
2908
2909 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2910 if (reachable(src)) {
2911 Assembler::divss(dst, as_Address(src));
2912 } else {
2913 lea(rscratch1, src);
2914 Assembler::divss(dst, Address(rscratch1, 0));
2915 }
2916 }
2917
2918 // !defined(COMPILER2) is because of stupid core builds
2919 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI
2920 void MacroAssembler::empty_FPU_stack() {
2921 if (VM_Version::supports_mmx()) {
2922 emms();
2923 } else {
2924 for (int i = 8; i-- > 0; ) ffree(i);
2925 }
2926 }
2927 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI
2928
2929
2930 // Defines obj, preserves var_size_in_bytes
2931 void MacroAssembler::eden_allocate(Register obj,
2932 Register var_size_in_bytes,
2933 int con_size_in_bytes,
2934 Register t1,
2935 Label& slow_case) {
2936 assert(obj == rax, "obj must be in rax, for cmpxchg");
2937 assert_different_registers(obj, var_size_in_bytes, t1);
2938 if (!Universe::heap()->supports_inline_contig_alloc()) {
2939 jmp(slow_case);
2940 } else {
2941 Register end = t1;
2942 Label retry;
2943 bind(retry);
2944 ExternalAddress heap_top((address) Universe::heap()->top_addr());
2945 movptr(obj, heap_top);
2946 if (var_size_in_bytes == noreg) {
2947 lea(end, Address(obj, con_size_in_bytes));
2948 } else {
2949 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
2950 }
2951 // if end < obj then we wrapped around => object too long => slow case
2952 cmpptr(end, obj);
2953 jcc(Assembler::below, slow_case);
2954 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr()));
2955 jcc(Assembler::above, slow_case);
2956 // Compare obj with the top addr, and if still equal, store the new top addr in
2957 // end at the address of the top addr pointer. Sets ZF if was equal, and clears
2958 // it otherwise. Use lock prefix for atomicity on MPs.
2959 locked_cmpxchgptr(end, heap_top);
2960 jcc(Assembler::notEqual, retry);
2961 }
2962 }
2963
2964 void MacroAssembler::enter() {
2965 push(rbp);
2966 mov(rbp, rsp);
2967 }
2968
2969 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2970 void MacroAssembler::fat_nop() {
2971 if (UseAddressNop) {
2972 addr_nop_5();
2973 } else {
2974 emit_int8(0x26); // es:
2975 emit_int8(0x2e); // cs:
2976 emit_int8(0x64); // fs:
2977 emit_int8(0x65); // gs:
2978 emit_int8((unsigned char)0x90);
2979 }
2980 }
2981
2982 void MacroAssembler::fcmp(Register tmp) {
2983 fcmp(tmp, 1, true, true);
2984 }
2985
2986 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2987 assert(!pop_right || pop_left, "usage error");
2988 if (VM_Version::supports_cmov()) {
2989 assert(tmp == noreg, "unneeded temp");
2990 if (pop_left) {
2991 fucomip(index);
2992 } else {
2993 fucomi(index);
2994 }
2995 if (pop_right) {
2996 fpop();
2997 }
2998 } else {
2999 assert(tmp != noreg, "need temp");
3000 if (pop_left) {
3001 if (pop_right) {
3002 fcompp();
3003 } else {
3004 fcomp(index);
3005 }
3006 } else {
3007 fcom(index);
3008 }
3009 // convert FPU condition into eflags condition via rax,
3010 save_rax(tmp);
3011 fwait(); fnstsw_ax();
3012 sahf();
3013 restore_rax(tmp);
3014 }
3015 // condition codes set as follows:
3016 //
3017 // CF (corresponds to C0) if x < y
3018 // PF (corresponds to C2) if unordered
3019 // ZF (corresponds to C3) if x = y
3020 }
3021
3022 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
3023 fcmp2int(dst, unordered_is_less, 1, true, true);
3024 }
3025
3026 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
3027 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
3028 Label L;
3029 if (unordered_is_less) {
3030 movl(dst, -1);
3031 jcc(Assembler::parity, L);
3032 jcc(Assembler::below , L);
3033 movl(dst, 0);
3034 jcc(Assembler::equal , L);
3035 increment(dst);
3036 } else { // unordered is greater
3037 movl(dst, 1);
3038 jcc(Assembler::parity, L);
3039 jcc(Assembler::above , L);
3040 movl(dst, 0);
3041 jcc(Assembler::equal , L);
3042 decrementl(dst);
3043 }
3044 bind(L);
3045 }
3046
3047 void MacroAssembler::fld_d(AddressLiteral src) {
3048 fld_d(as_Address(src));
3049 }
3050
3051 void MacroAssembler::fld_s(AddressLiteral src) {
3052 fld_s(as_Address(src));
3053 }
3054
3055 void MacroAssembler::fld_x(AddressLiteral src) {
3056 Assembler::fld_x(as_Address(src));
3057 }
3058
3059 void MacroAssembler::fldcw(AddressLiteral src) {
3060 Assembler::fldcw(as_Address(src));
3061 }
3062
3063 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
3064 if (reachable(src)) {
3065 Assembler::mulpd(dst, as_Address(src));
3066 } else {
3067 lea(rscratch1, src);
3068 Assembler::mulpd(dst, Address(rscratch1, 0));
3069 }
3070 }
3071
3072 void MacroAssembler::increase_precision() {
3073 subptr(rsp, BytesPerWord);
3074 fnstcw(Address(rsp, 0));
3075 movl(rax, Address(rsp, 0));
3076 orl(rax, 0x300);
3077 push(rax);
3078 fldcw(Address(rsp, 0));
3079 pop(rax);
3080 }
3081
3082 void MacroAssembler::restore_precision() {
3083 fldcw(Address(rsp, 0));
3084 addptr(rsp, BytesPerWord);
3085 }
3086
3087 void MacroAssembler::fpop() {
3088 ffree();
3089 fincstp();
3090 }
3091
3092 void MacroAssembler::load_float(Address src) {
3093 if (UseSSE >= 1) {
3094 movflt(xmm0, src);
3095 } else {
3096 LP64_ONLY(ShouldNotReachHere());
3097 NOT_LP64(fld_s(src));
3098 }
3099 }
3100
3101 void MacroAssembler::store_float(Address dst) {
3102 if (UseSSE >= 1) {
3103 movflt(dst, xmm0);
3104 } else {
3105 LP64_ONLY(ShouldNotReachHere());
3106 NOT_LP64(fstp_s(dst));
3107 }
3108 }
3109
3110 void MacroAssembler::load_double(Address src) {
3111 if (UseSSE >= 2) {
3112 movdbl(xmm0, src);
3113 } else {
3114 LP64_ONLY(ShouldNotReachHere());
3115 NOT_LP64(fld_d(src));
3116 }
3117 }
3118
3119 void MacroAssembler::store_double(Address dst) {
3120 if (UseSSE >= 2) {
3121 movdbl(dst, xmm0);
3122 } else {
3123 LP64_ONLY(ShouldNotReachHere());
3124 NOT_LP64(fstp_d(dst));
3125 }
3126 }
3127
3128 void MacroAssembler::fremr(Register tmp) {
3129 save_rax(tmp);
3130 { Label L;
3131 bind(L);
3132 fprem();
3133 fwait(); fnstsw_ax();
3134 #ifdef _LP64
3135 testl(rax, 0x400);
3136 jcc(Assembler::notEqual, L);
3137 #else
3138 sahf();
3139 jcc(Assembler::parity, L);
3140 #endif // _LP64
3141 }
3142 restore_rax(tmp);
3143 // Result is in ST0.
3144 // Note: fxch & fpop to get rid of ST1
3145 // (otherwise FPU stack could overflow eventually)
3146 fxch(1);
3147 fpop();
3148 }
3149
3150 // dst = c = a * b + c
3151 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3152 Assembler::vfmadd231sd(c, a, b);
3153 if (dst != c) {
3154 movdbl(dst, c);
3155 }
3156 }
3157
3158 // dst = c = a * b + c
3159 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
3160 Assembler::vfmadd231ss(c, a, b);
3161 if (dst != c) {
3162 movflt(dst, c);
3163 }
3164 }
3165
3166
3167
3168
3169 void MacroAssembler::incrementl(AddressLiteral dst) {
3170 if (reachable(dst)) {
3171 incrementl(as_Address(dst));
3172 } else {
3173 lea(rscratch1, dst);
3174 incrementl(Address(rscratch1, 0));
3175 }
3176 }
3177
3178 void MacroAssembler::incrementl(ArrayAddress dst) {
3179 incrementl(as_Address(dst));
3180 }
3181
3182 void MacroAssembler::incrementl(Register reg, int value) {
3183 if (value == min_jint) {addl(reg, value) ; return; }
3184 if (value < 0) { decrementl(reg, -value); return; }
3185 if (value == 0) { ; return; }
3186 if (value == 1 && UseIncDec) { incl(reg) ; return; }
3187 /* else */ { addl(reg, value) ; return; }
3188 }
3189
3190 void MacroAssembler::incrementl(Address dst, int value) {
3191 if (value == min_jint) {addl(dst, value) ; return; }
3192 if (value < 0) { decrementl(dst, -value); return; }
3193 if (value == 0) { ; return; }
3194 if (value == 1 && UseIncDec) { incl(dst) ; return; }
3195 /* else */ { addl(dst, value) ; return; }
3196 }
3197
3198 void MacroAssembler::jump(AddressLiteral dst) {
3199 if (reachable(dst)) {
3200 jmp_literal(dst.target(), dst.rspec());
3201 } else {
3202 lea(rscratch1, dst);
3203 jmp(rscratch1);
3204 }
3205 }
3206
3207 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
3208 if (reachable(dst)) {
3209 InstructionMark im(this);
3210 relocate(dst.reloc());
3211 const int short_size = 2;
3212 const int long_size = 6;
3213 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
3214 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
3215 // 0111 tttn #8-bit disp
3216 emit_int8(0x70 | cc);
3217 emit_int8((offs - short_size) & 0xFF);
3218 } else {
3219 // 0000 1111 1000 tttn #32-bit disp
3220 emit_int8(0x0F);
3221 emit_int8((unsigned char)(0x80 | cc));
3222 emit_int32(offs - long_size);
3223 }
3224 } else {
3225 #ifdef ASSERT
3226 warning("reversing conditional branch");
3227 #endif /* ASSERT */
3228 Label skip;
3229 jccb(reverse[cc], skip);
3230 lea(rscratch1, dst);
3231 Assembler::jmp(rscratch1);
3232 bind(skip);
3233 }
3234 }
3235
3236 void MacroAssembler::ldmxcsr(AddressLiteral src) {
3237 if (reachable(src)) {
3238 Assembler::ldmxcsr(as_Address(src));
3239 } else {
3240 lea(rscratch1, src);
3241 Assembler::ldmxcsr(Address(rscratch1, 0));
3242 }
3243 }
3244
3245 int MacroAssembler::load_signed_byte(Register dst, Address src) {
3246 int off;
3247 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3248 off = offset();
3249 movsbl(dst, src); // movsxb
3250 } else {
3251 off = load_unsigned_byte(dst, src);
3252 shll(dst, 24);
3253 sarl(dst, 24);
3254 }
3255 return off;
3256 }
3257
3258 // Note: load_signed_short used to be called load_signed_word.
3259 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
3260 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
3261 // The term "word" in HotSpot means a 32- or 64-bit machine word.
3262 int MacroAssembler::load_signed_short(Register dst, Address src) {
3263 int off;
3264 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3265 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
3266 // version but this is what 64bit has always done. This seems to imply
3267 // that users are only using 32bits worth.
3268 off = offset();
3269 movswl(dst, src); // movsxw
3270 } else {
3271 off = load_unsigned_short(dst, src);
3272 shll(dst, 16);
3273 sarl(dst, 16);
3274 }
3275 return off;
3276 }
3277
3278 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
3279 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3280 // and "3.9 Partial Register Penalties", p. 22).
3281 int off;
3282 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
3283 off = offset();
3284 movzbl(dst, src); // movzxb
3285 } else {
3286 xorl(dst, dst);
3287 off = offset();
3288 movb(dst, src);
3289 }
3290 return off;
3291 }
3292
3293 // Note: load_unsigned_short used to be called load_unsigned_word.
3294 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
3295 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
3296 // and "3.9 Partial Register Penalties", p. 22).
3297 int off;
3298 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
3299 off = offset();
3300 movzwl(dst, src); // movzxw
3301 } else {
3302 xorl(dst, dst);
3303 off = offset();
3304 movw(dst, src);
3305 }
3306 return off;
3307 }
3308
3309 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
3310 switch (size_in_bytes) {
3311 #ifndef _LP64
3312 case 8:
3313 assert(dst2 != noreg, "second dest register required");
3314 movl(dst, src);
3315 movl(dst2, src.plus_disp(BytesPerInt));
3316 break;
3317 #else
3318 case 8: movq(dst, src); break;
3319 #endif
3320 case 4: movl(dst, src); break;
3321 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
3322 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
3323 default: ShouldNotReachHere();
3324 }
3325 }
3326
3327 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
3328 switch (size_in_bytes) {
3329 #ifndef _LP64
3330 case 8:
3331 assert(src2 != noreg, "second source register required");
3332 movl(dst, src);
3333 movl(dst.plus_disp(BytesPerInt), src2);
3334 break;
3335 #else
3336 case 8: movq(dst, src); break;
3337 #endif
3338 case 4: movl(dst, src); break;
3339 case 2: movw(dst, src); break;
3340 case 1: movb(dst, src); break;
3341 default: ShouldNotReachHere();
3342 }
3343 }
3344
3345 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
3346 if (reachable(dst)) {
3347 movl(as_Address(dst), src);
3348 } else {
3349 lea(rscratch1, dst);
3350 movl(Address(rscratch1, 0), src);
3351 }
3352 }
3353
3354 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
3355 if (reachable(src)) {
3356 movl(dst, as_Address(src));
3357 } else {
3358 lea(rscratch1, src);
3359 movl(dst, Address(rscratch1, 0));
3360 }
3361 }
3362
3363 // C++ bool manipulation
3364
3365 void MacroAssembler::movbool(Register dst, Address src) {
3366 if(sizeof(bool) == 1)
3367 movb(dst, src);
3368 else if(sizeof(bool) == 2)
3369 movw(dst, src);
3370 else if(sizeof(bool) == 4)
3371 movl(dst, src);
3372 else
3373 // unsupported
3374 ShouldNotReachHere();
3375 }
3376
3377 void MacroAssembler::movbool(Address dst, bool boolconst) {
3378 if(sizeof(bool) == 1)
3379 movb(dst, (int) boolconst);
3380 else if(sizeof(bool) == 2)
3381 movw(dst, (int) boolconst);
3382 else if(sizeof(bool) == 4)
3383 movl(dst, (int) boolconst);
3384 else
3385 // unsupported
3386 ShouldNotReachHere();
3387 }
3388
3389 void MacroAssembler::movbool(Address dst, Register src) {
3390 if(sizeof(bool) == 1)
3391 movb(dst, src);
3392 else if(sizeof(bool) == 2)
3393 movw(dst, src);
3394 else if(sizeof(bool) == 4)
3395 movl(dst, src);
3396 else
3397 // unsupported
3398 ShouldNotReachHere();
3399 }
3400
3401 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
3402 movb(as_Address(dst), src);
3403 }
3404
3405 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
3406 if (reachable(src)) {
3407 movdl(dst, as_Address(src));
3408 } else {
3409 lea(rscratch1, src);
3410 movdl(dst, Address(rscratch1, 0));
3411 }
3412 }
3413
3414 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
3415 if (reachable(src)) {
3416 movq(dst, as_Address(src));
3417 } else {
3418 lea(rscratch1, src);
3419 movq(dst, Address(rscratch1, 0));
3420 }
3421 }
3422
3423 void MacroAssembler::setvectmask(Register dst, Register src) {
3424 Assembler::movl(dst, 1);
3425 Assembler::shlxl(dst, dst, src);
3426 Assembler::decl(dst);
3427 Assembler::kmovdl(k1, dst);
3428 Assembler::movl(dst, src);
3429 }
3430
3431 void MacroAssembler::restorevectmask() {
3432 Assembler::knotwl(k1, k0);
3433 }
3434
3435 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
3436 if (reachable(src)) {
3437 if (UseXmmLoadAndClearUpper) {
3438 movsd (dst, as_Address(src));
3439 } else {
3440 movlpd(dst, as_Address(src));
3441 }
3442 } else {
3443 lea(rscratch1, src);
3444 if (UseXmmLoadAndClearUpper) {
3445 movsd (dst, Address(rscratch1, 0));
3446 } else {
3447 movlpd(dst, Address(rscratch1, 0));
3448 }
3449 }
3450 }
3451
3452 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
3453 if (reachable(src)) {
3454 movss(dst, as_Address(src));
3455 } else {
3456 lea(rscratch1, src);
3457 movss(dst, Address(rscratch1, 0));
3458 }
3459 }
3460
3461 void MacroAssembler::movptr(Register dst, Register src) {
3462 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3463 }
3464
3465 void MacroAssembler::movptr(Register dst, Address src) {
3466 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3467 }
3468
3469 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
3470 void MacroAssembler::movptr(Register dst, intptr_t src) {
3471 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
3472 }
3473
3474 void MacroAssembler::movptr(Address dst, Register src) {
3475 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
3476 }
3477
3478 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
3479 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3480 Assembler::vextractf32x4(dst, src, 0);
3481 } else {
3482 Assembler::movdqu(dst, src);
3483 }
3484 }
3485
3486 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
3487 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3488 Assembler::vinsertf32x4(dst, dst, src, 0);
3489 } else {
3490 Assembler::movdqu(dst, src);
3491 }
3492 }
3493
3494 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
3495 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3496 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3497 } else {
3498 Assembler::movdqu(dst, src);
3499 }
3500 }
3501
3502 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
3503 if (reachable(src)) {
3504 movdqu(dst, as_Address(src));
3505 } else {
3506 lea(scratchReg, src);
3507 movdqu(dst, Address(scratchReg, 0));
3508 }
3509 }
3510
3511 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
3512 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) {
3513 vextractf64x4_low(dst, src);
3514 } else {
3515 Assembler::vmovdqu(dst, src);
3516 }
3517 }
3518
3519 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
3520 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) {
3521 vinsertf64x4_low(dst, src);
3522 } else {
3523 Assembler::vmovdqu(dst, src);
3524 }
3525 }
3526
3527 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3528 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3529 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit);
3530 }
3531 else {
3532 Assembler::vmovdqu(dst, src);
3533 }
3534 }
3535
3536 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) {
3537 if (reachable(src)) {
3538 vmovdqu(dst, as_Address(src));
3539 }
3540 else {
3541 lea(rscratch1, src);
3542 vmovdqu(dst, Address(rscratch1, 0));
3543 }
3544 }
3545
3546 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
3547 if (reachable(src)) {
3548 Assembler::movdqa(dst, as_Address(src));
3549 } else {
3550 lea(rscratch1, src);
3551 Assembler::movdqa(dst, Address(rscratch1, 0));
3552 }
3553 }
3554
3555 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
3556 if (reachable(src)) {
3557 Assembler::movsd(dst, as_Address(src));
3558 } else {
3559 lea(rscratch1, src);
3560 Assembler::movsd(dst, Address(rscratch1, 0));
3561 }
3562 }
3563
3564 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
3565 if (reachable(src)) {
3566 Assembler::movss(dst, as_Address(src));
3567 } else {
3568 lea(rscratch1, src);
3569 Assembler::movss(dst, Address(rscratch1, 0));
3570 }
3571 }
3572
3573 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
3574 if (reachable(src)) {
3575 Assembler::mulsd(dst, as_Address(src));
3576 } else {
3577 lea(rscratch1, src);
3578 Assembler::mulsd(dst, Address(rscratch1, 0));
3579 }
3580 }
3581
3582 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
3583 if (reachable(src)) {
3584 Assembler::mulss(dst, as_Address(src));
3585 } else {
3586 lea(rscratch1, src);
3587 Assembler::mulss(dst, Address(rscratch1, 0));
3588 }
3589 }
3590
3591 void MacroAssembler::null_check(Register reg, int offset) {
3592 if (needs_explicit_null_check(offset)) {
3593 // provoke OS NULL exception if reg = NULL by
3594 // accessing M[reg] w/o changing any (non-CC) registers
3595 // NOTE: cmpl is plenty here to provoke a segv
3596 cmpptr(rax, Address(reg, 0));
3597 // Note: should probably use testl(rax, Address(reg, 0));
3598 // may be shorter code (however, this version of
3599 // testl needs to be implemented first)
3600 } else {
3601 // nothing to do, (later) access of M[reg + offset]
3602 // will provoke OS NULL exception if reg = NULL
3603 }
3604 }
3605
3606 void MacroAssembler::os_breakpoint() {
3607 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3608 // (e.g., MSVC can't call ps() otherwise)
3609 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3610 }
3611
3612 #ifdef _LP64
3613 #define XSTATE_BV 0x200
3614 #endif
3615
3616 void MacroAssembler::pop_CPU_state() {
3617 pop_FPU_state();
3618 pop_IU_state();
3619 }
3620
3621 void MacroAssembler::pop_FPU_state() {
3622 #ifndef _LP64
3623 frstor(Address(rsp, 0));
3624 #else
3625 fxrstor(Address(rsp, 0));
3626 #endif
3627 addptr(rsp, FPUStateSizeInWords * wordSize);
3628 }
3629
3630 void MacroAssembler::pop_IU_state() {
3631 popa();
3632 LP64_ONLY(addq(rsp, 8));
3633 popf();
3634 }
3635
3636 // Save Integer and Float state
3637 // Warning: Stack must be 16 byte aligned (64bit)
3638 void MacroAssembler::push_CPU_state() {
3639 push_IU_state();
3640 push_FPU_state();
3641 }
3642
3643 void MacroAssembler::push_FPU_state() {
3644 subptr(rsp, FPUStateSizeInWords * wordSize);
3645 #ifndef _LP64
3646 fnsave(Address(rsp, 0));
3647 fwait();
3648 #else
3649 fxsave(Address(rsp, 0));
3650 #endif // LP64
3651 }
3652
3653 void MacroAssembler::push_IU_state() {
3654 // Push flags first because pusha kills them
3655 pushf();
3656 // Make sure rsp stays 16-byte aligned
3657 LP64_ONLY(subq(rsp, 8));
3658 pusha();
3659 }
3660
3661 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3662 if (!java_thread->is_valid()) {
3663 java_thread = rdi;
3664 get_thread(java_thread);
3665 }
3666 // we must set sp to zero to clear frame
3667 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3668 if (clear_fp) {
3669 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3670 }
3671
3672 // Always clear the pc because it could have been set by make_walkable()
3673 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3674
3675 }
3676
3677 void MacroAssembler::restore_rax(Register tmp) {
3678 if (tmp == noreg) pop(rax);
3679 else if (tmp != rax) mov(rax, tmp);
3680 }
3681
3682 void MacroAssembler::round_to(Register reg, int modulus) {
3683 addptr(reg, modulus - 1);
3684 andptr(reg, -modulus);
3685 }
3686
3687 void MacroAssembler::save_rax(Register tmp) {
3688 if (tmp == noreg) push(rax);
3689 else if (tmp != rax) mov(tmp, rax);
3690 }
3691
3692 // Write serialization page so VM thread can do a pseudo remote membar.
3693 // We use the current thread pointer to calculate a thread specific
3694 // offset to write to within the page. This minimizes bus traffic
3695 // due to cache line collision.
3696 void MacroAssembler::serialize_memory(Register thread, Register tmp) {
3697 movl(tmp, thread);
3698 shrl(tmp, os::get_serialize_page_shift_count());
3699 andl(tmp, (os::vm_page_size() - sizeof(int)));
3700
3701 Address index(noreg, tmp, Address::times_1);
3702 ExternalAddress page(os::get_memory_serialize_page());
3703
3704 // Size of store must match masking code above
3705 movl(as_Address(ArrayAddress(page, index)), tmp);
3706 }
3707
3708 // Calls to C land
3709 //
3710 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3711 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3712 // has to be reset to 0. This is required to allow proper stack traversal.
3713 void MacroAssembler::set_last_Java_frame(Register java_thread,
3714 Register last_java_sp,
3715 Register last_java_fp,
3716 address last_java_pc) {
3717 // determine java_thread register
3718 if (!java_thread->is_valid()) {
3719 java_thread = rdi;
3720 get_thread(java_thread);
3721 }
3722 // determine last_java_sp register
3723 if (!last_java_sp->is_valid()) {
3724 last_java_sp = rsp;
3725 }
3726
3727 // last_java_fp is optional
3728
3729 if (last_java_fp->is_valid()) {
3730 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3731 }
3732
3733 // last_java_pc is optional
3734
3735 if (last_java_pc != NULL) {
3736 lea(Address(java_thread,
3737 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3738 InternalAddress(last_java_pc));
3739
3740 }
3741 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3742 }
3743
3744 void MacroAssembler::shlptr(Register dst, int imm8) {
3745 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3746 }
3747
3748 void MacroAssembler::shrptr(Register dst, int imm8) {
3749 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3750 }
3751
3752 void MacroAssembler::sign_extend_byte(Register reg) {
3753 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3754 movsbl(reg, reg); // movsxb
3755 } else {
3756 shll(reg, 24);
3757 sarl(reg, 24);
3758 }
3759 }
3760
3761 void MacroAssembler::sign_extend_short(Register reg) {
3762 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3763 movswl(reg, reg); // movsxw
3764 } else {
3765 shll(reg, 16);
3766 sarl(reg, 16);
3767 }
3768 }
3769
3770 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3771 assert(reachable(src), "Address should be reachable");
3772 testl(dst, as_Address(src));
3773 }
3774
3775 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3776 int dst_enc = dst->encoding();
3777 int src_enc = src->encoding();
3778 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3779 Assembler::pcmpeqb(dst, src);
3780 } else if ((dst_enc < 16) && (src_enc < 16)) {
3781 Assembler::pcmpeqb(dst, src);
3782 } else if (src_enc < 16) {
3783 subptr(rsp, 64);
3784 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3785 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3786 Assembler::pcmpeqb(xmm0, src);
3787 movdqu(dst, xmm0);
3788 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3789 addptr(rsp, 64);
3790 } else if (dst_enc < 16) {
3791 subptr(rsp, 64);
3792 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3793 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3794 Assembler::pcmpeqb(dst, xmm0);
3795 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3796 addptr(rsp, 64);
3797 } else {
3798 subptr(rsp, 64);
3799 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3800 subptr(rsp, 64);
3801 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3802 movdqu(xmm0, src);
3803 movdqu(xmm1, dst);
3804 Assembler::pcmpeqb(xmm1, xmm0);
3805 movdqu(dst, xmm1);
3806 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3807 addptr(rsp, 64);
3808 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3809 addptr(rsp, 64);
3810 }
3811 }
3812
3813 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3814 int dst_enc = dst->encoding();
3815 int src_enc = src->encoding();
3816 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3817 Assembler::pcmpeqw(dst, src);
3818 } else if ((dst_enc < 16) && (src_enc < 16)) {
3819 Assembler::pcmpeqw(dst, src);
3820 } else if (src_enc < 16) {
3821 subptr(rsp, 64);
3822 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3823 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3824 Assembler::pcmpeqw(xmm0, src);
3825 movdqu(dst, xmm0);
3826 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3827 addptr(rsp, 64);
3828 } else if (dst_enc < 16) {
3829 subptr(rsp, 64);
3830 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3831 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3832 Assembler::pcmpeqw(dst, xmm0);
3833 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3834 addptr(rsp, 64);
3835 } else {
3836 subptr(rsp, 64);
3837 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3838 subptr(rsp, 64);
3839 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3840 movdqu(xmm0, src);
3841 movdqu(xmm1, dst);
3842 Assembler::pcmpeqw(xmm1, xmm0);
3843 movdqu(dst, xmm1);
3844 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3845 addptr(rsp, 64);
3846 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3847 addptr(rsp, 64);
3848 }
3849 }
3850
3851 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3852 int dst_enc = dst->encoding();
3853 if (dst_enc < 16) {
3854 Assembler::pcmpestri(dst, src, imm8);
3855 } else {
3856 subptr(rsp, 64);
3857 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3858 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3859 Assembler::pcmpestri(xmm0, src, imm8);
3860 movdqu(dst, xmm0);
3861 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3862 addptr(rsp, 64);
3863 }
3864 }
3865
3866 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3867 int dst_enc = dst->encoding();
3868 int src_enc = src->encoding();
3869 if ((dst_enc < 16) && (src_enc < 16)) {
3870 Assembler::pcmpestri(dst, src, imm8);
3871 } else if (src_enc < 16) {
3872 subptr(rsp, 64);
3873 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3874 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3875 Assembler::pcmpestri(xmm0, src, imm8);
3876 movdqu(dst, xmm0);
3877 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3878 addptr(rsp, 64);
3879 } else if (dst_enc < 16) {
3880 subptr(rsp, 64);
3881 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3882 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3883 Assembler::pcmpestri(dst, xmm0, imm8);
3884 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3885 addptr(rsp, 64);
3886 } else {
3887 subptr(rsp, 64);
3888 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3889 subptr(rsp, 64);
3890 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3891 movdqu(xmm0, src);
3892 movdqu(xmm1, dst);
3893 Assembler::pcmpestri(xmm1, xmm0, imm8);
3894 movdqu(dst, xmm1);
3895 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3896 addptr(rsp, 64);
3897 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3898 addptr(rsp, 64);
3899 }
3900 }
3901
3902 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3903 int dst_enc = dst->encoding();
3904 int src_enc = src->encoding();
3905 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3906 Assembler::pmovzxbw(dst, src);
3907 } else if ((dst_enc < 16) && (src_enc < 16)) {
3908 Assembler::pmovzxbw(dst, src);
3909 } else if (src_enc < 16) {
3910 subptr(rsp, 64);
3911 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3912 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3913 Assembler::pmovzxbw(xmm0, src);
3914 movdqu(dst, xmm0);
3915 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3916 addptr(rsp, 64);
3917 } else if (dst_enc < 16) {
3918 subptr(rsp, 64);
3919 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3920 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3921 Assembler::pmovzxbw(dst, xmm0);
3922 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3923 addptr(rsp, 64);
3924 } else {
3925 subptr(rsp, 64);
3926 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3927 subptr(rsp, 64);
3928 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3929 movdqu(xmm0, src);
3930 movdqu(xmm1, dst);
3931 Assembler::pmovzxbw(xmm1, xmm0);
3932 movdqu(dst, xmm1);
3933 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3934 addptr(rsp, 64);
3935 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3936 addptr(rsp, 64);
3937 }
3938 }
3939
3940 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3941 int dst_enc = dst->encoding();
3942 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
3943 Assembler::pmovzxbw(dst, src);
3944 } else if (dst_enc < 16) {
3945 Assembler::pmovzxbw(dst, src);
3946 } else {
3947 subptr(rsp, 64);
3948 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3949 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3950 Assembler::pmovzxbw(xmm0, src);
3951 movdqu(dst, xmm0);
3952 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3953 addptr(rsp, 64);
3954 }
3955 }
3956
3957 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3958 int src_enc = src->encoding();
3959 if (src_enc < 16) {
3960 Assembler::pmovmskb(dst, src);
3961 } else {
3962 subptr(rsp, 64);
3963 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3964 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3965 Assembler::pmovmskb(dst, xmm0);
3966 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3967 addptr(rsp, 64);
3968 }
3969 }
3970
3971 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3972 int dst_enc = dst->encoding();
3973 int src_enc = src->encoding();
3974 if ((dst_enc < 16) && (src_enc < 16)) {
3975 Assembler::ptest(dst, src);
3976 } else if (src_enc < 16) {
3977 subptr(rsp, 64);
3978 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3979 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
3980 Assembler::ptest(xmm0, src);
3981 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3982 addptr(rsp, 64);
3983 } else if (dst_enc < 16) {
3984 subptr(rsp, 64);
3985 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3986 evmovdqul(xmm0, src, Assembler::AVX_512bit);
3987 Assembler::ptest(dst, xmm0);
3988 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
3989 addptr(rsp, 64);
3990 } else {
3991 subptr(rsp, 64);
3992 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
3993 subptr(rsp, 64);
3994 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
3995 movdqu(xmm0, src);
3996 movdqu(xmm1, dst);
3997 Assembler::ptest(xmm1, xmm0);
3998 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
3999 addptr(rsp, 64);
4000 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4001 addptr(rsp, 64);
4002 }
4003 }
4004
4005 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
4006 if (reachable(src)) {
4007 Assembler::sqrtsd(dst, as_Address(src));
4008 } else {
4009 lea(rscratch1, src);
4010 Assembler::sqrtsd(dst, Address(rscratch1, 0));
4011 }
4012 }
4013
4014 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
4015 if (reachable(src)) {
4016 Assembler::sqrtss(dst, as_Address(src));
4017 } else {
4018 lea(rscratch1, src);
4019 Assembler::sqrtss(dst, Address(rscratch1, 0));
4020 }
4021 }
4022
4023 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
4024 if (reachable(src)) {
4025 Assembler::subsd(dst, as_Address(src));
4026 } else {
4027 lea(rscratch1, src);
4028 Assembler::subsd(dst, Address(rscratch1, 0));
4029 }
4030 }
4031
4032 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
4033 if (reachable(src)) {
4034 Assembler::subss(dst, as_Address(src));
4035 } else {
4036 lea(rscratch1, src);
4037 Assembler::subss(dst, Address(rscratch1, 0));
4038 }
4039 }
4040
4041 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
4042 if (reachable(src)) {
4043 Assembler::ucomisd(dst, as_Address(src));
4044 } else {
4045 lea(rscratch1, src);
4046 Assembler::ucomisd(dst, Address(rscratch1, 0));
4047 }
4048 }
4049
4050 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
4051 if (reachable(src)) {
4052 Assembler::ucomiss(dst, as_Address(src));
4053 } else {
4054 lea(rscratch1, src);
4055 Assembler::ucomiss(dst, Address(rscratch1, 0));
4056 }
4057 }
4058
4059 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) {
4060 // Used in sign-bit flipping with aligned address.
4061 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4062 if (reachable(src)) {
4063 Assembler::xorpd(dst, as_Address(src));
4064 } else {
4065 lea(rscratch1, src);
4066 Assembler::xorpd(dst, Address(rscratch1, 0));
4067 }
4068 }
4069
4070 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
4071 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4072 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4073 }
4074 else {
4075 Assembler::xorpd(dst, src);
4076 }
4077 }
4078
4079 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
4080 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
4081 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
4082 } else {
4083 Assembler::xorps(dst, src);
4084 }
4085 }
4086
4087 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) {
4088 // Used in sign-bit flipping with aligned address.
4089 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
4090 if (reachable(src)) {
4091 Assembler::xorps(dst, as_Address(src));
4092 } else {
4093 lea(rscratch1, src);
4094 Assembler::xorps(dst, Address(rscratch1, 0));
4095 }
4096 }
4097
4098 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
4099 // Used in sign-bit flipping with aligned address.
4100 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
4101 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
4102 if (reachable(src)) {
4103 Assembler::pshufb(dst, as_Address(src));
4104 } else {
4105 lea(rscratch1, src);
4106 Assembler::pshufb(dst, Address(rscratch1, 0));
4107 }
4108 }
4109
4110 // AVX 3-operands instructions
4111
4112 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4113 if (reachable(src)) {
4114 vaddsd(dst, nds, as_Address(src));
4115 } else {
4116 lea(rscratch1, src);
4117 vaddsd(dst, nds, Address(rscratch1, 0));
4118 }
4119 }
4120
4121 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
4122 if (reachable(src)) {
4123 vaddss(dst, nds, as_Address(src));
4124 } else {
4125 lea(rscratch1, src);
4126 vaddss(dst, nds, Address(rscratch1, 0));
4127 }
4128 }
4129
4130 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4131 int dst_enc = dst->encoding();
4132 int nds_enc = nds->encoding();
4133 int src_enc = src->encoding();
4134 if ((dst_enc < 16) && (nds_enc < 16)) {
4135 vandps(dst, nds, negate_field, vector_len);
4136 } else if ((src_enc < 16) && (dst_enc < 16)) {
4137 movss(src, nds);
4138 vandps(dst, src, negate_field, vector_len);
4139 } else if (src_enc < 16) {
4140 movss(src, nds);
4141 vandps(src, src, negate_field, vector_len);
4142 movss(dst, src);
4143 } else if (dst_enc < 16) {
4144 movdqu(src, xmm0);
4145 movss(xmm0, nds);
4146 vandps(dst, xmm0, negate_field, vector_len);
4147 movdqu(xmm0, src);
4148 } else {
4149 if (src_enc != dst_enc) {
4150 movdqu(src, xmm0);
4151 movss(xmm0, nds);
4152 vandps(xmm0, xmm0, negate_field, vector_len);
4153 movss(dst, xmm0);
4154 movdqu(xmm0, src);
4155 } else {
4156 subptr(rsp, 64);
4157 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4158 movss(xmm0, nds);
4159 vandps(xmm0, xmm0, negate_field, vector_len);
4160 movss(dst, xmm0);
4161 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4162 addptr(rsp, 64);
4163 }
4164 }
4165 }
4166
4167 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
4168 int dst_enc = dst->encoding();
4169 int nds_enc = nds->encoding();
4170 int src_enc = src->encoding();
4171 if ((dst_enc < 16) && (nds_enc < 16)) {
4172 vandpd(dst, nds, negate_field, vector_len);
4173 } else if ((src_enc < 16) && (dst_enc < 16)) {
4174 movsd(src, nds);
4175 vandpd(dst, src, negate_field, vector_len);
4176 } else if (src_enc < 16) {
4177 movsd(src, nds);
4178 vandpd(src, src, negate_field, vector_len);
4179 movsd(dst, src);
4180 } else if (dst_enc < 16) {
4181 movdqu(src, xmm0);
4182 movsd(xmm0, nds);
4183 vandpd(dst, xmm0, negate_field, vector_len);
4184 movdqu(xmm0, src);
4185 } else {
4186 if (src_enc != dst_enc) {
4187 movdqu(src, xmm0);
4188 movsd(xmm0, nds);
4189 vandpd(xmm0, xmm0, negate_field, vector_len);
4190 movsd(dst, xmm0);
4191 movdqu(xmm0, src);
4192 } else {
4193 subptr(rsp, 64);
4194 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4195 movsd(xmm0, nds);
4196 vandpd(xmm0, xmm0, negate_field, vector_len);
4197 movsd(dst, xmm0);
4198 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4199 addptr(rsp, 64);
4200 }
4201 }
4202 }
4203
4204 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4205 int dst_enc = dst->encoding();
4206 int nds_enc = nds->encoding();
4207 int src_enc = src->encoding();
4208 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4209 Assembler::vpaddb(dst, nds, src, vector_len);
4210 } else if ((dst_enc < 16) && (src_enc < 16)) {
4211 Assembler::vpaddb(dst, dst, src, vector_len);
4212 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4213 // use nds as scratch for src
4214 evmovdqul(nds, src, Assembler::AVX_512bit);
4215 Assembler::vpaddb(dst, dst, nds, vector_len);
4216 } else if ((src_enc < 16) && (nds_enc < 16)) {
4217 // use nds as scratch for dst
4218 evmovdqul(nds, dst, Assembler::AVX_512bit);
4219 Assembler::vpaddb(nds, nds, src, vector_len);
4220 evmovdqul(dst, nds, Assembler::AVX_512bit);
4221 } else if (dst_enc < 16) {
4222 // use nds as scatch for xmm0 to hold src
4223 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4224 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4225 Assembler::vpaddb(dst, dst, xmm0, vector_len);
4226 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4227 } else {
4228 // worse case scenario, all regs are in the upper bank
4229 subptr(rsp, 64);
4230 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4231 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4232 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4233 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4234 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len);
4235 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4236 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4237 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4238 addptr(rsp, 64);
4239 }
4240 }
4241
4242 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4243 int dst_enc = dst->encoding();
4244 int nds_enc = nds->encoding();
4245 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4246 Assembler::vpaddb(dst, nds, src, vector_len);
4247 } else if (dst_enc < 16) {
4248 Assembler::vpaddb(dst, dst, src, vector_len);
4249 } else if (nds_enc < 16) {
4250 // implies dst_enc in upper bank with src as scratch
4251 evmovdqul(nds, dst, Assembler::AVX_512bit);
4252 Assembler::vpaddb(nds, nds, src, vector_len);
4253 evmovdqul(dst, nds, Assembler::AVX_512bit);
4254 } else {
4255 // worse case scenario, all regs in upper bank
4256 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4257 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4258 Assembler::vpaddb(xmm0, xmm0, src, vector_len);
4259 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4260 }
4261 }
4262
4263 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4264 int dst_enc = dst->encoding();
4265 int nds_enc = nds->encoding();
4266 int src_enc = src->encoding();
4267 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4268 Assembler::vpaddw(dst, nds, src, vector_len);
4269 } else if ((dst_enc < 16) && (src_enc < 16)) {
4270 Assembler::vpaddw(dst, dst, src, vector_len);
4271 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4272 // use nds as scratch for src
4273 evmovdqul(nds, src, Assembler::AVX_512bit);
4274 Assembler::vpaddw(dst, dst, nds, vector_len);
4275 } else if ((src_enc < 16) && (nds_enc < 16)) {
4276 // use nds as scratch for dst
4277 evmovdqul(nds, dst, Assembler::AVX_512bit);
4278 Assembler::vpaddw(nds, nds, src, vector_len);
4279 evmovdqul(dst, nds, Assembler::AVX_512bit);
4280 } else if (dst_enc < 16) {
4281 // use nds as scatch for xmm0 to hold src
4282 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4283 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4284 Assembler::vpaddw(dst, dst, xmm0, vector_len);
4285 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4286 } else {
4287 // worse case scenario, all regs are in the upper bank
4288 subptr(rsp, 64);
4289 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4290 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4291 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4292 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4293 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len);
4294 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4295 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4296 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4297 addptr(rsp, 64);
4298 }
4299 }
4300
4301 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4302 int dst_enc = dst->encoding();
4303 int nds_enc = nds->encoding();
4304 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4305 Assembler::vpaddw(dst, nds, src, vector_len);
4306 } else if (dst_enc < 16) {
4307 Assembler::vpaddw(dst, dst, src, vector_len);
4308 } else if (nds_enc < 16) {
4309 // implies dst_enc in upper bank with src as scratch
4310 evmovdqul(nds, dst, Assembler::AVX_512bit);
4311 Assembler::vpaddw(nds, nds, src, vector_len);
4312 evmovdqul(dst, nds, Assembler::AVX_512bit);
4313 } else {
4314 // worse case scenario, all regs in upper bank
4315 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4316 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4317 Assembler::vpaddw(xmm0, xmm0, src, vector_len);
4318 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4319 }
4320 }
4321
4322 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
4323 if (reachable(src)) {
4324 Assembler::vpand(dst, nds, as_Address(src), vector_len);
4325 } else {
4326 lea(rscratch1, src);
4327 Assembler::vpand(dst, nds, Address(rscratch1, 0), vector_len);
4328 }
4329 }
4330
4331 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
4332 int dst_enc = dst->encoding();
4333 int src_enc = src->encoding();
4334 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4335 Assembler::vpbroadcastw(dst, src);
4336 } else if ((dst_enc < 16) && (src_enc < 16)) {
4337 Assembler::vpbroadcastw(dst, src);
4338 } else if (src_enc < 16) {
4339 subptr(rsp, 64);
4340 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4341 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4342 Assembler::vpbroadcastw(xmm0, src);
4343 movdqu(dst, xmm0);
4344 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4345 addptr(rsp, 64);
4346 } else if (dst_enc < 16) {
4347 subptr(rsp, 64);
4348 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4349 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4350 Assembler::vpbroadcastw(dst, xmm0);
4351 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4352 addptr(rsp, 64);
4353 } else {
4354 subptr(rsp, 64);
4355 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4356 subptr(rsp, 64);
4357 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4358 movdqu(xmm0, src);
4359 movdqu(xmm1, dst);
4360 Assembler::vpbroadcastw(xmm1, xmm0);
4361 movdqu(dst, xmm1);
4362 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4363 addptr(rsp, 64);
4364 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4365 addptr(rsp, 64);
4366 }
4367 }
4368
4369 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4370 int dst_enc = dst->encoding();
4371 int nds_enc = nds->encoding();
4372 int src_enc = src->encoding();
4373 assert(dst_enc == nds_enc, "");
4374 if ((dst_enc < 16) && (src_enc < 16)) {
4375 Assembler::vpcmpeqb(dst, nds, src, vector_len);
4376 } else if (src_enc < 16) {
4377 subptr(rsp, 64);
4378 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4379 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4380 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len);
4381 movdqu(dst, xmm0);
4382 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4383 addptr(rsp, 64);
4384 } else if (dst_enc < 16) {
4385 subptr(rsp, 64);
4386 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4387 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4388 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len);
4389 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4390 addptr(rsp, 64);
4391 } else {
4392 subptr(rsp, 64);
4393 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4394 subptr(rsp, 64);
4395 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4396 movdqu(xmm0, src);
4397 movdqu(xmm1, dst);
4398 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len);
4399 movdqu(dst, xmm1);
4400 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4401 addptr(rsp, 64);
4402 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4403 addptr(rsp, 64);
4404 }
4405 }
4406
4407 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4408 int dst_enc = dst->encoding();
4409 int nds_enc = nds->encoding();
4410 int src_enc = src->encoding();
4411 assert(dst_enc == nds_enc, "");
4412 if ((dst_enc < 16) && (src_enc < 16)) {
4413 Assembler::vpcmpeqw(dst, nds, src, vector_len);
4414 } else if (src_enc < 16) {
4415 subptr(rsp, 64);
4416 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4417 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4418 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len);
4419 movdqu(dst, xmm0);
4420 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4421 addptr(rsp, 64);
4422 } else if (dst_enc < 16) {
4423 subptr(rsp, 64);
4424 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4425 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4426 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len);
4427 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4428 addptr(rsp, 64);
4429 } else {
4430 subptr(rsp, 64);
4431 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4432 subptr(rsp, 64);
4433 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4434 movdqu(xmm0, src);
4435 movdqu(xmm1, dst);
4436 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len);
4437 movdqu(dst, xmm1);
4438 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4439 addptr(rsp, 64);
4440 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4441 addptr(rsp, 64);
4442 }
4443 }
4444
4445 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4446 int dst_enc = dst->encoding();
4447 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4448 Assembler::vpmovzxbw(dst, src, vector_len);
4449 } else if (dst_enc < 16) {
4450 Assembler::vpmovzxbw(dst, src, vector_len);
4451 } else {
4452 subptr(rsp, 64);
4453 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4454 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4455 Assembler::vpmovzxbw(xmm0, src, vector_len);
4456 movdqu(dst, xmm0);
4457 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4458 addptr(rsp, 64);
4459 }
4460 }
4461
4462 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) {
4463 int src_enc = src->encoding();
4464 if (src_enc < 16) {
4465 Assembler::vpmovmskb(dst, src);
4466 } else {
4467 subptr(rsp, 64);
4468 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4469 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4470 Assembler::vpmovmskb(dst, xmm0);
4471 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4472 addptr(rsp, 64);
4473 }
4474 }
4475
4476 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4477 int dst_enc = dst->encoding();
4478 int nds_enc = nds->encoding();
4479 int src_enc = src->encoding();
4480 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4481 Assembler::vpmullw(dst, nds, src, vector_len);
4482 } else if ((dst_enc < 16) && (src_enc < 16)) {
4483 Assembler::vpmullw(dst, dst, src, vector_len);
4484 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4485 // use nds as scratch for src
4486 evmovdqul(nds, src, Assembler::AVX_512bit);
4487 Assembler::vpmullw(dst, dst, nds, vector_len);
4488 } else if ((src_enc < 16) && (nds_enc < 16)) {
4489 // use nds as scratch for dst
4490 evmovdqul(nds, dst, Assembler::AVX_512bit);
4491 Assembler::vpmullw(nds, nds, src, vector_len);
4492 evmovdqul(dst, nds, Assembler::AVX_512bit);
4493 } else if (dst_enc < 16) {
4494 // use nds as scatch for xmm0 to hold src
4495 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4496 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4497 Assembler::vpmullw(dst, dst, xmm0, vector_len);
4498 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4499 } else {
4500 // worse case scenario, all regs are in the upper bank
4501 subptr(rsp, 64);
4502 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4503 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4504 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4505 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4506 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len);
4507 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4508 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4509 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4510 addptr(rsp, 64);
4511 }
4512 }
4513
4514 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4515 int dst_enc = dst->encoding();
4516 int nds_enc = nds->encoding();
4517 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4518 Assembler::vpmullw(dst, nds, src, vector_len);
4519 } else if (dst_enc < 16) {
4520 Assembler::vpmullw(dst, dst, src, vector_len);
4521 } else if (nds_enc < 16) {
4522 // implies dst_enc in upper bank with src as scratch
4523 evmovdqul(nds, dst, Assembler::AVX_512bit);
4524 Assembler::vpmullw(nds, nds, src, vector_len);
4525 evmovdqul(dst, nds, Assembler::AVX_512bit);
4526 } else {
4527 // worse case scenario, all regs in upper bank
4528 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4529 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4530 Assembler::vpmullw(xmm0, xmm0, src, vector_len);
4531 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4532 }
4533 }
4534
4535 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4536 int dst_enc = dst->encoding();
4537 int nds_enc = nds->encoding();
4538 int src_enc = src->encoding();
4539 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4540 Assembler::vpsubb(dst, nds, src, vector_len);
4541 } else if ((dst_enc < 16) && (src_enc < 16)) {
4542 Assembler::vpsubb(dst, dst, src, vector_len);
4543 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4544 // use nds as scratch for src
4545 evmovdqul(nds, src, Assembler::AVX_512bit);
4546 Assembler::vpsubb(dst, dst, nds, vector_len);
4547 } else if ((src_enc < 16) && (nds_enc < 16)) {
4548 // use nds as scratch for dst
4549 evmovdqul(nds, dst, Assembler::AVX_512bit);
4550 Assembler::vpsubb(nds, nds, src, vector_len);
4551 evmovdqul(dst, nds, Assembler::AVX_512bit);
4552 } else if (dst_enc < 16) {
4553 // use nds as scatch for xmm0 to hold src
4554 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4555 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4556 Assembler::vpsubb(dst, dst, xmm0, vector_len);
4557 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4558 } else {
4559 // worse case scenario, all regs are in the upper bank
4560 subptr(rsp, 64);
4561 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4562 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4563 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4564 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4565 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len);
4566 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4567 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4568 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4569 addptr(rsp, 64);
4570 }
4571 }
4572
4573 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4574 int dst_enc = dst->encoding();
4575 int nds_enc = nds->encoding();
4576 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4577 Assembler::vpsubb(dst, nds, src, vector_len);
4578 } else if (dst_enc < 16) {
4579 Assembler::vpsubb(dst, dst, src, vector_len);
4580 } else if (nds_enc < 16) {
4581 // implies dst_enc in upper bank with src as scratch
4582 evmovdqul(nds, dst, Assembler::AVX_512bit);
4583 Assembler::vpsubb(nds, nds, src, vector_len);
4584 evmovdqul(dst, nds, Assembler::AVX_512bit);
4585 } else {
4586 // worse case scenario, all regs in upper bank
4587 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4588 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4589 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4590 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4591 }
4592 }
4593
4594 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4595 int dst_enc = dst->encoding();
4596 int nds_enc = nds->encoding();
4597 int src_enc = src->encoding();
4598 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4599 Assembler::vpsubw(dst, nds, src, vector_len);
4600 } else if ((dst_enc < 16) && (src_enc < 16)) {
4601 Assembler::vpsubw(dst, dst, src, vector_len);
4602 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4603 // use nds as scratch for src
4604 evmovdqul(nds, src, Assembler::AVX_512bit);
4605 Assembler::vpsubw(dst, dst, nds, vector_len);
4606 } else if ((src_enc < 16) && (nds_enc < 16)) {
4607 // use nds as scratch for dst
4608 evmovdqul(nds, dst, Assembler::AVX_512bit);
4609 Assembler::vpsubw(nds, nds, src, vector_len);
4610 evmovdqul(dst, nds, Assembler::AVX_512bit);
4611 } else if (dst_enc < 16) {
4612 // use nds as scatch for xmm0 to hold src
4613 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4614 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4615 Assembler::vpsubw(dst, dst, xmm0, vector_len);
4616 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4617 } else {
4618 // worse case scenario, all regs are in the upper bank
4619 subptr(rsp, 64);
4620 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4621 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4622 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4623 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4624 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len);
4625 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4626 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4627 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4628 addptr(rsp, 64);
4629 }
4630 }
4631
4632 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4633 int dst_enc = dst->encoding();
4634 int nds_enc = nds->encoding();
4635 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4636 Assembler::vpsubw(dst, nds, src, vector_len);
4637 } else if (dst_enc < 16) {
4638 Assembler::vpsubw(dst, dst, src, vector_len);
4639 } else if (nds_enc < 16) {
4640 // implies dst_enc in upper bank with src as scratch
4641 evmovdqul(nds, dst, Assembler::AVX_512bit);
4642 Assembler::vpsubw(nds, nds, src, vector_len);
4643 evmovdqul(dst, nds, Assembler::AVX_512bit);
4644 } else {
4645 // worse case scenario, all regs in upper bank
4646 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4647 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4648 Assembler::vpsubw(xmm0, xmm0, src, vector_len);
4649 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4650 }
4651 }
4652
4653 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4654 int dst_enc = dst->encoding();
4655 int nds_enc = nds->encoding();
4656 int shift_enc = shift->encoding();
4657 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4658 Assembler::vpsraw(dst, nds, shift, vector_len);
4659 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4660 Assembler::vpsraw(dst, dst, shift, vector_len);
4661 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4662 // use nds_enc as scratch with shift
4663 evmovdqul(nds, shift, Assembler::AVX_512bit);
4664 Assembler::vpsraw(dst, dst, nds, vector_len);
4665 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4666 // use nds as scratch with dst
4667 evmovdqul(nds, dst, Assembler::AVX_512bit);
4668 Assembler::vpsraw(nds, nds, shift, vector_len);
4669 evmovdqul(dst, nds, Assembler::AVX_512bit);
4670 } else if (dst_enc < 16) {
4671 // use nds to save a copy of xmm0 and hold shift
4672 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4673 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4674 Assembler::vpsraw(dst, dst, xmm0, vector_len);
4675 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4676 } else if (nds_enc < 16) {
4677 // use nds as dest as temps
4678 evmovdqul(nds, dst, Assembler::AVX_512bit);
4679 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4680 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4681 Assembler::vpsraw(nds, nds, xmm0, vector_len);
4682 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4683 evmovdqul(dst, nds, Assembler::AVX_512bit);
4684 } else {
4685 // worse case scenario, all regs are in the upper bank
4686 subptr(rsp, 64);
4687 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4688 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4689 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4690 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4691 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4692 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4693 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4694 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4695 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4696 addptr(rsp, 64);
4697 }
4698 }
4699
4700 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4701 int dst_enc = dst->encoding();
4702 int nds_enc = nds->encoding();
4703 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4704 Assembler::vpsraw(dst, nds, shift, vector_len);
4705 } else if (dst_enc < 16) {
4706 Assembler::vpsraw(dst, dst, shift, vector_len);
4707 } else if (nds_enc < 16) {
4708 // use nds as scratch
4709 evmovdqul(nds, dst, Assembler::AVX_512bit);
4710 Assembler::vpsraw(nds, nds, shift, vector_len);
4711 evmovdqul(dst, nds, Assembler::AVX_512bit);
4712 } else {
4713 // use nds as scratch for xmm0
4714 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4715 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4716 Assembler::vpsraw(xmm0, xmm0, shift, vector_len);
4717 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4718 }
4719 }
4720
4721 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4722 int dst_enc = dst->encoding();
4723 int nds_enc = nds->encoding();
4724 int shift_enc = shift->encoding();
4725 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4726 Assembler::vpsrlw(dst, nds, shift, vector_len);
4727 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4728 Assembler::vpsrlw(dst, dst, shift, vector_len);
4729 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4730 // use nds_enc as scratch with shift
4731 evmovdqul(nds, shift, Assembler::AVX_512bit);
4732 Assembler::vpsrlw(dst, dst, nds, vector_len);
4733 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4734 // use nds as scratch with dst
4735 evmovdqul(nds, dst, Assembler::AVX_512bit);
4736 Assembler::vpsrlw(nds, nds, shift, vector_len);
4737 evmovdqul(dst, nds, Assembler::AVX_512bit);
4738 } else if (dst_enc < 16) {
4739 // use nds to save a copy of xmm0 and hold shift
4740 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4741 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4742 Assembler::vpsrlw(dst, dst, xmm0, vector_len);
4743 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4744 } else if (nds_enc < 16) {
4745 // use nds as dest as temps
4746 evmovdqul(nds, dst, Assembler::AVX_512bit);
4747 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4748 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4749 Assembler::vpsrlw(nds, nds, xmm0, vector_len);
4750 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4751 evmovdqul(dst, nds, Assembler::AVX_512bit);
4752 } else {
4753 // worse case scenario, all regs are in the upper bank
4754 subptr(rsp, 64);
4755 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4756 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4757 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4758 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4759 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4760 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4761 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4762 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4763 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4764 addptr(rsp, 64);
4765 }
4766 }
4767
4768 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4769 int dst_enc = dst->encoding();
4770 int nds_enc = nds->encoding();
4771 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4772 Assembler::vpsrlw(dst, nds, shift, vector_len);
4773 } else if (dst_enc < 16) {
4774 Assembler::vpsrlw(dst, dst, shift, vector_len);
4775 } else if (nds_enc < 16) {
4776 // use nds as scratch
4777 evmovdqul(nds, dst, Assembler::AVX_512bit);
4778 Assembler::vpsrlw(nds, nds, shift, vector_len);
4779 evmovdqul(dst, nds, Assembler::AVX_512bit);
4780 } else {
4781 // use nds as scratch for xmm0
4782 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4783 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4784 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len);
4785 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4786 }
4787 }
4788
4789 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
4790 int dst_enc = dst->encoding();
4791 int nds_enc = nds->encoding();
4792 int shift_enc = shift->encoding();
4793 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4794 Assembler::vpsllw(dst, nds, shift, vector_len);
4795 } else if ((dst_enc < 16) && (shift_enc < 16)) {
4796 Assembler::vpsllw(dst, dst, shift, vector_len);
4797 } else if ((dst_enc < 16) && (nds_enc < 16)) {
4798 // use nds_enc as scratch with shift
4799 evmovdqul(nds, shift, Assembler::AVX_512bit);
4800 Assembler::vpsllw(dst, dst, nds, vector_len);
4801 } else if ((shift_enc < 16) && (nds_enc < 16)) {
4802 // use nds as scratch with dst
4803 evmovdqul(nds, dst, Assembler::AVX_512bit);
4804 Assembler::vpsllw(nds, nds, shift, vector_len);
4805 evmovdqul(dst, nds, Assembler::AVX_512bit);
4806 } else if (dst_enc < 16) {
4807 // use nds to save a copy of xmm0 and hold shift
4808 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4809 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4810 Assembler::vpsllw(dst, dst, xmm0, vector_len);
4811 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4812 } else if (nds_enc < 16) {
4813 // use nds as dest as temps
4814 evmovdqul(nds, dst, Assembler::AVX_512bit);
4815 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4816 evmovdqul(xmm0, shift, Assembler::AVX_512bit);
4817 Assembler::vpsllw(nds, nds, xmm0, vector_len);
4818 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4819 evmovdqul(dst, nds, Assembler::AVX_512bit);
4820 } else {
4821 // worse case scenario, all regs are in the upper bank
4822 subptr(rsp, 64);
4823 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4824 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4825 evmovdqul(xmm1, shift, Assembler::AVX_512bit);
4826 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4827 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len);
4828 evmovdqul(xmm1, dst, Assembler::AVX_512bit);
4829 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4830 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4831 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4832 addptr(rsp, 64);
4833 }
4834 }
4835
4836 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
4837 int dst_enc = dst->encoding();
4838 int nds_enc = nds->encoding();
4839 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) {
4840 Assembler::vpsllw(dst, nds, shift, vector_len);
4841 } else if (dst_enc < 16) {
4842 Assembler::vpsllw(dst, dst, shift, vector_len);
4843 } else if (nds_enc < 16) {
4844 // use nds as scratch
4845 evmovdqul(nds, dst, Assembler::AVX_512bit);
4846 Assembler::vpsllw(nds, nds, shift, vector_len);
4847 evmovdqul(dst, nds, Assembler::AVX_512bit);
4848 } else {
4849 // use nds as scratch for xmm0
4850 evmovdqul(nds, xmm0, Assembler::AVX_512bit);
4851 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4852 Assembler::vpsllw(xmm0, xmm0, shift, vector_len);
4853 evmovdqul(xmm0, nds, Assembler::AVX_512bit);
4854 }
4855 }
4856
4857 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
4858 int dst_enc = dst->encoding();
4859 int src_enc = src->encoding();
4860 if ((dst_enc < 16) && (src_enc < 16)) {
4861 Assembler::vptest(dst, src);
4862 } else if (src_enc < 16) {
4863 subptr(rsp, 64);
4864 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4865 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4866 Assembler::vptest(xmm0, src);
4867 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4868 addptr(rsp, 64);
4869 } else if (dst_enc < 16) {
4870 subptr(rsp, 64);
4871 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4872 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4873 Assembler::vptest(dst, xmm0);
4874 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4875 addptr(rsp, 64);
4876 } else {
4877 subptr(rsp, 64);
4878 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4879 subptr(rsp, 64);
4880 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4881 movdqu(xmm0, src);
4882 movdqu(xmm1, dst);
4883 Assembler::vptest(xmm1, xmm0);
4884 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4885 addptr(rsp, 64);
4886 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4887 addptr(rsp, 64);
4888 }
4889 }
4890
4891 // This instruction exists within macros, ergo we cannot control its input
4892 // when emitted through those patterns.
4893 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4894 if (VM_Version::supports_avx512nobw()) {
4895 int dst_enc = dst->encoding();
4896 int src_enc = src->encoding();
4897 if (dst_enc == src_enc) {
4898 if (dst_enc < 16) {
4899 Assembler::punpcklbw(dst, src);
4900 } else {
4901 subptr(rsp, 64);
4902 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4903 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4904 Assembler::punpcklbw(xmm0, xmm0);
4905 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4906 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4907 addptr(rsp, 64);
4908 }
4909 } else {
4910 if ((src_enc < 16) && (dst_enc < 16)) {
4911 Assembler::punpcklbw(dst, src);
4912 } else if (src_enc < 16) {
4913 subptr(rsp, 64);
4914 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4915 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4916 Assembler::punpcklbw(xmm0, src);
4917 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4918 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4919 addptr(rsp, 64);
4920 } else if (dst_enc < 16) {
4921 subptr(rsp, 64);
4922 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4923 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4924 Assembler::punpcklbw(dst, xmm0);
4925 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4926 addptr(rsp, 64);
4927 } else {
4928 subptr(rsp, 64);
4929 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4930 subptr(rsp, 64);
4931 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
4932 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4933 evmovdqul(xmm1, src, Assembler::AVX_512bit);
4934 Assembler::punpcklbw(xmm0, xmm1);
4935 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4936 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
4937 addptr(rsp, 64);
4938 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4939 addptr(rsp, 64);
4940 }
4941 }
4942 } else {
4943 Assembler::punpcklbw(dst, src);
4944 }
4945 }
4946
4947 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
4948 if (VM_Version::supports_avx512vl()) {
4949 Assembler::pshufd(dst, src, mode);
4950 } else {
4951 int dst_enc = dst->encoding();
4952 if (dst_enc < 16) {
4953 Assembler::pshufd(dst, src, mode);
4954 } else {
4955 subptr(rsp, 64);
4956 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4957 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4958 Assembler::pshufd(xmm0, src, mode);
4959 movdqu(dst, xmm0);
4960 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4961 addptr(rsp, 64);
4962 }
4963 }
4964 }
4965
4966 // This instruction exists within macros, ergo we cannot control its input
4967 // when emitted through those patterns.
4968 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4969 if (VM_Version::supports_avx512nobw()) {
4970 int dst_enc = dst->encoding();
4971 int src_enc = src->encoding();
4972 if (dst_enc == src_enc) {
4973 if (dst_enc < 16) {
4974 Assembler::pshuflw(dst, src, mode);
4975 } else {
4976 subptr(rsp, 64);
4977 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4978 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4979 Assembler::pshuflw(xmm0, xmm0, mode);
4980 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4981 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4982 addptr(rsp, 64);
4983 }
4984 } else {
4985 if ((src_enc < 16) && (dst_enc < 16)) {
4986 Assembler::pshuflw(dst, src, mode);
4987 } else if (src_enc < 16) {
4988 subptr(rsp, 64);
4989 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4990 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
4991 Assembler::pshuflw(xmm0, src, mode);
4992 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
4993 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
4994 addptr(rsp, 64);
4995 } else if (dst_enc < 16) {
4996 subptr(rsp, 64);
4997 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
4998 evmovdqul(xmm0, src, Assembler::AVX_512bit);
4999 Assembler::pshuflw(dst, xmm0, mode);
5000 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5001 addptr(rsp, 64);
5002 } else {
5003 subptr(rsp, 64);
5004 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5005 subptr(rsp, 64);
5006 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit);
5007 evmovdqul(xmm0, dst, Assembler::AVX_512bit);
5008 evmovdqul(xmm1, src, Assembler::AVX_512bit);
5009 Assembler::pshuflw(xmm0, xmm1, mode);
5010 evmovdqul(dst, xmm0, Assembler::AVX_512bit);
5011 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit);
5012 addptr(rsp, 64);
5013 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5014 addptr(rsp, 64);
5015 }
5016 }
5017 } else {
5018 Assembler::pshuflw(dst, src, mode);
5019 }
5020 }
5021
5022 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5023 if (reachable(src)) {
5024 vandpd(dst, nds, as_Address(src), vector_len);
5025 } else {
5026 lea(rscratch1, src);
5027 vandpd(dst, nds, Address(rscratch1, 0), vector_len);
5028 }
5029 }
5030
5031 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5032 if (reachable(src)) {
5033 vandps(dst, nds, as_Address(src), vector_len);
5034 } else {
5035 lea(rscratch1, src);
5036 vandps(dst, nds, Address(rscratch1, 0), vector_len);
5037 }
5038 }
5039
5040 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5041 if (reachable(src)) {
5042 vdivsd(dst, nds, as_Address(src));
5043 } else {
5044 lea(rscratch1, src);
5045 vdivsd(dst, nds, Address(rscratch1, 0));
5046 }
5047 }
5048
5049 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5050 if (reachable(src)) {
5051 vdivss(dst, nds, as_Address(src));
5052 } else {
5053 lea(rscratch1, src);
5054 vdivss(dst, nds, Address(rscratch1, 0));
5055 }
5056 }
5057
5058 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5059 if (reachable(src)) {
5060 vmulsd(dst, nds, as_Address(src));
5061 } else {
5062 lea(rscratch1, src);
5063 vmulsd(dst, nds, Address(rscratch1, 0));
5064 }
5065 }
5066
5067 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5068 if (reachable(src)) {
5069 vmulss(dst, nds, as_Address(src));
5070 } else {
5071 lea(rscratch1, src);
5072 vmulss(dst, nds, Address(rscratch1, 0));
5073 }
5074 }
5075
5076 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5077 if (reachable(src)) {
5078 vsubsd(dst, nds, as_Address(src));
5079 } else {
5080 lea(rscratch1, src);
5081 vsubsd(dst, nds, Address(rscratch1, 0));
5082 }
5083 }
5084
5085 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5086 if (reachable(src)) {
5087 vsubss(dst, nds, as_Address(src));
5088 } else {
5089 lea(rscratch1, src);
5090 vsubss(dst, nds, Address(rscratch1, 0));
5091 }
5092 }
5093
5094 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5095 int nds_enc = nds->encoding();
5096 int dst_enc = dst->encoding();
5097 bool dst_upper_bank = (dst_enc > 15);
5098 bool nds_upper_bank = (nds_enc > 15);
5099 if (VM_Version::supports_avx512novl() &&
5100 (nds_upper_bank || dst_upper_bank)) {
5101 if (dst_upper_bank) {
5102 subptr(rsp, 64);
5103 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5104 movflt(xmm0, nds);
5105 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit);
5106 movflt(dst, xmm0);
5107 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5108 addptr(rsp, 64);
5109 } else {
5110 movflt(dst, nds);
5111 vxorps(dst, dst, src, Assembler::AVX_128bit);
5112 }
5113 } else {
5114 vxorps(dst, nds, src, Assembler::AVX_128bit);
5115 }
5116 }
5117
5118 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
5119 int nds_enc = nds->encoding();
5120 int dst_enc = dst->encoding();
5121 bool dst_upper_bank = (dst_enc > 15);
5122 bool nds_upper_bank = (nds_enc > 15);
5123 if (VM_Version::supports_avx512novl() &&
5124 (nds_upper_bank || dst_upper_bank)) {
5125 if (dst_upper_bank) {
5126 subptr(rsp, 64);
5127 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit);
5128 movdbl(xmm0, nds);
5129 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit);
5130 movdbl(dst, xmm0);
5131 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit);
5132 addptr(rsp, 64);
5133 } else {
5134 movdbl(dst, nds);
5135 vxorpd(dst, dst, src, Assembler::AVX_128bit);
5136 }
5137 } else {
5138 vxorpd(dst, nds, src, Assembler::AVX_128bit);
5139 }
5140 }
5141
5142 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5143 if (reachable(src)) {
5144 vxorpd(dst, nds, as_Address(src), vector_len);
5145 } else {
5146 lea(rscratch1, src);
5147 vxorpd(dst, nds, Address(rscratch1, 0), vector_len);
5148 }
5149 }
5150
5151 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) {
5152 if (reachable(src)) {
5153 vxorps(dst, nds, as_Address(src), vector_len);
5154 } else {
5155 lea(rscratch1, src);
5156 vxorps(dst, nds, Address(rscratch1, 0), vector_len);
5157 }
5158 }
5159
5160
5161 void MacroAssembler::resolve_jobject(Register value,
5162 Register thread,
5163 Register tmp) {
5164 assert_different_registers(value, thread, tmp);
5165 Label done, not_weak;
5166 testptr(value, value);
5167 jcc(Assembler::zero, done); // Use NULL as-is.
5168 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
5169 jcc(Assembler::zero, not_weak);
5170 // Resolve jweak.
5171 movptr(value, Address(value, -JNIHandles::weak_tag_value));
5172 verify_oop(value);
5173 #if INCLUDE_ALL_GCS
5174 if (UseG1GC) {
5175 g1_write_barrier_pre(noreg /* obj */,
5176 value /* pre_val */,
5177 thread /* thread */,
5178 tmp /* tmp */,
5179 true /* tosca_live */,
5180 true /* expand_call */);
5181 }
5182 #endif // INCLUDE_ALL_GCS
5183 jmp(done);
5184 bind(not_weak);
5185 // Resolve (untagged) jobject.
5186 movptr(value, Address(value, 0));
5187 verify_oop(value);
5188 bind(done);
5189 }
5190
5191 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
5192 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
5193 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
5194 // The inverted mask is sign-extended
5195 andptr(possibly_jweak, inverted_jweak_mask);
5196 }
5197
5198 //////////////////////////////////////////////////////////////////////////////////
5199 #if INCLUDE_ALL_GCS
5200
5201 void MacroAssembler::g1_write_barrier_pre(Register obj,
5202 Register pre_val,
5203 Register thread,
5204 Register tmp,
5205 bool tosca_live,
5206 bool expand_call) {
5207
5208 // If expand_call is true then we expand the call_VM_leaf macro
5209 // directly to skip generating the check by
5210 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp.
5211
5212 #ifdef _LP64
5213 assert(thread == r15_thread, "must be");
5214 #endif // _LP64
5215
5216 Label done;
5217 Label runtime;
5218
5219 assert(pre_val != noreg, "check this code");
5220
5221 if (obj != noreg) {
5222 assert_different_registers(obj, pre_val, tmp);
5223 assert(pre_val != rax, "check this code");
5224 }
5225
5226 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5227 SATBMarkQueue::byte_offset_of_active()));
5228 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5229 SATBMarkQueue::byte_offset_of_index()));
5230 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() +
5231 SATBMarkQueue::byte_offset_of_buf()));
5232
5233
5234 // Is marking active?
5235 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
5236 cmpl(in_progress, 0);
5237 } else {
5238 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
5239 cmpb(in_progress, 0);
5240 }
5241 jcc(Assembler::equal, done);
5242
5243 // Do we need to load the previous value?
5244 if (obj != noreg) {
5245 load_heap_oop(pre_val, Address(obj, 0));
5246 }
5247
5248 // Is the previous value null?
5249 cmpptr(pre_val, (int32_t) NULL_WORD);
5250 jcc(Assembler::equal, done);
5251
5252 // Can we store original value in the thread's buffer?
5253 // Is index == 0?
5254 // (The index field is typed as size_t.)
5255
5256 movptr(tmp, index); // tmp := *index_adr
5257 cmpptr(tmp, 0); // tmp == 0?
5258 jcc(Assembler::equal, runtime); // If yes, goto runtime
5259
5260 subptr(tmp, wordSize); // tmp := tmp - wordSize
5261 movptr(index, tmp); // *index_adr := tmp
5262 addptr(tmp, buffer); // tmp := tmp + *buffer_adr
5263
5264 // Record the previous value
5265 movptr(Address(tmp, 0), pre_val);
5266 jmp(done);
5267
5268 bind(runtime);
5269 // save the live input values
5270 if(tosca_live) push(rax);
5271
5272 if (obj != noreg && obj != rax)
5273 push(obj);
5274
5275 if (pre_val != rax)
5276 push(pre_val);
5277
5278 // Calling the runtime using the regular call_VM_leaf mechanism generates
5279 // code (generated by InterpreterMacroAssember::call_VM_leaf_base)
5280 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL.
5281 //
5282 // If we care generating the pre-barrier without a frame (e.g. in the
5283 // intrinsified Reference.get() routine) then ebp might be pointing to
5284 // the caller frame and so this check will most likely fail at runtime.
5285 //
5286 // Expanding the call directly bypasses the generation of the check.
5287 // So when we do not have have a full interpreter frame on the stack
5288 // expand_call should be passed true.
5289
5290 NOT_LP64( push(thread); )
5291
5292 if (expand_call) {
5293 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); )
5294 pass_arg1(this, thread);
5295 pass_arg0(this, pre_val);
5296 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2);
5297 } else {
5298 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread);
5299 }
5300
5301 NOT_LP64( pop(thread); )
5302
5303 // save the live input values
5304 if (pre_val != rax)
5305 pop(pre_val);
5306
5307 if (obj != noreg && obj != rax)
5308 pop(obj);
5309
5310 if(tosca_live) pop(rax);
5311
5312 bind(done);
5313 }
5314
5315 void MacroAssembler::g1_write_barrier_post(Register store_addr,
5316 Register new_val,
5317 Register thread,
5318 Register tmp,
5319 Register tmp2) {
5320 #ifdef _LP64
5321 assert(thread == r15_thread, "must be");
5322 #endif // _LP64
5323
5324 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5325 DirtyCardQueue::byte_offset_of_index()));
5326 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() +
5327 DirtyCardQueue::byte_offset_of_buf()));
5328
5329 CardTableModRefBS* ct =
5330 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set());
5331 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5332
5333 Label done;
5334 Label runtime;
5335
5336 // Does store cross heap regions?
5337
5338 movptr(tmp, store_addr);
5339 xorptr(tmp, new_val);
5340 shrptr(tmp, HeapRegion::LogOfHRGrainBytes);
5341 jcc(Assembler::equal, done);
5342
5343 // crosses regions, storing NULL?
5344
5345 cmpptr(new_val, (int32_t) NULL_WORD);
5346 jcc(Assembler::equal, done);
5347
5348 // storing region crossing non-NULL, is card already dirty?
5349
5350 const Register card_addr = tmp;
5351 const Register cardtable = tmp2;
5352
5353 movptr(card_addr, store_addr);
5354 shrptr(card_addr, CardTableModRefBS::card_shift);
5355 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT
5356 // a valid address and therefore is not properly handled by the relocation code.
5357 movptr(cardtable, (intptr_t)ct->byte_map_base);
5358 addptr(card_addr, cardtable);
5359
5360 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val());
5361 jcc(Assembler::equal, done);
5362
5363 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
5364 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5365 jcc(Assembler::equal, done);
5366
5367
5368 // storing a region crossing, non-NULL oop, card is clean.
5369 // dirty card and log.
5370
5371 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val());
5372
5373 cmpl(queue_index, 0);
5374 jcc(Assembler::equal, runtime);
5375 subl(queue_index, wordSize);
5376 movptr(tmp2, buffer);
5377 #ifdef _LP64
5378 movslq(rscratch1, queue_index);
5379 addq(tmp2, rscratch1);
5380 movq(Address(tmp2, 0), card_addr);
5381 #else
5382 addl(tmp2, queue_index);
5383 movl(Address(tmp2, 0), card_addr);
5384 #endif
5385 jmp(done);
5386
5387 bind(runtime);
5388 // save the live input values
5389 push(store_addr);
5390 push(new_val);
5391 #ifdef _LP64
5392 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread);
5393 #else
5394 push(thread);
5395 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread);
5396 pop(thread);
5397 #endif
5398 pop(new_val);
5399 pop(store_addr);
5400
5401 bind(done);
5402 }
5403
5404 #endif // INCLUDE_ALL_GCS
5405 //////////////////////////////////////////////////////////////////////////////////
5406
5407
5408 void MacroAssembler::store_check(Register obj, Address dst) {
5409 store_check(obj);
5410 }
5411
5412 void MacroAssembler::store_check(Register obj) {
5413 // Does a store check for the oop in register obj. The content of
5414 // register obj is destroyed afterwards.
5415 BarrierSet* bs = Universe::heap()->barrier_set();
5416 assert(bs->kind() == BarrierSet::CardTableForRS ||
5417 bs->kind() == BarrierSet::CardTableExtension,
5418 "Wrong barrier set kind");
5419
5420 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs);
5421 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code");
5422
5423 shrptr(obj, CardTableModRefBS::card_shift);
5424
5425 Address card_addr;
5426
5427 // The calculation for byte_map_base is as follows:
5428 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift);
5429 // So this essentially converts an address to a displacement and it will
5430 // never need to be relocated. On 64bit however the value may be too
5431 // large for a 32bit displacement.
5432 intptr_t disp = (intptr_t) ct->byte_map_base;
5433 if (is_simm32(disp)) {
5434 card_addr = Address(noreg, obj, Address::times_1, disp);
5435 } else {
5436 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative
5437 // displacement and done in a single instruction given favorable mapping and a
5438 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation
5439 // entry and that entry is not properly handled by the relocation code.
5440 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none);
5441 Address index(noreg, obj, Address::times_1);
5442 card_addr = as_Address(ArrayAddress(cardtable, index));
5443 }
5444
5445 int dirty = CardTableModRefBS::dirty_card_val();
5446 if (UseCondCardMark) {
5447 Label L_already_dirty;
5448 if (UseConcMarkSweepGC) {
5449 membar(Assembler::StoreLoad);
5450 }
5451 cmpb(card_addr, dirty);
5452 jcc(Assembler::equal, L_already_dirty);
5453 movb(card_addr, dirty);
5454 bind(L_already_dirty);
5455 } else {
5456 movb(card_addr, dirty);
5457 }
5458 }
5459
5460 void MacroAssembler::subptr(Register dst, int32_t imm32) {
5461 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
5462 }
5463
5464 // Force generation of a 4 byte immediate value even if it fits into 8bit
5465 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
5466 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
5467 }
5468
5469 void MacroAssembler::subptr(Register dst, Register src) {
5470 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
5471 }
5472
5473 // C++ bool manipulation
5474 void MacroAssembler::testbool(Register dst) {
5475 if(sizeof(bool) == 1)
5476 testb(dst, 0xff);
5477 else if(sizeof(bool) == 2) {
5478 // testw implementation needed for two byte bools
5479 ShouldNotReachHere();
5480 } else if(sizeof(bool) == 4)
5481 testl(dst, dst);
5482 else
5483 // unsupported
5484 ShouldNotReachHere();
5485 }
5486
5487 void MacroAssembler::testptr(Register dst, Register src) {
5488 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
5489 }
5490
5491 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5492 void MacroAssembler::tlab_allocate(Register obj,
5493 Register var_size_in_bytes,
5494 int con_size_in_bytes,
5495 Register t1,
5496 Register t2,
5497 Label& slow_case) {
5498 assert_different_registers(obj, t1, t2);
5499 assert_different_registers(obj, var_size_in_bytes, t1);
5500 Register end = t2;
5501 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread);
5502
5503 verify_tlab();
5504
5505 NOT_LP64(get_thread(thread));
5506
5507 movptr(obj, Address(thread, JavaThread::tlab_top_offset()));
5508 if (var_size_in_bytes == noreg) {
5509 lea(end, Address(obj, con_size_in_bytes));
5510 } else {
5511 lea(end, Address(obj, var_size_in_bytes, Address::times_1));
5512 }
5513 cmpptr(end, Address(thread, JavaThread::tlab_end_offset()));
5514 jcc(Assembler::above, slow_case);
5515
5516 // update the tlab top pointer
5517 movptr(Address(thread, JavaThread::tlab_top_offset()), end);
5518
5519 // recover var_size_in_bytes if necessary
5520 if (var_size_in_bytes == end) {
5521 subptr(var_size_in_bytes, obj);
5522 }
5523 verify_tlab();
5524 }
5525
5526 // Preserves rbx, and rdx.
5527 Register MacroAssembler::tlab_refill(Label& retry,
5528 Label& try_eden,
5529 Label& slow_case) {
5530 Register top = rax;
5531 Register t1 = rcx; // object size
5532 Register t2 = rsi;
5533 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread);
5534 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx);
5535 Label do_refill, discard_tlab;
5536
5537 if (!Universe::heap()->supports_inline_contig_alloc()) {
5538 // No allocation in the shared eden.
5539 jmp(slow_case);
5540 }
5541
5542 NOT_LP64(get_thread(thread_reg));
5543
5544 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5545 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5546
5547 // calculate amount of free space
5548 subptr(t1, top);
5549 shrptr(t1, LogHeapWordSize);
5550
5551 // Retain tlab and allocate object in shared space if
5552 // the amount free in the tlab is too large to discard.
5553 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())));
5554 jcc(Assembler::lessEqual, discard_tlab);
5555
5556 // Retain
5557 // %%% yuck as movptr...
5558 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment());
5559 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2);
5560 if (TLABStats) {
5561 // increment number of slow_allocations
5562 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1);
5563 }
5564 jmp(try_eden);
5565
5566 bind(discard_tlab);
5567 if (TLABStats) {
5568 // increment number of refills
5569 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1);
5570 // accumulate wastage -- t1 is amount free in tlab
5571 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1);
5572 }
5573
5574 // if tlab is currently allocated (top or end != null) then
5575 // fill [top, end + alignment_reserve) with array object
5576 testptr(top, top);
5577 jcc(Assembler::zero, do_refill);
5578
5579 // set up the mark word
5580 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2));
5581 // set the length to the remaining space
5582 subptr(t1, typeArrayOopDesc::header_size(T_INT));
5583 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve());
5584 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint)));
5585 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1);
5586 // set klass to intArrayKlass
5587 // dubious reloc why not an oop reloc?
5588 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr()));
5589 // store klass last. concurrent gcs assumes klass length is valid if
5590 // klass field is not null.
5591 store_klass(top, t1);
5592
5593 movptr(t1, top);
5594 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5595 incr_allocated_bytes(thread_reg, t1, 0);
5596
5597 // refill the tlab with an eden allocation
5598 bind(do_refill);
5599 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5600 shlptr(t1, LogHeapWordSize);
5601 // allocate new tlab, address returned in top
5602 eden_allocate(top, t1, 0, t2, slow_case);
5603
5604 // Check that t1 was preserved in eden_allocate.
5605 #ifdef ASSERT
5606 if (UseTLAB) {
5607 Label ok;
5608 Register tsize = rsi;
5609 assert_different_registers(tsize, thread_reg, t1);
5610 push(tsize);
5611 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset())));
5612 shlptr(tsize, LogHeapWordSize);
5613 cmpptr(t1, tsize);
5614 jcc(Assembler::equal, ok);
5615 STOP("assert(t1 != tlab size)");
5616 should_not_reach_here();
5617
5618 bind(ok);
5619 pop(tsize);
5620 }
5621 #endif
5622 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top);
5623 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top);
5624 addptr(top, t1);
5625 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes());
5626 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top);
5627
5628 if (ZeroTLAB) {
5629 // This is a fast TLAB refill, therefore the GC is not notified of it.
5630 // So compiled code must fill the new TLAB with zeroes.
5631 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5632 zero_memory(top, t1, 0, t2);
5633 }
5634
5635 verify_tlab();
5636 jmp(retry);
5637
5638 return thread_reg; // for use by caller
5639 }
5640
5641 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
5642 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
5643 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
5644 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
5645 Label done;
5646
5647 testptr(length_in_bytes, length_in_bytes);
5648 jcc(Assembler::zero, done);
5649
5650 // initialize topmost word, divide index by 2, check if odd and test if zero
5651 // note: for the remaining code to work, index must be a multiple of BytesPerWord
5652 #ifdef ASSERT
5653 {
5654 Label L;
5655 testptr(length_in_bytes, BytesPerWord - 1);
5656 jcc(Assembler::zero, L);
5657 stop("length must be a multiple of BytesPerWord");
5658 bind(L);
5659 }
5660 #endif
5661 Register index = length_in_bytes;
5662 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
5663 if (UseIncDec) {
5664 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
5665 } else {
5666 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
5667 shrptr(index, 1);
5668 }
5669 #ifndef _LP64
5670 // index could have not been a multiple of 8 (i.e., bit 2 was set)
5671 {
5672 Label even;
5673 // note: if index was a multiple of 8, then it cannot
5674 // be 0 now otherwise it must have been 0 before
5675 // => if it is even, we don't need to check for 0 again
5676 jcc(Assembler::carryClear, even);
5677 // clear topmost word (no jump would be needed if conditional assignment worked here)
5678 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
5679 // index could be 0 now, must check again
5680 jcc(Assembler::zero, done);
5681 bind(even);
5682 }
5683 #endif // !_LP64
5684 // initialize remaining object fields: index is a multiple of 2 now
5685 {
5686 Label loop;
5687 bind(loop);
5688 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
5689 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
5690 decrement(index);
5691 jcc(Assembler::notZero, loop);
5692 }
5693
5694 bind(done);
5695 }
5696
5697 void MacroAssembler::incr_allocated_bytes(Register thread,
5698 Register var_size_in_bytes,
5699 int con_size_in_bytes,
5700 Register t1) {
5701 if (!thread->is_valid()) {
5702 #ifdef _LP64
5703 thread = r15_thread;
5704 #else
5705 assert(t1->is_valid(), "need temp reg");
5706 thread = t1;
5707 get_thread(thread);
5708 #endif
5709 }
5710
5711 #ifdef _LP64
5712 if (var_size_in_bytes->is_valid()) {
5713 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5714 } else {
5715 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5716 }
5717 #else
5718 if (var_size_in_bytes->is_valid()) {
5719 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes);
5720 } else {
5721 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes);
5722 }
5723 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0);
5724 #endif
5725 }
5726
5727 // Look up the method for a megamorphic invokeinterface call.
5728 // The target method is determined by <intf_klass, itable_index>.
5729 // The receiver klass is in recv_klass.
5730 // On success, the result will be in method_result, and execution falls through.
5731 // On failure, execution transfers to the given label.
5732 void MacroAssembler::lookup_interface_method(Register recv_klass,
5733 Register intf_klass,
5734 RegisterOrConstant itable_index,
5735 Register method_result,
5736 Register scan_temp,
5737 Label& L_no_such_interface) {
5738 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp);
5739 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
5740 "caller must use same register for non-constant itable index as for method");
5741
5742 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
5743 int vtable_base = in_bytes(Klass::vtable_start_offset());
5744 int itentry_off = itableMethodEntry::method_offset_in_bytes();
5745 int scan_step = itableOffsetEntry::size() * wordSize;
5746 int vte_size = vtableEntry::size_in_bytes();
5747 Address::ScaleFactor times_vte_scale = Address::times_ptr;
5748 assert(vte_size == wordSize, "else adjust times_vte_scale");
5749
5750 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
5751
5752 // %%% Could store the aligned, prescaled offset in the klassoop.
5753 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
5754
5755 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
5756 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
5757 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
5758
5759 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
5760 // if (scan->interface() == intf) {
5761 // result = (klass + scan->offset() + itable_index);
5762 // }
5763 // }
5764 Label search, found_method;
5765
5766 for (int peel = 1; peel >= 0; peel--) {
5767 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
5768 cmpptr(intf_klass, method_result);
5769
5770 if (peel) {
5771 jccb(Assembler::equal, found_method);
5772 } else {
5773 jccb(Assembler::notEqual, search);
5774 // (invert the test to fall through to found_method...)
5775 }
5776
5777 if (!peel) break;
5778
5779 bind(search);
5780
5781 // Check that the previous entry is non-null. A null entry means that
5782 // the receiver class doesn't implement the interface, and wasn't the
5783 // same as when the caller was compiled.
5784 testptr(method_result, method_result);
5785 jcc(Assembler::zero, L_no_such_interface);
5786 addptr(scan_temp, scan_step);
5787 }
5788
5789 bind(found_method);
5790
5791 // Got a hit.
5792 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
5793 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
5794 }
5795
5796
5797 // virtual method calling
5798 void MacroAssembler::lookup_virtual_method(Register recv_klass,
5799 RegisterOrConstant vtable_index,
5800 Register method_result) {
5801 const int base = in_bytes(Klass::vtable_start_offset());
5802 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
5803 Address vtable_entry_addr(recv_klass,
5804 vtable_index, Address::times_ptr,
5805 base + vtableEntry::method_offset_in_bytes());
5806 movptr(method_result, vtable_entry_addr);
5807 }
5808
5809
5810 void MacroAssembler::check_klass_subtype(Register sub_klass,
5811 Register super_klass,
5812 Register temp_reg,
5813 Label& L_success) {
5814 Label L_failure;
5815 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL);
5816 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
5817 bind(L_failure);
5818 }
5819
5820
5821 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
5822 Register super_klass,
5823 Register temp_reg,
5824 Label* L_success,
5825 Label* L_failure,
5826 Label* L_slow_path,
5827 RegisterOrConstant super_check_offset) {
5828 assert_different_registers(sub_klass, super_klass, temp_reg);
5829 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
5830 if (super_check_offset.is_register()) {
5831 assert_different_registers(sub_klass, super_klass,
5832 super_check_offset.as_register());
5833 } else if (must_load_sco) {
5834 assert(temp_reg != noreg, "supply either a temp or a register offset");
5835 }
5836
5837 Label L_fallthrough;
5838 int label_nulls = 0;
5839 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5840 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5841 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
5842 assert(label_nulls <= 1, "at most one NULL in the batch");
5843
5844 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5845 int sco_offset = in_bytes(Klass::super_check_offset_offset());
5846 Address super_check_offset_addr(super_klass, sco_offset);
5847
5848 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
5849 // range of a jccb. If this routine grows larger, reconsider at
5850 // least some of these.
5851 #define local_jcc(assembler_cond, label) \
5852 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
5853 else jcc( assembler_cond, label) /*omit semi*/
5854
5855 // Hacked jmp, which may only be used just before L_fallthrough.
5856 #define final_jmp(label) \
5857 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
5858 else jmp(label) /*omit semi*/
5859
5860 // If the pointers are equal, we are done (e.g., String[] elements).
5861 // This self-check enables sharing of secondary supertype arrays among
5862 // non-primary types such as array-of-interface. Otherwise, each such
5863 // type would need its own customized SSA.
5864 // We move this check to the front of the fast path because many
5865 // type checks are in fact trivially successful in this manner,
5866 // so we get a nicely predicted branch right at the start of the check.
5867 cmpptr(sub_klass, super_klass);
5868 local_jcc(Assembler::equal, *L_success);
5869
5870 // Check the supertype display:
5871 if (must_load_sco) {
5872 // Positive movl does right thing on LP64.
5873 movl(temp_reg, super_check_offset_addr);
5874 super_check_offset = RegisterOrConstant(temp_reg);
5875 }
5876 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
5877 cmpptr(super_klass, super_check_addr); // load displayed supertype
5878
5879 // This check has worked decisively for primary supers.
5880 // Secondary supers are sought in the super_cache ('super_cache_addr').
5881 // (Secondary supers are interfaces and very deeply nested subtypes.)
5882 // This works in the same check above because of a tricky aliasing
5883 // between the super_cache and the primary super display elements.
5884 // (The 'super_check_addr' can address either, as the case requires.)
5885 // Note that the cache is updated below if it does not help us find
5886 // what we need immediately.
5887 // So if it was a primary super, we can just fail immediately.
5888 // Otherwise, it's the slow path for us (no success at this point).
5889
5890 if (super_check_offset.is_register()) {
5891 local_jcc(Assembler::equal, *L_success);
5892 cmpl(super_check_offset.as_register(), sc_offset);
5893 if (L_failure == &L_fallthrough) {
5894 local_jcc(Assembler::equal, *L_slow_path);
5895 } else {
5896 local_jcc(Assembler::notEqual, *L_failure);
5897 final_jmp(*L_slow_path);
5898 }
5899 } else if (super_check_offset.as_constant() == sc_offset) {
5900 // Need a slow path; fast failure is impossible.
5901 if (L_slow_path == &L_fallthrough) {
5902 local_jcc(Assembler::equal, *L_success);
5903 } else {
5904 local_jcc(Assembler::notEqual, *L_slow_path);
5905 final_jmp(*L_success);
5906 }
5907 } else {
5908 // No slow path; it's a fast decision.
5909 if (L_failure == &L_fallthrough) {
5910 local_jcc(Assembler::equal, *L_success);
5911 } else {
5912 local_jcc(Assembler::notEqual, *L_failure);
5913 final_jmp(*L_success);
5914 }
5915 }
5916
5917 bind(L_fallthrough);
5918
5919 #undef local_jcc
5920 #undef final_jmp
5921 }
5922
5923
5924 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
5925 Register super_klass,
5926 Register temp_reg,
5927 Register temp2_reg,
5928 Label* L_success,
5929 Label* L_failure,
5930 bool set_cond_codes) {
5931 assert_different_registers(sub_klass, super_klass, temp_reg);
5932 if (temp2_reg != noreg)
5933 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
5934 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
5935
5936 Label L_fallthrough;
5937 int label_nulls = 0;
5938 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
5939 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
5940 assert(label_nulls <= 1, "at most one NULL in the batch");
5941
5942 // a couple of useful fields in sub_klass:
5943 int ss_offset = in_bytes(Klass::secondary_supers_offset());
5944 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
5945 Address secondary_supers_addr(sub_klass, ss_offset);
5946 Address super_cache_addr( sub_klass, sc_offset);
5947
5948 // Do a linear scan of the secondary super-klass chain.
5949 // This code is rarely used, so simplicity is a virtue here.
5950 // The repne_scan instruction uses fixed registers, which we must spill.
5951 // Don't worry too much about pre-existing connections with the input regs.
5952
5953 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
5954 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
5955
5956 // Get super_klass value into rax (even if it was in rdi or rcx).
5957 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
5958 if (super_klass != rax || UseCompressedOops) {
5959 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5960 mov(rax, super_klass);
5961 }
5962 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5963 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5964
5965 #ifndef PRODUCT
5966 int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5967 ExternalAddress pst_counter_addr((address) pst_counter);
5968 NOT_LP64( incrementl(pst_counter_addr) );
5969 LP64_ONLY( lea(rcx, pst_counter_addr) );
5970 LP64_ONLY( incrementl(Address(rcx, 0)) );
5971 #endif //PRODUCT
5972
5973 // We will consult the secondary-super array.
5974 movptr(rdi, secondary_supers_addr);
5975 // Load the array length. (Positive movl does right thing on LP64.)
5976 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5977 // Skip to start of data.
5978 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5979
5980 // Scan RCX words at [RDI] for an occurrence of RAX.
5981 // Set NZ/Z based on last compare.
5982 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5983 // not change flags (only scas instruction which is repeated sets flags).
5984 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5985
5986 testptr(rax,rax); // Set Z = 0
5987 repne_scan();
5988
5989 // Unspill the temp. registers:
5990 if (pushed_rdi) pop(rdi);
5991 if (pushed_rcx) pop(rcx);
5992 if (pushed_rax) pop(rax);
5993
5994 if (set_cond_codes) {
5995 // Special hack for the AD files: rdi is guaranteed non-zero.
5996 assert(!pushed_rdi, "rdi must be left non-NULL");
5997 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5998 }
5999
6000 if (L_failure == &L_fallthrough)
6001 jccb(Assembler::notEqual, *L_failure);
6002 else jcc(Assembler::notEqual, *L_failure);
6003
6004 // Success. Cache the super we found and proceed in triumph.
6005 movptr(super_cache_addr, super_klass);
6006
6007 if (L_success != &L_fallthrough) {
6008 jmp(*L_success);
6009 }
6010
6011 #undef IS_A_TEMP
6012
6013 bind(L_fallthrough);
6014 }
6015
6016
6017 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
6018 if (VM_Version::supports_cmov()) {
6019 cmovl(cc, dst, src);
6020 } else {
6021 Label L;
6022 jccb(negate_condition(cc), L);
6023 movl(dst, src);
6024 bind(L);
6025 }
6026 }
6027
6028 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
6029 if (VM_Version::supports_cmov()) {
6030 cmovl(cc, dst, src);
6031 } else {
6032 Label L;
6033 jccb(negate_condition(cc), L);
6034 movl(dst, src);
6035 bind(L);
6036 }
6037 }
6038
6039 void MacroAssembler::verify_oop(Register reg, const char* s) {
6040 if (!VerifyOops) return;
6041
6042 // Pass register number to verify_oop_subroutine
6043 const char* b = NULL;
6044 {
6045 ResourceMark rm;
6046 stringStream ss;
6047 ss.print("verify_oop: %s: %s", reg->name(), s);
6048 b = code_string(ss.as_string());
6049 }
6050 BLOCK_COMMENT("verify_oop {");
6051 #ifdef _LP64
6052 push(rscratch1); // save r10, trashed by movptr()
6053 #endif
6054 push(rax); // save rax,
6055 push(reg); // pass register argument
6056 ExternalAddress buffer((address) b);
6057 // avoid using pushptr, as it modifies scratch registers
6058 // and our contract is not to modify anything
6059 movptr(rax, buffer.addr());
6060 push(rax);
6061 // call indirectly to solve generation ordering problem
6062 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6063 call(rax);
6064 // Caller pops the arguments (oop, message) and restores rax, r10
6065 BLOCK_COMMENT("} verify_oop");
6066 }
6067
6068
6069 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
6070 Register tmp,
6071 int offset) {
6072 intptr_t value = *delayed_value_addr;
6073 if (value != 0)
6074 return RegisterOrConstant(value + offset);
6075
6076 // load indirectly to solve generation ordering problem
6077 movptr(tmp, ExternalAddress((address) delayed_value_addr));
6078
6079 #ifdef ASSERT
6080 { Label L;
6081 testptr(tmp, tmp);
6082 if (WizardMode) {
6083 const char* buf = NULL;
6084 {
6085 ResourceMark rm;
6086 stringStream ss;
6087 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]);
6088 buf = code_string(ss.as_string());
6089 }
6090 jcc(Assembler::notZero, L);
6091 STOP(buf);
6092 } else {
6093 jccb(Assembler::notZero, L);
6094 hlt();
6095 }
6096 bind(L);
6097 }
6098 #endif
6099
6100 if (offset != 0)
6101 addptr(tmp, offset);
6102
6103 return RegisterOrConstant(tmp);
6104 }
6105
6106
6107 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
6108 int extra_slot_offset) {
6109 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
6110 int stackElementSize = Interpreter::stackElementSize;
6111 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
6112 #ifdef ASSERT
6113 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
6114 assert(offset1 - offset == stackElementSize, "correct arithmetic");
6115 #endif
6116 Register scale_reg = noreg;
6117 Address::ScaleFactor scale_factor = Address::no_scale;
6118 if (arg_slot.is_constant()) {
6119 offset += arg_slot.as_constant() * stackElementSize;
6120 } else {
6121 scale_reg = arg_slot.as_register();
6122 scale_factor = Address::times(stackElementSize);
6123 }
6124 offset += wordSize; // return PC is on stack
6125 return Address(rsp, scale_reg, scale_factor, offset);
6126 }
6127
6128
6129 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
6130 if (!VerifyOops) return;
6131
6132 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
6133 // Pass register number to verify_oop_subroutine
6134 const char* b = NULL;
6135 {
6136 ResourceMark rm;
6137 stringStream ss;
6138 ss.print("verify_oop_addr: %s", s);
6139 b = code_string(ss.as_string());
6140 }
6141 #ifdef _LP64
6142 push(rscratch1); // save r10, trashed by movptr()
6143 #endif
6144 push(rax); // save rax,
6145 // addr may contain rsp so we will have to adjust it based on the push
6146 // we just did (and on 64 bit we do two pushes)
6147 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
6148 // stores rax into addr which is backwards of what was intended.
6149 if (addr.uses(rsp)) {
6150 lea(rax, addr);
6151 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
6152 } else {
6153 pushptr(addr);
6154 }
6155
6156 ExternalAddress buffer((address) b);
6157 // pass msg argument
6158 // avoid using pushptr, as it modifies scratch registers
6159 // and our contract is not to modify anything
6160 movptr(rax, buffer.addr());
6161 push(rax);
6162
6163 // call indirectly to solve generation ordering problem
6164 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
6165 call(rax);
6166 // Caller pops the arguments (addr, message) and restores rax, r10.
6167 }
6168
6169 void MacroAssembler::verify_tlab() {
6170 #ifdef ASSERT
6171 if (UseTLAB && VerifyOops) {
6172 Label next, ok;
6173 Register t1 = rsi;
6174 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
6175
6176 push(t1);
6177 NOT_LP64(push(thread_reg));
6178 NOT_LP64(get_thread(thread_reg));
6179
6180 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6181 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
6182 jcc(Assembler::aboveEqual, next);
6183 STOP("assert(top >= start)");
6184 should_not_reach_here();
6185
6186 bind(next);
6187 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
6188 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
6189 jcc(Assembler::aboveEqual, ok);
6190 STOP("assert(top <= end)");
6191 should_not_reach_here();
6192
6193 bind(ok);
6194 NOT_LP64(pop(thread_reg));
6195 pop(t1);
6196 }
6197 #endif
6198 }
6199
6200 class ControlWord {
6201 public:
6202 int32_t _value;
6203
6204 int rounding_control() const { return (_value >> 10) & 3 ; }
6205 int precision_control() const { return (_value >> 8) & 3 ; }
6206 bool precision() const { return ((_value >> 5) & 1) != 0; }
6207 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6208 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6209 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6210 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6211 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6212
6213 void print() const {
6214 // rounding control
6215 const char* rc;
6216 switch (rounding_control()) {
6217 case 0: rc = "round near"; break;
6218 case 1: rc = "round down"; break;
6219 case 2: rc = "round up "; break;
6220 case 3: rc = "chop "; break;
6221 };
6222 // precision control
6223 const char* pc;
6224 switch (precision_control()) {
6225 case 0: pc = "24 bits "; break;
6226 case 1: pc = "reserved"; break;
6227 case 2: pc = "53 bits "; break;
6228 case 3: pc = "64 bits "; break;
6229 };
6230 // flags
6231 char f[9];
6232 f[0] = ' ';
6233 f[1] = ' ';
6234 f[2] = (precision ()) ? 'P' : 'p';
6235 f[3] = (underflow ()) ? 'U' : 'u';
6236 f[4] = (overflow ()) ? 'O' : 'o';
6237 f[5] = (zero_divide ()) ? 'Z' : 'z';
6238 f[6] = (denormalized()) ? 'D' : 'd';
6239 f[7] = (invalid ()) ? 'I' : 'i';
6240 f[8] = '\x0';
6241 // output
6242 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
6243 }
6244
6245 };
6246
6247 class StatusWord {
6248 public:
6249 int32_t _value;
6250
6251 bool busy() const { return ((_value >> 15) & 1) != 0; }
6252 bool C3() const { return ((_value >> 14) & 1) != 0; }
6253 bool C2() const { return ((_value >> 10) & 1) != 0; }
6254 bool C1() const { return ((_value >> 9) & 1) != 0; }
6255 bool C0() const { return ((_value >> 8) & 1) != 0; }
6256 int top() const { return (_value >> 11) & 7 ; }
6257 bool error_status() const { return ((_value >> 7) & 1) != 0; }
6258 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
6259 bool precision() const { return ((_value >> 5) & 1) != 0; }
6260 bool underflow() const { return ((_value >> 4) & 1) != 0; }
6261 bool overflow() const { return ((_value >> 3) & 1) != 0; }
6262 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
6263 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
6264 bool invalid() const { return ((_value >> 0) & 1) != 0; }
6265
6266 void print() const {
6267 // condition codes
6268 char c[5];
6269 c[0] = (C3()) ? '3' : '-';
6270 c[1] = (C2()) ? '2' : '-';
6271 c[2] = (C1()) ? '1' : '-';
6272 c[3] = (C0()) ? '0' : '-';
6273 c[4] = '\x0';
6274 // flags
6275 char f[9];
6276 f[0] = (error_status()) ? 'E' : '-';
6277 f[1] = (stack_fault ()) ? 'S' : '-';
6278 f[2] = (precision ()) ? 'P' : '-';
6279 f[3] = (underflow ()) ? 'U' : '-';
6280 f[4] = (overflow ()) ? 'O' : '-';
6281 f[5] = (zero_divide ()) ? 'Z' : '-';
6282 f[6] = (denormalized()) ? 'D' : '-';
6283 f[7] = (invalid ()) ? 'I' : '-';
6284 f[8] = '\x0';
6285 // output
6286 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
6287 }
6288
6289 };
6290
6291 class TagWord {
6292 public:
6293 int32_t _value;
6294
6295 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
6296
6297 void print() const {
6298 printf("%04x", _value & 0xFFFF);
6299 }
6300
6301 };
6302
6303 class FPU_Register {
6304 public:
6305 int32_t _m0;
6306 int32_t _m1;
6307 int16_t _ex;
6308
6309 bool is_indefinite() const {
6310 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
6311 }
6312
6313 void print() const {
6314 char sign = (_ex < 0) ? '-' : '+';
6315 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
6316 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
6317 };
6318
6319 };
6320
6321 class FPU_State {
6322 public:
6323 enum {
6324 register_size = 10,
6325 number_of_registers = 8,
6326 register_mask = 7
6327 };
6328
6329 ControlWord _control_word;
6330 StatusWord _status_word;
6331 TagWord _tag_word;
6332 int32_t _error_offset;
6333 int32_t _error_selector;
6334 int32_t _data_offset;
6335 int32_t _data_selector;
6336 int8_t _register[register_size * number_of_registers];
6337
6338 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
6339 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
6340
6341 const char* tag_as_string(int tag) const {
6342 switch (tag) {
6343 case 0: return "valid";
6344 case 1: return "zero";
6345 case 2: return "special";
6346 case 3: return "empty";
6347 }
6348 ShouldNotReachHere();
6349 return NULL;
6350 }
6351
6352 void print() const {
6353 // print computation registers
6354 { int t = _status_word.top();
6355 for (int i = 0; i < number_of_registers; i++) {
6356 int j = (i - t) & register_mask;
6357 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
6358 st(j)->print();
6359 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
6360 }
6361 }
6362 printf("\n");
6363 // print control registers
6364 printf("ctrl = "); _control_word.print(); printf("\n");
6365 printf("stat = "); _status_word .print(); printf("\n");
6366 printf("tags = "); _tag_word .print(); printf("\n");
6367 }
6368
6369 };
6370
6371 class Flag_Register {
6372 public:
6373 int32_t _value;
6374
6375 bool overflow() const { return ((_value >> 11) & 1) != 0; }
6376 bool direction() const { return ((_value >> 10) & 1) != 0; }
6377 bool sign() const { return ((_value >> 7) & 1) != 0; }
6378 bool zero() const { return ((_value >> 6) & 1) != 0; }
6379 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
6380 bool parity() const { return ((_value >> 2) & 1) != 0; }
6381 bool carry() const { return ((_value >> 0) & 1) != 0; }
6382
6383 void print() const {
6384 // flags
6385 char f[8];
6386 f[0] = (overflow ()) ? 'O' : '-';
6387 f[1] = (direction ()) ? 'D' : '-';
6388 f[2] = (sign ()) ? 'S' : '-';
6389 f[3] = (zero ()) ? 'Z' : '-';
6390 f[4] = (auxiliary_carry()) ? 'A' : '-';
6391 f[5] = (parity ()) ? 'P' : '-';
6392 f[6] = (carry ()) ? 'C' : '-';
6393 f[7] = '\x0';
6394 // output
6395 printf("%08x flags = %s", _value, f);
6396 }
6397
6398 };
6399
6400 class IU_Register {
6401 public:
6402 int32_t _value;
6403
6404 void print() const {
6405 printf("%08x %11d", _value, _value);
6406 }
6407
6408 };
6409
6410 class IU_State {
6411 public:
6412 Flag_Register _eflags;
6413 IU_Register _rdi;
6414 IU_Register _rsi;
6415 IU_Register _rbp;
6416 IU_Register _rsp;
6417 IU_Register _rbx;
6418 IU_Register _rdx;
6419 IU_Register _rcx;
6420 IU_Register _rax;
6421
6422 void print() const {
6423 // computation registers
6424 printf("rax, = "); _rax.print(); printf("\n");
6425 printf("rbx, = "); _rbx.print(); printf("\n");
6426 printf("rcx = "); _rcx.print(); printf("\n");
6427 printf("rdx = "); _rdx.print(); printf("\n");
6428 printf("rdi = "); _rdi.print(); printf("\n");
6429 printf("rsi = "); _rsi.print(); printf("\n");
6430 printf("rbp, = "); _rbp.print(); printf("\n");
6431 printf("rsp = "); _rsp.print(); printf("\n");
6432 printf("\n");
6433 // control registers
6434 printf("flgs = "); _eflags.print(); printf("\n");
6435 }
6436 };
6437
6438
6439 class CPU_State {
6440 public:
6441 FPU_State _fpu_state;
6442 IU_State _iu_state;
6443
6444 void print() const {
6445 printf("--------------------------------------------------\n");
6446 _iu_state .print();
6447 printf("\n");
6448 _fpu_state.print();
6449 printf("--------------------------------------------------\n");
6450 }
6451
6452 };
6453
6454
6455 static void _print_CPU_state(CPU_State* state) {
6456 state->print();
6457 };
6458
6459
6460 void MacroAssembler::print_CPU_state() {
6461 push_CPU_state();
6462 push(rsp); // pass CPU state
6463 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
6464 addptr(rsp, wordSize); // discard argument
6465 pop_CPU_state();
6466 }
6467
6468
6469 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
6470 static int counter = 0;
6471 FPU_State* fs = &state->_fpu_state;
6472 counter++;
6473 // For leaf calls, only verify that the top few elements remain empty.
6474 // We only need 1 empty at the top for C2 code.
6475 if( stack_depth < 0 ) {
6476 if( fs->tag_for_st(7) != 3 ) {
6477 printf("FPR7 not empty\n");
6478 state->print();
6479 assert(false, "error");
6480 return false;
6481 }
6482 return true; // All other stack states do not matter
6483 }
6484
6485 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std,
6486 "bad FPU control word");
6487
6488 // compute stack depth
6489 int i = 0;
6490 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
6491 int d = i;
6492 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
6493 // verify findings
6494 if (i != FPU_State::number_of_registers) {
6495 // stack not contiguous
6496 printf("%s: stack not contiguous at ST%d\n", s, i);
6497 state->print();
6498 assert(false, "error");
6499 return false;
6500 }
6501 // check if computed stack depth corresponds to expected stack depth
6502 if (stack_depth < 0) {
6503 // expected stack depth is -stack_depth or less
6504 if (d > -stack_depth) {
6505 // too many elements on the stack
6506 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
6507 state->print();
6508 assert(false, "error");
6509 return false;
6510 }
6511 } else {
6512 // expected stack depth is stack_depth
6513 if (d != stack_depth) {
6514 // wrong stack depth
6515 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
6516 state->print();
6517 assert(false, "error");
6518 return false;
6519 }
6520 }
6521 // everything is cool
6522 return true;
6523 }
6524
6525
6526 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
6527 if (!VerifyFPU) return;
6528 push_CPU_state();
6529 push(rsp); // pass CPU state
6530 ExternalAddress msg((address) s);
6531 // pass message string s
6532 pushptr(msg.addr());
6533 push(stack_depth); // pass stack depth
6534 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
6535 addptr(rsp, 3 * wordSize); // discard arguments
6536 // check for error
6537 { Label L;
6538 testl(rax, rax);
6539 jcc(Assembler::notZero, L);
6540 int3(); // break if error condition
6541 bind(L);
6542 }
6543 pop_CPU_state();
6544 }
6545
6546 void MacroAssembler::restore_cpu_control_state_after_jni() {
6547 // Either restore the MXCSR register after returning from the JNI Call
6548 // or verify that it wasn't changed (with -Xcheck:jni flag).
6549 if (VM_Version::supports_sse()) {
6550 if (RestoreMXCSROnJNICalls) {
6551 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std()));
6552 } else if (CheckJNICalls) {
6553 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6554 }
6555 }
6556 if (VM_Version::supports_avx()) {
6557 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6558 vzeroupper();
6559 }
6560
6561 #ifndef _LP64
6562 // Either restore the x87 floating pointer control word after returning
6563 // from the JNI call or verify that it wasn't changed.
6564 if (CheckJNICalls) {
6565 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6566 }
6567 #endif // _LP64
6568 }
6569
6570 void MacroAssembler::load_mirror(Register mirror, Register method) {
6571 // get mirror
6572 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6573 movptr(mirror, Address(method, Method::const_offset()));
6574 movptr(mirror, Address(mirror, ConstMethod::constants_offset()));
6575 movptr(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
6576 movptr(mirror, Address(mirror, mirror_offset));
6577 }
6578
6579 void MacroAssembler::load_klass(Register dst, Register src) {
6580 #ifdef _LP64
6581 if (UseCompressedClassPointers) {
6582 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6583 decode_klass_not_null(dst);
6584 } else
6585 #endif
6586 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6587 }
6588
6589 void MacroAssembler::load_prototype_header(Register dst, Register src) {
6590 load_klass(dst, src);
6591 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6592 }
6593
6594 void MacroAssembler::store_klass(Register dst, Register src) {
6595 #ifdef _LP64
6596 if (UseCompressedClassPointers) {
6597 encode_klass_not_null(src);
6598 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6599 } else
6600 #endif
6601 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6602 }
6603
6604 void MacroAssembler::load_heap_oop(Register dst, Address src) {
6605 #ifdef _LP64
6606 // FIXME: Must change all places where we try to load the klass.
6607 if (UseCompressedOops) {
6608 movl(dst, src);
6609 decode_heap_oop(dst);
6610 } else
6611 #endif
6612 movptr(dst, src);
6613 }
6614
6615 // Doesn't do verfication, generates fixed size code
6616 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) {
6617 #ifdef _LP64
6618 if (UseCompressedOops) {
6619 movl(dst, src);
6620 decode_heap_oop_not_null(dst);
6621 } else
6622 #endif
6623 movptr(dst, src);
6624 }
6625
6626 void MacroAssembler::store_heap_oop(Address dst, Register src) {
6627 #ifdef _LP64
6628 if (UseCompressedOops) {
6629 assert(!dst.uses(src), "not enough registers");
6630 encode_heap_oop(src);
6631 movl(dst, src);
6632 } else
6633 #endif
6634 movptr(dst, src);
6635 }
6636
6637 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) {
6638 assert_different_registers(src1, tmp);
6639 #ifdef _LP64
6640 if (UseCompressedOops) {
6641 bool did_push = false;
6642 if (tmp == noreg) {
6643 tmp = rax;
6644 push(tmp);
6645 did_push = true;
6646 assert(!src2.uses(rsp), "can't push");
6647 }
6648 load_heap_oop(tmp, src2);
6649 cmpptr(src1, tmp);
6650 if (did_push) pop(tmp);
6651 } else
6652 #endif
6653 cmpptr(src1, src2);
6654 }
6655
6656 // Used for storing NULLs.
6657 void MacroAssembler::store_heap_oop_null(Address dst) {
6658 #ifdef _LP64
6659 if (UseCompressedOops) {
6660 movl(dst, (int32_t)NULL_WORD);
6661 } else {
6662 movslq(dst, (int32_t)NULL_WORD);
6663 }
6664 #else
6665 movl(dst, (int32_t)NULL_WORD);
6666 #endif
6667 }
6668
6669 #ifdef _LP64
6670 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6671 if (UseCompressedClassPointers) {
6672 // Store to klass gap in destination
6673 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6674 }
6675 }
6676
6677 #ifdef ASSERT
6678 void MacroAssembler::verify_heapbase(const char* msg) {
6679 assert (UseCompressedOops, "should be compressed");
6680 assert (Universe::heap() != NULL, "java heap should be initialized");
6681 if (CheckCompressedOops) {
6682 Label ok;
6683 push(rscratch1); // cmpptr trashes rscratch1
6684 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6685 jcc(Assembler::equal, ok);
6686 STOP(msg);
6687 bind(ok);
6688 pop(rscratch1);
6689 }
6690 }
6691 #endif
6692
6693 // Algorithm must match oop.inline.hpp encode_heap_oop.
6694 void MacroAssembler::encode_heap_oop(Register r) {
6695 #ifdef ASSERT
6696 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6697 #endif
6698 verify_oop(r, "broken oop in encode_heap_oop");
6699 if (Universe::narrow_oop_base() == NULL) {
6700 if (Universe::narrow_oop_shift() != 0) {
6701 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6702 shrq(r, LogMinObjAlignmentInBytes);
6703 }
6704 return;
6705 }
6706 testq(r, r);
6707 cmovq(Assembler::equal, r, r12_heapbase);
6708 subq(r, r12_heapbase);
6709 shrq(r, LogMinObjAlignmentInBytes);
6710 }
6711
6712 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6713 #ifdef ASSERT
6714 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6715 if (CheckCompressedOops) {
6716 Label ok;
6717 testq(r, r);
6718 jcc(Assembler::notEqual, ok);
6719 STOP("null oop passed to encode_heap_oop_not_null");
6720 bind(ok);
6721 }
6722 #endif
6723 verify_oop(r, "broken oop in encode_heap_oop_not_null");
6724 if (Universe::narrow_oop_base() != NULL) {
6725 subq(r, r12_heapbase);
6726 }
6727 if (Universe::narrow_oop_shift() != 0) {
6728 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6729 shrq(r, LogMinObjAlignmentInBytes);
6730 }
6731 }
6732
6733 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6734 #ifdef ASSERT
6735 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6736 if (CheckCompressedOops) {
6737 Label ok;
6738 testq(src, src);
6739 jcc(Assembler::notEqual, ok);
6740 STOP("null oop passed to encode_heap_oop_not_null2");
6741 bind(ok);
6742 }
6743 #endif
6744 verify_oop(src, "broken oop in encode_heap_oop_not_null2");
6745 if (dst != src) {
6746 movq(dst, src);
6747 }
6748 if (Universe::narrow_oop_base() != NULL) {
6749 subq(dst, r12_heapbase);
6750 }
6751 if (Universe::narrow_oop_shift() != 0) {
6752 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6753 shrq(dst, LogMinObjAlignmentInBytes);
6754 }
6755 }
6756
6757 void MacroAssembler::decode_heap_oop(Register r) {
6758 #ifdef ASSERT
6759 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6760 #endif
6761 if (Universe::narrow_oop_base() == NULL) {
6762 if (Universe::narrow_oop_shift() != 0) {
6763 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6764 shlq(r, LogMinObjAlignmentInBytes);
6765 }
6766 } else {
6767 Label done;
6768 shlq(r, LogMinObjAlignmentInBytes);
6769 jccb(Assembler::equal, done);
6770 addq(r, r12_heapbase);
6771 bind(done);
6772 }
6773 verify_oop(r, "broken oop in decode_heap_oop");
6774 }
6775
6776 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6777 // Note: it will change flags
6778 assert (UseCompressedOops, "should only be used for compressed headers");
6779 assert (Universe::heap() != NULL, "java heap should be initialized");
6780 // Cannot assert, unverified entry point counts instructions (see .ad file)
6781 // vtableStubs also counts instructions in pd_code_size_limit.
6782 // Also do not verify_oop as this is called by verify_oop.
6783 if (Universe::narrow_oop_shift() != 0) {
6784 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6785 shlq(r, LogMinObjAlignmentInBytes);
6786 if (Universe::narrow_oop_base() != NULL) {
6787 addq(r, r12_heapbase);
6788 }
6789 } else {
6790 assert (Universe::narrow_oop_base() == NULL, "sanity");
6791 }
6792 }
6793
6794 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6795 // Note: it will change flags
6796 assert (UseCompressedOops, "should only be used for compressed headers");
6797 assert (Universe::heap() != NULL, "java heap should be initialized");
6798 // Cannot assert, unverified entry point counts instructions (see .ad file)
6799 // vtableStubs also counts instructions in pd_code_size_limit.
6800 // Also do not verify_oop as this is called by verify_oop.
6801 if (Universe::narrow_oop_shift() != 0) {
6802 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong");
6803 if (LogMinObjAlignmentInBytes == Address::times_8) {
6804 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6805 } else {
6806 if (dst != src) {
6807 movq(dst, src);
6808 }
6809 shlq(dst, LogMinObjAlignmentInBytes);
6810 if (Universe::narrow_oop_base() != NULL) {
6811 addq(dst, r12_heapbase);
6812 }
6813 }
6814 } else {
6815 assert (Universe::narrow_oop_base() == NULL, "sanity");
6816 if (dst != src) {
6817 movq(dst, src);
6818 }
6819 }
6820 }
6821
6822 void MacroAssembler::encode_klass_not_null(Register r) {
6823 if (Universe::narrow_klass_base() != NULL) {
6824 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6825 assert(r != r12_heapbase, "Encoding a klass in r12");
6826 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6827 subq(r, r12_heapbase);
6828 }
6829 if (Universe::narrow_klass_shift() != 0) {
6830 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6831 shrq(r, LogKlassAlignmentInBytes);
6832 }
6833 if (Universe::narrow_klass_base() != NULL) {
6834 reinit_heapbase();
6835 }
6836 }
6837
6838 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
6839 if (dst == src) {
6840 encode_klass_not_null(src);
6841 } else {
6842 if (Universe::narrow_klass_base() != NULL) {
6843 mov64(dst, (int64_t)Universe::narrow_klass_base());
6844 negq(dst);
6845 addq(dst, src);
6846 } else {
6847 movptr(dst, src);
6848 }
6849 if (Universe::narrow_klass_shift() != 0) {
6850 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6851 shrq(dst, LogKlassAlignmentInBytes);
6852 }
6853 }
6854 }
6855
6856 // Function instr_size_for_decode_klass_not_null() counts the instructions
6857 // generated by decode_klass_not_null(register r) and reinit_heapbase(),
6858 // when (Universe::heap() != NULL). Hence, if the instructions they
6859 // generate change, then this method needs to be updated.
6860 int MacroAssembler::instr_size_for_decode_klass_not_null() {
6861 assert (UseCompressedClassPointers, "only for compressed klass ptrs");
6862 if (Universe::narrow_klass_base() != NULL) {
6863 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()).
6864 return (Universe::narrow_klass_shift() == 0 ? 20 : 24);
6865 } else {
6866 // longest load decode klass function, mov64, leaq
6867 return 16;
6868 }
6869 }
6870
6871 // !!! If the instructions that get generated here change then function
6872 // instr_size_for_decode_klass_not_null() needs to get updated.
6873 void MacroAssembler::decode_klass_not_null(Register r) {
6874 // Note: it will change flags
6875 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6876 assert(r != r12_heapbase, "Decoding a klass in r12");
6877 // Cannot assert, unverified entry point counts instructions (see .ad file)
6878 // vtableStubs also counts instructions in pd_code_size_limit.
6879 // Also do not verify_oop as this is called by verify_oop.
6880 if (Universe::narrow_klass_shift() != 0) {
6881 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6882 shlq(r, LogKlassAlignmentInBytes);
6883 }
6884 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base.
6885 if (Universe::narrow_klass_base() != NULL) {
6886 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base());
6887 addq(r, r12_heapbase);
6888 reinit_heapbase();
6889 }
6890 }
6891
6892 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
6893 // Note: it will change flags
6894 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6895 if (dst == src) {
6896 decode_klass_not_null(dst);
6897 } else {
6898 // Cannot assert, unverified entry point counts instructions (see .ad file)
6899 // vtableStubs also counts instructions in pd_code_size_limit.
6900 // Also do not verify_oop as this is called by verify_oop.
6901 mov64(dst, (int64_t)Universe::narrow_klass_base());
6902 if (Universe::narrow_klass_shift() != 0) {
6903 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong");
6904 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6905 leaq(dst, Address(dst, src, Address::times_8, 0));
6906 } else {
6907 addq(dst, src);
6908 }
6909 }
6910 }
6911
6912 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6913 assert (UseCompressedOops, "should only be used for compressed headers");
6914 assert (Universe::heap() != NULL, "java heap should be initialized");
6915 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6916 int oop_index = oop_recorder()->find_index(obj);
6917 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6918 mov_narrow_oop(dst, oop_index, rspec);
6919 }
6920
6921 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6922 assert (UseCompressedOops, "should only be used for compressed headers");
6923 assert (Universe::heap() != NULL, "java heap should be initialized");
6924 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6925 int oop_index = oop_recorder()->find_index(obj);
6926 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6927 mov_narrow_oop(dst, oop_index, rspec);
6928 }
6929
6930 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6931 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6932 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6933 int klass_index = oop_recorder()->find_index(k);
6934 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6935 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6936 }
6937
6938 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6939 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6940 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6941 int klass_index = oop_recorder()->find_index(k);
6942 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6943 mov_narrow_oop(dst, Klass::encode_klass(k), rspec);
6944 }
6945
6946 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6947 assert (UseCompressedOops, "should only be used for compressed headers");
6948 assert (Universe::heap() != NULL, "java heap should be initialized");
6949 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6950 int oop_index = oop_recorder()->find_index(obj);
6951 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6952 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6953 }
6954
6955 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6956 assert (UseCompressedOops, "should only be used for compressed headers");
6957 assert (Universe::heap() != NULL, "java heap should be initialized");
6958 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6959 int oop_index = oop_recorder()->find_index(obj);
6960 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6961 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6962 }
6963
6964 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6965 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6966 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6967 int klass_index = oop_recorder()->find_index(k);
6968 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6969 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6970 }
6971
6972 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6973 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6974 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
6975 int klass_index = oop_recorder()->find_index(k);
6976 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6977 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec);
6978 }
6979
6980 void MacroAssembler::reinit_heapbase() {
6981 if (UseCompressedOops || UseCompressedClassPointers) {
6982 if (Universe::heap() != NULL) {
6983 if (Universe::narrow_oop_base() == NULL) {
6984 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6985 } else {
6986 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base());
6987 }
6988 } else {
6989 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr()));
6990 }
6991 }
6992 }
6993
6994 #endif // _LP64
6995
6996
6997 // C2 compiled method's prolog code.
6998 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) {
6999
7000 // WARNING: Initial instruction MUST be 5 bytes or longer so that
7001 // NativeJump::patch_verified_entry will be able to patch out the entry
7002 // code safely. The push to verify stack depth is ok at 5 bytes,
7003 // the frame allocation can be either 3 or 6 bytes. So if we don't do
7004 // stack bang then we must use the 6 byte frame allocation even if
7005 // we have no frame. :-(
7006 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
7007
7008 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
7009 // Remove word for return addr
7010 framesize -= wordSize;
7011 stack_bang_size -= wordSize;
7012
7013 // Calls to C2R adapters often do not accept exceptional returns.
7014 // We require that their callers must bang for them. But be careful, because
7015 // some VM calls (such as call site linkage) can use several kilobytes of
7016 // stack. But the stack safety zone should account for that.
7017 // See bugs 4446381, 4468289, 4497237.
7018 if (stack_bang_size > 0) {
7019 generate_stack_overflow_check(stack_bang_size);
7020
7021 // We always push rbp, so that on return to interpreter rbp, will be
7022 // restored correctly and we can correct the stack.
7023 push(rbp);
7024 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7025 if (PreserveFramePointer) {
7026 mov(rbp, rsp);
7027 }
7028 // Remove word for ebp
7029 framesize -= wordSize;
7030
7031 // Create frame
7032 if (framesize) {
7033 subptr(rsp, framesize);
7034 }
7035 } else {
7036 // Create frame (force generation of a 4 byte immediate value)
7037 subptr_imm32(rsp, framesize);
7038
7039 // Save RBP register now.
7040 framesize -= wordSize;
7041 movptr(Address(rsp, framesize), rbp);
7042 // Save caller's stack pointer into RBP if the frame pointer is preserved.
7043 if (PreserveFramePointer) {
7044 movptr(rbp, rsp);
7045 if (framesize > 0) {
7046 addptr(rbp, framesize);
7047 }
7048 }
7049 }
7050
7051 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
7052 framesize -= wordSize;
7053 movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
7054 }
7055
7056 #ifndef _LP64
7057 // If method sets FPU control word do it now
7058 if (fp_mode_24b) {
7059 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
7060 }
7061 if (UseSSE >= 2 && VerifyFPU) {
7062 verify_FPU(0, "FPU stack must be clean on entry");
7063 }
7064 #endif
7065
7066 #ifdef ASSERT
7067 if (VerifyStackAtCalls) {
7068 Label L;
7069 push(rax);
7070 mov(rax, rsp);
7071 andptr(rax, StackAlignmentInBytes-1);
7072 cmpptr(rax, StackAlignmentInBytes-wordSize);
7073 pop(rax);
7074 jcc(Assembler::equal, L);
7075 STOP("Stack is not properly aligned!");
7076 bind(L);
7077 }
7078 #endif
7079
7080 }
7081
7082 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) {
7083 // cnt - number of qwords (8-byte words).
7084 // base - start address, qword aligned.
7085 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7086 assert(base==rdi, "base register must be edi for rep stos");
7087 assert(tmp==rax, "tmp register must be eax for rep stos");
7088 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7089 assert(InitArrayShortSize % BytesPerLong == 0,
7090 "InitArrayShortSize should be the multiple of BytesPerLong");
7091
7092 Label DONE;
7093
7094 xorptr(tmp, tmp);
7095
7096 if (!is_large) {
7097 Label LOOP, LONG;
7098 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7099 jccb(Assembler::greater, LONG);
7100
7101 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7102
7103 decrement(cnt);
7104 jccb(Assembler::negative, DONE); // Zero length
7105
7106 // Use individual pointer-sized stores for small counts:
7107 BIND(LOOP);
7108 movptr(Address(base, cnt, Address::times_ptr), tmp);
7109 decrement(cnt);
7110 jccb(Assembler::greaterEqual, LOOP);
7111 jmpb(DONE);
7112
7113 BIND(LONG);
7114 }
7115
7116 // Use longer rep-prefixed ops for non-small counts:
7117 if (UseFastStosb) {
7118 shlptr(cnt, 3); // convert to number of bytes
7119 rep_stosb();
7120 } else {
7121 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7122 rep_stos();
7123 }
7124
7125 BIND(DONE);
7126 }
7127
7128 #ifdef COMPILER2
7129
7130 // IndexOf for constant substrings with size >= 8 chars
7131 // which don't need to be loaded through stack.
7132 void MacroAssembler::string_indexofC8(Register str1, Register str2,
7133 Register cnt1, Register cnt2,
7134 int int_cnt2, Register result,
7135 XMMRegister vec, Register tmp,
7136 int ae) {
7137 ShortBranchVerifier sbv(this);
7138 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7139 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7140
7141 // This method uses the pcmpestri instruction with bound registers
7142 // inputs:
7143 // xmm - substring
7144 // rax - substring length (elements count)
7145 // mem - scanned string
7146 // rdx - string length (elements count)
7147 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7148 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7149 // outputs:
7150 // rcx - matched index in string
7151 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7152 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7153 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7154 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7155 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7156
7157 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR,
7158 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR,
7159 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE;
7160
7161 // Note, inline_string_indexOf() generates checks:
7162 // if (substr.count > string.count) return -1;
7163 // if (substr.count == 0) return 0;
7164 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars");
7165
7166 // Load substring.
7167 if (ae == StrIntrinsicNode::UL) {
7168 pmovzxbw(vec, Address(str2, 0));
7169 } else {
7170 movdqu(vec, Address(str2, 0));
7171 }
7172 movl(cnt2, int_cnt2);
7173 movptr(result, str1); // string addr
7174
7175 if (int_cnt2 > stride) {
7176 jmpb(SCAN_TO_SUBSTR);
7177
7178 // Reload substr for rescan, this code
7179 // is executed only for large substrings (> 8 chars)
7180 bind(RELOAD_SUBSTR);
7181 if (ae == StrIntrinsicNode::UL) {
7182 pmovzxbw(vec, Address(str2, 0));
7183 } else {
7184 movdqu(vec, Address(str2, 0));
7185 }
7186 negptr(cnt2); // Jumped here with negative cnt2, convert to positive
7187
7188 bind(RELOAD_STR);
7189 // We came here after the beginning of the substring was
7190 // matched but the rest of it was not so we need to search
7191 // again. Start from the next element after the previous match.
7192
7193 // cnt2 is number of substring reminding elements and
7194 // cnt1 is number of string reminding elements when cmp failed.
7195 // Restored cnt1 = cnt1 - cnt2 + int_cnt2
7196 subl(cnt1, cnt2);
7197 addl(cnt1, int_cnt2);
7198 movl(cnt2, int_cnt2); // Now restore cnt2
7199
7200 decrementl(cnt1); // Shift to next element
7201 cmpl(cnt1, cnt2);
7202 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7203
7204 addptr(result, (1<<scale1));
7205
7206 } // (int_cnt2 > 8)
7207
7208 // Scan string for start of substr in 16-byte vectors
7209 bind(SCAN_TO_SUBSTR);
7210 pcmpestri(vec, Address(result, 0), mode);
7211 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7212 subl(cnt1, stride);
7213 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7214 cmpl(cnt1, cnt2);
7215 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7216 addptr(result, 16);
7217 jmpb(SCAN_TO_SUBSTR);
7218
7219 // Found a potential substr
7220 bind(FOUND_CANDIDATE);
7221 // Matched whole vector if first element matched (tmp(rcx) == 0).
7222 if (int_cnt2 == stride) {
7223 jccb(Assembler::overflow, RET_FOUND); // OF == 1
7224 } else { // int_cnt2 > 8
7225 jccb(Assembler::overflow, FOUND_SUBSTR);
7226 }
7227 // After pcmpestri tmp(rcx) contains matched element index
7228 // Compute start addr of substr
7229 lea(result, Address(result, tmp, scale1));
7230
7231 // Make sure string is still long enough
7232 subl(cnt1, tmp);
7233 cmpl(cnt1, cnt2);
7234 if (int_cnt2 == stride) {
7235 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7236 } else { // int_cnt2 > 8
7237 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD);
7238 }
7239 // Left less then substring.
7240
7241 bind(RET_NOT_FOUND);
7242 movl(result, -1);
7243 jmp(EXIT);
7244
7245 if (int_cnt2 > stride) {
7246 // This code is optimized for the case when whole substring
7247 // is matched if its head is matched.
7248 bind(MATCH_SUBSTR_HEAD);
7249 pcmpestri(vec, Address(result, 0), mode);
7250 // Reload only string if does not match
7251 jcc(Assembler::noOverflow, RELOAD_STR); // OF == 0
7252
7253 Label CONT_SCAN_SUBSTR;
7254 // Compare the rest of substring (> 8 chars).
7255 bind(FOUND_SUBSTR);
7256 // First 8 chars are already matched.
7257 negptr(cnt2);
7258 addptr(cnt2, stride);
7259
7260 bind(SCAN_SUBSTR);
7261 subl(cnt1, stride);
7262 cmpl(cnt2, -stride); // Do not read beyond substring
7263 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR);
7264 // Back-up strings to avoid reading beyond substring:
7265 // cnt1 = cnt1 - cnt2 + 8
7266 addl(cnt1, cnt2); // cnt2 is negative
7267 addl(cnt1, stride);
7268 movl(cnt2, stride); negptr(cnt2);
7269 bind(CONT_SCAN_SUBSTR);
7270 if (int_cnt2 < (int)G) {
7271 int tail_off1 = int_cnt2<<scale1;
7272 int tail_off2 = int_cnt2<<scale2;
7273 if (ae == StrIntrinsicNode::UL) {
7274 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2));
7275 } else {
7276 movdqu(vec, Address(str2, cnt2, scale2, tail_off2));
7277 }
7278 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode);
7279 } else {
7280 // calculate index in register to avoid integer overflow (int_cnt2*2)
7281 movl(tmp, int_cnt2);
7282 addptr(tmp, cnt2);
7283 if (ae == StrIntrinsicNode::UL) {
7284 pmovzxbw(vec, Address(str2, tmp, scale2, 0));
7285 } else {
7286 movdqu(vec, Address(str2, tmp, scale2, 0));
7287 }
7288 pcmpestri(vec, Address(result, tmp, scale1, 0), mode);
7289 }
7290 // Need to reload strings pointers if not matched whole vector
7291 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7292 addptr(cnt2, stride);
7293 jcc(Assembler::negative, SCAN_SUBSTR);
7294 // Fall through if found full substring
7295
7296 } // (int_cnt2 > 8)
7297
7298 bind(RET_FOUND);
7299 // Found result if we matched full small substring.
7300 // Compute substr offset
7301 subptr(result, str1);
7302 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7303 shrl(result, 1); // index
7304 }
7305 bind(EXIT);
7306
7307 } // string_indexofC8
7308
7309 // Small strings are loaded through stack if they cross page boundary.
7310 void MacroAssembler::string_indexof(Register str1, Register str2,
7311 Register cnt1, Register cnt2,
7312 int int_cnt2, Register result,
7313 XMMRegister vec, Register tmp,
7314 int ae) {
7315 ShortBranchVerifier sbv(this);
7316 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7317 assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
7318
7319 //
7320 // int_cnt2 is length of small (< 8 chars) constant substring
7321 // or (-1) for non constant substring in which case its length
7322 // is in cnt2 register.
7323 //
7324 // Note, inline_string_indexOf() generates checks:
7325 // if (substr.count > string.count) return -1;
7326 // if (substr.count == 0) return 0;
7327 //
7328 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8
7329 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0");
7330 // This method uses the pcmpestri instruction with bound registers
7331 // inputs:
7332 // xmm - substring
7333 // rax - substring length (elements count)
7334 // mem - scanned string
7335 // rdx - string length (elements count)
7336 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts)
7337 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes)
7338 // outputs:
7339 // rcx - matched index in string
7340 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7341 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts
7342 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2;
7343 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1;
7344
7345 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR,
7346 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR,
7347 FOUND_CANDIDATE;
7348
7349 { //========================================================
7350 // We don't know where these strings are located
7351 // and we can't read beyond them. Load them through stack.
7352 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR;
7353
7354 movptr(tmp, rsp); // save old SP
7355
7356 if (int_cnt2 > 0) { // small (< 8 chars) constant substring
7357 if (int_cnt2 == (1>>scale2)) { // One byte
7358 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding");
7359 load_unsigned_byte(result, Address(str2, 0));
7360 movdl(vec, result); // move 32 bits
7361 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes
7362 // Not enough header space in 32-bit VM: 12+3 = 15.
7363 movl(result, Address(str2, -1));
7364 shrl(result, 8);
7365 movdl(vec, result); // move 32 bits
7366 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char
7367 load_unsigned_short(result, Address(str2, 0));
7368 movdl(vec, result); // move 32 bits
7369 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars
7370 movdl(vec, Address(str2, 0)); // move 32 bits
7371 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars
7372 movq(vec, Address(str2, 0)); // move 64 bits
7373 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7})
7374 // Array header size is 12 bytes in 32-bit VM
7375 // + 6 bytes for 3 chars == 18 bytes,
7376 // enough space to load vec and shift.
7377 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity");
7378 if (ae == StrIntrinsicNode::UL) {
7379 int tail_off = int_cnt2-8;
7380 pmovzxbw(vec, Address(str2, tail_off));
7381 psrldq(vec, -2*tail_off);
7382 }
7383 else {
7384 int tail_off = int_cnt2*(1<<scale2);
7385 movdqu(vec, Address(str2, tail_off-16));
7386 psrldq(vec, 16-tail_off);
7387 }
7388 }
7389 } else { // not constant substring
7390 cmpl(cnt2, stride);
7391 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough
7392
7393 // We can read beyond string if srt+16 does not cross page boundary
7394 // since heaps are aligned and mapped by pages.
7395 assert(os::vm_page_size() < (int)G, "default page should be small");
7396 movl(result, str2); // We need only low 32 bits
7397 andl(result, (os::vm_page_size()-1));
7398 cmpl(result, (os::vm_page_size()-16));
7399 jccb(Assembler::belowEqual, CHECK_STR);
7400
7401 // Move small strings to stack to allow load 16 bytes into vec.
7402 subptr(rsp, 16);
7403 int stk_offset = wordSize-(1<<scale2);
7404 push(cnt2);
7405
7406 bind(COPY_SUBSTR);
7407 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) {
7408 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1));
7409 movb(Address(rsp, cnt2, scale2, stk_offset), result);
7410 } else if (ae == StrIntrinsicNode::UU) {
7411 load_unsigned_short(result, Address(str2, cnt2, scale2, -2));
7412 movw(Address(rsp, cnt2, scale2, stk_offset), result);
7413 }
7414 decrement(cnt2);
7415 jccb(Assembler::notZero, COPY_SUBSTR);
7416
7417 pop(cnt2);
7418 movptr(str2, rsp); // New substring address
7419 } // non constant
7420
7421 bind(CHECK_STR);
7422 cmpl(cnt1, stride);
7423 jccb(Assembler::aboveEqual, BIG_STRINGS);
7424
7425 // Check cross page boundary.
7426 movl(result, str1); // We need only low 32 bits
7427 andl(result, (os::vm_page_size()-1));
7428 cmpl(result, (os::vm_page_size()-16));
7429 jccb(Assembler::belowEqual, BIG_STRINGS);
7430
7431 subptr(rsp, 16);
7432 int stk_offset = -(1<<scale1);
7433 if (int_cnt2 < 0) { // not constant
7434 push(cnt2);
7435 stk_offset += wordSize;
7436 }
7437 movl(cnt2, cnt1);
7438
7439 bind(COPY_STR);
7440 if (ae == StrIntrinsicNode::LL) {
7441 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1));
7442 movb(Address(rsp, cnt2, scale1, stk_offset), result);
7443 } else {
7444 load_unsigned_short(result, Address(str1, cnt2, scale1, -2));
7445 movw(Address(rsp, cnt2, scale1, stk_offset), result);
7446 }
7447 decrement(cnt2);
7448 jccb(Assembler::notZero, COPY_STR);
7449
7450 if (int_cnt2 < 0) { // not constant
7451 pop(cnt2);
7452 }
7453 movptr(str1, rsp); // New string address
7454
7455 bind(BIG_STRINGS);
7456 // Load substring.
7457 if (int_cnt2 < 0) { // -1
7458 if (ae == StrIntrinsicNode::UL) {
7459 pmovzxbw(vec, Address(str2, 0));
7460 } else {
7461 movdqu(vec, Address(str2, 0));
7462 }
7463 push(cnt2); // substr count
7464 push(str2); // substr addr
7465 push(str1); // string addr
7466 } else {
7467 // Small (< 8 chars) constant substrings are loaded already.
7468 movl(cnt2, int_cnt2);
7469 }
7470 push(tmp); // original SP
7471
7472 } // Finished loading
7473
7474 //========================================================
7475 // Start search
7476 //
7477
7478 movptr(result, str1); // string addr
7479
7480 if (int_cnt2 < 0) { // Only for non constant substring
7481 jmpb(SCAN_TO_SUBSTR);
7482
7483 // SP saved at sp+0
7484 // String saved at sp+1*wordSize
7485 // Substr saved at sp+2*wordSize
7486 // Substr count saved at sp+3*wordSize
7487
7488 // Reload substr for rescan, this code
7489 // is executed only for large substrings (> 8 chars)
7490 bind(RELOAD_SUBSTR);
7491 movptr(str2, Address(rsp, 2*wordSize));
7492 movl(cnt2, Address(rsp, 3*wordSize));
7493 if (ae == StrIntrinsicNode::UL) {
7494 pmovzxbw(vec, Address(str2, 0));
7495 } else {
7496 movdqu(vec, Address(str2, 0));
7497 }
7498 // We came here after the beginning of the substring was
7499 // matched but the rest of it was not so we need to search
7500 // again. Start from the next element after the previous match.
7501 subptr(str1, result); // Restore counter
7502 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7503 shrl(str1, 1);
7504 }
7505 addl(cnt1, str1);
7506 decrementl(cnt1); // Shift to next element
7507 cmpl(cnt1, cnt2);
7508 jcc(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7509
7510 addptr(result, (1<<scale1));
7511 } // non constant
7512
7513 // Scan string for start of substr in 16-byte vectors
7514 bind(SCAN_TO_SUBSTR);
7515 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri");
7516 pcmpestri(vec, Address(result, 0), mode);
7517 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1
7518 subl(cnt1, stride);
7519 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string
7520 cmpl(cnt1, cnt2);
7521 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring
7522 addptr(result, 16);
7523
7524 bind(ADJUST_STR);
7525 cmpl(cnt1, stride); // Do not read beyond string
7526 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR);
7527 // Back-up string to avoid reading beyond string.
7528 lea(result, Address(result, cnt1, scale1, -16));
7529 movl(cnt1, stride);
7530 jmpb(SCAN_TO_SUBSTR);
7531
7532 // Found a potential substr
7533 bind(FOUND_CANDIDATE);
7534 // After pcmpestri tmp(rcx) contains matched element index
7535
7536 // Make sure string is still long enough
7537 subl(cnt1, tmp);
7538 cmpl(cnt1, cnt2);
7539 jccb(Assembler::greaterEqual, FOUND_SUBSTR);
7540 // Left less then substring.
7541
7542 bind(RET_NOT_FOUND);
7543 movl(result, -1);
7544 jmpb(CLEANUP);
7545
7546 bind(FOUND_SUBSTR);
7547 // Compute start addr of substr
7548 lea(result, Address(result, tmp, scale1));
7549 if (int_cnt2 > 0) { // Constant substring
7550 // Repeat search for small substring (< 8 chars)
7551 // from new point without reloading substring.
7552 // Have to check that we don't read beyond string.
7553 cmpl(tmp, stride-int_cnt2);
7554 jccb(Assembler::greater, ADJUST_STR);
7555 // Fall through if matched whole substring.
7556 } else { // non constant
7557 assert(int_cnt2 == -1, "should be != 0");
7558
7559 addl(tmp, cnt2);
7560 // Found result if we matched whole substring.
7561 cmpl(tmp, stride);
7562 jccb(Assembler::lessEqual, RET_FOUND);
7563
7564 // Repeat search for small substring (<= 8 chars)
7565 // from new point 'str1' without reloading substring.
7566 cmpl(cnt2, stride);
7567 // Have to check that we don't read beyond string.
7568 jccb(Assembler::lessEqual, ADJUST_STR);
7569
7570 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG;
7571 // Compare the rest of substring (> 8 chars).
7572 movptr(str1, result);
7573
7574 cmpl(tmp, cnt2);
7575 // First 8 chars are already matched.
7576 jccb(Assembler::equal, CHECK_NEXT);
7577
7578 bind(SCAN_SUBSTR);
7579 pcmpestri(vec, Address(str1, 0), mode);
7580 // Need to reload strings pointers if not matched whole vector
7581 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0
7582
7583 bind(CHECK_NEXT);
7584 subl(cnt2, stride);
7585 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring
7586 addptr(str1, 16);
7587 if (ae == StrIntrinsicNode::UL) {
7588 addptr(str2, 8);
7589 } else {
7590 addptr(str2, 16);
7591 }
7592 subl(cnt1, stride);
7593 cmpl(cnt2, stride); // Do not read beyond substring
7594 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR);
7595 // Back-up strings to avoid reading beyond substring.
7596
7597 if (ae == StrIntrinsicNode::UL) {
7598 lea(str2, Address(str2, cnt2, scale2, -8));
7599 lea(str1, Address(str1, cnt2, scale1, -16));
7600 } else {
7601 lea(str2, Address(str2, cnt2, scale2, -16));
7602 lea(str1, Address(str1, cnt2, scale1, -16));
7603 }
7604 subl(cnt1, cnt2);
7605 movl(cnt2, stride);
7606 addl(cnt1, stride);
7607 bind(CONT_SCAN_SUBSTR);
7608 if (ae == StrIntrinsicNode::UL) {
7609 pmovzxbw(vec, Address(str2, 0));
7610 } else {
7611 movdqu(vec, Address(str2, 0));
7612 }
7613 jmp(SCAN_SUBSTR);
7614
7615 bind(RET_FOUND_LONG);
7616 movptr(str1, Address(rsp, wordSize));
7617 } // non constant
7618
7619 bind(RET_FOUND);
7620 // Compute substr offset
7621 subptr(result, str1);
7622 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) {
7623 shrl(result, 1); // index
7624 }
7625 bind(CLEANUP);
7626 pop(rsp); // restore SP
7627
7628 } // string_indexof
7629
7630 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
7631 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) {
7632 ShortBranchVerifier sbv(this);
7633 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required");
7634
7635 int stride = 8;
7636
7637 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP,
7638 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP,
7639 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT,
7640 FOUND_SEQ_CHAR, DONE_LABEL;
7641
7642 movptr(result, str1);
7643 if (UseAVX >= 2) {
7644 cmpl(cnt1, stride);
7645 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7646 cmpl(cnt1, 2*stride);
7647 jcc(Assembler::less, SCAN_TO_8_CHAR_INIT);
7648 movdl(vec1, ch);
7649 vpbroadcastw(vec1, vec1);
7650 vpxor(vec2, vec2);
7651 movl(tmp, cnt1);
7652 andl(tmp, 0xFFFFFFF0); //vector count (in chars)
7653 andl(cnt1,0x0000000F); //tail count (in chars)
7654
7655 bind(SCAN_TO_16_CHAR_LOOP);
7656 vmovdqu(vec3, Address(result, 0));
7657 vpcmpeqw(vec3, vec3, vec1, 1);
7658 vptest(vec2, vec3);
7659 jcc(Assembler::carryClear, FOUND_CHAR);
7660 addptr(result, 32);
7661 subl(tmp, 2*stride);
7662 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP);
7663 jmp(SCAN_TO_8_CHAR);
7664 bind(SCAN_TO_8_CHAR_INIT);
7665 movdl(vec1, ch);
7666 pshuflw(vec1, vec1, 0x00);
7667 pshufd(vec1, vec1, 0);
7668 pxor(vec2, vec2);
7669 }
7670 bind(SCAN_TO_8_CHAR);
7671 cmpl(cnt1, stride);
7672 if (UseAVX >= 2) {
7673 jcc(Assembler::less, SCAN_TO_CHAR);
7674 } else {
7675 jcc(Assembler::less, SCAN_TO_CHAR_LOOP);
7676 movdl(vec1, ch);
7677 pshuflw(vec1, vec1, 0x00);
7678 pshufd(vec1, vec1, 0);
7679 pxor(vec2, vec2);
7680 }
7681 movl(tmp, cnt1);
7682 andl(tmp, 0xFFFFFFF8); //vector count (in chars)
7683 andl(cnt1,0x00000007); //tail count (in chars)
7684
7685 bind(SCAN_TO_8_CHAR_LOOP);
7686 movdqu(vec3, Address(result, 0));
7687 pcmpeqw(vec3, vec1);
7688 ptest(vec2, vec3);
7689 jcc(Assembler::carryClear, FOUND_CHAR);
7690 addptr(result, 16);
7691 subl(tmp, stride);
7692 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP);
7693 bind(SCAN_TO_CHAR);
7694 testl(cnt1, cnt1);
7695 jcc(Assembler::zero, RET_NOT_FOUND);
7696 bind(SCAN_TO_CHAR_LOOP);
7697 load_unsigned_short(tmp, Address(result, 0));
7698 cmpl(ch, tmp);
7699 jccb(Assembler::equal, FOUND_SEQ_CHAR);
7700 addptr(result, 2);
7701 subl(cnt1, 1);
7702 jccb(Assembler::zero, RET_NOT_FOUND);
7703 jmp(SCAN_TO_CHAR_LOOP);
7704
7705 bind(RET_NOT_FOUND);
7706 movl(result, -1);
7707 jmpb(DONE_LABEL);
7708
7709 bind(FOUND_CHAR);
7710 if (UseAVX >= 2) {
7711 vpmovmskb(tmp, vec3);
7712 } else {
7713 pmovmskb(tmp, vec3);
7714 }
7715 bsfl(ch, tmp);
7716 addl(result, ch);
7717
7718 bind(FOUND_SEQ_CHAR);
7719 subptr(result, str1);
7720 shrl(result, 1);
7721
7722 bind(DONE_LABEL);
7723 } // string_indexof_char
7724
7725 // helper function for string_compare
7726 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
7727 Address::ScaleFactor scale, Address::ScaleFactor scale1,
7728 Address::ScaleFactor scale2, Register index, int ae) {
7729 if (ae == StrIntrinsicNode::LL) {
7730 load_unsigned_byte(elem1, Address(str1, index, scale, 0));
7731 load_unsigned_byte(elem2, Address(str2, index, scale, 0));
7732 } else if (ae == StrIntrinsicNode::UU) {
7733 load_unsigned_short(elem1, Address(str1, index, scale, 0));
7734 load_unsigned_short(elem2, Address(str2, index, scale, 0));
7735 } else {
7736 load_unsigned_byte(elem1, Address(str1, index, scale1, 0));
7737 load_unsigned_short(elem2, Address(str2, index, scale2, 0));
7738 }
7739 }
7740
7741 // Compare strings, used for char[] and byte[].
7742 void MacroAssembler::string_compare(Register str1, Register str2,
7743 Register cnt1, Register cnt2, Register result,
7744 XMMRegister vec1, int ae) {
7745 ShortBranchVerifier sbv(this);
7746 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL;
7747 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3
7748 int stride, stride2, adr_stride, adr_stride1, adr_stride2;
7749 int stride2x2 = 0x40;
7750 Address::ScaleFactor scale = Address::no_scale;
7751 Address::ScaleFactor scale1 = Address::no_scale;
7752 Address::ScaleFactor scale2 = Address::no_scale;
7753
7754 if (ae != StrIntrinsicNode::LL) {
7755 stride2x2 = 0x20;
7756 }
7757
7758 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) {
7759 shrl(cnt2, 1);
7760 }
7761 // Compute the minimum of the string lengths and the
7762 // difference of the string lengths (stack).
7763 // Do the conditional move stuff
7764 movl(result, cnt1);
7765 subl(cnt1, cnt2);
7766 push(cnt1);
7767 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2)
7768
7769 // Is the minimum length zero?
7770 testl(cnt2, cnt2);
7771 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7772 if (ae == StrIntrinsicNode::LL) {
7773 // Load first bytes
7774 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0]
7775 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0]
7776 } else if (ae == StrIntrinsicNode::UU) {
7777 // Load first characters
7778 load_unsigned_short(result, Address(str1, 0));
7779 load_unsigned_short(cnt1, Address(str2, 0));
7780 } else {
7781 load_unsigned_byte(result, Address(str1, 0));
7782 load_unsigned_short(cnt1, Address(str2, 0));
7783 }
7784 subl(result, cnt1);
7785 jcc(Assembler::notZero, POP_LABEL);
7786
7787 if (ae == StrIntrinsicNode::UU) {
7788 // Divide length by 2 to get number of chars
7789 shrl(cnt2, 1);
7790 }
7791 cmpl(cnt2, 1);
7792 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7793
7794 // Check if the strings start at the same location and setup scale and stride
7795 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7796 cmpptr(str1, str2);
7797 jcc(Assembler::equal, LENGTH_DIFF_LABEL);
7798 if (ae == StrIntrinsicNode::LL) {
7799 scale = Address::times_1;
7800 stride = 16;
7801 } else {
7802 scale = Address::times_2;
7803 stride = 8;
7804 }
7805 } else {
7806 scale1 = Address::times_1;
7807 scale2 = Address::times_2;
7808 // scale not used
7809 stride = 8;
7810 }
7811
7812 if (UseAVX >= 2 && UseSSE42Intrinsics) {
7813 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR;
7814 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR;
7815 Label COMPARE_WIDE_VECTORS_LOOP_AVX2;
7816 Label COMPARE_TAIL_LONG;
7817 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3
7818
7819 int pcmpmask = 0x19;
7820 if (ae == StrIntrinsicNode::LL) {
7821 pcmpmask &= ~0x01;
7822 }
7823
7824 // Setup to compare 16-chars (32-bytes) vectors,
7825 // start from first character again because it has aligned address.
7826 if (ae == StrIntrinsicNode::LL) {
7827 stride2 = 32;
7828 } else {
7829 stride2 = 16;
7830 }
7831 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7832 adr_stride = stride << scale;
7833 } else {
7834 adr_stride1 = 8; //stride << scale1;
7835 adr_stride2 = 16; //stride << scale2;
7836 }
7837
7838 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
7839 // rax and rdx are used by pcmpestri as elements counters
7840 movl(result, cnt2);
7841 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count
7842 jcc(Assembler::zero, COMPARE_TAIL_LONG);
7843
7844 // fast path : compare first 2 8-char vectors.
7845 bind(COMPARE_16_CHARS);
7846 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7847 movdqu(vec1, Address(str1, 0));
7848 } else {
7849 pmovzxbw(vec1, Address(str1, 0));
7850 }
7851 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7852 jccb(Assembler::below, COMPARE_INDEX_CHAR);
7853
7854 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7855 movdqu(vec1, Address(str1, adr_stride));
7856 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask);
7857 } else {
7858 pmovzxbw(vec1, Address(str1, adr_stride1));
7859 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask);
7860 }
7861 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS);
7862 addl(cnt1, stride);
7863
7864 // Compare the characters at index in cnt1
7865 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character
7866 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
7867 subl(result, cnt2);
7868 jmp(POP_LABEL);
7869
7870 // Setup the registers to start vector comparison loop
7871 bind(COMPARE_WIDE_VECTORS);
7872 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7873 lea(str1, Address(str1, result, scale));
7874 lea(str2, Address(str2, result, scale));
7875 } else {
7876 lea(str1, Address(str1, result, scale1));
7877 lea(str2, Address(str2, result, scale2));
7878 }
7879 subl(result, stride2);
7880 subl(cnt2, stride2);
7881 jcc(Assembler::zero, COMPARE_WIDE_TAIL);
7882 negptr(result);
7883
7884 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest)
7885 bind(COMPARE_WIDE_VECTORS_LOOP);
7886
7887 #ifdef _LP64
7888 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
7889 cmpl(cnt2, stride2x2);
7890 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2);
7891 testl(cnt2, stride2x2-1); // cnt2 holds the vector count
7892 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40
7893
7894 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
7895 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7896 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit);
7897 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7898 } else {
7899 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit);
7900 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0
7901 }
7902 kortestql(k7, k7);
7903 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare
7904 addptr(result, stride2x2); // update since we already compared at this addr
7905 subl(cnt2, stride2x2); // and sub the size too
7906 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3);
7907
7908 vpxor(vec1, vec1);
7909 jmpb(COMPARE_WIDE_TAIL);
7910 }//if (VM_Version::supports_avx512vlbw())
7911 #endif // _LP64
7912
7913
7914 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7915 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7916 vmovdqu(vec1, Address(str1, result, scale));
7917 vpxor(vec1, Address(str2, result, scale));
7918 } else {
7919 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit);
7920 vpxor(vec1, Address(str2, result, scale2));
7921 }
7922 vptest(vec1, vec1);
7923 jcc(Assembler::notZero, VECTOR_NOT_EQUAL);
7924 addptr(result, stride2);
7925 subl(cnt2, stride2);
7926 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP);
7927 // clean upper bits of YMM registers
7928 vpxor(vec1, vec1);
7929
7930 // compare wide vectors tail
7931 bind(COMPARE_WIDE_TAIL);
7932 testptr(result, result);
7933 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7934
7935 movl(result, stride2);
7936 movl(cnt2, result);
7937 negptr(result);
7938 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2);
7939
7940 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors.
7941 bind(VECTOR_NOT_EQUAL);
7942 // clean upper bits of YMM registers
7943 vpxor(vec1, vec1);
7944 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7945 lea(str1, Address(str1, result, scale));
7946 lea(str2, Address(str2, result, scale));
7947 } else {
7948 lea(str1, Address(str1, result, scale1));
7949 lea(str2, Address(str2, result, scale2));
7950 }
7951 jmp(COMPARE_16_CHARS);
7952
7953 // Compare tail chars, length between 1 to 15 chars
7954 bind(COMPARE_TAIL_LONG);
7955 movl(cnt2, result);
7956 cmpl(cnt2, stride);
7957 jcc(Assembler::less, COMPARE_SMALL_STR);
7958
7959 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7960 movdqu(vec1, Address(str1, 0));
7961 } else {
7962 pmovzxbw(vec1, Address(str1, 0));
7963 }
7964 pcmpestri(vec1, Address(str2, 0), pcmpmask);
7965 jcc(Assembler::below, COMPARE_INDEX_CHAR);
7966 subptr(cnt2, stride);
7967 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
7968 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7969 lea(str1, Address(str1, result, scale));
7970 lea(str2, Address(str2, result, scale));
7971 } else {
7972 lea(str1, Address(str1, result, scale1));
7973 lea(str2, Address(str2, result, scale2));
7974 }
7975 negptr(cnt2);
7976 jmpb(WHILE_HEAD_LABEL);
7977
7978 bind(COMPARE_SMALL_STR);
7979 } else if (UseSSE42Intrinsics) {
7980 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL;
7981 int pcmpmask = 0x19;
7982 // Setup to compare 8-char (16-byte) vectors,
7983 // start from first character again because it has aligned address.
7984 movl(result, cnt2);
7985 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count
7986 if (ae == StrIntrinsicNode::LL) {
7987 pcmpmask &= ~0x01;
7988 }
7989 jcc(Assembler::zero, COMPARE_TAIL);
7990 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
7991 lea(str1, Address(str1, result, scale));
7992 lea(str2, Address(str2, result, scale));
7993 } else {
7994 lea(str1, Address(str1, result, scale1));
7995 lea(str2, Address(str2, result, scale2));
7996 }
7997 negptr(result);
7998
7999 // pcmpestri
8000 // inputs:
8001 // vec1- substring
8002 // rax - negative string length (elements count)
8003 // mem - scanned string
8004 // rdx - string length (elements count)
8005 // pcmpmask - cmp mode: 11000 (string compare with negated result)
8006 // + 00 (unsigned bytes) or + 01 (unsigned shorts)
8007 // outputs:
8008 // rcx - first mismatched element index
8009 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri");
8010
8011 bind(COMPARE_WIDE_VECTORS);
8012 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8013 movdqu(vec1, Address(str1, result, scale));
8014 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8015 } else {
8016 pmovzxbw(vec1, Address(str1, result, scale1));
8017 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8018 }
8019 // After pcmpestri cnt1(rcx) contains mismatched element index
8020
8021 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1
8022 addptr(result, stride);
8023 subptr(cnt2, stride);
8024 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS);
8025
8026 // compare wide vectors tail
8027 testptr(result, result);
8028 jcc(Assembler::zero, LENGTH_DIFF_LABEL);
8029
8030 movl(cnt2, stride);
8031 movl(result, stride);
8032 negptr(result);
8033 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8034 movdqu(vec1, Address(str1, result, scale));
8035 pcmpestri(vec1, Address(str2, result, scale), pcmpmask);
8036 } else {
8037 pmovzxbw(vec1, Address(str1, result, scale1));
8038 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask);
8039 }
8040 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL);
8041
8042 // Mismatched characters in the vectors
8043 bind(VECTOR_NOT_EQUAL);
8044 addptr(cnt1, result);
8045 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae);
8046 subl(result, cnt2);
8047 jmpb(POP_LABEL);
8048
8049 bind(COMPARE_TAIL); // limit is zero
8050 movl(cnt2, result);
8051 // Fallthru to tail compare
8052 }
8053 // Shift str2 and str1 to the end of the arrays, negate min
8054 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) {
8055 lea(str1, Address(str1, cnt2, scale));
8056 lea(str2, Address(str2, cnt2, scale));
8057 } else {
8058 lea(str1, Address(str1, cnt2, scale1));
8059 lea(str2, Address(str2, cnt2, scale2));
8060 }
8061 decrementl(cnt2); // first character was compared already
8062 negptr(cnt2);
8063
8064 // Compare the rest of the elements
8065 bind(WHILE_HEAD_LABEL);
8066 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae);
8067 subl(result, cnt1);
8068 jccb(Assembler::notZero, POP_LABEL);
8069 increment(cnt2);
8070 jccb(Assembler::notZero, WHILE_HEAD_LABEL);
8071
8072 // Strings are equal up to min length. Return the length difference.
8073 bind(LENGTH_DIFF_LABEL);
8074 pop(result);
8075 if (ae == StrIntrinsicNode::UU) {
8076 // Divide diff by 2 to get number of chars
8077 sarl(result, 1);
8078 }
8079 jmpb(DONE_LABEL);
8080
8081 #ifdef _LP64
8082 if (VM_Version::supports_avx512vlbw()) {
8083
8084 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED);
8085
8086 kmovql(cnt1, k7);
8087 notq(cnt1);
8088 bsfq(cnt2, cnt1);
8089 if (ae != StrIntrinsicNode::LL) {
8090 // Divide diff by 2 to get number of chars
8091 sarl(cnt2, 1);
8092 }
8093 addq(result, cnt2);
8094 if (ae == StrIntrinsicNode::LL) {
8095 load_unsigned_byte(cnt1, Address(str2, result));
8096 load_unsigned_byte(result, Address(str1, result));
8097 } else if (ae == StrIntrinsicNode::UU) {
8098 load_unsigned_short(cnt1, Address(str2, result, scale));
8099 load_unsigned_short(result, Address(str1, result, scale));
8100 } else {
8101 load_unsigned_short(cnt1, Address(str2, result, scale2));
8102 load_unsigned_byte(result, Address(str1, result, scale1));
8103 }
8104 subl(result, cnt1);
8105 jmpb(POP_LABEL);
8106 }//if (VM_Version::supports_avx512vlbw())
8107 #endif // _LP64
8108
8109 // Discard the stored length difference
8110 bind(POP_LABEL);
8111 pop(cnt1);
8112
8113 // That's it
8114 bind(DONE_LABEL);
8115 if(ae == StrIntrinsicNode::UL) {
8116 negl(result);
8117 }
8118
8119 }
8120
8121 // Search for Non-ASCII character (Negative byte value) in a byte array,
8122 // return true if it has any and false otherwise.
8123 // ..\jdk\src\java.base\share\classes\java\lang\StringCoding.java
8124 // @HotSpotIntrinsicCandidate
8125 // private static boolean hasNegatives(byte[] ba, int off, int len) {
8126 // for (int i = off; i < off + len; i++) {
8127 // if (ba[i] < 0) {
8128 // return true;
8129 // }
8130 // }
8131 // return false;
8132 // }
8133 void MacroAssembler::has_negatives(Register ary1, Register len,
8134 Register result, Register tmp1,
8135 XMMRegister vec1, XMMRegister vec2) {
8136 // rsi: byte array
8137 // rcx: len
8138 // rax: result
8139 ShortBranchVerifier sbv(this);
8140 assert_different_registers(ary1, len, result, tmp1);
8141 assert_different_registers(vec1, vec2);
8142 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE;
8143
8144 // len == 0
8145 testl(len, len);
8146 jcc(Assembler::zero, FALSE_LABEL);
8147
8148 if ((UseAVX > 2) && // AVX512
8149 VM_Version::supports_avx512vlbw() &&
8150 VM_Version::supports_bmi2()) {
8151
8152 set_vector_masking(); // opening of the stub context for programming mask registers
8153
8154 Label test_64_loop, test_tail;
8155 Register tmp3_aliased = len;
8156
8157 movl(tmp1, len);
8158 vpxor(vec2, vec2, vec2, Assembler::AVX_512bit);
8159
8160 andl(tmp1, 64 - 1); // tail count (in chars) 0x3F
8161 andl(len, ~(64 - 1)); // vector count (in chars)
8162 jccb(Assembler::zero, test_tail);
8163
8164 lea(ary1, Address(ary1, len, Address::times_1));
8165 negptr(len);
8166
8167 bind(test_64_loop);
8168 // Check whether our 64 elements of size byte contain negatives
8169 evpcmpgtb(k2, vec2, Address(ary1, len, Address::times_1), Assembler::AVX_512bit);
8170 kortestql(k2, k2);
8171 jcc(Assembler::notZero, TRUE_LABEL);
8172
8173 addptr(len, 64);
8174 jccb(Assembler::notZero, test_64_loop);
8175
8176
8177 bind(test_tail);
8178 // bail out when there is nothing to be done
8179 testl(tmp1, -1);
8180 jcc(Assembler::zero, FALSE_LABEL);
8181
8182 // Save k1
8183 kmovql(k3, k1);
8184
8185 // ~(~0 << len) applied up to two times (for 32-bit scenario)
8186 #ifdef _LP64
8187 mov64(tmp3_aliased, 0xFFFFFFFFFFFFFFFF);
8188 shlxq(tmp3_aliased, tmp3_aliased, tmp1);
8189 notq(tmp3_aliased);
8190 kmovql(k1, tmp3_aliased);
8191 #else
8192 Label k_init;
8193 jmp(k_init);
8194
8195 // We could not read 64-bits from a general purpose register thus we move
8196 // data required to compose 64 1's to the instruction stream
8197 // We emit 64 byte wide series of elements from 0..63 which later on would
8198 // be used as a compare targets with tail count contained in tmp1 register.
8199 // Result would be a k1 register having tmp1 consecutive number or 1
8200 // counting from least significant bit.
8201 address tmp = pc();
8202 emit_int64(0x0706050403020100);
8203 emit_int64(0x0F0E0D0C0B0A0908);
8204 emit_int64(0x1716151413121110);
8205 emit_int64(0x1F1E1D1C1B1A1918);
8206 emit_int64(0x2726252423222120);
8207 emit_int64(0x2F2E2D2C2B2A2928);
8208 emit_int64(0x3736353433323130);
8209 emit_int64(0x3F3E3D3C3B3A3938);
8210
8211 bind(k_init);
8212 lea(len, InternalAddress(tmp));
8213 // create mask to test for negative byte inside a vector
8214 evpbroadcastb(vec1, tmp1, Assembler::AVX_512bit);
8215 evpcmpgtb(k1, vec1, Address(len, 0), Assembler::AVX_512bit);
8216
8217 #endif
8218 evpcmpgtb(k2, k1, vec2, Address(ary1, 0), Assembler::AVX_512bit);
8219 ktestq(k2, k1);
8220 // Restore k1
8221 kmovql(k1, k3);
8222 jcc(Assembler::notZero, TRUE_LABEL);
8223
8224 jmp(FALSE_LABEL);
8225
8226 clear_vector_masking(); // closing of the stub context for programming mask registers
8227 } else {
8228 movl(result, len); // copy
8229
8230 if (UseAVX == 2 && UseSSE >= 2) {
8231 // With AVX2, use 32-byte vector compare
8232 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8233
8234 // Compare 32-byte vectors
8235 andl(result, 0x0000001f); // tail count (in bytes)
8236 andl(len, 0xffffffe0); // vector count (in bytes)
8237 jccb(Assembler::zero, COMPARE_TAIL);
8238
8239 lea(ary1, Address(ary1, len, Address::times_1));
8240 negptr(len);
8241
8242 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector
8243 movdl(vec2, tmp1);
8244 vpbroadcastd(vec2, vec2);
8245
8246 bind(COMPARE_WIDE_VECTORS);
8247 vmovdqu(vec1, Address(ary1, len, Address::times_1));
8248 vptest(vec1, vec2);
8249 jccb(Assembler::notZero, TRUE_LABEL);
8250 addptr(len, 32);
8251 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8252
8253 testl(result, result);
8254 jccb(Assembler::zero, FALSE_LABEL);
8255
8256 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8257 vptest(vec1, vec2);
8258 jccb(Assembler::notZero, TRUE_LABEL);
8259 jmpb(FALSE_LABEL);
8260
8261 bind(COMPARE_TAIL); // len is zero
8262 movl(len, result);
8263 // Fallthru to tail compare
8264 } else if (UseSSE42Intrinsics) {
8265 // With SSE4.2, use double quad vector compare
8266 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8267
8268 // Compare 16-byte vectors
8269 andl(result, 0x0000000f); // tail count (in bytes)
8270 andl(len, 0xfffffff0); // vector count (in bytes)
8271 jccb(Assembler::zero, COMPARE_TAIL);
8272
8273 lea(ary1, Address(ary1, len, Address::times_1));
8274 negptr(len);
8275
8276 movl(tmp1, 0x80808080);
8277 movdl(vec2, tmp1);
8278 pshufd(vec2, vec2, 0);
8279
8280 bind(COMPARE_WIDE_VECTORS);
8281 movdqu(vec1, Address(ary1, len, Address::times_1));
8282 ptest(vec1, vec2);
8283 jccb(Assembler::notZero, TRUE_LABEL);
8284 addptr(len, 16);
8285 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8286
8287 testl(result, result);
8288 jccb(Assembler::zero, FALSE_LABEL);
8289
8290 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8291 ptest(vec1, vec2);
8292 jccb(Assembler::notZero, TRUE_LABEL);
8293 jmpb(FALSE_LABEL);
8294
8295 bind(COMPARE_TAIL); // len is zero
8296 movl(len, result);
8297 // Fallthru to tail compare
8298 }
8299 }
8300 // Compare 4-byte vectors
8301 andl(len, 0xfffffffc); // vector count (in bytes)
8302 jccb(Assembler::zero, COMPARE_CHAR);
8303
8304 lea(ary1, Address(ary1, len, Address::times_1));
8305 negptr(len);
8306
8307 bind(COMPARE_VECTORS);
8308 movl(tmp1, Address(ary1, len, Address::times_1));
8309 andl(tmp1, 0x80808080);
8310 jccb(Assembler::notZero, TRUE_LABEL);
8311 addptr(len, 4);
8312 jcc(Assembler::notZero, COMPARE_VECTORS);
8313
8314 // Compare trailing char (final 2 bytes), if any
8315 bind(COMPARE_CHAR);
8316 testl(result, 0x2); // tail char
8317 jccb(Assembler::zero, COMPARE_BYTE);
8318 load_unsigned_short(tmp1, Address(ary1, 0));
8319 andl(tmp1, 0x00008080);
8320 jccb(Assembler::notZero, TRUE_LABEL);
8321 subptr(result, 2);
8322 lea(ary1, Address(ary1, 2));
8323
8324 bind(COMPARE_BYTE);
8325 testl(result, 0x1); // tail byte
8326 jccb(Assembler::zero, FALSE_LABEL);
8327 load_unsigned_byte(tmp1, Address(ary1, 0));
8328 andl(tmp1, 0x00000080);
8329 jccb(Assembler::notEqual, TRUE_LABEL);
8330 jmpb(FALSE_LABEL);
8331
8332 bind(TRUE_LABEL);
8333 movl(result, 1); // return true
8334 jmpb(DONE);
8335
8336 bind(FALSE_LABEL);
8337 xorl(result, result); // return false
8338
8339 // That's it
8340 bind(DONE);
8341 if (UseAVX >= 2 && UseSSE >= 2) {
8342 // clean upper bits of YMM registers
8343 vpxor(vec1, vec1);
8344 vpxor(vec2, vec2);
8345 }
8346 }
8347 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings.
8348 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2,
8349 Register limit, Register result, Register chr,
8350 XMMRegister vec1, XMMRegister vec2, bool is_char) {
8351 ShortBranchVerifier sbv(this);
8352 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE;
8353
8354 int length_offset = arrayOopDesc::length_offset_in_bytes();
8355 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE);
8356
8357 if (is_array_equ) {
8358 // Check the input args
8359 cmpptr(ary1, ary2);
8360 jcc(Assembler::equal, TRUE_LABEL);
8361
8362 // Need additional checks for arrays_equals.
8363 testptr(ary1, ary1);
8364 jcc(Assembler::zero, FALSE_LABEL);
8365 testptr(ary2, ary2);
8366 jcc(Assembler::zero, FALSE_LABEL);
8367
8368 // Check the lengths
8369 movl(limit, Address(ary1, length_offset));
8370 cmpl(limit, Address(ary2, length_offset));
8371 jcc(Assembler::notEqual, FALSE_LABEL);
8372 }
8373
8374 // count == 0
8375 testl(limit, limit);
8376 jcc(Assembler::zero, TRUE_LABEL);
8377
8378 if (is_array_equ) {
8379 // Load array address
8380 lea(ary1, Address(ary1, base_offset));
8381 lea(ary2, Address(ary2, base_offset));
8382 }
8383
8384 if (is_array_equ && is_char) {
8385 // arrays_equals when used for char[].
8386 shll(limit, 1); // byte count != 0
8387 }
8388 movl(result, limit); // copy
8389
8390 if (UseAVX >= 2) {
8391 // With AVX2, use 32-byte vector compare
8392 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8393
8394 // Compare 32-byte vectors
8395 andl(result, 0x0000001f); // tail count (in bytes)
8396 andl(limit, 0xffffffe0); // vector count (in bytes)
8397 jcc(Assembler::zero, COMPARE_TAIL);
8398
8399 lea(ary1, Address(ary1, limit, Address::times_1));
8400 lea(ary2, Address(ary2, limit, Address::times_1));
8401 negptr(limit);
8402
8403 bind(COMPARE_WIDE_VECTORS);
8404
8405 #ifdef _LP64
8406 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop
8407 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3;
8408
8409 cmpl(limit, -64);
8410 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2);
8411
8412 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop
8413
8414 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit);
8415 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit);
8416 kortestql(k7, k7);
8417 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8418 addptr(limit, 64); // update since we already compared at this addr
8419 cmpl(limit, -64);
8420 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3);
8421
8422 // At this point we may still need to compare -limit+result bytes.
8423 // We could execute the next two instruction and just continue via non-wide path:
8424 // cmpl(limit, 0);
8425 // jcc(Assembler::equal, COMPARE_TAIL); // true
8426 // But since we stopped at the points ary{1,2}+limit which are
8427 // not farther than 64 bytes from the ends of arrays ary{1,2}+result
8428 // (|limit| <= 32 and result < 32),
8429 // we may just compare the last 64 bytes.
8430 //
8431 addptr(result, -64); // it is safe, bc we just came from this area
8432 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit);
8433 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit);
8434 kortestql(k7, k7);
8435 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare
8436
8437 jmp(TRUE_LABEL);
8438
8439 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2);
8440
8441 }//if (VM_Version::supports_avx512vlbw())
8442 #endif //_LP64
8443
8444 vmovdqu(vec1, Address(ary1, limit, Address::times_1));
8445 vmovdqu(vec2, Address(ary2, limit, Address::times_1));
8446 vpxor(vec1, vec2);
8447
8448 vptest(vec1, vec1);
8449 jcc(Assembler::notZero, FALSE_LABEL);
8450 addptr(limit, 32);
8451 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8452
8453 testl(result, result);
8454 jcc(Assembler::zero, TRUE_LABEL);
8455
8456 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32));
8457 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32));
8458 vpxor(vec1, vec2);
8459
8460 vptest(vec1, vec1);
8461 jccb(Assembler::notZero, FALSE_LABEL);
8462 jmpb(TRUE_LABEL);
8463
8464 bind(COMPARE_TAIL); // limit is zero
8465 movl(limit, result);
8466 // Fallthru to tail compare
8467 } else if (UseSSE42Intrinsics) {
8468 // With SSE4.2, use double quad vector compare
8469 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL;
8470
8471 // Compare 16-byte vectors
8472 andl(result, 0x0000000f); // tail count (in bytes)
8473 andl(limit, 0xfffffff0); // vector count (in bytes)
8474 jcc(Assembler::zero, COMPARE_TAIL);
8475
8476 lea(ary1, Address(ary1, limit, Address::times_1));
8477 lea(ary2, Address(ary2, limit, Address::times_1));
8478 negptr(limit);
8479
8480 bind(COMPARE_WIDE_VECTORS);
8481 movdqu(vec1, Address(ary1, limit, Address::times_1));
8482 movdqu(vec2, Address(ary2, limit, Address::times_1));
8483 pxor(vec1, vec2);
8484
8485 ptest(vec1, vec1);
8486 jcc(Assembler::notZero, FALSE_LABEL);
8487 addptr(limit, 16);
8488 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS);
8489
8490 testl(result, result);
8491 jcc(Assembler::zero, TRUE_LABEL);
8492
8493 movdqu(vec1, Address(ary1, result, Address::times_1, -16));
8494 movdqu(vec2, Address(ary2, result, Address::times_1, -16));
8495 pxor(vec1, vec2);
8496
8497 ptest(vec1, vec1);
8498 jccb(Assembler::notZero, FALSE_LABEL);
8499 jmpb(TRUE_LABEL);
8500
8501 bind(COMPARE_TAIL); // limit is zero
8502 movl(limit, result);
8503 // Fallthru to tail compare
8504 }
8505
8506 // Compare 4-byte vectors
8507 andl(limit, 0xfffffffc); // vector count (in bytes)
8508 jccb(Assembler::zero, COMPARE_CHAR);
8509
8510 lea(ary1, Address(ary1, limit, Address::times_1));
8511 lea(ary2, Address(ary2, limit, Address::times_1));
8512 negptr(limit);
8513
8514 bind(COMPARE_VECTORS);
8515 movl(chr, Address(ary1, limit, Address::times_1));
8516 cmpl(chr, Address(ary2, limit, Address::times_1));
8517 jccb(Assembler::notEqual, FALSE_LABEL);
8518 addptr(limit, 4);
8519 jcc(Assembler::notZero, COMPARE_VECTORS);
8520
8521 // Compare trailing char (final 2 bytes), if any
8522 bind(COMPARE_CHAR);
8523 testl(result, 0x2); // tail char
8524 jccb(Assembler::zero, COMPARE_BYTE);
8525 load_unsigned_short(chr, Address(ary1, 0));
8526 load_unsigned_short(limit, Address(ary2, 0));
8527 cmpl(chr, limit);
8528 jccb(Assembler::notEqual, FALSE_LABEL);
8529
8530 if (is_array_equ && is_char) {
8531 bind(COMPARE_BYTE);
8532 } else {
8533 lea(ary1, Address(ary1, 2));
8534 lea(ary2, Address(ary2, 2));
8535
8536 bind(COMPARE_BYTE);
8537 testl(result, 0x1); // tail byte
8538 jccb(Assembler::zero, TRUE_LABEL);
8539 load_unsigned_byte(chr, Address(ary1, 0));
8540 load_unsigned_byte(limit, Address(ary2, 0));
8541 cmpl(chr, limit);
8542 jccb(Assembler::notEqual, FALSE_LABEL);
8543 }
8544 bind(TRUE_LABEL);
8545 movl(result, 1); // return true
8546 jmpb(DONE);
8547
8548 bind(FALSE_LABEL);
8549 xorl(result, result); // return false
8550
8551 // That's it
8552 bind(DONE);
8553 if (UseAVX >= 2) {
8554 // clean upper bits of YMM registers
8555 vpxor(vec1, vec1);
8556 vpxor(vec2, vec2);
8557 }
8558 }
8559
8560 #endif
8561
8562 void MacroAssembler::generate_fill(BasicType t, bool aligned,
8563 Register to, Register value, Register count,
8564 Register rtmp, XMMRegister xtmp) {
8565 ShortBranchVerifier sbv(this);
8566 assert_different_registers(to, value, count, rtmp);
8567 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte;
8568 Label L_fill_2_bytes, L_fill_4_bytes;
8569
8570 int shift = -1;
8571 switch (t) {
8572 case T_BYTE:
8573 shift = 2;
8574 break;
8575 case T_SHORT:
8576 shift = 1;
8577 break;
8578 case T_INT:
8579 shift = 0;
8580 break;
8581 default: ShouldNotReachHere();
8582 }
8583
8584 if (t == T_BYTE) {
8585 andl(value, 0xff);
8586 movl(rtmp, value);
8587 shll(rtmp, 8);
8588 orl(value, rtmp);
8589 }
8590 if (t == T_SHORT) {
8591 andl(value, 0xffff);
8592 }
8593 if (t == T_BYTE || t == T_SHORT) {
8594 movl(rtmp, value);
8595 shll(rtmp, 16);
8596 orl(value, rtmp);
8597 }
8598
8599 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
8600 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
8601 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
8602 // align source address at 4 bytes address boundary
8603 if (t == T_BYTE) {
8604 // One byte misalignment happens only for byte arrays
8605 testptr(to, 1);
8606 jccb(Assembler::zero, L_skip_align1);
8607 movb(Address(to, 0), value);
8608 increment(to);
8609 decrement(count);
8610 BIND(L_skip_align1);
8611 }
8612 // Two bytes misalignment happens only for byte and short (char) arrays
8613 testptr(to, 2);
8614 jccb(Assembler::zero, L_skip_align2);
8615 movw(Address(to, 0), value);
8616 addptr(to, 2);
8617 subl(count, 1<<(shift-1));
8618 BIND(L_skip_align2);
8619 }
8620 if (UseSSE < 2) {
8621 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8622 // Fill 32-byte chunks
8623 subl(count, 8 << shift);
8624 jcc(Assembler::less, L_check_fill_8_bytes);
8625 align(16);
8626
8627 BIND(L_fill_32_bytes_loop);
8628
8629 for (int i = 0; i < 32; i += 4) {
8630 movl(Address(to, i), value);
8631 }
8632
8633 addptr(to, 32);
8634 subl(count, 8 << shift);
8635 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8636 BIND(L_check_fill_8_bytes);
8637 addl(count, 8 << shift);
8638 jccb(Assembler::zero, L_exit);
8639 jmpb(L_fill_8_bytes);
8640
8641 //
8642 // length is too short, just fill qwords
8643 //
8644 BIND(L_fill_8_bytes_loop);
8645 movl(Address(to, 0), value);
8646 movl(Address(to, 4), value);
8647 addptr(to, 8);
8648 BIND(L_fill_8_bytes);
8649 subl(count, 1 << (shift + 1));
8650 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8651 // fall through to fill 4 bytes
8652 } else {
8653 Label L_fill_32_bytes;
8654 if (!UseUnalignedLoadStores) {
8655 // align to 8 bytes, we know we are 4 byte aligned to start
8656 testptr(to, 4);
8657 jccb(Assembler::zero, L_fill_32_bytes);
8658 movl(Address(to, 0), value);
8659 addptr(to, 4);
8660 subl(count, 1<<shift);
8661 }
8662 BIND(L_fill_32_bytes);
8663 {
8664 assert( UseSSE >= 2, "supported cpu only" );
8665 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
8666 if (UseAVX > 2) {
8667 movl(rtmp, 0xffff);
8668 kmovwl(k1, rtmp);
8669 }
8670 movdl(xtmp, value);
8671 if (UseAVX > 2 && UseUnalignedLoadStores) {
8672 // Fill 64-byte chunks
8673 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8674 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
8675
8676 subl(count, 16 << shift);
8677 jcc(Assembler::less, L_check_fill_32_bytes);
8678 align(16);
8679
8680 BIND(L_fill_64_bytes_loop);
8681 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
8682 addptr(to, 64);
8683 subl(count, 16 << shift);
8684 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8685
8686 BIND(L_check_fill_32_bytes);
8687 addl(count, 8 << shift);
8688 jccb(Assembler::less, L_check_fill_8_bytes);
8689 vmovdqu(Address(to, 0), xtmp);
8690 addptr(to, 32);
8691 subl(count, 8 << shift);
8692
8693 BIND(L_check_fill_8_bytes);
8694 } else if (UseAVX == 2 && UseUnalignedLoadStores) {
8695 // Fill 64-byte chunks
8696 Label L_fill_64_bytes_loop, L_check_fill_32_bytes;
8697 vpbroadcastd(xtmp, xtmp);
8698
8699 subl(count, 16 << shift);
8700 jcc(Assembler::less, L_check_fill_32_bytes);
8701 align(16);
8702
8703 BIND(L_fill_64_bytes_loop);
8704 vmovdqu(Address(to, 0), xtmp);
8705 vmovdqu(Address(to, 32), xtmp);
8706 addptr(to, 64);
8707 subl(count, 16 << shift);
8708 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
8709
8710 BIND(L_check_fill_32_bytes);
8711 addl(count, 8 << shift);
8712 jccb(Assembler::less, L_check_fill_8_bytes);
8713 vmovdqu(Address(to, 0), xtmp);
8714 addptr(to, 32);
8715 subl(count, 8 << shift);
8716
8717 BIND(L_check_fill_8_bytes);
8718 // clean upper bits of YMM registers
8719 movdl(xtmp, value);
8720 pshufd(xtmp, xtmp, 0);
8721 } else {
8722 // Fill 32-byte chunks
8723 pshufd(xtmp, xtmp, 0);
8724
8725 subl(count, 8 << shift);
8726 jcc(Assembler::less, L_check_fill_8_bytes);
8727 align(16);
8728
8729 BIND(L_fill_32_bytes_loop);
8730
8731 if (UseUnalignedLoadStores) {
8732 movdqu(Address(to, 0), xtmp);
8733 movdqu(Address(to, 16), xtmp);
8734 } else {
8735 movq(Address(to, 0), xtmp);
8736 movq(Address(to, 8), xtmp);
8737 movq(Address(to, 16), xtmp);
8738 movq(Address(to, 24), xtmp);
8739 }
8740
8741 addptr(to, 32);
8742 subl(count, 8 << shift);
8743 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
8744
8745 BIND(L_check_fill_8_bytes);
8746 }
8747 addl(count, 8 << shift);
8748 jccb(Assembler::zero, L_exit);
8749 jmpb(L_fill_8_bytes);
8750
8751 //
8752 // length is too short, just fill qwords
8753 //
8754 BIND(L_fill_8_bytes_loop);
8755 movq(Address(to, 0), xtmp);
8756 addptr(to, 8);
8757 BIND(L_fill_8_bytes);
8758 subl(count, 1 << (shift + 1));
8759 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
8760 }
8761 }
8762 // fill trailing 4 bytes
8763 BIND(L_fill_4_bytes);
8764 testl(count, 1<<shift);
8765 jccb(Assembler::zero, L_fill_2_bytes);
8766 movl(Address(to, 0), value);
8767 if (t == T_BYTE || t == T_SHORT) {
8768 addptr(to, 4);
8769 BIND(L_fill_2_bytes);
8770 // fill trailing 2 bytes
8771 testl(count, 1<<(shift-1));
8772 jccb(Assembler::zero, L_fill_byte);
8773 movw(Address(to, 0), value);
8774 if (t == T_BYTE) {
8775 addptr(to, 2);
8776 BIND(L_fill_byte);
8777 // fill trailing byte
8778 testl(count, 1);
8779 jccb(Assembler::zero, L_exit);
8780 movb(Address(to, 0), value);
8781 } else {
8782 BIND(L_fill_byte);
8783 }
8784 } else {
8785 BIND(L_fill_2_bytes);
8786 }
8787 BIND(L_exit);
8788 }
8789
8790 // encode char[] to byte[] in ISO_8859_1
8791 //@HotSpotIntrinsicCandidate
8792 //private static int implEncodeISOArray(byte[] sa, int sp,
8793 //byte[] da, int dp, int len) {
8794 // int i = 0;
8795 // for (; i < len; i++) {
8796 // char c = StringUTF16.getChar(sa, sp++);
8797 // if (c > '\u00FF')
8798 // break;
8799 // da[dp++] = (byte)c;
8800 // }
8801 // return i;
8802 //}
8803 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
8804 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8805 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8806 Register tmp5, Register result) {
8807
8808 // rsi: src
8809 // rdi: dst
8810 // rdx: len
8811 // rcx: tmp5
8812 // rax: result
8813 ShortBranchVerifier sbv(this);
8814 assert_different_registers(src, dst, len, tmp5, result);
8815 Label L_done, L_copy_1_char, L_copy_1_char_exit;
8816
8817 // set result
8818 xorl(result, result);
8819 // check for zero length
8820 testl(len, len);
8821 jcc(Assembler::zero, L_done);
8822
8823 movl(result, len);
8824
8825 // Setup pointers
8826 lea(src, Address(src, len, Address::times_2)); // char[]
8827 lea(dst, Address(dst, len, Address::times_1)); // byte[]
8828 negptr(len);
8829
8830 if (UseSSE42Intrinsics || UseAVX >= 2) {
8831 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit;
8832 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
8833
8834 if (UseAVX >= 2) {
8835 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
8836 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8837 movdl(tmp1Reg, tmp5);
8838 vpbroadcastd(tmp1Reg, tmp1Reg);
8839 jmp(L_chars_32_check);
8840
8841 bind(L_copy_32_chars);
8842 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
8843 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
8844 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8845 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8846 jccb(Assembler::notZero, L_copy_32_chars_exit);
8847 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
8848 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
8849 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
8850
8851 bind(L_chars_32_check);
8852 addptr(len, 32);
8853 jcc(Assembler::lessEqual, L_copy_32_chars);
8854
8855 bind(L_copy_32_chars_exit);
8856 subptr(len, 16);
8857 jccb(Assembler::greater, L_copy_16_chars_exit);
8858
8859 } else if (UseSSE42Intrinsics) {
8860 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector
8861 movdl(tmp1Reg, tmp5);
8862 pshufd(tmp1Reg, tmp1Reg, 0);
8863 jmpb(L_chars_16_check);
8864 }
8865
8866 bind(L_copy_16_chars);
8867 if (UseAVX >= 2) {
8868 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
8869 vptest(tmp2Reg, tmp1Reg);
8870 jcc(Assembler::notZero, L_copy_16_chars_exit);
8871 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
8872 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
8873 } else {
8874 if (UseAVX > 0) {
8875 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8876 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8877 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
8878 } else {
8879 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
8880 por(tmp2Reg, tmp3Reg);
8881 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
8882 por(tmp2Reg, tmp4Reg);
8883 }
8884 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8885 jccb(Assembler::notZero, L_copy_16_chars_exit);
8886 packuswb(tmp3Reg, tmp4Reg);
8887 }
8888 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
8889
8890 bind(L_chars_16_check);
8891 addptr(len, 16);
8892 jcc(Assembler::lessEqual, L_copy_16_chars);
8893
8894 bind(L_copy_16_chars_exit);
8895 if (UseAVX >= 2) {
8896 // clean upper bits of YMM registers
8897 vpxor(tmp2Reg, tmp2Reg);
8898 vpxor(tmp3Reg, tmp3Reg);
8899 vpxor(tmp4Reg, tmp4Reg);
8900 movdl(tmp1Reg, tmp5);
8901 pshufd(tmp1Reg, tmp1Reg, 0);
8902 }
8903 subptr(len, 8);
8904 jccb(Assembler::greater, L_copy_8_chars_exit);
8905
8906 bind(L_copy_8_chars);
8907 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
8908 ptest(tmp3Reg, tmp1Reg);
8909 jccb(Assembler::notZero, L_copy_8_chars_exit);
8910 packuswb(tmp3Reg, tmp1Reg);
8911 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
8912 addptr(len, 8);
8913 jccb(Assembler::lessEqual, L_copy_8_chars);
8914
8915 bind(L_copy_8_chars_exit);
8916 subptr(len, 8);
8917 jccb(Assembler::zero, L_done);
8918 }
8919
8920 bind(L_copy_1_char);
8921 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
8922 testl(tmp5, 0xff00); // check if Unicode char
8923 jccb(Assembler::notZero, L_copy_1_char_exit);
8924 movb(Address(dst, len, Address::times_1, 0), tmp5);
8925 addptr(len, 1);
8926 jccb(Assembler::less, L_copy_1_char);
8927
8928 bind(L_copy_1_char_exit);
8929 addptr(result, len); // len is negative count of not processed elements
8930
8931 bind(L_done);
8932 }
8933
8934 #ifdef _LP64
8935 /**
8936 * Helper for multiply_to_len().
8937 */
8938 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
8939 addq(dest_lo, src1);
8940 adcq(dest_hi, 0);
8941 addq(dest_lo, src2);
8942 adcq(dest_hi, 0);
8943 }
8944
8945 /**
8946 * Multiply 64 bit by 64 bit first loop.
8947 */
8948 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
8949 Register y, Register y_idx, Register z,
8950 Register carry, Register product,
8951 Register idx, Register kdx) {
8952 //
8953 // jlong carry, x[], y[], z[];
8954 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
8955 // huge_128 product = y[idx] * x[xstart] + carry;
8956 // z[kdx] = (jlong)product;
8957 // carry = (jlong)(product >>> 64);
8958 // }
8959 // z[xstart] = carry;
8960 //
8961
8962 Label L_first_loop, L_first_loop_exit;
8963 Label L_one_x, L_one_y, L_multiply;
8964
8965 decrementl(xstart);
8966 jcc(Assembler::negative, L_one_x);
8967
8968 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
8969 rorq(x_xstart, 32); // convert big-endian to little-endian
8970
8971 bind(L_first_loop);
8972 decrementl(idx);
8973 jcc(Assembler::negative, L_first_loop_exit);
8974 decrementl(idx);
8975 jcc(Assembler::negative, L_one_y);
8976 movq(y_idx, Address(y, idx, Address::times_4, 0));
8977 rorq(y_idx, 32); // convert big-endian to little-endian
8978 bind(L_multiply);
8979 movq(product, x_xstart);
8980 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
8981 addq(product, carry);
8982 adcq(rdx, 0);
8983 subl(kdx, 2);
8984 movl(Address(z, kdx, Address::times_4, 4), product);
8985 shrq(product, 32);
8986 movl(Address(z, kdx, Address::times_4, 0), product);
8987 movq(carry, rdx);
8988 jmp(L_first_loop);
8989
8990 bind(L_one_y);
8991 movl(y_idx, Address(y, 0));
8992 jmp(L_multiply);
8993
8994 bind(L_one_x);
8995 movl(x_xstart, Address(x, 0));
8996 jmp(L_first_loop);
8997
8998 bind(L_first_loop_exit);
8999 }
9000
9001 /**
9002 * Multiply 64 bit by 64 bit and add 128 bit.
9003 */
9004 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
9005 Register yz_idx, Register idx,
9006 Register carry, Register product, int offset) {
9007 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
9008 // z[kdx] = (jlong)product;
9009
9010 movq(yz_idx, Address(y, idx, Address::times_4, offset));
9011 rorq(yz_idx, 32); // convert big-endian to little-endian
9012 movq(product, x_xstart);
9013 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9014 movq(yz_idx, Address(z, idx, Address::times_4, offset));
9015 rorq(yz_idx, 32); // convert big-endian to little-endian
9016
9017 add2_with_carry(rdx, product, carry, yz_idx);
9018
9019 movl(Address(z, idx, Address::times_4, offset+4), product);
9020 shrq(product, 32);
9021 movl(Address(z, idx, Address::times_4, offset), product);
9022
9023 }
9024
9025 /**
9026 * Multiply 128 bit by 128 bit. Unrolled inner loop.
9027 */
9028 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
9029 Register yz_idx, Register idx, Register jdx,
9030 Register carry, Register product,
9031 Register carry2) {
9032 // jlong carry, x[], y[], z[];
9033 // int kdx = ystart+1;
9034 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9035 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
9036 // z[kdx+idx+1] = (jlong)product;
9037 // jlong carry2 = (jlong)(product >>> 64);
9038 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
9039 // z[kdx+idx] = (jlong)product;
9040 // carry = (jlong)(product >>> 64);
9041 // }
9042 // idx += 2;
9043 // if (idx > 0) {
9044 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
9045 // z[kdx+idx] = (jlong)product;
9046 // carry = (jlong)(product >>> 64);
9047 // }
9048 //
9049
9050 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9051
9052 movl(jdx, idx);
9053 andl(jdx, 0xFFFFFFFC);
9054 shrl(jdx, 2);
9055
9056 bind(L_third_loop);
9057 subl(jdx, 1);
9058 jcc(Assembler::negative, L_third_loop_exit);
9059 subl(idx, 4);
9060
9061 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
9062 movq(carry2, rdx);
9063
9064 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
9065 movq(carry, rdx);
9066 jmp(L_third_loop);
9067
9068 bind (L_third_loop_exit);
9069
9070 andl (idx, 0x3);
9071 jcc(Assembler::zero, L_post_third_loop_done);
9072
9073 Label L_check_1;
9074 subl(idx, 2);
9075 jcc(Assembler::negative, L_check_1);
9076
9077 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
9078 movq(carry, rdx);
9079
9080 bind (L_check_1);
9081 addl (idx, 0x2);
9082 andl (idx, 0x1);
9083 subl(idx, 1);
9084 jcc(Assembler::negative, L_post_third_loop_done);
9085
9086 movl(yz_idx, Address(y, idx, Address::times_4, 0));
9087 movq(product, x_xstart);
9088 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
9089 movl(yz_idx, Address(z, idx, Address::times_4, 0));
9090
9091 add2_with_carry(rdx, product, yz_idx, carry);
9092
9093 movl(Address(z, idx, Address::times_4, 0), product);
9094 shrq(product, 32);
9095
9096 shlq(rdx, 32);
9097 orq(product, rdx);
9098 movq(carry, product);
9099
9100 bind(L_post_third_loop_done);
9101 }
9102
9103 /**
9104 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
9105 *
9106 */
9107 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
9108 Register carry, Register carry2,
9109 Register idx, Register jdx,
9110 Register yz_idx1, Register yz_idx2,
9111 Register tmp, Register tmp3, Register tmp4) {
9112 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
9113
9114 // jlong carry, x[], y[], z[];
9115 // int kdx = ystart+1;
9116 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
9117 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
9118 // jlong carry2 = (jlong)(tmp3 >>> 64);
9119 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
9120 // carry = (jlong)(tmp4 >>> 64);
9121 // z[kdx+idx+1] = (jlong)tmp3;
9122 // z[kdx+idx] = (jlong)tmp4;
9123 // }
9124 // idx += 2;
9125 // if (idx > 0) {
9126 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
9127 // z[kdx+idx] = (jlong)yz_idx1;
9128 // carry = (jlong)(yz_idx1 >>> 64);
9129 // }
9130 //
9131
9132 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
9133
9134 movl(jdx, idx);
9135 andl(jdx, 0xFFFFFFFC);
9136 shrl(jdx, 2);
9137
9138 bind(L_third_loop);
9139 subl(jdx, 1);
9140 jcc(Assembler::negative, L_third_loop_exit);
9141 subl(idx, 4);
9142
9143 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
9144 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
9145 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
9146 rorxq(yz_idx2, yz_idx2, 32);
9147
9148 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9149 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
9150
9151 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
9152 rorxq(yz_idx1, yz_idx1, 32);
9153 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9154 rorxq(yz_idx2, yz_idx2, 32);
9155
9156 if (VM_Version::supports_adx()) {
9157 adcxq(tmp3, carry);
9158 adoxq(tmp3, yz_idx1);
9159
9160 adcxq(tmp4, tmp);
9161 adoxq(tmp4, yz_idx2);
9162
9163 movl(carry, 0); // does not affect flags
9164 adcxq(carry2, carry);
9165 adoxq(carry2, carry);
9166 } else {
9167 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
9168 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
9169 }
9170 movq(carry, carry2);
9171
9172 movl(Address(z, idx, Address::times_4, 12), tmp3);
9173 shrq(tmp3, 32);
9174 movl(Address(z, idx, Address::times_4, 8), tmp3);
9175
9176 movl(Address(z, idx, Address::times_4, 4), tmp4);
9177 shrq(tmp4, 32);
9178 movl(Address(z, idx, Address::times_4, 0), tmp4);
9179
9180 jmp(L_third_loop);
9181
9182 bind (L_third_loop_exit);
9183
9184 andl (idx, 0x3);
9185 jcc(Assembler::zero, L_post_third_loop_done);
9186
9187 Label L_check_1;
9188 subl(idx, 2);
9189 jcc(Assembler::negative, L_check_1);
9190
9191 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
9192 rorxq(yz_idx1, yz_idx1, 32);
9193 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
9194 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
9195 rorxq(yz_idx2, yz_idx2, 32);
9196
9197 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
9198
9199 movl(Address(z, idx, Address::times_4, 4), tmp3);
9200 shrq(tmp3, 32);
9201 movl(Address(z, idx, Address::times_4, 0), tmp3);
9202 movq(carry, tmp4);
9203
9204 bind (L_check_1);
9205 addl (idx, 0x2);
9206 andl (idx, 0x1);
9207 subl(idx, 1);
9208 jcc(Assembler::negative, L_post_third_loop_done);
9209 movl(tmp4, Address(y, idx, Address::times_4, 0));
9210 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
9211 movl(tmp4, Address(z, idx, Address::times_4, 0));
9212
9213 add2_with_carry(carry2, tmp3, tmp4, carry);
9214
9215 movl(Address(z, idx, Address::times_4, 0), tmp3);
9216 shrq(tmp3, 32);
9217
9218 shlq(carry2, 32);
9219 orq(tmp3, carry2);
9220 movq(carry, tmp3);
9221
9222 bind(L_post_third_loop_done);
9223 }
9224
9225 /**
9226 * Code for BigInteger::multiplyToLen() instrinsic.
9227 *
9228 * rdi: x
9229 * rax: xlen
9230 * rsi: y
9231 * rcx: ylen
9232 * r8: z
9233 * r11: zlen
9234 * r12: tmp1
9235 * r13: tmp2
9236 * r14: tmp3
9237 * r15: tmp4
9238 * rbx: tmp5
9239 *
9240 */
9241 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
9242 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
9243 ShortBranchVerifier sbv(this);
9244 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
9245
9246 push(tmp1);
9247 push(tmp2);
9248 push(tmp3);
9249 push(tmp4);
9250 push(tmp5);
9251
9252 push(xlen);
9253 push(zlen);
9254
9255 const Register idx = tmp1;
9256 const Register kdx = tmp2;
9257 const Register xstart = tmp3;
9258
9259 const Register y_idx = tmp4;
9260 const Register carry = tmp5;
9261 const Register product = xlen;
9262 const Register x_xstart = zlen; // reuse register
9263
9264 // First Loop.
9265 //
9266 // final static long LONG_MASK = 0xffffffffL;
9267 // int xstart = xlen - 1;
9268 // int ystart = ylen - 1;
9269 // long carry = 0;
9270 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
9271 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
9272 // z[kdx] = (int)product;
9273 // carry = product >>> 32;
9274 // }
9275 // z[xstart] = (int)carry;
9276 //
9277
9278 movl(idx, ylen); // idx = ylen;
9279 movl(kdx, zlen); // kdx = xlen+ylen;
9280 xorq(carry, carry); // carry = 0;
9281
9282 Label L_done;
9283
9284 movl(xstart, xlen);
9285 decrementl(xstart);
9286 jcc(Assembler::negative, L_done);
9287
9288 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
9289
9290 Label L_second_loop;
9291 testl(kdx, kdx);
9292 jcc(Assembler::zero, L_second_loop);
9293
9294 Label L_carry;
9295 subl(kdx, 1);
9296 jcc(Assembler::zero, L_carry);
9297
9298 movl(Address(z, kdx, Address::times_4, 0), carry);
9299 shrq(carry, 32);
9300 subl(kdx, 1);
9301
9302 bind(L_carry);
9303 movl(Address(z, kdx, Address::times_4, 0), carry);
9304
9305 // Second and third (nested) loops.
9306 //
9307 // for (int i = xstart-1; i >= 0; i--) { // Second loop
9308 // carry = 0;
9309 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
9310 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
9311 // (z[k] & LONG_MASK) + carry;
9312 // z[k] = (int)product;
9313 // carry = product >>> 32;
9314 // }
9315 // z[i] = (int)carry;
9316 // }
9317 //
9318 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
9319
9320 const Register jdx = tmp1;
9321
9322 bind(L_second_loop);
9323 xorl(carry, carry); // carry = 0;
9324 movl(jdx, ylen); // j = ystart+1
9325
9326 subl(xstart, 1); // i = xstart-1;
9327 jcc(Assembler::negative, L_done);
9328
9329 push (z);
9330
9331 Label L_last_x;
9332 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
9333 subl(xstart, 1); // i = xstart-1;
9334 jcc(Assembler::negative, L_last_x);
9335
9336 if (UseBMI2Instructions) {
9337 movq(rdx, Address(x, xstart, Address::times_4, 0));
9338 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
9339 } else {
9340 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
9341 rorq(x_xstart, 32); // convert big-endian to little-endian
9342 }
9343
9344 Label L_third_loop_prologue;
9345 bind(L_third_loop_prologue);
9346
9347 push (x);
9348 push (xstart);
9349 push (ylen);
9350
9351
9352 if (UseBMI2Instructions) {
9353 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
9354 } else { // !UseBMI2Instructions
9355 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
9356 }
9357
9358 pop(ylen);
9359 pop(xlen);
9360 pop(x);
9361 pop(z);
9362
9363 movl(tmp3, xlen);
9364 addl(tmp3, 1);
9365 movl(Address(z, tmp3, Address::times_4, 0), carry);
9366 subl(tmp3, 1);
9367 jccb(Assembler::negative, L_done);
9368
9369 shrq(carry, 32);
9370 movl(Address(z, tmp3, Address::times_4, 0), carry);
9371 jmp(L_second_loop);
9372
9373 // Next infrequent code is moved outside loops.
9374 bind(L_last_x);
9375 if (UseBMI2Instructions) {
9376 movl(rdx, Address(x, 0));
9377 } else {
9378 movl(x_xstart, Address(x, 0));
9379 }
9380 jmp(L_third_loop_prologue);
9381
9382 bind(L_done);
9383
9384 pop(zlen);
9385 pop(xlen);
9386
9387 pop(tmp5);
9388 pop(tmp4);
9389 pop(tmp3);
9390 pop(tmp2);
9391 pop(tmp1);
9392 }
9393
9394 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
9395 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
9396 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
9397 Label VECTOR64_LOOP, VECTOR64_TAIL, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
9398 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
9399 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL;
9400 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
9401 Label SAME_TILL_END, DONE;
9402 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
9403
9404 //scale is in rcx in both Win64 and Unix
9405 ShortBranchVerifier sbv(this);
9406
9407 shlq(length);
9408 xorq(result, result);
9409
9410 if ((UseAVX > 2) &&
9411 VM_Version::supports_avx512vlbw()) {
9412 set_vector_masking(); // opening of the stub context for programming mask registers
9413 cmpq(length, 64);
9414 jcc(Assembler::less, VECTOR32_TAIL);
9415 movq(tmp1, length);
9416 andq(tmp1, 0x3F); // tail count
9417 andq(length, ~(0x3F)); //vector count
9418
9419 bind(VECTOR64_LOOP);
9420 // AVX512 code to compare 64 byte vectors.
9421 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
9422 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
9423 kortestql(k7, k7);
9424 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
9425 addq(result, 64);
9426 subq(length, 64);
9427 jccb(Assembler::notZero, VECTOR64_LOOP);
9428
9429 //bind(VECTOR64_TAIL);
9430 testq(tmp1, tmp1);
9431 jcc(Assembler::zero, SAME_TILL_END);
9432
9433 bind(VECTOR64_TAIL);
9434 // AVX512 code to compare upto 63 byte vectors.
9435 // Save k1
9436 kmovql(k3, k1);
9437 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
9438 shlxq(tmp2, tmp2, tmp1);
9439 notq(tmp2);
9440 kmovql(k1, tmp2);
9441
9442 evmovdqub(rymm0, k1, Address(obja, result), Assembler::AVX_512bit);
9443 evpcmpeqb(k7, k1, rymm0, Address(objb, result), Assembler::AVX_512bit);
9444
9445 ktestql(k7, k1);
9446 // Restore k1
9447 kmovql(k1, k3);
9448 jcc(Assembler::below, SAME_TILL_END); // not mismatch
9449
9450 bind(VECTOR64_NOT_EQUAL);
9451 kmovql(tmp1, k7);
9452 notq(tmp1);
9453 tzcntq(tmp1, tmp1);
9454 addq(result, tmp1);
9455 shrq(result);
9456 jmp(DONE);
9457 bind(VECTOR32_TAIL);
9458 clear_vector_masking(); // closing of the stub context for programming mask registers
9459 }
9460
9461 cmpq(length, 8);
9462 jcc(Assembler::equal, VECTOR8_LOOP);
9463 jcc(Assembler::less, VECTOR4_TAIL);
9464
9465 if (UseAVX >= 2) {
9466
9467 cmpq(length, 16);
9468 jcc(Assembler::equal, VECTOR16_LOOP);
9469 jcc(Assembler::less, VECTOR8_LOOP);
9470
9471 cmpq(length, 32);
9472 jccb(Assembler::less, VECTOR16_TAIL);
9473
9474 subq(length, 32);
9475 bind(VECTOR32_LOOP);
9476 vmovdqu(rymm0, Address(obja, result));
9477 vmovdqu(rymm1, Address(objb, result));
9478 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
9479 vptest(rymm2, rymm2);
9480 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
9481 addq(result, 32);
9482 subq(length, 32);
9483 jccb(Assembler::greaterEqual, VECTOR32_LOOP);
9484 addq(length, 32);
9485 jcc(Assembler::equal, SAME_TILL_END);
9486 //falling through if less than 32 bytes left //close the branch here.
9487
9488 bind(VECTOR16_TAIL);
9489 cmpq(length, 16);
9490 jccb(Assembler::less, VECTOR8_TAIL);
9491 bind(VECTOR16_LOOP);
9492 movdqu(rymm0, Address(obja, result));
9493 movdqu(rymm1, Address(objb, result));
9494 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
9495 ptest(rymm2, rymm2);
9496 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9497 addq(result, 16);
9498 subq(length, 16);
9499 jcc(Assembler::equal, SAME_TILL_END);
9500 //falling through if less than 16 bytes left
9501 } else {//regular intrinsics
9502
9503 cmpq(length, 16);
9504 jccb(Assembler::less, VECTOR8_TAIL);
9505
9506 subq(length, 16);
9507 bind(VECTOR16_LOOP);
9508 movdqu(rymm0, Address(obja, result));
9509 movdqu(rymm1, Address(objb, result));
9510 pxor(rymm0, rymm1);
9511 ptest(rymm0, rymm0);
9512 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
9513 addq(result, 16);
9514 subq(length, 16);
9515 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
9516 addq(length, 16);
9517 jcc(Assembler::equal, SAME_TILL_END);
9518 //falling through if less than 16 bytes left
9519 }
9520
9521 bind(VECTOR8_TAIL);
9522 cmpq(length, 8);
9523 jccb(Assembler::less, VECTOR4_TAIL);
9524 bind(VECTOR8_LOOP);
9525 movq(tmp1, Address(obja, result));
9526 movq(tmp2, Address(objb, result));
9527 xorq(tmp1, tmp2);
9528 testq(tmp1, tmp1);
9529 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
9530 addq(result, 8);
9531 subq(length, 8);
9532 jcc(Assembler::equal, SAME_TILL_END);
9533 //falling through if less than 8 bytes left
9534
9535 bind(VECTOR4_TAIL);
9536 cmpq(length, 4);
9537 jccb(Assembler::less, BYTES_TAIL);
9538 bind(VECTOR4_LOOP);
9539 movl(tmp1, Address(obja, result));
9540 xorl(tmp1, Address(objb, result));
9541 testl(tmp1, tmp1);
9542 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
9543 addq(result, 4);
9544 subq(length, 4);
9545 jcc(Assembler::equal, SAME_TILL_END);
9546 //falling through if less than 4 bytes left
9547
9548 bind(BYTES_TAIL);
9549 bind(BYTES_LOOP);
9550 load_unsigned_byte(tmp1, Address(obja, result));
9551 load_unsigned_byte(tmp2, Address(objb, result));
9552 xorl(tmp1, tmp2);
9553 testl(tmp1, tmp1);
9554 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9555 decq(length);
9556 jccb(Assembler::zero, SAME_TILL_END);
9557 incq(result);
9558 load_unsigned_byte(tmp1, Address(obja, result));
9559 load_unsigned_byte(tmp2, Address(objb, result));
9560 xorl(tmp1, tmp2);
9561 testl(tmp1, tmp1);
9562 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9563 decq(length);
9564 jccb(Assembler::zero, SAME_TILL_END);
9565 incq(result);
9566 load_unsigned_byte(tmp1, Address(obja, result));
9567 load_unsigned_byte(tmp2, Address(objb, result));
9568 xorl(tmp1, tmp2);
9569 testl(tmp1, tmp1);
9570 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
9571 jmpb(SAME_TILL_END);
9572
9573 if (UseAVX >= 2) {
9574 bind(VECTOR32_NOT_EQUAL);
9575 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
9576 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
9577 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
9578 vpmovmskb(tmp1, rymm0);
9579 bsfq(tmp1, tmp1);
9580 addq(result, tmp1);
9581 shrq(result);
9582 jmpb(DONE);
9583 }
9584
9585 bind(VECTOR16_NOT_EQUAL);
9586 if (UseAVX >= 2) {
9587 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
9588 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
9589 pxor(rymm0, rymm2);
9590 } else {
9591 pcmpeqb(rymm2, rymm2);
9592 pxor(rymm0, rymm1);
9593 pcmpeqb(rymm0, rymm1);
9594 pxor(rymm0, rymm2);
9595 }
9596 pmovmskb(tmp1, rymm0);
9597 bsfq(tmp1, tmp1);
9598 addq(result, tmp1);
9599 shrq(result);
9600 jmpb(DONE);
9601
9602 bind(VECTOR8_NOT_EQUAL);
9603 bind(VECTOR4_NOT_EQUAL);
9604 bsfq(tmp1, tmp1);
9605 shrq(tmp1, 3);
9606 addq(result, tmp1);
9607 bind(BYTES_NOT_EQUAL);
9608 shrq(result);
9609 jmpb(DONE);
9610
9611 bind(SAME_TILL_END);
9612 mov64(result, -1);
9613
9614 bind(DONE);
9615 }
9616
9617 //Helper functions for square_to_len()
9618
9619 /**
9620 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
9621 * Preserves x and z and modifies rest of the registers.
9622 */
9623 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9624 // Perform square and right shift by 1
9625 // Handle odd xlen case first, then for even xlen do the following
9626 // jlong carry = 0;
9627 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
9628 // huge_128 product = x[j:j+1] * x[j:j+1];
9629 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
9630 // z[i+2:i+3] = (jlong)(product >>> 1);
9631 // carry = (jlong)product;
9632 // }
9633
9634 xorq(tmp5, tmp5); // carry
9635 xorq(rdxReg, rdxReg);
9636 xorl(tmp1, tmp1); // index for x
9637 xorl(tmp4, tmp4); // index for z
9638
9639 Label L_first_loop, L_first_loop_exit;
9640
9641 testl(xlen, 1);
9642 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
9643
9644 // Square and right shift by 1 the odd element using 32 bit multiply
9645 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
9646 imulq(raxReg, raxReg);
9647 shrq(raxReg, 1);
9648 adcq(tmp5, 0);
9649 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
9650 incrementl(tmp1);
9651 addl(tmp4, 2);
9652
9653 // Square and right shift by 1 the rest using 64 bit multiply
9654 bind(L_first_loop);
9655 cmpptr(tmp1, xlen);
9656 jccb(Assembler::equal, L_first_loop_exit);
9657
9658 // Square
9659 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
9660 rorq(raxReg, 32); // convert big-endian to little-endian
9661 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
9662
9663 // Right shift by 1 and save carry
9664 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
9665 rcrq(rdxReg, 1);
9666 rcrq(raxReg, 1);
9667 adcq(tmp5, 0);
9668
9669 // Store result in z
9670 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
9671 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
9672
9673 // Update indices for x and z
9674 addl(tmp1, 2);
9675 addl(tmp4, 4);
9676 jmp(L_first_loop);
9677
9678 bind(L_first_loop_exit);
9679 }
9680
9681
9682 /**
9683 * Perform the following multiply add operation using BMI2 instructions
9684 * carry:sum = sum + op1*op2 + carry
9685 * op2 should be in rdx
9686 * op2 is preserved, all other registers are modified
9687 */
9688 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
9689 // assert op2 is rdx
9690 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
9691 addq(sum, carry);
9692 adcq(tmp2, 0);
9693 addq(sum, op1);
9694 adcq(tmp2, 0);
9695 movq(carry, tmp2);
9696 }
9697
9698 /**
9699 * Perform the following multiply add operation:
9700 * carry:sum = sum + op1*op2 + carry
9701 * Preserves op1, op2 and modifies rest of registers
9702 */
9703 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
9704 // rdx:rax = op1 * op2
9705 movq(raxReg, op2);
9706 mulq(op1);
9707
9708 // rdx:rax = sum + carry + rdx:rax
9709 addq(sum, carry);
9710 adcq(rdxReg, 0);
9711 addq(sum, raxReg);
9712 adcq(rdxReg, 0);
9713
9714 // carry:sum = rdx:sum
9715 movq(carry, rdxReg);
9716 }
9717
9718 /**
9719 * Add 64 bit long carry into z[] with carry propogation.
9720 * Preserves z and carry register values and modifies rest of registers.
9721 *
9722 */
9723 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
9724 Label L_fourth_loop, L_fourth_loop_exit;
9725
9726 movl(tmp1, 1);
9727 subl(zlen, 2);
9728 addq(Address(z, zlen, Address::times_4, 0), carry);
9729
9730 bind(L_fourth_loop);
9731 jccb(Assembler::carryClear, L_fourth_loop_exit);
9732 subl(zlen, 2);
9733 jccb(Assembler::negative, L_fourth_loop_exit);
9734 addq(Address(z, zlen, Address::times_4, 0), tmp1);
9735 jmp(L_fourth_loop);
9736 bind(L_fourth_loop_exit);
9737 }
9738
9739 /**
9740 * Shift z[] left by 1 bit.
9741 * Preserves x, len, z and zlen registers and modifies rest of the registers.
9742 *
9743 */
9744 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
9745
9746 Label L_fifth_loop, L_fifth_loop_exit;
9747
9748 // Fifth loop
9749 // Perform primitiveLeftShift(z, zlen, 1)
9750
9751 const Register prev_carry = tmp1;
9752 const Register new_carry = tmp4;
9753 const Register value = tmp2;
9754 const Register zidx = tmp3;
9755
9756 // int zidx, carry;
9757 // long value;
9758 // carry = 0;
9759 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
9760 // (carry:value) = (z[i] << 1) | carry ;
9761 // z[i] = value;
9762 // }
9763
9764 movl(zidx, zlen);
9765 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
9766
9767 bind(L_fifth_loop);
9768 decl(zidx); // Use decl to preserve carry flag
9769 decl(zidx);
9770 jccb(Assembler::negative, L_fifth_loop_exit);
9771
9772 if (UseBMI2Instructions) {
9773 movq(value, Address(z, zidx, Address::times_4, 0));
9774 rclq(value, 1);
9775 rorxq(value, value, 32);
9776 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9777 }
9778 else {
9779 // clear new_carry
9780 xorl(new_carry, new_carry);
9781
9782 // Shift z[i] by 1, or in previous carry and save new carry
9783 movq(value, Address(z, zidx, Address::times_4, 0));
9784 shlq(value, 1);
9785 adcl(new_carry, 0);
9786
9787 orq(value, prev_carry);
9788 rorq(value, 0x20);
9789 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
9790
9791 // Set previous carry = new carry
9792 movl(prev_carry, new_carry);
9793 }
9794 jmp(L_fifth_loop);
9795
9796 bind(L_fifth_loop_exit);
9797 }
9798
9799
9800 /**
9801 * Code for BigInteger::squareToLen() intrinsic
9802 *
9803 * rdi: x
9804 * rsi: len
9805 * r8: z
9806 * rcx: zlen
9807 * r12: tmp1
9808 * r13: tmp2
9809 * r14: tmp3
9810 * r15: tmp4
9811 * rbx: tmp5
9812 *
9813 */
9814 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9815
9816 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply;
9817 push(tmp1);
9818 push(tmp2);
9819 push(tmp3);
9820 push(tmp4);
9821 push(tmp5);
9822
9823 // First loop
9824 // Store the squares, right shifted one bit (i.e., divided by 2).
9825 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
9826
9827 // Add in off-diagonal sums.
9828 //
9829 // Second, third (nested) and fourth loops.
9830 // zlen +=2;
9831 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
9832 // carry = 0;
9833 // long op2 = x[xidx:xidx+1];
9834 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
9835 // k -= 2;
9836 // long op1 = x[j:j+1];
9837 // long sum = z[k:k+1];
9838 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
9839 // z[k:k+1] = sum;
9840 // }
9841 // add_one_64(z, k, carry, tmp_regs);
9842 // }
9843
9844 const Register carry = tmp5;
9845 const Register sum = tmp3;
9846 const Register op1 = tmp4;
9847 Register op2 = tmp2;
9848
9849 push(zlen);
9850 push(len);
9851 addl(zlen,2);
9852 bind(L_second_loop);
9853 xorq(carry, carry);
9854 subl(zlen, 4);
9855 subl(len, 2);
9856 push(zlen);
9857 push(len);
9858 cmpl(len, 0);
9859 jccb(Assembler::lessEqual, L_second_loop_exit);
9860
9861 // Multiply an array by one 64 bit long.
9862 if (UseBMI2Instructions) {
9863 op2 = rdxReg;
9864 movq(op2, Address(x, len, Address::times_4, 0));
9865 rorxq(op2, op2, 32);
9866 }
9867 else {
9868 movq(op2, Address(x, len, Address::times_4, 0));
9869 rorq(op2, 32);
9870 }
9871
9872 bind(L_third_loop);
9873 decrementl(len);
9874 jccb(Assembler::negative, L_third_loop_exit);
9875 decrementl(len);
9876 jccb(Assembler::negative, L_last_x);
9877
9878 movq(op1, Address(x, len, Address::times_4, 0));
9879 rorq(op1, 32);
9880
9881 bind(L_multiply);
9882 subl(zlen, 2);
9883 movq(sum, Address(z, zlen, Address::times_4, 0));
9884
9885 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
9886 if (UseBMI2Instructions) {
9887 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
9888 }
9889 else {
9890 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9891 }
9892
9893 movq(Address(z, zlen, Address::times_4, 0), sum);
9894
9895 jmp(L_third_loop);
9896 bind(L_third_loop_exit);
9897
9898 // Fourth loop
9899 // Add 64 bit long carry into z with carry propogation.
9900 // Uses offsetted zlen.
9901 add_one_64(z, zlen, carry, tmp1);
9902
9903 pop(len);
9904 pop(zlen);
9905 jmp(L_second_loop);
9906
9907 // Next infrequent code is moved outside loops.
9908 bind(L_last_x);
9909 movl(op1, Address(x, 0));
9910 jmp(L_multiply);
9911
9912 bind(L_second_loop_exit);
9913 pop(len);
9914 pop(zlen);
9915 pop(len);
9916 pop(zlen);
9917
9918 // Fifth loop
9919 // Shift z left 1 bit.
9920 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
9921
9922 // z[zlen-1] |= x[len-1] & 1;
9923 movl(tmp3, Address(x, len, Address::times_4, -4));
9924 andl(tmp3, 1);
9925 orl(Address(z, zlen, Address::times_4, -4), tmp3);
9926
9927 pop(tmp5);
9928 pop(tmp4);
9929 pop(tmp3);
9930 pop(tmp2);
9931 pop(tmp1);
9932 }
9933
9934 /**
9935 * Helper function for mul_add()
9936 * Multiply the in[] by int k and add to out[] starting at offset offs using
9937 * 128 bit by 32 bit multiply and return the carry in tmp5.
9938 * Only quad int aligned length of in[] is operated on in this function.
9939 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
9940 * This function preserves out, in and k registers.
9941 * len and offset point to the appropriate index in "in" & "out" correspondingly
9942 * tmp5 has the carry.
9943 * other registers are temporary and are modified.
9944 *
9945 */
9946 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
9947 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
9948 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
9949
9950 Label L_first_loop, L_first_loop_exit;
9951
9952 movl(tmp1, len);
9953 shrl(tmp1, 2);
9954
9955 bind(L_first_loop);
9956 subl(tmp1, 1);
9957 jccb(Assembler::negative, L_first_loop_exit);
9958
9959 subl(len, 4);
9960 subl(offset, 4);
9961
9962 Register op2 = tmp2;
9963 const Register sum = tmp3;
9964 const Register op1 = tmp4;
9965 const Register carry = tmp5;
9966
9967 if (UseBMI2Instructions) {
9968 op2 = rdxReg;
9969 }
9970
9971 movq(op1, Address(in, len, Address::times_4, 8));
9972 rorq(op1, 32);
9973 movq(sum, Address(out, offset, Address::times_4, 8));
9974 rorq(sum, 32);
9975 if (UseBMI2Instructions) {
9976 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9977 }
9978 else {
9979 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9980 }
9981 // Store back in big endian from little endian
9982 rorq(sum, 0x20);
9983 movq(Address(out, offset, Address::times_4, 8), sum);
9984
9985 movq(op1, Address(in, len, Address::times_4, 0));
9986 rorq(op1, 32);
9987 movq(sum, Address(out, offset, Address::times_4, 0));
9988 rorq(sum, 32);
9989 if (UseBMI2Instructions) {
9990 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
9991 }
9992 else {
9993 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
9994 }
9995 // Store back in big endian from little endian
9996 rorq(sum, 0x20);
9997 movq(Address(out, offset, Address::times_4, 0), sum);
9998
9999 jmp(L_first_loop);
10000 bind(L_first_loop_exit);
10001 }
10002
10003 /**
10004 * Code for BigInteger::mulAdd() intrinsic
10005 *
10006 * rdi: out
10007 * rsi: in
10008 * r11: offs (out.length - offset)
10009 * rcx: len
10010 * r8: k
10011 * r12: tmp1
10012 * r13: tmp2
10013 * r14: tmp3
10014 * r15: tmp4
10015 * rbx: tmp5
10016 * Multiply the in[] by word k and add to out[], return the carry in rax
10017 */
10018 void MacroAssembler::mul_add(Register out, Register in, Register offs,
10019 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
10020 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
10021
10022 Label L_carry, L_last_in, L_done;
10023
10024 // carry = 0;
10025 // for (int j=len-1; j >= 0; j--) {
10026 // long product = (in[j] & LONG_MASK) * kLong +
10027 // (out[offs] & LONG_MASK) + carry;
10028 // out[offs--] = (int)product;
10029 // carry = product >>> 32;
10030 // }
10031 //
10032 push(tmp1);
10033 push(tmp2);
10034 push(tmp3);
10035 push(tmp4);
10036 push(tmp5);
10037
10038 Register op2 = tmp2;
10039 const Register sum = tmp3;
10040 const Register op1 = tmp4;
10041 const Register carry = tmp5;
10042
10043 if (UseBMI2Instructions) {
10044 op2 = rdxReg;
10045 movl(op2, k);
10046 }
10047 else {
10048 movl(op2, k);
10049 }
10050
10051 xorq(carry, carry);
10052
10053 //First loop
10054
10055 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
10056 //The carry is in tmp5
10057 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
10058
10059 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
10060 decrementl(len);
10061 jccb(Assembler::negative, L_carry);
10062 decrementl(len);
10063 jccb(Assembler::negative, L_last_in);
10064
10065 movq(op1, Address(in, len, Address::times_4, 0));
10066 rorq(op1, 32);
10067
10068 subl(offs, 2);
10069 movq(sum, Address(out, offs, Address::times_4, 0));
10070 rorq(sum, 32);
10071
10072 if (UseBMI2Instructions) {
10073 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
10074 }
10075 else {
10076 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
10077 }
10078
10079 // Store back in big endian from little endian
10080 rorq(sum, 0x20);
10081 movq(Address(out, offs, Address::times_4, 0), sum);
10082
10083 testl(len, len);
10084 jccb(Assembler::zero, L_carry);
10085
10086 //Multiply the last in[] entry, if any
10087 bind(L_last_in);
10088 movl(op1, Address(in, 0));
10089 movl(sum, Address(out, offs, Address::times_4, -4));
10090
10091 movl(raxReg, k);
10092 mull(op1); //tmp4 * eax -> edx:eax
10093 addl(sum, carry);
10094 adcl(rdxReg, 0);
10095 addl(sum, raxReg);
10096 adcl(rdxReg, 0);
10097 movl(carry, rdxReg);
10098
10099 movl(Address(out, offs, Address::times_4, -4), sum);
10100
10101 bind(L_carry);
10102 //return tmp5/carry as carry in rax
10103 movl(rax, carry);
10104
10105 bind(L_done);
10106 pop(tmp5);
10107 pop(tmp4);
10108 pop(tmp3);
10109 pop(tmp2);
10110 pop(tmp1);
10111 }
10112 #endif
10113
10114 /**
10115 * Emits code to update CRC-32 with a byte value according to constants in table
10116 *
10117 * @param [in,out]crc Register containing the crc.
10118 * @param [in]val Register containing the byte to fold into the CRC.
10119 * @param [in]table Register containing the table of crc constants.
10120 *
10121 * uint32_t crc;
10122 * val = crc_table[(val ^ crc) & 0xFF];
10123 * crc = val ^ (crc >> 8);
10124 *
10125 */
10126 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
10127 xorl(val, crc);
10128 andl(val, 0xFF);
10129 shrl(crc, 8); // unsigned shift
10130 xorl(crc, Address(table, val, Address::times_4, 0));
10131 }
10132
10133 /**
10134 * Fold 128-bit data chunk
10135 */
10136 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
10137 if (UseAVX > 0) {
10138 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
10139 vpclmulldq(xcrc, xK, xcrc); // [63:0]
10140 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
10141 pxor(xcrc, xtmp);
10142 } else {
10143 movdqa(xtmp, xcrc);
10144 pclmulhdq(xtmp, xK); // [123:64]
10145 pclmulldq(xcrc, xK); // [63:0]
10146 pxor(xcrc, xtmp);
10147 movdqu(xtmp, Address(buf, offset));
10148 pxor(xcrc, xtmp);
10149 }
10150 }
10151
10152 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
10153 if (UseAVX > 0) {
10154 vpclmulhdq(xtmp, xK, xcrc);
10155 vpclmulldq(xcrc, xK, xcrc);
10156 pxor(xcrc, xbuf);
10157 pxor(xcrc, xtmp);
10158 } else {
10159 movdqa(xtmp, xcrc);
10160 pclmulhdq(xtmp, xK);
10161 pclmulldq(xcrc, xK);
10162 pxor(xcrc, xbuf);
10163 pxor(xcrc, xtmp);
10164 }
10165 }
10166
10167 /**
10168 * 8-bit folds to compute 32-bit CRC
10169 *
10170 * uint64_t xcrc;
10171 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
10172 */
10173 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
10174 movdl(tmp, xcrc);
10175 andl(tmp, 0xFF);
10176 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
10177 psrldq(xcrc, 1); // unsigned shift one byte
10178 pxor(xcrc, xtmp);
10179 }
10180
10181 /**
10182 * uint32_t crc;
10183 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
10184 */
10185 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
10186 movl(tmp, crc);
10187 andl(tmp, 0xFF);
10188 shrl(crc, 8);
10189 xorl(crc, Address(table, tmp, Address::times_4, 0));
10190 }
10191
10192 /**
10193 * @param crc register containing existing CRC (32-bit)
10194 * @param buf register pointing to input byte buffer (byte*)
10195 * @param len register containing number of bytes
10196 * @param table register that will contain address of CRC table
10197 * @param tmp scratch register
10198 */
10199 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
10200 assert_different_registers(crc, buf, len, table, tmp, rax);
10201
10202 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
10203 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
10204
10205 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
10206 // context for the registers used, where all instructions below are using 128-bit mode
10207 // On EVEX without VL and BW, these instructions will all be AVX.
10208 if (VM_Version::supports_avx512vlbw()) {
10209 movl(tmp, 0xffff);
10210 kmovwl(k1, tmp);
10211 }
10212
10213 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
10214 notl(crc); // ~crc
10215 cmpl(len, 16);
10216 jcc(Assembler::less, L_tail);
10217
10218 // Align buffer to 16 bytes
10219 movl(tmp, buf);
10220 andl(tmp, 0xF);
10221 jccb(Assembler::zero, L_aligned);
10222 subl(tmp, 16);
10223 addl(len, tmp);
10224
10225 align(4);
10226 BIND(L_align_loop);
10227 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10228 update_byte_crc32(crc, rax, table);
10229 increment(buf);
10230 incrementl(tmp);
10231 jccb(Assembler::less, L_align_loop);
10232
10233 BIND(L_aligned);
10234 movl(tmp, len); // save
10235 shrl(len, 4);
10236 jcc(Assembler::zero, L_tail_restore);
10237
10238 // Fold crc into first bytes of vector
10239 movdqa(xmm1, Address(buf, 0));
10240 movdl(rax, xmm1);
10241 xorl(crc, rax);
10242 if (VM_Version::supports_sse4_1()) {
10243 pinsrd(xmm1, crc, 0);
10244 } else {
10245 pinsrw(xmm1, crc, 0);
10246 shrl(crc, 16);
10247 pinsrw(xmm1, crc, 1);
10248 }
10249 addptr(buf, 16);
10250 subl(len, 4); // len > 0
10251 jcc(Assembler::less, L_fold_tail);
10252
10253 movdqa(xmm2, Address(buf, 0));
10254 movdqa(xmm3, Address(buf, 16));
10255 movdqa(xmm4, Address(buf, 32));
10256 addptr(buf, 48);
10257 subl(len, 3);
10258 jcc(Assembler::lessEqual, L_fold_512b);
10259
10260 // Fold total 512 bits of polynomial on each iteration,
10261 // 128 bits per each of 4 parallel streams.
10262 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
10263
10264 align(32);
10265 BIND(L_fold_512b_loop);
10266 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10267 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
10268 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
10269 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
10270 addptr(buf, 64);
10271 subl(len, 4);
10272 jcc(Assembler::greater, L_fold_512b_loop);
10273
10274 // Fold 512 bits to 128 bits.
10275 BIND(L_fold_512b);
10276 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10277 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
10278 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
10279 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
10280
10281 // Fold the rest of 128 bits data chunks
10282 BIND(L_fold_tail);
10283 addl(len, 3);
10284 jccb(Assembler::lessEqual, L_fold_128b);
10285 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
10286
10287 BIND(L_fold_tail_loop);
10288 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
10289 addptr(buf, 16);
10290 decrementl(len);
10291 jccb(Assembler::greater, L_fold_tail_loop);
10292
10293 // Fold 128 bits in xmm1 down into 32 bits in crc register.
10294 BIND(L_fold_128b);
10295 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
10296 if (UseAVX > 0) {
10297 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
10298 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
10299 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
10300 } else {
10301 movdqa(xmm2, xmm0);
10302 pclmulqdq(xmm2, xmm1, 0x1);
10303 movdqa(xmm3, xmm0);
10304 pand(xmm3, xmm2);
10305 pclmulqdq(xmm0, xmm3, 0x1);
10306 }
10307 psrldq(xmm1, 8);
10308 psrldq(xmm2, 4);
10309 pxor(xmm0, xmm1);
10310 pxor(xmm0, xmm2);
10311
10312 // 8 8-bit folds to compute 32-bit CRC.
10313 for (int j = 0; j < 4; j++) {
10314 fold_8bit_crc32(xmm0, table, xmm1, rax);
10315 }
10316 movdl(crc, xmm0); // mov 32 bits to general register
10317 for (int j = 0; j < 4; j++) {
10318 fold_8bit_crc32(crc, table, rax);
10319 }
10320
10321 BIND(L_tail_restore);
10322 movl(len, tmp); // restore
10323 BIND(L_tail);
10324 andl(len, 0xf);
10325 jccb(Assembler::zero, L_exit);
10326
10327 // Fold the rest of bytes
10328 align(4);
10329 BIND(L_tail_loop);
10330 movsbl(rax, Address(buf, 0)); // load byte with sign extension
10331 update_byte_crc32(crc, rax, table);
10332 increment(buf);
10333 decrementl(len);
10334 jccb(Assembler::greater, L_tail_loop);
10335
10336 BIND(L_exit);
10337 notl(crc); // ~c
10338 }
10339
10340 #ifdef _LP64
10341 // S. Gueron / Information Processing Letters 112 (2012) 184
10342 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
10343 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
10344 // Output: the 64-bit carry-less product of B * CONST
10345 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
10346 Register tmp1, Register tmp2, Register tmp3) {
10347 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10348 if (n > 0) {
10349 addq(tmp3, n * 256 * 8);
10350 }
10351 // Q1 = TABLEExt[n][B & 0xFF];
10352 movl(tmp1, in);
10353 andl(tmp1, 0x000000FF);
10354 shll(tmp1, 3);
10355 addq(tmp1, tmp3);
10356 movq(tmp1, Address(tmp1, 0));
10357
10358 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10359 movl(tmp2, in);
10360 shrl(tmp2, 8);
10361 andl(tmp2, 0x000000FF);
10362 shll(tmp2, 3);
10363 addq(tmp2, tmp3);
10364 movq(tmp2, Address(tmp2, 0));
10365
10366 shlq(tmp2, 8);
10367 xorq(tmp1, tmp2);
10368
10369 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10370 movl(tmp2, in);
10371 shrl(tmp2, 16);
10372 andl(tmp2, 0x000000FF);
10373 shll(tmp2, 3);
10374 addq(tmp2, tmp3);
10375 movq(tmp2, Address(tmp2, 0));
10376
10377 shlq(tmp2, 16);
10378 xorq(tmp1, tmp2);
10379
10380 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10381 shrl(in, 24);
10382 andl(in, 0x000000FF);
10383 shll(in, 3);
10384 addq(in, tmp3);
10385 movq(in, Address(in, 0));
10386
10387 shlq(in, 24);
10388 xorq(in, tmp1);
10389 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10390 }
10391
10392 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10393 Register in_out,
10394 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10395 XMMRegister w_xtmp2,
10396 Register tmp1,
10397 Register n_tmp2, Register n_tmp3) {
10398 if (is_pclmulqdq_supported) {
10399 movdl(w_xtmp1, in_out); // modified blindly
10400
10401 movl(tmp1, const_or_pre_comp_const_index);
10402 movdl(w_xtmp2, tmp1);
10403 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10404
10405 movdq(in_out, w_xtmp1);
10406 } else {
10407 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
10408 }
10409 }
10410
10411 // Recombination Alternative 2: No bit-reflections
10412 // T1 = (CRC_A * U1) << 1
10413 // T2 = (CRC_B * U2) << 1
10414 // C1 = T1 >> 32
10415 // C2 = T2 >> 32
10416 // T1 = T1 & 0xFFFFFFFF
10417 // T2 = T2 & 0xFFFFFFFF
10418 // T1 = CRC32(0, T1)
10419 // T2 = CRC32(0, T2)
10420 // C1 = C1 ^ T1
10421 // C2 = C2 ^ T2
10422 // CRC = C1 ^ C2 ^ CRC_C
10423 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10424 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10425 Register tmp1, Register tmp2,
10426 Register n_tmp3) {
10427 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10428 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10429 shlq(in_out, 1);
10430 movl(tmp1, in_out);
10431 shrq(in_out, 32);
10432 xorl(tmp2, tmp2);
10433 crc32(tmp2, tmp1, 4);
10434 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
10435 shlq(in1, 1);
10436 movl(tmp1, in1);
10437 shrq(in1, 32);
10438 xorl(tmp2, tmp2);
10439 crc32(tmp2, tmp1, 4);
10440 xorl(in1, tmp2);
10441 xorl(in_out, in1);
10442 xorl(in_out, in2);
10443 }
10444
10445 // Set N to predefined value
10446 // Subtract from a lenght of a buffer
10447 // execute in a loop:
10448 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
10449 // for i = 1 to N do
10450 // CRC_A = CRC32(CRC_A, A[i])
10451 // CRC_B = CRC32(CRC_B, B[i])
10452 // CRC_C = CRC32(CRC_C, C[i])
10453 // end for
10454 // Recombine
10455 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10456 Register in_out1, Register in_out2, Register in_out3,
10457 Register tmp1, Register tmp2, Register tmp3,
10458 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10459 Register tmp4, Register tmp5,
10460 Register n_tmp6) {
10461 Label L_processPartitions;
10462 Label L_processPartition;
10463 Label L_exit;
10464
10465 bind(L_processPartitions);
10466 cmpl(in_out1, 3 * size);
10467 jcc(Assembler::less, L_exit);
10468 xorl(tmp1, tmp1);
10469 xorl(tmp2, tmp2);
10470 movq(tmp3, in_out2);
10471 addq(tmp3, size);
10472
10473 bind(L_processPartition);
10474 crc32(in_out3, Address(in_out2, 0), 8);
10475 crc32(tmp1, Address(in_out2, size), 8);
10476 crc32(tmp2, Address(in_out2, size * 2), 8);
10477 addq(in_out2, 8);
10478 cmpq(in_out2, tmp3);
10479 jcc(Assembler::less, L_processPartition);
10480 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10481 w_xtmp1, w_xtmp2, w_xtmp3,
10482 tmp4, tmp5,
10483 n_tmp6);
10484 addq(in_out2, 2 * size);
10485 subl(in_out1, 3 * size);
10486 jmp(L_processPartitions);
10487
10488 bind(L_exit);
10489 }
10490 #else
10491 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
10492 Register tmp1, Register tmp2, Register tmp3,
10493 XMMRegister xtmp1, XMMRegister xtmp2) {
10494 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
10495 if (n > 0) {
10496 addl(tmp3, n * 256 * 8);
10497 }
10498 // Q1 = TABLEExt[n][B & 0xFF];
10499 movl(tmp1, in_out);
10500 andl(tmp1, 0x000000FF);
10501 shll(tmp1, 3);
10502 addl(tmp1, tmp3);
10503 movq(xtmp1, Address(tmp1, 0));
10504
10505 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
10506 movl(tmp2, in_out);
10507 shrl(tmp2, 8);
10508 andl(tmp2, 0x000000FF);
10509 shll(tmp2, 3);
10510 addl(tmp2, tmp3);
10511 movq(xtmp2, Address(tmp2, 0));
10512
10513 psllq(xtmp2, 8);
10514 pxor(xtmp1, xtmp2);
10515
10516 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
10517 movl(tmp2, in_out);
10518 shrl(tmp2, 16);
10519 andl(tmp2, 0x000000FF);
10520 shll(tmp2, 3);
10521 addl(tmp2, tmp3);
10522 movq(xtmp2, Address(tmp2, 0));
10523
10524 psllq(xtmp2, 16);
10525 pxor(xtmp1, xtmp2);
10526
10527 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
10528 shrl(in_out, 24);
10529 andl(in_out, 0x000000FF);
10530 shll(in_out, 3);
10531 addl(in_out, tmp3);
10532 movq(xtmp2, Address(in_out, 0));
10533
10534 psllq(xtmp2, 24);
10535 pxor(xtmp1, xtmp2); // Result in CXMM
10536 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
10537 }
10538
10539 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
10540 Register in_out,
10541 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
10542 XMMRegister w_xtmp2,
10543 Register tmp1,
10544 Register n_tmp2, Register n_tmp3) {
10545 if (is_pclmulqdq_supported) {
10546 movdl(w_xtmp1, in_out);
10547
10548 movl(tmp1, const_or_pre_comp_const_index);
10549 movdl(w_xtmp2, tmp1);
10550 pclmulqdq(w_xtmp1, w_xtmp2, 0);
10551 // Keep result in XMM since GPR is 32 bit in length
10552 } else {
10553 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
10554 }
10555 }
10556
10557 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
10558 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10559 Register tmp1, Register tmp2,
10560 Register n_tmp3) {
10561 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10562 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
10563
10564 psllq(w_xtmp1, 1);
10565 movdl(tmp1, w_xtmp1);
10566 psrlq(w_xtmp1, 32);
10567 movdl(in_out, w_xtmp1);
10568
10569 xorl(tmp2, tmp2);
10570 crc32(tmp2, tmp1, 4);
10571 xorl(in_out, tmp2);
10572
10573 psllq(w_xtmp2, 1);
10574 movdl(tmp1, w_xtmp2);
10575 psrlq(w_xtmp2, 32);
10576 movdl(in1, w_xtmp2);
10577
10578 xorl(tmp2, tmp2);
10579 crc32(tmp2, tmp1, 4);
10580 xorl(in1, tmp2);
10581 xorl(in_out, in1);
10582 xorl(in_out, in2);
10583 }
10584
10585 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
10586 Register in_out1, Register in_out2, Register in_out3,
10587 Register tmp1, Register tmp2, Register tmp3,
10588 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10589 Register tmp4, Register tmp5,
10590 Register n_tmp6) {
10591 Label L_processPartitions;
10592 Label L_processPartition;
10593 Label L_exit;
10594
10595 bind(L_processPartitions);
10596 cmpl(in_out1, 3 * size);
10597 jcc(Assembler::less, L_exit);
10598 xorl(tmp1, tmp1);
10599 xorl(tmp2, tmp2);
10600 movl(tmp3, in_out2);
10601 addl(tmp3, size);
10602
10603 bind(L_processPartition);
10604 crc32(in_out3, Address(in_out2, 0), 4);
10605 crc32(tmp1, Address(in_out2, size), 4);
10606 crc32(tmp2, Address(in_out2, size*2), 4);
10607 crc32(in_out3, Address(in_out2, 0+4), 4);
10608 crc32(tmp1, Address(in_out2, size+4), 4);
10609 crc32(tmp2, Address(in_out2, size*2+4), 4);
10610 addl(in_out2, 8);
10611 cmpl(in_out2, tmp3);
10612 jcc(Assembler::less, L_processPartition);
10613
10614 push(tmp3);
10615 push(in_out1);
10616 push(in_out2);
10617 tmp4 = tmp3;
10618 tmp5 = in_out1;
10619 n_tmp6 = in_out2;
10620
10621 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
10622 w_xtmp1, w_xtmp2, w_xtmp3,
10623 tmp4, tmp5,
10624 n_tmp6);
10625
10626 pop(in_out2);
10627 pop(in_out1);
10628 pop(tmp3);
10629
10630 addl(in_out2, 2 * size);
10631 subl(in_out1, 3 * size);
10632 jmp(L_processPartitions);
10633
10634 bind(L_exit);
10635 }
10636 #endif //LP64
10637
10638 #ifdef _LP64
10639 // Algorithm 2: Pipelined usage of the CRC32 instruction.
10640 // Input: A buffer I of L bytes.
10641 // Output: the CRC32C value of the buffer.
10642 // Notations:
10643 // Write L = 24N + r, with N = floor (L/24).
10644 // r = L mod 24 (0 <= r < 24).
10645 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
10646 // N quadwords, and R consists of r bytes.
10647 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
10648 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
10649 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
10650 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
10651 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10652 Register tmp1, Register tmp2, Register tmp3,
10653 Register tmp4, Register tmp5, Register tmp6,
10654 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10655 bool is_pclmulqdq_supported) {
10656 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10657 Label L_wordByWord;
10658 Label L_byteByByteProlog;
10659 Label L_byteByByte;
10660 Label L_exit;
10661
10662 if (is_pclmulqdq_supported ) {
10663 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10664 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
10665
10666 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10667 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10668
10669 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10670 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10671 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
10672 } else {
10673 const_or_pre_comp_const_index[0] = 1;
10674 const_or_pre_comp_const_index[1] = 0;
10675
10676 const_or_pre_comp_const_index[2] = 3;
10677 const_or_pre_comp_const_index[3] = 2;
10678
10679 const_or_pre_comp_const_index[4] = 5;
10680 const_or_pre_comp_const_index[5] = 4;
10681 }
10682 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10683 in2, in1, in_out,
10684 tmp1, tmp2, tmp3,
10685 w_xtmp1, w_xtmp2, w_xtmp3,
10686 tmp4, tmp5,
10687 tmp6);
10688 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10689 in2, in1, in_out,
10690 tmp1, tmp2, tmp3,
10691 w_xtmp1, w_xtmp2, w_xtmp3,
10692 tmp4, tmp5,
10693 tmp6);
10694 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10695 in2, in1, in_out,
10696 tmp1, tmp2, tmp3,
10697 w_xtmp1, w_xtmp2, w_xtmp3,
10698 tmp4, tmp5,
10699 tmp6);
10700 movl(tmp1, in2);
10701 andl(tmp1, 0x00000007);
10702 negl(tmp1);
10703 addl(tmp1, in2);
10704 addq(tmp1, in1);
10705
10706 BIND(L_wordByWord);
10707 cmpq(in1, tmp1);
10708 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10709 crc32(in_out, Address(in1, 0), 4);
10710 addq(in1, 4);
10711 jmp(L_wordByWord);
10712
10713 BIND(L_byteByByteProlog);
10714 andl(in2, 0x00000007);
10715 movl(tmp2, 1);
10716
10717 BIND(L_byteByByte);
10718 cmpl(tmp2, in2);
10719 jccb(Assembler::greater, L_exit);
10720 crc32(in_out, Address(in1, 0), 1);
10721 incq(in1);
10722 incl(tmp2);
10723 jmp(L_byteByByte);
10724
10725 BIND(L_exit);
10726 }
10727 #else
10728 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
10729 Register tmp1, Register tmp2, Register tmp3,
10730 Register tmp4, Register tmp5, Register tmp6,
10731 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
10732 bool is_pclmulqdq_supported) {
10733 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
10734 Label L_wordByWord;
10735 Label L_byteByByteProlog;
10736 Label L_byteByByte;
10737 Label L_exit;
10738
10739 if (is_pclmulqdq_supported) {
10740 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
10741 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
10742
10743 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
10744 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
10745
10746 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
10747 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
10748 } else {
10749 const_or_pre_comp_const_index[0] = 1;
10750 const_or_pre_comp_const_index[1] = 0;
10751
10752 const_or_pre_comp_const_index[2] = 3;
10753 const_or_pre_comp_const_index[3] = 2;
10754
10755 const_or_pre_comp_const_index[4] = 5;
10756 const_or_pre_comp_const_index[5] = 4;
10757 }
10758 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
10759 in2, in1, in_out,
10760 tmp1, tmp2, tmp3,
10761 w_xtmp1, w_xtmp2, w_xtmp3,
10762 tmp4, tmp5,
10763 tmp6);
10764 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
10765 in2, in1, in_out,
10766 tmp1, tmp2, tmp3,
10767 w_xtmp1, w_xtmp2, w_xtmp3,
10768 tmp4, tmp5,
10769 tmp6);
10770 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
10771 in2, in1, in_out,
10772 tmp1, tmp2, tmp3,
10773 w_xtmp1, w_xtmp2, w_xtmp3,
10774 tmp4, tmp5,
10775 tmp6);
10776 movl(tmp1, in2);
10777 andl(tmp1, 0x00000007);
10778 negl(tmp1);
10779 addl(tmp1, in2);
10780 addl(tmp1, in1);
10781
10782 BIND(L_wordByWord);
10783 cmpl(in1, tmp1);
10784 jcc(Assembler::greaterEqual, L_byteByByteProlog);
10785 crc32(in_out, Address(in1,0), 4);
10786 addl(in1, 4);
10787 jmp(L_wordByWord);
10788
10789 BIND(L_byteByByteProlog);
10790 andl(in2, 0x00000007);
10791 movl(tmp2, 1);
10792
10793 BIND(L_byteByByte);
10794 cmpl(tmp2, in2);
10795 jccb(Assembler::greater, L_exit);
10796 movb(tmp1, Address(in1, 0));
10797 crc32(in_out, tmp1, 1);
10798 incl(in1);
10799 incl(tmp2);
10800 jmp(L_byteByByte);
10801
10802 BIND(L_exit);
10803 }
10804 #endif // LP64
10805 #undef BIND
10806 #undef BLOCK_COMMENT
10807
10808 // Compress char[] array to byte[].
10809 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
10810 // @HotSpotIntrinsicCandidate
10811 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
10812 // for (int i = 0; i < len; i++) {
10813 // int c = src[srcOff++];
10814 // if (c >>> 8 != 0) {
10815 // return 0;
10816 // }
10817 // dst[dstOff++] = (byte)c;
10818 // }
10819 // return len;
10820 // }
10821 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
10822 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
10823 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
10824 Register tmp5, Register result) {
10825 Label copy_chars_loop, return_length, return_zero, done, below_threshold;
10826
10827 // rsi: src
10828 // rdi: dst
10829 // rdx: len
10830 // rcx: tmp5
10831 // rax: result
10832
10833 // rsi holds start addr of source char[] to be compressed
10834 // rdi holds start addr of destination byte[]
10835 // rdx holds length
10836
10837 assert(len != result, "");
10838
10839 // save length for return
10840 push(len);
10841
10842 if ((UseAVX > 2) && // AVX512
10843 VM_Version::supports_avx512vlbw() &&
10844 VM_Version::supports_bmi2()) {
10845
10846 set_vector_masking(); // opening of the stub context for programming mask registers
10847
10848 Label copy_32_loop, copy_loop_tail, restore_k1_return_zero;
10849
10850 // alignement
10851 Label post_alignement;
10852
10853 // if length of the string is less than 16, handle it in an old fashioned
10854 // way
10855 testl(len, -32);
10856 jcc(Assembler::zero, below_threshold);
10857
10858 // First check whether a character is compressable ( <= 0xFF).
10859 // Create mask to test for Unicode chars inside zmm vector
10860 movl(result, 0x00FF);
10861 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
10862
10863 // Save k1
10864 kmovql(k3, k1);
10865
10866 testl(len, -64);
10867 jcc(Assembler::zero, post_alignement);
10868
10869 movl(tmp5, dst);
10870 andl(tmp5, (32 - 1));
10871 negl(tmp5);
10872 andl(tmp5, (32 - 1));
10873
10874 // bail out when there is nothing to be done
10875 testl(tmp5, 0xFFFFFFFF);
10876 jcc(Assembler::zero, post_alignement);
10877
10878 // ~(~0 << len), where len is the # of remaining elements to process
10879 movl(result, 0xFFFFFFFF);
10880 shlxl(result, result, tmp5);
10881 notl(result);
10882 kmovdl(k1, result);
10883
10884 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10885 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10886 ktestd(k2, k1);
10887 jcc(Assembler::carryClear, restore_k1_return_zero);
10888
10889 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10890
10891 addptr(src, tmp5);
10892 addptr(src, tmp5);
10893 addptr(dst, tmp5);
10894 subl(len, tmp5);
10895
10896 bind(post_alignement);
10897 // end of alignement
10898
10899 movl(tmp5, len);
10900 andl(tmp5, (32 - 1)); // tail count (in chars)
10901 andl(len, ~(32 - 1)); // vector count (in chars)
10902 jcc(Assembler::zero, copy_loop_tail);
10903
10904 lea(src, Address(src, len, Address::times_2));
10905 lea(dst, Address(dst, len, Address::times_1));
10906 negptr(len);
10907
10908 bind(copy_32_loop);
10909 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
10910 evpcmpuw(k2, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10911 kortestdl(k2, k2);
10912 jcc(Assembler::carryClear, restore_k1_return_zero);
10913
10914 // All elements in current processed chunk are valid candidates for
10915 // compression. Write a truncated byte elements to the memory.
10916 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
10917 addptr(len, 32);
10918 jcc(Assembler::notZero, copy_32_loop);
10919
10920 bind(copy_loop_tail);
10921 // bail out when there is nothing to be done
10922 testl(tmp5, 0xFFFFFFFF);
10923 // Restore k1
10924 kmovql(k1, k3);
10925 jcc(Assembler::zero, return_length);
10926
10927 movl(len, tmp5);
10928
10929 // ~(~0 << len), where len is the # of remaining elements to process
10930 movl(result, 0xFFFFFFFF);
10931 shlxl(result, result, len);
10932 notl(result);
10933
10934 kmovdl(k1, result);
10935
10936 evmovdquw(tmp1Reg, k1, Address(src, 0), Assembler::AVX_512bit);
10937 evpcmpuw(k2, k1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
10938 ktestd(k2, k1);
10939 jcc(Assembler::carryClear, restore_k1_return_zero);
10940
10941 evpmovwb(Address(dst, 0), k1, tmp1Reg, Assembler::AVX_512bit);
10942 // Restore k1
10943 kmovql(k1, k3);
10944 jmp(return_length);
10945
10946 bind(restore_k1_return_zero);
10947 // Restore k1
10948 kmovql(k1, k3);
10949 jmp(return_zero);
10950
10951 clear_vector_masking(); // closing of the stub context for programming mask registers
10952 }
10953 if (UseSSE42Intrinsics) {
10954 Label copy_32_loop, copy_16, copy_tail;
10955
10956 bind(below_threshold);
10957
10958 movl(result, len);
10959
10960 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
10961
10962 // vectored compression
10963 andl(len, 0xfffffff0); // vector count (in chars)
10964 andl(result, 0x0000000f); // tail count (in chars)
10965 testl(len, len);
10966 jccb(Assembler::zero, copy_16);
10967
10968 // compress 16 chars per iter
10969 movdl(tmp1Reg, tmp5);
10970 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10971 pxor(tmp4Reg, tmp4Reg);
10972
10973 lea(src, Address(src, len, Address::times_2));
10974 lea(dst, Address(dst, len, Address::times_1));
10975 negptr(len);
10976
10977 bind(copy_32_loop);
10978 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
10979 por(tmp4Reg, tmp2Reg);
10980 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
10981 por(tmp4Reg, tmp3Reg);
10982 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
10983 jcc(Assembler::notZero, return_zero);
10984 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
10985 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
10986 addptr(len, 16);
10987 jcc(Assembler::notZero, copy_32_loop);
10988
10989 // compress next vector of 8 chars (if any)
10990 bind(copy_16);
10991 movl(len, result);
10992 andl(len, 0xfffffff8); // vector count (in chars)
10993 andl(result, 0x00000007); // tail count (in chars)
10994 testl(len, len);
10995 jccb(Assembler::zero, copy_tail);
10996
10997 movdl(tmp1Reg, tmp5);
10998 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
10999 pxor(tmp3Reg, tmp3Reg);
11000
11001 movdqu(tmp2Reg, Address(src, 0));
11002 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
11003 jccb(Assembler::notZero, return_zero);
11004 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
11005 movq(Address(dst, 0), tmp2Reg);
11006 addptr(src, 16);
11007 addptr(dst, 8);
11008
11009 bind(copy_tail);
11010 movl(len, result);
11011 }
11012 // compress 1 char per iter
11013 testl(len, len);
11014 jccb(Assembler::zero, return_length);
11015 lea(src, Address(src, len, Address::times_2));
11016 lea(dst, Address(dst, len, Address::times_1));
11017 negptr(len);
11018
11019 bind(copy_chars_loop);
11020 load_unsigned_short(result, Address(src, len, Address::times_2));
11021 testl(result, 0xff00); // check if Unicode char
11022 jccb(Assembler::notZero, return_zero);
11023 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte
11024 increment(len);
11025 jcc(Assembler::notZero, copy_chars_loop);
11026
11027 // if compression succeeded, return length
11028 bind(return_length);
11029 pop(result);
11030 jmpb(done);
11031
11032 // if compression failed, return 0
11033 bind(return_zero);
11034 xorl(result, result);
11035 addptr(rsp, wordSize);
11036
11037 bind(done);
11038 }
11039
11040 // Inflate byte[] array to char[].
11041 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
11042 // @HotSpotIntrinsicCandidate
11043 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
11044 // for (int i = 0; i < len; i++) {
11045 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
11046 // }
11047 // }
11048 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
11049 XMMRegister tmp1, Register tmp2) {
11050 Label copy_chars_loop, done, below_threshold;
11051 // rsi: src
11052 // rdi: dst
11053 // rdx: len
11054 // rcx: tmp2
11055
11056 // rsi holds start addr of source byte[] to be inflated
11057 // rdi holds start addr of destination char[]
11058 // rdx holds length
11059 assert_different_registers(src, dst, len, tmp2);
11060
11061 if ((UseAVX > 2) && // AVX512
11062 VM_Version::supports_avx512vlbw() &&
11063 VM_Version::supports_bmi2()) {
11064
11065 set_vector_masking(); // opening of the stub context for programming mask registers
11066
11067 Label copy_32_loop, copy_tail;
11068 Register tmp3_aliased = len;
11069
11070 // if length of the string is less than 16, handle it in an old fashioned
11071 // way
11072 testl(len, -16);
11073 jcc(Assembler::zero, below_threshold);
11074
11075 // In order to use only one arithmetic operation for the main loop we use
11076 // this pre-calculation
11077 movl(tmp2, len);
11078 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
11079 andl(len, -32); // vector count
11080 jccb(Assembler::zero, copy_tail);
11081
11082 lea(src, Address(src, len, Address::times_1));
11083 lea(dst, Address(dst, len, Address::times_2));
11084 negptr(len);
11085
11086
11087 // inflate 32 chars per iter
11088 bind(copy_32_loop);
11089 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
11090 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
11091 addptr(len, 32);
11092 jcc(Assembler::notZero, copy_32_loop);
11093
11094 bind(copy_tail);
11095 // bail out when there is nothing to be done
11096 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
11097 jcc(Assembler::zero, done);
11098
11099 // Save k1
11100 kmovql(k2, k1);
11101
11102 // ~(~0 << length), where length is the # of remaining elements to process
11103 movl(tmp3_aliased, -1);
11104 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
11105 notl(tmp3_aliased);
11106 kmovdl(k1, tmp3_aliased);
11107 evpmovzxbw(tmp1, k1, Address(src, 0), Assembler::AVX_512bit);
11108 evmovdquw(Address(dst, 0), k1, tmp1, Assembler::AVX_512bit);
11109
11110 // Restore k1
11111 kmovql(k1, k2);
11112 jmp(done);
11113
11114 clear_vector_masking(); // closing of the stub context for programming mask registers
11115 }
11116 if (UseSSE42Intrinsics) {
11117 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
11118
11119 movl(tmp2, len);
11120
11121 if (UseAVX > 1) {
11122 andl(tmp2, (16 - 1));
11123 andl(len, -16);
11124 jccb(Assembler::zero, copy_new_tail);
11125 } else {
11126 andl(tmp2, 0x00000007); // tail count (in chars)
11127 andl(len, 0xfffffff8); // vector count (in chars)
11128 jccb(Assembler::zero, copy_tail);
11129 }
11130
11131 // vectored inflation
11132 lea(src, Address(src, len, Address::times_1));
11133 lea(dst, Address(dst, len, Address::times_2));
11134 negptr(len);
11135
11136 if (UseAVX > 1) {
11137 bind(copy_16_loop);
11138 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
11139 vmovdqu(Address(dst, len, Address::times_2), tmp1);
11140 addptr(len, 16);
11141 jcc(Assembler::notZero, copy_16_loop);
11142
11143 bind(below_threshold);
11144 bind(copy_new_tail);
11145 if ((UseAVX > 2) &&
11146 VM_Version::supports_avx512vlbw() &&
11147 VM_Version::supports_bmi2()) {
11148 movl(tmp2, len);
11149 } else {
11150 movl(len, tmp2);
11151 }
11152 andl(tmp2, 0x00000007);
11153 andl(len, 0xFFFFFFF8);
11154 jccb(Assembler::zero, copy_tail);
11155
11156 pmovzxbw(tmp1, Address(src, 0));
11157 movdqu(Address(dst, 0), tmp1);
11158 addptr(src, 8);
11159 addptr(dst, 2 * 8);
11160
11161 jmp(copy_tail, true);
11162 }
11163
11164 // inflate 8 chars per iter
11165 bind(copy_8_loop);
11166 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
11167 movdqu(Address(dst, len, Address::times_2), tmp1);
11168 addptr(len, 8);
11169 jcc(Assembler::notZero, copy_8_loop);
11170
11171 bind(copy_tail);
11172 movl(len, tmp2);
11173
11174 cmpl(len, 4);
11175 jccb(Assembler::less, copy_bytes);
11176
11177 movdl(tmp1, Address(src, 0)); // load 4 byte chars
11178 pmovzxbw(tmp1, tmp1);
11179 movq(Address(dst, 0), tmp1);
11180 subptr(len, 4);
11181 addptr(src, 4);
11182 addptr(dst, 8);
11183
11184 bind(copy_bytes);
11185 }
11186 testl(len, len);
11187 jccb(Assembler::zero, done);
11188 lea(src, Address(src, len, Address::times_1));
11189 lea(dst, Address(dst, len, Address::times_2));
11190 negptr(len);
11191
11192 // inflate 1 char per iter
11193 bind(copy_chars_loop);
11194 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
11195 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
11196 increment(len);
11197 jcc(Assembler::notZero, copy_chars_loop);
11198
11199 bind(done);
11200 }
11201
11202 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
11203 switch (cond) {
11204 // Note some conditions are synonyms for others
11205 case Assembler::zero: return Assembler::notZero;
11206 case Assembler::notZero: return Assembler::zero;
11207 case Assembler::less: return Assembler::greaterEqual;
11208 case Assembler::lessEqual: return Assembler::greater;
11209 case Assembler::greater: return Assembler::lessEqual;
11210 case Assembler::greaterEqual: return Assembler::less;
11211 case Assembler::below: return Assembler::aboveEqual;
11212 case Assembler::belowEqual: return Assembler::above;
11213 case Assembler::above: return Assembler::belowEqual;
11214 case Assembler::aboveEqual: return Assembler::below;
11215 case Assembler::overflow: return Assembler::noOverflow;
11216 case Assembler::noOverflow: return Assembler::overflow;
11217 case Assembler::negative: return Assembler::positive;
11218 case Assembler::positive: return Assembler::negative;
11219 case Assembler::parity: return Assembler::noParity;
11220 case Assembler::noParity: return Assembler::parity;
11221 }
11222 ShouldNotReachHere(); return Assembler::overflow;
11223 }
11224
11225 SkipIfEqual::SkipIfEqual(
11226 MacroAssembler* masm, const bool* flag_addr, bool value) {
11227 _masm = masm;
11228 _masm->cmp8(ExternalAddress((address)flag_addr), value);
11229 _masm->jcc(Assembler::equal, _label);
11230 }
11231
11232 SkipIfEqual::~SkipIfEqual() {
11233 _masm->bind(_label);
11234 }
11235
11236 // 32-bit Windows has its own fast-path implementation
11237 // of get_thread
11238 #if !defined(WIN32) || defined(_LP64)
11239
11240 // This is simply a call to Thread::current()
11241 void MacroAssembler::get_thread(Register thread) {
11242 if (thread != rax) {
11243 push(rax);
11244 }
11245 LP64_ONLY(push(rdi);)
11246 LP64_ONLY(push(rsi);)
11247 push(rdx);
11248 push(rcx);
11249 #ifdef _LP64
11250 push(r8);
11251 push(r9);
11252 push(r10);
11253 push(r11);
11254 #endif
11255
11256 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11257
11258 #ifdef _LP64
11259 pop(r11);
11260 pop(r10);
11261 pop(r9);
11262 pop(r8);
11263 #endif
11264 pop(rcx);
11265 pop(rdx);
11266 LP64_ONLY(pop(rsi);)
11267 LP64_ONLY(pop(rdi);)
11268 if (thread != rax) {
11269 mov(thread, rax);
11270 pop(rax);
11271 }
11272 }
11273
11274 #endif