1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2015 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 bool VM_Version::_is_determine_features_test_running = false;
41
42
43 #define MSG(flag) \
44 if (flag && !FLAG_IS_DEFAULT(flag)) \
45 jio_fprintf(defaultStream::error_stream(), \
46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
47 " -XX:+" #flag " will be disabled!\n");
48
49 void VM_Version::initialize() {
50
51 // Test which instructions are supported and measure cache line size.
52 determine_features();
53
54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
56 if (VM_Version::has_tcheck() && VM_Version::has_lqarx()) {
57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
58 } else if (VM_Version::has_popcntw()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
60 } else if (VM_Version::has_cmpb()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
62 } else if (VM_Version::has_popcntb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
64 } else {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
66 }
67 }
68
69 bool PowerArchitecturePPC64_ok = false;
70 switch (PowerArchitecturePPC64) {
71 case 8: if (!VM_Version::has_tcheck() ) break;
72 if (!VM_Version::has_lqarx() ) break;
73 case 7: if (!VM_Version::has_popcntw()) break;
74 case 6: if (!VM_Version::has_cmpb() ) break;
75 case 5: if (!VM_Version::has_popcntb()) break;
76 case 0: PowerArchitecturePPC64_ok = true; break;
77 default: break;
78 }
79 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
80 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
81
82 // Power 8: Configure Data Stream Control Register.
83 if (PowerArchitecturePPC64 >= 8) {
84 config_dscr();
85 }
86
87 if (!UseSIGTRAP) {
88 MSG(TrapBasedICMissChecks);
89 MSG(TrapBasedNotEntrantChecks);
90 MSG(TrapBasedNullChecks);
91 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
92 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
93 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
94 }
95
96 #ifdef COMPILER2
97 if (!UseSIGTRAP) {
98 MSG(TrapBasedRangeChecks);
99 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
100 }
101
102 // On Power6 test for section size.
103 if (PowerArchitecturePPC64 == 6) {
104 determine_section_size();
105 // TODO: PPC port } else {
106 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
107 }
108
109 MaxVectorSize = 8;
110 #endif
111
112 // Create and print feature-string.
113 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
114 jio_snprintf(buf, sizeof(buf),
115 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s",
116 (has_fsqrt() ? " fsqrt" : ""),
117 (has_isel() ? " isel" : ""),
118 (has_lxarxeh() ? " lxarxeh" : ""),
119 (has_cmpb() ? " cmpb" : ""),
120 //(has_mftgpr()? " mftgpr" : ""),
121 (has_popcntb() ? " popcntb" : ""),
122 (has_popcntw() ? " popcntw" : ""),
123 (has_fcfids() ? " fcfids" : ""),
124 (has_vand() ? " vand" : ""),
125 (has_lqarx() ? " lqarx" : ""),
126 (has_vcipher() ? " vcipher" : ""),
127 (has_vpmsumb() ? " vpmsumb" : ""),
128 (has_tcheck() ? " tcheck" : "")
129 // Make sure number of %s matches num_features!
130 );
131 _features_string = os::strdup(buf);
132 if (Verbose) {
133 print_features();
134 }
135
136 // PPC64 supports 8-byte compare-exchange operations (see
137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
139 _supports_cx8 = true;
140
141 // Used by C1.
142 _supports_atomic_getset4 = true;
143 _supports_atomic_getadd4 = true;
144 _supports_atomic_getset8 = true;
145 _supports_atomic_getadd8 = true;
146
147 UseSSE = 0; // Only on x86 and x64
148
593 // Emit code.
594 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
595 uint32_t *code = (uint32_t *)a->pc();
596 // Don't use R0 in ldarx.
597 // Keep R3_ARG1 unmodified, it contains &field (see below).
598 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
599 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
600 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
601 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
602 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
603 a->cmpb(R7, R5, R6); // code[4] -> cmpb
604 a->popcntb(R7, R5); // code[5] -> popcntb
605 a->popcntw(R7, R5); // code[6] -> popcntw
606 a->fcfids(F3, F4); // code[7] -> fcfids
607 a->vand(VR0, VR0, VR0); // code[8] -> vand
608 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
609 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
610 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
611 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
612 a->tcheck(0); // code[12] -> tcheck
613 a->blr();
614
615 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
616 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
617 a->dcbz(R3_ARG1); // R3_ARG1 = addr
618 a->blr();
619
620 uint32_t *code_end = (uint32_t *)a->pc();
621 a->flush();
622 _features = VM_Version::unknown_m;
623
624 // Print the detection code.
625 if (PrintAssembly) {
626 ttyLocker ttyl;
627 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
628 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
629 }
630
631 // Measure cache line size.
632 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
640 VM_Version::_is_determine_features_test_running = true;
641 // We must align the first argument to 16 bytes because of the lqarx check.
642 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
643 VM_Version::_is_determine_features_test_running = false;
644
645 // determine which instructions are legal.
646 int feature_cntr = 0;
647 if (code[feature_cntr++]) features |= fsqrt_m;
648 if (code[feature_cntr++]) features |= fsqrts_m;
649 if (code[feature_cntr++]) features |= isel_m;
650 if (code[feature_cntr++]) features |= lxarxeh_m;
651 if (code[feature_cntr++]) features |= cmpb_m;
652 if (code[feature_cntr++]) features |= popcntb_m;
653 if (code[feature_cntr++]) features |= popcntw_m;
654 if (code[feature_cntr++]) features |= fcfids_m;
655 if (code[feature_cntr++]) features |= vand_m;
656 if (code[feature_cntr++]) features |= lqarx_m;
657 if (code[feature_cntr++]) features |= vcipher_m;
658 if (code[feature_cntr++]) features |= vpmsumb_m;
659 if (code[feature_cntr++]) features |= tcheck_m;
660
661 // Print the detection code.
662 if (PrintAssembly) {
663 ttyLocker ttyl;
664 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
665 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
666 }
667
668 _features = features;
669 }
670
671 // Power 8: Configure Data Stream Control Register.
672 void VM_Version::config_dscr() {
673 assert(has_tcheck(), "Only execute on Power 8 or later!");
674
675 // 7 InstWords for each call (function descriptor + blr instruction).
676 const int code_size = (2+2*7)*BytesPerInstWord;
677
678 // Allocate space for the code.
679 ResourceMark rm;
680 CodeBuffer cb("config_dscr", code_size, 0);
681 MacroAssembler* a = new MacroAssembler(&cb);
682
683 // Emit code.
684 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
685 uint32_t *code = (uint32_t *)a->pc();
686 a->mfdscr(R3);
687 a->blr();
688
689 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
690 a->mtdscr(R3);
691 a->blr();
692
693 uint32_t *code_end = (uint32_t *)a->pc();
694 a->flush();
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1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 bool VM_Version::_is_determine_features_test_running = false;
41
42
43 #define MSG(flag) \
44 if (flag && !FLAG_IS_DEFAULT(flag)) \
45 jio_fprintf(defaultStream::error_stream(), \
46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
47 " -XX:+" #flag " will be disabled!\n");
48
49 void VM_Version::initialize() {
50
51 // Test which instructions are supported and measure cache line size.
52 determine_features();
53
54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
56 if (VM_Version::has_lqarx()) {
57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
58 } else if (VM_Version::has_popcntw()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
60 } else if (VM_Version::has_cmpb()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
62 } else if (VM_Version::has_popcntb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
64 } else {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
66 }
67 }
68
69 bool PowerArchitecturePPC64_ok = false;
70 switch (PowerArchitecturePPC64) {
71 case 8: if (!VM_Version::has_lqarx() ) break;
72 case 7: if (!VM_Version::has_popcntw()) break;
73 case 6: if (!VM_Version::has_cmpb() ) break;
74 case 5: if (!VM_Version::has_popcntb()) break;
75 case 0: PowerArchitecturePPC64_ok = true; break;
76 default: break;
77 }
78 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
79 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
80
81 // Power 8: Configure Data Stream Control Register.
82 if (has_mfdscr()) {
83 config_dscr();
84 }
85
86 if (!UseSIGTRAP) {
87 MSG(TrapBasedICMissChecks);
88 MSG(TrapBasedNotEntrantChecks);
89 MSG(TrapBasedNullChecks);
90 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
91 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
92 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
93 }
94
95 #ifdef COMPILER2
96 if (!UseSIGTRAP) {
97 MSG(TrapBasedRangeChecks);
98 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
99 }
100
101 // On Power6 test for section size.
102 if (PowerArchitecturePPC64 == 6) {
103 determine_section_size();
104 // TODO: PPC port } else {
105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
106 }
107
108 MaxVectorSize = 8;
109 #endif
110
111 // Create and print feature-string.
112 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
113 jio_snprintf(buf, sizeof(buf),
114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s",
115 (has_fsqrt() ? " fsqrt" : ""),
116 (has_isel() ? " isel" : ""),
117 (has_lxarxeh() ? " lxarxeh" : ""),
118 (has_cmpb() ? " cmpb" : ""),
119 //(has_mftgpr()? " mftgpr" : ""),
120 (has_popcntb() ? " popcntb" : ""),
121 (has_popcntw() ? " popcntw" : ""),
122 (has_fcfids() ? " fcfids" : ""),
123 (has_vand() ? " vand" : ""),
124 (has_lqarx() ? " lqarx" : ""),
125 (has_vcipher() ? " vcipher" : ""),
126 (has_vpmsumb() ? " vpmsumb" : ""),
127 (has_tcheck() ? " tcheck" : ""),
128 (has_mfdscr() ? " mfdscr" : "")
129 // Make sure number of %s matches num_features!
130 );
131 _features_string = os::strdup(buf);
132 if (Verbose) {
133 print_features();
134 }
135
136 // PPC64 supports 8-byte compare-exchange operations (see
137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
139 _supports_cx8 = true;
140
141 // Used by C1.
142 _supports_atomic_getset4 = true;
143 _supports_atomic_getadd4 = true;
144 _supports_atomic_getset8 = true;
145 _supports_atomic_getadd8 = true;
146
147 UseSSE = 0; // Only on x86 and x64
148
593 // Emit code.
594 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
595 uint32_t *code = (uint32_t *)a->pc();
596 // Don't use R0 in ldarx.
597 // Keep R3_ARG1 unmodified, it contains &field (see below).
598 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
599 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
600 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
601 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
602 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
603 a->cmpb(R7, R5, R6); // code[4] -> cmpb
604 a->popcntb(R7, R5); // code[5] -> popcntb
605 a->popcntw(R7, R5); // code[6] -> popcntw
606 a->fcfids(F3, F4); // code[7] -> fcfids
607 a->vand(VR0, VR0, VR0); // code[8] -> vand
608 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
609 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
610 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
611 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
612 a->tcheck(0); // code[12] -> tcheck
613 a->mfdscr(R0); // code[13] -> mfdscr
614 a->blr();
615
616 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
617 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
618 a->dcbz(R3_ARG1); // R3_ARG1 = addr
619 a->blr();
620
621 uint32_t *code_end = (uint32_t *)a->pc();
622 a->flush();
623 _features = VM_Version::unknown_m;
624
625 // Print the detection code.
626 if (PrintAssembly) {
627 ttyLocker ttyl;
628 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
629 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
630 }
631
632 // Measure cache line size.
633 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
641 VM_Version::_is_determine_features_test_running = true;
642 // We must align the first argument to 16 bytes because of the lqarx check.
643 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
644 VM_Version::_is_determine_features_test_running = false;
645
646 // determine which instructions are legal.
647 int feature_cntr = 0;
648 if (code[feature_cntr++]) features |= fsqrt_m;
649 if (code[feature_cntr++]) features |= fsqrts_m;
650 if (code[feature_cntr++]) features |= isel_m;
651 if (code[feature_cntr++]) features |= lxarxeh_m;
652 if (code[feature_cntr++]) features |= cmpb_m;
653 if (code[feature_cntr++]) features |= popcntb_m;
654 if (code[feature_cntr++]) features |= popcntw_m;
655 if (code[feature_cntr++]) features |= fcfids_m;
656 if (code[feature_cntr++]) features |= vand_m;
657 if (code[feature_cntr++]) features |= lqarx_m;
658 if (code[feature_cntr++]) features |= vcipher_m;
659 if (code[feature_cntr++]) features |= vpmsumb_m;
660 if (code[feature_cntr++]) features |= tcheck_m;
661 if (code[feature_cntr++]) features |= mfdscr_m;
662
663 // Print the detection code.
664 if (PrintAssembly) {
665 ttyLocker ttyl;
666 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
667 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
668 }
669
670 _features = features;
671 }
672
673 // Power 8: Configure Data Stream Control Register.
674 void VM_Version::config_dscr() {
675 // 7 InstWords for each call (function descriptor + blr instruction).
676 const int code_size = (2+2*7)*BytesPerInstWord;
677
678 // Allocate space for the code.
679 ResourceMark rm;
680 CodeBuffer cb("config_dscr", code_size, 0);
681 MacroAssembler* a = new MacroAssembler(&cb);
682
683 // Emit code.
684 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
685 uint32_t *code = (uint32_t *)a->pc();
686 a->mfdscr(R3);
687 a->blr();
688
689 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
690 a->mtdscr(R3);
691 a->blr();
692
693 uint32_t *code_end = (uint32_t *)a->pc();
694 a->flush();
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