1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "utilities/defaultStream.hpp"
35 #include "utilities/globalDefinitions.hpp"
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 bool VM_Version::_is_determine_features_test_running = false;
41
42
43 #define MSG(flag) \
44 if (flag && !FLAG_IS_DEFAULT(flag)) \
45 jio_fprintf(defaultStream::error_stream(), \
46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
47 " -XX:+" #flag " will be disabled!\n");
48
49 void VM_Version::initialize() {
50
51 // Test which instructions are supported and measure cache line size.
52 determine_features();
53
54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
56 if (VM_Version::has_lqarx()) {
57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
58 } else if (VM_Version::has_popcntw()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
60 } else if (VM_Version::has_cmpb()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
62 } else if (VM_Version::has_popcntb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
64 } else {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
66 }
67 }
68
69 bool PowerArchitecturePPC64_ok = false;
70 switch (PowerArchitecturePPC64) {
71 case 8: if (!VM_Version::has_lqarx() ) break;
72 case 7: if (!VM_Version::has_popcntw()) break;
73 case 6: if (!VM_Version::has_cmpb() ) break;
74 case 5: if (!VM_Version::has_popcntb()) break;
75 case 0: PowerArchitecturePPC64_ok = true; break;
76 default: break;
77 }
78 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
79 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
80
81 // Power 8: Configure Data Stream Control Register.
82 if (has_mfdscr()) {
83 config_dscr();
84 }
85
86 if (!UseSIGTRAP) {
87 MSG(TrapBasedICMissChecks);
88 MSG(TrapBasedNotEntrantChecks);
89 MSG(TrapBasedNullChecks);
90 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
91 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
92 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
93 }
94
95 #ifdef COMPILER2
96 if (!UseSIGTRAP) {
97 MSG(TrapBasedRangeChecks);
98 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
99 }
100
101 // On Power6 test for section size.
102 if (PowerArchitecturePPC64 == 6) {
103 determine_section_size();
104 // TODO: PPC port } else {
105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
106 }
107
108 MaxVectorSize = 8;
109 #endif
110
111 // Create and print feature-string.
112 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
113 jio_snprintf(buf, sizeof(buf),
114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s",
115 (has_fsqrt() ? " fsqrt" : ""),
116 (has_isel() ? " isel" : ""),
117 (has_lxarxeh() ? " lxarxeh" : ""),
118 (has_cmpb() ? " cmpb" : ""),
119 //(has_mftgpr()? " mftgpr" : ""),
120 (has_popcntb() ? " popcntb" : ""),
121 (has_popcntw() ? " popcntw" : ""),
122 (has_fcfids() ? " fcfids" : ""),
123 (has_vand() ? " vand" : ""),
124 (has_lqarx() ? " lqarx" : ""),
125 (has_vcipher() ? " aes" : ""),
126 (has_vpmsumb() ? " vpmsumb" : ""),
127 (has_tcheck() ? " tcheck" : ""),
128 (has_mfdscr() ? " mfdscr" : "")
129 // Make sure number of %s matches num_features!
130 );
131 _features_string = os::strdup(buf);
132 if (Verbose) {
133 print_features();
134 }
135
136 // PPC64 supports 8-byte compare-exchange operations (see
137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
139 _supports_cx8 = true;
140
141 // Used by C1.
142 _supports_atomic_getset4 = true;
143 _supports_atomic_getadd4 = true;
144 _supports_atomic_getset8 = true;
145 _supports_atomic_getadd8 = true;
146
147 UseSSE = 0; // Only on x86 and x64
148
149 intx cache_line_size = L1_data_cache_line_size();
150
151 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
152
153 if (AllocatePrefetchStyle == 4) {
154 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
155 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
156 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
157 } else {
158 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
159 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
160 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
161 }
162
163 assert(AllocatePrefetchLines > 0, "invalid value");
164 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
165 AllocatePrefetchLines = 1; // Conservative value.
166 }
167
168 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
169 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
170 }
171
172 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
173
174 // Implementation does not use any of the vector instructions
175 // available with Power8. Their exploitation is still pending.
176 if (!UseCRC32Intrinsics) {
177 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
178 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
179 }
180 }
181
182 if (UseCRC32CIntrinsics) {
183 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
184 warning("CRC32C intrinsics are not available on this CPU");
185 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
186 }
187
188 // The AES intrinsic stubs require AES instruction support.
189 #if defined(VM_LITTLE_ENDIAN)
190 if (has_vcipher()) {
191 if (FLAG_IS_DEFAULT(UseAES)) {
192 UseAES = true;
193 }
194 } else if (UseAES) {
195 if (!FLAG_IS_DEFAULT(UseAES))
196 warning("AES instructions are not available on this CPU");
197 FLAG_SET_DEFAULT(UseAES, false);
198 }
199
200 if (UseAES && has_vcipher()) {
201 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
202 UseAESIntrinsics = true;
203 }
204 } else if (UseAESIntrinsics) {
205 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
206 warning("AES intrinsics are not available on this CPU");
207 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
208 }
209
210 #else
211 if (UseAES) {
212 warning("AES instructions are not available on this CPU");
213 FLAG_SET_DEFAULT(UseAES, false);
214 }
215 if (UseAESIntrinsics) {
216 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
217 warning("AES intrinsics are not available on this CPU");
218 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
219 }
220 #endif
221
222 if (UseAESCTRIntrinsics) {
223 warning("AES/CTR intrinsics are not available on this CPU");
224 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
225 }
226
227 if (UseGHASHIntrinsics) {
228 warning("GHASH intrinsics are not available on this CPU");
229 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
230 }
231
232 if (UseSHA) {
233 warning("SHA instructions are not available on this CPU");
234 FLAG_SET_DEFAULT(UseSHA, false);
235 }
236 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
237 warning("SHA intrinsics are not available on this CPU");
238 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
239 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
240 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
241 }
242
243 if (UseAdler32Intrinsics) {
244 warning("Adler32Intrinsics not available on this CPU.");
245 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
246 }
247
248 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
249 UseMultiplyToLenIntrinsic = true;
250 }
251 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
252 UseMontgomeryMultiplyIntrinsic = true;
253 }
254 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
255 UseMontgomerySquareIntrinsic = true;
256 }
257
258 if (UseVectorizedMismatchIntrinsic) {
259 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
260 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
261 }
262
263
264 // Adjust RTM (Restricted Transactional Memory) flags.
265 if (UseRTMLocking) {
266 // If CPU or OS are too old:
267 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
268 // setting during arguments processing. See use_biased_locking().
269 // VM_Version_init() is executed after UseBiasedLocking is used
270 // in Thread::allocate().
271 if (!has_tcheck()) {
272 vm_exit_during_initialization("RTM instructions are not available on this CPU");
273 }
274 bool os_too_old = true;
275 #ifdef AIX
276 if (os::Aix::os_version() >= 0x0701031e) { // at least AIX 7.1.3.30
277 os_too_old = false;
278 }
279 #endif
280 #ifdef linux
281 // At least Linux kernel 4.2, as the problematic behavior of syscalls
282 // being called in the middle of a transaction has been addressed.
283 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894
284 // in Linux kernel source tree: https://goo.gl/Kc5i7A
285 if (os::Linux::os_version_is_known()) {
286 if (os::Linux::os_version() >= 0x040200)
287 os_too_old = false;
288 } else {
289 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown.");
290 }
291 #endif
292 if (os_too_old) {
293 vm_exit_during_initialization("RTM is not supported on this OS version.");
294 }
295 }
296
297 if (UseRTMLocking) {
298 #if INCLUDE_RTM_OPT
299 if (!UnlockExperimentalVMOptions) {
300 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
301 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
302 } else {
303 warning("UseRTMLocking is only available as experimental option on this platform.");
304 }
305 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
306 // RTM locking should be used only for applications with
307 // high lock contention. For now we do not use it by default.
308 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
309 }
310 if (!is_power_of_2(RTMTotalCountIncrRate)) {
311 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
312 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
313 }
314 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
315 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
316 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
317 }
318 guarantee(RTMSpinLoopCount > 0, "unsupported");
319 #else
320 // Only C2 does RTM locking optimization.
321 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
322 // setting during arguments processing. See use_biased_locking().
323 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
324 #endif
325 } else { // !UseRTMLocking
326 if (UseRTMForStackLocks) {
327 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
328 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
329 }
330 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
331 }
332 if (UseRTMDeopt) {
333 FLAG_SET_DEFAULT(UseRTMDeopt, false);
334 }
335 if (PrintPreciseRTMLockingStatistics) {
336 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
337 }
338 }
339
340 // This machine allows unaligned memory accesses
341 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
342 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
343 }
344 }
345
346 bool VM_Version::use_biased_locking() {
347 #if INCLUDE_RTM_OPT
348 // RTM locking is most useful when there is high lock contention and
349 // low data contention. With high lock contention the lock is usually
350 // inflated and biased locking is not suitable for that case.
351 // RTM locking code requires that biased locking is off.
352 // Note: we can't switch off UseBiasedLocking in get_processor_features()
353 // because it is used by Thread::allocate() which is called before
354 // VM_Version::initialize().
355 if (UseRTMLocking && UseBiasedLocking) {
356 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
357 FLAG_SET_DEFAULT(UseBiasedLocking, false);
358 } else {
359 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
360 UseBiasedLocking = false;
361 }
362 }
363 #endif
364 return UseBiasedLocking;
365 }
366
367 void VM_Version::print_features() {
368 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
369 }
370
371 #ifdef COMPILER2
372 // Determine section size on power6: If section size is 8 instructions,
373 // there should be a difference between the two testloops of ~15 %. If
374 // no difference is detected the section is assumed to be 32 instructions.
375 void VM_Version::determine_section_size() {
376
377 int unroll = 80;
378
379 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
380
381 // Allocate space for the code.
382 ResourceMark rm;
383 CodeBuffer cb("detect_section_size", code_size, 0);
384 MacroAssembler* a = new MacroAssembler(&cb);
385
386 uint32_t *code = (uint32_t *)a->pc();
387 // Emit code.
388 void (*test1)() = (void(*)())(void *)a->function_entry();
389
390 Label l1;
391
392 a->li(R4, 1);
393 a->sldi(R4, R4, 28);
394 a->b(l1);
395 a->align(CodeEntryAlignment);
396
397 a->bind(l1);
398
399 for (int i = 0; i < unroll; i++) {
400 // Schleife 1
401 // ------- sector 0 ------------
402 // ;; 0
403 a->nop(); // 1
404 a->fpnop0(); // 2
405 a->fpnop1(); // 3
406 a->addi(R4,R4, -1); // 4
407
408 // ;; 1
409 a->nop(); // 5
410 a->fmr(F6, F6); // 6
411 a->fmr(F7, F7); // 7
412 a->endgroup(); // 8
413 // ------- sector 8 ------------
414
415 // ;; 2
416 a->nop(); // 9
417 a->nop(); // 10
418 a->fmr(F8, F8); // 11
419 a->fmr(F9, F9); // 12
420
421 // ;; 3
422 a->nop(); // 13
423 a->fmr(F10, F10); // 14
424 a->fmr(F11, F11); // 15
425 a->endgroup(); // 16
426 // -------- sector 16 -------------
427
428 // ;; 4
429 a->nop(); // 17
430 a->nop(); // 18
431 a->fmr(F15, F15); // 19
432 a->fmr(F16, F16); // 20
433
434 // ;; 5
435 a->nop(); // 21
436 a->fmr(F17, F17); // 22
437 a->fmr(F18, F18); // 23
438 a->endgroup(); // 24
439 // ------- sector 24 ------------
440
441 // ;; 6
442 a->nop(); // 25
443 a->nop(); // 26
444 a->fmr(F19, F19); // 27
445 a->fmr(F20, F20); // 28
446
447 // ;; 7
448 a->nop(); // 29
449 a->fmr(F21, F21); // 30
450 a->fmr(F22, F22); // 31
451 a->brnop0(); // 32
452
453 // ------- sector 32 ------------
454 }
455
456 // ;; 8
457 a->cmpdi(CCR0, R4, unroll); // 33
458 a->bge(CCR0, l1); // 34
459 a->blr();
460
461 // Emit code.
462 void (*test2)() = (void(*)())(void *)a->function_entry();
463 // uint32_t *code = (uint32_t *)a->pc();
464
465 Label l2;
466
467 a->li(R4, 1);
468 a->sldi(R4, R4, 28);
469 a->b(l2);
470 a->align(CodeEntryAlignment);
471
472 a->bind(l2);
473
474 for (int i = 0; i < unroll; i++) {
475 // Schleife 2
476 // ------- sector 0 ------------
477 // ;; 0
478 a->brnop0(); // 1
479 a->nop(); // 2
480 //a->cmpdi(CCR0, R4, unroll);
481 a->fpnop0(); // 3
482 a->fpnop1(); // 4
483 a->addi(R4,R4, -1); // 5
484
485 // ;; 1
486
487 a->nop(); // 6
488 a->fmr(F6, F6); // 7
489 a->fmr(F7, F7); // 8
490 // ------- sector 8 ---------------
491
492 // ;; 2
493 a->endgroup(); // 9
494
495 // ;; 3
496 a->nop(); // 10
497 a->nop(); // 11
498 a->fmr(F8, F8); // 12
499
500 // ;; 4
501 a->fmr(F9, F9); // 13
502 a->nop(); // 14
503 a->fmr(F10, F10); // 15
504
505 // ;; 5
506 a->fmr(F11, F11); // 16
507 // -------- sector 16 -------------
508
509 // ;; 6
510 a->endgroup(); // 17
511
512 // ;; 7
513 a->nop(); // 18
514 a->nop(); // 19
515 a->fmr(F15, F15); // 20
516
517 // ;; 8
518 a->fmr(F16, F16); // 21
519 a->nop(); // 22
520 a->fmr(F17, F17); // 23
521
522 // ;; 9
523 a->fmr(F18, F18); // 24
524 // -------- sector 24 -------------
525
526 // ;; 10
527 a->endgroup(); // 25
528
529 // ;; 11
530 a->nop(); // 26
531 a->nop(); // 27
532 a->fmr(F19, F19); // 28
533
534 // ;; 12
535 a->fmr(F20, F20); // 29
536 a->nop(); // 30
537 a->fmr(F21, F21); // 31
538
539 // ;; 13
540 a->fmr(F22, F22); // 32
541 }
542
543 // -------- sector 32 -------------
544 // ;; 14
545 a->cmpdi(CCR0, R4, unroll); // 33
546 a->bge(CCR0, l2); // 34
547
548 a->blr();
549 uint32_t *code_end = (uint32_t *)a->pc();
550 a->flush();
551
552 double loop1_seconds,loop2_seconds, rel_diff;
553 uint64_t start1, stop1;
554
555 start1 = os::current_thread_cpu_time(false);
556 (*test1)();
557 stop1 = os::current_thread_cpu_time(false);
558 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
559
560
561 start1 = os::current_thread_cpu_time(false);
562 (*test2)();
563 stop1 = os::current_thread_cpu_time(false);
564
565 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
566
567 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
568
569 if (PrintAssembly) {
570 ttyLocker ttyl;
571 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
572 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
573 tty->print_cr("Time loop1 :%f", loop1_seconds);
574 tty->print_cr("Time loop2 :%f", loop2_seconds);
575 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
576
577 if (rel_diff > 12.0) {
578 tty->print_cr("Section Size 8 Instructions");
579 } else{
580 tty->print_cr("Section Size 32 Instructions or Power5");
581 }
582 }
583
584 #if 0 // TODO: PPC port
585 // Set sector size (if not set explicitly).
586 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
587 if (rel_diff > 12.0) {
588 PdScheduling::power6SectorSize = 0x20;
589 } else {
590 PdScheduling::power6SectorSize = 0x80;
591 }
592 } else if (Power6SectorSize128PPC64) {
593 PdScheduling::power6SectorSize = 0x80;
594 } else {
595 PdScheduling::power6SectorSize = 0x20;
596 }
597 #endif
598 if (UsePower6SchedulerPPC64) Unimplemented();
599 }
600 #endif // COMPILER2
601
602 void VM_Version::determine_features() {
603 #if defined(ABI_ELFv2)
604 // 1 InstWord per call for the blr instruction.
605 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
606 #else
607 // 7 InstWords for each call (function descriptor + blr instruction).
608 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
609 #endif
610 int features = 0;
611
612 // create test area
613 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
614 char test_area[BUFFER_SIZE];
615 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
616
617 // Allocate space for the code.
618 ResourceMark rm;
619 CodeBuffer cb("detect_cpu_features", code_size, 0);
620 MacroAssembler* a = new MacroAssembler(&cb);
621
622 // Must be set to true so we can generate the test code.
623 _features = VM_Version::all_features_m;
624
625 // Emit code.
626 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
627 uint32_t *code = (uint32_t *)a->pc();
628 // Don't use R0 in ldarx.
629 // Keep R3_ARG1 unmodified, it contains &field (see below).
630 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
631 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
632 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
633 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
634 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
635 a->cmpb(R7, R5, R6); // code[4] -> cmpb
636 a->popcntb(R7, R5); // code[5] -> popcntb
637 a->popcntw(R7, R5); // code[6] -> popcntw
638 a->fcfids(F3, F4); // code[7] -> fcfids
639 a->vand(VR0, VR0, VR0); // code[8] -> vand
640 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
641 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
642 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
643 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
644 a->tcheck(0); // code[12] -> tcheck
645 a->mfdscr(R0); // code[13] -> mfdscr
646 a->blr();
647
648 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
649 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
650 a->dcbz(R3_ARG1); // R3_ARG1 = addr
651 a->blr();
652
653 uint32_t *code_end = (uint32_t *)a->pc();
654 a->flush();
655 _features = VM_Version::unknown_m;
656
657 // Print the detection code.
658 if (PrintAssembly) {
659 ttyLocker ttyl;
660 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
661 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
662 }
663
664 // Measure cache line size.
665 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
666 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
667 int count = 0; // count zeroed bytes
668 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
669 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
670 _L1_data_cache_line_size = count;
671
672 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
673 VM_Version::_is_determine_features_test_running = true;
674 // We must align the first argument to 16 bytes because of the lqarx check.
675 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
676 VM_Version::_is_determine_features_test_running = false;
677
678 // determine which instructions are legal.
679 int feature_cntr = 0;
680 if (code[feature_cntr++]) features |= fsqrt_m;
681 if (code[feature_cntr++]) features |= fsqrts_m;
682 if (code[feature_cntr++]) features |= isel_m;
683 if (code[feature_cntr++]) features |= lxarxeh_m;
684 if (code[feature_cntr++]) features |= cmpb_m;
685 if (code[feature_cntr++]) features |= popcntb_m;
686 if (code[feature_cntr++]) features |= popcntw_m;
687 if (code[feature_cntr++]) features |= fcfids_m;
688 if (code[feature_cntr++]) features |= vand_m;
689 if (code[feature_cntr++]) features |= lqarx_m;
690 if (code[feature_cntr++]) features |= vcipher_m;
691 if (code[feature_cntr++]) features |= vpmsumb_m;
692 if (code[feature_cntr++]) features |= tcheck_m;
693 if (code[feature_cntr++]) features |= mfdscr_m;
694
695 // Print the detection code.
696 if (PrintAssembly) {
697 ttyLocker ttyl;
698 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
699 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
700 }
701
702 _features = features;
703 }
704
705 // Power 8: Configure Data Stream Control Register.
706 void VM_Version::config_dscr() {
707 // 7 InstWords for each call (function descriptor + blr instruction).
708 const int code_size = (2+2*7)*BytesPerInstWord;
709
710 // Allocate space for the code.
711 ResourceMark rm;
712 CodeBuffer cb("config_dscr", code_size, 0);
713 MacroAssembler* a = new MacroAssembler(&cb);
714
715 // Emit code.
716 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
717 uint32_t *code = (uint32_t *)a->pc();
718 a->mfdscr(R3);
719 a->blr();
720
721 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
722 a->mtdscr(R3);
723 a->blr();
724
725 uint32_t *code_end = (uint32_t *)a->pc();
726 a->flush();
727
728 // Print the detection code.
729 if (PrintAssembly) {
730 ttyLocker ttyl;
731 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
732 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
733 }
734
735 // Apply the configuration if needed.
736 uint64_t dscr_val = (*get_dscr)();
737 if (Verbose) {
738 tty->print_cr("dscr value was 0x%lx" , dscr_val);
739 }
740 bool change_requested = false;
741 if (DSCR_PPC64 != (uintx)-1) {
742 dscr_val = DSCR_PPC64;
743 change_requested = true;
744 }
745 if (DSCR_DPFD_PPC64 <= 7) {
746 uint64_t mask = 0x7;
747 if ((dscr_val & mask) != DSCR_DPFD_PPC64) {
748 dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64);
749 change_requested = true;
750 }
751 }
752 if (DSCR_URG_PPC64 <= 7) {
753 uint64_t mask = 0x7 << 6;
754 if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
755 dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
756 change_requested = true;
757 }
758 }
759 if (change_requested) {
760 (*set_dscr)(dscr_val);
761 if (Verbose) {
762 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
763 }
764 }
765 }
766
767 static uint64_t saved_features = 0;
768
769 void VM_Version::allow_all() {
770 saved_features = _features;
771 _features = all_features_m;
772 }
773
774 void VM_Version::revert() {
775 _features = saved_features;
776 }