105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
106 }
107
108 MaxVectorSize = 8;
109 #endif
110
111 // Create and print feature-string.
112 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
113 jio_snprintf(buf, sizeof(buf),
114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s",
115 (has_fsqrt() ? " fsqrt" : ""),
116 (has_isel() ? " isel" : ""),
117 (has_lxarxeh() ? " lxarxeh" : ""),
118 (has_cmpb() ? " cmpb" : ""),
119 //(has_mftgpr()? " mftgpr" : ""),
120 (has_popcntb() ? " popcntb" : ""),
121 (has_popcntw() ? " popcntw" : ""),
122 (has_fcfids() ? " fcfids" : ""),
123 (has_vand() ? " vand" : ""),
124 (has_lqarx() ? " lqarx" : ""),
125 (has_vcipher() ? " vcipher" : ""),
126 (has_vpmsumb() ? " vpmsumb" : ""),
127 (has_tcheck() ? " tcheck" : ""),
128 (has_mfdscr() ? " mfdscr" : "")
129 // Make sure number of %s matches num_features!
130 );
131 _features_string = os::strdup(buf);
132 if (Verbose) {
133 print_features();
134 }
135
136 // PPC64 supports 8-byte compare-exchange operations (see
137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
139 _supports_cx8 = true;
140
141 // Used by C1.
142 _supports_atomic_getset4 = true;
143 _supports_atomic_getadd4 = true;
144 _supports_atomic_getset8 = true;
145 _supports_atomic_getadd8 = true;
169 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
170 }
171
172 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
173
174 // Implementation does not use any of the vector instructions
175 // available with Power8. Their exploitation is still pending.
176 if (!UseCRC32Intrinsics) {
177 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
178 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
179 }
180 }
181
182 if (UseCRC32CIntrinsics) {
183 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
184 warning("CRC32C intrinsics are not available on this CPU");
185 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
186 }
187
188 // The AES intrinsic stubs require AES instruction support.
189 if (UseAES) {
190 warning("AES instructions are not available on this CPU");
191 FLAG_SET_DEFAULT(UseAES, false);
192 }
193 if (UseAESIntrinsics) {
194 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
195 warning("AES intrinsics are not available on this CPU");
196 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
197 }
198
199 if (UseAESCTRIntrinsics) {
200 warning("AES/CTR intrinsics are not available on this CPU");
201 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
202 }
203
204 if (UseGHASHIntrinsics) {
205 warning("GHASH intrinsics are not available on this CPU");
206 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
207 }
208
209 if (UseSHA) {
210 warning("SHA instructions are not available on this CPU");
211 FLAG_SET_DEFAULT(UseSHA, false);
212 }
213 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
214 warning("SHA intrinsics are not available on this CPU");
215 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
216 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
217 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
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105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
106 }
107
108 MaxVectorSize = 8;
109 #endif
110
111 // Create and print feature-string.
112 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
113 jio_snprintf(buf, sizeof(buf),
114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s",
115 (has_fsqrt() ? " fsqrt" : ""),
116 (has_isel() ? " isel" : ""),
117 (has_lxarxeh() ? " lxarxeh" : ""),
118 (has_cmpb() ? " cmpb" : ""),
119 //(has_mftgpr()? " mftgpr" : ""),
120 (has_popcntb() ? " popcntb" : ""),
121 (has_popcntw() ? " popcntw" : ""),
122 (has_fcfids() ? " fcfids" : ""),
123 (has_vand() ? " vand" : ""),
124 (has_lqarx() ? " lqarx" : ""),
125 (has_vcipher() ? " aes" : ""),
126 (has_vpmsumb() ? " vpmsumb" : ""),
127 (has_tcheck() ? " tcheck" : ""),
128 (has_mfdscr() ? " mfdscr" : "")
129 // Make sure number of %s matches num_features!
130 );
131 _features_string = os::strdup(buf);
132 if (Verbose) {
133 print_features();
134 }
135
136 // PPC64 supports 8-byte compare-exchange operations (see
137 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
138 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
139 _supports_cx8 = true;
140
141 // Used by C1.
142 _supports_atomic_getset4 = true;
143 _supports_atomic_getadd4 = true;
144 _supports_atomic_getset8 = true;
145 _supports_atomic_getadd8 = true;
169 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
170 }
171
172 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
173
174 // Implementation does not use any of the vector instructions
175 // available with Power8. Their exploitation is still pending.
176 if (!UseCRC32Intrinsics) {
177 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
178 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
179 }
180 }
181
182 if (UseCRC32CIntrinsics) {
183 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
184 warning("CRC32C intrinsics are not available on this CPU");
185 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
186 }
187
188 // The AES intrinsic stubs require AES instruction support.
189 #if defined(VM_LITTLE_ENDIAN)
190 if (has_vcipher()) {
191 if (FLAG_IS_DEFAULT(UseAES)) {
192 UseAES = true;
193 }
194 } else if (UseAES) {
195 if (!FLAG_IS_DEFAULT(UseAES))
196 warning("AES instructions are not available on this CPU");
197 FLAG_SET_DEFAULT(UseAES, false);
198 }
199
200 if (UseAES && has_vcipher()) {
201 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
202 UseAESIntrinsics = true;
203 }
204 } else if (UseAESIntrinsics) {
205 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
206 warning("AES intrinsics are not available on this CPU");
207 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
208 }
209
210 #else
211 if (UseAES) {
212 warning("AES instructions are not available on this CPU");
213 FLAG_SET_DEFAULT(UseAES, false);
214 }
215 if (UseAESIntrinsics) {
216 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
217 warning("AES intrinsics are not available on this CPU");
218 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
219 }
220 #endif
221
222 if (UseAESCTRIntrinsics) {
223 warning("AES/CTR intrinsics are not available on this CPU");
224 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
225 }
226
227 if (UseGHASHIntrinsics) {
228 warning("GHASH intrinsics are not available on this CPU");
229 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
230 }
231
232 if (UseSHA) {
233 warning("SHA instructions are not available on this CPU");
234 FLAG_SET_DEFAULT(UseSHA, false);
235 }
236 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
237 warning("SHA intrinsics are not available on this CPU");
238 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
239 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
240 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
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