1 //
2 // Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
605 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr = (Assembler::ldst_op << 30)
952 | (dst_enc << 25)
953 | (primary << 19)
954 | (src1_enc << 14);
955
956 uint index = src2_enc;
957 int disp = disp32;
958
959 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
960 disp += STACK_BIAS;
961 // Check that stack offset fits, load into O7 if not
962 if (!Assembler::is_simm13(disp)) {
963 MacroAssembler _masm(&cbuf);
964 __ set(disp, O7);
965 if (index != R_G0_enc) {
966 __ add(O7, reg_to_register_object(index), O7);
967 }
968 index = R_O7_enc;
969 disp = 0;
970 }
971 }
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 if (VerifyOops) {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rspec);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1298 __ reserved_stack_check();
1299 }
1300
1301 // If this does safepoint polling, then do it here
1302 if(do_polling() && ra_->C->is_method_compilation()) {
1303 AddressLiteral polling_page(os::get_polling_page());
1304 __ sethi(polling_page, L0);
1305 __ relocate(relocInfo::poll_return_type);
1306 __ ld_ptr(L0, 0, G0);
1307 }
1308
1309 // If this is a return, then stuff the restore in the delay slot
1310 if(do_polling()) {
1311 if (UseCBCond && !ra_->C->is_method_compilation()) {
1312 // Insert extra padding for the case when the epilogue is preceded by
1313 // a cbcond jump, which can't be followed by a CTI instruction
1314 __ nop();
1315 }
1316 __ ret();
1317 __ delayed()->restore();
1318 } else {
1319 __ restore();
1320 }
1321 }
1322
1323 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1324 return MachNode::size(ra_);
1325 }
1326
1327 int MachEpilogNode::reloc() const {
1328 return 16; // a large enough number
1329 }
1330
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332 return MachNode::pipeline_class();
1333 }
1334
1335 int MachEpilogNode::safepoint_offset() const {
1336 assert( do_polling(), "no return for this epilog node");
1337 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339
1340 //=============================================================================
1341
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345 if (!OptoReg::is_valid(reg)) return rc_bad;
1346 if (OptoReg::is_stack(reg)) return rc_stack;
1347 VMReg r = OptoReg::as_VMReg(reg);
1348 if (r->is_Register()) return rc_int;
1349 assert(r->is_FloatRegister(), "must be");
1350 return rc_float;
1351 }
1352
1353 #ifndef PRODUCT
1354 ATTRIBUTE_PRINTF(2, 3)
1355 static void print_helper(outputStream* st, const char* format, ...) {
1356 if (st->position() > 0) {
1357 st->cr();
1358 st->sp();
1359 }
1360 va_list ap;
1361 va_start(ap, format);
1362 st->vprint(format, ap);
1363 va_end(ap);
1364 }
1365 #endif // !PRODUCT
1366
1367 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1368 if (cbuf) {
1369 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1370 }
1371 #ifndef PRODUCT
1372 else {
1373 if (is_load) {
1374 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1375 } else {
1376 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1377 }
1378 }
1379 #endif
1380 }
1381
1382 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1383 if (cbuf) {
1384 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1385 }
1386 #ifndef PRODUCT
1387 else {
1388 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1389 }
1390 #endif
1391 }
1392
1393 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1394 CodeBuffer *cbuf,
1395 PhaseRegAlloc *ra_,
1396 outputStream* st) {
1397 // Get registers to move
1398 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1399 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1400 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1401 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1402
1403 enum RC src_second_rc = rc_class(src_second);
1404 enum RC src_first_rc = rc_class(src_first);
1405 enum RC dst_second_rc = rc_class(dst_second);
1406 enum RC dst_first_rc = rc_class(dst_first);
1407
1408 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1409
1410 if (src_first == dst_first && src_second == dst_second) {
1411 return; // Self copy, no move
1412 }
1413
1414 // --------------------------------------
1415 // Check for mem-mem move. Load into unused float registers and fall into
1416 // the float-store case.
1417 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1418 int offset = ra_->reg2offset(src_first);
1419 // Further check for aligned-adjacent pair, so we can use a double load
1420 if ((src_first&1) == 0 && src_first+1 == src_second) {
1421 src_second = OptoReg::Name(R_F31_num);
1422 src_second_rc = rc_float;
1423 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1424 } else {
1425 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1426 }
1427 src_first = OptoReg::Name(R_F30_num);
1428 src_first_rc = rc_float;
1429 }
1430
1431 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1432 int offset = ra_->reg2offset(src_second);
1433 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1434 src_second = OptoReg::Name(R_F31_num);
1435 src_second_rc = rc_float;
1436 }
1437
1438 // --------------------------------------
1439 // Check for float->int copy; requires a trip through memory
1440 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1441 int offset = frame::register_save_words*wordSize;
1442 if (cbuf) {
1443 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1444 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1445 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1447 }
1448 #ifndef PRODUCT
1449 else {
1450 print_helper(st, "SUB R_SP,16,R_SP");
1451 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1452 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1453 print_helper(st, "ADD R_SP,16,R_SP");
1454 }
1455 #endif
1456 }
1457
1458 // Check for float->int copy on T4
1459 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1460 // Further check for aligned-adjacent pair, so we can use a double move
1461 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1463 return;
1464 }
1465 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1466 }
1467 // Check for int->float copy on T4
1468 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1469 // Further check for aligned-adjacent pair, so we can use a double move
1470 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1471 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1472 return;
1473 }
1474 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1475 }
1476
1477 // --------------------------------------
1478 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1479 // In such cases, I have to do the big-endian swap. For aligned targets, the
1480 // hardware does the flop for me. Doubles are always aligned, so no problem
1481 // there. Misaligned sources only come from native-long-returns (handled
1482 // special below).
1483 #ifndef _LP64
1484 if (src_first_rc == rc_int && // source is already big-endian
1485 src_second_rc != rc_bad && // 64-bit move
1486 ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1487 assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1488 // Do the big-endian flop.
1489 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1490 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1491 }
1492 #endif
1493
1494 // --------------------------------------
1495 // Check for integer reg-reg copy
1496 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1497 #ifndef _LP64
1498 if (src_first == R_O0_num && src_second == R_O1_num) { // Check for the evil O0/O1 native long-return case
1499 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1500 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1501 // operand contains the least significant word of the 64-bit value and vice versa.
1502 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1503 assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1504 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1505 if ( cbuf ) {
1506 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1507 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1508 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1509 #ifndef PRODUCT
1510 } else {
1511 print_helper(st, "SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1512 print_helper(st, "SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1513 print_helper(st, "OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1514 #endif
1515 }
1516 return;
1517 } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1518 // returning a long value in I0/I1
1519 // a SpillCopy must be able to target a return instruction's reg_class
1520 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1521 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1522 // operand contains the least significant word of the 64-bit value and vice versa.
1523 OptoReg::Name tdest = dst_first;
1524
1525 if (src_first == dst_first) {
1526 tdest = OptoReg::Name(R_O7_num);
1527 }
1528
1529 if (cbuf) {
1530 assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1531 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1532 // ShrL_reg_imm6
1533 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1534 // ShrR_reg_imm6 src, 0, dst
1535 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1536 if (tdest != dst_first) {
1537 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1538 }
1539 }
1540 #ifndef PRODUCT
1541 else {
1542 print_helper(st, "SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1543 print_helper(st, "SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1544 if (tdest != dst_first) {
1545 print_helper(st, "MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1546 }
1547 }
1548 #endif // PRODUCT
1549 return size+8;
1550 }
1551 #endif // !_LP64
1552 // Else normal reg-reg copy
1553 assert(src_second != dst_first, "smashed second before evacuating it");
1554 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1555 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1556 // This moves an aligned adjacent pair.
1557 // See if we are done.
1558 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1559 return;
1560 }
1561 }
1562
1563 // Check for integer store
1564 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1565 int offset = ra_->reg2offset(dst_first);
1566 // Further check for aligned-adjacent pair, so we can use a double store
1567 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1568 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1569 return;
1570 }
1571 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1572 }
1573
1574 // Check for integer load
1575 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1576 int offset = ra_->reg2offset(src_first);
1577 // Further check for aligned-adjacent pair, so we can use a double load
1578 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1579 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1580 return;
1581 }
1582 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1583 }
1584
1585 // Check for float reg-reg copy
1586 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1587 // Further check for aligned-adjacent pair, so we can use a double move
1588 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1589 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1590 return;
1591 }
1592 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1593 }
1594
1595 // Check for float store
1596 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1597 int offset = ra_->reg2offset(dst_first);
1598 // Further check for aligned-adjacent pair, so we can use a double store
1599 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1600 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1601 return;
1602 }
1603 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1604 }
1605
1606 // Check for float load
1607 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1608 int offset = ra_->reg2offset(src_first);
1609 // Further check for aligned-adjacent pair, so we can use a double load
1610 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1611 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1612 return;
1613 }
1614 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1615 }
1616
1617 // --------------------------------------------------------------------
1618 // Check for hi bits still needing moving. Only happens for misaligned
1619 // arguments to native calls.
1620 if (src_second == dst_second) {
1621 return; // Self copy; no move
1622 }
1623 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1624
1625 #ifndef _LP64
1626 // In the LP64 build, all registers can be moved as aligned/adjacent
1627 // pairs, so there's never any need to move the high bits separately.
1628 // The 32-bit builds have to deal with the 32-bit ABI which can force
1629 // all sorts of silly alignment problems.
1630
1631 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1632 // 32-bits of a 64-bit register, but are needed in low bits of another
1633 // register (else it's a hi-bits-to-hi-bits copy which should have
1634 // happened already as part of a 64-bit move)
1635 if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1636 assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1637 assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1638 // Shift src_second down to dst_second's low bits.
1639 if (cbuf) {
1640 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1641 #ifndef PRODUCT
1642 } else {
1643 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1644 #endif
1645 }
1646 return;
1647 }
1648
1649 // Check for high word integer store. Must down-shift the hi bits
1650 // into a temp register, then fall into the case of storing int bits.
1651 if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1652 // Shift src_second down to dst_second's low bits.
1653 if (cbuf) {
1654 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1655 #ifndef PRODUCT
1656 } else {
1657 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1658 #endif
1659 }
1660 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1661 }
1662
1663 // Check for high word integer load
1664 if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1665 return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1666
1667 // Check for high word integer store
1668 if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1669 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1670
1671 // Check for high word float store
1672 if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1673 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1674
1675 #endif // !_LP64
1676
1677 Unimplemented();
1678 }
1679
1680 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1681 PhaseRegAlloc *ra_,
1682 bool do_size,
1683 outputStream* st) const {
1684 assert(!do_size, "not supported");
1685 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1686 return 0;
1687 }
1688
1689 #ifndef PRODUCT
1690 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1691 implementation( NULL, ra_, false, st );
1692 }
1693 #endif
1694
1695 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1696 implementation( &cbuf, ra_, false, NULL );
1697 }
1698
1699 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1700 return MachNode::size(ra_);
1701 }
1702
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711 MacroAssembler _masm(&cbuf);
1712 for (int i = 0; i < _count; i += 1) {
1713 __ nop();
1714 }
1715 }
1716
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718 return 4 * _count;
1719 }
1720
1721
1722 //=============================================================================
1723 #ifndef PRODUCT
1724 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1725 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1726 int reg = ra_->get_reg_first(this);
1727 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1728 }
1729 #endif
1730
1731 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1732 MacroAssembler _masm(&cbuf);
1733 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1734 int reg = ra_->get_encode(this);
1735
1736 if (Assembler::is_simm13(offset)) {
1737 __ add(SP, offset, reg_to_register_object(reg));
1738 } else {
1739 __ set(offset, O7);
1740 __ add(SP, O7, reg_to_register_object(reg));
1741 }
1742 }
1743
1744 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1745 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1746 assert(ra_ == ra_->C->regalloc(), "sanity");
1747 return ra_->C->scratch_emit_size(this);
1748 }
1749
1750 //=============================================================================
1751 #ifndef PRODUCT
1752 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1753 st->print_cr("\nUEP:");
1754 #ifdef _LP64
1755 if (UseCompressedClassPointers) {
1756 assert(Universe::heap() != NULL, "java heap should be initialized");
1757 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1758 if (Universe::narrow_klass_base() != 0) {
1759 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1760 if (Universe::narrow_klass_shift() != 0) {
1761 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1762 }
1763 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1764 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1765 } else {
1766 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1767 }
1768 } else {
1769 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1770 }
1771 st->print_cr("\tCMP R_G5,R_G3" );
1772 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1773 #else // _LP64
1774 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1775 st->print_cr("\tCMP R_G5,R_G3" );
1776 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1777 #endif // _LP64
1778 }
1779 #endif
1780
1781 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1782 MacroAssembler _masm(&cbuf);
1783 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1784 Register temp_reg = G3;
1785 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1786
1787 // Load klass from receiver
1788 __ load_klass(O0, temp_reg);
1789 // Compare against expected klass
1790 __ cmp(temp_reg, G5_ic_reg);
1791 // Branch to miss code, checks xcc or icc depending
1792 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1793 }
1794
1795 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1796 return MachNode::size(ra_);
1797 }
1798
1799
1800 //=============================================================================
1801
1802
1803 // Emit exception handler code.
1804 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1805 Register temp_reg = G3;
1806 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1807 MacroAssembler _masm(&cbuf);
1808
1809 address base = __ start_a_stub(size_exception_handler());
1810 if (base == NULL) {
1811 ciEnv::current()->record_failure("CodeCache is full");
1812 return 0; // CodeBuffer::expand failed
1813 }
1814
1815 int offset = __ offset();
1816
1817 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1818 __ delayed()->nop();
1819
1820 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1821
1822 __ end_a_stub();
1823
1824 return offset;
1825 }
1826
1827 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1828 // Can't use any of the current frame's registers as we may have deopted
1829 // at a poll and everything (including G3) can be live.
1830 Register temp_reg = L0;
1831 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1832 MacroAssembler _masm(&cbuf);
1833
1834 address base = __ start_a_stub(size_deopt_handler());
1835 if (base == NULL) {
1836 ciEnv::current()->record_failure("CodeCache is full");
1837 return 0; // CodeBuffer::expand failed
1838 }
1839
1840 int offset = __ offset();
1841 __ save_frame(0);
1842 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1843 __ delayed()->restore();
1844
1845 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1846
1847 __ end_a_stub();
1848 return offset;
1849
1850 }
1851
1852 // Given a register encoding, produce a Integer Register object
1853 static Register reg_to_register_object(int register_encoding) {
1854 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1855 return as_Register(register_encoding);
1856 }
1857
1858 // Given a register encoding, produce a single-precision Float Register object
1859 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1860 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1861 return as_SingleFloatRegister(register_encoding);
1862 }
1863
1864 // Given a register encoding, produce a double-precision Float Register object
1865 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1866 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1867 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1868 return as_DoubleFloatRegister(register_encoding);
1869 }
1870
1871 const bool Matcher::match_rule_supported(int opcode) {
1872 if (!has_match_rule(opcode))
1873 return false;
1874
1875 switch (opcode) {
1876 case Op_CountLeadingZerosI:
1877 case Op_CountLeadingZerosL:
1878 case Op_CountTrailingZerosI:
1879 case Op_CountTrailingZerosL:
1880 case Op_PopCountI:
1881 case Op_PopCountL:
1882 if (!UsePopCountInstruction)
1883 return false;
1884 case Op_CompareAndSwapL:
1885 #ifdef _LP64
1886 case Op_CompareAndSwapP:
1887 #endif
1888 if (!VM_Version::supports_cx8())
1889 return false;
1890 break;
1891 }
1892
1893 return true; // Per default match rules are supported.
1894 }
1895
1896 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1897
1898 // TODO
1899 // identify extra cases that we might want to provide match rules for
1900 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1901 bool ret_value = match_rule_supported(opcode);
1902 // Add rules here.
1903
1904 return ret_value; // Per default match rules are supported.
1905 }
1906
1907 const bool Matcher::has_predicated_vectors(void) {
1908 return false;
1909 }
1910
1911 const int Matcher::float_pressure(int default_pressure_threshold) {
1912 return default_pressure_threshold;
1913 }
1914
1915 int Matcher::regnum_to_fpu_offset(int regnum) {
1916 return regnum - 32; // The FP registers are in the second chunk
1917 }
1918
1919 #ifdef ASSERT
1920 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1921 #endif
1922
1923 // Vector width in bytes
1924 const int Matcher::vector_width_in_bytes(BasicType bt) {
1925 assert(MaxVectorSize == 8, "");
1926 return 8;
1927 }
1928
1929 // Vector ideal reg
1930 const int Matcher::vector_ideal_reg(int size) {
1931 assert(MaxVectorSize == 8, "");
1932 return Op_RegD;
1933 }
1934
1935 const int Matcher::vector_shift_count_ideal_reg(int size) {
1936 fatal("vector shift is not supported");
1937 return Node::NotAMachineReg;
1938 }
1939
1940 // Limits on vector size (number of elements) loaded into vector.
1941 const int Matcher::max_vector_size(const BasicType bt) {
1942 assert(is_java_primitive(bt), "only primitive type vectors");
1943 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1944 }
1945
1946 const int Matcher::min_vector_size(const BasicType bt) {
1947 return max_vector_size(bt); // Same as max.
1948 }
1949
1950 // SPARC doesn't support misaligned vectors store/load.
1951 const bool Matcher::misaligned_vectors_ok() {
1952 return false;
1953 }
1954
1955 // Current (2013) SPARC platforms need to read original key
1956 // to construct decryption expanded key
1957 const bool Matcher::pass_original_key_for_aes() {
1958 return true;
1959 }
1960
1961 // USII supports fxtof through the whole range of number, USIII doesn't
1962 const bool Matcher::convL2FSupported(void) {
1963 return VM_Version::has_fast_fxtof();
1964 }
1965
1966 // Is this branch offset short enough that a short branch can be used?
1967 //
1968 // NOTE: If the platform does not provide any short branch variants, then
1969 // this method should return false for offset 0.
1970 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1971 // The passed offset is relative to address of the branch.
1972 // Don't need to adjust the offset.
1973 return UseCBCond && Assembler::is_simm12(offset);
1974 }
1975
1976 const bool Matcher::isSimpleConstant64(jlong value) {
1977 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1978 // Depends on optimizations in MacroAssembler::setx.
1979 int hi = (int)(value >> 32);
1980 int lo = (int)(value & ~0);
1981 return (hi == 0) || (hi == -1) || (lo == 0);
1982 }
1983
1984 // No scaling for the parameter the ClearArray node.
1985 const bool Matcher::init_array_count_is_in_bytes = true;
1986
1987 // No additional cost for CMOVL.
1988 const int Matcher::long_cmove_cost() { return 0; }
1989
1990 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1991 const int Matcher::float_cmove_cost() {
1992 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1993 }
1994
1995 // Does the CPU require late expand (see block.cpp for description of late expand)?
1996 const bool Matcher::require_postalloc_expand = false;
1997
1998 // Should the Matcher clone shifts on addressing modes, expecting them to
1999 // be subsumed into complex addressing expressions or compute them into
2000 // registers? True for Intel but false for most RISCs
2001 const bool Matcher::clone_shift_expressions = false;
2002
2003 // Do we need to mask the count passed to shift instructions or does
2004 // the cpu only look at the lower 5/6 bits anyway?
2005 const bool Matcher::need_masked_shift_count = false;
2006
2007 bool Matcher::narrow_oop_use_complex_address() {
2008 NOT_LP64(ShouldNotCallThis());
2009 assert(UseCompressedOops, "only for compressed oops code");
2010 return false;
2011 }
2012
2013 bool Matcher::narrow_klass_use_complex_address() {
2014 NOT_LP64(ShouldNotCallThis());
2015 assert(UseCompressedClassPointers, "only for compressed klass code");
2016 return false;
2017 }
2018
2019 // Is it better to copy float constants, or load them directly from memory?
2020 // Intel can load a float constant from a direct address, requiring no
2021 // extra registers. Most RISCs will have to materialize an address into a
2022 // register first, so they would do better to copy the constant from stack.
2023 const bool Matcher::rematerialize_float_constants = false;
2024
2025 // If CPU can load and store mis-aligned doubles directly then no fixup is
2026 // needed. Else we split the double into 2 integer pieces and move it
2027 // piece-by-piece. Only happens when passing doubles into C code as the
2028 // Java calling convention forces doubles to be aligned.
2029 #ifdef _LP64
2030 const bool Matcher::misaligned_doubles_ok = true;
2031 #else
2032 const bool Matcher::misaligned_doubles_ok = false;
2033 #endif
2034
2035 // No-op on SPARC.
2036 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2037 }
2038
2039 // Advertise here if the CPU requires explicit rounding operations
2040 // to implement the UseStrictFP mode.
2041 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2042
2043 // Are floats converted to double when stored to stack during deoptimization?
2044 // Sparc does not handle callee-save floats.
2045 bool Matcher::float_in_double() { return false; }
2046
2047 // Do ints take an entire long register or just half?
2048 // Note that we if-def off of _LP64.
2049 // The relevant question is how the int is callee-saved. In _LP64
2050 // the whole long is written but de-opt'ing will have to extract
2051 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2052 #ifdef _LP64
2053 const bool Matcher::int_in_long = true;
2054 #else
2055 const bool Matcher::int_in_long = false;
2056 #endif
2057
2058 // Return whether or not this register is ever used as an argument. This
2059 // function is used on startup to build the trampoline stubs in generateOptoStub.
2060 // Registers not mentioned will be killed by the VM call in the trampoline, and
2061 // arguments in those registers not be available to the callee.
2062 bool Matcher::can_be_java_arg( int reg ) {
2063 // Standard sparc 6 args in registers
2064 if( reg == R_I0_num ||
2065 reg == R_I1_num ||
2066 reg == R_I2_num ||
2067 reg == R_I3_num ||
2068 reg == R_I4_num ||
2069 reg == R_I5_num ) return true;
2070 #ifdef _LP64
2071 // 64-bit builds can pass 64-bit pointers and longs in
2072 // the high I registers
2073 if( reg == R_I0H_num ||
2074 reg == R_I1H_num ||
2075 reg == R_I2H_num ||
2076 reg == R_I3H_num ||
2077 reg == R_I4H_num ||
2078 reg == R_I5H_num ) return true;
2079
2080 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2081 return true;
2082 }
2083
2084 #else
2085 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2086 // Longs cannot be passed in O regs, because O regs become I regs
2087 // after a 'save' and I regs get their high bits chopped off on
2088 // interrupt.
2089 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2090 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2091 #endif
2092 // A few float args in registers
2093 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2094
2095 return false;
2096 }
2097
2098 bool Matcher::is_spillable_arg( int reg ) {
2099 return can_be_java_arg(reg);
2100 }
2101
2102 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2103 // Use hardware SDIVX instruction when it is
2104 // faster than a code which use multiply.
2105 return VM_Version::has_fast_idiv();
2106 }
2107
2108 // Register for DIVI projection of divmodI
2109 RegMask Matcher::divI_proj_mask() {
2110 ShouldNotReachHere();
2111 return RegMask();
2112 }
2113
2114 // Register for MODI projection of divmodI
2115 RegMask Matcher::modI_proj_mask() {
2116 ShouldNotReachHere();
2117 return RegMask();
2118 }
2119
2120 // Register for DIVL projection of divmodL
2121 RegMask Matcher::divL_proj_mask() {
2122 ShouldNotReachHere();
2123 return RegMask();
2124 }
2125
2126 // Register for MODL projection of divmodL
2127 RegMask Matcher::modL_proj_mask() {
2128 ShouldNotReachHere();
2129 return RegMask();
2130 }
2131
2132 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2133 return L7_REGP_mask();
2134 }
2135
2136 %}
2137
2138
2139 // The intptr_t operand types, defined by textual substitution.
2140 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2141 #ifdef _LP64
2142 #define immX immL
2143 #define immX13 immL13
2144 #define immX13m7 immL13m7
2145 #define iRegX iRegL
2146 #define g1RegX g1RegL
2147 #else
2148 #define immX immI
2149 #define immX13 immI13
2150 #define immX13m7 immI13m7
2151 #define iRegX iRegI
2152 #define g1RegX g1RegI
2153 #endif
2154
2155 //----------ENCODING BLOCK-----------------------------------------------------
2156 // This block specifies the encoding classes used by the compiler to output
2157 // byte streams. Encoding classes are parameterized macros used by
2158 // Machine Instruction Nodes in order to generate the bit encoding of the
2159 // instruction. Operands specify their base encoding interface with the
2160 // interface keyword. There are currently supported four interfaces,
2161 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2162 // operand to generate a function which returns its register number when
2163 // queried. CONST_INTER causes an operand to generate a function which
2164 // returns the value of the constant when queried. MEMORY_INTER causes an
2165 // operand to generate four functions which return the Base Register, the
2166 // Index Register, the Scale Value, and the Offset Value of the operand when
2167 // queried. COND_INTER causes an operand to generate six functions which
2168 // return the encoding code (ie - encoding bits for the instruction)
2169 // associated with each basic boolean condition for a conditional instruction.
2170 //
2171 // Instructions specify two basic values for encoding. Again, a function
2172 // is available to check if the constant displacement is an oop. They use the
2173 // ins_encode keyword to specify their encoding classes (which must be
2174 // a sequence of enc_class names, and their parameters, specified in
2175 // the encoding block), and they use the
2176 // opcode keyword to specify, in order, their primary, secondary, and
2177 // tertiary opcode. Only the opcode sections which a particular instruction
2178 // needs for encoding need to be specified.
2179 encode %{
2180 enc_class enc_untested %{
2181 #ifdef ASSERT
2182 MacroAssembler _masm(&cbuf);
2183 __ untested("encoding");
2184 #endif
2185 %}
2186
2187 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2188 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2189 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2190 %}
2191
2192 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2193 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2194 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2195 %}
2196
2197 enc_class form3_mem_prefetch_read( memory mem ) %{
2198 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2199 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2200 %}
2201
2202 enc_class form3_mem_prefetch_write( memory mem ) %{
2203 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2204 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2205 %}
2206
2207 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2208 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2209 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2210 guarantee($mem$$index == R_G0_enc, "double index?");
2211 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2212 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2213 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2214 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2215 %}
2216
2217 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2218 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2219 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2220 guarantee($mem$$index == R_G0_enc, "double index?");
2221 // Load long with 2 instructions
2222 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2223 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2224 %}
2225
2226 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2227 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2228 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2229 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2230 %}
2231
2232 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2233 // Encode a reg-reg copy. If it is useless, then empty encoding.
2234 if( $rs2$$reg != $rd$$reg )
2235 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2236 %}
2237
2238 // Target lo half of long
2239 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2240 // Encode a reg-reg copy. If it is useless, then empty encoding.
2241 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2242 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2243 %}
2244
2245 // Source lo half of long
2246 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2247 // Encode a reg-reg copy. If it is useless, then empty encoding.
2248 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2249 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2250 %}
2251
2252 // Target hi half of long
2253 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2254 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2255 %}
2256
2257 // Source lo half of long, and leave it sign extended.
2258 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2259 // Sign extend low half
2260 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2261 %}
2262
2263 // Source hi half of long, and leave it sign extended.
2264 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2265 // Shift high half to low half
2266 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2267 %}
2268
2269 // Source hi half of long
2270 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2271 // Encode a reg-reg copy. If it is useless, then empty encoding.
2272 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2273 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2274 %}
2275
2276 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2277 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2278 %}
2279
2280 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2281 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2282 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2283 %}
2284
2285 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2286 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2287 // clear if nothing else is happening
2288 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2289 // blt,a,pn done
2290 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2291 // mov dst,-1 in delay slot
2292 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2293 %}
2294
2295 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2296 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2297 %}
2298
2299 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2300 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2301 %}
2302
2303 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2304 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2305 %}
2306
2307 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2308 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2309 %}
2310
2311 enc_class move_return_pc_to_o1() %{
2312 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2313 %}
2314
2315 #ifdef _LP64
2316 /* %%% merge with enc_to_bool */
2317 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2318 MacroAssembler _masm(&cbuf);
2319
2320 Register src_reg = reg_to_register_object($src$$reg);
2321 Register dst_reg = reg_to_register_object($dst$$reg);
2322 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2323 %}
2324 #endif
2325
2326 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2327 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2328 MacroAssembler _masm(&cbuf);
2329
2330 Register p_reg = reg_to_register_object($p$$reg);
2331 Register q_reg = reg_to_register_object($q$$reg);
2332 Register y_reg = reg_to_register_object($y$$reg);
2333 Register tmp_reg = reg_to_register_object($tmp$$reg);
2334
2335 __ subcc( p_reg, q_reg, p_reg );
2336 __ add ( p_reg, y_reg, tmp_reg );
2337 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2338 %}
2339
2340 enc_class form_d2i_helper(regD src, regF dst) %{
2341 // fcmp %fcc0,$src,$src
2342 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2343 // branch %fcc0 not-nan, predict taken
2344 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2345 // fdtoi $src,$dst
2346 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2347 // fitos $dst,$dst (if nan)
2348 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2349 // clear $dst (if nan)
2350 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2351 // carry on here...
2352 %}
2353
2354 enc_class form_d2l_helper(regD src, regD dst) %{
2355 // fcmp %fcc0,$src,$src check for NAN
2356 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2357 // branch %fcc0 not-nan, predict taken
2358 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2359 // fdtox $src,$dst convert in delay slot
2360 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2361 // fxtod $dst,$dst (if nan)
2362 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2363 // clear $dst (if nan)
2364 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2365 // carry on here...
2366 %}
2367
2368 enc_class form_f2i_helper(regF src, regF dst) %{
2369 // fcmps %fcc0,$src,$src
2370 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2371 // branch %fcc0 not-nan, predict taken
2372 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2373 // fstoi $src,$dst
2374 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2375 // fitos $dst,$dst (if nan)
2376 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2377 // clear $dst (if nan)
2378 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2379 // carry on here...
2380 %}
2381
2382 enc_class form_f2l_helper(regF src, regD dst) %{
2383 // fcmps %fcc0,$src,$src
2384 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2385 // branch %fcc0 not-nan, predict taken
2386 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2387 // fstox $src,$dst
2388 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2389 // fxtod $dst,$dst (if nan)
2390 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2391 // clear $dst (if nan)
2392 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2393 // carry on here...
2394 %}
2395
2396 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2397 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2398 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2399 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2400
2401 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2402
2403 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2404 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2405
2406 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2407 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2408 %}
2409
2410 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2411 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2412 %}
2413
2414 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2415 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2416 %}
2417
2418 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2419 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2420 %}
2421
2422 enc_class form3_convI2F(regF rs2, regF rd) %{
2423 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2424 %}
2425
2426 // Encloding class for traceable jumps
2427 enc_class form_jmpl(g3RegP dest) %{
2428 emit_jmpl(cbuf, $dest$$reg);
2429 %}
2430
2431 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2432 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2433 %}
2434
2435 enc_class form2_nop() %{
2436 emit_nop(cbuf);
2437 %}
2438
2439 enc_class form2_illtrap() %{
2440 emit_illtrap(cbuf);
2441 %}
2442
2443
2444 // Compare longs and convert into -1, 0, 1.
2445 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2446 // CMP $src1,$src2
2447 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2448 // blt,a,pn done
2449 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2450 // mov dst,-1 in delay slot
2451 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2452 // bgt,a,pn done
2453 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2454 // mov dst,1 in delay slot
2455 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2456 // CLR $dst
2457 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2458 %}
2459
2460 enc_class enc_PartialSubtypeCheck() %{
2461 MacroAssembler _masm(&cbuf);
2462 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2463 __ delayed()->nop();
2464 %}
2465
2466 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2467 MacroAssembler _masm(&cbuf);
2468 Label* L = $labl$$label;
2469 Assembler::Predict predict_taken =
2470 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2471
2472 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2473 __ delayed()->nop();
2474 %}
2475
2476 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2477 MacroAssembler _masm(&cbuf);
2478 Label* L = $labl$$label;
2479 Assembler::Predict predict_taken =
2480 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2481
2482 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2483 __ delayed()->nop();
2484 %}
2485
2486 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2487 int op = (Assembler::arith_op << 30) |
2488 ($dst$$reg << 25) |
2489 (Assembler::movcc_op3 << 19) |
2490 (1 << 18) | // cc2 bit for 'icc'
2491 ($cmp$$cmpcode << 14) |
2492 (0 << 13) | // select register move
2493 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2494 ($src$$reg << 0);
2495 cbuf.insts()->emit_int32(op);
2496 %}
2497
2498 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2499 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2500 int op = (Assembler::arith_op << 30) |
2501 ($dst$$reg << 25) |
2502 (Assembler::movcc_op3 << 19) |
2503 (1 << 18) | // cc2 bit for 'icc'
2504 ($cmp$$cmpcode << 14) |
2505 (1 << 13) | // select immediate move
2506 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2507 (simm11 << 0);
2508 cbuf.insts()->emit_int32(op);
2509 %}
2510
2511 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2512 int op = (Assembler::arith_op << 30) |
2513 ($dst$$reg << 25) |
2514 (Assembler::movcc_op3 << 19) |
2515 (0 << 18) | // cc2 bit for 'fccX'
2516 ($cmp$$cmpcode << 14) |
2517 (0 << 13) | // select register move
2518 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2519 ($src$$reg << 0);
2520 cbuf.insts()->emit_int32(op);
2521 %}
2522
2523 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2524 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2525 int op = (Assembler::arith_op << 30) |
2526 ($dst$$reg << 25) |
2527 (Assembler::movcc_op3 << 19) |
2528 (0 << 18) | // cc2 bit for 'fccX'
2529 ($cmp$$cmpcode << 14) |
2530 (1 << 13) | // select immediate move
2531 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2532 (simm11 << 0);
2533 cbuf.insts()->emit_int32(op);
2534 %}
2535
2536 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2537 int op = (Assembler::arith_op << 30) |
2538 ($dst$$reg << 25) |
2539 (Assembler::fpop2_op3 << 19) |
2540 (0 << 18) |
2541 ($cmp$$cmpcode << 14) |
2542 (1 << 13) | // select register move
2543 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2544 ($primary << 5) | // select single, double or quad
2545 ($src$$reg << 0);
2546 cbuf.insts()->emit_int32(op);
2547 %}
2548
2549 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2550 int op = (Assembler::arith_op << 30) |
2551 ($dst$$reg << 25) |
2552 (Assembler::fpop2_op3 << 19) |
2553 (0 << 18) |
2554 ($cmp$$cmpcode << 14) |
2555 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2556 ($primary << 5) | // select single, double or quad
2557 ($src$$reg << 0);
2558 cbuf.insts()->emit_int32(op);
2559 %}
2560
2561 // Used by the MIN/MAX encodings. Same as a CMOV, but
2562 // the condition comes from opcode-field instead of an argument.
2563 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2564 int op = (Assembler::arith_op << 30) |
2565 ($dst$$reg << 25) |
2566 (Assembler::movcc_op3 << 19) |
2567 (1 << 18) | // cc2 bit for 'icc'
2568 ($primary << 14) |
2569 (0 << 13) | // select register move
2570 (0 << 11) | // cc1, cc0 bits for 'icc'
2571 ($src$$reg << 0);
2572 cbuf.insts()->emit_int32(op);
2573 %}
2574
2575 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2576 int op = (Assembler::arith_op << 30) |
2577 ($dst$$reg << 25) |
2578 (Assembler::movcc_op3 << 19) |
2579 (6 << 16) | // cc2 bit for 'xcc'
2580 ($primary << 14) |
2581 (0 << 13) | // select register move
2582 (0 << 11) | // cc1, cc0 bits for 'icc'
2583 ($src$$reg << 0);
2584 cbuf.insts()->emit_int32(op);
2585 %}
2586
2587 enc_class Set13( immI13 src, iRegI rd ) %{
2588 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2589 %}
2590
2591 enc_class SetHi22( immI src, iRegI rd ) %{
2592 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2593 %}
2594
2595 enc_class Set32( immI src, iRegI rd ) %{
2596 MacroAssembler _masm(&cbuf);
2597 __ set($src$$constant, reg_to_register_object($rd$$reg));
2598 %}
2599
2600 enc_class call_epilog %{
2601 if( VerifyStackAtCalls ) {
2602 MacroAssembler _masm(&cbuf);
2603 int framesize = ra_->C->frame_size_in_bytes();
2604 Register temp_reg = G3;
2605 __ add(SP, framesize, temp_reg);
2606 __ cmp(temp_reg, FP);
2607 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2608 }
2609 %}
2610
2611 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2612 // to G1 so the register allocator will not have to deal with the misaligned register
2613 // pair.
2614 enc_class adjust_long_from_native_call %{
2615 #ifndef _LP64
2616 if (returns_long()) {
2617 // sllx O0,32,O0
2618 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2619 // srl O1,0,O1
2620 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2621 // or O0,O1,G1
2622 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2623 }
2624 #endif
2625 %}
2626
2627 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2628 // CALL directly to the runtime
2629 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2630 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2631 %}
2632
2633 enc_class preserve_SP %{
2634 MacroAssembler _masm(&cbuf);
2635 __ mov(SP, L7_mh_SP_save);
2636 %}
2637
2638 enc_class restore_SP %{
2639 MacroAssembler _masm(&cbuf);
2640 __ mov(L7_mh_SP_save, SP);
2641 %}
2642
2643 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2644 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2645 // who we intended to call.
2646 if (!_method) {
2647 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2648 } else {
2649 int method_index = resolved_method_index(cbuf);
2650 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2651 : static_call_Relocation::spec(method_index);
2652 emit_call_reloc(cbuf, $meth$$method, rspec);
2653
2654 // Emit stub for static call.
2655 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2656 // Stub does not fit into scratch buffer if TraceJumps is enabled
2657 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2658 ciEnv::current()->record_failure("CodeCache is full");
2659 return;
2660 }
2661 }
2662 %}
2663
2664 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2665 MacroAssembler _masm(&cbuf);
2666 __ set_inst_mark();
2667 int vtable_index = this->_vtable_index;
2668 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2669 if (vtable_index < 0) {
2670 // must be invalid_vtable_index, not nonvirtual_vtable_index
2671 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2672 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2673 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2674 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2675 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2676 } else {
2677 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2678 // Just go thru the vtable
2679 // get receiver klass (receiver already checked for non-null)
2680 // If we end up going thru a c2i adapter interpreter expects method in G5
2681 int off = __ offset();
2682 __ load_klass(O0, G3_scratch);
2683 int klass_load_size;
2684 if (UseCompressedClassPointers) {
2685 assert(Universe::heap() != NULL, "java heap should be initialized");
2686 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2687 } else {
2688 klass_load_size = 1*BytesPerInstWord;
2689 }
2690 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2691 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2692 if (Assembler::is_simm13(v_off)) {
2693 __ ld_ptr(G3, v_off, G5_method);
2694 } else {
2695 // Generate 2 instructions
2696 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2697 __ or3(G5_method, v_off & 0x3ff, G5_method);
2698 // ld_ptr, set_hi, set
2699 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2700 "Unexpected instruction size(s)");
2701 __ ld_ptr(G3, G5_method, G5_method);
2702 }
2703 // NOTE: for vtable dispatches, the vtable entry will never be null.
2704 // However it may very well end up in handle_wrong_method if the
2705 // method is abstract for the particular class.
2706 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2707 // jump to target (either compiled code or c2iadapter)
2708 __ jmpl(G3_scratch, G0, O7);
2709 __ delayed()->nop();
2710 }
2711 %}
2712
2713 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2714 MacroAssembler _masm(&cbuf);
2715
2716 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2717 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2718 // we might be calling a C2I adapter which needs it.
2719
2720 assert(temp_reg != G5_ic_reg, "conflicting registers");
2721 // Load nmethod
2722 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2723
2724 // CALL to compiled java, indirect the contents of G3
2725 __ set_inst_mark();
2726 __ callr(temp_reg, G0);
2727 __ delayed()->nop();
2728 %}
2729
2730 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2731 MacroAssembler _masm(&cbuf);
2732 Register Rdividend = reg_to_register_object($src1$$reg);
2733 Register Rdivisor = reg_to_register_object($src2$$reg);
2734 Register Rresult = reg_to_register_object($dst$$reg);
2735
2736 __ sra(Rdivisor, 0, Rdivisor);
2737 __ sra(Rdividend, 0, Rdividend);
2738 __ sdivx(Rdividend, Rdivisor, Rresult);
2739 %}
2740
2741 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2742 MacroAssembler _masm(&cbuf);
2743
2744 Register Rdividend = reg_to_register_object($src1$$reg);
2745 int divisor = $imm$$constant;
2746 Register Rresult = reg_to_register_object($dst$$reg);
2747
2748 __ sra(Rdividend, 0, Rdividend);
2749 __ sdivx(Rdividend, divisor, Rresult);
2750 %}
2751
2752 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2753 MacroAssembler _masm(&cbuf);
2754 Register Rsrc1 = reg_to_register_object($src1$$reg);
2755 Register Rsrc2 = reg_to_register_object($src2$$reg);
2756 Register Rdst = reg_to_register_object($dst$$reg);
2757
2758 __ sra( Rsrc1, 0, Rsrc1 );
2759 __ sra( Rsrc2, 0, Rsrc2 );
2760 __ mulx( Rsrc1, Rsrc2, Rdst );
2761 __ srlx( Rdst, 32, Rdst );
2762 %}
2763
2764 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2765 MacroAssembler _masm(&cbuf);
2766 Register Rdividend = reg_to_register_object($src1$$reg);
2767 Register Rdivisor = reg_to_register_object($src2$$reg);
2768 Register Rresult = reg_to_register_object($dst$$reg);
2769 Register Rscratch = reg_to_register_object($scratch$$reg);
2770
2771 assert(Rdividend != Rscratch, "");
2772 assert(Rdivisor != Rscratch, "");
2773
2774 __ sra(Rdividend, 0, Rdividend);
2775 __ sra(Rdivisor, 0, Rdivisor);
2776 __ sdivx(Rdividend, Rdivisor, Rscratch);
2777 __ mulx(Rscratch, Rdivisor, Rscratch);
2778 __ sub(Rdividend, Rscratch, Rresult);
2779 %}
2780
2781 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2782 MacroAssembler _masm(&cbuf);
2783
2784 Register Rdividend = reg_to_register_object($src1$$reg);
2785 int divisor = $imm$$constant;
2786 Register Rresult = reg_to_register_object($dst$$reg);
2787 Register Rscratch = reg_to_register_object($scratch$$reg);
2788
2789 assert(Rdividend != Rscratch, "");
2790
2791 __ sra(Rdividend, 0, Rdividend);
2792 __ sdivx(Rdividend, divisor, Rscratch);
2793 __ mulx(Rscratch, divisor, Rscratch);
2794 __ sub(Rdividend, Rscratch, Rresult);
2795 %}
2796
2797 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2798 MacroAssembler _masm(&cbuf);
2799
2800 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2801 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2802
2803 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2804 %}
2805
2806 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2807 MacroAssembler _masm(&cbuf);
2808
2809 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2810 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2811
2812 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2813 %}
2814
2815 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2816 MacroAssembler _masm(&cbuf);
2817
2818 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2819 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2820
2821 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2822 %}
2823
2824 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2825 MacroAssembler _masm(&cbuf);
2826
2827 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2828 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2829
2830 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2831 %}
2832
2833 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2834 MacroAssembler _masm(&cbuf);
2835
2836 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2837 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2838
2839 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2840 %}
2841
2842 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2843 MacroAssembler _masm(&cbuf);
2844
2845 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2846 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2847
2848 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2849 %}
2850
2851 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2852 MacroAssembler _masm(&cbuf);
2853
2854 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2855 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2856
2857 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2858 %}
2859
2860 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2861 MacroAssembler _masm(&cbuf);
2862
2863 Register Roop = reg_to_register_object($oop$$reg);
2864 Register Rbox = reg_to_register_object($box$$reg);
2865 Register Rscratch = reg_to_register_object($scratch$$reg);
2866 Register Rmark = reg_to_register_object($scratch2$$reg);
2867
2868 assert(Roop != Rscratch, "");
2869 assert(Roop != Rmark, "");
2870 assert(Rbox != Rscratch, "");
2871 assert(Rbox != Rmark, "");
2872
2873 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2874 %}
2875
2876 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2877 MacroAssembler _masm(&cbuf);
2878
2879 Register Roop = reg_to_register_object($oop$$reg);
2880 Register Rbox = reg_to_register_object($box$$reg);
2881 Register Rscratch = reg_to_register_object($scratch$$reg);
2882 Register Rmark = reg_to_register_object($scratch2$$reg);
2883
2884 assert(Roop != Rscratch, "");
2885 assert(Roop != Rmark, "");
2886 assert(Rbox != Rscratch, "");
2887 assert(Rbox != Rmark, "");
2888
2889 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2890 %}
2891
2892 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2893 MacroAssembler _masm(&cbuf);
2894 Register Rmem = reg_to_register_object($mem$$reg);
2895 Register Rold = reg_to_register_object($old$$reg);
2896 Register Rnew = reg_to_register_object($new$$reg);
2897
2898 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2899 __ cmp( Rold, Rnew );
2900 %}
2901
2902 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2903 Register Rmem = reg_to_register_object($mem$$reg);
2904 Register Rold = reg_to_register_object($old$$reg);
2905 Register Rnew = reg_to_register_object($new$$reg);
2906
2907 MacroAssembler _masm(&cbuf);
2908 __ mov(Rnew, O7);
2909 __ casx(Rmem, Rold, O7);
2910 __ cmp( Rold, O7 );
2911 %}
2912
2913 // raw int cas, used for compareAndSwap
2914 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2915 Register Rmem = reg_to_register_object($mem$$reg);
2916 Register Rold = reg_to_register_object($old$$reg);
2917 Register Rnew = reg_to_register_object($new$$reg);
2918
2919 MacroAssembler _masm(&cbuf);
2920 __ mov(Rnew, O7);
2921 __ cas(Rmem, Rold, O7);
2922 __ cmp( Rold, O7 );
2923 %}
2924
2925 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2926 Register Rres = reg_to_register_object($res$$reg);
2927
2928 MacroAssembler _masm(&cbuf);
2929 __ mov(1, Rres);
2930 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2931 %}
2932
2933 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2934 Register Rres = reg_to_register_object($res$$reg);
2935
2936 MacroAssembler _masm(&cbuf);
2937 __ mov(1, Rres);
2938 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2939 %}
2940
2941 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2942 MacroAssembler _masm(&cbuf);
2943 Register Rdst = reg_to_register_object($dst$$reg);
2944 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2945 : reg_to_DoubleFloatRegister_object($src1$$reg);
2946 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2947 : reg_to_DoubleFloatRegister_object($src2$$reg);
2948
2949 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2950 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2951 %}
2952
2953 enc_class enc_rethrow() %{
2954 cbuf.set_insts_mark();
2955 Register temp_reg = G3;
2956 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2957 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2958 MacroAssembler _masm(&cbuf);
2959 #ifdef ASSERT
2960 __ save_frame(0);
2961 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2962 __ sethi(last_rethrow_addrlit, L1);
2963 Address addr(L1, last_rethrow_addrlit.low10());
2964 __ rdpc(L2);
2965 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2966 __ st_ptr(L2, addr);
2967 __ restore();
2968 #endif
2969 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2970 __ delayed()->nop();
2971 %}
2972
2973 enc_class emit_mem_nop() %{
2974 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2975 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2976 %}
2977
2978 enc_class emit_fadd_nop() %{
2979 // Generates the instruction FMOVS f31,f31
2980 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2981 %}
2982
2983 enc_class emit_br_nop() %{
2984 // Generates the instruction BPN,PN .
2985 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2986 %}
2987
2988 enc_class enc_membar_acquire %{
2989 MacroAssembler _masm(&cbuf);
2990 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2991 %}
2992
2993 enc_class enc_membar_release %{
2994 MacroAssembler _masm(&cbuf);
2995 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2996 %}
2997
2998 enc_class enc_membar_volatile %{
2999 MacroAssembler _masm(&cbuf);
3000 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3001 %}
3002
3003 %}
3004
3005 //----------FRAME--------------------------------------------------------------
3006 // Definition of frame structure and management information.
3007 //
3008 // S T A C K L A Y O U T Allocators stack-slot number
3009 // | (to get allocators register number
3010 // G Owned by | | v add VMRegImpl::stack0)
3011 // r CALLER | |
3012 // o | +--------+ pad to even-align allocators stack-slot
3013 // w V | pad0 | numbers; owned by CALLER
3014 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3015 // h ^ | in | 5
3016 // | | args | 4 Holes in incoming args owned by SELF
3017 // | | | | 3
3018 // | | +--------+
3019 // V | | old out| Empty on Intel, window on Sparc
3020 // | old |preserve| Must be even aligned.
3021 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3022 // | | in | 3 area for Intel ret address
3023 // Owned by |preserve| Empty on Sparc.
3024 // SELF +--------+
3025 // | | pad2 | 2 pad to align old SP
3026 // | +--------+ 1
3027 // | | locks | 0
3028 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3029 // | | pad1 | 11 pad to align new SP
3030 // | +--------+
3031 // | | | 10
3032 // | | spills | 9 spills
3033 // V | | 8 (pad0 slot for callee)
3034 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3035 // ^ | out | 7
3036 // | | args | 6 Holes in outgoing args owned by CALLEE
3037 // Owned by +--------+
3038 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3039 // | new |preserve| Must be even-aligned.
3040 // | SP-+--------+----> Matcher::_new_SP, even aligned
3041 // | | |
3042 //
3043 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3044 // known from SELF's arguments and the Java calling convention.
3045 // Region 6-7 is determined per call site.
3046 // Note 2: If the calling convention leaves holes in the incoming argument
3047 // area, those holes are owned by SELF. Holes in the outgoing area
3048 // are owned by the CALLEE. Holes should not be nessecary in the
3049 // incoming area, as the Java calling convention is completely under
3050 // the control of the AD file. Doubles can be sorted and packed to
3051 // avoid holes. Holes in the outgoing arguments may be necessary for
3052 // varargs C calling conventions.
3053 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3054 // even aligned with pad0 as needed.
3055 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3056 // region 6-11 is even aligned; it may be padded out more so that
3057 // the region from SP to FP meets the minimum stack alignment.
3058
3059 frame %{
3060 // What direction does stack grow in (assumed to be same for native & Java)
3061 stack_direction(TOWARDS_LOW);
3062
3063 // These two registers define part of the calling convention
3064 // between compiled code and the interpreter.
3065 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3066 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3067
3068 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3069 cisc_spilling_operand_name(indOffset);
3070
3071 // Number of stack slots consumed by a Monitor enter
3072 #ifdef _LP64
3073 sync_stack_slots(2);
3074 #else
3075 sync_stack_slots(1);
3076 #endif
3077
3078 // Compiled code's Frame Pointer
3079 frame_pointer(R_SP);
3080
3081 // Stack alignment requirement
3082 stack_alignment(StackAlignmentInBytes);
3083 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3084 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3085
3086 // Number of stack slots between incoming argument block and the start of
3087 // a new frame. The PROLOG must add this many slots to the stack. The
3088 // EPILOG must remove this many slots.
3089 in_preserve_stack_slots(0);
3090
3091 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3092 // for calls to C. Supports the var-args backing area for register parms.
3093 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3094 #ifdef _LP64
3095 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3096 varargs_C_out_slots_killed(12);
3097 #else
3098 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3099 varargs_C_out_slots_killed( 7);
3100 #endif
3101
3102 // The after-PROLOG location of the return address. Location of
3103 // return address specifies a type (REG or STACK) and a number
3104 // representing the register number (i.e. - use a register name) or
3105 // stack slot.
3106 return_addr(REG R_I7); // Ret Addr is in register I7
3107
3108 // Body of function which returns an OptoRegs array locating
3109 // arguments either in registers or in stack slots for calling
3110 // java
3111 calling_convention %{
3112 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3113
3114 %}
3115
3116 // Body of function which returns an OptoRegs array locating
3117 // arguments either in registers or in stack slots for calling
3118 // C.
3119 c_calling_convention %{
3120 // This is obviously always outgoing
3121 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3122 %}
3123
3124 // Location of native (C/C++) and interpreter return values. This is specified to
3125 // be the same as Java. In the 32-bit VM, long values are actually returned from
3126 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3127 // to and from the register pairs is done by the appropriate call and epilog
3128 // opcodes. This simplifies the register allocator.
3129 c_return_value %{
3130 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3131 #ifdef _LP64
3132 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3133 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3134 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3135 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3136 #else // !_LP64
3137 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3138 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3139 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3140 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3141 #endif
3142 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3143 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3144 %}
3145
3146 // Location of compiled Java return values. Same as C
3147 return_value %{
3148 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3149 #ifdef _LP64
3150 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3151 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3152 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3153 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3154 #else // !_LP64
3155 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3156 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3157 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3158 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3159 #endif
3160 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3161 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3162 %}
3163
3164 %}
3165
3166
3167 //----------ATTRIBUTES---------------------------------------------------------
3168 //----------Operand Attributes-------------------------------------------------
3169 op_attrib op_cost(1); // Required cost attribute
3170
3171 //----------Instruction Attributes---------------------------------------------
3172 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3173 ins_attrib ins_size(32); // Required size attribute (in bits)
3174
3175 // avoid_back_to_back attribute is an expression that must return
3176 // one of the following values defined in MachNode:
3177 // AVOID_NONE - instruction can be placed anywhere
3178 // AVOID_BEFORE - instruction cannot be placed after an
3179 // instruction with MachNode::AVOID_AFTER
3180 // AVOID_AFTER - the next instruction cannot be the one
3181 // with MachNode::AVOID_BEFORE
3182 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3183 // the same time
3184 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3185
3186 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3187 // non-matching short branch variant of some
3188 // long branch?
3189
3190 //----------OPERANDS-----------------------------------------------------------
3191 // Operand definitions must precede instruction definitions for correct parsing
3192 // in the ADLC because operands constitute user defined types which are used in
3193 // instruction definitions.
3194
3195 //----------Simple Operands----------------------------------------------------
3196 // Immediate Operands
3197 // Integer Immediate: 32-bit
3198 operand immI() %{
3199 match(ConI);
3200
3201 op_cost(0);
3202 // formats are generated automatically for constants and base registers
3203 format %{ %}
3204 interface(CONST_INTER);
3205 %}
3206
3207 // Integer Immediate: 0-bit
3208 operand immI0() %{
3209 predicate(n->get_int() == 0);
3210 match(ConI);
3211 op_cost(0);
3212
3213 format %{ %}
3214 interface(CONST_INTER);
3215 %}
3216
3217 // Integer Immediate: 5-bit
3218 operand immI5() %{
3219 predicate(Assembler::is_simm5(n->get_int()));
3220 match(ConI);
3221 op_cost(0);
3222 format %{ %}
3223 interface(CONST_INTER);
3224 %}
3225
3226 // Integer Immediate: 8-bit
3227 operand immI8() %{
3228 predicate(Assembler::is_simm8(n->get_int()));
3229 match(ConI);
3230 op_cost(0);
3231 format %{ %}
3232 interface(CONST_INTER);
3233 %}
3234
3235 // Integer Immediate: the value 10
3236 operand immI10() %{
3237 predicate(n->get_int() == 10);
3238 match(ConI);
3239 op_cost(0);
3240
3241 format %{ %}
3242 interface(CONST_INTER);
3243 %}
3244
3245 // Integer Immediate: 11-bit
3246 operand immI11() %{
3247 predicate(Assembler::is_simm11(n->get_int()));
3248 match(ConI);
3249 op_cost(0);
3250 format %{ %}
3251 interface(CONST_INTER);
3252 %}
3253
3254 // Integer Immediate: 13-bit
3255 operand immI13() %{
3256 predicate(Assembler::is_simm13(n->get_int()));
3257 match(ConI);
3258 op_cost(0);
3259
3260 format %{ %}
3261 interface(CONST_INTER);
3262 %}
3263
3264 // Integer Immediate: 13-bit minus 7
3265 operand immI13m7() %{
3266 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3267 match(ConI);
3268 op_cost(0);
3269
3270 format %{ %}
3271 interface(CONST_INTER);
3272 %}
3273
3274 // Integer Immediate: 16-bit
3275 operand immI16() %{
3276 predicate(Assembler::is_simm16(n->get_int()));
3277 match(ConI);
3278 op_cost(0);
3279 format %{ %}
3280 interface(CONST_INTER);
3281 %}
3282
3283 // Integer Immediate: the values 1-31
3284 operand immI_1_31() %{
3285 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3286 match(ConI);
3287 op_cost(0);
3288
3289 format %{ %}
3290 interface(CONST_INTER);
3291 %}
3292
3293 // Integer Immediate: the values 32-63
3294 operand immI_32_63() %{
3295 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3296 match(ConI);
3297 op_cost(0);
3298
3299 format %{ %}
3300 interface(CONST_INTER);
3301 %}
3302
3303 // Immediates for special shifts (sign extend)
3304
3305 // Integer Immediate: the value 16
3306 operand immI_16() %{
3307 predicate(n->get_int() == 16);
3308 match(ConI);
3309 op_cost(0);
3310
3311 format %{ %}
3312 interface(CONST_INTER);
3313 %}
3314
3315 // Integer Immediate: the value 24
3316 operand immI_24() %{
3317 predicate(n->get_int() == 24);
3318 match(ConI);
3319 op_cost(0);
3320
3321 format %{ %}
3322 interface(CONST_INTER);
3323 %}
3324 // Integer Immediate: the value 255
3325 operand immI_255() %{
3326 predicate( n->get_int() == 255 );
3327 match(ConI);
3328 op_cost(0);
3329
3330 format %{ %}
3331 interface(CONST_INTER);
3332 %}
3333
3334 // Integer Immediate: the value 65535
3335 operand immI_65535() %{
3336 predicate(n->get_int() == 65535);
3337 match(ConI);
3338 op_cost(0);
3339
3340 format %{ %}
3341 interface(CONST_INTER);
3342 %}
3343
3344 // Integer Immediate: the values 0-31
3345 operand immU5() %{
3346 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3347 match(ConI);
3348 op_cost(0);
3349
3350 format %{ %}
3351 interface(CONST_INTER);
3352 %}
3353
3354 // Integer Immediate: 6-bit
3355 operand immU6() %{
3356 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3357 match(ConI);
3358 op_cost(0);
3359 format %{ %}
3360 interface(CONST_INTER);
3361 %}
3362
3363 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3364 operand immU12() %{
3365 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3366 match(ConI);
3367 op_cost(0);
3368
3369 format %{ %}
3370 interface(CONST_INTER);
3371 %}
3372
3373 // Integer Immediate non-negative
3374 operand immU31()
3375 %{
3376 predicate(n->get_int() >= 0);
3377 match(ConI);
3378
3379 op_cost(0);
3380 format %{ %}
3381 interface(CONST_INTER);
3382 %}
3383
3384 // Long Immediate: the value FF
3385 operand immL_FF() %{
3386 predicate( n->get_long() == 0xFFL );
3387 match(ConL);
3388 op_cost(0);
3389
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3393
3394 // Long Immediate: the value FFFF
3395 operand immL_FFFF() %{
3396 predicate( n->get_long() == 0xFFFFL );
3397 match(ConL);
3398 op_cost(0);
3399
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403
3404 // Pointer Immediate: 32 or 64-bit
3405 operand immP() %{
3406 match(ConP);
3407
3408 op_cost(5);
3409 // formats are generated automatically for constants and base registers
3410 format %{ %}
3411 interface(CONST_INTER);
3412 %}
3413
3414 #ifdef _LP64
3415 // Pointer Immediate: 64-bit
3416 operand immP_set() %{
3417 predicate(!VM_Version::is_niagara_plus());
3418 match(ConP);
3419
3420 op_cost(5);
3421 // formats are generated automatically for constants and base registers
3422 format %{ %}
3423 interface(CONST_INTER);
3424 %}
3425
3426 // Pointer Immediate: 64-bit
3427 // From Niagara2 processors on a load should be better than materializing.
3428 operand immP_load() %{
3429 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3430 match(ConP);
3431
3432 op_cost(5);
3433 // formats are generated automatically for constants and base registers
3434 format %{ %}
3435 interface(CONST_INTER);
3436 %}
3437
3438 // Pointer Immediate: 64-bit
3439 operand immP_no_oop_cheap() %{
3440 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3441 match(ConP);
3442
3443 op_cost(5);
3444 // formats are generated automatically for constants and base registers
3445 format %{ %}
3446 interface(CONST_INTER);
3447 %}
3448 #endif
3449
3450 operand immP13() %{
3451 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3452 match(ConP);
3453 op_cost(0);
3454
3455 format %{ %}
3456 interface(CONST_INTER);
3457 %}
3458
3459 operand immP0() %{
3460 predicate(n->get_ptr() == 0);
3461 match(ConP);
3462 op_cost(0);
3463
3464 format %{ %}
3465 interface(CONST_INTER);
3466 %}
3467
3468 operand immP_poll() %{
3469 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3470 match(ConP);
3471
3472 // formats are generated automatically for constants and base registers
3473 format %{ %}
3474 interface(CONST_INTER);
3475 %}
3476
3477 // Pointer Immediate
3478 operand immN()
3479 %{
3480 match(ConN);
3481
3482 op_cost(10);
3483 format %{ %}
3484 interface(CONST_INTER);
3485 %}
3486
3487 operand immNKlass()
3488 %{
3489 match(ConNKlass);
3490
3491 op_cost(10);
3492 format %{ %}
3493 interface(CONST_INTER);
3494 %}
3495
3496 // NULL Pointer Immediate
3497 operand immN0()
3498 %{
3499 predicate(n->get_narrowcon() == 0);
3500 match(ConN);
3501
3502 op_cost(0);
3503 format %{ %}
3504 interface(CONST_INTER);
3505 %}
3506
3507 operand immL() %{
3508 match(ConL);
3509 op_cost(40);
3510 // formats are generated automatically for constants and base registers
3511 format %{ %}
3512 interface(CONST_INTER);
3513 %}
3514
3515 operand immL0() %{
3516 predicate(n->get_long() == 0L);
3517 match(ConL);
3518 op_cost(0);
3519 // formats are generated automatically for constants and base registers
3520 format %{ %}
3521 interface(CONST_INTER);
3522 %}
3523
3524 // Integer Immediate: 5-bit
3525 operand immL5() %{
3526 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3527 match(ConL);
3528 op_cost(0);
3529 format %{ %}
3530 interface(CONST_INTER);
3531 %}
3532
3533 // Long Immediate: 13-bit
3534 operand immL13() %{
3535 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3536 match(ConL);
3537 op_cost(0);
3538
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3542
3543 // Long Immediate: 13-bit minus 7
3544 operand immL13m7() %{
3545 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3546 match(ConL);
3547 op_cost(0);
3548
3549 format %{ %}
3550 interface(CONST_INTER);
3551 %}
3552
3553 // Long Immediate: low 32-bit mask
3554 operand immL_32bits() %{
3555 predicate(n->get_long() == 0xFFFFFFFFL);
3556 match(ConL);
3557 op_cost(0);
3558
3559 format %{ %}
3560 interface(CONST_INTER);
3561 %}
3562
3563 // Long Immediate: cheap (materialize in <= 3 instructions)
3564 operand immL_cheap() %{
3565 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3566 match(ConL);
3567 op_cost(0);
3568
3569 format %{ %}
3570 interface(CONST_INTER);
3571 %}
3572
3573 // Long Immediate: expensive (materialize in > 3 instructions)
3574 operand immL_expensive() %{
3575 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3576 match(ConL);
3577 op_cost(0);
3578
3579 format %{ %}
3580 interface(CONST_INTER);
3581 %}
3582
3583 // Double Immediate
3584 operand immD() %{
3585 match(ConD);
3586
3587 op_cost(40);
3588 format %{ %}
3589 interface(CONST_INTER);
3590 %}
3591
3592 // Double Immediate: +0.0d
3593 operand immD0() %{
3594 predicate(jlong_cast(n->getd()) == 0);
3595 match(ConD);
3596
3597 op_cost(0);
3598 format %{ %}
3599 interface(CONST_INTER);
3600 %}
3601
3602 // Float Immediate
3603 operand immF() %{
3604 match(ConF);
3605
3606 op_cost(20);
3607 format %{ %}
3608 interface(CONST_INTER);
3609 %}
3610
3611 // Float Immediate: +0.0f
3612 operand immF0() %{
3613 predicate(jint_cast(n->getf()) == 0);
3614 match(ConF);
3615
3616 op_cost(0);
3617 format %{ %}
3618 interface(CONST_INTER);
3619 %}
3620
3621 // Integer Register Operands
3622 // Integer Register
3623 operand iRegI() %{
3624 constraint(ALLOC_IN_RC(int_reg));
3625 match(RegI);
3626
3627 match(notemp_iRegI);
3628 match(g1RegI);
3629 match(o0RegI);
3630 match(iRegIsafe);
3631
3632 format %{ %}
3633 interface(REG_INTER);
3634 %}
3635
3636 operand notemp_iRegI() %{
3637 constraint(ALLOC_IN_RC(notemp_int_reg));
3638 match(RegI);
3639
3640 match(o0RegI);
3641
3642 format %{ %}
3643 interface(REG_INTER);
3644 %}
3645
3646 operand o0RegI() %{
3647 constraint(ALLOC_IN_RC(o0_regI));
3648 match(iRegI);
3649
3650 format %{ %}
3651 interface(REG_INTER);
3652 %}
3653
3654 // Pointer Register
3655 operand iRegP() %{
3656 constraint(ALLOC_IN_RC(ptr_reg));
3657 match(RegP);
3658
3659 match(lock_ptr_RegP);
3660 match(g1RegP);
3661 match(g2RegP);
3662 match(g3RegP);
3663 match(g4RegP);
3664 match(i0RegP);
3665 match(o0RegP);
3666 match(o1RegP);
3667 match(l7RegP);
3668
3669 format %{ %}
3670 interface(REG_INTER);
3671 %}
3672
3673 operand sp_ptr_RegP() %{
3674 constraint(ALLOC_IN_RC(sp_ptr_reg));
3675 match(RegP);
3676 match(iRegP);
3677
3678 format %{ %}
3679 interface(REG_INTER);
3680 %}
3681
3682 operand lock_ptr_RegP() %{
3683 constraint(ALLOC_IN_RC(lock_ptr_reg));
3684 match(RegP);
3685 match(i0RegP);
3686 match(o0RegP);
3687 match(o1RegP);
3688 match(l7RegP);
3689
3690 format %{ %}
3691 interface(REG_INTER);
3692 %}
3693
3694 operand g1RegP() %{
3695 constraint(ALLOC_IN_RC(g1_regP));
3696 match(iRegP);
3697
3698 format %{ %}
3699 interface(REG_INTER);
3700 %}
3701
3702 operand g2RegP() %{
3703 constraint(ALLOC_IN_RC(g2_regP));
3704 match(iRegP);
3705
3706 format %{ %}
3707 interface(REG_INTER);
3708 %}
3709
3710 operand g3RegP() %{
3711 constraint(ALLOC_IN_RC(g3_regP));
3712 match(iRegP);
3713
3714 format %{ %}
3715 interface(REG_INTER);
3716 %}
3717
3718 operand g1RegI() %{
3719 constraint(ALLOC_IN_RC(g1_regI));
3720 match(iRegI);
3721
3722 format %{ %}
3723 interface(REG_INTER);
3724 %}
3725
3726 operand g3RegI() %{
3727 constraint(ALLOC_IN_RC(g3_regI));
3728 match(iRegI);
3729
3730 format %{ %}
3731 interface(REG_INTER);
3732 %}
3733
3734 operand g4RegI() %{
3735 constraint(ALLOC_IN_RC(g4_regI));
3736 match(iRegI);
3737
3738 format %{ %}
3739 interface(REG_INTER);
3740 %}
3741
3742 operand g4RegP() %{
3743 constraint(ALLOC_IN_RC(g4_regP));
3744 match(iRegP);
3745
3746 format %{ %}
3747 interface(REG_INTER);
3748 %}
3749
3750 operand i0RegP() %{
3751 constraint(ALLOC_IN_RC(i0_regP));
3752 match(iRegP);
3753
3754 format %{ %}
3755 interface(REG_INTER);
3756 %}
3757
3758 operand o0RegP() %{
3759 constraint(ALLOC_IN_RC(o0_regP));
3760 match(iRegP);
3761
3762 format %{ %}
3763 interface(REG_INTER);
3764 %}
3765
3766 operand o1RegP() %{
3767 constraint(ALLOC_IN_RC(o1_regP));
3768 match(iRegP);
3769
3770 format %{ %}
3771 interface(REG_INTER);
3772 %}
3773
3774 operand o2RegP() %{
3775 constraint(ALLOC_IN_RC(o2_regP));
3776 match(iRegP);
3777
3778 format %{ %}
3779 interface(REG_INTER);
3780 %}
3781
3782 operand o7RegP() %{
3783 constraint(ALLOC_IN_RC(o7_regP));
3784 match(iRegP);
3785
3786 format %{ %}
3787 interface(REG_INTER);
3788 %}
3789
3790 operand l7RegP() %{
3791 constraint(ALLOC_IN_RC(l7_regP));
3792 match(iRegP);
3793
3794 format %{ %}
3795 interface(REG_INTER);
3796 %}
3797
3798 operand o7RegI() %{
3799 constraint(ALLOC_IN_RC(o7_regI));
3800 match(iRegI);
3801
3802 format %{ %}
3803 interface(REG_INTER);
3804 %}
3805
3806 operand iRegN() %{
3807 constraint(ALLOC_IN_RC(int_reg));
3808 match(RegN);
3809
3810 format %{ %}
3811 interface(REG_INTER);
3812 %}
3813
3814 // Long Register
3815 operand iRegL() %{
3816 constraint(ALLOC_IN_RC(long_reg));
3817 match(RegL);
3818
3819 format %{ %}
3820 interface(REG_INTER);
3821 %}
3822
3823 operand o2RegL() %{
3824 constraint(ALLOC_IN_RC(o2_regL));
3825 match(iRegL);
3826
3827 format %{ %}
3828 interface(REG_INTER);
3829 %}
3830
3831 operand o7RegL() %{
3832 constraint(ALLOC_IN_RC(o7_regL));
3833 match(iRegL);
3834
3835 format %{ %}
3836 interface(REG_INTER);
3837 %}
3838
3839 operand g1RegL() %{
3840 constraint(ALLOC_IN_RC(g1_regL));
3841 match(iRegL);
3842
3843 format %{ %}
3844 interface(REG_INTER);
3845 %}
3846
3847 operand g3RegL() %{
3848 constraint(ALLOC_IN_RC(g3_regL));
3849 match(iRegL);
3850
3851 format %{ %}
3852 interface(REG_INTER);
3853 %}
3854
3855 // Int Register safe
3856 // This is 64bit safe
3857 operand iRegIsafe() %{
3858 constraint(ALLOC_IN_RC(long_reg));
3859
3860 match(iRegI);
3861
3862 format %{ %}
3863 interface(REG_INTER);
3864 %}
3865
3866 // Condition Code Flag Register
3867 operand flagsReg() %{
3868 constraint(ALLOC_IN_RC(int_flags));
3869 match(RegFlags);
3870
3871 format %{ "ccr" %} // both ICC and XCC
3872 interface(REG_INTER);
3873 %}
3874
3875 // Condition Code Register, unsigned comparisons.
3876 operand flagsRegU() %{
3877 constraint(ALLOC_IN_RC(int_flags));
3878 match(RegFlags);
3879
3880 format %{ "icc_U" %}
3881 interface(REG_INTER);
3882 %}
3883
3884 // Condition Code Register, pointer comparisons.
3885 operand flagsRegP() %{
3886 constraint(ALLOC_IN_RC(int_flags));
3887 match(RegFlags);
3888
3889 #ifdef _LP64
3890 format %{ "xcc_P" %}
3891 #else
3892 format %{ "icc_P" %}
3893 #endif
3894 interface(REG_INTER);
3895 %}
3896
3897 // Condition Code Register, long comparisons.
3898 operand flagsRegL() %{
3899 constraint(ALLOC_IN_RC(int_flags));
3900 match(RegFlags);
3901
3902 format %{ "xcc_L" %}
3903 interface(REG_INTER);
3904 %}
3905
3906 // Condition Code Register, floating comparisons, unordered same as "less".
3907 operand flagsRegF() %{
3908 constraint(ALLOC_IN_RC(float_flags));
3909 match(RegFlags);
3910 match(flagsRegF0);
3911
3912 format %{ %}
3913 interface(REG_INTER);
3914 %}
3915
3916 operand flagsRegF0() %{
3917 constraint(ALLOC_IN_RC(float_flag0));
3918 match(RegFlags);
3919
3920 format %{ %}
3921 interface(REG_INTER);
3922 %}
3923
3924
3925 // Condition Code Flag Register used by long compare
3926 operand flagsReg_long_LTGE() %{
3927 constraint(ALLOC_IN_RC(int_flags));
3928 match(RegFlags);
3929 format %{ "icc_LTGE" %}
3930 interface(REG_INTER);
3931 %}
3932 operand flagsReg_long_EQNE() %{
3933 constraint(ALLOC_IN_RC(int_flags));
3934 match(RegFlags);
3935 format %{ "icc_EQNE" %}
3936 interface(REG_INTER);
3937 %}
3938 operand flagsReg_long_LEGT() %{
3939 constraint(ALLOC_IN_RC(int_flags));
3940 match(RegFlags);
3941 format %{ "icc_LEGT" %}
3942 interface(REG_INTER);
3943 %}
3944
3945
3946 operand regD() %{
3947 constraint(ALLOC_IN_RC(dflt_reg));
3948 match(RegD);
3949
3950 match(regD_low);
3951
3952 format %{ %}
3953 interface(REG_INTER);
3954 %}
3955
3956 operand regF() %{
3957 constraint(ALLOC_IN_RC(sflt_reg));
3958 match(RegF);
3959
3960 format %{ %}
3961 interface(REG_INTER);
3962 %}
3963
3964 operand regD_low() %{
3965 constraint(ALLOC_IN_RC(dflt_low_reg));
3966 match(regD);
3967
3968 format %{ %}
3969 interface(REG_INTER);
3970 %}
3971
3972 // Special Registers
3973
3974 // Method Register
3975 operand inline_cache_regP(iRegP reg) %{
3976 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3977 match(reg);
3978 format %{ %}
3979 interface(REG_INTER);
3980 %}
3981
3982 operand interpreter_method_oop_regP(iRegP reg) %{
3983 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3984 match(reg);
3985 format %{ %}
3986 interface(REG_INTER);
3987 %}
3988
3989
3990 //----------Complex Operands---------------------------------------------------
3991 // Indirect Memory Reference
3992 operand indirect(sp_ptr_RegP reg) %{
3993 constraint(ALLOC_IN_RC(sp_ptr_reg));
3994 match(reg);
3995
3996 op_cost(100);
3997 format %{ "[$reg]" %}
3998 interface(MEMORY_INTER) %{
3999 base($reg);
4000 index(0x0);
4001 scale(0x0);
4002 disp(0x0);
4003 %}
4004 %}
4005
4006 // Indirect with simm13 Offset
4007 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4008 constraint(ALLOC_IN_RC(sp_ptr_reg));
4009 match(AddP reg offset);
4010
4011 op_cost(100);
4012 format %{ "[$reg + $offset]" %}
4013 interface(MEMORY_INTER) %{
4014 base($reg);
4015 index(0x0);
4016 scale(0x0);
4017 disp($offset);
4018 %}
4019 %}
4020
4021 // Indirect with simm13 Offset minus 7
4022 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4023 constraint(ALLOC_IN_RC(sp_ptr_reg));
4024 match(AddP reg offset);
4025
4026 op_cost(100);
4027 format %{ "[$reg + $offset]" %}
4028 interface(MEMORY_INTER) %{
4029 base($reg);
4030 index(0x0);
4031 scale(0x0);
4032 disp($offset);
4033 %}
4034 %}
4035
4036 // Note: Intel has a swapped version also, like this:
4037 //operand indOffsetX(iRegI reg, immP offset) %{
4038 // constraint(ALLOC_IN_RC(int_reg));
4039 // match(AddP offset reg);
4040 //
4041 // op_cost(100);
4042 // format %{ "[$reg + $offset]" %}
4043 // interface(MEMORY_INTER) %{
4044 // base($reg);
4045 // index(0x0);
4046 // scale(0x0);
4047 // disp($offset);
4048 // %}
4049 //%}
4050 //// However, it doesn't make sense for SPARC, since
4051 // we have no particularly good way to embed oops in
4052 // single instructions.
4053
4054 // Indirect with Register Index
4055 operand indIndex(iRegP addr, iRegX index) %{
4056 constraint(ALLOC_IN_RC(ptr_reg));
4057 match(AddP addr index);
4058
4059 op_cost(100);
4060 format %{ "[$addr + $index]" %}
4061 interface(MEMORY_INTER) %{
4062 base($addr);
4063 index($index);
4064 scale(0x0);
4065 disp(0x0);
4066 %}
4067 %}
4068
4069 //----------Special Memory Operands--------------------------------------------
4070 // Stack Slot Operand - This operand is used for loading and storing temporary
4071 // values on the stack where a match requires a value to
4072 // flow through memory.
4073 operand stackSlotI(sRegI reg) %{
4074 constraint(ALLOC_IN_RC(stack_slots));
4075 op_cost(100);
4076 //match(RegI);
4077 format %{ "[$reg]" %}
4078 interface(MEMORY_INTER) %{
4079 base(0xE); // R_SP
4080 index(0x0);
4081 scale(0x0);
4082 disp($reg); // Stack Offset
4083 %}
4084 %}
4085
4086 operand stackSlotP(sRegP reg) %{
4087 constraint(ALLOC_IN_RC(stack_slots));
4088 op_cost(100);
4089 //match(RegP);
4090 format %{ "[$reg]" %}
4091 interface(MEMORY_INTER) %{
4092 base(0xE); // R_SP
4093 index(0x0);
4094 scale(0x0);
4095 disp($reg); // Stack Offset
4096 %}
4097 %}
4098
4099 operand stackSlotF(sRegF reg) %{
4100 constraint(ALLOC_IN_RC(stack_slots));
4101 op_cost(100);
4102 //match(RegF);
4103 format %{ "[$reg]" %}
4104 interface(MEMORY_INTER) %{
4105 base(0xE); // R_SP
4106 index(0x0);
4107 scale(0x0);
4108 disp($reg); // Stack Offset
4109 %}
4110 %}
4111 operand stackSlotD(sRegD reg) %{
4112 constraint(ALLOC_IN_RC(stack_slots));
4113 op_cost(100);
4114 //match(RegD);
4115 format %{ "[$reg]" %}
4116 interface(MEMORY_INTER) %{
4117 base(0xE); // R_SP
4118 index(0x0);
4119 scale(0x0);
4120 disp($reg); // Stack Offset
4121 %}
4122 %}
4123 operand stackSlotL(sRegL reg) %{
4124 constraint(ALLOC_IN_RC(stack_slots));
4125 op_cost(100);
4126 //match(RegL);
4127 format %{ "[$reg]" %}
4128 interface(MEMORY_INTER) %{
4129 base(0xE); // R_SP
4130 index(0x0);
4131 scale(0x0);
4132 disp($reg); // Stack Offset
4133 %}
4134 %}
4135
4136 // Operands for expressing Control Flow
4137 // NOTE: Label is a predefined operand which should not be redefined in
4138 // the AD file. It is generically handled within the ADLC.
4139
4140 //----------Conditional Branch Operands----------------------------------------
4141 // Comparison Op - This is the operation of the comparison, and is limited to
4142 // the following set of codes:
4143 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4144 //
4145 // Other attributes of the comparison, such as unsignedness, are specified
4146 // by the comparison instruction that sets a condition code flags register.
4147 // That result is represented by a flags operand whose subtype is appropriate
4148 // to the unsignedness (etc.) of the comparison.
4149 //
4150 // Later, the instruction which matches both the Comparison Op (a Bool) and
4151 // the flags (produced by the Cmp) specifies the coding of the comparison op
4152 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4153
4154 operand cmpOp() %{
4155 match(Bool);
4156
4157 format %{ "" %}
4158 interface(COND_INTER) %{
4159 equal(0x1);
4160 not_equal(0x9);
4161 less(0x3);
4162 greater_equal(0xB);
4163 less_equal(0x2);
4164 greater(0xA);
4165 overflow(0x7);
4166 no_overflow(0xF);
4167 %}
4168 %}
4169
4170 // Comparison Op, unsigned
4171 operand cmpOpU() %{
4172 match(Bool);
4173 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4174 n->as_Bool()->_test._test != BoolTest::no_overflow);
4175
4176 format %{ "u" %}
4177 interface(COND_INTER) %{
4178 equal(0x1);
4179 not_equal(0x9);
4180 less(0x5);
4181 greater_equal(0xD);
4182 less_equal(0x4);
4183 greater(0xC);
4184 overflow(0x7);
4185 no_overflow(0xF);
4186 %}
4187 %}
4188
4189 // Comparison Op, pointer (same as unsigned)
4190 operand cmpOpP() %{
4191 match(Bool);
4192 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4193 n->as_Bool()->_test._test != BoolTest::no_overflow);
4194
4195 format %{ "p" %}
4196 interface(COND_INTER) %{
4197 equal(0x1);
4198 not_equal(0x9);
4199 less(0x5);
4200 greater_equal(0xD);
4201 less_equal(0x4);
4202 greater(0xC);
4203 overflow(0x7);
4204 no_overflow(0xF);
4205 %}
4206 %}
4207
4208 // Comparison Op, branch-register encoding
4209 operand cmpOp_reg() %{
4210 match(Bool);
4211 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4212 n->as_Bool()->_test._test != BoolTest::no_overflow);
4213
4214 format %{ "" %}
4215 interface(COND_INTER) %{
4216 equal (0x1);
4217 not_equal (0x5);
4218 less (0x3);
4219 greater_equal(0x7);
4220 less_equal (0x2);
4221 greater (0x6);
4222 overflow(0x7); // not supported
4223 no_overflow(0xF); // not supported
4224 %}
4225 %}
4226
4227 // Comparison Code, floating, unordered same as less
4228 operand cmpOpF() %{
4229 match(Bool);
4230 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4231 n->as_Bool()->_test._test != BoolTest::no_overflow);
4232
4233 format %{ "fl" %}
4234 interface(COND_INTER) %{
4235 equal(0x9);
4236 not_equal(0x1);
4237 less(0x3);
4238 greater_equal(0xB);
4239 less_equal(0xE);
4240 greater(0x6);
4241
4242 overflow(0x7); // not supported
4243 no_overflow(0xF); // not supported
4244 %}
4245 %}
4246
4247 // Used by long compare
4248 operand cmpOp_commute() %{
4249 match(Bool);
4250 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4251 n->as_Bool()->_test._test != BoolTest::no_overflow);
4252
4253 format %{ "" %}
4254 interface(COND_INTER) %{
4255 equal(0x1);
4256 not_equal(0x9);
4257 less(0xA);
4258 greater_equal(0x2);
4259 less_equal(0xB);
4260 greater(0x3);
4261 overflow(0x7);
4262 no_overflow(0xF);
4263 %}
4264 %}
4265
4266 //----------OPERAND CLASSES----------------------------------------------------
4267 // Operand Classes are groups of operands that are used to simplify
4268 // instruction definitions by not requiring the AD writer to specify separate
4269 // instructions for every form of operand when the instruction accepts
4270 // multiple operand types with the same basic encoding and format. The classic
4271 // case of this is memory operands.
4272 opclass memory( indirect, indOffset13, indIndex );
4273 opclass indIndexMemory( indIndex );
4274
4275 //----------PIPELINE-----------------------------------------------------------
4276 pipeline %{
4277
4278 //----------ATTRIBUTES---------------------------------------------------------
4279 attributes %{
4280 fixed_size_instructions; // Fixed size instructions
4281 branch_has_delay_slot; // Branch has delay slot following
4282 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4283 instruction_unit_size = 4; // An instruction is 4 bytes long
4284 instruction_fetch_unit_size = 16; // The processor fetches one line
4285 instruction_fetch_units = 1; // of 16 bytes
4286
4287 // List of nop instructions
4288 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4289 %}
4290
4291 //----------RESOURCES----------------------------------------------------------
4292 // Resources are the functional units available to the machine
4293 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4294
4295 //----------PIPELINE DESCRIPTION-----------------------------------------------
4296 // Pipeline Description specifies the stages in the machine's pipeline
4297
4298 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4299
4300 //----------PIPELINE CLASSES---------------------------------------------------
4301 // Pipeline Classes describe the stages in which input and output are
4302 // referenced by the hardware pipeline.
4303
4304 // Integer ALU reg-reg operation
4305 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4306 single_instruction;
4307 dst : E(write);
4308 src1 : R(read);
4309 src2 : R(read);
4310 IALU : R;
4311 %}
4312
4313 // Integer ALU reg-reg long operation
4314 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4315 instruction_count(2);
4316 dst : E(write);
4317 src1 : R(read);
4318 src2 : R(read);
4319 IALU : R;
4320 IALU : R;
4321 %}
4322
4323 // Integer ALU reg-reg long dependent operation
4324 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4325 instruction_count(1); multiple_bundles;
4326 dst : E(write);
4327 src1 : R(read);
4328 src2 : R(read);
4329 cr : E(write);
4330 IALU : R(2);
4331 %}
4332
4333 // Integer ALU reg-imm operaion
4334 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4335 single_instruction;
4336 dst : E(write);
4337 src1 : R(read);
4338 IALU : R;
4339 %}
4340
4341 // Integer ALU reg-reg operation with condition code
4342 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4343 single_instruction;
4344 dst : E(write);
4345 cr : E(write);
4346 src1 : R(read);
4347 src2 : R(read);
4348 IALU : R;
4349 %}
4350
4351 // Integer ALU reg-imm operation with condition code
4352 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4353 single_instruction;
4354 dst : E(write);
4355 cr : E(write);
4356 src1 : R(read);
4357 IALU : R;
4358 %}
4359
4360 // Integer ALU zero-reg operation
4361 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4362 single_instruction;
4363 dst : E(write);
4364 src2 : R(read);
4365 IALU : R;
4366 %}
4367
4368 // Integer ALU zero-reg operation with condition code only
4369 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4370 single_instruction;
4371 cr : E(write);
4372 src : R(read);
4373 IALU : R;
4374 %}
4375
4376 // Integer ALU reg-reg operation with condition code only
4377 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4378 single_instruction;
4379 cr : E(write);
4380 src1 : R(read);
4381 src2 : R(read);
4382 IALU : R;
4383 %}
4384
4385 // Integer ALU reg-imm operation with condition code only
4386 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4387 single_instruction;
4388 cr : E(write);
4389 src1 : R(read);
4390 IALU : R;
4391 %}
4392
4393 // Integer ALU reg-reg-zero operation with condition code only
4394 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4395 single_instruction;
4396 cr : E(write);
4397 src1 : R(read);
4398 src2 : R(read);
4399 IALU : R;
4400 %}
4401
4402 // Integer ALU reg-imm-zero operation with condition code only
4403 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4404 single_instruction;
4405 cr : E(write);
4406 src1 : R(read);
4407 IALU : R;
4408 %}
4409
4410 // Integer ALU reg-reg operation with condition code, src1 modified
4411 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4412 single_instruction;
4413 cr : E(write);
4414 src1 : E(write);
4415 src1 : R(read);
4416 src2 : R(read);
4417 IALU : R;
4418 %}
4419
4420 // Integer ALU reg-imm operation with condition code, src1 modified
4421 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4422 single_instruction;
4423 cr : E(write);
4424 src1 : E(write);
4425 src1 : R(read);
4426 IALU : R;
4427 %}
4428
4429 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4430 multiple_bundles;
4431 dst : E(write)+4;
4432 cr : E(write);
4433 src1 : R(read);
4434 src2 : R(read);
4435 IALU : R(3);
4436 BR : R(2);
4437 %}
4438
4439 // Integer ALU operation
4440 pipe_class ialu_none(iRegI dst) %{
4441 single_instruction;
4442 dst : E(write);
4443 IALU : R;
4444 %}
4445
4446 // Integer ALU reg operation
4447 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4448 single_instruction; may_have_no_code;
4449 dst : E(write);
4450 src : R(read);
4451 IALU : R;
4452 %}
4453
4454 // Integer ALU reg conditional operation
4455 // This instruction has a 1 cycle stall, and cannot execute
4456 // in the same cycle as the instruction setting the condition
4457 // code. We kludge this by pretending to read the condition code
4458 // 1 cycle earlier, and by marking the functional units as busy
4459 // for 2 cycles with the result available 1 cycle later than
4460 // is really the case.
4461 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4462 single_instruction;
4463 op2_out : C(write);
4464 op1 : R(read);
4465 cr : R(read); // This is really E, with a 1 cycle stall
4466 BR : R(2);
4467 MS : R(2);
4468 %}
4469
4470 #ifdef _LP64
4471 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4472 instruction_count(1); multiple_bundles;
4473 dst : C(write)+1;
4474 src : R(read)+1;
4475 IALU : R(1);
4476 BR : E(2);
4477 MS : E(2);
4478 %}
4479 #endif
4480
4481 // Integer ALU reg operation
4482 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4483 single_instruction; may_have_no_code;
4484 dst : E(write);
4485 src : R(read);
4486 IALU : R;
4487 %}
4488 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4489 single_instruction; may_have_no_code;
4490 dst : E(write);
4491 src : R(read);
4492 IALU : R;
4493 %}
4494
4495 // Two integer ALU reg operations
4496 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4497 instruction_count(2);
4498 dst : E(write);
4499 src : R(read);
4500 A0 : R;
4501 A1 : R;
4502 %}
4503
4504 // Two integer ALU reg operations
4505 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4506 instruction_count(2); may_have_no_code;
4507 dst : E(write);
4508 src : R(read);
4509 A0 : R;
4510 A1 : R;
4511 %}
4512
4513 // Integer ALU imm operation
4514 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4515 single_instruction;
4516 dst : E(write);
4517 IALU : R;
4518 %}
4519
4520 // Integer ALU reg-reg with carry operation
4521 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4522 single_instruction;
4523 dst : E(write);
4524 src1 : R(read);
4525 src2 : R(read);
4526 IALU : R;
4527 %}
4528
4529 // Integer ALU cc operation
4530 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4531 single_instruction;
4532 dst : E(write);
4533 cc : R(read);
4534 IALU : R;
4535 %}
4536
4537 // Integer ALU cc / second IALU operation
4538 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4539 instruction_count(1); multiple_bundles;
4540 dst : E(write)+1;
4541 src : R(read);
4542 IALU : R;
4543 %}
4544
4545 // Integer ALU cc / second IALU operation
4546 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4547 instruction_count(1); multiple_bundles;
4548 dst : E(write)+1;
4549 p : R(read);
4550 q : R(read);
4551 IALU : R;
4552 %}
4553
4554 // Integer ALU hi-lo-reg operation
4555 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4556 instruction_count(1); multiple_bundles;
4557 dst : E(write)+1;
4558 IALU : R(2);
4559 %}
4560
4561 // Float ALU hi-lo-reg operation (with temp)
4562 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4563 instruction_count(1); multiple_bundles;
4564 dst : E(write)+1;
4565 IALU : R(2);
4566 %}
4567
4568 // Long Constant
4569 pipe_class loadConL( iRegL dst, immL src ) %{
4570 instruction_count(2); multiple_bundles;
4571 dst : E(write)+1;
4572 IALU : R(2);
4573 IALU : R(2);
4574 %}
4575
4576 // Pointer Constant
4577 pipe_class loadConP( iRegP dst, immP src ) %{
4578 instruction_count(0); multiple_bundles;
4579 fixed_latency(6);
4580 %}
4581
4582 // Polling Address
4583 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4584 #ifdef _LP64
4585 instruction_count(0); multiple_bundles;
4586 fixed_latency(6);
4587 #else
4588 dst : E(write);
4589 IALU : R;
4590 #endif
4591 %}
4592
4593 // Long Constant small
4594 pipe_class loadConLlo( iRegL dst, immL src ) %{
4595 instruction_count(2);
4596 dst : E(write);
4597 IALU : R;
4598 IALU : R;
4599 %}
4600
4601 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4602 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4603 instruction_count(1); multiple_bundles;
4604 src : R(read);
4605 dst : M(write)+1;
4606 IALU : R;
4607 MS : E;
4608 %}
4609
4610 // Integer ALU nop operation
4611 pipe_class ialu_nop() %{
4612 single_instruction;
4613 IALU : R;
4614 %}
4615
4616 // Integer ALU nop operation
4617 pipe_class ialu_nop_A0() %{
4618 single_instruction;
4619 A0 : R;
4620 %}
4621
4622 // Integer ALU nop operation
4623 pipe_class ialu_nop_A1() %{
4624 single_instruction;
4625 A1 : R;
4626 %}
4627
4628 // Integer Multiply reg-reg operation
4629 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4630 single_instruction;
4631 dst : E(write);
4632 src1 : R(read);
4633 src2 : R(read);
4634 MS : R(5);
4635 %}
4636
4637 // Integer Multiply reg-imm operation
4638 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4639 single_instruction;
4640 dst : E(write);
4641 src1 : R(read);
4642 MS : R(5);
4643 %}
4644
4645 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4646 single_instruction;
4647 dst : E(write)+4;
4648 src1 : R(read);
4649 src2 : R(read);
4650 MS : R(6);
4651 %}
4652
4653 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4654 single_instruction;
4655 dst : E(write)+4;
4656 src1 : R(read);
4657 MS : R(6);
4658 %}
4659
4660 // Integer Divide reg-reg
4661 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4662 instruction_count(1); multiple_bundles;
4663 dst : E(write);
4664 temp : E(write);
4665 src1 : R(read);
4666 src2 : R(read);
4667 temp : R(read);
4668 MS : R(38);
4669 %}
4670
4671 // Integer Divide reg-imm
4672 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4673 instruction_count(1); multiple_bundles;
4674 dst : E(write);
4675 temp : E(write);
4676 src1 : R(read);
4677 temp : R(read);
4678 MS : R(38);
4679 %}
4680
4681 // Long Divide
4682 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4683 dst : E(write)+71;
4684 src1 : R(read);
4685 src2 : R(read)+1;
4686 MS : R(70);
4687 %}
4688
4689 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4690 dst : E(write)+71;
4691 src1 : R(read);
4692 MS : R(70);
4693 %}
4694
4695 // Floating Point Add Float
4696 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4697 single_instruction;
4698 dst : X(write);
4699 src1 : E(read);
4700 src2 : E(read);
4701 FA : R;
4702 %}
4703
4704 // Floating Point Add Double
4705 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4706 single_instruction;
4707 dst : X(write);
4708 src1 : E(read);
4709 src2 : E(read);
4710 FA : R;
4711 %}
4712
4713 // Floating Point Conditional Move based on integer flags
4714 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4715 single_instruction;
4716 dst : X(write);
4717 src : E(read);
4718 cr : R(read);
4719 FA : R(2);
4720 BR : R(2);
4721 %}
4722
4723 // Floating Point Conditional Move based on integer flags
4724 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4725 single_instruction;
4726 dst : X(write);
4727 src : E(read);
4728 cr : R(read);
4729 FA : R(2);
4730 BR : R(2);
4731 %}
4732
4733 // Floating Point Multiply Float
4734 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4735 single_instruction;
4736 dst : X(write);
4737 src1 : E(read);
4738 src2 : E(read);
4739 FM : R;
4740 %}
4741
4742 // Floating Point Multiply Double
4743 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4744 single_instruction;
4745 dst : X(write);
4746 src1 : E(read);
4747 src2 : E(read);
4748 FM : R;
4749 %}
4750
4751 // Floating Point Divide Float
4752 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4753 single_instruction;
4754 dst : X(write);
4755 src1 : E(read);
4756 src2 : E(read);
4757 FM : R;
4758 FDIV : C(14);
4759 %}
4760
4761 // Floating Point Divide Double
4762 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4763 single_instruction;
4764 dst : X(write);
4765 src1 : E(read);
4766 src2 : E(read);
4767 FM : R;
4768 FDIV : C(17);
4769 %}
4770
4771 // Floating Point Move/Negate/Abs Float
4772 pipe_class faddF_reg(regF dst, regF src) %{
4773 single_instruction;
4774 dst : W(write);
4775 src : E(read);
4776 FA : R(1);
4777 %}
4778
4779 // Floating Point Move/Negate/Abs Double
4780 pipe_class faddD_reg(regD dst, regD src) %{
4781 single_instruction;
4782 dst : W(write);
4783 src : E(read);
4784 FA : R;
4785 %}
4786
4787 // Floating Point Convert F->D
4788 pipe_class fcvtF2D(regD dst, regF src) %{
4789 single_instruction;
4790 dst : X(write);
4791 src : E(read);
4792 FA : R;
4793 %}
4794
4795 // Floating Point Convert I->D
4796 pipe_class fcvtI2D(regD dst, regF src) %{
4797 single_instruction;
4798 dst : X(write);
4799 src : E(read);
4800 FA : R;
4801 %}
4802
4803 // Floating Point Convert LHi->D
4804 pipe_class fcvtLHi2D(regD dst, regD src) %{
4805 single_instruction;
4806 dst : X(write);
4807 src : E(read);
4808 FA : R;
4809 %}
4810
4811 // Floating Point Convert L->D
4812 pipe_class fcvtL2D(regD dst, regF src) %{
4813 single_instruction;
4814 dst : X(write);
4815 src : E(read);
4816 FA : R;
4817 %}
4818
4819 // Floating Point Convert L->F
4820 pipe_class fcvtL2F(regD dst, regF src) %{
4821 single_instruction;
4822 dst : X(write);
4823 src : E(read);
4824 FA : R;
4825 %}
4826
4827 // Floating Point Convert D->F
4828 pipe_class fcvtD2F(regD dst, regF src) %{
4829 single_instruction;
4830 dst : X(write);
4831 src : E(read);
4832 FA : R;
4833 %}
4834
4835 // Floating Point Convert I->L
4836 pipe_class fcvtI2L(regD dst, regF src) %{
4837 single_instruction;
4838 dst : X(write);
4839 src : E(read);
4840 FA : R;
4841 %}
4842
4843 // Floating Point Convert D->F
4844 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4845 instruction_count(1); multiple_bundles;
4846 dst : X(write)+6;
4847 src : E(read);
4848 FA : R;
4849 %}
4850
4851 // Floating Point Convert D->L
4852 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4853 instruction_count(1); multiple_bundles;
4854 dst : X(write)+6;
4855 src : E(read);
4856 FA : R;
4857 %}
4858
4859 // Floating Point Convert F->I
4860 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4861 instruction_count(1); multiple_bundles;
4862 dst : X(write)+6;
4863 src : E(read);
4864 FA : R;
4865 %}
4866
4867 // Floating Point Convert F->L
4868 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4869 instruction_count(1); multiple_bundles;
4870 dst : X(write)+6;
4871 src : E(read);
4872 FA : R;
4873 %}
4874
4875 // Floating Point Convert I->F
4876 pipe_class fcvtI2F(regF dst, regF src) %{
4877 single_instruction;
4878 dst : X(write);
4879 src : E(read);
4880 FA : R;
4881 %}
4882
4883 // Floating Point Compare
4884 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4885 single_instruction;
4886 cr : X(write);
4887 src1 : E(read);
4888 src2 : E(read);
4889 FA : R;
4890 %}
4891
4892 // Floating Point Compare
4893 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4894 single_instruction;
4895 cr : X(write);
4896 src1 : E(read);
4897 src2 : E(read);
4898 FA : R;
4899 %}
4900
4901 // Floating Add Nop
4902 pipe_class fadd_nop() %{
4903 single_instruction;
4904 FA : R;
4905 %}
4906
4907 // Integer Store to Memory
4908 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4909 single_instruction;
4910 mem : R(read);
4911 src : C(read);
4912 MS : R;
4913 %}
4914
4915 // Integer Store to Memory
4916 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4917 single_instruction;
4918 mem : R(read);
4919 src : C(read);
4920 MS : R;
4921 %}
4922
4923 // Integer Store Zero to Memory
4924 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4925 single_instruction;
4926 mem : R(read);
4927 MS : R;
4928 %}
4929
4930 // Special Stack Slot Store
4931 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4932 single_instruction;
4933 stkSlot : R(read);
4934 src : C(read);
4935 MS : R;
4936 %}
4937
4938 // Special Stack Slot Store
4939 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4940 instruction_count(2); multiple_bundles;
4941 stkSlot : R(read);
4942 src : C(read);
4943 MS : R(2);
4944 %}
4945
4946 // Float Store
4947 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4948 single_instruction;
4949 mem : R(read);
4950 src : C(read);
4951 MS : R;
4952 %}
4953
4954 // Float Store
4955 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4956 single_instruction;
4957 mem : R(read);
4958 MS : R;
4959 %}
4960
4961 // Double Store
4962 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4963 instruction_count(1);
4964 mem : R(read);
4965 src : C(read);
4966 MS : R;
4967 %}
4968
4969 // Double Store
4970 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4971 single_instruction;
4972 mem : R(read);
4973 MS : R;
4974 %}
4975
4976 // Special Stack Slot Float Store
4977 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4978 single_instruction;
4979 stkSlot : R(read);
4980 src : C(read);
4981 MS : R;
4982 %}
4983
4984 // Special Stack Slot Double Store
4985 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4986 single_instruction;
4987 stkSlot : R(read);
4988 src : C(read);
4989 MS : R;
4990 %}
4991
4992 // Integer Load (when sign bit propagation not needed)
4993 pipe_class iload_mem(iRegI dst, memory mem) %{
4994 single_instruction;
4995 mem : R(read);
4996 dst : C(write);
4997 MS : R;
4998 %}
4999
5000 // Integer Load from stack operand
5001 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5002 single_instruction;
5003 mem : R(read);
5004 dst : C(write);
5005 MS : R;
5006 %}
5007
5008 // Integer Load (when sign bit propagation or masking is needed)
5009 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5010 single_instruction;
5011 mem : R(read);
5012 dst : M(write);
5013 MS : R;
5014 %}
5015
5016 // Float Load
5017 pipe_class floadF_mem(regF dst, memory mem) %{
5018 single_instruction;
5019 mem : R(read);
5020 dst : M(write);
5021 MS : R;
5022 %}
5023
5024 // Float Load
5025 pipe_class floadD_mem(regD dst, memory mem) %{
5026 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5027 mem : R(read);
5028 dst : M(write);
5029 MS : R;
5030 %}
5031
5032 // Float Load
5033 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5034 single_instruction;
5035 stkSlot : R(read);
5036 dst : M(write);
5037 MS : R;
5038 %}
5039
5040 // Float Load
5041 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5042 single_instruction;
5043 stkSlot : R(read);
5044 dst : M(write);
5045 MS : R;
5046 %}
5047
5048 // Memory Nop
5049 pipe_class mem_nop() %{
5050 single_instruction;
5051 MS : R;
5052 %}
5053
5054 pipe_class sethi(iRegP dst, immI src) %{
5055 single_instruction;
5056 dst : E(write);
5057 IALU : R;
5058 %}
5059
5060 pipe_class loadPollP(iRegP poll) %{
5061 single_instruction;
5062 poll : R(read);
5063 MS : R;
5064 %}
5065
5066 pipe_class br(Universe br, label labl) %{
5067 single_instruction_with_delay_slot;
5068 BR : R;
5069 %}
5070
5071 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5072 single_instruction_with_delay_slot;
5073 cr : E(read);
5074 BR : R;
5075 %}
5076
5077 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5078 single_instruction_with_delay_slot;
5079 op1 : E(read);
5080 BR : R;
5081 MS : R;
5082 %}
5083
5084 // Compare and branch
5085 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5086 instruction_count(2); has_delay_slot;
5087 cr : E(write);
5088 src1 : R(read);
5089 src2 : R(read);
5090 IALU : R;
5091 BR : R;
5092 %}
5093
5094 // Compare and branch
5095 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5096 instruction_count(2); has_delay_slot;
5097 cr : E(write);
5098 src1 : R(read);
5099 IALU : R;
5100 BR : R;
5101 %}
5102
5103 // Compare and branch using cbcond
5104 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5105 single_instruction;
5106 src1 : E(read);
5107 src2 : E(read);
5108 IALU : R;
5109 BR : R;
5110 %}
5111
5112 // Compare and branch using cbcond
5113 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5114 single_instruction;
5115 src1 : E(read);
5116 IALU : R;
5117 BR : R;
5118 %}
5119
5120 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5121 single_instruction_with_delay_slot;
5122 cr : E(read);
5123 BR : R;
5124 %}
5125
5126 pipe_class br_nop() %{
5127 single_instruction;
5128 BR : R;
5129 %}
5130
5131 pipe_class simple_call(method meth) %{
5132 instruction_count(2); multiple_bundles; force_serialization;
5133 fixed_latency(100);
5134 BR : R(1);
5135 MS : R(1);
5136 A0 : R(1);
5137 %}
5138
5139 pipe_class compiled_call(method meth) %{
5140 instruction_count(1); multiple_bundles; force_serialization;
5141 fixed_latency(100);
5142 MS : R(1);
5143 %}
5144
5145 pipe_class call(method meth) %{
5146 instruction_count(0); multiple_bundles; force_serialization;
5147 fixed_latency(100);
5148 %}
5149
5150 pipe_class tail_call(Universe ignore, label labl) %{
5151 single_instruction; has_delay_slot;
5152 fixed_latency(100);
5153 BR : R(1);
5154 MS : R(1);
5155 %}
5156
5157 pipe_class ret(Universe ignore) %{
5158 single_instruction; has_delay_slot;
5159 BR : R(1);
5160 MS : R(1);
5161 %}
5162
5163 pipe_class ret_poll(g3RegP poll) %{
5164 instruction_count(3); has_delay_slot;
5165 poll : E(read);
5166 MS : R;
5167 %}
5168
5169 // The real do-nothing guy
5170 pipe_class empty( ) %{
5171 instruction_count(0);
5172 %}
5173
5174 pipe_class long_memory_op() %{
5175 instruction_count(0); multiple_bundles; force_serialization;
5176 fixed_latency(25);
5177 MS : R(1);
5178 %}
5179
5180 // Check-cast
5181 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5182 array : R(read);
5183 match : R(read);
5184 IALU : R(2);
5185 BR : R(2);
5186 MS : R;
5187 %}
5188
5189 // Convert FPU flags into +1,0,-1
5190 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5191 src1 : E(read);
5192 src2 : E(read);
5193 dst : E(write);
5194 FA : R;
5195 MS : R(2);
5196 BR : R(2);
5197 %}
5198
5199 // Compare for p < q, and conditionally add y
5200 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5201 p : E(read);
5202 q : E(read);
5203 y : E(read);
5204 IALU : R(3)
5205 %}
5206
5207 // Perform a compare, then move conditionally in a branch delay slot.
5208 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5209 src2 : E(read);
5210 srcdst : E(read);
5211 IALU : R;
5212 BR : R;
5213 %}
5214
5215 // Define the class for the Nop node
5216 define %{
5217 MachNop = ialu_nop;
5218 %}
5219
5220 %}
5221
5222 //----------INSTRUCTIONS-------------------------------------------------------
5223
5224 //------------Special Stack Slot instructions - no match rules-----------------
5225 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5226 // No match rule to avoid chain rule match.
5227 effect(DEF dst, USE src);
5228 ins_cost(MEMORY_REF_COST);
5229 format %{ "LDF $src,$dst\t! stkI to regF" %}
5230 opcode(Assembler::ldf_op3);
5231 ins_encode(simple_form3_mem_reg(src, dst));
5232 ins_pipe(floadF_stk);
5233 %}
5234
5235 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5236 // No match rule to avoid chain rule match.
5237 effect(DEF dst, USE src);
5238 ins_cost(MEMORY_REF_COST);
5239 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5240 opcode(Assembler::lddf_op3);
5241 ins_encode(simple_form3_mem_reg(src, dst));
5242 ins_pipe(floadD_stk);
5243 %}
5244
5245 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5246 // No match rule to avoid chain rule match.
5247 effect(DEF dst, USE src);
5248 ins_cost(MEMORY_REF_COST);
5249 format %{ "STF $src,$dst\t! regF to stkI" %}
5250 opcode(Assembler::stf_op3);
5251 ins_encode(simple_form3_mem_reg(dst, src));
5252 ins_pipe(fstoreF_stk_reg);
5253 %}
5254
5255 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5256 // No match rule to avoid chain rule match.
5257 effect(DEF dst, USE src);
5258 ins_cost(MEMORY_REF_COST);
5259 format %{ "STDF $src,$dst\t! regD to stkL" %}
5260 opcode(Assembler::stdf_op3);
5261 ins_encode(simple_form3_mem_reg(dst, src));
5262 ins_pipe(fstoreD_stk_reg);
5263 %}
5264
5265 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5266 effect(DEF dst, USE src);
5267 ins_cost(MEMORY_REF_COST*2);
5268 format %{ "STW $src,$dst.hi\t! long\n\t"
5269 "STW R_G0,$dst.lo" %}
5270 opcode(Assembler::stw_op3);
5271 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5272 ins_pipe(lstoreI_stk_reg);
5273 %}
5274
5275 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5276 // No match rule to avoid chain rule match.
5277 effect(DEF dst, USE src);
5278 ins_cost(MEMORY_REF_COST);
5279 format %{ "STX $src,$dst\t! regL to stkD" %}
5280 opcode(Assembler::stx_op3);
5281 ins_encode(simple_form3_mem_reg( dst, src ) );
5282 ins_pipe(istore_stk_reg);
5283 %}
5284
5285 //---------- Chain stack slots between similar types --------
5286
5287 // Load integer from stack slot
5288 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5289 match(Set dst src);
5290 ins_cost(MEMORY_REF_COST);
5291
5292 format %{ "LDUW $src,$dst\t!stk" %}
5293 opcode(Assembler::lduw_op3);
5294 ins_encode(simple_form3_mem_reg( src, dst ) );
5295 ins_pipe(iload_mem);
5296 %}
5297
5298 // Store integer to stack slot
5299 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5300 match(Set dst src);
5301 ins_cost(MEMORY_REF_COST);
5302
5303 format %{ "STW $src,$dst\t!stk" %}
5304 opcode(Assembler::stw_op3);
5305 ins_encode(simple_form3_mem_reg( dst, src ) );
5306 ins_pipe(istore_mem_reg);
5307 %}
5308
5309 // Load long from stack slot
5310 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5311 match(Set dst src);
5312
5313 ins_cost(MEMORY_REF_COST);
5314 format %{ "LDX $src,$dst\t! long" %}
5315 opcode(Assembler::ldx_op3);
5316 ins_encode(simple_form3_mem_reg( src, dst ) );
5317 ins_pipe(iload_mem);
5318 %}
5319
5320 // Store long to stack slot
5321 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5322 match(Set dst src);
5323
5324 ins_cost(MEMORY_REF_COST);
5325 format %{ "STX $src,$dst\t! long" %}
5326 opcode(Assembler::stx_op3);
5327 ins_encode(simple_form3_mem_reg( dst, src ) );
5328 ins_pipe(istore_mem_reg);
5329 %}
5330
5331 #ifdef _LP64
5332 // Load pointer from stack slot, 64-bit encoding
5333 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5334 match(Set dst src);
5335 ins_cost(MEMORY_REF_COST);
5336 format %{ "LDX $src,$dst\t!ptr" %}
5337 opcode(Assembler::ldx_op3);
5338 ins_encode(simple_form3_mem_reg( src, dst ) );
5339 ins_pipe(iload_mem);
5340 %}
5341
5342 // Store pointer to stack slot
5343 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5344 match(Set dst src);
5345 ins_cost(MEMORY_REF_COST);
5346 format %{ "STX $src,$dst\t!ptr" %}
5347 opcode(Assembler::stx_op3);
5348 ins_encode(simple_form3_mem_reg( dst, src ) );
5349 ins_pipe(istore_mem_reg);
5350 %}
5351 #else // _LP64
5352 // Load pointer from stack slot, 32-bit encoding
5353 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5354 match(Set dst src);
5355 ins_cost(MEMORY_REF_COST);
5356 format %{ "LDUW $src,$dst\t!ptr" %}
5357 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5358 ins_encode(simple_form3_mem_reg( src, dst ) );
5359 ins_pipe(iload_mem);
5360 %}
5361
5362 // Store pointer to stack slot
5363 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5364 match(Set dst src);
5365 ins_cost(MEMORY_REF_COST);
5366 format %{ "STW $src,$dst\t!ptr" %}
5367 opcode(Assembler::stw_op3, Assembler::ldst_op);
5368 ins_encode(simple_form3_mem_reg( dst, src ) );
5369 ins_pipe(istore_mem_reg);
5370 %}
5371 #endif // _LP64
5372
5373 //------------Special Nop instructions for bundling - no match rules-----------
5374 // Nop using the A0 functional unit
5375 instruct Nop_A0() %{
5376 ins_cost(0);
5377
5378 format %{ "NOP ! Alu Pipeline" %}
5379 opcode(Assembler::or_op3, Assembler::arith_op);
5380 ins_encode( form2_nop() );
5381 ins_pipe(ialu_nop_A0);
5382 %}
5383
5384 // Nop using the A1 functional unit
5385 instruct Nop_A1( ) %{
5386 ins_cost(0);
5387
5388 format %{ "NOP ! Alu Pipeline" %}
5389 opcode(Assembler::or_op3, Assembler::arith_op);
5390 ins_encode( form2_nop() );
5391 ins_pipe(ialu_nop_A1);
5392 %}
5393
5394 // Nop using the memory functional unit
5395 instruct Nop_MS( ) %{
5396 ins_cost(0);
5397
5398 format %{ "NOP ! Memory Pipeline" %}
5399 ins_encode( emit_mem_nop );
5400 ins_pipe(mem_nop);
5401 %}
5402
5403 // Nop using the floating add functional unit
5404 instruct Nop_FA( ) %{
5405 ins_cost(0);
5406
5407 format %{ "NOP ! Floating Add Pipeline" %}
5408 ins_encode( emit_fadd_nop );
5409 ins_pipe(fadd_nop);
5410 %}
5411
5412 // Nop using the branch functional unit
5413 instruct Nop_BR( ) %{
5414 ins_cost(0);
5415
5416 format %{ "NOP ! Branch Pipeline" %}
5417 ins_encode( emit_br_nop );
5418 ins_pipe(br_nop);
5419 %}
5420
5421 //----------Load/Store/Move Instructions---------------------------------------
5422 //----------Load Instructions--------------------------------------------------
5423 // Load Byte (8bit signed)
5424 instruct loadB(iRegI dst, memory mem) %{
5425 match(Set dst (LoadB mem));
5426 ins_cost(MEMORY_REF_COST);
5427
5428 size(4);
5429 format %{ "LDSB $mem,$dst\t! byte" %}
5430 ins_encode %{
5431 __ ldsb($mem$$Address, $dst$$Register);
5432 %}
5433 ins_pipe(iload_mask_mem);
5434 %}
5435
5436 // Load Byte (8bit signed) into a Long Register
5437 instruct loadB2L(iRegL dst, memory mem) %{
5438 match(Set dst (ConvI2L (LoadB mem)));
5439 ins_cost(MEMORY_REF_COST);
5440
5441 size(4);
5442 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5443 ins_encode %{
5444 __ ldsb($mem$$Address, $dst$$Register);
5445 %}
5446 ins_pipe(iload_mask_mem);
5447 %}
5448
5449 // Load Unsigned Byte (8bit UNsigned) into an int reg
5450 instruct loadUB(iRegI dst, memory mem) %{
5451 match(Set dst (LoadUB mem));
5452 ins_cost(MEMORY_REF_COST);
5453
5454 size(4);
5455 format %{ "LDUB $mem,$dst\t! ubyte" %}
5456 ins_encode %{
5457 __ ldub($mem$$Address, $dst$$Register);
5458 %}
5459 ins_pipe(iload_mem);
5460 %}
5461
5462 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5463 instruct loadUB2L(iRegL dst, memory mem) %{
5464 match(Set dst (ConvI2L (LoadUB mem)));
5465 ins_cost(MEMORY_REF_COST);
5466
5467 size(4);
5468 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5469 ins_encode %{
5470 __ ldub($mem$$Address, $dst$$Register);
5471 %}
5472 ins_pipe(iload_mem);
5473 %}
5474
5475 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5476 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5477 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5478 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5479
5480 size(2*4);
5481 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5482 "AND $dst,right_n_bits($mask, 8),$dst" %}
5483 ins_encode %{
5484 __ ldub($mem$$Address, $dst$$Register);
5485 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5486 %}
5487 ins_pipe(iload_mem);
5488 %}
5489
5490 // Load Short (16bit signed)
5491 instruct loadS(iRegI dst, memory mem) %{
5492 match(Set dst (LoadS mem));
5493 ins_cost(MEMORY_REF_COST);
5494
5495 size(4);
5496 format %{ "LDSH $mem,$dst\t! short" %}
5497 ins_encode %{
5498 __ ldsh($mem$$Address, $dst$$Register);
5499 %}
5500 ins_pipe(iload_mask_mem);
5501 %}
5502
5503 // Load Short (16 bit signed) to Byte (8 bit signed)
5504 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5505 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5506 ins_cost(MEMORY_REF_COST);
5507
5508 size(4);
5509
5510 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5511 ins_encode %{
5512 __ ldsb($mem$$Address, $dst$$Register, 1);
5513 %}
5514 ins_pipe(iload_mask_mem);
5515 %}
5516
5517 // Load Short (16bit signed) into a Long Register
5518 instruct loadS2L(iRegL dst, memory mem) %{
5519 match(Set dst (ConvI2L (LoadS mem)));
5520 ins_cost(MEMORY_REF_COST);
5521
5522 size(4);
5523 format %{ "LDSH $mem,$dst\t! short -> long" %}
5524 ins_encode %{
5525 __ ldsh($mem$$Address, $dst$$Register);
5526 %}
5527 ins_pipe(iload_mask_mem);
5528 %}
5529
5530 // Load Unsigned Short/Char (16bit UNsigned)
5531 instruct loadUS(iRegI dst, memory mem) %{
5532 match(Set dst (LoadUS mem));
5533 ins_cost(MEMORY_REF_COST);
5534
5535 size(4);
5536 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5537 ins_encode %{
5538 __ lduh($mem$$Address, $dst$$Register);
5539 %}
5540 ins_pipe(iload_mem);
5541 %}
5542
5543 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5544 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5545 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5546 ins_cost(MEMORY_REF_COST);
5547
5548 size(4);
5549 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5550 ins_encode %{
5551 __ ldsb($mem$$Address, $dst$$Register, 1);
5552 %}
5553 ins_pipe(iload_mask_mem);
5554 %}
5555
5556 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5557 instruct loadUS2L(iRegL dst, memory mem) %{
5558 match(Set dst (ConvI2L (LoadUS mem)));
5559 ins_cost(MEMORY_REF_COST);
5560
5561 size(4);
5562 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5563 ins_encode %{
5564 __ lduh($mem$$Address, $dst$$Register);
5565 %}
5566 ins_pipe(iload_mem);
5567 %}
5568
5569 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5570 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5571 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5572 ins_cost(MEMORY_REF_COST);
5573
5574 size(4);
5575 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5576 ins_encode %{
5577 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5578 %}
5579 ins_pipe(iload_mem);
5580 %}
5581
5582 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5583 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5584 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5585 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5586
5587 size(2*4);
5588 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5589 "AND $dst,$mask,$dst" %}
5590 ins_encode %{
5591 Register Rdst = $dst$$Register;
5592 __ lduh($mem$$Address, Rdst);
5593 __ and3(Rdst, $mask$$constant, Rdst);
5594 %}
5595 ins_pipe(iload_mem);
5596 %}
5597
5598 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5599 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5600 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5601 effect(TEMP dst, TEMP tmp);
5602 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5603
5604 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5605 "SET right_n_bits($mask, 16),$tmp\n\t"
5606 "AND $dst,$tmp,$dst" %}
5607 ins_encode %{
5608 Register Rdst = $dst$$Register;
5609 Register Rtmp = $tmp$$Register;
5610 __ lduh($mem$$Address, Rdst);
5611 __ set($mask$$constant & right_n_bits(16), Rtmp);
5612 __ and3(Rdst, Rtmp, Rdst);
5613 %}
5614 ins_pipe(iload_mem);
5615 %}
5616
5617 // Load Integer
5618 instruct loadI(iRegI dst, memory mem) %{
5619 match(Set dst (LoadI mem));
5620 ins_cost(MEMORY_REF_COST);
5621
5622 size(4);
5623 format %{ "LDUW $mem,$dst\t! int" %}
5624 ins_encode %{
5625 __ lduw($mem$$Address, $dst$$Register);
5626 %}
5627 ins_pipe(iload_mem);
5628 %}
5629
5630 // Load Integer to Byte (8 bit signed)
5631 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5632 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5633 ins_cost(MEMORY_REF_COST);
5634
5635 size(4);
5636
5637 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5638 ins_encode %{
5639 __ ldsb($mem$$Address, $dst$$Register, 3);
5640 %}
5641 ins_pipe(iload_mask_mem);
5642 %}
5643
5644 // Load Integer to Unsigned Byte (8 bit UNsigned)
5645 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5646 match(Set dst (AndI (LoadI mem) mask));
5647 ins_cost(MEMORY_REF_COST);
5648
5649 size(4);
5650
5651 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5652 ins_encode %{
5653 __ ldub($mem$$Address, $dst$$Register, 3);
5654 %}
5655 ins_pipe(iload_mask_mem);
5656 %}
5657
5658 // Load Integer to Short (16 bit signed)
5659 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5660 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5661 ins_cost(MEMORY_REF_COST);
5662
5663 size(4);
5664
5665 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5666 ins_encode %{
5667 __ ldsh($mem$$Address, $dst$$Register, 2);
5668 %}
5669 ins_pipe(iload_mask_mem);
5670 %}
5671
5672 // Load Integer to Unsigned Short (16 bit UNsigned)
5673 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5674 match(Set dst (AndI (LoadI mem) mask));
5675 ins_cost(MEMORY_REF_COST);
5676
5677 size(4);
5678
5679 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5680 ins_encode %{
5681 __ lduh($mem$$Address, $dst$$Register, 2);
5682 %}
5683 ins_pipe(iload_mask_mem);
5684 %}
5685
5686 // Load Integer into a Long Register
5687 instruct loadI2L(iRegL dst, memory mem) %{
5688 match(Set dst (ConvI2L (LoadI mem)));
5689 ins_cost(MEMORY_REF_COST);
5690
5691 size(4);
5692 format %{ "LDSW $mem,$dst\t! int -> long" %}
5693 ins_encode %{
5694 __ ldsw($mem$$Address, $dst$$Register);
5695 %}
5696 ins_pipe(iload_mask_mem);
5697 %}
5698
5699 // Load Integer with mask 0xFF into a Long Register
5700 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5701 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5702 ins_cost(MEMORY_REF_COST);
5703
5704 size(4);
5705 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5706 ins_encode %{
5707 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5708 %}
5709 ins_pipe(iload_mem);
5710 %}
5711
5712 // Load Integer with mask 0xFFFF into a Long Register
5713 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5714 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5715 ins_cost(MEMORY_REF_COST);
5716
5717 size(4);
5718 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5719 ins_encode %{
5720 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5721 %}
5722 ins_pipe(iload_mem);
5723 %}
5724
5725 // Load Integer with a 12-bit mask into a Long Register
5726 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5727 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5728 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5729
5730 size(2*4);
5731 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5732 "AND $dst,$mask,$dst" %}
5733 ins_encode %{
5734 Register Rdst = $dst$$Register;
5735 __ lduw($mem$$Address, Rdst);
5736 __ and3(Rdst, $mask$$constant, Rdst);
5737 %}
5738 ins_pipe(iload_mem);
5739 %}
5740
5741 // Load Integer with a 31-bit mask into a Long Register
5742 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5743 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5744 effect(TEMP dst, TEMP tmp);
5745 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5746
5747 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5748 "SET $mask,$tmp\n\t"
5749 "AND $dst,$tmp,$dst" %}
5750 ins_encode %{
5751 Register Rdst = $dst$$Register;
5752 Register Rtmp = $tmp$$Register;
5753 __ lduw($mem$$Address, Rdst);
5754 __ set($mask$$constant, Rtmp);
5755 __ and3(Rdst, Rtmp, Rdst);
5756 %}
5757 ins_pipe(iload_mem);
5758 %}
5759
5760 // Load Unsigned Integer into a Long Register
5761 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5762 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5763 ins_cost(MEMORY_REF_COST);
5764
5765 size(4);
5766 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5767 ins_encode %{
5768 __ lduw($mem$$Address, $dst$$Register);
5769 %}
5770 ins_pipe(iload_mem);
5771 %}
5772
5773 // Load Long - aligned
5774 instruct loadL(iRegL dst, memory mem ) %{
5775 match(Set dst (LoadL mem));
5776 ins_cost(MEMORY_REF_COST);
5777
5778 size(4);
5779 format %{ "LDX $mem,$dst\t! long" %}
5780 ins_encode %{
5781 __ ldx($mem$$Address, $dst$$Register);
5782 %}
5783 ins_pipe(iload_mem);
5784 %}
5785
5786 // Load Long - UNaligned
5787 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5788 match(Set dst (LoadL_unaligned mem));
5789 effect(KILL tmp);
5790 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5791 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5792 "\tLDUW $mem ,$dst\n"
5793 "\tSLLX #32, $dst, $dst\n"
5794 "\tOR $dst, R_O7, $dst" %}
5795 opcode(Assembler::lduw_op3);
5796 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5797 ins_pipe(iload_mem);
5798 %}
5799
5800 // Load Range
5801 instruct loadRange(iRegI dst, memory mem) %{
5802 match(Set dst (LoadRange mem));
5803 ins_cost(MEMORY_REF_COST);
5804
5805 format %{ "LDUW $mem,$dst\t! range" %}
5806 opcode(Assembler::lduw_op3);
5807 ins_encode(simple_form3_mem_reg( mem, dst ) );
5808 ins_pipe(iload_mem);
5809 %}
5810
5811 // Load Integer into %f register (for fitos/fitod)
5812 instruct loadI_freg(regF dst, memory mem) %{
5813 match(Set dst (LoadI mem));
5814 ins_cost(MEMORY_REF_COST);
5815
5816 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5817 opcode(Assembler::ldf_op3);
5818 ins_encode(simple_form3_mem_reg( mem, dst ) );
5819 ins_pipe(floadF_mem);
5820 %}
5821
5822 // Load Pointer
5823 instruct loadP(iRegP dst, memory mem) %{
5824 match(Set dst (LoadP mem));
5825 ins_cost(MEMORY_REF_COST);
5826 size(4);
5827
5828 #ifndef _LP64
5829 format %{ "LDUW $mem,$dst\t! ptr" %}
5830 ins_encode %{
5831 __ lduw($mem$$Address, $dst$$Register);
5832 %}
5833 #else
5834 format %{ "LDX $mem,$dst\t! ptr" %}
5835 ins_encode %{
5836 __ ldx($mem$$Address, $dst$$Register);
5837 %}
5838 #endif
5839 ins_pipe(iload_mem);
5840 %}
5841
5842 // Load Compressed Pointer
5843 instruct loadN(iRegN dst, memory mem) %{
5844 match(Set dst (LoadN mem));
5845 ins_cost(MEMORY_REF_COST);
5846 size(4);
5847
5848 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5849 ins_encode %{
5850 __ lduw($mem$$Address, $dst$$Register);
5851 %}
5852 ins_pipe(iload_mem);
5853 %}
5854
5855 // Load Klass Pointer
5856 instruct loadKlass(iRegP dst, memory mem) %{
5857 match(Set dst (LoadKlass mem));
5858 ins_cost(MEMORY_REF_COST);
5859 size(4);
5860
5861 #ifndef _LP64
5862 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5863 ins_encode %{
5864 __ lduw($mem$$Address, $dst$$Register);
5865 %}
5866 #else
5867 format %{ "LDX $mem,$dst\t! klass ptr" %}
5868 ins_encode %{
5869 __ ldx($mem$$Address, $dst$$Register);
5870 %}
5871 #endif
5872 ins_pipe(iload_mem);
5873 %}
5874
5875 // Load narrow Klass Pointer
5876 instruct loadNKlass(iRegN dst, memory mem) %{
5877 match(Set dst (LoadNKlass mem));
5878 ins_cost(MEMORY_REF_COST);
5879 size(4);
5880
5881 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5882 ins_encode %{
5883 __ lduw($mem$$Address, $dst$$Register);
5884 %}
5885 ins_pipe(iload_mem);
5886 %}
5887
5888 // Load Double
5889 instruct loadD(regD dst, memory mem) %{
5890 match(Set dst (LoadD mem));
5891 ins_cost(MEMORY_REF_COST);
5892
5893 format %{ "LDDF $mem,$dst" %}
5894 opcode(Assembler::lddf_op3);
5895 ins_encode(simple_form3_mem_reg( mem, dst ) );
5896 ins_pipe(floadD_mem);
5897 %}
5898
5899 // Load Double - UNaligned
5900 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5901 match(Set dst (LoadD_unaligned mem));
5902 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5903 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5904 "\tLDF $mem+4,$dst.lo\t!" %}
5905 opcode(Assembler::ldf_op3);
5906 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5907 ins_pipe(iload_mem);
5908 %}
5909
5910 // Load Float
5911 instruct loadF(regF dst, memory mem) %{
5912 match(Set dst (LoadF mem));
5913 ins_cost(MEMORY_REF_COST);
5914
5915 format %{ "LDF $mem,$dst" %}
5916 opcode(Assembler::ldf_op3);
5917 ins_encode(simple_form3_mem_reg( mem, dst ) );
5918 ins_pipe(floadF_mem);
5919 %}
5920
5921 // Load Constant
5922 instruct loadConI( iRegI dst, immI src ) %{
5923 match(Set dst src);
5924 ins_cost(DEFAULT_COST * 3/2);
5925 format %{ "SET $src,$dst" %}
5926 ins_encode( Set32(src, dst) );
5927 ins_pipe(ialu_hi_lo_reg);
5928 %}
5929
5930 instruct loadConI13( iRegI dst, immI13 src ) %{
5931 match(Set dst src);
5932
5933 size(4);
5934 format %{ "MOV $src,$dst" %}
5935 ins_encode( Set13( src, dst ) );
5936 ins_pipe(ialu_imm);
5937 %}
5938
5939 #ifndef _LP64
5940 instruct loadConP(iRegP dst, immP con) %{
5941 match(Set dst con);
5942 ins_cost(DEFAULT_COST * 3/2);
5943 format %{ "SET $con,$dst\t!ptr" %}
5944 ins_encode %{
5945 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5946 intptr_t val = $con$$constant;
5947 if (constant_reloc == relocInfo::oop_type) {
5948 __ set_oop_constant((jobject) val, $dst$$Register);
5949 } else if (constant_reloc == relocInfo::metadata_type) {
5950 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5951 } else { // non-oop pointers, e.g. card mark base, heap top
5952 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5953 __ set(val, $dst$$Register);
5954 }
5955 %}
5956 ins_pipe(loadConP);
5957 %}
5958 #else
5959 instruct loadConP_set(iRegP dst, immP_set con) %{
5960 match(Set dst con);
5961 ins_cost(DEFAULT_COST * 3/2);
5962 format %{ "SET $con,$dst\t! ptr" %}
5963 ins_encode %{
5964 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5965 intptr_t val = $con$$constant;
5966 if (constant_reloc == relocInfo::oop_type) {
5967 __ set_oop_constant((jobject) val, $dst$$Register);
5968 } else if (constant_reloc == relocInfo::metadata_type) {
5969 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5970 } else { // non-oop pointers, e.g. card mark base, heap top
5971 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5972 __ set(val, $dst$$Register);
5973 }
5974 %}
5975 ins_pipe(loadConP);
5976 %}
5977
5978 instruct loadConP_load(iRegP dst, immP_load con) %{
5979 match(Set dst con);
5980 ins_cost(MEMORY_REF_COST);
5981 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5982 ins_encode %{
5983 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5984 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5985 %}
5986 ins_pipe(loadConP);
5987 %}
5988
5989 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5990 match(Set dst con);
5991 ins_cost(DEFAULT_COST * 3/2);
5992 format %{ "SET $con,$dst\t! non-oop ptr" %}
5993 ins_encode %{
5994 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5995 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5996 } else {
5997 __ set($con$$constant, $dst$$Register);
5998 }
5999 %}
6000 ins_pipe(loadConP);
6001 %}
6002 #endif // _LP64
6003
6004 instruct loadConP0(iRegP dst, immP0 src) %{
6005 match(Set dst src);
6006
6007 size(4);
6008 format %{ "CLR $dst\t!ptr" %}
6009 ins_encode %{
6010 __ clr($dst$$Register);
6011 %}
6012 ins_pipe(ialu_imm);
6013 %}
6014
6015 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6016 match(Set dst src);
6017 ins_cost(DEFAULT_COST);
6018 format %{ "SET $src,$dst\t!ptr" %}
6019 ins_encode %{
6020 AddressLiteral polling_page(os::get_polling_page());
6021 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6022 %}
6023 ins_pipe(loadConP_poll);
6024 %}
6025
6026 instruct loadConN0(iRegN dst, immN0 src) %{
6027 match(Set dst src);
6028
6029 size(4);
6030 format %{ "CLR $dst\t! compressed NULL ptr" %}
6031 ins_encode %{
6032 __ clr($dst$$Register);
6033 %}
6034 ins_pipe(ialu_imm);
6035 %}
6036
6037 instruct loadConN(iRegN dst, immN src) %{
6038 match(Set dst src);
6039 ins_cost(DEFAULT_COST * 3/2);
6040 format %{ "SET $src,$dst\t! compressed ptr" %}
6041 ins_encode %{
6042 Register dst = $dst$$Register;
6043 __ set_narrow_oop((jobject)$src$$constant, dst);
6044 %}
6045 ins_pipe(ialu_hi_lo_reg);
6046 %}
6047
6048 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6049 match(Set dst src);
6050 ins_cost(DEFAULT_COST * 3/2);
6051 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6052 ins_encode %{
6053 Register dst = $dst$$Register;
6054 __ set_narrow_klass((Klass*)$src$$constant, dst);
6055 %}
6056 ins_pipe(ialu_hi_lo_reg);
6057 %}
6058
6059 // Materialize long value (predicated by immL_cheap).
6060 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6061 match(Set dst con);
6062 effect(KILL tmp);
6063 ins_cost(DEFAULT_COST * 3);
6064 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6065 ins_encode %{
6066 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6067 %}
6068 ins_pipe(loadConL);
6069 %}
6070
6071 // Load long value from constant table (predicated by immL_expensive).
6072 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6073 match(Set dst con);
6074 ins_cost(MEMORY_REF_COST);
6075 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6076 ins_encode %{
6077 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6078 __ ldx($constanttablebase, con_offset, $dst$$Register);
6079 %}
6080 ins_pipe(loadConL);
6081 %}
6082
6083 instruct loadConL0( iRegL dst, immL0 src ) %{
6084 match(Set dst src);
6085 ins_cost(DEFAULT_COST);
6086 size(4);
6087 format %{ "CLR $dst\t! long" %}
6088 ins_encode( Set13( src, dst ) );
6089 ins_pipe(ialu_imm);
6090 %}
6091
6092 instruct loadConL13( iRegL dst, immL13 src ) %{
6093 match(Set dst src);
6094 ins_cost(DEFAULT_COST * 2);
6095
6096 size(4);
6097 format %{ "MOV $src,$dst\t! long" %}
6098 ins_encode( Set13( src, dst ) );
6099 ins_pipe(ialu_imm);
6100 %}
6101
6102 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6103 match(Set dst con);
6104 effect(KILL tmp);
6105 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6106 ins_encode %{
6107 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6108 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6109 %}
6110 ins_pipe(loadConFD);
6111 %}
6112
6113 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6114 match(Set dst con);
6115 effect(KILL tmp);
6116 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6117 ins_encode %{
6118 // XXX This is a quick fix for 6833573.
6119 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6120 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6121 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6122 %}
6123 ins_pipe(loadConFD);
6124 %}
6125
6126 // Prefetch instructions for allocation.
6127 // Must be safe to execute with invalid address (cannot fault).
6128
6129 instruct prefetchAlloc( memory mem ) %{
6130 predicate(AllocatePrefetchInstr == 0);
6131 match( PrefetchAllocation mem );
6132 ins_cost(MEMORY_REF_COST);
6133
6134 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6135 opcode(Assembler::prefetch_op3);
6136 ins_encode( form3_mem_prefetch_write( mem ) );
6137 ins_pipe(iload_mem);
6138 %}
6139
6140 // Use BIS instruction to prefetch for allocation.
6141 // Could fault, need space at the end of TLAB.
6142 instruct prefetchAlloc_bis( iRegP dst ) %{
6143 predicate(AllocatePrefetchInstr == 1);
6144 match( PrefetchAllocation dst );
6145 ins_cost(MEMORY_REF_COST);
6146 size(4);
6147
6148 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6149 ins_encode %{
6150 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6151 %}
6152 ins_pipe(istore_mem_reg);
6153 %}
6154
6155 // Next code is used for finding next cache line address to prefetch.
6156 #ifndef _LP64
6157 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6158 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6159 ins_cost(DEFAULT_COST);
6160 size(4);
6161
6162 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6163 ins_encode %{
6164 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6165 %}
6166 ins_pipe(ialu_reg_imm);
6167 %}
6168 #else
6169 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6170 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6171 ins_cost(DEFAULT_COST);
6172 size(4);
6173
6174 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6175 ins_encode %{
6176 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6177 %}
6178 ins_pipe(ialu_reg_imm);
6179 %}
6180 #endif
6181
6182 //----------Store Instructions-------------------------------------------------
6183 // Store Byte
6184 instruct storeB(memory mem, iRegI src) %{
6185 match(Set mem (StoreB mem src));
6186 ins_cost(MEMORY_REF_COST);
6187
6188 format %{ "STB $src,$mem\t! byte" %}
6189 opcode(Assembler::stb_op3);
6190 ins_encode(simple_form3_mem_reg( mem, src ) );
6191 ins_pipe(istore_mem_reg);
6192 %}
6193
6194 instruct storeB0(memory mem, immI0 src) %{
6195 match(Set mem (StoreB mem src));
6196 ins_cost(MEMORY_REF_COST);
6197
6198 format %{ "STB $src,$mem\t! byte" %}
6199 opcode(Assembler::stb_op3);
6200 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6201 ins_pipe(istore_mem_zero);
6202 %}
6203
6204 instruct storeCM0(memory mem, immI0 src) %{
6205 match(Set mem (StoreCM mem src));
6206 ins_cost(MEMORY_REF_COST);
6207
6208 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6209 opcode(Assembler::stb_op3);
6210 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6211 ins_pipe(istore_mem_zero);
6212 %}
6213
6214 // Store Char/Short
6215 instruct storeC(memory mem, iRegI src) %{
6216 match(Set mem (StoreC mem src));
6217 ins_cost(MEMORY_REF_COST);
6218
6219 format %{ "STH $src,$mem\t! short" %}
6220 opcode(Assembler::sth_op3);
6221 ins_encode(simple_form3_mem_reg( mem, src ) );
6222 ins_pipe(istore_mem_reg);
6223 %}
6224
6225 instruct storeC0(memory mem, immI0 src) %{
6226 match(Set mem (StoreC mem src));
6227 ins_cost(MEMORY_REF_COST);
6228
6229 format %{ "STH $src,$mem\t! short" %}
6230 opcode(Assembler::sth_op3);
6231 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6232 ins_pipe(istore_mem_zero);
6233 %}
6234
6235 // Store Integer
6236 instruct storeI(memory mem, iRegI src) %{
6237 match(Set mem (StoreI mem src));
6238 ins_cost(MEMORY_REF_COST);
6239
6240 format %{ "STW $src,$mem" %}
6241 opcode(Assembler::stw_op3);
6242 ins_encode(simple_form3_mem_reg( mem, src ) );
6243 ins_pipe(istore_mem_reg);
6244 %}
6245
6246 // Store Long
6247 instruct storeL(memory mem, iRegL src) %{
6248 match(Set mem (StoreL mem src));
6249 ins_cost(MEMORY_REF_COST);
6250 format %{ "STX $src,$mem\t! long" %}
6251 opcode(Assembler::stx_op3);
6252 ins_encode(simple_form3_mem_reg( mem, src ) );
6253 ins_pipe(istore_mem_reg);
6254 %}
6255
6256 instruct storeI0(memory mem, immI0 src) %{
6257 match(Set mem (StoreI mem src));
6258 ins_cost(MEMORY_REF_COST);
6259
6260 format %{ "STW $src,$mem" %}
6261 opcode(Assembler::stw_op3);
6262 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6263 ins_pipe(istore_mem_zero);
6264 %}
6265
6266 instruct storeL0(memory mem, immL0 src) %{
6267 match(Set mem (StoreL mem src));
6268 ins_cost(MEMORY_REF_COST);
6269
6270 format %{ "STX $src,$mem" %}
6271 opcode(Assembler::stx_op3);
6272 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6273 ins_pipe(istore_mem_zero);
6274 %}
6275
6276 // Store Integer from float register (used after fstoi)
6277 instruct storeI_Freg(memory mem, regF src) %{
6278 match(Set mem (StoreI mem src));
6279 ins_cost(MEMORY_REF_COST);
6280
6281 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6282 opcode(Assembler::stf_op3);
6283 ins_encode(simple_form3_mem_reg( mem, src ) );
6284 ins_pipe(fstoreF_mem_reg);
6285 %}
6286
6287 // Store Pointer
6288 instruct storeP(memory dst, sp_ptr_RegP src) %{
6289 match(Set dst (StoreP dst src));
6290 ins_cost(MEMORY_REF_COST);
6291
6292 #ifndef _LP64
6293 format %{ "STW $src,$dst\t! ptr" %}
6294 opcode(Assembler::stw_op3, 0, REGP_OP);
6295 #else
6296 format %{ "STX $src,$dst\t! ptr" %}
6297 opcode(Assembler::stx_op3, 0, REGP_OP);
6298 #endif
6299 ins_encode( form3_mem_reg( dst, src ) );
6300 ins_pipe(istore_mem_spORreg);
6301 %}
6302
6303 instruct storeP0(memory dst, immP0 src) %{
6304 match(Set dst (StoreP dst src));
6305 ins_cost(MEMORY_REF_COST);
6306
6307 #ifndef _LP64
6308 format %{ "STW $src,$dst\t! ptr" %}
6309 opcode(Assembler::stw_op3, 0, REGP_OP);
6310 #else
6311 format %{ "STX $src,$dst\t! ptr" %}
6312 opcode(Assembler::stx_op3, 0, REGP_OP);
6313 #endif
6314 ins_encode( form3_mem_reg( dst, R_G0 ) );
6315 ins_pipe(istore_mem_zero);
6316 %}
6317
6318 // Store Compressed Pointer
6319 instruct storeN(memory dst, iRegN src) %{
6320 match(Set dst (StoreN dst src));
6321 ins_cost(MEMORY_REF_COST);
6322 size(4);
6323
6324 format %{ "STW $src,$dst\t! compressed ptr" %}
6325 ins_encode %{
6326 Register base = as_Register($dst$$base);
6327 Register index = as_Register($dst$$index);
6328 Register src = $src$$Register;
6329 if (index != G0) {
6330 __ stw(src, base, index);
6331 } else {
6332 __ stw(src, base, $dst$$disp);
6333 }
6334 %}
6335 ins_pipe(istore_mem_spORreg);
6336 %}
6337
6338 instruct storeNKlass(memory dst, iRegN src) %{
6339 match(Set dst (StoreNKlass dst src));
6340 ins_cost(MEMORY_REF_COST);
6341 size(4);
6342
6343 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6344 ins_encode %{
6345 Register base = as_Register($dst$$base);
6346 Register index = as_Register($dst$$index);
6347 Register src = $src$$Register;
6348 if (index != G0) {
6349 __ stw(src, base, index);
6350 } else {
6351 __ stw(src, base, $dst$$disp);
6352 }
6353 %}
6354 ins_pipe(istore_mem_spORreg);
6355 %}
6356
6357 instruct storeN0(memory dst, immN0 src) %{
6358 match(Set dst (StoreN dst src));
6359 ins_cost(MEMORY_REF_COST);
6360 size(4);
6361
6362 format %{ "STW $src,$dst\t! compressed ptr" %}
6363 ins_encode %{
6364 Register base = as_Register($dst$$base);
6365 Register index = as_Register($dst$$index);
6366 if (index != G0) {
6367 __ stw(0, base, index);
6368 } else {
6369 __ stw(0, base, $dst$$disp);
6370 }
6371 %}
6372 ins_pipe(istore_mem_zero);
6373 %}
6374
6375 // Store Double
6376 instruct storeD( memory mem, regD src) %{
6377 match(Set mem (StoreD mem src));
6378 ins_cost(MEMORY_REF_COST);
6379
6380 format %{ "STDF $src,$mem" %}
6381 opcode(Assembler::stdf_op3);
6382 ins_encode(simple_form3_mem_reg( mem, src ) );
6383 ins_pipe(fstoreD_mem_reg);
6384 %}
6385
6386 instruct storeD0( memory mem, immD0 src) %{
6387 match(Set mem (StoreD mem src));
6388 ins_cost(MEMORY_REF_COST);
6389
6390 format %{ "STX $src,$mem" %}
6391 opcode(Assembler::stx_op3);
6392 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6393 ins_pipe(fstoreD_mem_zero);
6394 %}
6395
6396 // Store Float
6397 instruct storeF( memory mem, regF src) %{
6398 match(Set mem (StoreF mem src));
6399 ins_cost(MEMORY_REF_COST);
6400
6401 format %{ "STF $src,$mem" %}
6402 opcode(Assembler::stf_op3);
6403 ins_encode(simple_form3_mem_reg( mem, src ) );
6404 ins_pipe(fstoreF_mem_reg);
6405 %}
6406
6407 instruct storeF0( memory mem, immF0 src) %{
6408 match(Set mem (StoreF mem src));
6409 ins_cost(MEMORY_REF_COST);
6410
6411 format %{ "STW $src,$mem\t! storeF0" %}
6412 opcode(Assembler::stw_op3);
6413 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6414 ins_pipe(fstoreF_mem_zero);
6415 %}
6416
6417 // Convert oop pointer into compressed form
6418 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6419 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6420 match(Set dst (EncodeP src));
6421 format %{ "encode_heap_oop $src, $dst" %}
6422 ins_encode %{
6423 __ encode_heap_oop($src$$Register, $dst$$Register);
6424 %}
6425 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6426 ins_pipe(ialu_reg);
6427 %}
6428
6429 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6430 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6431 match(Set dst (EncodeP src));
6432 format %{ "encode_heap_oop_not_null $src, $dst" %}
6433 ins_encode %{
6434 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6435 %}
6436 ins_pipe(ialu_reg);
6437 %}
6438
6439 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6440 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6441 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6442 match(Set dst (DecodeN src));
6443 format %{ "decode_heap_oop $src, $dst" %}
6444 ins_encode %{
6445 __ decode_heap_oop($src$$Register, $dst$$Register);
6446 %}
6447 ins_pipe(ialu_reg);
6448 %}
6449
6450 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6451 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6452 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6453 match(Set dst (DecodeN src));
6454 format %{ "decode_heap_oop_not_null $src, $dst" %}
6455 ins_encode %{
6456 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6457 %}
6458 ins_pipe(ialu_reg);
6459 %}
6460
6461 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6462 match(Set dst (EncodePKlass src));
6463 format %{ "encode_klass_not_null $src, $dst" %}
6464 ins_encode %{
6465 __ encode_klass_not_null($src$$Register, $dst$$Register);
6466 %}
6467 ins_pipe(ialu_reg);
6468 %}
6469
6470 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6471 match(Set dst (DecodeNKlass src));
6472 format %{ "decode_klass_not_null $src, $dst" %}
6473 ins_encode %{
6474 __ decode_klass_not_null($src$$Register, $dst$$Register);
6475 %}
6476 ins_pipe(ialu_reg);
6477 %}
6478
6479 //----------MemBar Instructions-----------------------------------------------
6480 // Memory barrier flavors
6481
6482 instruct membar_acquire() %{
6483 match(MemBarAcquire);
6484 match(LoadFence);
6485 ins_cost(4*MEMORY_REF_COST);
6486
6487 size(0);
6488 format %{ "MEMBAR-acquire" %}
6489 ins_encode( enc_membar_acquire );
6490 ins_pipe(long_memory_op);
6491 %}
6492
6493 instruct membar_acquire_lock() %{
6494 match(MemBarAcquireLock);
6495 ins_cost(0);
6496
6497 size(0);
6498 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6499 ins_encode( );
6500 ins_pipe(empty);
6501 %}
6502
6503 instruct membar_release() %{
6504 match(MemBarRelease);
6505 match(StoreFence);
6506 ins_cost(4*MEMORY_REF_COST);
6507
6508 size(0);
6509 format %{ "MEMBAR-release" %}
6510 ins_encode( enc_membar_release );
6511 ins_pipe(long_memory_op);
6512 %}
6513
6514 instruct membar_release_lock() %{
6515 match(MemBarReleaseLock);
6516 ins_cost(0);
6517
6518 size(0);
6519 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6520 ins_encode( );
6521 ins_pipe(empty);
6522 %}
6523
6524 instruct membar_volatile() %{
6525 match(MemBarVolatile);
6526 ins_cost(4*MEMORY_REF_COST);
6527
6528 size(4);
6529 format %{ "MEMBAR-volatile" %}
6530 ins_encode( enc_membar_volatile );
6531 ins_pipe(long_memory_op);
6532 %}
6533
6534 instruct unnecessary_membar_volatile() %{
6535 match(MemBarVolatile);
6536 predicate(Matcher::post_store_load_barrier(n));
6537 ins_cost(0);
6538
6539 size(0);
6540 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6541 ins_encode( );
6542 ins_pipe(empty);
6543 %}
6544
6545 instruct membar_storestore() %{
6546 match(MemBarStoreStore);
6547 ins_cost(0);
6548
6549 size(0);
6550 format %{ "!MEMBAR-storestore (empty encoding)" %}
6551 ins_encode( );
6552 ins_pipe(empty);
6553 %}
6554
6555 //----------Register Move Instructions-----------------------------------------
6556 instruct roundDouble_nop(regD dst) %{
6557 match(Set dst (RoundDouble dst));
6558 ins_cost(0);
6559 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6560 ins_encode( );
6561 ins_pipe(empty);
6562 %}
6563
6564
6565 instruct roundFloat_nop(regF dst) %{
6566 match(Set dst (RoundFloat dst));
6567 ins_cost(0);
6568 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6569 ins_encode( );
6570 ins_pipe(empty);
6571 %}
6572
6573
6574 // Cast Index to Pointer for unsafe natives
6575 instruct castX2P(iRegX src, iRegP dst) %{
6576 match(Set dst (CastX2P src));
6577
6578 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6579 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6580 ins_pipe(ialu_reg);
6581 %}
6582
6583 // Cast Pointer to Index for unsafe natives
6584 instruct castP2X(iRegP src, iRegX dst) %{
6585 match(Set dst (CastP2X src));
6586
6587 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6588 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6589 ins_pipe(ialu_reg);
6590 %}
6591
6592 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6593 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6594 match(Set stkSlot src); // chain rule
6595 ins_cost(MEMORY_REF_COST);
6596 format %{ "STDF $src,$stkSlot\t!stk" %}
6597 opcode(Assembler::stdf_op3);
6598 ins_encode(simple_form3_mem_reg(stkSlot, src));
6599 ins_pipe(fstoreD_stk_reg);
6600 %}
6601
6602 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6603 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6604 match(Set dst stkSlot); // chain rule
6605 ins_cost(MEMORY_REF_COST);
6606 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6607 opcode(Assembler::lddf_op3);
6608 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6609 ins_pipe(floadD_stk);
6610 %}
6611
6612 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6613 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6614 match(Set stkSlot src); // chain rule
6615 ins_cost(MEMORY_REF_COST);
6616 format %{ "STF $src,$stkSlot\t!stk" %}
6617 opcode(Assembler::stf_op3);
6618 ins_encode(simple_form3_mem_reg(stkSlot, src));
6619 ins_pipe(fstoreF_stk_reg);
6620 %}
6621
6622 //----------Conditional Move---------------------------------------------------
6623 // Conditional move
6624 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6625 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6626 ins_cost(150);
6627 format %{ "MOV$cmp $pcc,$src,$dst" %}
6628 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6629 ins_pipe(ialu_reg);
6630 %}
6631
6632 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6633 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6634 ins_cost(140);
6635 format %{ "MOV$cmp $pcc,$src,$dst" %}
6636 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6637 ins_pipe(ialu_imm);
6638 %}
6639
6640 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6641 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6642 ins_cost(150);
6643 size(4);
6644 format %{ "MOV$cmp $icc,$src,$dst" %}
6645 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6646 ins_pipe(ialu_reg);
6647 %}
6648
6649 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6650 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6651 ins_cost(140);
6652 size(4);
6653 format %{ "MOV$cmp $icc,$src,$dst" %}
6654 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6655 ins_pipe(ialu_imm);
6656 %}
6657
6658 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6659 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6660 ins_cost(150);
6661 size(4);
6662 format %{ "MOV$cmp $icc,$src,$dst" %}
6663 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6664 ins_pipe(ialu_reg);
6665 %}
6666
6667 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6668 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6669 ins_cost(140);
6670 size(4);
6671 format %{ "MOV$cmp $icc,$src,$dst" %}
6672 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6673 ins_pipe(ialu_imm);
6674 %}
6675
6676 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6677 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6678 ins_cost(150);
6679 size(4);
6680 format %{ "MOV$cmp $fcc,$src,$dst" %}
6681 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6682 ins_pipe(ialu_reg);
6683 %}
6684
6685 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6686 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6687 ins_cost(140);
6688 size(4);
6689 format %{ "MOV$cmp $fcc,$src,$dst" %}
6690 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6691 ins_pipe(ialu_imm);
6692 %}
6693
6694 // Conditional move for RegN. Only cmov(reg,reg).
6695 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6696 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6697 ins_cost(150);
6698 format %{ "MOV$cmp $pcc,$src,$dst" %}
6699 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6700 ins_pipe(ialu_reg);
6701 %}
6702
6703 // This instruction also works with CmpN so we don't need cmovNN_reg.
6704 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6705 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6706 ins_cost(150);
6707 size(4);
6708 format %{ "MOV$cmp $icc,$src,$dst" %}
6709 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6710 ins_pipe(ialu_reg);
6711 %}
6712
6713 // This instruction also works with CmpN so we don't need cmovNN_reg.
6714 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6715 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6716 ins_cost(150);
6717 size(4);
6718 format %{ "MOV$cmp $icc,$src,$dst" %}
6719 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6720 ins_pipe(ialu_reg);
6721 %}
6722
6723 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6724 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6725 ins_cost(150);
6726 size(4);
6727 format %{ "MOV$cmp $fcc,$src,$dst" %}
6728 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6729 ins_pipe(ialu_reg);
6730 %}
6731
6732 // Conditional move
6733 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6734 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6735 ins_cost(150);
6736 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6737 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6738 ins_pipe(ialu_reg);
6739 %}
6740
6741 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6742 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6743 ins_cost(140);
6744 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6745 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6746 ins_pipe(ialu_imm);
6747 %}
6748
6749 // This instruction also works with CmpN so we don't need cmovPN_reg.
6750 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6751 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6752 ins_cost(150);
6753
6754 size(4);
6755 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6756 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6757 ins_pipe(ialu_reg);
6758 %}
6759
6760 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6761 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6762 ins_cost(150);
6763
6764 size(4);
6765 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6766 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6767 ins_pipe(ialu_reg);
6768 %}
6769
6770 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6771 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6772 ins_cost(140);
6773
6774 size(4);
6775 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6776 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6777 ins_pipe(ialu_imm);
6778 %}
6779
6780 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6781 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6782 ins_cost(140);
6783
6784 size(4);
6785 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6786 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6787 ins_pipe(ialu_imm);
6788 %}
6789
6790 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6791 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6792 ins_cost(150);
6793 size(4);
6794 format %{ "MOV$cmp $fcc,$src,$dst" %}
6795 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6796 ins_pipe(ialu_imm);
6797 %}
6798
6799 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6800 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6801 ins_cost(140);
6802 size(4);
6803 format %{ "MOV$cmp $fcc,$src,$dst" %}
6804 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6805 ins_pipe(ialu_imm);
6806 %}
6807
6808 // Conditional move
6809 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6810 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6811 ins_cost(150);
6812 opcode(0x101);
6813 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6814 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6815 ins_pipe(int_conditional_float_move);
6816 %}
6817
6818 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6819 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6820 ins_cost(150);
6821
6822 size(4);
6823 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6824 opcode(0x101);
6825 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6826 ins_pipe(int_conditional_float_move);
6827 %}
6828
6829 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6830 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6831 ins_cost(150);
6832
6833 size(4);
6834 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6835 opcode(0x101);
6836 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6837 ins_pipe(int_conditional_float_move);
6838 %}
6839
6840 // Conditional move,
6841 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6842 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6843 ins_cost(150);
6844 size(4);
6845 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6846 opcode(0x1);
6847 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6848 ins_pipe(int_conditional_double_move);
6849 %}
6850
6851 // Conditional move
6852 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6853 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6854 ins_cost(150);
6855 size(4);
6856 opcode(0x102);
6857 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6858 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6859 ins_pipe(int_conditional_double_move);
6860 %}
6861
6862 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6863 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6864 ins_cost(150);
6865
6866 size(4);
6867 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6868 opcode(0x102);
6869 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6870 ins_pipe(int_conditional_double_move);
6871 %}
6872
6873 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6874 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6875 ins_cost(150);
6876
6877 size(4);
6878 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6879 opcode(0x102);
6880 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6881 ins_pipe(int_conditional_double_move);
6882 %}
6883
6884 // Conditional move,
6885 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6886 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6887 ins_cost(150);
6888 size(4);
6889 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6890 opcode(0x2);
6891 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6892 ins_pipe(int_conditional_double_move);
6893 %}
6894
6895 // Conditional move
6896 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6897 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6898 ins_cost(150);
6899 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6900 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6901 ins_pipe(ialu_reg);
6902 %}
6903
6904 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6905 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6906 ins_cost(140);
6907 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6908 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6909 ins_pipe(ialu_imm);
6910 %}
6911
6912 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6913 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6914 ins_cost(150);
6915
6916 size(4);
6917 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6918 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6919 ins_pipe(ialu_reg);
6920 %}
6921
6922
6923 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6924 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6925 ins_cost(150);
6926
6927 size(4);
6928 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6929 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6930 ins_pipe(ialu_reg);
6931 %}
6932
6933
6934 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6935 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6936 ins_cost(150);
6937
6938 size(4);
6939 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6940 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6941 ins_pipe(ialu_reg);
6942 %}
6943
6944
6945
6946 //----------OS and Locking Instructions----------------------------------------
6947
6948 // This name is KNOWN by the ADLC and cannot be changed.
6949 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6950 // for this guy.
6951 instruct tlsLoadP(g2RegP dst) %{
6952 match(Set dst (ThreadLocal));
6953
6954 size(0);
6955 ins_cost(0);
6956 format %{ "# TLS is in G2" %}
6957 ins_encode( /*empty encoding*/ );
6958 ins_pipe(ialu_none);
6959 %}
6960
6961 instruct checkCastPP( iRegP dst ) %{
6962 match(Set dst (CheckCastPP dst));
6963
6964 size(0);
6965 format %{ "# checkcastPP of $dst" %}
6966 ins_encode( /*empty encoding*/ );
6967 ins_pipe(empty);
6968 %}
6969
6970
6971 instruct castPP( iRegP dst ) %{
6972 match(Set dst (CastPP dst));
6973 format %{ "# castPP of $dst" %}
6974 ins_encode( /*empty encoding*/ );
6975 ins_pipe(empty);
6976 %}
6977
6978 instruct castII( iRegI dst ) %{
6979 match(Set dst (CastII dst));
6980 format %{ "# castII of $dst" %}
6981 ins_encode( /*empty encoding*/ );
6982 ins_cost(0);
6983 ins_pipe(empty);
6984 %}
6985
6986 //----------Arithmetic Instructions--------------------------------------------
6987 // Addition Instructions
6988 // Register Addition
6989 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6990 match(Set dst (AddI src1 src2));
6991
6992 size(4);
6993 format %{ "ADD $src1,$src2,$dst" %}
6994 ins_encode %{
6995 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6996 %}
6997 ins_pipe(ialu_reg_reg);
6998 %}
6999
7000 // Immediate Addition
7001 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7002 match(Set dst (AddI src1 src2));
7003
7004 size(4);
7005 format %{ "ADD $src1,$src2,$dst" %}
7006 opcode(Assembler::add_op3, Assembler::arith_op);
7007 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7008 ins_pipe(ialu_reg_imm);
7009 %}
7010
7011 // Pointer Register Addition
7012 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7013 match(Set dst (AddP src1 src2));
7014
7015 size(4);
7016 format %{ "ADD $src1,$src2,$dst" %}
7017 opcode(Assembler::add_op3, Assembler::arith_op);
7018 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7019 ins_pipe(ialu_reg_reg);
7020 %}
7021
7022 // Pointer Immediate Addition
7023 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7024 match(Set dst (AddP src1 src2));
7025
7026 size(4);
7027 format %{ "ADD $src1,$src2,$dst" %}
7028 opcode(Assembler::add_op3, Assembler::arith_op);
7029 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7030 ins_pipe(ialu_reg_imm);
7031 %}
7032
7033 // Long Addition
7034 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7035 match(Set dst (AddL src1 src2));
7036
7037 size(4);
7038 format %{ "ADD $src1,$src2,$dst\t! long" %}
7039 opcode(Assembler::add_op3, Assembler::arith_op);
7040 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7041 ins_pipe(ialu_reg_reg);
7042 %}
7043
7044 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7045 match(Set dst (AddL src1 con));
7046
7047 size(4);
7048 format %{ "ADD $src1,$con,$dst" %}
7049 opcode(Assembler::add_op3, Assembler::arith_op);
7050 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7051 ins_pipe(ialu_reg_imm);
7052 %}
7053
7054 //----------Conditional_store--------------------------------------------------
7055 // Conditional-store of the updated heap-top.
7056 // Used during allocation of the shared heap.
7057 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7058
7059 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7060 instruct loadPLocked(iRegP dst, memory mem) %{
7061 match(Set dst (LoadPLocked mem));
7062 ins_cost(MEMORY_REF_COST);
7063
7064 #ifndef _LP64
7065 format %{ "LDUW $mem,$dst\t! ptr" %}
7066 opcode(Assembler::lduw_op3, 0, REGP_OP);
7067 #else
7068 format %{ "LDX $mem,$dst\t! ptr" %}
7069 opcode(Assembler::ldx_op3, 0, REGP_OP);
7070 #endif
7071 ins_encode( form3_mem_reg( mem, dst ) );
7072 ins_pipe(iload_mem);
7073 %}
7074
7075 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7076 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7077 effect( KILL newval );
7078 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7079 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7080 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7081 ins_pipe( long_memory_op );
7082 %}
7083
7084 // Conditional-store of an int value.
7085 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7086 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7087 effect( KILL newval );
7088 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7089 "CMP $oldval,$newval\t\t! See if we made progress" %}
7090 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7091 ins_pipe( long_memory_op );
7092 %}
7093
7094 // Conditional-store of a long value.
7095 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7096 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7097 effect( KILL newval );
7098 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7099 "CMP $oldval,$newval\t\t! See if we made progress" %}
7100 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7101 ins_pipe( long_memory_op );
7102 %}
7103
7104 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7105
7106 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7107 predicate(VM_Version::supports_cx8());
7108 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7109 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7110 format %{
7111 "MOV $newval,O7\n\t"
7112 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7113 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7114 "MOV 1,$res\n\t"
7115 "MOVne xcc,R_G0,$res"
7116 %}
7117 ins_encode( enc_casx(mem_ptr, oldval, newval),
7118 enc_lflags_ne_to_boolean(res) );
7119 ins_pipe( long_memory_op );
7120 %}
7121
7122
7123 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7124 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7125 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7126 format %{
7127 "MOV $newval,O7\n\t"
7128 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7129 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7130 "MOV 1,$res\n\t"
7131 "MOVne icc,R_G0,$res"
7132 %}
7133 ins_encode( enc_casi(mem_ptr, oldval, newval),
7134 enc_iflags_ne_to_boolean(res) );
7135 ins_pipe( long_memory_op );
7136 %}
7137
7138 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7139 #ifdef _LP64
7140 predicate(VM_Version::supports_cx8());
7141 #endif
7142 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7143 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7144 format %{
7145 "MOV $newval,O7\n\t"
7146 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7147 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7148 "MOV 1,$res\n\t"
7149 "MOVne xcc,R_G0,$res"
7150 %}
7151 #ifdef _LP64
7152 ins_encode( enc_casx(mem_ptr, oldval, newval),
7153 enc_lflags_ne_to_boolean(res) );
7154 #else
7155 ins_encode( enc_casi(mem_ptr, oldval, newval),
7156 enc_iflags_ne_to_boolean(res) );
7157 #endif
7158 ins_pipe( long_memory_op );
7159 %}
7160
7161 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7162 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7163 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7164 format %{
7165 "MOV $newval,O7\n\t"
7166 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7167 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7168 "MOV 1,$res\n\t"
7169 "MOVne icc,R_G0,$res"
7170 %}
7171 ins_encode( enc_casi(mem_ptr, oldval, newval),
7172 enc_iflags_ne_to_boolean(res) );
7173 ins_pipe( long_memory_op );
7174 %}
7175
7176 instruct xchgI( memory mem, iRegI newval) %{
7177 match(Set newval (GetAndSetI mem newval));
7178 format %{ "SWAP [$mem],$newval" %}
7179 size(4);
7180 ins_encode %{
7181 __ swap($mem$$Address, $newval$$Register);
7182 %}
7183 ins_pipe( long_memory_op );
7184 %}
7185
7186 #ifndef _LP64
7187 instruct xchgP( memory mem, iRegP newval) %{
7188 match(Set newval (GetAndSetP mem newval));
7189 format %{ "SWAP [$mem],$newval" %}
7190 size(4);
7191 ins_encode %{
7192 __ swap($mem$$Address, $newval$$Register);
7193 %}
7194 ins_pipe( long_memory_op );
7195 %}
7196 #endif
7197
7198 instruct xchgN( memory mem, iRegN newval) %{
7199 match(Set newval (GetAndSetN mem newval));
7200 format %{ "SWAP [$mem],$newval" %}
7201 size(4);
7202 ins_encode %{
7203 __ swap($mem$$Address, $newval$$Register);
7204 %}
7205 ins_pipe( long_memory_op );
7206 %}
7207
7208 //---------------------
7209 // Subtraction Instructions
7210 // Register Subtraction
7211 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7212 match(Set dst (SubI src1 src2));
7213
7214 size(4);
7215 format %{ "SUB $src1,$src2,$dst" %}
7216 opcode(Assembler::sub_op3, Assembler::arith_op);
7217 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7218 ins_pipe(ialu_reg_reg);
7219 %}
7220
7221 // Immediate Subtraction
7222 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7223 match(Set dst (SubI src1 src2));
7224
7225 size(4);
7226 format %{ "SUB $src1,$src2,$dst" %}
7227 opcode(Assembler::sub_op3, Assembler::arith_op);
7228 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7229 ins_pipe(ialu_reg_imm);
7230 %}
7231
7232 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7233 match(Set dst (SubI zero src2));
7234
7235 size(4);
7236 format %{ "NEG $src2,$dst" %}
7237 opcode(Assembler::sub_op3, Assembler::arith_op);
7238 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7239 ins_pipe(ialu_zero_reg);
7240 %}
7241
7242 // Long subtraction
7243 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7244 match(Set dst (SubL src1 src2));
7245
7246 size(4);
7247 format %{ "SUB $src1,$src2,$dst\t! long" %}
7248 opcode(Assembler::sub_op3, Assembler::arith_op);
7249 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7250 ins_pipe(ialu_reg_reg);
7251 %}
7252
7253 // Immediate Subtraction
7254 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7255 match(Set dst (SubL src1 con));
7256
7257 size(4);
7258 format %{ "SUB $src1,$con,$dst\t! long" %}
7259 opcode(Assembler::sub_op3, Assembler::arith_op);
7260 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7261 ins_pipe(ialu_reg_imm);
7262 %}
7263
7264 // Long negation
7265 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7266 match(Set dst (SubL zero src2));
7267
7268 size(4);
7269 format %{ "NEG $src2,$dst\t! long" %}
7270 opcode(Assembler::sub_op3, Assembler::arith_op);
7271 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7272 ins_pipe(ialu_zero_reg);
7273 %}
7274
7275 // Multiplication Instructions
7276 // Integer Multiplication
7277 // Register Multiplication
7278 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7279 match(Set dst (MulI src1 src2));
7280
7281 size(4);
7282 format %{ "MULX $src1,$src2,$dst" %}
7283 opcode(Assembler::mulx_op3, Assembler::arith_op);
7284 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7285 ins_pipe(imul_reg_reg);
7286 %}
7287
7288 // Immediate Multiplication
7289 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7290 match(Set dst (MulI src1 src2));
7291
7292 size(4);
7293 format %{ "MULX $src1,$src2,$dst" %}
7294 opcode(Assembler::mulx_op3, Assembler::arith_op);
7295 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7296 ins_pipe(imul_reg_imm);
7297 %}
7298
7299 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7300 match(Set dst (MulL src1 src2));
7301 ins_cost(DEFAULT_COST * 5);
7302 size(4);
7303 format %{ "MULX $src1,$src2,$dst\t! long" %}
7304 opcode(Assembler::mulx_op3, Assembler::arith_op);
7305 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7306 ins_pipe(mulL_reg_reg);
7307 %}
7308
7309 // Immediate Multiplication
7310 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7311 match(Set dst (MulL src1 src2));
7312 ins_cost(DEFAULT_COST * 5);
7313 size(4);
7314 format %{ "MULX $src1,$src2,$dst" %}
7315 opcode(Assembler::mulx_op3, Assembler::arith_op);
7316 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7317 ins_pipe(mulL_reg_imm);
7318 %}
7319
7320 // Integer Division
7321 // Register Division
7322 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7323 match(Set dst (DivI src1 src2));
7324 ins_cost((2+71)*DEFAULT_COST);
7325
7326 format %{ "SRA $src2,0,$src2\n\t"
7327 "SRA $src1,0,$src1\n\t"
7328 "SDIVX $src1,$src2,$dst" %}
7329 ins_encode( idiv_reg( src1, src2, dst ) );
7330 ins_pipe(sdiv_reg_reg);
7331 %}
7332
7333 // Immediate Division
7334 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7335 match(Set dst (DivI src1 src2));
7336 ins_cost((2+71)*DEFAULT_COST);
7337
7338 format %{ "SRA $src1,0,$src1\n\t"
7339 "SDIVX $src1,$src2,$dst" %}
7340 ins_encode( idiv_imm( src1, src2, dst ) );
7341 ins_pipe(sdiv_reg_imm);
7342 %}
7343
7344 //----------Div-By-10-Expansion------------------------------------------------
7345 // Extract hi bits of a 32x32->64 bit multiply.
7346 // Expand rule only, not matched
7347 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7348 effect( DEF dst, USE src1, USE src2 );
7349 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7350 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7351 ins_encode( enc_mul_hi(dst,src1,src2));
7352 ins_pipe(sdiv_reg_reg);
7353 %}
7354
7355 // Magic constant, reciprocal of 10
7356 instruct loadConI_x66666667(iRegIsafe dst) %{
7357 effect( DEF dst );
7358
7359 size(8);
7360 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7361 ins_encode( Set32(0x66666667, dst) );
7362 ins_pipe(ialu_hi_lo_reg);
7363 %}
7364
7365 // Register Shift Right Arithmetic Long by 32-63
7366 instruct sra_31( iRegI dst, iRegI src ) %{
7367 effect( DEF dst, USE src );
7368 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7369 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7370 ins_pipe(ialu_reg_reg);
7371 %}
7372
7373 // Arithmetic Shift Right by 8-bit immediate
7374 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7375 effect( DEF dst, USE src );
7376 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7377 opcode(Assembler::sra_op3, Assembler::arith_op);
7378 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7379 ins_pipe(ialu_reg_imm);
7380 %}
7381
7382 // Integer DIV with 10
7383 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7384 match(Set dst (DivI src div));
7385 ins_cost((6+6)*DEFAULT_COST);
7386 expand %{
7387 iRegIsafe tmp1; // Killed temps;
7388 iRegIsafe tmp2; // Killed temps;
7389 iRegI tmp3; // Killed temps;
7390 iRegI tmp4; // Killed temps;
7391 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7392 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7393 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7394 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7395 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7396 %}
7397 %}
7398
7399 // Register Long Division
7400 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7401 match(Set dst (DivL src1 src2));
7402 ins_cost(DEFAULT_COST*71);
7403 size(4);
7404 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7405 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7406 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7407 ins_pipe(divL_reg_reg);
7408 %}
7409
7410 // Register Long Division
7411 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7412 match(Set dst (DivL src1 src2));
7413 ins_cost(DEFAULT_COST*71);
7414 size(4);
7415 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7416 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7417 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7418 ins_pipe(divL_reg_imm);
7419 %}
7420
7421 // Integer Remainder
7422 // Register Remainder
7423 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7424 match(Set dst (ModI src1 src2));
7425 effect( KILL ccr, KILL temp);
7426
7427 format %{ "SREM $src1,$src2,$dst" %}
7428 ins_encode( irem_reg(src1, src2, dst, temp) );
7429 ins_pipe(sdiv_reg_reg);
7430 %}
7431
7432 // Immediate Remainder
7433 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7434 match(Set dst (ModI src1 src2));
7435 effect( KILL ccr, KILL temp);
7436
7437 format %{ "SREM $src1,$src2,$dst" %}
7438 ins_encode( irem_imm(src1, src2, dst, temp) );
7439 ins_pipe(sdiv_reg_imm);
7440 %}
7441
7442 // Register Long Remainder
7443 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7444 effect(DEF dst, USE src1, USE src2);
7445 size(4);
7446 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7447 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7448 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7449 ins_pipe(divL_reg_reg);
7450 %}
7451
7452 // Register Long Division
7453 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7454 effect(DEF dst, USE src1, USE src2);
7455 size(4);
7456 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7457 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7458 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7459 ins_pipe(divL_reg_imm);
7460 %}
7461
7462 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7463 effect(DEF dst, USE src1, USE src2);
7464 size(4);
7465 format %{ "MULX $src1,$src2,$dst\t! long" %}
7466 opcode(Assembler::mulx_op3, Assembler::arith_op);
7467 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7468 ins_pipe(mulL_reg_reg);
7469 %}
7470
7471 // Immediate Multiplication
7472 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7473 effect(DEF dst, USE src1, USE src2);
7474 size(4);
7475 format %{ "MULX $src1,$src2,$dst" %}
7476 opcode(Assembler::mulx_op3, Assembler::arith_op);
7477 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7478 ins_pipe(mulL_reg_imm);
7479 %}
7480
7481 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7482 effect(DEF dst, USE src1, USE src2);
7483 size(4);
7484 format %{ "SUB $src1,$src2,$dst\t! long" %}
7485 opcode(Assembler::sub_op3, Assembler::arith_op);
7486 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7487 ins_pipe(ialu_reg_reg);
7488 %}
7489
7490 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7491 effect(DEF dst, USE src1, USE src2);
7492 size(4);
7493 format %{ "SUB $src1,$src2,$dst\t! long" %}
7494 opcode(Assembler::sub_op3, Assembler::arith_op);
7495 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7496 ins_pipe(ialu_reg_reg);
7497 %}
7498
7499 // Register Long Remainder
7500 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7501 match(Set dst (ModL src1 src2));
7502 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7503 expand %{
7504 iRegL tmp1;
7505 iRegL tmp2;
7506 divL_reg_reg_1(tmp1, src1, src2);
7507 mulL_reg_reg_1(tmp2, tmp1, src2);
7508 subL_reg_reg_1(dst, src1, tmp2);
7509 %}
7510 %}
7511
7512 // Register Long Remainder
7513 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7514 match(Set dst (ModL src1 src2));
7515 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7516 expand %{
7517 iRegL tmp1;
7518 iRegL tmp2;
7519 divL_reg_imm13_1(tmp1, src1, src2);
7520 mulL_reg_imm13_1(tmp2, tmp1, src2);
7521 subL_reg_reg_2 (dst, src1, tmp2);
7522 %}
7523 %}
7524
7525 // Integer Shift Instructions
7526 // Register Shift Left
7527 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7528 match(Set dst (LShiftI src1 src2));
7529
7530 size(4);
7531 format %{ "SLL $src1,$src2,$dst" %}
7532 opcode(Assembler::sll_op3, Assembler::arith_op);
7533 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7534 ins_pipe(ialu_reg_reg);
7535 %}
7536
7537 // Register Shift Left Immediate
7538 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7539 match(Set dst (LShiftI src1 src2));
7540
7541 size(4);
7542 format %{ "SLL $src1,$src2,$dst" %}
7543 opcode(Assembler::sll_op3, Assembler::arith_op);
7544 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7545 ins_pipe(ialu_reg_imm);
7546 %}
7547
7548 // Register Shift Left
7549 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7550 match(Set dst (LShiftL src1 src2));
7551
7552 size(4);
7553 format %{ "SLLX $src1,$src2,$dst" %}
7554 opcode(Assembler::sllx_op3, Assembler::arith_op);
7555 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7556 ins_pipe(ialu_reg_reg);
7557 %}
7558
7559 // Register Shift Left Immediate
7560 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7561 match(Set dst (LShiftL src1 src2));
7562
7563 size(4);
7564 format %{ "SLLX $src1,$src2,$dst" %}
7565 opcode(Assembler::sllx_op3, Assembler::arith_op);
7566 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7567 ins_pipe(ialu_reg_imm);
7568 %}
7569
7570 // Register Arithmetic Shift Right
7571 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7572 match(Set dst (RShiftI src1 src2));
7573 size(4);
7574 format %{ "SRA $src1,$src2,$dst" %}
7575 opcode(Assembler::sra_op3, Assembler::arith_op);
7576 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7577 ins_pipe(ialu_reg_reg);
7578 %}
7579
7580 // Register Arithmetic Shift Right Immediate
7581 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7582 match(Set dst (RShiftI src1 src2));
7583
7584 size(4);
7585 format %{ "SRA $src1,$src2,$dst" %}
7586 opcode(Assembler::sra_op3, Assembler::arith_op);
7587 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7588 ins_pipe(ialu_reg_imm);
7589 %}
7590
7591 // Register Shift Right Arithmatic Long
7592 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7593 match(Set dst (RShiftL src1 src2));
7594
7595 size(4);
7596 format %{ "SRAX $src1,$src2,$dst" %}
7597 opcode(Assembler::srax_op3, Assembler::arith_op);
7598 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7599 ins_pipe(ialu_reg_reg);
7600 %}
7601
7602 // Register Shift Left Immediate
7603 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7604 match(Set dst (RShiftL src1 src2));
7605
7606 size(4);
7607 format %{ "SRAX $src1,$src2,$dst" %}
7608 opcode(Assembler::srax_op3, Assembler::arith_op);
7609 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7610 ins_pipe(ialu_reg_imm);
7611 %}
7612
7613 // Register Shift Right
7614 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7615 match(Set dst (URShiftI src1 src2));
7616
7617 size(4);
7618 format %{ "SRL $src1,$src2,$dst" %}
7619 opcode(Assembler::srl_op3, Assembler::arith_op);
7620 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7621 ins_pipe(ialu_reg_reg);
7622 %}
7623
7624 // Register Shift Right Immediate
7625 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7626 match(Set dst (URShiftI src1 src2));
7627
7628 size(4);
7629 format %{ "SRL $src1,$src2,$dst" %}
7630 opcode(Assembler::srl_op3, Assembler::arith_op);
7631 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7632 ins_pipe(ialu_reg_imm);
7633 %}
7634
7635 // Register Shift Right
7636 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7637 match(Set dst (URShiftL src1 src2));
7638
7639 size(4);
7640 format %{ "SRLX $src1,$src2,$dst" %}
7641 opcode(Assembler::srlx_op3, Assembler::arith_op);
7642 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7643 ins_pipe(ialu_reg_reg);
7644 %}
7645
7646 // Register Shift Right Immediate
7647 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7648 match(Set dst (URShiftL src1 src2));
7649
7650 size(4);
7651 format %{ "SRLX $src1,$src2,$dst" %}
7652 opcode(Assembler::srlx_op3, Assembler::arith_op);
7653 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7654 ins_pipe(ialu_reg_imm);
7655 %}
7656
7657 // Register Shift Right Immediate with a CastP2X
7658 #ifdef _LP64
7659 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7660 match(Set dst (URShiftL (CastP2X src1) src2));
7661 size(4);
7662 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7663 opcode(Assembler::srlx_op3, Assembler::arith_op);
7664 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7665 ins_pipe(ialu_reg_imm);
7666 %}
7667 #else
7668 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7669 match(Set dst (URShiftI (CastP2X src1) src2));
7670 size(4);
7671 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7672 opcode(Assembler::srl_op3, Assembler::arith_op);
7673 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7674 ins_pipe(ialu_reg_imm);
7675 %}
7676 #endif
7677
7678
7679 //----------Floating Point Arithmetic Instructions-----------------------------
7680
7681 // Add float single precision
7682 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7683 match(Set dst (AddF src1 src2));
7684
7685 size(4);
7686 format %{ "FADDS $src1,$src2,$dst" %}
7687 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7688 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7689 ins_pipe(faddF_reg_reg);
7690 %}
7691
7692 // Add float double precision
7693 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7694 match(Set dst (AddD src1 src2));
7695
7696 size(4);
7697 format %{ "FADDD $src1,$src2,$dst" %}
7698 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7699 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7700 ins_pipe(faddD_reg_reg);
7701 %}
7702
7703 // Sub float single precision
7704 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7705 match(Set dst (SubF src1 src2));
7706
7707 size(4);
7708 format %{ "FSUBS $src1,$src2,$dst" %}
7709 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7710 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7711 ins_pipe(faddF_reg_reg);
7712 %}
7713
7714 // Sub float double precision
7715 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7716 match(Set dst (SubD src1 src2));
7717
7718 size(4);
7719 format %{ "FSUBD $src1,$src2,$dst" %}
7720 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7721 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7722 ins_pipe(faddD_reg_reg);
7723 %}
7724
7725 // Mul float single precision
7726 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7727 match(Set dst (MulF src1 src2));
7728
7729 size(4);
7730 format %{ "FMULS $src1,$src2,$dst" %}
7731 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7732 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7733 ins_pipe(fmulF_reg_reg);
7734 %}
7735
7736 // Mul float double precision
7737 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7738 match(Set dst (MulD src1 src2));
7739
7740 size(4);
7741 format %{ "FMULD $src1,$src2,$dst" %}
7742 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7743 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7744 ins_pipe(fmulD_reg_reg);
7745 %}
7746
7747 // Div float single precision
7748 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7749 match(Set dst (DivF src1 src2));
7750
7751 size(4);
7752 format %{ "FDIVS $src1,$src2,$dst" %}
7753 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7754 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7755 ins_pipe(fdivF_reg_reg);
7756 %}
7757
7758 // Div float double precision
7759 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7760 match(Set dst (DivD src1 src2));
7761
7762 size(4);
7763 format %{ "FDIVD $src1,$src2,$dst" %}
7764 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7765 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7766 ins_pipe(fdivD_reg_reg);
7767 %}
7768
7769 // Absolute float double precision
7770 instruct absD_reg(regD dst, regD src) %{
7771 match(Set dst (AbsD src));
7772
7773 format %{ "FABSd $src,$dst" %}
7774 ins_encode(fabsd(dst, src));
7775 ins_pipe(faddD_reg);
7776 %}
7777
7778 // Absolute float single precision
7779 instruct absF_reg(regF dst, regF src) %{
7780 match(Set dst (AbsF src));
7781
7782 format %{ "FABSs $src,$dst" %}
7783 ins_encode(fabss(dst, src));
7784 ins_pipe(faddF_reg);
7785 %}
7786
7787 instruct negF_reg(regF dst, regF src) %{
7788 match(Set dst (NegF src));
7789
7790 size(4);
7791 format %{ "FNEGs $src,$dst" %}
7792 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7793 ins_encode(form3_opf_rs2F_rdF(src, dst));
7794 ins_pipe(faddF_reg);
7795 %}
7796
7797 instruct negD_reg(regD dst, regD src) %{
7798 match(Set dst (NegD src));
7799
7800 format %{ "FNEGd $src,$dst" %}
7801 ins_encode(fnegd(dst, src));
7802 ins_pipe(faddD_reg);
7803 %}
7804
7805 // Sqrt float double precision
7806 instruct sqrtF_reg_reg(regF dst, regF src) %{
7807 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7808
7809 size(4);
7810 format %{ "FSQRTS $src,$dst" %}
7811 ins_encode(fsqrts(dst, src));
7812 ins_pipe(fdivF_reg_reg);
7813 %}
7814
7815 // Sqrt float double precision
7816 instruct sqrtD_reg_reg(regD dst, regD src) %{
7817 match(Set dst (SqrtD src));
7818
7819 size(4);
7820 format %{ "FSQRTD $src,$dst" %}
7821 ins_encode(fsqrtd(dst, src));
7822 ins_pipe(fdivD_reg_reg);
7823 %}
7824
7825 //----------Logical Instructions-----------------------------------------------
7826 // And Instructions
7827 // Register And
7828 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7829 match(Set dst (AndI src1 src2));
7830
7831 size(4);
7832 format %{ "AND $src1,$src2,$dst" %}
7833 opcode(Assembler::and_op3, Assembler::arith_op);
7834 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7835 ins_pipe(ialu_reg_reg);
7836 %}
7837
7838 // Immediate And
7839 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7840 match(Set dst (AndI src1 src2));
7841
7842 size(4);
7843 format %{ "AND $src1,$src2,$dst" %}
7844 opcode(Assembler::and_op3, Assembler::arith_op);
7845 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7846 ins_pipe(ialu_reg_imm);
7847 %}
7848
7849 // Register And Long
7850 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7851 match(Set dst (AndL src1 src2));
7852
7853 ins_cost(DEFAULT_COST);
7854 size(4);
7855 format %{ "AND $src1,$src2,$dst\t! long" %}
7856 opcode(Assembler::and_op3, Assembler::arith_op);
7857 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7858 ins_pipe(ialu_reg_reg);
7859 %}
7860
7861 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7862 match(Set dst (AndL src1 con));
7863
7864 ins_cost(DEFAULT_COST);
7865 size(4);
7866 format %{ "AND $src1,$con,$dst\t! long" %}
7867 opcode(Assembler::and_op3, Assembler::arith_op);
7868 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7869 ins_pipe(ialu_reg_imm);
7870 %}
7871
7872 // Or Instructions
7873 // Register Or
7874 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7875 match(Set dst (OrI src1 src2));
7876
7877 size(4);
7878 format %{ "OR $src1,$src2,$dst" %}
7879 opcode(Assembler::or_op3, Assembler::arith_op);
7880 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7881 ins_pipe(ialu_reg_reg);
7882 %}
7883
7884 // Immediate Or
7885 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7886 match(Set dst (OrI src1 src2));
7887
7888 size(4);
7889 format %{ "OR $src1,$src2,$dst" %}
7890 opcode(Assembler::or_op3, Assembler::arith_op);
7891 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7892 ins_pipe(ialu_reg_imm);
7893 %}
7894
7895 // Register Or Long
7896 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7897 match(Set dst (OrL src1 src2));
7898
7899 ins_cost(DEFAULT_COST);
7900 size(4);
7901 format %{ "OR $src1,$src2,$dst\t! long" %}
7902 opcode(Assembler::or_op3, Assembler::arith_op);
7903 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7904 ins_pipe(ialu_reg_reg);
7905 %}
7906
7907 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7908 match(Set dst (OrL src1 con));
7909 ins_cost(DEFAULT_COST*2);
7910
7911 ins_cost(DEFAULT_COST);
7912 size(4);
7913 format %{ "OR $src1,$con,$dst\t! long" %}
7914 opcode(Assembler::or_op3, Assembler::arith_op);
7915 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7916 ins_pipe(ialu_reg_imm);
7917 %}
7918
7919 #ifndef _LP64
7920
7921 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7922 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7923 match(Set dst (OrI src1 (CastP2X src2)));
7924
7925 size(4);
7926 format %{ "OR $src1,$src2,$dst" %}
7927 opcode(Assembler::or_op3, Assembler::arith_op);
7928 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7929 ins_pipe(ialu_reg_reg);
7930 %}
7931
7932 #else
7933
7934 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7935 match(Set dst (OrL src1 (CastP2X src2)));
7936
7937 ins_cost(DEFAULT_COST);
7938 size(4);
7939 format %{ "OR $src1,$src2,$dst\t! long" %}
7940 opcode(Assembler::or_op3, Assembler::arith_op);
7941 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7942 ins_pipe(ialu_reg_reg);
7943 %}
7944
7945 #endif
7946
7947 // Xor Instructions
7948 // Register Xor
7949 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7950 match(Set dst (XorI src1 src2));
7951
7952 size(4);
7953 format %{ "XOR $src1,$src2,$dst" %}
7954 opcode(Assembler::xor_op3, Assembler::arith_op);
7955 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7956 ins_pipe(ialu_reg_reg);
7957 %}
7958
7959 // Immediate Xor
7960 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7961 match(Set dst (XorI src1 src2));
7962
7963 size(4);
7964 format %{ "XOR $src1,$src2,$dst" %}
7965 opcode(Assembler::xor_op3, Assembler::arith_op);
7966 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7967 ins_pipe(ialu_reg_imm);
7968 %}
7969
7970 // Register Xor Long
7971 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7972 match(Set dst (XorL src1 src2));
7973
7974 ins_cost(DEFAULT_COST);
7975 size(4);
7976 format %{ "XOR $src1,$src2,$dst\t! long" %}
7977 opcode(Assembler::xor_op3, Assembler::arith_op);
7978 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7979 ins_pipe(ialu_reg_reg);
7980 %}
7981
7982 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7983 match(Set dst (XorL src1 con));
7984
7985 ins_cost(DEFAULT_COST);
7986 size(4);
7987 format %{ "XOR $src1,$con,$dst\t! long" %}
7988 opcode(Assembler::xor_op3, Assembler::arith_op);
7989 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7990 ins_pipe(ialu_reg_imm);
7991 %}
7992
7993 //----------Convert to Boolean-------------------------------------------------
7994 // Nice hack for 32-bit tests but doesn't work for
7995 // 64-bit pointers.
7996 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7997 match(Set dst (Conv2B src));
7998 effect( KILL ccr );
7999 ins_cost(DEFAULT_COST*2);
8000 format %{ "CMP R_G0,$src\n\t"
8001 "ADDX R_G0,0,$dst" %}
8002 ins_encode( enc_to_bool( src, dst ) );
8003 ins_pipe(ialu_reg_ialu);
8004 %}
8005
8006 #ifndef _LP64
8007 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8008 match(Set dst (Conv2B src));
8009 effect( KILL ccr );
8010 ins_cost(DEFAULT_COST*2);
8011 format %{ "CMP R_G0,$src\n\t"
8012 "ADDX R_G0,0,$dst" %}
8013 ins_encode( enc_to_bool( src, dst ) );
8014 ins_pipe(ialu_reg_ialu);
8015 %}
8016 #else
8017 instruct convP2B( iRegI dst, iRegP src ) %{
8018 match(Set dst (Conv2B src));
8019 ins_cost(DEFAULT_COST*2);
8020 format %{ "MOV $src,$dst\n\t"
8021 "MOVRNZ $src,1,$dst" %}
8022 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8023 ins_pipe(ialu_clr_and_mover);
8024 %}
8025 #endif
8026
8027 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8028 match(Set dst (CmpLTMask src zero));
8029 effect(KILL ccr);
8030 size(4);
8031 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8032 ins_encode %{
8033 __ sra($src$$Register, 31, $dst$$Register);
8034 %}
8035 ins_pipe(ialu_reg_imm);
8036 %}
8037
8038 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8039 match(Set dst (CmpLTMask p q));
8040 effect( KILL ccr );
8041 ins_cost(DEFAULT_COST*4);
8042 format %{ "CMP $p,$q\n\t"
8043 "MOV #0,$dst\n\t"
8044 "BLT,a .+8\n\t"
8045 "MOV #-1,$dst" %}
8046 ins_encode( enc_ltmask(p,q,dst) );
8047 ins_pipe(ialu_reg_reg_ialu);
8048 %}
8049
8050 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8051 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8052 effect(KILL ccr, TEMP tmp);
8053 ins_cost(DEFAULT_COST*3);
8054
8055 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8056 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8057 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8058 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8059 ins_pipe(cadd_cmpltmask);
8060 %}
8061
8062 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8063 match(Set p (AndI (CmpLTMask p q) y));
8064 effect(KILL ccr);
8065 ins_cost(DEFAULT_COST*3);
8066
8067 format %{ "CMP $p,$q\n\t"
8068 "MOV $y,$p\n\t"
8069 "MOVge G0,$p" %}
8070 ins_encode %{
8071 __ cmp($p$$Register, $q$$Register);
8072 __ mov($y$$Register, $p$$Register);
8073 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8074 %}
8075 ins_pipe(ialu_reg_reg_ialu);
8076 %}
8077
8078 //-----------------------------------------------------------------
8079 // Direct raw moves between float and general registers using VIS3.
8080
8081 // ins_pipe(faddF_reg);
8082 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8083 predicate(UseVIS >= 3);
8084 match(Set dst (MoveF2I src));
8085
8086 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8087 ins_encode %{
8088 __ movstouw($src$$FloatRegister, $dst$$Register);
8089 %}
8090 ins_pipe(ialu_reg_reg);
8091 %}
8092
8093 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8094 predicate(UseVIS >= 3);
8095 match(Set dst (MoveI2F src));
8096
8097 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8098 ins_encode %{
8099 __ movwtos($src$$Register, $dst$$FloatRegister);
8100 %}
8101 ins_pipe(ialu_reg_reg);
8102 %}
8103
8104 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8105 predicate(UseVIS >= 3);
8106 match(Set dst (MoveD2L src));
8107
8108 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8109 ins_encode %{
8110 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8111 %}
8112 ins_pipe(ialu_reg_reg);
8113 %}
8114
8115 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8116 predicate(UseVIS >= 3);
8117 match(Set dst (MoveL2D src));
8118
8119 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8120 ins_encode %{
8121 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8122 %}
8123 ins_pipe(ialu_reg_reg);
8124 %}
8125
8126
8127 // Raw moves between float and general registers using stack.
8128
8129 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8130 match(Set dst (MoveF2I src));
8131 effect(DEF dst, USE src);
8132 ins_cost(MEMORY_REF_COST);
8133
8134 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8135 opcode(Assembler::lduw_op3);
8136 ins_encode(simple_form3_mem_reg( src, dst ) );
8137 ins_pipe(iload_mem);
8138 %}
8139
8140 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8141 match(Set dst (MoveI2F src));
8142 effect(DEF dst, USE src);
8143 ins_cost(MEMORY_REF_COST);
8144
8145 format %{ "LDF $src,$dst\t! MoveI2F" %}
8146 opcode(Assembler::ldf_op3);
8147 ins_encode(simple_form3_mem_reg(src, dst));
8148 ins_pipe(floadF_stk);
8149 %}
8150
8151 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8152 match(Set dst (MoveD2L src));
8153 effect(DEF dst, USE src);
8154 ins_cost(MEMORY_REF_COST);
8155
8156 format %{ "LDX $src,$dst\t! MoveD2L" %}
8157 opcode(Assembler::ldx_op3);
8158 ins_encode(simple_form3_mem_reg( src, dst ) );
8159 ins_pipe(iload_mem);
8160 %}
8161
8162 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8163 match(Set dst (MoveL2D src));
8164 effect(DEF dst, USE src);
8165 ins_cost(MEMORY_REF_COST);
8166
8167 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8168 opcode(Assembler::lddf_op3);
8169 ins_encode(simple_form3_mem_reg(src, dst));
8170 ins_pipe(floadD_stk);
8171 %}
8172
8173 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8174 match(Set dst (MoveF2I src));
8175 effect(DEF dst, USE src);
8176 ins_cost(MEMORY_REF_COST);
8177
8178 format %{ "STF $src,$dst\t! MoveF2I" %}
8179 opcode(Assembler::stf_op3);
8180 ins_encode(simple_form3_mem_reg(dst, src));
8181 ins_pipe(fstoreF_stk_reg);
8182 %}
8183
8184 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8185 match(Set dst (MoveI2F src));
8186 effect(DEF dst, USE src);
8187 ins_cost(MEMORY_REF_COST);
8188
8189 format %{ "STW $src,$dst\t! MoveI2F" %}
8190 opcode(Assembler::stw_op3);
8191 ins_encode(simple_form3_mem_reg( dst, src ) );
8192 ins_pipe(istore_mem_reg);
8193 %}
8194
8195 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8196 match(Set dst (MoveD2L src));
8197 effect(DEF dst, USE src);
8198 ins_cost(MEMORY_REF_COST);
8199
8200 format %{ "STDF $src,$dst\t! MoveD2L" %}
8201 opcode(Assembler::stdf_op3);
8202 ins_encode(simple_form3_mem_reg(dst, src));
8203 ins_pipe(fstoreD_stk_reg);
8204 %}
8205
8206 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8207 match(Set dst (MoveL2D src));
8208 effect(DEF dst, USE src);
8209 ins_cost(MEMORY_REF_COST);
8210
8211 format %{ "STX $src,$dst\t! MoveL2D" %}
8212 opcode(Assembler::stx_op3);
8213 ins_encode(simple_form3_mem_reg( dst, src ) );
8214 ins_pipe(istore_mem_reg);
8215 %}
8216
8217
8218 //----------Arithmetic Conversion Instructions---------------------------------
8219 // The conversions operations are all Alpha sorted. Please keep it that way!
8220
8221 instruct convD2F_reg(regF dst, regD src) %{
8222 match(Set dst (ConvD2F src));
8223 size(4);
8224 format %{ "FDTOS $src,$dst" %}
8225 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8226 ins_encode(form3_opf_rs2D_rdF(src, dst));
8227 ins_pipe(fcvtD2F);
8228 %}
8229
8230
8231 // Convert a double to an int in a float register.
8232 // If the double is a NAN, stuff a zero in instead.
8233 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8234 effect(DEF dst, USE src, KILL fcc0);
8235 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8236 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8237 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8238 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8239 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8240 "skip:" %}
8241 ins_encode(form_d2i_helper(src,dst));
8242 ins_pipe(fcvtD2I);
8243 %}
8244
8245 instruct convD2I_stk(stackSlotI dst, regD src) %{
8246 match(Set dst (ConvD2I src));
8247 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8248 expand %{
8249 regF tmp;
8250 convD2I_helper(tmp, src);
8251 regF_to_stkI(dst, tmp);
8252 %}
8253 %}
8254
8255 instruct convD2I_reg(iRegI dst, regD src) %{
8256 predicate(UseVIS >= 3);
8257 match(Set dst (ConvD2I src));
8258 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8259 expand %{
8260 regF tmp;
8261 convD2I_helper(tmp, src);
8262 MoveF2I_reg_reg(dst, tmp);
8263 %}
8264 %}
8265
8266
8267 // Convert a double to a long in a double register.
8268 // If the double is a NAN, stuff a zero in instead.
8269 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8270 effect(DEF dst, USE src, KILL fcc0);
8271 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8272 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8273 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8274 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8275 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8276 "skip:" %}
8277 ins_encode(form_d2l_helper(src,dst));
8278 ins_pipe(fcvtD2L);
8279 %}
8280
8281 instruct convD2L_stk(stackSlotL dst, regD src) %{
8282 match(Set dst (ConvD2L src));
8283 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8284 expand %{
8285 regD tmp;
8286 convD2L_helper(tmp, src);
8287 regD_to_stkL(dst, tmp);
8288 %}
8289 %}
8290
8291 instruct convD2L_reg(iRegL dst, regD src) %{
8292 predicate(UseVIS >= 3);
8293 match(Set dst (ConvD2L src));
8294 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8295 expand %{
8296 regD tmp;
8297 convD2L_helper(tmp, src);
8298 MoveD2L_reg_reg(dst, tmp);
8299 %}
8300 %}
8301
8302
8303 instruct convF2D_reg(regD dst, regF src) %{
8304 match(Set dst (ConvF2D src));
8305 format %{ "FSTOD $src,$dst" %}
8306 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8307 ins_encode(form3_opf_rs2F_rdD(src, dst));
8308 ins_pipe(fcvtF2D);
8309 %}
8310
8311
8312 // Convert a float to an int in a float register.
8313 // If the float is a NAN, stuff a zero in instead.
8314 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8315 effect(DEF dst, USE src, KILL fcc0);
8316 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8317 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8318 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8319 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8320 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8321 "skip:" %}
8322 ins_encode(form_f2i_helper(src,dst));
8323 ins_pipe(fcvtF2I);
8324 %}
8325
8326 instruct convF2I_stk(stackSlotI dst, regF src) %{
8327 match(Set dst (ConvF2I src));
8328 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8329 expand %{
8330 regF tmp;
8331 convF2I_helper(tmp, src);
8332 regF_to_stkI(dst, tmp);
8333 %}
8334 %}
8335
8336 instruct convF2I_reg(iRegI dst, regF src) %{
8337 predicate(UseVIS >= 3);
8338 match(Set dst (ConvF2I src));
8339 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8340 expand %{
8341 regF tmp;
8342 convF2I_helper(tmp, src);
8343 MoveF2I_reg_reg(dst, tmp);
8344 %}
8345 %}
8346
8347
8348 // Convert a float to a long in a float register.
8349 // If the float is a NAN, stuff a zero in instead.
8350 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8351 effect(DEF dst, USE src, KILL fcc0);
8352 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8353 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8354 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8355 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8356 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8357 "skip:" %}
8358 ins_encode(form_f2l_helper(src,dst));
8359 ins_pipe(fcvtF2L);
8360 %}
8361
8362 instruct convF2L_stk(stackSlotL dst, regF src) %{
8363 match(Set dst (ConvF2L src));
8364 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8365 expand %{
8366 regD tmp;
8367 convF2L_helper(tmp, src);
8368 regD_to_stkL(dst, tmp);
8369 %}
8370 %}
8371
8372 instruct convF2L_reg(iRegL dst, regF src) %{
8373 predicate(UseVIS >= 3);
8374 match(Set dst (ConvF2L src));
8375 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8376 expand %{
8377 regD tmp;
8378 convF2L_helper(tmp, src);
8379 MoveD2L_reg_reg(dst, tmp);
8380 %}
8381 %}
8382
8383
8384 instruct convI2D_helper(regD dst, regF tmp) %{
8385 effect(USE tmp, DEF dst);
8386 format %{ "FITOD $tmp,$dst" %}
8387 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8388 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8389 ins_pipe(fcvtI2D);
8390 %}
8391
8392 instruct convI2D_stk(stackSlotI src, regD dst) %{
8393 match(Set dst (ConvI2D src));
8394 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8395 expand %{
8396 regF tmp;
8397 stkI_to_regF(tmp, src);
8398 convI2D_helper(dst, tmp);
8399 %}
8400 %}
8401
8402 instruct convI2D_reg(regD_low dst, iRegI src) %{
8403 predicate(UseVIS >= 3);
8404 match(Set dst (ConvI2D src));
8405 expand %{
8406 regF tmp;
8407 MoveI2F_reg_reg(tmp, src);
8408 convI2D_helper(dst, tmp);
8409 %}
8410 %}
8411
8412 instruct convI2D_mem(regD_low dst, memory mem) %{
8413 match(Set dst (ConvI2D (LoadI mem)));
8414 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8415 format %{ "LDF $mem,$dst\n\t"
8416 "FITOD $dst,$dst" %}
8417 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8418 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8419 ins_pipe(floadF_mem);
8420 %}
8421
8422
8423 instruct convI2F_helper(regF dst, regF tmp) %{
8424 effect(DEF dst, USE tmp);
8425 format %{ "FITOS $tmp,$dst" %}
8426 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8427 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8428 ins_pipe(fcvtI2F);
8429 %}
8430
8431 instruct convI2F_stk(regF dst, stackSlotI src) %{
8432 match(Set dst (ConvI2F src));
8433 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8434 expand %{
8435 regF tmp;
8436 stkI_to_regF(tmp,src);
8437 convI2F_helper(dst, tmp);
8438 %}
8439 %}
8440
8441 instruct convI2F_reg(regF dst, iRegI src) %{
8442 predicate(UseVIS >= 3);
8443 match(Set dst (ConvI2F src));
8444 ins_cost(DEFAULT_COST);
8445 expand %{
8446 regF tmp;
8447 MoveI2F_reg_reg(tmp, src);
8448 convI2F_helper(dst, tmp);
8449 %}
8450 %}
8451
8452 instruct convI2F_mem( regF dst, memory mem ) %{
8453 match(Set dst (ConvI2F (LoadI mem)));
8454 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8455 format %{ "LDF $mem,$dst\n\t"
8456 "FITOS $dst,$dst" %}
8457 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8458 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8459 ins_pipe(floadF_mem);
8460 %}
8461
8462
8463 instruct convI2L_reg(iRegL dst, iRegI src) %{
8464 match(Set dst (ConvI2L src));
8465 size(4);
8466 format %{ "SRA $src,0,$dst\t! int->long" %}
8467 opcode(Assembler::sra_op3, Assembler::arith_op);
8468 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8469 ins_pipe(ialu_reg_reg);
8470 %}
8471
8472 // Zero-extend convert int to long
8473 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8474 match(Set dst (AndL (ConvI2L src) mask) );
8475 size(4);
8476 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8477 opcode(Assembler::srl_op3, Assembler::arith_op);
8478 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8479 ins_pipe(ialu_reg_reg);
8480 %}
8481
8482 // Zero-extend long
8483 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8484 match(Set dst (AndL src mask) );
8485 size(4);
8486 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8487 opcode(Assembler::srl_op3, Assembler::arith_op);
8488 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8489 ins_pipe(ialu_reg_reg);
8490 %}
8491
8492
8493 //-----------
8494 // Long to Double conversion using V8 opcodes.
8495 // Still useful because cheetah traps and becomes
8496 // amazingly slow for some common numbers.
8497
8498 // Magic constant, 0x43300000
8499 instruct loadConI_x43300000(iRegI dst) %{
8500 effect(DEF dst);
8501 size(4);
8502 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8503 ins_encode(SetHi22(0x43300000, dst));
8504 ins_pipe(ialu_none);
8505 %}
8506
8507 // Magic constant, 0x41f00000
8508 instruct loadConI_x41f00000(iRegI dst) %{
8509 effect(DEF dst);
8510 size(4);
8511 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8512 ins_encode(SetHi22(0x41f00000, dst));
8513 ins_pipe(ialu_none);
8514 %}
8515
8516 // Construct a double from two float halves
8517 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8518 effect(DEF dst, USE src1, USE src2);
8519 size(8);
8520 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8521 "FMOVS $src2.lo,$dst.lo" %}
8522 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8523 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8524 ins_pipe(faddD_reg_reg);
8525 %}
8526
8527 // Convert integer in high half of a double register (in the lower half of
8528 // the double register file) to double
8529 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8530 effect(DEF dst, USE src);
8531 size(4);
8532 format %{ "FITOD $src,$dst" %}
8533 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8534 ins_encode(form3_opf_rs2D_rdD(src, dst));
8535 ins_pipe(fcvtLHi2D);
8536 %}
8537
8538 // Add float double precision
8539 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8540 effect(DEF dst, USE src1, USE src2);
8541 size(4);
8542 format %{ "FADDD $src1,$src2,$dst" %}
8543 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8544 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8545 ins_pipe(faddD_reg_reg);
8546 %}
8547
8548 // Sub float double precision
8549 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8550 effect(DEF dst, USE src1, USE src2);
8551 size(4);
8552 format %{ "FSUBD $src1,$src2,$dst" %}
8553 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8554 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8555 ins_pipe(faddD_reg_reg);
8556 %}
8557
8558 // Mul float double precision
8559 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8560 effect(DEF dst, USE src1, USE src2);
8561 size(4);
8562 format %{ "FMULD $src1,$src2,$dst" %}
8563 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8564 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8565 ins_pipe(fmulD_reg_reg);
8566 %}
8567
8568 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8569 match(Set dst (ConvL2D src));
8570 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8571
8572 expand %{
8573 regD_low tmpsrc;
8574 iRegI ix43300000;
8575 iRegI ix41f00000;
8576 stackSlotL lx43300000;
8577 stackSlotL lx41f00000;
8578 regD_low dx43300000;
8579 regD dx41f00000;
8580 regD tmp1;
8581 regD_low tmp2;
8582 regD tmp3;
8583 regD tmp4;
8584
8585 stkL_to_regD(tmpsrc, src);
8586
8587 loadConI_x43300000(ix43300000);
8588 loadConI_x41f00000(ix41f00000);
8589 regI_to_stkLHi(lx43300000, ix43300000);
8590 regI_to_stkLHi(lx41f00000, ix41f00000);
8591 stkL_to_regD(dx43300000, lx43300000);
8592 stkL_to_regD(dx41f00000, lx41f00000);
8593
8594 convI2D_regDHi_regD(tmp1, tmpsrc);
8595 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8596 subD_regD_regD(tmp3, tmp2, dx43300000);
8597 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8598 addD_regD_regD(dst, tmp3, tmp4);
8599 %}
8600 %}
8601
8602 // Long to Double conversion using fast fxtof
8603 instruct convL2D_helper(regD dst, regD tmp) %{
8604 effect(DEF dst, USE tmp);
8605 size(4);
8606 format %{ "FXTOD $tmp,$dst" %}
8607 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8608 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8609 ins_pipe(fcvtL2D);
8610 %}
8611
8612 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8613 predicate(VM_Version::has_fast_fxtof());
8614 match(Set dst (ConvL2D src));
8615 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8616 expand %{
8617 regD tmp;
8618 stkL_to_regD(tmp, src);
8619 convL2D_helper(dst, tmp);
8620 %}
8621 %}
8622
8623 instruct convL2D_reg(regD dst, iRegL src) %{
8624 predicate(UseVIS >= 3);
8625 match(Set dst (ConvL2D src));
8626 expand %{
8627 regD tmp;
8628 MoveL2D_reg_reg(tmp, src);
8629 convL2D_helper(dst, tmp);
8630 %}
8631 %}
8632
8633 // Long to Float conversion using fast fxtof
8634 instruct convL2F_helper(regF dst, regD tmp) %{
8635 effect(DEF dst, USE tmp);
8636 size(4);
8637 format %{ "FXTOS $tmp,$dst" %}
8638 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8639 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8640 ins_pipe(fcvtL2F);
8641 %}
8642
8643 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8644 match(Set dst (ConvL2F src));
8645 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8646 expand %{
8647 regD tmp;
8648 stkL_to_regD(tmp, src);
8649 convL2F_helper(dst, tmp);
8650 %}
8651 %}
8652
8653 instruct convL2F_reg(regF dst, iRegL src) %{
8654 predicate(UseVIS >= 3);
8655 match(Set dst (ConvL2F src));
8656 ins_cost(DEFAULT_COST);
8657 expand %{
8658 regD tmp;
8659 MoveL2D_reg_reg(tmp, src);
8660 convL2F_helper(dst, tmp);
8661 %}
8662 %}
8663
8664 //-----------
8665
8666 instruct convL2I_reg(iRegI dst, iRegL src) %{
8667 match(Set dst (ConvL2I src));
8668 #ifndef _LP64
8669 format %{ "MOV $src.lo,$dst\t! long->int" %}
8670 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8671 ins_pipe(ialu_move_reg_I_to_L);
8672 #else
8673 size(4);
8674 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8675 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8676 ins_pipe(ialu_reg);
8677 #endif
8678 %}
8679
8680 // Register Shift Right Immediate
8681 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8682 match(Set dst (ConvL2I (RShiftL src cnt)));
8683
8684 size(4);
8685 format %{ "SRAX $src,$cnt,$dst" %}
8686 opcode(Assembler::srax_op3, Assembler::arith_op);
8687 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8688 ins_pipe(ialu_reg_imm);
8689 %}
8690
8691 //----------Control Flow Instructions------------------------------------------
8692 // Compare Instructions
8693 // Compare Integers
8694 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8695 match(Set icc (CmpI op1 op2));
8696 effect( DEF icc, USE op1, USE op2 );
8697
8698 size(4);
8699 format %{ "CMP $op1,$op2" %}
8700 opcode(Assembler::subcc_op3, Assembler::arith_op);
8701 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8702 ins_pipe(ialu_cconly_reg_reg);
8703 %}
8704
8705 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8706 match(Set icc (CmpU op1 op2));
8707
8708 size(4);
8709 format %{ "CMP $op1,$op2\t! unsigned" %}
8710 opcode(Assembler::subcc_op3, Assembler::arith_op);
8711 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8712 ins_pipe(ialu_cconly_reg_reg);
8713 %}
8714
8715 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8716 match(Set icc (CmpI op1 op2));
8717 effect( DEF icc, USE op1 );
8718
8719 size(4);
8720 format %{ "CMP $op1,$op2" %}
8721 opcode(Assembler::subcc_op3, Assembler::arith_op);
8722 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8723 ins_pipe(ialu_cconly_reg_imm);
8724 %}
8725
8726 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8727 match(Set icc (CmpI (AndI op1 op2) zero));
8728
8729 size(4);
8730 format %{ "BTST $op2,$op1" %}
8731 opcode(Assembler::andcc_op3, Assembler::arith_op);
8732 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8733 ins_pipe(ialu_cconly_reg_reg_zero);
8734 %}
8735
8736 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8737 match(Set icc (CmpI (AndI op1 op2) zero));
8738
8739 size(4);
8740 format %{ "BTST $op2,$op1" %}
8741 opcode(Assembler::andcc_op3, Assembler::arith_op);
8742 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8743 ins_pipe(ialu_cconly_reg_imm_zero);
8744 %}
8745
8746 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8747 match(Set xcc (CmpL op1 op2));
8748 effect( DEF xcc, USE op1, USE op2 );
8749
8750 size(4);
8751 format %{ "CMP $op1,$op2\t\t! long" %}
8752 opcode(Assembler::subcc_op3, Assembler::arith_op);
8753 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8754 ins_pipe(ialu_cconly_reg_reg);
8755 %}
8756
8757 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8758 match(Set xcc (CmpL op1 con));
8759 effect( DEF xcc, USE op1, USE con );
8760
8761 size(4);
8762 format %{ "CMP $op1,$con\t\t! long" %}
8763 opcode(Assembler::subcc_op3, Assembler::arith_op);
8764 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8765 ins_pipe(ialu_cconly_reg_reg);
8766 %}
8767
8768 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8769 match(Set xcc (CmpL (AndL op1 op2) zero));
8770 effect( DEF xcc, USE op1, USE op2 );
8771
8772 size(4);
8773 format %{ "BTST $op1,$op2\t\t! long" %}
8774 opcode(Assembler::andcc_op3, Assembler::arith_op);
8775 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8776 ins_pipe(ialu_cconly_reg_reg);
8777 %}
8778
8779 // useful for checking the alignment of a pointer:
8780 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8781 match(Set xcc (CmpL (AndL op1 con) zero));
8782 effect( DEF xcc, USE op1, USE con );
8783
8784 size(4);
8785 format %{ "BTST $op1,$con\t\t! long" %}
8786 opcode(Assembler::andcc_op3, Assembler::arith_op);
8787 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8788 ins_pipe(ialu_cconly_reg_reg);
8789 %}
8790
8791 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8792 match(Set icc (CmpU op1 op2));
8793
8794 size(4);
8795 format %{ "CMP $op1,$op2\t! unsigned" %}
8796 opcode(Assembler::subcc_op3, Assembler::arith_op);
8797 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8798 ins_pipe(ialu_cconly_reg_imm);
8799 %}
8800
8801 // Compare Pointers
8802 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8803 match(Set pcc (CmpP op1 op2));
8804
8805 size(4);
8806 format %{ "CMP $op1,$op2\t! ptr" %}
8807 opcode(Assembler::subcc_op3, Assembler::arith_op);
8808 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8809 ins_pipe(ialu_cconly_reg_reg);
8810 %}
8811
8812 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8813 match(Set pcc (CmpP op1 op2));
8814
8815 size(4);
8816 format %{ "CMP $op1,$op2\t! ptr" %}
8817 opcode(Assembler::subcc_op3, Assembler::arith_op);
8818 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8819 ins_pipe(ialu_cconly_reg_imm);
8820 %}
8821
8822 // Compare Narrow oops
8823 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8824 match(Set icc (CmpN op1 op2));
8825
8826 size(4);
8827 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8828 opcode(Assembler::subcc_op3, Assembler::arith_op);
8829 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8830 ins_pipe(ialu_cconly_reg_reg);
8831 %}
8832
8833 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8834 match(Set icc (CmpN op1 op2));
8835
8836 size(4);
8837 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8838 opcode(Assembler::subcc_op3, Assembler::arith_op);
8839 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8840 ins_pipe(ialu_cconly_reg_imm);
8841 %}
8842
8843 //----------Max and Min--------------------------------------------------------
8844 // Min Instructions
8845 // Conditional move for min
8846 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8847 effect( USE_DEF op2, USE op1, USE icc );
8848
8849 size(4);
8850 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8851 opcode(Assembler::less);
8852 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8853 ins_pipe(ialu_reg_flags);
8854 %}
8855
8856 // Min Register with Register.
8857 instruct minI_eReg(iRegI op1, iRegI op2) %{
8858 match(Set op2 (MinI op1 op2));
8859 ins_cost(DEFAULT_COST*2);
8860 expand %{
8861 flagsReg icc;
8862 compI_iReg(icc,op1,op2);
8863 cmovI_reg_lt(op2,op1,icc);
8864 %}
8865 %}
8866
8867 // Max Instructions
8868 // Conditional move for max
8869 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8870 effect( USE_DEF op2, USE op1, USE icc );
8871 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8872 opcode(Assembler::greater);
8873 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8874 ins_pipe(ialu_reg_flags);
8875 %}
8876
8877 // Max Register with Register
8878 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8879 match(Set op2 (MaxI op1 op2));
8880 ins_cost(DEFAULT_COST*2);
8881 expand %{
8882 flagsReg icc;
8883 compI_iReg(icc,op1,op2);
8884 cmovI_reg_gt(op2,op1,icc);
8885 %}
8886 %}
8887
8888
8889 //----------Float Compares----------------------------------------------------
8890 // Compare floating, generate condition code
8891 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8892 match(Set fcc (CmpF src1 src2));
8893
8894 size(4);
8895 format %{ "FCMPs $fcc,$src1,$src2" %}
8896 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8897 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8898 ins_pipe(faddF_fcc_reg_reg_zero);
8899 %}
8900
8901 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8902 match(Set fcc (CmpD src1 src2));
8903
8904 size(4);
8905 format %{ "FCMPd $fcc,$src1,$src2" %}
8906 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8907 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8908 ins_pipe(faddD_fcc_reg_reg_zero);
8909 %}
8910
8911
8912 // Compare floating, generate -1,0,1
8913 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8914 match(Set dst (CmpF3 src1 src2));
8915 effect(KILL fcc0);
8916 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8917 format %{ "fcmpl $dst,$src1,$src2" %}
8918 // Primary = float
8919 opcode( true );
8920 ins_encode( floating_cmp( dst, src1, src2 ) );
8921 ins_pipe( floating_cmp );
8922 %}
8923
8924 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8925 match(Set dst (CmpD3 src1 src2));
8926 effect(KILL fcc0);
8927 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8928 format %{ "dcmpl $dst,$src1,$src2" %}
8929 // Primary = double (not float)
8930 opcode( false );
8931 ins_encode( floating_cmp( dst, src1, src2 ) );
8932 ins_pipe( floating_cmp );
8933 %}
8934
8935 //----------Branches---------------------------------------------------------
8936 // Jump
8937 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8938 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8939 match(Jump switch_val);
8940 effect(TEMP table);
8941
8942 ins_cost(350);
8943
8944 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8945 "LD [O7 + $switch_val], O7\n\t"
8946 "JUMP O7" %}
8947 ins_encode %{
8948 // Calculate table address into a register.
8949 Register table_reg;
8950 Register label_reg = O7;
8951 // If we are calculating the size of this instruction don't trust
8952 // zero offsets because they might change when
8953 // MachConstantBaseNode decides to optimize the constant table
8954 // base.
8955 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8956 table_reg = $constanttablebase;
8957 } else {
8958 table_reg = O7;
8959 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8960 __ add($constanttablebase, con_offset, table_reg);
8961 }
8962
8963 // Jump to base address + switch value
8964 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8965 __ jmp(label_reg, G0);
8966 __ delayed()->nop();
8967 %}
8968 ins_pipe(ialu_reg_reg);
8969 %}
8970
8971 // Direct Branch. Use V8 version with longer range.
8972 instruct branch(label labl) %{
8973 match(Goto);
8974 effect(USE labl);
8975
8976 size(8);
8977 ins_cost(BRANCH_COST);
8978 format %{ "BA $labl" %}
8979 ins_encode %{
8980 Label* L = $labl$$label;
8981 __ ba(*L);
8982 __ delayed()->nop();
8983 %}
8984 ins_avoid_back_to_back(AVOID_BEFORE);
8985 ins_pipe(br);
8986 %}
8987
8988 // Direct Branch, short with no delay slot
8989 instruct branch_short(label labl) %{
8990 match(Goto);
8991 predicate(UseCBCond);
8992 effect(USE labl);
8993
8994 size(4);
8995 ins_cost(BRANCH_COST);
8996 format %{ "BA $labl\t! short branch" %}
8997 ins_encode %{
8998 Label* L = $labl$$label;
8999 assert(__ use_cbcond(*L), "back to back cbcond");
9000 __ ba_short(*L);
9001 %}
9002 ins_short_branch(1);
9003 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9004 ins_pipe(cbcond_reg_imm);
9005 %}
9006
9007 // Conditional Direct Branch
9008 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9009 match(If cmp icc);
9010 effect(USE labl);
9011
9012 size(8);
9013 ins_cost(BRANCH_COST);
9014 format %{ "BP$cmp $icc,$labl" %}
9015 // Prim = bits 24-22, Secnd = bits 31-30
9016 ins_encode( enc_bp( labl, cmp, icc ) );
9017 ins_avoid_back_to_back(AVOID_BEFORE);
9018 ins_pipe(br_cc);
9019 %}
9020
9021 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9022 match(If cmp icc);
9023 effect(USE labl);
9024
9025 ins_cost(BRANCH_COST);
9026 format %{ "BP$cmp $icc,$labl" %}
9027 // Prim = bits 24-22, Secnd = bits 31-30
9028 ins_encode( enc_bp( labl, cmp, icc ) );
9029 ins_avoid_back_to_back(AVOID_BEFORE);
9030 ins_pipe(br_cc);
9031 %}
9032
9033 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9034 match(If cmp pcc);
9035 effect(USE labl);
9036
9037 size(8);
9038 ins_cost(BRANCH_COST);
9039 format %{ "BP$cmp $pcc,$labl" %}
9040 ins_encode %{
9041 Label* L = $labl$$label;
9042 Assembler::Predict predict_taken =
9043 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9044
9045 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9046 __ delayed()->nop();
9047 %}
9048 ins_avoid_back_to_back(AVOID_BEFORE);
9049 ins_pipe(br_cc);
9050 %}
9051
9052 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9053 match(If cmp fcc);
9054 effect(USE labl);
9055
9056 size(8);
9057 ins_cost(BRANCH_COST);
9058 format %{ "FBP$cmp $fcc,$labl" %}
9059 ins_encode %{
9060 Label* L = $labl$$label;
9061 Assembler::Predict predict_taken =
9062 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9063
9064 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9065 __ delayed()->nop();
9066 %}
9067 ins_avoid_back_to_back(AVOID_BEFORE);
9068 ins_pipe(br_fcc);
9069 %}
9070
9071 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9072 match(CountedLoopEnd cmp icc);
9073 effect(USE labl);
9074
9075 size(8);
9076 ins_cost(BRANCH_COST);
9077 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9078 // Prim = bits 24-22, Secnd = bits 31-30
9079 ins_encode( enc_bp( labl, cmp, icc ) );
9080 ins_avoid_back_to_back(AVOID_BEFORE);
9081 ins_pipe(br_cc);
9082 %}
9083
9084 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9085 match(CountedLoopEnd cmp icc);
9086 effect(USE labl);
9087
9088 size(8);
9089 ins_cost(BRANCH_COST);
9090 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9091 // Prim = bits 24-22, Secnd = bits 31-30
9092 ins_encode( enc_bp( labl, cmp, icc ) );
9093 ins_avoid_back_to_back(AVOID_BEFORE);
9094 ins_pipe(br_cc);
9095 %}
9096
9097 // Compare and branch instructions
9098 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9099 match(If cmp (CmpI op1 op2));
9100 effect(USE labl, KILL icc);
9101
9102 size(12);
9103 ins_cost(BRANCH_COST);
9104 format %{ "CMP $op1,$op2\t! int\n\t"
9105 "BP$cmp $labl" %}
9106 ins_encode %{
9107 Label* L = $labl$$label;
9108 Assembler::Predict predict_taken =
9109 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9110 __ cmp($op1$$Register, $op2$$Register);
9111 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9112 __ delayed()->nop();
9113 %}
9114 ins_pipe(cmp_br_reg_reg);
9115 %}
9116
9117 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9118 match(If cmp (CmpI op1 op2));
9119 effect(USE labl, KILL icc);
9120
9121 size(12);
9122 ins_cost(BRANCH_COST);
9123 format %{ "CMP $op1,$op2\t! int\n\t"
9124 "BP$cmp $labl" %}
9125 ins_encode %{
9126 Label* L = $labl$$label;
9127 Assembler::Predict predict_taken =
9128 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9129 __ cmp($op1$$Register, $op2$$constant);
9130 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9131 __ delayed()->nop();
9132 %}
9133 ins_pipe(cmp_br_reg_imm);
9134 %}
9135
9136 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9137 match(If cmp (CmpU op1 op2));
9138 effect(USE labl, KILL icc);
9139
9140 size(12);
9141 ins_cost(BRANCH_COST);
9142 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9143 "BP$cmp $labl" %}
9144 ins_encode %{
9145 Label* L = $labl$$label;
9146 Assembler::Predict predict_taken =
9147 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9148 __ cmp($op1$$Register, $op2$$Register);
9149 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9150 __ delayed()->nop();
9151 %}
9152 ins_pipe(cmp_br_reg_reg);
9153 %}
9154
9155 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9156 match(If cmp (CmpU op1 op2));
9157 effect(USE labl, KILL icc);
9158
9159 size(12);
9160 ins_cost(BRANCH_COST);
9161 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9162 "BP$cmp $labl" %}
9163 ins_encode %{
9164 Label* L = $labl$$label;
9165 Assembler::Predict predict_taken =
9166 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9167 __ cmp($op1$$Register, $op2$$constant);
9168 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9169 __ delayed()->nop();
9170 %}
9171 ins_pipe(cmp_br_reg_imm);
9172 %}
9173
9174 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9175 match(If cmp (CmpL op1 op2));
9176 effect(USE labl, KILL xcc);
9177
9178 size(12);
9179 ins_cost(BRANCH_COST);
9180 format %{ "CMP $op1,$op2\t! long\n\t"
9181 "BP$cmp $labl" %}
9182 ins_encode %{
9183 Label* L = $labl$$label;
9184 Assembler::Predict predict_taken =
9185 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9186 __ cmp($op1$$Register, $op2$$Register);
9187 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9188 __ delayed()->nop();
9189 %}
9190 ins_pipe(cmp_br_reg_reg);
9191 %}
9192
9193 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9194 match(If cmp (CmpL op1 op2));
9195 effect(USE labl, KILL xcc);
9196
9197 size(12);
9198 ins_cost(BRANCH_COST);
9199 format %{ "CMP $op1,$op2\t! long\n\t"
9200 "BP$cmp $labl" %}
9201 ins_encode %{
9202 Label* L = $labl$$label;
9203 Assembler::Predict predict_taken =
9204 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9205 __ cmp($op1$$Register, $op2$$constant);
9206 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9207 __ delayed()->nop();
9208 %}
9209 ins_pipe(cmp_br_reg_imm);
9210 %}
9211
9212 // Compare Pointers and branch
9213 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9214 match(If cmp (CmpP op1 op2));
9215 effect(USE labl, KILL pcc);
9216
9217 size(12);
9218 ins_cost(BRANCH_COST);
9219 format %{ "CMP $op1,$op2\t! ptr\n\t"
9220 "B$cmp $labl" %}
9221 ins_encode %{
9222 Label* L = $labl$$label;
9223 Assembler::Predict predict_taken =
9224 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9225 __ cmp($op1$$Register, $op2$$Register);
9226 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9227 __ delayed()->nop();
9228 %}
9229 ins_pipe(cmp_br_reg_reg);
9230 %}
9231
9232 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9233 match(If cmp (CmpP op1 null));
9234 effect(USE labl, KILL pcc);
9235
9236 size(12);
9237 ins_cost(BRANCH_COST);
9238 format %{ "CMP $op1,0\t! ptr\n\t"
9239 "B$cmp $labl" %}
9240 ins_encode %{
9241 Label* L = $labl$$label;
9242 Assembler::Predict predict_taken =
9243 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9244 __ cmp($op1$$Register, G0);
9245 // bpr() is not used here since it has shorter distance.
9246 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9247 __ delayed()->nop();
9248 %}
9249 ins_pipe(cmp_br_reg_reg);
9250 %}
9251
9252 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9253 match(If cmp (CmpN op1 op2));
9254 effect(USE labl, KILL icc);
9255
9256 size(12);
9257 ins_cost(BRANCH_COST);
9258 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9259 "BP$cmp $labl" %}
9260 ins_encode %{
9261 Label* L = $labl$$label;
9262 Assembler::Predict predict_taken =
9263 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9264 __ cmp($op1$$Register, $op2$$Register);
9265 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9266 __ delayed()->nop();
9267 %}
9268 ins_pipe(cmp_br_reg_reg);
9269 %}
9270
9271 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9272 match(If cmp (CmpN op1 null));
9273 effect(USE labl, KILL icc);
9274
9275 size(12);
9276 ins_cost(BRANCH_COST);
9277 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9278 "BP$cmp $labl" %}
9279 ins_encode %{
9280 Label* L = $labl$$label;
9281 Assembler::Predict predict_taken =
9282 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9283 __ cmp($op1$$Register, G0);
9284 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9285 __ delayed()->nop();
9286 %}
9287 ins_pipe(cmp_br_reg_reg);
9288 %}
9289
9290 // Loop back branch
9291 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9292 match(CountedLoopEnd cmp (CmpI op1 op2));
9293 effect(USE labl, KILL icc);
9294
9295 size(12);
9296 ins_cost(BRANCH_COST);
9297 format %{ "CMP $op1,$op2\t! int\n\t"
9298 "BP$cmp $labl\t! Loop end" %}
9299 ins_encode %{
9300 Label* L = $labl$$label;
9301 Assembler::Predict predict_taken =
9302 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9303 __ cmp($op1$$Register, $op2$$Register);
9304 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9305 __ delayed()->nop();
9306 %}
9307 ins_pipe(cmp_br_reg_reg);
9308 %}
9309
9310 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9311 match(CountedLoopEnd cmp (CmpI op1 op2));
9312 effect(USE labl, KILL icc);
9313
9314 size(12);
9315 ins_cost(BRANCH_COST);
9316 format %{ "CMP $op1,$op2\t! int\n\t"
9317 "BP$cmp $labl\t! Loop end" %}
9318 ins_encode %{
9319 Label* L = $labl$$label;
9320 Assembler::Predict predict_taken =
9321 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9322 __ cmp($op1$$Register, $op2$$constant);
9323 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9324 __ delayed()->nop();
9325 %}
9326 ins_pipe(cmp_br_reg_imm);
9327 %}
9328
9329 // Short compare and branch instructions
9330 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9331 match(If cmp (CmpI op1 op2));
9332 predicate(UseCBCond);
9333 effect(USE labl, KILL icc);
9334
9335 size(4);
9336 ins_cost(BRANCH_COST);
9337 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9338 ins_encode %{
9339 Label* L = $labl$$label;
9340 assert(__ use_cbcond(*L), "back to back cbcond");
9341 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9342 %}
9343 ins_short_branch(1);
9344 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9345 ins_pipe(cbcond_reg_reg);
9346 %}
9347
9348 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9349 match(If cmp (CmpI op1 op2));
9350 predicate(UseCBCond);
9351 effect(USE labl, KILL icc);
9352
9353 size(4);
9354 ins_cost(BRANCH_COST);
9355 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9356 ins_encode %{
9357 Label* L = $labl$$label;
9358 assert(__ use_cbcond(*L), "back to back cbcond");
9359 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9360 %}
9361 ins_short_branch(1);
9362 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9363 ins_pipe(cbcond_reg_imm);
9364 %}
9365
9366 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9367 match(If cmp (CmpU op1 op2));
9368 predicate(UseCBCond);
9369 effect(USE labl, KILL icc);
9370
9371 size(4);
9372 ins_cost(BRANCH_COST);
9373 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9374 ins_encode %{
9375 Label* L = $labl$$label;
9376 assert(__ use_cbcond(*L), "back to back cbcond");
9377 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9378 %}
9379 ins_short_branch(1);
9380 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9381 ins_pipe(cbcond_reg_reg);
9382 %}
9383
9384 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9385 match(If cmp (CmpU op1 op2));
9386 predicate(UseCBCond);
9387 effect(USE labl, KILL icc);
9388
9389 size(4);
9390 ins_cost(BRANCH_COST);
9391 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9392 ins_encode %{
9393 Label* L = $labl$$label;
9394 assert(__ use_cbcond(*L), "back to back cbcond");
9395 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9396 %}
9397 ins_short_branch(1);
9398 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9399 ins_pipe(cbcond_reg_imm);
9400 %}
9401
9402 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9403 match(If cmp (CmpL op1 op2));
9404 predicate(UseCBCond);
9405 effect(USE labl, KILL xcc);
9406
9407 size(4);
9408 ins_cost(BRANCH_COST);
9409 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9410 ins_encode %{
9411 Label* L = $labl$$label;
9412 assert(__ use_cbcond(*L), "back to back cbcond");
9413 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9414 %}
9415 ins_short_branch(1);
9416 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9417 ins_pipe(cbcond_reg_reg);
9418 %}
9419
9420 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9421 match(If cmp (CmpL op1 op2));
9422 predicate(UseCBCond);
9423 effect(USE labl, KILL xcc);
9424
9425 size(4);
9426 ins_cost(BRANCH_COST);
9427 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9428 ins_encode %{
9429 Label* L = $labl$$label;
9430 assert(__ use_cbcond(*L), "back to back cbcond");
9431 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9432 %}
9433 ins_short_branch(1);
9434 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9435 ins_pipe(cbcond_reg_imm);
9436 %}
9437
9438 // Compare Pointers and branch
9439 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9440 match(If cmp (CmpP op1 op2));
9441 predicate(UseCBCond);
9442 effect(USE labl, KILL pcc);
9443
9444 size(4);
9445 ins_cost(BRANCH_COST);
9446 #ifdef _LP64
9447 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9448 #else
9449 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9450 #endif
9451 ins_encode %{
9452 Label* L = $labl$$label;
9453 assert(__ use_cbcond(*L), "back to back cbcond");
9454 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9455 %}
9456 ins_short_branch(1);
9457 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9458 ins_pipe(cbcond_reg_reg);
9459 %}
9460
9461 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9462 match(If cmp (CmpP op1 null));
9463 predicate(UseCBCond);
9464 effect(USE labl, KILL pcc);
9465
9466 size(4);
9467 ins_cost(BRANCH_COST);
9468 #ifdef _LP64
9469 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9470 #else
9471 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9472 #endif
9473 ins_encode %{
9474 Label* L = $labl$$label;
9475 assert(__ use_cbcond(*L), "back to back cbcond");
9476 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9477 %}
9478 ins_short_branch(1);
9479 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9480 ins_pipe(cbcond_reg_reg);
9481 %}
9482
9483 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9484 match(If cmp (CmpN op1 op2));
9485 predicate(UseCBCond);
9486 effect(USE labl, KILL icc);
9487
9488 size(4);
9489 ins_cost(BRANCH_COST);
9490 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9491 ins_encode %{
9492 Label* L = $labl$$label;
9493 assert(__ use_cbcond(*L), "back to back cbcond");
9494 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9495 %}
9496 ins_short_branch(1);
9497 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9498 ins_pipe(cbcond_reg_reg);
9499 %}
9500
9501 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9502 match(If cmp (CmpN op1 null));
9503 predicate(UseCBCond);
9504 effect(USE labl, KILL icc);
9505
9506 size(4);
9507 ins_cost(BRANCH_COST);
9508 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9509 ins_encode %{
9510 Label* L = $labl$$label;
9511 assert(__ use_cbcond(*L), "back to back cbcond");
9512 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9513 %}
9514 ins_short_branch(1);
9515 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9516 ins_pipe(cbcond_reg_reg);
9517 %}
9518
9519 // Loop back branch
9520 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9521 match(CountedLoopEnd cmp (CmpI op1 op2));
9522 predicate(UseCBCond);
9523 effect(USE labl, KILL icc);
9524
9525 size(4);
9526 ins_cost(BRANCH_COST);
9527 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9528 ins_encode %{
9529 Label* L = $labl$$label;
9530 assert(__ use_cbcond(*L), "back to back cbcond");
9531 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9532 %}
9533 ins_short_branch(1);
9534 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9535 ins_pipe(cbcond_reg_reg);
9536 %}
9537
9538 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9539 match(CountedLoopEnd cmp (CmpI op1 op2));
9540 predicate(UseCBCond);
9541 effect(USE labl, KILL icc);
9542
9543 size(4);
9544 ins_cost(BRANCH_COST);
9545 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9546 ins_encode %{
9547 Label* L = $labl$$label;
9548 assert(__ use_cbcond(*L), "back to back cbcond");
9549 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9550 %}
9551 ins_short_branch(1);
9552 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9553 ins_pipe(cbcond_reg_imm);
9554 %}
9555
9556 // Branch-on-register tests all 64 bits. We assume that values
9557 // in 64-bit registers always remains zero or sign extended
9558 // unless our code munges the high bits. Interrupts can chop
9559 // the high order bits to zero or sign at any time.
9560 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9561 match(If cmp (CmpI op1 zero));
9562 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9563 effect(USE labl);
9564
9565 size(8);
9566 ins_cost(BRANCH_COST);
9567 format %{ "BR$cmp $op1,$labl" %}
9568 ins_encode( enc_bpr( labl, cmp, op1 ) );
9569 ins_avoid_back_to_back(AVOID_BEFORE);
9570 ins_pipe(br_reg);
9571 %}
9572
9573 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9574 match(If cmp (CmpP op1 null));
9575 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9576 effect(USE labl);
9577
9578 size(8);
9579 ins_cost(BRANCH_COST);
9580 format %{ "BR$cmp $op1,$labl" %}
9581 ins_encode( enc_bpr( labl, cmp, op1 ) );
9582 ins_avoid_back_to_back(AVOID_BEFORE);
9583 ins_pipe(br_reg);
9584 %}
9585
9586 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9587 match(If cmp (CmpL op1 zero));
9588 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9589 effect(USE labl);
9590
9591 size(8);
9592 ins_cost(BRANCH_COST);
9593 format %{ "BR$cmp $op1,$labl" %}
9594 ins_encode( enc_bpr( labl, cmp, op1 ) );
9595 ins_avoid_back_to_back(AVOID_BEFORE);
9596 ins_pipe(br_reg);
9597 %}
9598
9599
9600 // ============================================================================
9601 // Long Compare
9602 //
9603 // Currently we hold longs in 2 registers. Comparing such values efficiently
9604 // is tricky. The flavor of compare used depends on whether we are testing
9605 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9606 // The GE test is the negated LT test. The LE test can be had by commuting
9607 // the operands (yielding a GE test) and then negating; negate again for the
9608 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9609 // NE test is negated from that.
9610
9611 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9612 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9613 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9614 // are collapsed internally in the ADLC's dfa-gen code. The match for
9615 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9616 // foo match ends up with the wrong leaf. One fix is to not match both
9617 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9618 // both forms beat the trinary form of long-compare and both are very useful
9619 // on Intel which has so few registers.
9620
9621 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9622 match(If cmp xcc);
9623 effect(USE labl);
9624
9625 size(8);
9626 ins_cost(BRANCH_COST);
9627 format %{ "BP$cmp $xcc,$labl" %}
9628 ins_encode %{
9629 Label* L = $labl$$label;
9630 Assembler::Predict predict_taken =
9631 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9632
9633 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9634 __ delayed()->nop();
9635 %}
9636 ins_avoid_back_to_back(AVOID_BEFORE);
9637 ins_pipe(br_cc);
9638 %}
9639
9640 // Manifest a CmpL3 result in an integer register. Very painful.
9641 // This is the test to avoid.
9642 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9643 match(Set dst (CmpL3 src1 src2) );
9644 effect( KILL ccr );
9645 ins_cost(6*DEFAULT_COST);
9646 size(24);
9647 format %{ "CMP $src1,$src2\t\t! long\n"
9648 "\tBLT,a,pn done\n"
9649 "\tMOV -1,$dst\t! delay slot\n"
9650 "\tBGT,a,pn done\n"
9651 "\tMOV 1,$dst\t! delay slot\n"
9652 "\tCLR $dst\n"
9653 "done:" %}
9654 ins_encode( cmpl_flag(src1,src2,dst) );
9655 ins_pipe(cmpL_reg);
9656 %}
9657
9658 // Conditional move
9659 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9660 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9661 ins_cost(150);
9662 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9663 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9664 ins_pipe(ialu_reg);
9665 %}
9666
9667 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9668 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9669 ins_cost(140);
9670 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9671 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9672 ins_pipe(ialu_imm);
9673 %}
9674
9675 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9676 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9677 ins_cost(150);
9678 format %{ "MOV$cmp $xcc,$src,$dst" %}
9679 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9680 ins_pipe(ialu_reg);
9681 %}
9682
9683 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9684 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9685 ins_cost(140);
9686 format %{ "MOV$cmp $xcc,$src,$dst" %}
9687 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9688 ins_pipe(ialu_imm);
9689 %}
9690
9691 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9692 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9693 ins_cost(150);
9694 format %{ "MOV$cmp $xcc,$src,$dst" %}
9695 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9696 ins_pipe(ialu_reg);
9697 %}
9698
9699 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9700 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9701 ins_cost(150);
9702 format %{ "MOV$cmp $xcc,$src,$dst" %}
9703 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9704 ins_pipe(ialu_reg);
9705 %}
9706
9707 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9708 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9709 ins_cost(140);
9710 format %{ "MOV$cmp $xcc,$src,$dst" %}
9711 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9712 ins_pipe(ialu_imm);
9713 %}
9714
9715 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9716 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9717 ins_cost(150);
9718 opcode(0x101);
9719 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9720 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9721 ins_pipe(int_conditional_float_move);
9722 %}
9723
9724 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9725 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9726 ins_cost(150);
9727 opcode(0x102);
9728 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9729 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9730 ins_pipe(int_conditional_float_move);
9731 %}
9732
9733 // ============================================================================
9734 // Safepoint Instruction
9735 instruct safePoint_poll(iRegP poll) %{
9736 match(SafePoint poll);
9737 effect(USE poll);
9738
9739 size(4);
9740 #ifdef _LP64
9741 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9742 #else
9743 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9744 #endif
9745 ins_encode %{
9746 __ relocate(relocInfo::poll_type);
9747 __ ld_ptr($poll$$Register, 0, G0);
9748 %}
9749 ins_pipe(loadPollP);
9750 %}
9751
9752 // ============================================================================
9753 // Call Instructions
9754 // Call Java Static Instruction
9755 instruct CallStaticJavaDirect( method meth ) %{
9756 match(CallStaticJava);
9757 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9758 effect(USE meth);
9759
9760 size(8);
9761 ins_cost(CALL_COST);
9762 format %{ "CALL,static ; NOP ==> " %}
9763 ins_encode( Java_Static_Call( meth ), call_epilog );
9764 ins_avoid_back_to_back(AVOID_BEFORE);
9765 ins_pipe(simple_call);
9766 %}
9767
9768 // Call Java Static Instruction (method handle version)
9769 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9770 match(CallStaticJava);
9771 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9772 effect(USE meth, KILL l7_mh_SP_save);
9773
9774 size(16);
9775 ins_cost(CALL_COST);
9776 format %{ "CALL,static/MethodHandle" %}
9777 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9778 ins_pipe(simple_call);
9779 %}
9780
9781 // Call Java Dynamic Instruction
9782 instruct CallDynamicJavaDirect( method meth ) %{
9783 match(CallDynamicJava);
9784 effect(USE meth);
9785
9786 ins_cost(CALL_COST);
9787 format %{ "SET (empty),R_G5\n\t"
9788 "CALL,dynamic ; NOP ==> " %}
9789 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9790 ins_pipe(call);
9791 %}
9792
9793 // Call Runtime Instruction
9794 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9795 match(CallRuntime);
9796 effect(USE meth, KILL l7);
9797 ins_cost(CALL_COST);
9798 format %{ "CALL,runtime" %}
9799 ins_encode( Java_To_Runtime( meth ),
9800 call_epilog, adjust_long_from_native_call );
9801 ins_avoid_back_to_back(AVOID_BEFORE);
9802 ins_pipe(simple_call);
9803 %}
9804
9805 // Call runtime without safepoint - same as CallRuntime
9806 instruct CallLeafDirect(method meth, l7RegP l7) %{
9807 match(CallLeaf);
9808 effect(USE meth, KILL l7);
9809 ins_cost(CALL_COST);
9810 format %{ "CALL,runtime leaf" %}
9811 ins_encode( Java_To_Runtime( meth ),
9812 call_epilog,
9813 adjust_long_from_native_call );
9814 ins_avoid_back_to_back(AVOID_BEFORE);
9815 ins_pipe(simple_call);
9816 %}
9817
9818 // Call runtime without safepoint - same as CallLeaf
9819 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9820 match(CallLeafNoFP);
9821 effect(USE meth, KILL l7);
9822 ins_cost(CALL_COST);
9823 format %{ "CALL,runtime leaf nofp" %}
9824 ins_encode( Java_To_Runtime( meth ),
9825 call_epilog,
9826 adjust_long_from_native_call );
9827 ins_avoid_back_to_back(AVOID_BEFORE);
9828 ins_pipe(simple_call);
9829 %}
9830
9831 // Tail Call; Jump from runtime stub to Java code.
9832 // Also known as an 'interprocedural jump'.
9833 // Target of jump will eventually return to caller.
9834 // TailJump below removes the return address.
9835 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9836 match(TailCall jump_target method_oop );
9837
9838 ins_cost(CALL_COST);
9839 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9840 ins_encode(form_jmpl(jump_target));
9841 ins_avoid_back_to_back(AVOID_BEFORE);
9842 ins_pipe(tail_call);
9843 %}
9844
9845
9846 // Return Instruction
9847 instruct Ret() %{
9848 match(Return);
9849
9850 // The epilogue node did the ret already.
9851 size(0);
9852 format %{ "! return" %}
9853 ins_encode();
9854 ins_pipe(empty);
9855 %}
9856
9857
9858 // Tail Jump; remove the return address; jump to target.
9859 // TailCall above leaves the return address around.
9860 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9861 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9862 // "restore" before this instruction (in Epilogue), we need to materialize it
9863 // in %i0.
9864 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9865 match( TailJump jump_target ex_oop );
9866 ins_cost(CALL_COST);
9867 format %{ "! discard R_O7\n\t"
9868 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9869 ins_encode(form_jmpl_set_exception_pc(jump_target));
9870 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9871 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9872 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9873 ins_avoid_back_to_back(AVOID_BEFORE);
9874 ins_pipe(tail_call);
9875 %}
9876
9877 // Create exception oop: created by stack-crawling runtime code.
9878 // Created exception is now available to this handler, and is setup
9879 // just prior to jumping to this handler. No code emitted.
9880 instruct CreateException( o0RegP ex_oop )
9881 %{
9882 match(Set ex_oop (CreateEx));
9883 ins_cost(0);
9884
9885 size(0);
9886 // use the following format syntax
9887 format %{ "! exception oop is in R_O0; no code emitted" %}
9888 ins_encode();
9889 ins_pipe(empty);
9890 %}
9891
9892
9893 // Rethrow exception:
9894 // The exception oop will come in the first argument position.
9895 // Then JUMP (not call) to the rethrow stub code.
9896 instruct RethrowException()
9897 %{
9898 match(Rethrow);
9899 ins_cost(CALL_COST);
9900
9901 // use the following format syntax
9902 format %{ "Jmp rethrow_stub" %}
9903 ins_encode(enc_rethrow);
9904 ins_avoid_back_to_back(AVOID_BEFORE);
9905 ins_pipe(tail_call);
9906 %}
9907
9908
9909 // Die now
9910 instruct ShouldNotReachHere( )
9911 %{
9912 match(Halt);
9913 ins_cost(CALL_COST);
9914
9915 size(4);
9916 // Use the following format syntax
9917 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9918 ins_encode( form2_illtrap() );
9919 ins_pipe(tail_call);
9920 %}
9921
9922 // ============================================================================
9923 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9924 // array for an instance of the superklass. Set a hidden internal cache on a
9925 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9926 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9927 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9928 match(Set index (PartialSubtypeCheck sub super));
9929 effect( KILL pcc, KILL o7 );
9930 ins_cost(DEFAULT_COST*10);
9931 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9932 ins_encode( enc_PartialSubtypeCheck() );
9933 ins_avoid_back_to_back(AVOID_BEFORE);
9934 ins_pipe(partial_subtype_check_pipe);
9935 %}
9936
9937 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9938 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9939 effect( KILL idx, KILL o7 );
9940 ins_cost(DEFAULT_COST*10);
9941 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9942 ins_encode( enc_PartialSubtypeCheck() );
9943 ins_avoid_back_to_back(AVOID_BEFORE);
9944 ins_pipe(partial_subtype_check_pipe);
9945 %}
9946
9947
9948 // ============================================================================
9949 // inlined locking and unlocking
9950
9951 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9952 match(Set pcc (FastLock object box));
9953
9954 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9955 ins_cost(100);
9956
9957 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9958 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9959 ins_pipe(long_memory_op);
9960 %}
9961
9962
9963 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9964 match(Set pcc (FastUnlock object box));
9965 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9966 ins_cost(100);
9967
9968 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9969 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9970 ins_pipe(long_memory_op);
9971 %}
9972
9973 // The encodings are generic.
9974 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9975 predicate(!use_block_zeroing(n->in(2)) );
9976 match(Set dummy (ClearArray cnt base));
9977 effect(TEMP temp, KILL ccr);
9978 ins_cost(300);
9979 format %{ "MOV $cnt,$temp\n"
9980 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9981 " BRge loop\t\t! Clearing loop\n"
9982 " STX G0,[$base+$temp]\t! delay slot" %}
9983
9984 ins_encode %{
9985 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9986 Register nof_bytes_arg = $cnt$$Register;
9987 Register nof_bytes_tmp = $temp$$Register;
9988 Register base_pointer_arg = $base$$Register;
9989
9990 Label loop;
9991 __ mov(nof_bytes_arg, nof_bytes_tmp);
9992
9993 // Loop and clear, walking backwards through the array.
9994 // nof_bytes_tmp (if >0) is always the number of bytes to zero
9995 __ bind(loop);
9996 __ deccc(nof_bytes_tmp, 8);
9997 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
9998 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
9999 // %%%% this mini-loop must not cross a cache boundary!
10000 %}
10001 ins_pipe(long_memory_op);
10002 %}
10003
10004 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10005 predicate(use_block_zeroing(n->in(2)));
10006 match(Set dummy (ClearArray cnt base));
10007 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10008 ins_cost(300);
10009 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10010
10011 ins_encode %{
10012
10013 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10014 Register to = $base$$Register;
10015 Register count = $cnt$$Register;
10016
10017 Label Ldone;
10018 __ nop(); // Separate short branches
10019 // Use BIS for zeroing (temp is not used).
10020 __ bis_zeroing(to, count, G0, Ldone);
10021 __ bind(Ldone);
10022
10023 %}
10024 ins_pipe(long_memory_op);
10025 %}
10026
10027 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10028 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10029 match(Set dummy (ClearArray cnt base));
10030 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10031 ins_cost(300);
10032 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10033
10034 ins_encode %{
10035
10036 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10037 Register to = $base$$Register;
10038 Register count = $cnt$$Register;
10039 Register temp = $tmp$$Register;
10040
10041 Label Ldone;
10042 __ nop(); // Separate short branches
10043 // Use BIS for zeroing
10044 __ bis_zeroing(to, count, temp, Ldone);
10045 __ bind(Ldone);
10046
10047 %}
10048 ins_pipe(long_memory_op);
10049 %}
10050
10051 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10052 o7RegI tmp, flagsReg ccr) %{
10053 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10054 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10055 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10056 ins_cost(300);
10057 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10058 ins_encode %{
10059 __ string_compare($str1$$Register, $str2$$Register,
10060 $cnt1$$Register, $cnt2$$Register,
10061 $tmp$$Register, $tmp$$Register,
10062 $result$$Register, StrIntrinsicNode::LL);
10063 %}
10064 ins_pipe(long_memory_op);
10065 %}
10066
10067 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10068 o7RegI tmp, flagsReg ccr) %{
10069 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10070 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10071 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10072 ins_cost(300);
10073 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10074 ins_encode %{
10075 __ string_compare($str1$$Register, $str2$$Register,
10076 $cnt1$$Register, $cnt2$$Register,
10077 $tmp$$Register, $tmp$$Register,
10078 $result$$Register, StrIntrinsicNode::UU);
10079 %}
10080 ins_pipe(long_memory_op);
10081 %}
10082
10083 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10084 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10085 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10086 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10087 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10088 ins_cost(300);
10089 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10090 ins_encode %{
10091 __ string_compare($str1$$Register, $str2$$Register,
10092 $cnt1$$Register, $cnt2$$Register,
10093 $tmp1$$Register, $tmp2$$Register,
10094 $result$$Register, StrIntrinsicNode::LU);
10095 %}
10096 ins_pipe(long_memory_op);
10097 %}
10098
10099 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10100 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10101 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10102 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10103 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10104 ins_cost(300);
10105 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10106 ins_encode %{
10107 __ string_compare($str2$$Register, $str1$$Register,
10108 $cnt2$$Register, $cnt1$$Register,
10109 $tmp1$$Register, $tmp2$$Register,
10110 $result$$Register, StrIntrinsicNode::UL);
10111 %}
10112 ins_pipe(long_memory_op);
10113 %}
10114
10115 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10116 o7RegI tmp, flagsReg ccr) %{
10117 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10118 match(Set result (StrEquals (Binary str1 str2) cnt));
10119 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10120 ins_cost(300);
10121 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10122 ins_encode %{
10123 __ array_equals(false, $str1$$Register, $str2$$Register,
10124 $cnt$$Register, $tmp$$Register,
10125 $result$$Register, true /* byte */);
10126 %}
10127 ins_pipe(long_memory_op);
10128 %}
10129
10130 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10131 o7RegI tmp, flagsReg ccr) %{
10132 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10133 match(Set result (StrEquals (Binary str1 str2) cnt));
10134 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10135 ins_cost(300);
10136 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10137 ins_encode %{
10138 __ array_equals(false, $str1$$Register, $str2$$Register,
10139 $cnt$$Register, $tmp$$Register,
10140 $result$$Register, false /* byte */);
10141 %}
10142 ins_pipe(long_memory_op);
10143 %}
10144
10145 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10146 o7RegI tmp2, flagsReg ccr) %{
10147 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10148 match(Set result (AryEq ary1 ary2));
10149 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10150 ins_cost(300);
10151 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10152 ins_encode %{
10153 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10154 $tmp1$$Register, $tmp2$$Register,
10155 $result$$Register, true /* byte */);
10156 %}
10157 ins_pipe(long_memory_op);
10158 %}
10159
10160 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10161 o7RegI tmp2, flagsReg ccr) %{
10162 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10163 match(Set result (AryEq ary1 ary2));
10164 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10165 ins_cost(300);
10166 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10167 ins_encode %{
10168 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10169 $tmp1$$Register, $tmp2$$Register,
10170 $result$$Register, false /* byte */);
10171 %}
10172 ins_pipe(long_memory_op);
10173 %}
10174
10175 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
10176 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
10177 flagsReg ccr)
10178 %{
10179 match(Set resultR (HasNegatives pAryR iSizeR));
10180 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
10181 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
10182 ins_encode %{
10183 __ has_negatives($pAryR$$Register, $iSizeR$$Register,
10184 $resultR$$Register,
10185 $tmp1L$$Register, $tmp2L$$Register,
10186 $tmp3L$$Register, $tmp4L$$Register);
10187 %}
10188 ins_pipe(long_memory_op);
10189 %}
10190
10191 // char[] to byte[] compression
10192 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10193 predicate(UseVIS < 3);
10194 match(Set result (StrCompressedCopy src (Binary dst len)));
10195 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10196 ins_cost(300);
10197 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10198 ins_encode %{
10199 Label Ldone;
10200 __ signx($len$$Register);
10201 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10202 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10203 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10204 __ bind(Ldone);
10205 %}
10206 ins_pipe(long_memory_op);
10207 %}
10208
10209 // fast char[] to byte[] compression using VIS instructions
10210 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10211 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10212 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10213 predicate(UseVIS >= 3);
10214 match(Set result (StrCompressedCopy src (Binary dst len)));
10215 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10216 ins_cost(300);
10217 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10218 ins_encode %{
10219 Label Ldone;
10220 __ signx($len$$Register);
10221 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10222 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10223 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10224 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10225 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10226 __ bind(Ldone);
10227 %}
10228 ins_pipe(long_memory_op);
10229 %}
10230
10231 // byte[] to char[] inflation
10232 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10233 iRegL tmp, flagsReg ccr) %{
10234 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10235 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10236 ins_cost(300);
10237 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10238 ins_encode %{
10239 Label Ldone;
10240 __ signx($len$$Register);
10241 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10242 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10243 __ bind(Ldone);
10244 %}
10245 ins_pipe(long_memory_op);
10246 %}
10247
10248 // fast byte[] to char[] inflation using VIS instructions
10249 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10250 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10251 predicate(UseVIS >= 3);
10252 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10253 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10254 ins_cost(300);
10255 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10256 ins_encode %{
10257 Label Ldone;
10258 __ signx($len$$Register);
10259 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10260 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10261 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10262 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10263 __ bind(Ldone);
10264 %}
10265 ins_pipe(long_memory_op);
10266 %}
10267
10268
10269 //---------- Zeros Count Instructions ------------------------------------------
10270
10271 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10272 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10273 match(Set dst (CountLeadingZerosI src));
10274 effect(TEMP dst, TEMP tmp, KILL cr);
10275
10276 // x |= (x >> 1);
10277 // x |= (x >> 2);
10278 // x |= (x >> 4);
10279 // x |= (x >> 8);
10280 // x |= (x >> 16);
10281 // return (WORDBITS - popc(x));
10282 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10283 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10284 "OR $dst,$tmp,$dst\n\t"
10285 "SRL $dst,2,$tmp\n\t"
10286 "OR $dst,$tmp,$dst\n\t"
10287 "SRL $dst,4,$tmp\n\t"
10288 "OR $dst,$tmp,$dst\n\t"
10289 "SRL $dst,8,$tmp\n\t"
10290 "OR $dst,$tmp,$dst\n\t"
10291 "SRL $dst,16,$tmp\n\t"
10292 "OR $dst,$tmp,$dst\n\t"
10293 "POPC $dst,$dst\n\t"
10294 "MOV 32,$tmp\n\t"
10295 "SUB $tmp,$dst,$dst" %}
10296 ins_encode %{
10297 Register Rdst = $dst$$Register;
10298 Register Rsrc = $src$$Register;
10299 Register Rtmp = $tmp$$Register;
10300 __ srl(Rsrc, 1, Rtmp);
10301 __ srl(Rsrc, 0, Rdst);
10302 __ or3(Rdst, Rtmp, Rdst);
10303 __ srl(Rdst, 2, Rtmp);
10304 __ or3(Rdst, Rtmp, Rdst);
10305 __ srl(Rdst, 4, Rtmp);
10306 __ or3(Rdst, Rtmp, Rdst);
10307 __ srl(Rdst, 8, Rtmp);
10308 __ or3(Rdst, Rtmp, Rdst);
10309 __ srl(Rdst, 16, Rtmp);
10310 __ or3(Rdst, Rtmp, Rdst);
10311 __ popc(Rdst, Rdst);
10312 __ mov(BitsPerInt, Rtmp);
10313 __ sub(Rtmp, Rdst, Rdst);
10314 %}
10315 ins_pipe(ialu_reg);
10316 %}
10317
10318 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10319 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10320 match(Set dst (CountLeadingZerosL src));
10321 effect(TEMP dst, TEMP tmp, KILL cr);
10322
10323 // x |= (x >> 1);
10324 // x |= (x >> 2);
10325 // x |= (x >> 4);
10326 // x |= (x >> 8);
10327 // x |= (x >> 16);
10328 // x |= (x >> 32);
10329 // return (WORDBITS - popc(x));
10330 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10331 "OR $src,$tmp,$dst\n\t"
10332 "SRLX $dst,2,$tmp\n\t"
10333 "OR $dst,$tmp,$dst\n\t"
10334 "SRLX $dst,4,$tmp\n\t"
10335 "OR $dst,$tmp,$dst\n\t"
10336 "SRLX $dst,8,$tmp\n\t"
10337 "OR $dst,$tmp,$dst\n\t"
10338 "SRLX $dst,16,$tmp\n\t"
10339 "OR $dst,$tmp,$dst\n\t"
10340 "SRLX $dst,32,$tmp\n\t"
10341 "OR $dst,$tmp,$dst\n\t"
10342 "POPC $dst,$dst\n\t"
10343 "MOV 64,$tmp\n\t"
10344 "SUB $tmp,$dst,$dst" %}
10345 ins_encode %{
10346 Register Rdst = $dst$$Register;
10347 Register Rsrc = $src$$Register;
10348 Register Rtmp = $tmp$$Register;
10349 __ srlx(Rsrc, 1, Rtmp);
10350 __ or3( Rsrc, Rtmp, Rdst);
10351 __ srlx(Rdst, 2, Rtmp);
10352 __ or3( Rdst, Rtmp, Rdst);
10353 __ srlx(Rdst, 4, Rtmp);
10354 __ or3( Rdst, Rtmp, Rdst);
10355 __ srlx(Rdst, 8, Rtmp);
10356 __ or3( Rdst, Rtmp, Rdst);
10357 __ srlx(Rdst, 16, Rtmp);
10358 __ or3( Rdst, Rtmp, Rdst);
10359 __ srlx(Rdst, 32, Rtmp);
10360 __ or3( Rdst, Rtmp, Rdst);
10361 __ popc(Rdst, Rdst);
10362 __ mov(BitsPerLong, Rtmp);
10363 __ sub(Rtmp, Rdst, Rdst);
10364 %}
10365 ins_pipe(ialu_reg);
10366 %}
10367
10368 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10369 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10370 match(Set dst (CountTrailingZerosI src));
10371 effect(TEMP dst, KILL cr);
10372
10373 // return popc(~x & (x - 1));
10374 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10375 "ANDN $dst,$src,$dst\n\t"
10376 "SRL $dst,R_G0,$dst\n\t"
10377 "POPC $dst,$dst" %}
10378 ins_encode %{
10379 Register Rdst = $dst$$Register;
10380 Register Rsrc = $src$$Register;
10381 __ sub(Rsrc, 1, Rdst);
10382 __ andn(Rdst, Rsrc, Rdst);
10383 __ srl(Rdst, G0, Rdst);
10384 __ popc(Rdst, Rdst);
10385 %}
10386 ins_pipe(ialu_reg);
10387 %}
10388
10389 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10390 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10391 match(Set dst (CountTrailingZerosL src));
10392 effect(TEMP dst, KILL cr);
10393
10394 // return popc(~x & (x - 1));
10395 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10396 "ANDN $dst,$src,$dst\n\t"
10397 "POPC $dst,$dst" %}
10398 ins_encode %{
10399 Register Rdst = $dst$$Register;
10400 Register Rsrc = $src$$Register;
10401 __ sub(Rsrc, 1, Rdst);
10402 __ andn(Rdst, Rsrc, Rdst);
10403 __ popc(Rdst, Rdst);
10404 %}
10405 ins_pipe(ialu_reg);
10406 %}
10407
10408
10409 //---------- Population Count Instructions -------------------------------------
10410
10411 instruct popCountI(iRegIsafe dst, iRegI src) %{
10412 predicate(UsePopCountInstruction);
10413 match(Set dst (PopCountI src));
10414
10415 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10416 "POPC $dst, $dst" %}
10417 ins_encode %{
10418 __ srl($src$$Register, G0, $dst$$Register);
10419 __ popc($dst$$Register, $dst$$Register);
10420 %}
10421 ins_pipe(ialu_reg);
10422 %}
10423
10424 // Note: Long.bitCount(long) returns an int.
10425 instruct popCountL(iRegIsafe dst, iRegL src) %{
10426 predicate(UsePopCountInstruction);
10427 match(Set dst (PopCountL src));
10428
10429 format %{ "POPC $src, $dst" %}
10430 ins_encode %{
10431 __ popc($src$$Register, $dst$$Register);
10432 %}
10433 ins_pipe(ialu_reg);
10434 %}
10435
10436
10437 // ============================================================================
10438 //------------Bytes reverse--------------------------------------------------
10439
10440 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10441 match(Set dst (ReverseBytesI src));
10442
10443 // Op cost is artificially doubled to make sure that load or store
10444 // instructions are preferred over this one which requires a spill
10445 // onto a stack slot.
10446 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10447 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10448
10449 ins_encode %{
10450 __ set($src$$disp + STACK_BIAS, O7);
10451 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10452 %}
10453 ins_pipe( iload_mem );
10454 %}
10455
10456 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10457 match(Set dst (ReverseBytesL src));
10458
10459 // Op cost is artificially doubled to make sure that load or store
10460 // instructions are preferred over this one which requires a spill
10461 // onto a stack slot.
10462 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10463 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10464
10465 ins_encode %{
10466 __ set($src$$disp + STACK_BIAS, O7);
10467 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10468 %}
10469 ins_pipe( iload_mem );
10470 %}
10471
10472 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10473 match(Set dst (ReverseBytesUS src));
10474
10475 // Op cost is artificially doubled to make sure that load or store
10476 // instructions are preferred over this one which requires a spill
10477 // onto a stack slot.
10478 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10479 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10480
10481 ins_encode %{
10482 // the value was spilled as an int so bias the load
10483 __ set($src$$disp + STACK_BIAS + 2, O7);
10484 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10485 %}
10486 ins_pipe( iload_mem );
10487 %}
10488
10489 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10490 match(Set dst (ReverseBytesS src));
10491
10492 // Op cost is artificially doubled to make sure that load or store
10493 // instructions are preferred over this one which requires a spill
10494 // onto a stack slot.
10495 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10496 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10497
10498 ins_encode %{
10499 // the value was spilled as an int so bias the load
10500 __ set($src$$disp + STACK_BIAS + 2, O7);
10501 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10502 %}
10503 ins_pipe( iload_mem );
10504 %}
10505
10506 // Load Integer reversed byte order
10507 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10508 match(Set dst (ReverseBytesI (LoadI src)));
10509
10510 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10511 size(4);
10512 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10513
10514 ins_encode %{
10515 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10516 %}
10517 ins_pipe(iload_mem);
10518 %}
10519
10520 // Load Long - aligned and reversed
10521 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10522 match(Set dst (ReverseBytesL (LoadL src)));
10523
10524 ins_cost(MEMORY_REF_COST);
10525 size(4);
10526 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10527
10528 ins_encode %{
10529 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10530 %}
10531 ins_pipe(iload_mem);
10532 %}
10533
10534 // Load unsigned short / char reversed byte order
10535 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10536 match(Set dst (ReverseBytesUS (LoadUS src)));
10537
10538 ins_cost(MEMORY_REF_COST);
10539 size(4);
10540 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10541
10542 ins_encode %{
10543 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10544 %}
10545 ins_pipe(iload_mem);
10546 %}
10547
10548 // Load short reversed byte order
10549 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10550 match(Set dst (ReverseBytesS (LoadS src)));
10551
10552 ins_cost(MEMORY_REF_COST);
10553 size(4);
10554 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10555
10556 ins_encode %{
10557 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10558 %}
10559 ins_pipe(iload_mem);
10560 %}
10561
10562 // Store Integer reversed byte order
10563 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10564 match(Set dst (StoreI dst (ReverseBytesI src)));
10565
10566 ins_cost(MEMORY_REF_COST);
10567 size(4);
10568 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10569
10570 ins_encode %{
10571 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10572 %}
10573 ins_pipe(istore_mem_reg);
10574 %}
10575
10576 // Store Long reversed byte order
10577 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10578 match(Set dst (StoreL dst (ReverseBytesL src)));
10579
10580 ins_cost(MEMORY_REF_COST);
10581 size(4);
10582 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10583
10584 ins_encode %{
10585 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10586 %}
10587 ins_pipe(istore_mem_reg);
10588 %}
10589
10590 // Store unsighed short/char reversed byte order
10591 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10592 match(Set dst (StoreC dst (ReverseBytesUS src)));
10593
10594 ins_cost(MEMORY_REF_COST);
10595 size(4);
10596 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10597
10598 ins_encode %{
10599 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10600 %}
10601 ins_pipe(istore_mem_reg);
10602 %}
10603
10604 // Store short reversed byte order
10605 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10606 match(Set dst (StoreC dst (ReverseBytesS src)));
10607
10608 ins_cost(MEMORY_REF_COST);
10609 size(4);
10610 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10611
10612 ins_encode %{
10613 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10614 %}
10615 ins_pipe(istore_mem_reg);
10616 %}
10617
10618 // ====================VECTOR INSTRUCTIONS=====================================
10619
10620 // Load Aligned Packed values into a Double Register
10621 instruct loadV8(regD dst, memory mem) %{
10622 predicate(n->as_LoadVector()->memory_size() == 8);
10623 match(Set dst (LoadVector mem));
10624 ins_cost(MEMORY_REF_COST);
10625 size(4);
10626 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10627 ins_encode %{
10628 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10629 %}
10630 ins_pipe(floadD_mem);
10631 %}
10632
10633 // Store Vector in Double register to memory
10634 instruct storeV8(memory mem, regD src) %{
10635 predicate(n->as_StoreVector()->memory_size() == 8);
10636 match(Set mem (StoreVector mem src));
10637 ins_cost(MEMORY_REF_COST);
10638 size(4);
10639 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10640 ins_encode %{
10641 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10642 %}
10643 ins_pipe(fstoreD_mem_reg);
10644 %}
10645
10646 // Store Zero into vector in memory
10647 instruct storeV8B_zero(memory mem, immI0 zero) %{
10648 predicate(n->as_StoreVector()->memory_size() == 8);
10649 match(Set mem (StoreVector mem (ReplicateB zero)));
10650 ins_cost(MEMORY_REF_COST);
10651 size(4);
10652 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10653 ins_encode %{
10654 __ stx(G0, $mem$$Address);
10655 %}
10656 ins_pipe(fstoreD_mem_zero);
10657 %}
10658
10659 instruct storeV4S_zero(memory mem, immI0 zero) %{
10660 predicate(n->as_StoreVector()->memory_size() == 8);
10661 match(Set mem (StoreVector mem (ReplicateS zero)));
10662 ins_cost(MEMORY_REF_COST);
10663 size(4);
10664 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10665 ins_encode %{
10666 __ stx(G0, $mem$$Address);
10667 %}
10668 ins_pipe(fstoreD_mem_zero);
10669 %}
10670
10671 instruct storeV2I_zero(memory mem, immI0 zero) %{
10672 predicate(n->as_StoreVector()->memory_size() == 8);
10673 match(Set mem (StoreVector mem (ReplicateI zero)));
10674 ins_cost(MEMORY_REF_COST);
10675 size(4);
10676 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10677 ins_encode %{
10678 __ stx(G0, $mem$$Address);
10679 %}
10680 ins_pipe(fstoreD_mem_zero);
10681 %}
10682
10683 instruct storeV2F_zero(memory mem, immF0 zero) %{
10684 predicate(n->as_StoreVector()->memory_size() == 8);
10685 match(Set mem (StoreVector mem (ReplicateF zero)));
10686 ins_cost(MEMORY_REF_COST);
10687 size(4);
10688 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10689 ins_encode %{
10690 __ stx(G0, $mem$$Address);
10691 %}
10692 ins_pipe(fstoreD_mem_zero);
10693 %}
10694
10695 // Replicate scalar to packed byte values into Double register
10696 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10697 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10698 match(Set dst (ReplicateB src));
10699 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10700 format %{ "SLLX $src,56,$tmp\n\t"
10701 "SRLX $tmp, 8,$tmp2\n\t"
10702 "OR $tmp,$tmp2,$tmp\n\t"
10703 "SRLX $tmp,16,$tmp2\n\t"
10704 "OR $tmp,$tmp2,$tmp\n\t"
10705 "SRLX $tmp,32,$tmp2\n\t"
10706 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10707 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10708 ins_encode %{
10709 Register Rsrc = $src$$Register;
10710 Register Rtmp = $tmp$$Register;
10711 Register Rtmp2 = $tmp2$$Register;
10712 __ sllx(Rsrc, 56, Rtmp);
10713 __ srlx(Rtmp, 8, Rtmp2);
10714 __ or3 (Rtmp, Rtmp2, Rtmp);
10715 __ srlx(Rtmp, 16, Rtmp2);
10716 __ or3 (Rtmp, Rtmp2, Rtmp);
10717 __ srlx(Rtmp, 32, Rtmp2);
10718 __ or3 (Rtmp, Rtmp2, Rtmp);
10719 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10720 %}
10721 ins_pipe(ialu_reg);
10722 %}
10723
10724 // Replicate scalar to packed byte values into Double stack
10725 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10726 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10727 match(Set dst (ReplicateB src));
10728 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10729 format %{ "SLLX $src,56,$tmp\n\t"
10730 "SRLX $tmp, 8,$tmp2\n\t"
10731 "OR $tmp,$tmp2,$tmp\n\t"
10732 "SRLX $tmp,16,$tmp2\n\t"
10733 "OR $tmp,$tmp2,$tmp\n\t"
10734 "SRLX $tmp,32,$tmp2\n\t"
10735 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10736 "STX $tmp,$dst\t! regL to stkD" %}
10737 ins_encode %{
10738 Register Rsrc = $src$$Register;
10739 Register Rtmp = $tmp$$Register;
10740 Register Rtmp2 = $tmp2$$Register;
10741 __ sllx(Rsrc, 56, Rtmp);
10742 __ srlx(Rtmp, 8, Rtmp2);
10743 __ or3 (Rtmp, Rtmp2, Rtmp);
10744 __ srlx(Rtmp, 16, Rtmp2);
10745 __ or3 (Rtmp, Rtmp2, Rtmp);
10746 __ srlx(Rtmp, 32, Rtmp2);
10747 __ or3 (Rtmp, Rtmp2, Rtmp);
10748 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10749 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10750 %}
10751 ins_pipe(ialu_reg);
10752 %}
10753
10754 // Replicate scalar constant to packed byte values in Double register
10755 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10756 predicate(n->as_Vector()->length() == 8);
10757 match(Set dst (ReplicateB con));
10758 effect(KILL tmp);
10759 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10760 ins_encode %{
10761 // XXX This is a quick fix for 6833573.
10762 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10763 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10764 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10765 %}
10766 ins_pipe(loadConFD);
10767 %}
10768
10769 // Replicate scalar to packed char/short values into Double register
10770 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10771 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10772 match(Set dst (ReplicateS src));
10773 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10774 format %{ "SLLX $src,48,$tmp\n\t"
10775 "SRLX $tmp,16,$tmp2\n\t"
10776 "OR $tmp,$tmp2,$tmp\n\t"
10777 "SRLX $tmp,32,$tmp2\n\t"
10778 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10779 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10780 ins_encode %{
10781 Register Rsrc = $src$$Register;
10782 Register Rtmp = $tmp$$Register;
10783 Register Rtmp2 = $tmp2$$Register;
10784 __ sllx(Rsrc, 48, Rtmp);
10785 __ srlx(Rtmp, 16, Rtmp2);
10786 __ or3 (Rtmp, Rtmp2, Rtmp);
10787 __ srlx(Rtmp, 32, Rtmp2);
10788 __ or3 (Rtmp, Rtmp2, Rtmp);
10789 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10790 %}
10791 ins_pipe(ialu_reg);
10792 %}
10793
10794 // Replicate scalar to packed char/short values into Double stack
10795 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10796 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10797 match(Set dst (ReplicateS src));
10798 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10799 format %{ "SLLX $src,48,$tmp\n\t"
10800 "SRLX $tmp,16,$tmp2\n\t"
10801 "OR $tmp,$tmp2,$tmp\n\t"
10802 "SRLX $tmp,32,$tmp2\n\t"
10803 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10804 "STX $tmp,$dst\t! regL to stkD" %}
10805 ins_encode %{
10806 Register Rsrc = $src$$Register;
10807 Register Rtmp = $tmp$$Register;
10808 Register Rtmp2 = $tmp2$$Register;
10809 __ sllx(Rsrc, 48, Rtmp);
10810 __ srlx(Rtmp, 16, Rtmp2);
10811 __ or3 (Rtmp, Rtmp2, Rtmp);
10812 __ srlx(Rtmp, 32, Rtmp2);
10813 __ or3 (Rtmp, Rtmp2, Rtmp);
10814 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10815 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10816 %}
10817 ins_pipe(ialu_reg);
10818 %}
10819
10820 // Replicate scalar constant to packed char/short values in Double register
10821 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10822 predicate(n->as_Vector()->length() == 4);
10823 match(Set dst (ReplicateS con));
10824 effect(KILL tmp);
10825 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10826 ins_encode %{
10827 // XXX This is a quick fix for 6833573.
10828 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10829 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10830 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10831 %}
10832 ins_pipe(loadConFD);
10833 %}
10834
10835 // Replicate scalar to packed int values into Double register
10836 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10837 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10838 match(Set dst (ReplicateI src));
10839 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10840 format %{ "SLLX $src,32,$tmp\n\t"
10841 "SRLX $tmp,32,$tmp2\n\t"
10842 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10843 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10844 ins_encode %{
10845 Register Rsrc = $src$$Register;
10846 Register Rtmp = $tmp$$Register;
10847 Register Rtmp2 = $tmp2$$Register;
10848 __ sllx(Rsrc, 32, Rtmp);
10849 __ srlx(Rtmp, 32, Rtmp2);
10850 __ or3 (Rtmp, Rtmp2, Rtmp);
10851 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10852 %}
10853 ins_pipe(ialu_reg);
10854 %}
10855
10856 // Replicate scalar to packed int values into Double stack
10857 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10858 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10859 match(Set dst (ReplicateI src));
10860 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10861 format %{ "SLLX $src,32,$tmp\n\t"
10862 "SRLX $tmp,32,$tmp2\n\t"
10863 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10864 "STX $tmp,$dst\t! regL to stkD" %}
10865 ins_encode %{
10866 Register Rsrc = $src$$Register;
10867 Register Rtmp = $tmp$$Register;
10868 Register Rtmp2 = $tmp2$$Register;
10869 __ sllx(Rsrc, 32, Rtmp);
10870 __ srlx(Rtmp, 32, Rtmp2);
10871 __ or3 (Rtmp, Rtmp2, Rtmp);
10872 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10873 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10874 %}
10875 ins_pipe(ialu_reg);
10876 %}
10877
10878 // Replicate scalar zero constant to packed int values in Double register
10879 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10880 predicate(n->as_Vector()->length() == 2);
10881 match(Set dst (ReplicateI con));
10882 effect(KILL tmp);
10883 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10884 ins_encode %{
10885 // XXX This is a quick fix for 6833573.
10886 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10887 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10888 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10889 %}
10890 ins_pipe(loadConFD);
10891 %}
10892
10893 // Replicate scalar to packed float values into Double stack
10894 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10895 predicate(n->as_Vector()->length() == 2);
10896 match(Set dst (ReplicateF src));
10897 ins_cost(MEMORY_REF_COST*2);
10898 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10899 "STF $src,$dst.lo" %}
10900 opcode(Assembler::stf_op3);
10901 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10902 ins_pipe(fstoreF_stk_reg);
10903 %}
10904
10905 // Replicate scalar zero constant to packed float values in Double register
10906 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10907 predicate(n->as_Vector()->length() == 2);
10908 match(Set dst (ReplicateF con));
10909 effect(KILL tmp);
10910 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10911 ins_encode %{
10912 // XXX This is a quick fix for 6833573.
10913 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10914 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10915 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10916 %}
10917 ins_pipe(loadConFD);
10918 %}
10919
10920 //----------PEEPHOLE RULES-----------------------------------------------------
10921 // These must follow all instruction definitions as they use the names
10922 // defined in the instructions definitions.
10923 //
10924 // peepmatch ( root_instr_name [preceding_instruction]* );
10925 //
10926 // peepconstraint %{
10927 // (instruction_number.operand_name relational_op instruction_number.operand_name
10928 // [, ...] );
10929 // // instruction numbers are zero-based using left to right order in peepmatch
10930 //
10931 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10932 // // provide an instruction_number.operand_name for each operand that appears
10933 // // in the replacement instruction's match rule
10934 //
10935 // ---------VM FLAGS---------------------------------------------------------
10936 //
10937 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10938 //
10939 // Each peephole rule is given an identifying number starting with zero and
10940 // increasing by one in the order seen by the parser. An individual peephole
10941 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10942 // on the command-line.
10943 //
10944 // ---------CURRENT LIMITATIONS----------------------------------------------
10945 //
10946 // Only match adjacent instructions in same basic block
10947 // Only equality constraints
10948 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10949 // Only one replacement instruction
10950 //
10951 // ---------EXAMPLE----------------------------------------------------------
10952 //
10953 // // pertinent parts of existing instructions in architecture description
10954 // instruct movI(eRegI dst, eRegI src) %{
10955 // match(Set dst (CopyI src));
10956 // %}
10957 //
10958 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10959 // match(Set dst (AddI dst src));
10960 // effect(KILL cr);
10961 // %}
10962 //
10963 // // Change (inc mov) to lea
10964 // peephole %{
10965 // // increment preceeded by register-register move
10966 // peepmatch ( incI_eReg movI );
10967 // // require that the destination register of the increment
10968 // // match the destination register of the move
10969 // peepconstraint ( 0.dst == 1.dst );
10970 // // construct a replacement instruction that sets
10971 // // the destination to ( move's source register + one )
10972 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10973 // %}
10974 //
10975
10976 // // Change load of spilled value to only a spill
10977 // instruct storeI(memory mem, eRegI src) %{
10978 // match(Set mem (StoreI mem src));
10979 // %}
10980 //
10981 // instruct loadI(eRegI dst, memory mem) %{
10982 // match(Set dst (LoadI mem));
10983 // %}
10984 //
10985 // peephole %{
10986 // peepmatch ( loadI storeI );
10987 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10988 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10989 // %}
10990
10991 //----------SMARTSPILL RULES---------------------------------------------------
10992 // These must follow all instruction definitions as they use the names
10993 // defined in the instructions definitions.
10994 //
10995 // SPARC will probably not have any of these rules due to RISC instruction set.
10996
10997 //----------PIPELINE-----------------------------------------------------------
10998 // Rules which define the behavior of the target architectures pipeline.