1 //
2 // Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
605 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr = (Assembler::ldst_op << 30)
952 | (dst_enc << 25)
953 | (primary << 19)
954 | (src1_enc << 14);
955
956 uint index = src2_enc;
957 int disp = disp32;
958
959 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
960 disp += STACK_BIAS;
961 // Check that stack offset fits, load into O7 if not
962 if (!Assembler::is_simm13(disp)) {
963 MacroAssembler _masm(&cbuf);
964 __ set(disp, O7);
965 if (index != R_G0_enc) {
966 __ add(O7, reg_to_register_object(index), O7);
967 }
968 index = R_O7_enc;
969 disp = 0;
970 }
971 }
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 if (VerifyOops) {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rspec);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1298 __ reserved_stack_check();
1299 }
1300
1301 // If this does safepoint polling, then do it here
1302 if(do_polling() && ra_->C->is_method_compilation()) {
1303 AddressLiteral polling_page(os::get_polling_page());
1304 __ sethi(polling_page, L0);
1305 __ relocate(relocInfo::poll_return_type);
1306 __ ld_ptr(L0, 0, G0);
1307 }
1308
1309 // If this is a return, then stuff the restore in the delay slot
1310 if(do_polling()) {
1311 if (UseCBCond && !ra_->C->is_method_compilation()) {
1312 // Insert extra padding for the case when the epilogue is preceded by
1313 // a cbcond jump, which can't be followed by a CTI instruction
1314 __ nop();
1315 }
1316 __ ret();
1317 __ delayed()->restore();
1318 } else {
1319 __ restore();
1320 }
1321 }
1322
1323 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1324 return MachNode::size(ra_);
1325 }
1326
1327 int MachEpilogNode::reloc() const {
1328 return 16; // a large enough number
1329 }
1330
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332 return MachNode::pipeline_class();
1333 }
1334
1335 int MachEpilogNode::safepoint_offset() const {
1336 assert( do_polling(), "no return for this epilog node");
1337 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339
1340 //=============================================================================
1341
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345 if (!OptoReg::is_valid(reg)) return rc_bad;
1346 if (OptoReg::is_stack(reg)) return rc_stack;
1347 VMReg r = OptoReg::as_VMReg(reg);
1348 if (r->is_Register()) return rc_int;
1349 assert(r->is_FloatRegister(), "must be");
1350 return rc_float;
1351 }
1352
1353 #ifndef PRODUCT
1354 ATTRIBUTE_PRINTF(2, 3)
1355 static void print_helper(outputStream* st, const char* format, ...) {
1356 if (st->position() > 0) {
1357 st->cr();
1358 st->sp();
1359 }
1360 va_list ap;
1361 va_start(ap, format);
1362 st->vprint(format, ap);
1363 va_end(ap);
1364 }
1365 #endif // !PRODUCT
1366
1367 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1368 if (cbuf) {
1369 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1370 }
1371 #ifndef PRODUCT
1372 else {
1373 if (is_load) {
1374 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1375 } else {
1376 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1377 }
1378 }
1379 #endif
1380 }
1381
1382 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1383 if (cbuf) {
1384 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1385 }
1386 #ifndef PRODUCT
1387 else {
1388 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1389 }
1390 #endif
1391 }
1392
1393 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1394 CodeBuffer *cbuf,
1395 PhaseRegAlloc *ra_,
1396 outputStream* st) {
1397 // Get registers to move
1398 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1399 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1400 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1401 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1402
1403 enum RC src_second_rc = rc_class(src_second);
1404 enum RC src_first_rc = rc_class(src_first);
1405 enum RC dst_second_rc = rc_class(dst_second);
1406 enum RC dst_first_rc = rc_class(dst_first);
1407
1408 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1409
1410 if (src_first == dst_first && src_second == dst_second) {
1411 return; // Self copy, no move
1412 }
1413
1414 // --------------------------------------
1415 // Check for mem-mem move. Load into unused float registers and fall into
1416 // the float-store case.
1417 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1418 int offset = ra_->reg2offset(src_first);
1419 // Further check for aligned-adjacent pair, so we can use a double load
1420 if ((src_first&1) == 0 && src_first+1 == src_second) {
1421 src_second = OptoReg::Name(R_F31_num);
1422 src_second_rc = rc_float;
1423 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1424 } else {
1425 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1426 }
1427 src_first = OptoReg::Name(R_F30_num);
1428 src_first_rc = rc_float;
1429 }
1430
1431 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1432 int offset = ra_->reg2offset(src_second);
1433 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1434 src_second = OptoReg::Name(R_F31_num);
1435 src_second_rc = rc_float;
1436 }
1437
1438 // --------------------------------------
1439 // Check for float->int copy; requires a trip through memory
1440 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1441 int offset = frame::register_save_words*wordSize;
1442 if (cbuf) {
1443 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1444 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1445 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1447 }
1448 #ifndef PRODUCT
1449 else {
1450 print_helper(st, "SUB R_SP,16,R_SP");
1451 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1452 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1453 print_helper(st, "ADD R_SP,16,R_SP");
1454 }
1455 #endif
1456 }
1457
1458 // Check for float->int copy on T4
1459 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1460 // Further check for aligned-adjacent pair, so we can use a double move
1461 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1463 return;
1464 }
1465 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1466 }
1467 // Check for int->float copy on T4
1468 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1469 // Further check for aligned-adjacent pair, so we can use a double move
1470 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1471 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1472 return;
1473 }
1474 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1475 }
1476
1477 // --------------------------------------
1478 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1479 // In such cases, I have to do the big-endian swap. For aligned targets, the
1480 // hardware does the flop for me. Doubles are always aligned, so no problem
1481 // there. Misaligned sources only come from native-long-returns (handled
1482 // special below).
1483 #ifndef _LP64
1484 if (src_first_rc == rc_int && // source is already big-endian
1485 src_second_rc != rc_bad && // 64-bit move
1486 ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1487 assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1488 // Do the big-endian flop.
1489 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1490 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1491 }
1492 #endif
1493
1494 // --------------------------------------
1495 // Check for integer reg-reg copy
1496 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1497 #ifndef _LP64
1498 if (src_first == R_O0_num && src_second == R_O1_num) { // Check for the evil O0/O1 native long-return case
1499 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1500 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1501 // operand contains the least significant word of the 64-bit value and vice versa.
1502 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1503 assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1504 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1505 if ( cbuf ) {
1506 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1507 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1508 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1509 #ifndef PRODUCT
1510 } else {
1511 print_helper(st, "SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1512 print_helper(st, "SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1513 print_helper(st, "OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1514 #endif
1515 }
1516 return;
1517 } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1518 // returning a long value in I0/I1
1519 // a SpillCopy must be able to target a return instruction's reg_class
1520 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1521 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1522 // operand contains the least significant word of the 64-bit value and vice versa.
1523 OptoReg::Name tdest = dst_first;
1524
1525 if (src_first == dst_first) {
1526 tdest = OptoReg::Name(R_O7_num);
1527 }
1528
1529 if (cbuf) {
1530 assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1531 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1532 // ShrL_reg_imm6
1533 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1534 // ShrR_reg_imm6 src, 0, dst
1535 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1536 if (tdest != dst_first) {
1537 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1538 }
1539 }
1540 #ifndef PRODUCT
1541 else {
1542 print_helper(st, "SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1543 print_helper(st, "SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1544 if (tdest != dst_first) {
1545 print_helper(st, "MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1546 }
1547 }
1548 #endif // PRODUCT
1549 return size+8;
1550 }
1551 #endif // !_LP64
1552 // Else normal reg-reg copy
1553 assert(src_second != dst_first, "smashed second before evacuating it");
1554 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1555 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1556 // This moves an aligned adjacent pair.
1557 // See if we are done.
1558 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1559 return;
1560 }
1561 }
1562
1563 // Check for integer store
1564 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1565 int offset = ra_->reg2offset(dst_first);
1566 // Further check for aligned-adjacent pair, so we can use a double store
1567 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1568 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1569 return;
1570 }
1571 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1572 }
1573
1574 // Check for integer load
1575 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1576 int offset = ra_->reg2offset(src_first);
1577 // Further check for aligned-adjacent pair, so we can use a double load
1578 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1579 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1580 return;
1581 }
1582 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1583 }
1584
1585 // Check for float reg-reg copy
1586 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1587 // Further check for aligned-adjacent pair, so we can use a double move
1588 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1589 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1590 return;
1591 }
1592 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1593 }
1594
1595 // Check for float store
1596 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1597 int offset = ra_->reg2offset(dst_first);
1598 // Further check for aligned-adjacent pair, so we can use a double store
1599 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1600 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1601 return;
1602 }
1603 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1604 }
1605
1606 // Check for float load
1607 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1608 int offset = ra_->reg2offset(src_first);
1609 // Further check for aligned-adjacent pair, so we can use a double load
1610 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1611 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1612 return;
1613 }
1614 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1615 }
1616
1617 // --------------------------------------------------------------------
1618 // Check for hi bits still needing moving. Only happens for misaligned
1619 // arguments to native calls.
1620 if (src_second == dst_second) {
1621 return; // Self copy; no move
1622 }
1623 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1624
1625 #ifndef _LP64
1626 // In the LP64 build, all registers can be moved as aligned/adjacent
1627 // pairs, so there's never any need to move the high bits separately.
1628 // The 32-bit builds have to deal with the 32-bit ABI which can force
1629 // all sorts of silly alignment problems.
1630
1631 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1632 // 32-bits of a 64-bit register, but are needed in low bits of another
1633 // register (else it's a hi-bits-to-hi-bits copy which should have
1634 // happened already as part of a 64-bit move)
1635 if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1636 assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1637 assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1638 // Shift src_second down to dst_second's low bits.
1639 if (cbuf) {
1640 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1641 #ifndef PRODUCT
1642 } else {
1643 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1644 #endif
1645 }
1646 return;
1647 }
1648
1649 // Check for high word integer store. Must down-shift the hi bits
1650 // into a temp register, then fall into the case of storing int bits.
1651 if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1652 // Shift src_second down to dst_second's low bits.
1653 if (cbuf) {
1654 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1655 #ifndef PRODUCT
1656 } else {
1657 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1658 #endif
1659 }
1660 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1661 }
1662
1663 // Check for high word integer load
1664 if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1665 return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1666
1667 // Check for high word integer store
1668 if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1669 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1670
1671 // Check for high word float store
1672 if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1673 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1674
1675 #endif // !_LP64
1676
1677 Unimplemented();
1678 }
1679
1680 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1681 PhaseRegAlloc *ra_,
1682 bool do_size,
1683 outputStream* st) const {
1684 assert(!do_size, "not supported");
1685 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1686 return 0;
1687 }
1688
1689 #ifndef PRODUCT
1690 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1691 implementation( NULL, ra_, false, st );
1692 }
1693 #endif
1694
1695 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1696 implementation( &cbuf, ra_, false, NULL );
1697 }
1698
1699 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1700 return MachNode::size(ra_);
1701 }
1702
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711 MacroAssembler _masm(&cbuf);
1712 for (int i = 0; i < _count; i += 1) {
1713 __ nop();
1714 }
1715 }
1716
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718 return 4 * _count;
1719 }
1720
1721
1722 //=============================================================================
1723 #ifndef PRODUCT
1724 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1725 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1726 int reg = ra_->get_reg_first(this);
1727 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1728 }
1729 #endif
1730
1731 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1732 MacroAssembler _masm(&cbuf);
1733 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1734 int reg = ra_->get_encode(this);
1735
1736 if (Assembler::is_simm13(offset)) {
1737 __ add(SP, offset, reg_to_register_object(reg));
1738 } else {
1739 __ set(offset, O7);
1740 __ add(SP, O7, reg_to_register_object(reg));
1741 }
1742 }
1743
1744 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1745 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1746 assert(ra_ == ra_->C->regalloc(), "sanity");
1747 return ra_->C->scratch_emit_size(this);
1748 }
1749
1750 //=============================================================================
1751 #ifndef PRODUCT
1752 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1753 st->print_cr("\nUEP:");
1754 #ifdef _LP64
1755 if (UseCompressedClassPointers) {
1756 assert(Universe::heap() != NULL, "java heap should be initialized");
1757 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1758 if (Universe::narrow_klass_base() != 0) {
1759 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1760 if (Universe::narrow_klass_shift() != 0) {
1761 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1762 }
1763 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1764 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1765 } else {
1766 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1767 }
1768 } else {
1769 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1770 }
1771 st->print_cr("\tCMP R_G5,R_G3" );
1772 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1773 #else // _LP64
1774 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1775 st->print_cr("\tCMP R_G5,R_G3" );
1776 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1777 #endif // _LP64
1778 }
1779 #endif
1780
1781 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1782 MacroAssembler _masm(&cbuf);
1783 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1784 Register temp_reg = G3;
1785 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1786
1787 // Load klass from receiver
1788 __ load_klass(O0, temp_reg);
1789 // Compare against expected klass
1790 __ cmp(temp_reg, G5_ic_reg);
1791 // Branch to miss code, checks xcc or icc depending
1792 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1793 }
1794
1795 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1796 return MachNode::size(ra_);
1797 }
1798
1799
1800 //=============================================================================
1801
1802
1803 // Emit exception handler code.
1804 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1805 Register temp_reg = G3;
1806 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1807 MacroAssembler _masm(&cbuf);
1808
1809 address base = __ start_a_stub(size_exception_handler());
1810 if (base == NULL) {
1811 ciEnv::current()->record_failure("CodeCache is full");
1812 return 0; // CodeBuffer::expand failed
1813 }
1814
1815 int offset = __ offset();
1816
1817 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1818 __ delayed()->nop();
1819
1820 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1821
1822 __ end_a_stub();
1823
1824 return offset;
1825 }
1826
1827 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1828 // Can't use any of the current frame's registers as we may have deopted
1829 // at a poll and everything (including G3) can be live.
1830 Register temp_reg = L0;
1831 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1832 MacroAssembler _masm(&cbuf);
1833
1834 address base = __ start_a_stub(size_deopt_handler());
1835 if (base == NULL) {
1836 ciEnv::current()->record_failure("CodeCache is full");
1837 return 0; // CodeBuffer::expand failed
1838 }
1839
1840 int offset = __ offset();
1841 __ save_frame(0);
1842 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1843 __ delayed()->restore();
1844
1845 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1846
1847 __ end_a_stub();
1848 return offset;
1849
1850 }
1851
1852 // Given a register encoding, produce a Integer Register object
1853 static Register reg_to_register_object(int register_encoding) {
1854 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1855 return as_Register(register_encoding);
1856 }
1857
1858 // Given a register encoding, produce a single-precision Float Register object
1859 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1860 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1861 return as_SingleFloatRegister(register_encoding);
1862 }
1863
1864 // Given a register encoding, produce a double-precision Float Register object
1865 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1866 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1867 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1868 return as_DoubleFloatRegister(register_encoding);
1869 }
1870
1871 const bool Matcher::match_rule_supported(int opcode) {
1872 if (!has_match_rule(opcode))
1873 return false;
1874
1875 switch (opcode) {
1876 case Op_CountLeadingZerosI:
1877 case Op_CountLeadingZerosL:
1878 case Op_CountTrailingZerosI:
1879 case Op_CountTrailingZerosL:
1880 case Op_PopCountI:
1881 case Op_PopCountL:
1882 if (!UsePopCountInstruction)
1883 return false;
1884 case Op_CompareAndSwapL:
1885 #ifdef _LP64
1886 case Op_CompareAndSwapP:
1887 #endif
1888 if (!VM_Version::supports_cx8())
1889 return false;
1890 break;
1891 }
1892
1893 return true; // Per default match rules are supported.
1894 }
1895
1896 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1897
1898 // TODO
1899 // identify extra cases that we might want to provide match rules for
1900 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1901 bool ret_value = match_rule_supported(opcode);
1902 // Add rules here.
1903
1904 return ret_value; // Per default match rules are supported.
1905 }
1906
1907 const bool Matcher::has_predicated_vectors(void) {
1908 return false;
1909 }
1910
1911 const int Matcher::float_pressure(int default_pressure_threshold) {
1912 return default_pressure_threshold;
1913 }
1914
1915 int Matcher::regnum_to_fpu_offset(int regnum) {
1916 return regnum - 32; // The FP registers are in the second chunk
1917 }
1918
1919 #ifdef ASSERT
1920 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1921 #endif
1922
1923 // Vector width in bytes
1924 const int Matcher::vector_width_in_bytes(BasicType bt) {
1925 assert(MaxVectorSize == 8, "");
1926 return 8;
1927 }
1928
1929 // Vector ideal reg
1930 const int Matcher::vector_ideal_reg(int size) {
1931 assert(MaxVectorSize == 8, "");
1932 return Op_RegD;
1933 }
1934
1935 const int Matcher::vector_shift_count_ideal_reg(int size) {
1936 fatal("vector shift is not supported");
1937 return Node::NotAMachineReg;
1938 }
1939
1940 // Limits on vector size (number of elements) loaded into vector.
1941 const int Matcher::max_vector_size(const BasicType bt) {
1942 assert(is_java_primitive(bt), "only primitive type vectors");
1943 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1944 }
1945
1946 const int Matcher::min_vector_size(const BasicType bt) {
1947 return max_vector_size(bt); // Same as max.
1948 }
1949
1950 // SPARC doesn't support misaligned vectors store/load.
1951 const bool Matcher::misaligned_vectors_ok() {
1952 return false;
1953 }
1954
1955 // Current (2013) SPARC platforms need to read original key
1956 // to construct decryption expanded key
1957 const bool Matcher::pass_original_key_for_aes() {
1958 return true;
1959 }
1960
1961 // USII supports fxtof through the whole range of number, USIII doesn't
1962 const bool Matcher::convL2FSupported(void) {
1963 return VM_Version::has_fast_fxtof();
1964 }
1965
1966 // Is this branch offset short enough that a short branch can be used?
1967 //
1968 // NOTE: If the platform does not provide any short branch variants, then
1969 // this method should return false for offset 0.
1970 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1971 // The passed offset is relative to address of the branch.
1972 // Don't need to adjust the offset.
1973 return UseCBCond && Assembler::is_simm12(offset);
1974 }
1975
1976 const bool Matcher::isSimpleConstant64(jlong value) {
1977 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1978 // Depends on optimizations in MacroAssembler::setx.
1979 int hi = (int)(value >> 32);
1980 int lo = (int)(value & ~0);
1981 return (hi == 0) || (hi == -1) || (lo == 0);
1982 }
1983
1984 // No scaling for the parameter the ClearArray node.
1985 const bool Matcher::init_array_count_is_in_bytes = true;
1986
1987 // No additional cost for CMOVL.
1988 const int Matcher::long_cmove_cost() { return 0; }
1989
1990 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1991 const int Matcher::float_cmove_cost() {
1992 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1993 }
1994
1995 // Does the CPU require late expand (see block.cpp for description of late expand)?
1996 const bool Matcher::require_postalloc_expand = false;
1997
1998 // Should the Matcher clone shifts on addressing modes, expecting them to
1999 // be subsumed into complex addressing expressions or compute them into
2000 // registers? True for Intel but false for most RISCs
2001 const bool Matcher::clone_shift_expressions = false;
2002
2003 // Do we need to mask the count passed to shift instructions or does
2004 // the cpu only look at the lower 5/6 bits anyway?
2005 const bool Matcher::need_masked_shift_count = false;
2006
2007 bool Matcher::narrow_oop_use_complex_address() {
2008 NOT_LP64(ShouldNotCallThis());
2009 assert(UseCompressedOops, "only for compressed oops code");
2010 return false;
2011 }
2012
2013 bool Matcher::narrow_klass_use_complex_address() {
2014 NOT_LP64(ShouldNotCallThis());
2015 assert(UseCompressedClassPointers, "only for compressed klass code");
2016 return false;
2017 }
2018
2019 bool Matcher::const_oop_prefer_decode() {
2020 // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
2021 return Universe::narrow_oop_base() == NULL;
2022 }
2023
2024 bool Matcher::const_klass_prefer_decode() {
2025 // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
2026 return Universe::narrow_klass_base() == NULL;
2027 }
2028
2029 // Is it better to copy float constants, or load them directly from memory?
2030 // Intel can load a float constant from a direct address, requiring no
2031 // extra registers. Most RISCs will have to materialize an address into a
2032 // register first, so they would do better to copy the constant from stack.
2033 const bool Matcher::rematerialize_float_constants = false;
2034
2035 // If CPU can load and store mis-aligned doubles directly then no fixup is
2036 // needed. Else we split the double into 2 integer pieces and move it
2037 // piece-by-piece. Only happens when passing doubles into C code as the
2038 // Java calling convention forces doubles to be aligned.
2039 #ifdef _LP64
2040 const bool Matcher::misaligned_doubles_ok = true;
2041 #else
2042 const bool Matcher::misaligned_doubles_ok = false;
2043 #endif
2044
2045 // No-op on SPARC.
2046 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2047 }
2048
2049 // Advertise here if the CPU requires explicit rounding operations
2050 // to implement the UseStrictFP mode.
2051 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2052
2053 // Are floats converted to double when stored to stack during deoptimization?
2054 // Sparc does not handle callee-save floats.
2055 bool Matcher::float_in_double() { return false; }
2056
2057 // Do ints take an entire long register or just half?
2058 // Note that we if-def off of _LP64.
2059 // The relevant question is how the int is callee-saved. In _LP64
2060 // the whole long is written but de-opt'ing will have to extract
2061 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2062 #ifdef _LP64
2063 const bool Matcher::int_in_long = true;
2064 #else
2065 const bool Matcher::int_in_long = false;
2066 #endif
2067
2068 // Return whether or not this register is ever used as an argument. This
2069 // function is used on startup to build the trampoline stubs in generateOptoStub.
2070 // Registers not mentioned will be killed by the VM call in the trampoline, and
2071 // arguments in those registers not be available to the callee.
2072 bool Matcher::can_be_java_arg( int reg ) {
2073 // Standard sparc 6 args in registers
2074 if( reg == R_I0_num ||
2075 reg == R_I1_num ||
2076 reg == R_I2_num ||
2077 reg == R_I3_num ||
2078 reg == R_I4_num ||
2079 reg == R_I5_num ) return true;
2080 #ifdef _LP64
2081 // 64-bit builds can pass 64-bit pointers and longs in
2082 // the high I registers
2083 if( reg == R_I0H_num ||
2084 reg == R_I1H_num ||
2085 reg == R_I2H_num ||
2086 reg == R_I3H_num ||
2087 reg == R_I4H_num ||
2088 reg == R_I5H_num ) return true;
2089
2090 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2091 return true;
2092 }
2093
2094 #else
2095 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2096 // Longs cannot be passed in O regs, because O regs become I regs
2097 // after a 'save' and I regs get their high bits chopped off on
2098 // interrupt.
2099 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2100 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2101 #endif
2102 // A few float args in registers
2103 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2104
2105 return false;
2106 }
2107
2108 bool Matcher::is_spillable_arg( int reg ) {
2109 return can_be_java_arg(reg);
2110 }
2111
2112 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2113 // Use hardware SDIVX instruction when it is
2114 // faster than a code which use multiply.
2115 return VM_Version::has_fast_idiv();
2116 }
2117
2118 // Register for DIVI projection of divmodI
2119 RegMask Matcher::divI_proj_mask() {
2120 ShouldNotReachHere();
2121 return RegMask();
2122 }
2123
2124 // Register for MODI projection of divmodI
2125 RegMask Matcher::modI_proj_mask() {
2126 ShouldNotReachHere();
2127 return RegMask();
2128 }
2129
2130 // Register for DIVL projection of divmodL
2131 RegMask Matcher::divL_proj_mask() {
2132 ShouldNotReachHere();
2133 return RegMask();
2134 }
2135
2136 // Register for MODL projection of divmodL
2137 RegMask Matcher::modL_proj_mask() {
2138 ShouldNotReachHere();
2139 return RegMask();
2140 }
2141
2142 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2143 return L7_REGP_mask();
2144 }
2145
2146 %}
2147
2148
2149 // The intptr_t operand types, defined by textual substitution.
2150 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2151 #ifdef _LP64
2152 #define immX immL
2153 #define immX13 immL13
2154 #define immX13m7 immL13m7
2155 #define iRegX iRegL
2156 #define g1RegX g1RegL
2157 #else
2158 #define immX immI
2159 #define immX13 immI13
2160 #define immX13m7 immI13m7
2161 #define iRegX iRegI
2162 #define g1RegX g1RegI
2163 #endif
2164
2165 //----------ENCODING BLOCK-----------------------------------------------------
2166 // This block specifies the encoding classes used by the compiler to output
2167 // byte streams. Encoding classes are parameterized macros used by
2168 // Machine Instruction Nodes in order to generate the bit encoding of the
2169 // instruction. Operands specify their base encoding interface with the
2170 // interface keyword. There are currently supported four interfaces,
2171 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2172 // operand to generate a function which returns its register number when
2173 // queried. CONST_INTER causes an operand to generate a function which
2174 // returns the value of the constant when queried. MEMORY_INTER causes an
2175 // operand to generate four functions which return the Base Register, the
2176 // Index Register, the Scale Value, and the Offset Value of the operand when
2177 // queried. COND_INTER causes an operand to generate six functions which
2178 // return the encoding code (ie - encoding bits for the instruction)
2179 // associated with each basic boolean condition for a conditional instruction.
2180 //
2181 // Instructions specify two basic values for encoding. Again, a function
2182 // is available to check if the constant displacement is an oop. They use the
2183 // ins_encode keyword to specify their encoding classes (which must be
2184 // a sequence of enc_class names, and their parameters, specified in
2185 // the encoding block), and they use the
2186 // opcode keyword to specify, in order, their primary, secondary, and
2187 // tertiary opcode. Only the opcode sections which a particular instruction
2188 // needs for encoding need to be specified.
2189 encode %{
2190 enc_class enc_untested %{
2191 #ifdef ASSERT
2192 MacroAssembler _masm(&cbuf);
2193 __ untested("encoding");
2194 #endif
2195 %}
2196
2197 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2198 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2199 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2200 %}
2201
2202 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2203 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2204 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2205 %}
2206
2207 enc_class form3_mem_prefetch_read( memory mem ) %{
2208 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2209 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2210 %}
2211
2212 enc_class form3_mem_prefetch_write( memory mem ) %{
2213 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2214 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2215 %}
2216
2217 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2218 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2219 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2220 guarantee($mem$$index == R_G0_enc, "double index?");
2221 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2222 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2223 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2224 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2225 %}
2226
2227 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2228 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2229 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2230 guarantee($mem$$index == R_G0_enc, "double index?");
2231 // Load long with 2 instructions
2232 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2233 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2234 %}
2235
2236 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2237 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2238 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2239 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2240 %}
2241
2242 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2243 // Encode a reg-reg copy. If it is useless, then empty encoding.
2244 if( $rs2$$reg != $rd$$reg )
2245 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2246 %}
2247
2248 // Target lo half of long
2249 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2250 // Encode a reg-reg copy. If it is useless, then empty encoding.
2251 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2252 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2253 %}
2254
2255 // Source lo half of long
2256 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2257 // Encode a reg-reg copy. If it is useless, then empty encoding.
2258 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2259 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2260 %}
2261
2262 // Target hi half of long
2263 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2264 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2265 %}
2266
2267 // Source lo half of long, and leave it sign extended.
2268 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2269 // Sign extend low half
2270 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2271 %}
2272
2273 // Source hi half of long, and leave it sign extended.
2274 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2275 // Shift high half to low half
2276 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2277 %}
2278
2279 // Source hi half of long
2280 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2281 // Encode a reg-reg copy. If it is useless, then empty encoding.
2282 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2283 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2284 %}
2285
2286 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2287 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2288 %}
2289
2290 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2291 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2292 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2293 %}
2294
2295 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2296 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2297 // clear if nothing else is happening
2298 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2299 // blt,a,pn done
2300 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2301 // mov dst,-1 in delay slot
2302 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2303 %}
2304
2305 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2306 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2307 %}
2308
2309 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2310 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2311 %}
2312
2313 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2314 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2315 %}
2316
2317 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2318 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2319 %}
2320
2321 enc_class move_return_pc_to_o1() %{
2322 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2323 %}
2324
2325 #ifdef _LP64
2326 /* %%% merge with enc_to_bool */
2327 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2328 MacroAssembler _masm(&cbuf);
2329
2330 Register src_reg = reg_to_register_object($src$$reg);
2331 Register dst_reg = reg_to_register_object($dst$$reg);
2332 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2333 %}
2334 #endif
2335
2336 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2337 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2338 MacroAssembler _masm(&cbuf);
2339
2340 Register p_reg = reg_to_register_object($p$$reg);
2341 Register q_reg = reg_to_register_object($q$$reg);
2342 Register y_reg = reg_to_register_object($y$$reg);
2343 Register tmp_reg = reg_to_register_object($tmp$$reg);
2344
2345 __ subcc( p_reg, q_reg, p_reg );
2346 __ add ( p_reg, y_reg, tmp_reg );
2347 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2348 %}
2349
2350 enc_class form_d2i_helper(regD src, regF dst) %{
2351 // fcmp %fcc0,$src,$src
2352 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2353 // branch %fcc0 not-nan, predict taken
2354 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2355 // fdtoi $src,$dst
2356 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2357 // fitos $dst,$dst (if nan)
2358 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2359 // clear $dst (if nan)
2360 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2361 // carry on here...
2362 %}
2363
2364 enc_class form_d2l_helper(regD src, regD dst) %{
2365 // fcmp %fcc0,$src,$src check for NAN
2366 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2367 // branch %fcc0 not-nan, predict taken
2368 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2369 // fdtox $src,$dst convert in delay slot
2370 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2371 // fxtod $dst,$dst (if nan)
2372 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2373 // clear $dst (if nan)
2374 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2375 // carry on here...
2376 %}
2377
2378 enc_class form_f2i_helper(regF src, regF dst) %{
2379 // fcmps %fcc0,$src,$src
2380 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2381 // branch %fcc0 not-nan, predict taken
2382 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2383 // fstoi $src,$dst
2384 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2385 // fitos $dst,$dst (if nan)
2386 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2387 // clear $dst (if nan)
2388 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2389 // carry on here...
2390 %}
2391
2392 enc_class form_f2l_helper(regF src, regD dst) %{
2393 // fcmps %fcc0,$src,$src
2394 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2395 // branch %fcc0 not-nan, predict taken
2396 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2397 // fstox $src,$dst
2398 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2399 // fxtod $dst,$dst (if nan)
2400 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2401 // clear $dst (if nan)
2402 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2403 // carry on here...
2404 %}
2405
2406 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2407 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2408 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2409 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2410
2411 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2412
2413 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2414 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2415
2416 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2417 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2418 %}
2419
2420 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2421 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2422 %}
2423
2424 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2425 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2426 %}
2427
2428 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2429 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2430 %}
2431
2432 enc_class form3_convI2F(regF rs2, regF rd) %{
2433 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2434 %}
2435
2436 // Encloding class for traceable jumps
2437 enc_class form_jmpl(g3RegP dest) %{
2438 emit_jmpl(cbuf, $dest$$reg);
2439 %}
2440
2441 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2442 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2443 %}
2444
2445 enc_class form2_nop() %{
2446 emit_nop(cbuf);
2447 %}
2448
2449 enc_class form2_illtrap() %{
2450 emit_illtrap(cbuf);
2451 %}
2452
2453
2454 // Compare longs and convert into -1, 0, 1.
2455 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2456 // CMP $src1,$src2
2457 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2458 // blt,a,pn done
2459 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2460 // mov dst,-1 in delay slot
2461 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2462 // bgt,a,pn done
2463 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2464 // mov dst,1 in delay slot
2465 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2466 // CLR $dst
2467 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2468 %}
2469
2470 enc_class enc_PartialSubtypeCheck() %{
2471 MacroAssembler _masm(&cbuf);
2472 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2473 __ delayed()->nop();
2474 %}
2475
2476 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2477 MacroAssembler _masm(&cbuf);
2478 Label* L = $labl$$label;
2479 Assembler::Predict predict_taken =
2480 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2481
2482 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2483 __ delayed()->nop();
2484 %}
2485
2486 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2487 MacroAssembler _masm(&cbuf);
2488 Label* L = $labl$$label;
2489 Assembler::Predict predict_taken =
2490 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2491
2492 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2493 __ delayed()->nop();
2494 %}
2495
2496 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2497 int op = (Assembler::arith_op << 30) |
2498 ($dst$$reg << 25) |
2499 (Assembler::movcc_op3 << 19) |
2500 (1 << 18) | // cc2 bit for 'icc'
2501 ($cmp$$cmpcode << 14) |
2502 (0 << 13) | // select register move
2503 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2504 ($src$$reg << 0);
2505 cbuf.insts()->emit_int32(op);
2506 %}
2507
2508 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2509 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2510 int op = (Assembler::arith_op << 30) |
2511 ($dst$$reg << 25) |
2512 (Assembler::movcc_op3 << 19) |
2513 (1 << 18) | // cc2 bit for 'icc'
2514 ($cmp$$cmpcode << 14) |
2515 (1 << 13) | // select immediate move
2516 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2517 (simm11 << 0);
2518 cbuf.insts()->emit_int32(op);
2519 %}
2520
2521 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2522 int op = (Assembler::arith_op << 30) |
2523 ($dst$$reg << 25) |
2524 (Assembler::movcc_op3 << 19) |
2525 (0 << 18) | // cc2 bit for 'fccX'
2526 ($cmp$$cmpcode << 14) |
2527 (0 << 13) | // select register move
2528 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2529 ($src$$reg << 0);
2530 cbuf.insts()->emit_int32(op);
2531 %}
2532
2533 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2534 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2535 int op = (Assembler::arith_op << 30) |
2536 ($dst$$reg << 25) |
2537 (Assembler::movcc_op3 << 19) |
2538 (0 << 18) | // cc2 bit for 'fccX'
2539 ($cmp$$cmpcode << 14) |
2540 (1 << 13) | // select immediate move
2541 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2542 (simm11 << 0);
2543 cbuf.insts()->emit_int32(op);
2544 %}
2545
2546 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2547 int op = (Assembler::arith_op << 30) |
2548 ($dst$$reg << 25) |
2549 (Assembler::fpop2_op3 << 19) |
2550 (0 << 18) |
2551 ($cmp$$cmpcode << 14) |
2552 (1 << 13) | // select register move
2553 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2554 ($primary << 5) | // select single, double or quad
2555 ($src$$reg << 0);
2556 cbuf.insts()->emit_int32(op);
2557 %}
2558
2559 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2560 int op = (Assembler::arith_op << 30) |
2561 ($dst$$reg << 25) |
2562 (Assembler::fpop2_op3 << 19) |
2563 (0 << 18) |
2564 ($cmp$$cmpcode << 14) |
2565 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2566 ($primary << 5) | // select single, double or quad
2567 ($src$$reg << 0);
2568 cbuf.insts()->emit_int32(op);
2569 %}
2570
2571 // Used by the MIN/MAX encodings. Same as a CMOV, but
2572 // the condition comes from opcode-field instead of an argument.
2573 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2574 int op = (Assembler::arith_op << 30) |
2575 ($dst$$reg << 25) |
2576 (Assembler::movcc_op3 << 19) |
2577 (1 << 18) | // cc2 bit for 'icc'
2578 ($primary << 14) |
2579 (0 << 13) | // select register move
2580 (0 << 11) | // cc1, cc0 bits for 'icc'
2581 ($src$$reg << 0);
2582 cbuf.insts()->emit_int32(op);
2583 %}
2584
2585 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2586 int op = (Assembler::arith_op << 30) |
2587 ($dst$$reg << 25) |
2588 (Assembler::movcc_op3 << 19) |
2589 (6 << 16) | // cc2 bit for 'xcc'
2590 ($primary << 14) |
2591 (0 << 13) | // select register move
2592 (0 << 11) | // cc1, cc0 bits for 'icc'
2593 ($src$$reg << 0);
2594 cbuf.insts()->emit_int32(op);
2595 %}
2596
2597 enc_class Set13( immI13 src, iRegI rd ) %{
2598 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2599 %}
2600
2601 enc_class SetHi22( immI src, iRegI rd ) %{
2602 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2603 %}
2604
2605 enc_class Set32( immI src, iRegI rd ) %{
2606 MacroAssembler _masm(&cbuf);
2607 __ set($src$$constant, reg_to_register_object($rd$$reg));
2608 %}
2609
2610 enc_class call_epilog %{
2611 if( VerifyStackAtCalls ) {
2612 MacroAssembler _masm(&cbuf);
2613 int framesize = ra_->C->frame_size_in_bytes();
2614 Register temp_reg = G3;
2615 __ add(SP, framesize, temp_reg);
2616 __ cmp(temp_reg, FP);
2617 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2618 }
2619 %}
2620
2621 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2622 // to G1 so the register allocator will not have to deal with the misaligned register
2623 // pair.
2624 enc_class adjust_long_from_native_call %{
2625 #ifndef _LP64
2626 if (returns_long()) {
2627 // sllx O0,32,O0
2628 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2629 // srl O1,0,O1
2630 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2631 // or O0,O1,G1
2632 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2633 }
2634 #endif
2635 %}
2636
2637 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2638 // CALL directly to the runtime
2639 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2640 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2641 %}
2642
2643 enc_class preserve_SP %{
2644 MacroAssembler _masm(&cbuf);
2645 __ mov(SP, L7_mh_SP_save);
2646 %}
2647
2648 enc_class restore_SP %{
2649 MacroAssembler _masm(&cbuf);
2650 __ mov(L7_mh_SP_save, SP);
2651 %}
2652
2653 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2654 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2655 // who we intended to call.
2656 if (!_method) {
2657 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2658 } else {
2659 int method_index = resolved_method_index(cbuf);
2660 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2661 : static_call_Relocation::spec(method_index);
2662 emit_call_reloc(cbuf, $meth$$method, rspec);
2663
2664 // Emit stub for static call.
2665 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2666 // Stub does not fit into scratch buffer if TraceJumps is enabled
2667 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2668 ciEnv::current()->record_failure("CodeCache is full");
2669 return;
2670 }
2671 }
2672 %}
2673
2674 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2675 MacroAssembler _masm(&cbuf);
2676 __ set_inst_mark();
2677 int vtable_index = this->_vtable_index;
2678 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2679 if (vtable_index < 0) {
2680 // must be invalid_vtable_index, not nonvirtual_vtable_index
2681 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2682 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2683 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2684 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2685 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2686 } else {
2687 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2688 // Just go thru the vtable
2689 // get receiver klass (receiver already checked for non-null)
2690 // If we end up going thru a c2i adapter interpreter expects method in G5
2691 int off = __ offset();
2692 __ load_klass(O0, G3_scratch);
2693 int klass_load_size;
2694 if (UseCompressedClassPointers) {
2695 assert(Universe::heap() != NULL, "java heap should be initialized");
2696 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2697 } else {
2698 klass_load_size = 1*BytesPerInstWord;
2699 }
2700 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2701 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2702 if (Assembler::is_simm13(v_off)) {
2703 __ ld_ptr(G3, v_off, G5_method);
2704 } else {
2705 // Generate 2 instructions
2706 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2707 __ or3(G5_method, v_off & 0x3ff, G5_method);
2708 // ld_ptr, set_hi, set
2709 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2710 "Unexpected instruction size(s)");
2711 __ ld_ptr(G3, G5_method, G5_method);
2712 }
2713 // NOTE: for vtable dispatches, the vtable entry will never be null.
2714 // However it may very well end up in handle_wrong_method if the
2715 // method is abstract for the particular class.
2716 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2717 // jump to target (either compiled code or c2iadapter)
2718 __ jmpl(G3_scratch, G0, O7);
2719 __ delayed()->nop();
2720 }
2721 %}
2722
2723 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2724 MacroAssembler _masm(&cbuf);
2725
2726 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2727 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2728 // we might be calling a C2I adapter which needs it.
2729
2730 assert(temp_reg != G5_ic_reg, "conflicting registers");
2731 // Load nmethod
2732 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2733
2734 // CALL to compiled java, indirect the contents of G3
2735 __ set_inst_mark();
2736 __ callr(temp_reg, G0);
2737 __ delayed()->nop();
2738 %}
2739
2740 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2741 MacroAssembler _masm(&cbuf);
2742 Register Rdividend = reg_to_register_object($src1$$reg);
2743 Register Rdivisor = reg_to_register_object($src2$$reg);
2744 Register Rresult = reg_to_register_object($dst$$reg);
2745
2746 __ sra(Rdivisor, 0, Rdivisor);
2747 __ sra(Rdividend, 0, Rdividend);
2748 __ sdivx(Rdividend, Rdivisor, Rresult);
2749 %}
2750
2751 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2752 MacroAssembler _masm(&cbuf);
2753
2754 Register Rdividend = reg_to_register_object($src1$$reg);
2755 int divisor = $imm$$constant;
2756 Register Rresult = reg_to_register_object($dst$$reg);
2757
2758 __ sra(Rdividend, 0, Rdividend);
2759 __ sdivx(Rdividend, divisor, Rresult);
2760 %}
2761
2762 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2763 MacroAssembler _masm(&cbuf);
2764 Register Rsrc1 = reg_to_register_object($src1$$reg);
2765 Register Rsrc2 = reg_to_register_object($src2$$reg);
2766 Register Rdst = reg_to_register_object($dst$$reg);
2767
2768 __ sra( Rsrc1, 0, Rsrc1 );
2769 __ sra( Rsrc2, 0, Rsrc2 );
2770 __ mulx( Rsrc1, Rsrc2, Rdst );
2771 __ srlx( Rdst, 32, Rdst );
2772 %}
2773
2774 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2775 MacroAssembler _masm(&cbuf);
2776 Register Rdividend = reg_to_register_object($src1$$reg);
2777 Register Rdivisor = reg_to_register_object($src2$$reg);
2778 Register Rresult = reg_to_register_object($dst$$reg);
2779 Register Rscratch = reg_to_register_object($scratch$$reg);
2780
2781 assert(Rdividend != Rscratch, "");
2782 assert(Rdivisor != Rscratch, "");
2783
2784 __ sra(Rdividend, 0, Rdividend);
2785 __ sra(Rdivisor, 0, Rdivisor);
2786 __ sdivx(Rdividend, Rdivisor, Rscratch);
2787 __ mulx(Rscratch, Rdivisor, Rscratch);
2788 __ sub(Rdividend, Rscratch, Rresult);
2789 %}
2790
2791 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2792 MacroAssembler _masm(&cbuf);
2793
2794 Register Rdividend = reg_to_register_object($src1$$reg);
2795 int divisor = $imm$$constant;
2796 Register Rresult = reg_to_register_object($dst$$reg);
2797 Register Rscratch = reg_to_register_object($scratch$$reg);
2798
2799 assert(Rdividend != Rscratch, "");
2800
2801 __ sra(Rdividend, 0, Rdividend);
2802 __ sdivx(Rdividend, divisor, Rscratch);
2803 __ mulx(Rscratch, divisor, Rscratch);
2804 __ sub(Rdividend, Rscratch, Rresult);
2805 %}
2806
2807 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2808 MacroAssembler _masm(&cbuf);
2809
2810 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2811 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2812
2813 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2814 %}
2815
2816 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2817 MacroAssembler _masm(&cbuf);
2818
2819 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2820 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2821
2822 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2823 %}
2824
2825 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2826 MacroAssembler _masm(&cbuf);
2827
2828 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2829 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2830
2831 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2832 %}
2833
2834 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2835 MacroAssembler _masm(&cbuf);
2836
2837 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2838 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2839
2840 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2841 %}
2842
2843 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2844 MacroAssembler _masm(&cbuf);
2845
2846 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2847 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2848
2849 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2850 %}
2851
2852 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2853 MacroAssembler _masm(&cbuf);
2854
2855 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2856 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2857
2858 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2859 %}
2860
2861 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2862 MacroAssembler _masm(&cbuf);
2863
2864 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2865 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2866
2867 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2868 %}
2869
2870 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2871 MacroAssembler _masm(&cbuf);
2872
2873 Register Roop = reg_to_register_object($oop$$reg);
2874 Register Rbox = reg_to_register_object($box$$reg);
2875 Register Rscratch = reg_to_register_object($scratch$$reg);
2876 Register Rmark = reg_to_register_object($scratch2$$reg);
2877
2878 assert(Roop != Rscratch, "");
2879 assert(Roop != Rmark, "");
2880 assert(Rbox != Rscratch, "");
2881 assert(Rbox != Rmark, "");
2882
2883 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2884 %}
2885
2886 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2887 MacroAssembler _masm(&cbuf);
2888
2889 Register Roop = reg_to_register_object($oop$$reg);
2890 Register Rbox = reg_to_register_object($box$$reg);
2891 Register Rscratch = reg_to_register_object($scratch$$reg);
2892 Register Rmark = reg_to_register_object($scratch2$$reg);
2893
2894 assert(Roop != Rscratch, "");
2895 assert(Roop != Rmark, "");
2896 assert(Rbox != Rscratch, "");
2897 assert(Rbox != Rmark, "");
2898
2899 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2900 %}
2901
2902 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2903 MacroAssembler _masm(&cbuf);
2904 Register Rmem = reg_to_register_object($mem$$reg);
2905 Register Rold = reg_to_register_object($old$$reg);
2906 Register Rnew = reg_to_register_object($new$$reg);
2907
2908 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2909 __ cmp( Rold, Rnew );
2910 %}
2911
2912 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2913 Register Rmem = reg_to_register_object($mem$$reg);
2914 Register Rold = reg_to_register_object($old$$reg);
2915 Register Rnew = reg_to_register_object($new$$reg);
2916
2917 MacroAssembler _masm(&cbuf);
2918 __ mov(Rnew, O7);
2919 __ casx(Rmem, Rold, O7);
2920 __ cmp( Rold, O7 );
2921 %}
2922
2923 // raw int cas, used for compareAndSwap
2924 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2925 Register Rmem = reg_to_register_object($mem$$reg);
2926 Register Rold = reg_to_register_object($old$$reg);
2927 Register Rnew = reg_to_register_object($new$$reg);
2928
2929 MacroAssembler _masm(&cbuf);
2930 __ mov(Rnew, O7);
2931 __ cas(Rmem, Rold, O7);
2932 __ cmp( Rold, O7 );
2933 %}
2934
2935 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2936 Register Rres = reg_to_register_object($res$$reg);
2937
2938 MacroAssembler _masm(&cbuf);
2939 __ mov(1, Rres);
2940 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2941 %}
2942
2943 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2944 Register Rres = reg_to_register_object($res$$reg);
2945
2946 MacroAssembler _masm(&cbuf);
2947 __ mov(1, Rres);
2948 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2949 %}
2950
2951 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2952 MacroAssembler _masm(&cbuf);
2953 Register Rdst = reg_to_register_object($dst$$reg);
2954 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2955 : reg_to_DoubleFloatRegister_object($src1$$reg);
2956 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2957 : reg_to_DoubleFloatRegister_object($src2$$reg);
2958
2959 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2960 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2961 %}
2962
2963 enc_class enc_rethrow() %{
2964 cbuf.set_insts_mark();
2965 Register temp_reg = G3;
2966 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2967 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2968 MacroAssembler _masm(&cbuf);
2969 #ifdef ASSERT
2970 __ save_frame(0);
2971 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2972 __ sethi(last_rethrow_addrlit, L1);
2973 Address addr(L1, last_rethrow_addrlit.low10());
2974 __ rdpc(L2);
2975 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2976 __ st_ptr(L2, addr);
2977 __ restore();
2978 #endif
2979 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2980 __ delayed()->nop();
2981 %}
2982
2983 enc_class emit_mem_nop() %{
2984 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2985 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2986 %}
2987
2988 enc_class emit_fadd_nop() %{
2989 // Generates the instruction FMOVS f31,f31
2990 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2991 %}
2992
2993 enc_class emit_br_nop() %{
2994 // Generates the instruction BPN,PN .
2995 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2996 %}
2997
2998 enc_class enc_membar_acquire %{
2999 MacroAssembler _masm(&cbuf);
3000 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3001 %}
3002
3003 enc_class enc_membar_release %{
3004 MacroAssembler _masm(&cbuf);
3005 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3006 %}
3007
3008 enc_class enc_membar_volatile %{
3009 MacroAssembler _masm(&cbuf);
3010 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3011 %}
3012
3013 %}
3014
3015 //----------FRAME--------------------------------------------------------------
3016 // Definition of frame structure and management information.
3017 //
3018 // S T A C K L A Y O U T Allocators stack-slot number
3019 // | (to get allocators register number
3020 // G Owned by | | v add VMRegImpl::stack0)
3021 // r CALLER | |
3022 // o | +--------+ pad to even-align allocators stack-slot
3023 // w V | pad0 | numbers; owned by CALLER
3024 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3025 // h ^ | in | 5
3026 // | | args | 4 Holes in incoming args owned by SELF
3027 // | | | | 3
3028 // | | +--------+
3029 // V | | old out| Empty on Intel, window on Sparc
3030 // | old |preserve| Must be even aligned.
3031 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3032 // | | in | 3 area for Intel ret address
3033 // Owned by |preserve| Empty on Sparc.
3034 // SELF +--------+
3035 // | | pad2 | 2 pad to align old SP
3036 // | +--------+ 1
3037 // | | locks | 0
3038 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3039 // | | pad1 | 11 pad to align new SP
3040 // | +--------+
3041 // | | | 10
3042 // | | spills | 9 spills
3043 // V | | 8 (pad0 slot for callee)
3044 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3045 // ^ | out | 7
3046 // | | args | 6 Holes in outgoing args owned by CALLEE
3047 // Owned by +--------+
3048 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3049 // | new |preserve| Must be even-aligned.
3050 // | SP-+--------+----> Matcher::_new_SP, even aligned
3051 // | | |
3052 //
3053 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3054 // known from SELF's arguments and the Java calling convention.
3055 // Region 6-7 is determined per call site.
3056 // Note 2: If the calling convention leaves holes in the incoming argument
3057 // area, those holes are owned by SELF. Holes in the outgoing area
3058 // are owned by the CALLEE. Holes should not be nessecary in the
3059 // incoming area, as the Java calling convention is completely under
3060 // the control of the AD file. Doubles can be sorted and packed to
3061 // avoid holes. Holes in the outgoing arguments may be necessary for
3062 // varargs C calling conventions.
3063 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3064 // even aligned with pad0 as needed.
3065 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3066 // region 6-11 is even aligned; it may be padded out more so that
3067 // the region from SP to FP meets the minimum stack alignment.
3068
3069 frame %{
3070 // What direction does stack grow in (assumed to be same for native & Java)
3071 stack_direction(TOWARDS_LOW);
3072
3073 // These two registers define part of the calling convention
3074 // between compiled code and the interpreter.
3075 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3076 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3077
3078 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3079 cisc_spilling_operand_name(indOffset);
3080
3081 // Number of stack slots consumed by a Monitor enter
3082 #ifdef _LP64
3083 sync_stack_slots(2);
3084 #else
3085 sync_stack_slots(1);
3086 #endif
3087
3088 // Compiled code's Frame Pointer
3089 frame_pointer(R_SP);
3090
3091 // Stack alignment requirement
3092 stack_alignment(StackAlignmentInBytes);
3093 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3094 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3095
3096 // Number of stack slots between incoming argument block and the start of
3097 // a new frame. The PROLOG must add this many slots to the stack. The
3098 // EPILOG must remove this many slots.
3099 in_preserve_stack_slots(0);
3100
3101 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3102 // for calls to C. Supports the var-args backing area for register parms.
3103 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3104 #ifdef _LP64
3105 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3106 varargs_C_out_slots_killed(12);
3107 #else
3108 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3109 varargs_C_out_slots_killed( 7);
3110 #endif
3111
3112 // The after-PROLOG location of the return address. Location of
3113 // return address specifies a type (REG or STACK) and a number
3114 // representing the register number (i.e. - use a register name) or
3115 // stack slot.
3116 return_addr(REG R_I7); // Ret Addr is in register I7
3117
3118 // Body of function which returns an OptoRegs array locating
3119 // arguments either in registers or in stack slots for calling
3120 // java
3121 calling_convention %{
3122 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3123
3124 %}
3125
3126 // Body of function which returns an OptoRegs array locating
3127 // arguments either in registers or in stack slots for calling
3128 // C.
3129 c_calling_convention %{
3130 // This is obviously always outgoing
3131 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3132 %}
3133
3134 // Location of native (C/C++) and interpreter return values. This is specified to
3135 // be the same as Java. In the 32-bit VM, long values are actually returned from
3136 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3137 // to and from the register pairs is done by the appropriate call and epilog
3138 // opcodes. This simplifies the register allocator.
3139 c_return_value %{
3140 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3141 #ifdef _LP64
3142 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3143 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3144 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3145 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3146 #else // !_LP64
3147 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3148 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3149 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3150 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3151 #endif
3152 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3153 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3154 %}
3155
3156 // Location of compiled Java return values. Same as C
3157 return_value %{
3158 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3159 #ifdef _LP64
3160 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3161 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3162 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3163 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3164 #else // !_LP64
3165 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3166 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3167 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3168 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3169 #endif
3170 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3171 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3172 %}
3173
3174 %}
3175
3176
3177 //----------ATTRIBUTES---------------------------------------------------------
3178 //----------Operand Attributes-------------------------------------------------
3179 op_attrib op_cost(1); // Required cost attribute
3180
3181 //----------Instruction Attributes---------------------------------------------
3182 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3183 ins_attrib ins_size(32); // Required size attribute (in bits)
3184
3185 // avoid_back_to_back attribute is an expression that must return
3186 // one of the following values defined in MachNode:
3187 // AVOID_NONE - instruction can be placed anywhere
3188 // AVOID_BEFORE - instruction cannot be placed after an
3189 // instruction with MachNode::AVOID_AFTER
3190 // AVOID_AFTER - the next instruction cannot be the one
3191 // with MachNode::AVOID_BEFORE
3192 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3193 // the same time
3194 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3195
3196 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3197 // non-matching short branch variant of some
3198 // long branch?
3199
3200 //----------OPERANDS-----------------------------------------------------------
3201 // Operand definitions must precede instruction definitions for correct parsing
3202 // in the ADLC because operands constitute user defined types which are used in
3203 // instruction definitions.
3204
3205 //----------Simple Operands----------------------------------------------------
3206 // Immediate Operands
3207 // Integer Immediate: 32-bit
3208 operand immI() %{
3209 match(ConI);
3210
3211 op_cost(0);
3212 // formats are generated automatically for constants and base registers
3213 format %{ %}
3214 interface(CONST_INTER);
3215 %}
3216
3217 // Integer Immediate: 0-bit
3218 operand immI0() %{
3219 predicate(n->get_int() == 0);
3220 match(ConI);
3221 op_cost(0);
3222
3223 format %{ %}
3224 interface(CONST_INTER);
3225 %}
3226
3227 // Integer Immediate: 5-bit
3228 operand immI5() %{
3229 predicate(Assembler::is_simm5(n->get_int()));
3230 match(ConI);
3231 op_cost(0);
3232 format %{ %}
3233 interface(CONST_INTER);
3234 %}
3235
3236 // Integer Immediate: 8-bit
3237 operand immI8() %{
3238 predicate(Assembler::is_simm8(n->get_int()));
3239 match(ConI);
3240 op_cost(0);
3241 format %{ %}
3242 interface(CONST_INTER);
3243 %}
3244
3245 // Integer Immediate: the value 10
3246 operand immI10() %{
3247 predicate(n->get_int() == 10);
3248 match(ConI);
3249 op_cost(0);
3250
3251 format %{ %}
3252 interface(CONST_INTER);
3253 %}
3254
3255 // Integer Immediate: 11-bit
3256 operand immI11() %{
3257 predicate(Assembler::is_simm11(n->get_int()));
3258 match(ConI);
3259 op_cost(0);
3260 format %{ %}
3261 interface(CONST_INTER);
3262 %}
3263
3264 // Integer Immediate: 13-bit
3265 operand immI13() %{
3266 predicate(Assembler::is_simm13(n->get_int()));
3267 match(ConI);
3268 op_cost(0);
3269
3270 format %{ %}
3271 interface(CONST_INTER);
3272 %}
3273
3274 // Integer Immediate: 13-bit minus 7
3275 operand immI13m7() %{
3276 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3277 match(ConI);
3278 op_cost(0);
3279
3280 format %{ %}
3281 interface(CONST_INTER);
3282 %}
3283
3284 // Integer Immediate: 16-bit
3285 operand immI16() %{
3286 predicate(Assembler::is_simm16(n->get_int()));
3287 match(ConI);
3288 op_cost(0);
3289 format %{ %}
3290 interface(CONST_INTER);
3291 %}
3292
3293 // Integer Immediate: the values 1-31
3294 operand immI_1_31() %{
3295 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3296 match(ConI);
3297 op_cost(0);
3298
3299 format %{ %}
3300 interface(CONST_INTER);
3301 %}
3302
3303 // Integer Immediate: the values 32-63
3304 operand immI_32_63() %{
3305 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3306 match(ConI);
3307 op_cost(0);
3308
3309 format %{ %}
3310 interface(CONST_INTER);
3311 %}
3312
3313 // Immediates for special shifts (sign extend)
3314
3315 // Integer Immediate: the value 16
3316 operand immI_16() %{
3317 predicate(n->get_int() == 16);
3318 match(ConI);
3319 op_cost(0);
3320
3321 format %{ %}
3322 interface(CONST_INTER);
3323 %}
3324
3325 // Integer Immediate: the value 24
3326 operand immI_24() %{
3327 predicate(n->get_int() == 24);
3328 match(ConI);
3329 op_cost(0);
3330
3331 format %{ %}
3332 interface(CONST_INTER);
3333 %}
3334 // Integer Immediate: the value 255
3335 operand immI_255() %{
3336 predicate( n->get_int() == 255 );
3337 match(ConI);
3338 op_cost(0);
3339
3340 format %{ %}
3341 interface(CONST_INTER);
3342 %}
3343
3344 // Integer Immediate: the value 65535
3345 operand immI_65535() %{
3346 predicate(n->get_int() == 65535);
3347 match(ConI);
3348 op_cost(0);
3349
3350 format %{ %}
3351 interface(CONST_INTER);
3352 %}
3353
3354 // Integer Immediate: the values 0-31
3355 operand immU5() %{
3356 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3357 match(ConI);
3358 op_cost(0);
3359
3360 format %{ %}
3361 interface(CONST_INTER);
3362 %}
3363
3364 // Integer Immediate: 6-bit
3365 operand immU6() %{
3366 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3367 match(ConI);
3368 op_cost(0);
3369 format %{ %}
3370 interface(CONST_INTER);
3371 %}
3372
3373 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3374 operand immU12() %{
3375 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3376 match(ConI);
3377 op_cost(0);
3378
3379 format %{ %}
3380 interface(CONST_INTER);
3381 %}
3382
3383 // Integer Immediate non-negative
3384 operand immU31()
3385 %{
3386 predicate(n->get_int() >= 0);
3387 match(ConI);
3388
3389 op_cost(0);
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3393
3394 // Long Immediate: the value FF
3395 operand immL_FF() %{
3396 predicate( n->get_long() == 0xFFL );
3397 match(ConL);
3398 op_cost(0);
3399
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403
3404 // Long Immediate: the value FFFF
3405 operand immL_FFFF() %{
3406 predicate( n->get_long() == 0xFFFFL );
3407 match(ConL);
3408 op_cost(0);
3409
3410 format %{ %}
3411 interface(CONST_INTER);
3412 %}
3413
3414 // Pointer Immediate: 32 or 64-bit
3415 operand immP() %{
3416 match(ConP);
3417
3418 op_cost(5);
3419 // formats are generated automatically for constants and base registers
3420 format %{ %}
3421 interface(CONST_INTER);
3422 %}
3423
3424 #ifdef _LP64
3425 // Pointer Immediate: 64-bit
3426 operand immP_set() %{
3427 predicate(!VM_Version::is_niagara_plus());
3428 match(ConP);
3429
3430 op_cost(5);
3431 // formats are generated automatically for constants and base registers
3432 format %{ %}
3433 interface(CONST_INTER);
3434 %}
3435
3436 // Pointer Immediate: 64-bit
3437 // From Niagara2 processors on a load should be better than materializing.
3438 operand immP_load() %{
3439 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3440 match(ConP);
3441
3442 op_cost(5);
3443 // formats are generated automatically for constants and base registers
3444 format %{ %}
3445 interface(CONST_INTER);
3446 %}
3447
3448 // Pointer Immediate: 64-bit
3449 operand immP_no_oop_cheap() %{
3450 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3451 match(ConP);
3452
3453 op_cost(5);
3454 // formats are generated automatically for constants and base registers
3455 format %{ %}
3456 interface(CONST_INTER);
3457 %}
3458 #endif
3459
3460 operand immP13() %{
3461 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3462 match(ConP);
3463 op_cost(0);
3464
3465 format %{ %}
3466 interface(CONST_INTER);
3467 %}
3468
3469 operand immP0() %{
3470 predicate(n->get_ptr() == 0);
3471 match(ConP);
3472 op_cost(0);
3473
3474 format %{ %}
3475 interface(CONST_INTER);
3476 %}
3477
3478 operand immP_poll() %{
3479 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3480 match(ConP);
3481
3482 // formats are generated automatically for constants and base registers
3483 format %{ %}
3484 interface(CONST_INTER);
3485 %}
3486
3487 // Pointer Immediate
3488 operand immN()
3489 %{
3490 match(ConN);
3491
3492 op_cost(10);
3493 format %{ %}
3494 interface(CONST_INTER);
3495 %}
3496
3497 operand immNKlass()
3498 %{
3499 match(ConNKlass);
3500
3501 op_cost(10);
3502 format %{ %}
3503 interface(CONST_INTER);
3504 %}
3505
3506 // NULL Pointer Immediate
3507 operand immN0()
3508 %{
3509 predicate(n->get_narrowcon() == 0);
3510 match(ConN);
3511
3512 op_cost(0);
3513 format %{ %}
3514 interface(CONST_INTER);
3515 %}
3516
3517 operand immL() %{
3518 match(ConL);
3519 op_cost(40);
3520 // formats are generated automatically for constants and base registers
3521 format %{ %}
3522 interface(CONST_INTER);
3523 %}
3524
3525 operand immL0() %{
3526 predicate(n->get_long() == 0L);
3527 match(ConL);
3528 op_cost(0);
3529 // formats are generated automatically for constants and base registers
3530 format %{ %}
3531 interface(CONST_INTER);
3532 %}
3533
3534 // Integer Immediate: 5-bit
3535 operand immL5() %{
3536 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3537 match(ConL);
3538 op_cost(0);
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3542
3543 // Long Immediate: 13-bit
3544 operand immL13() %{
3545 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3546 match(ConL);
3547 op_cost(0);
3548
3549 format %{ %}
3550 interface(CONST_INTER);
3551 %}
3552
3553 // Long Immediate: 13-bit minus 7
3554 operand immL13m7() %{
3555 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3556 match(ConL);
3557 op_cost(0);
3558
3559 format %{ %}
3560 interface(CONST_INTER);
3561 %}
3562
3563 // Long Immediate: low 32-bit mask
3564 operand immL_32bits() %{
3565 predicate(n->get_long() == 0xFFFFFFFFL);
3566 match(ConL);
3567 op_cost(0);
3568
3569 format %{ %}
3570 interface(CONST_INTER);
3571 %}
3572
3573 // Long Immediate: cheap (materialize in <= 3 instructions)
3574 operand immL_cheap() %{
3575 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3576 match(ConL);
3577 op_cost(0);
3578
3579 format %{ %}
3580 interface(CONST_INTER);
3581 %}
3582
3583 // Long Immediate: expensive (materialize in > 3 instructions)
3584 operand immL_expensive() %{
3585 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3586 match(ConL);
3587 op_cost(0);
3588
3589 format %{ %}
3590 interface(CONST_INTER);
3591 %}
3592
3593 // Double Immediate
3594 operand immD() %{
3595 match(ConD);
3596
3597 op_cost(40);
3598 format %{ %}
3599 interface(CONST_INTER);
3600 %}
3601
3602 // Double Immediate: +0.0d
3603 operand immD0() %{
3604 predicate(jlong_cast(n->getd()) == 0);
3605 match(ConD);
3606
3607 op_cost(0);
3608 format %{ %}
3609 interface(CONST_INTER);
3610 %}
3611
3612 // Float Immediate
3613 operand immF() %{
3614 match(ConF);
3615
3616 op_cost(20);
3617 format %{ %}
3618 interface(CONST_INTER);
3619 %}
3620
3621 // Float Immediate: +0.0f
3622 operand immF0() %{
3623 predicate(jint_cast(n->getf()) == 0);
3624 match(ConF);
3625
3626 op_cost(0);
3627 format %{ %}
3628 interface(CONST_INTER);
3629 %}
3630
3631 // Integer Register Operands
3632 // Integer Register
3633 operand iRegI() %{
3634 constraint(ALLOC_IN_RC(int_reg));
3635 match(RegI);
3636
3637 match(notemp_iRegI);
3638 match(g1RegI);
3639 match(o0RegI);
3640 match(iRegIsafe);
3641
3642 format %{ %}
3643 interface(REG_INTER);
3644 %}
3645
3646 operand notemp_iRegI() %{
3647 constraint(ALLOC_IN_RC(notemp_int_reg));
3648 match(RegI);
3649
3650 match(o0RegI);
3651
3652 format %{ %}
3653 interface(REG_INTER);
3654 %}
3655
3656 operand o0RegI() %{
3657 constraint(ALLOC_IN_RC(o0_regI));
3658 match(iRegI);
3659
3660 format %{ %}
3661 interface(REG_INTER);
3662 %}
3663
3664 // Pointer Register
3665 operand iRegP() %{
3666 constraint(ALLOC_IN_RC(ptr_reg));
3667 match(RegP);
3668
3669 match(lock_ptr_RegP);
3670 match(g1RegP);
3671 match(g2RegP);
3672 match(g3RegP);
3673 match(g4RegP);
3674 match(i0RegP);
3675 match(o0RegP);
3676 match(o1RegP);
3677 match(l7RegP);
3678
3679 format %{ %}
3680 interface(REG_INTER);
3681 %}
3682
3683 operand sp_ptr_RegP() %{
3684 constraint(ALLOC_IN_RC(sp_ptr_reg));
3685 match(RegP);
3686 match(iRegP);
3687
3688 format %{ %}
3689 interface(REG_INTER);
3690 %}
3691
3692 operand lock_ptr_RegP() %{
3693 constraint(ALLOC_IN_RC(lock_ptr_reg));
3694 match(RegP);
3695 match(i0RegP);
3696 match(o0RegP);
3697 match(o1RegP);
3698 match(l7RegP);
3699
3700 format %{ %}
3701 interface(REG_INTER);
3702 %}
3703
3704 operand g1RegP() %{
3705 constraint(ALLOC_IN_RC(g1_regP));
3706 match(iRegP);
3707
3708 format %{ %}
3709 interface(REG_INTER);
3710 %}
3711
3712 operand g2RegP() %{
3713 constraint(ALLOC_IN_RC(g2_regP));
3714 match(iRegP);
3715
3716 format %{ %}
3717 interface(REG_INTER);
3718 %}
3719
3720 operand g3RegP() %{
3721 constraint(ALLOC_IN_RC(g3_regP));
3722 match(iRegP);
3723
3724 format %{ %}
3725 interface(REG_INTER);
3726 %}
3727
3728 operand g1RegI() %{
3729 constraint(ALLOC_IN_RC(g1_regI));
3730 match(iRegI);
3731
3732 format %{ %}
3733 interface(REG_INTER);
3734 %}
3735
3736 operand g3RegI() %{
3737 constraint(ALLOC_IN_RC(g3_regI));
3738 match(iRegI);
3739
3740 format %{ %}
3741 interface(REG_INTER);
3742 %}
3743
3744 operand g4RegI() %{
3745 constraint(ALLOC_IN_RC(g4_regI));
3746 match(iRegI);
3747
3748 format %{ %}
3749 interface(REG_INTER);
3750 %}
3751
3752 operand g4RegP() %{
3753 constraint(ALLOC_IN_RC(g4_regP));
3754 match(iRegP);
3755
3756 format %{ %}
3757 interface(REG_INTER);
3758 %}
3759
3760 operand i0RegP() %{
3761 constraint(ALLOC_IN_RC(i0_regP));
3762 match(iRegP);
3763
3764 format %{ %}
3765 interface(REG_INTER);
3766 %}
3767
3768 operand o0RegP() %{
3769 constraint(ALLOC_IN_RC(o0_regP));
3770 match(iRegP);
3771
3772 format %{ %}
3773 interface(REG_INTER);
3774 %}
3775
3776 operand o1RegP() %{
3777 constraint(ALLOC_IN_RC(o1_regP));
3778 match(iRegP);
3779
3780 format %{ %}
3781 interface(REG_INTER);
3782 %}
3783
3784 operand o2RegP() %{
3785 constraint(ALLOC_IN_RC(o2_regP));
3786 match(iRegP);
3787
3788 format %{ %}
3789 interface(REG_INTER);
3790 %}
3791
3792 operand o7RegP() %{
3793 constraint(ALLOC_IN_RC(o7_regP));
3794 match(iRegP);
3795
3796 format %{ %}
3797 interface(REG_INTER);
3798 %}
3799
3800 operand l7RegP() %{
3801 constraint(ALLOC_IN_RC(l7_regP));
3802 match(iRegP);
3803
3804 format %{ %}
3805 interface(REG_INTER);
3806 %}
3807
3808 operand o7RegI() %{
3809 constraint(ALLOC_IN_RC(o7_regI));
3810 match(iRegI);
3811
3812 format %{ %}
3813 interface(REG_INTER);
3814 %}
3815
3816 operand iRegN() %{
3817 constraint(ALLOC_IN_RC(int_reg));
3818 match(RegN);
3819
3820 format %{ %}
3821 interface(REG_INTER);
3822 %}
3823
3824 // Long Register
3825 operand iRegL() %{
3826 constraint(ALLOC_IN_RC(long_reg));
3827 match(RegL);
3828
3829 format %{ %}
3830 interface(REG_INTER);
3831 %}
3832
3833 operand o2RegL() %{
3834 constraint(ALLOC_IN_RC(o2_regL));
3835 match(iRegL);
3836
3837 format %{ %}
3838 interface(REG_INTER);
3839 %}
3840
3841 operand o7RegL() %{
3842 constraint(ALLOC_IN_RC(o7_regL));
3843 match(iRegL);
3844
3845 format %{ %}
3846 interface(REG_INTER);
3847 %}
3848
3849 operand g1RegL() %{
3850 constraint(ALLOC_IN_RC(g1_regL));
3851 match(iRegL);
3852
3853 format %{ %}
3854 interface(REG_INTER);
3855 %}
3856
3857 operand g3RegL() %{
3858 constraint(ALLOC_IN_RC(g3_regL));
3859 match(iRegL);
3860
3861 format %{ %}
3862 interface(REG_INTER);
3863 %}
3864
3865 // Int Register safe
3866 // This is 64bit safe
3867 operand iRegIsafe() %{
3868 constraint(ALLOC_IN_RC(long_reg));
3869
3870 match(iRegI);
3871
3872 format %{ %}
3873 interface(REG_INTER);
3874 %}
3875
3876 // Condition Code Flag Register
3877 operand flagsReg() %{
3878 constraint(ALLOC_IN_RC(int_flags));
3879 match(RegFlags);
3880
3881 format %{ "ccr" %} // both ICC and XCC
3882 interface(REG_INTER);
3883 %}
3884
3885 // Condition Code Register, unsigned comparisons.
3886 operand flagsRegU() %{
3887 constraint(ALLOC_IN_RC(int_flags));
3888 match(RegFlags);
3889
3890 format %{ "icc_U" %}
3891 interface(REG_INTER);
3892 %}
3893
3894 // Condition Code Register, pointer comparisons.
3895 operand flagsRegP() %{
3896 constraint(ALLOC_IN_RC(int_flags));
3897 match(RegFlags);
3898
3899 #ifdef _LP64
3900 format %{ "xcc_P" %}
3901 #else
3902 format %{ "icc_P" %}
3903 #endif
3904 interface(REG_INTER);
3905 %}
3906
3907 // Condition Code Register, long comparisons.
3908 operand flagsRegL() %{
3909 constraint(ALLOC_IN_RC(int_flags));
3910 match(RegFlags);
3911
3912 format %{ "xcc_L" %}
3913 interface(REG_INTER);
3914 %}
3915
3916 // Condition Code Register, floating comparisons, unordered same as "less".
3917 operand flagsRegF() %{
3918 constraint(ALLOC_IN_RC(float_flags));
3919 match(RegFlags);
3920 match(flagsRegF0);
3921
3922 format %{ %}
3923 interface(REG_INTER);
3924 %}
3925
3926 operand flagsRegF0() %{
3927 constraint(ALLOC_IN_RC(float_flag0));
3928 match(RegFlags);
3929
3930 format %{ %}
3931 interface(REG_INTER);
3932 %}
3933
3934
3935 // Condition Code Flag Register used by long compare
3936 operand flagsReg_long_LTGE() %{
3937 constraint(ALLOC_IN_RC(int_flags));
3938 match(RegFlags);
3939 format %{ "icc_LTGE" %}
3940 interface(REG_INTER);
3941 %}
3942 operand flagsReg_long_EQNE() %{
3943 constraint(ALLOC_IN_RC(int_flags));
3944 match(RegFlags);
3945 format %{ "icc_EQNE" %}
3946 interface(REG_INTER);
3947 %}
3948 operand flagsReg_long_LEGT() %{
3949 constraint(ALLOC_IN_RC(int_flags));
3950 match(RegFlags);
3951 format %{ "icc_LEGT" %}
3952 interface(REG_INTER);
3953 %}
3954
3955
3956 operand regD() %{
3957 constraint(ALLOC_IN_RC(dflt_reg));
3958 match(RegD);
3959
3960 match(regD_low);
3961
3962 format %{ %}
3963 interface(REG_INTER);
3964 %}
3965
3966 operand regF() %{
3967 constraint(ALLOC_IN_RC(sflt_reg));
3968 match(RegF);
3969
3970 format %{ %}
3971 interface(REG_INTER);
3972 %}
3973
3974 operand regD_low() %{
3975 constraint(ALLOC_IN_RC(dflt_low_reg));
3976 match(regD);
3977
3978 format %{ %}
3979 interface(REG_INTER);
3980 %}
3981
3982 // Special Registers
3983
3984 // Method Register
3985 operand inline_cache_regP(iRegP reg) %{
3986 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3987 match(reg);
3988 format %{ %}
3989 interface(REG_INTER);
3990 %}
3991
3992 operand interpreter_method_oop_regP(iRegP reg) %{
3993 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3994 match(reg);
3995 format %{ %}
3996 interface(REG_INTER);
3997 %}
3998
3999
4000 //----------Complex Operands---------------------------------------------------
4001 // Indirect Memory Reference
4002 operand indirect(sp_ptr_RegP reg) %{
4003 constraint(ALLOC_IN_RC(sp_ptr_reg));
4004 match(reg);
4005
4006 op_cost(100);
4007 format %{ "[$reg]" %}
4008 interface(MEMORY_INTER) %{
4009 base($reg);
4010 index(0x0);
4011 scale(0x0);
4012 disp(0x0);
4013 %}
4014 %}
4015
4016 // Indirect with simm13 Offset
4017 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4018 constraint(ALLOC_IN_RC(sp_ptr_reg));
4019 match(AddP reg offset);
4020
4021 op_cost(100);
4022 format %{ "[$reg + $offset]" %}
4023 interface(MEMORY_INTER) %{
4024 base($reg);
4025 index(0x0);
4026 scale(0x0);
4027 disp($offset);
4028 %}
4029 %}
4030
4031 // Indirect with simm13 Offset minus 7
4032 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4033 constraint(ALLOC_IN_RC(sp_ptr_reg));
4034 match(AddP reg offset);
4035
4036 op_cost(100);
4037 format %{ "[$reg + $offset]" %}
4038 interface(MEMORY_INTER) %{
4039 base($reg);
4040 index(0x0);
4041 scale(0x0);
4042 disp($offset);
4043 %}
4044 %}
4045
4046 // Note: Intel has a swapped version also, like this:
4047 //operand indOffsetX(iRegI reg, immP offset) %{
4048 // constraint(ALLOC_IN_RC(int_reg));
4049 // match(AddP offset reg);
4050 //
4051 // op_cost(100);
4052 // format %{ "[$reg + $offset]" %}
4053 // interface(MEMORY_INTER) %{
4054 // base($reg);
4055 // index(0x0);
4056 // scale(0x0);
4057 // disp($offset);
4058 // %}
4059 //%}
4060 //// However, it doesn't make sense for SPARC, since
4061 // we have no particularly good way to embed oops in
4062 // single instructions.
4063
4064 // Indirect with Register Index
4065 operand indIndex(iRegP addr, iRegX index) %{
4066 constraint(ALLOC_IN_RC(ptr_reg));
4067 match(AddP addr index);
4068
4069 op_cost(100);
4070 format %{ "[$addr + $index]" %}
4071 interface(MEMORY_INTER) %{
4072 base($addr);
4073 index($index);
4074 scale(0x0);
4075 disp(0x0);
4076 %}
4077 %}
4078
4079 //----------Special Memory Operands--------------------------------------------
4080 // Stack Slot Operand - This operand is used for loading and storing temporary
4081 // values on the stack where a match requires a value to
4082 // flow through memory.
4083 operand stackSlotI(sRegI reg) %{
4084 constraint(ALLOC_IN_RC(stack_slots));
4085 op_cost(100);
4086 //match(RegI);
4087 format %{ "[$reg]" %}
4088 interface(MEMORY_INTER) %{
4089 base(0xE); // R_SP
4090 index(0x0);
4091 scale(0x0);
4092 disp($reg); // Stack Offset
4093 %}
4094 %}
4095
4096 operand stackSlotP(sRegP reg) %{
4097 constraint(ALLOC_IN_RC(stack_slots));
4098 op_cost(100);
4099 //match(RegP);
4100 format %{ "[$reg]" %}
4101 interface(MEMORY_INTER) %{
4102 base(0xE); // R_SP
4103 index(0x0);
4104 scale(0x0);
4105 disp($reg); // Stack Offset
4106 %}
4107 %}
4108
4109 operand stackSlotF(sRegF reg) %{
4110 constraint(ALLOC_IN_RC(stack_slots));
4111 op_cost(100);
4112 //match(RegF);
4113 format %{ "[$reg]" %}
4114 interface(MEMORY_INTER) %{
4115 base(0xE); // R_SP
4116 index(0x0);
4117 scale(0x0);
4118 disp($reg); // Stack Offset
4119 %}
4120 %}
4121 operand stackSlotD(sRegD reg) %{
4122 constraint(ALLOC_IN_RC(stack_slots));
4123 op_cost(100);
4124 //match(RegD);
4125 format %{ "[$reg]" %}
4126 interface(MEMORY_INTER) %{
4127 base(0xE); // R_SP
4128 index(0x0);
4129 scale(0x0);
4130 disp($reg); // Stack Offset
4131 %}
4132 %}
4133 operand stackSlotL(sRegL reg) %{
4134 constraint(ALLOC_IN_RC(stack_slots));
4135 op_cost(100);
4136 //match(RegL);
4137 format %{ "[$reg]" %}
4138 interface(MEMORY_INTER) %{
4139 base(0xE); // R_SP
4140 index(0x0);
4141 scale(0x0);
4142 disp($reg); // Stack Offset
4143 %}
4144 %}
4145
4146 // Operands for expressing Control Flow
4147 // NOTE: Label is a predefined operand which should not be redefined in
4148 // the AD file. It is generically handled within the ADLC.
4149
4150 //----------Conditional Branch Operands----------------------------------------
4151 // Comparison Op - This is the operation of the comparison, and is limited to
4152 // the following set of codes:
4153 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4154 //
4155 // Other attributes of the comparison, such as unsignedness, are specified
4156 // by the comparison instruction that sets a condition code flags register.
4157 // That result is represented by a flags operand whose subtype is appropriate
4158 // to the unsignedness (etc.) of the comparison.
4159 //
4160 // Later, the instruction which matches both the Comparison Op (a Bool) and
4161 // the flags (produced by the Cmp) specifies the coding of the comparison op
4162 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4163
4164 operand cmpOp() %{
4165 match(Bool);
4166
4167 format %{ "" %}
4168 interface(COND_INTER) %{
4169 equal(0x1);
4170 not_equal(0x9);
4171 less(0x3);
4172 greater_equal(0xB);
4173 less_equal(0x2);
4174 greater(0xA);
4175 overflow(0x7);
4176 no_overflow(0xF);
4177 %}
4178 %}
4179
4180 // Comparison Op, unsigned
4181 operand cmpOpU() %{
4182 match(Bool);
4183 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4184 n->as_Bool()->_test._test != BoolTest::no_overflow);
4185
4186 format %{ "u" %}
4187 interface(COND_INTER) %{
4188 equal(0x1);
4189 not_equal(0x9);
4190 less(0x5);
4191 greater_equal(0xD);
4192 less_equal(0x4);
4193 greater(0xC);
4194 overflow(0x7);
4195 no_overflow(0xF);
4196 %}
4197 %}
4198
4199 // Comparison Op, pointer (same as unsigned)
4200 operand cmpOpP() %{
4201 match(Bool);
4202 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4203 n->as_Bool()->_test._test != BoolTest::no_overflow);
4204
4205 format %{ "p" %}
4206 interface(COND_INTER) %{
4207 equal(0x1);
4208 not_equal(0x9);
4209 less(0x5);
4210 greater_equal(0xD);
4211 less_equal(0x4);
4212 greater(0xC);
4213 overflow(0x7);
4214 no_overflow(0xF);
4215 %}
4216 %}
4217
4218 // Comparison Op, branch-register encoding
4219 operand cmpOp_reg() %{
4220 match(Bool);
4221 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4222 n->as_Bool()->_test._test != BoolTest::no_overflow);
4223
4224 format %{ "" %}
4225 interface(COND_INTER) %{
4226 equal (0x1);
4227 not_equal (0x5);
4228 less (0x3);
4229 greater_equal(0x7);
4230 less_equal (0x2);
4231 greater (0x6);
4232 overflow(0x7); // not supported
4233 no_overflow(0xF); // not supported
4234 %}
4235 %}
4236
4237 // Comparison Code, floating, unordered same as less
4238 operand cmpOpF() %{
4239 match(Bool);
4240 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4241 n->as_Bool()->_test._test != BoolTest::no_overflow);
4242
4243 format %{ "fl" %}
4244 interface(COND_INTER) %{
4245 equal(0x9);
4246 not_equal(0x1);
4247 less(0x3);
4248 greater_equal(0xB);
4249 less_equal(0xE);
4250 greater(0x6);
4251
4252 overflow(0x7); // not supported
4253 no_overflow(0xF); // not supported
4254 %}
4255 %}
4256
4257 // Used by long compare
4258 operand cmpOp_commute() %{
4259 match(Bool);
4260 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4261 n->as_Bool()->_test._test != BoolTest::no_overflow);
4262
4263 format %{ "" %}
4264 interface(COND_INTER) %{
4265 equal(0x1);
4266 not_equal(0x9);
4267 less(0xA);
4268 greater_equal(0x2);
4269 less_equal(0xB);
4270 greater(0x3);
4271 overflow(0x7);
4272 no_overflow(0xF);
4273 %}
4274 %}
4275
4276 //----------OPERAND CLASSES----------------------------------------------------
4277 // Operand Classes are groups of operands that are used to simplify
4278 // instruction definitions by not requiring the AD writer to specify separate
4279 // instructions for every form of operand when the instruction accepts
4280 // multiple operand types with the same basic encoding and format. The classic
4281 // case of this is memory operands.
4282 opclass memory( indirect, indOffset13, indIndex );
4283 opclass indIndexMemory( indIndex );
4284
4285 //----------PIPELINE-----------------------------------------------------------
4286 pipeline %{
4287
4288 //----------ATTRIBUTES---------------------------------------------------------
4289 attributes %{
4290 fixed_size_instructions; // Fixed size instructions
4291 branch_has_delay_slot; // Branch has delay slot following
4292 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4293 instruction_unit_size = 4; // An instruction is 4 bytes long
4294 instruction_fetch_unit_size = 16; // The processor fetches one line
4295 instruction_fetch_units = 1; // of 16 bytes
4296
4297 // List of nop instructions
4298 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4299 %}
4300
4301 //----------RESOURCES----------------------------------------------------------
4302 // Resources are the functional units available to the machine
4303 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4304
4305 //----------PIPELINE DESCRIPTION-----------------------------------------------
4306 // Pipeline Description specifies the stages in the machine's pipeline
4307
4308 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4309
4310 //----------PIPELINE CLASSES---------------------------------------------------
4311 // Pipeline Classes describe the stages in which input and output are
4312 // referenced by the hardware pipeline.
4313
4314 // Integer ALU reg-reg operation
4315 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4316 single_instruction;
4317 dst : E(write);
4318 src1 : R(read);
4319 src2 : R(read);
4320 IALU : R;
4321 %}
4322
4323 // Integer ALU reg-reg long operation
4324 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4325 instruction_count(2);
4326 dst : E(write);
4327 src1 : R(read);
4328 src2 : R(read);
4329 IALU : R;
4330 IALU : R;
4331 %}
4332
4333 // Integer ALU reg-reg long dependent operation
4334 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4335 instruction_count(1); multiple_bundles;
4336 dst : E(write);
4337 src1 : R(read);
4338 src2 : R(read);
4339 cr : E(write);
4340 IALU : R(2);
4341 %}
4342
4343 // Integer ALU reg-imm operaion
4344 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4345 single_instruction;
4346 dst : E(write);
4347 src1 : R(read);
4348 IALU : R;
4349 %}
4350
4351 // Integer ALU reg-reg operation with condition code
4352 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4353 single_instruction;
4354 dst : E(write);
4355 cr : E(write);
4356 src1 : R(read);
4357 src2 : R(read);
4358 IALU : R;
4359 %}
4360
4361 // Integer ALU reg-imm operation with condition code
4362 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4363 single_instruction;
4364 dst : E(write);
4365 cr : E(write);
4366 src1 : R(read);
4367 IALU : R;
4368 %}
4369
4370 // Integer ALU zero-reg operation
4371 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4372 single_instruction;
4373 dst : E(write);
4374 src2 : R(read);
4375 IALU : R;
4376 %}
4377
4378 // Integer ALU zero-reg operation with condition code only
4379 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4380 single_instruction;
4381 cr : E(write);
4382 src : R(read);
4383 IALU : R;
4384 %}
4385
4386 // Integer ALU reg-reg operation with condition code only
4387 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4388 single_instruction;
4389 cr : E(write);
4390 src1 : R(read);
4391 src2 : R(read);
4392 IALU : R;
4393 %}
4394
4395 // Integer ALU reg-imm operation with condition code only
4396 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4397 single_instruction;
4398 cr : E(write);
4399 src1 : R(read);
4400 IALU : R;
4401 %}
4402
4403 // Integer ALU reg-reg-zero operation with condition code only
4404 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4405 single_instruction;
4406 cr : E(write);
4407 src1 : R(read);
4408 src2 : R(read);
4409 IALU : R;
4410 %}
4411
4412 // Integer ALU reg-imm-zero operation with condition code only
4413 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4414 single_instruction;
4415 cr : E(write);
4416 src1 : R(read);
4417 IALU : R;
4418 %}
4419
4420 // Integer ALU reg-reg operation with condition code, src1 modified
4421 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4422 single_instruction;
4423 cr : E(write);
4424 src1 : E(write);
4425 src1 : R(read);
4426 src2 : R(read);
4427 IALU : R;
4428 %}
4429
4430 // Integer ALU reg-imm operation with condition code, src1 modified
4431 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4432 single_instruction;
4433 cr : E(write);
4434 src1 : E(write);
4435 src1 : R(read);
4436 IALU : R;
4437 %}
4438
4439 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4440 multiple_bundles;
4441 dst : E(write)+4;
4442 cr : E(write);
4443 src1 : R(read);
4444 src2 : R(read);
4445 IALU : R(3);
4446 BR : R(2);
4447 %}
4448
4449 // Integer ALU operation
4450 pipe_class ialu_none(iRegI dst) %{
4451 single_instruction;
4452 dst : E(write);
4453 IALU : R;
4454 %}
4455
4456 // Integer ALU reg operation
4457 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4458 single_instruction; may_have_no_code;
4459 dst : E(write);
4460 src : R(read);
4461 IALU : R;
4462 %}
4463
4464 // Integer ALU reg conditional operation
4465 // This instruction has a 1 cycle stall, and cannot execute
4466 // in the same cycle as the instruction setting the condition
4467 // code. We kludge this by pretending to read the condition code
4468 // 1 cycle earlier, and by marking the functional units as busy
4469 // for 2 cycles with the result available 1 cycle later than
4470 // is really the case.
4471 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4472 single_instruction;
4473 op2_out : C(write);
4474 op1 : R(read);
4475 cr : R(read); // This is really E, with a 1 cycle stall
4476 BR : R(2);
4477 MS : R(2);
4478 %}
4479
4480 #ifdef _LP64
4481 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4482 instruction_count(1); multiple_bundles;
4483 dst : C(write)+1;
4484 src : R(read)+1;
4485 IALU : R(1);
4486 BR : E(2);
4487 MS : E(2);
4488 %}
4489 #endif
4490
4491 // Integer ALU reg operation
4492 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4493 single_instruction; may_have_no_code;
4494 dst : E(write);
4495 src : R(read);
4496 IALU : R;
4497 %}
4498 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4499 single_instruction; may_have_no_code;
4500 dst : E(write);
4501 src : R(read);
4502 IALU : R;
4503 %}
4504
4505 // Two integer ALU reg operations
4506 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4507 instruction_count(2);
4508 dst : E(write);
4509 src : R(read);
4510 A0 : R;
4511 A1 : R;
4512 %}
4513
4514 // Two integer ALU reg operations
4515 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4516 instruction_count(2); may_have_no_code;
4517 dst : E(write);
4518 src : R(read);
4519 A0 : R;
4520 A1 : R;
4521 %}
4522
4523 // Integer ALU imm operation
4524 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4525 single_instruction;
4526 dst : E(write);
4527 IALU : R;
4528 %}
4529
4530 // Integer ALU reg-reg with carry operation
4531 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4532 single_instruction;
4533 dst : E(write);
4534 src1 : R(read);
4535 src2 : R(read);
4536 IALU : R;
4537 %}
4538
4539 // Integer ALU cc operation
4540 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4541 single_instruction;
4542 dst : E(write);
4543 cc : R(read);
4544 IALU : R;
4545 %}
4546
4547 // Integer ALU cc / second IALU operation
4548 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4549 instruction_count(1); multiple_bundles;
4550 dst : E(write)+1;
4551 src : R(read);
4552 IALU : R;
4553 %}
4554
4555 // Integer ALU cc / second IALU operation
4556 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4557 instruction_count(1); multiple_bundles;
4558 dst : E(write)+1;
4559 p : R(read);
4560 q : R(read);
4561 IALU : R;
4562 %}
4563
4564 // Integer ALU hi-lo-reg operation
4565 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4566 instruction_count(1); multiple_bundles;
4567 dst : E(write)+1;
4568 IALU : R(2);
4569 %}
4570
4571 // Float ALU hi-lo-reg operation (with temp)
4572 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4573 instruction_count(1); multiple_bundles;
4574 dst : E(write)+1;
4575 IALU : R(2);
4576 %}
4577
4578 // Long Constant
4579 pipe_class loadConL( iRegL dst, immL src ) %{
4580 instruction_count(2); multiple_bundles;
4581 dst : E(write)+1;
4582 IALU : R(2);
4583 IALU : R(2);
4584 %}
4585
4586 // Pointer Constant
4587 pipe_class loadConP( iRegP dst, immP src ) %{
4588 instruction_count(0); multiple_bundles;
4589 fixed_latency(6);
4590 %}
4591
4592 // Polling Address
4593 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4594 #ifdef _LP64
4595 instruction_count(0); multiple_bundles;
4596 fixed_latency(6);
4597 #else
4598 dst : E(write);
4599 IALU : R;
4600 #endif
4601 %}
4602
4603 // Long Constant small
4604 pipe_class loadConLlo( iRegL dst, immL src ) %{
4605 instruction_count(2);
4606 dst : E(write);
4607 IALU : R;
4608 IALU : R;
4609 %}
4610
4611 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4612 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4613 instruction_count(1); multiple_bundles;
4614 src : R(read);
4615 dst : M(write)+1;
4616 IALU : R;
4617 MS : E;
4618 %}
4619
4620 // Integer ALU nop operation
4621 pipe_class ialu_nop() %{
4622 single_instruction;
4623 IALU : R;
4624 %}
4625
4626 // Integer ALU nop operation
4627 pipe_class ialu_nop_A0() %{
4628 single_instruction;
4629 A0 : R;
4630 %}
4631
4632 // Integer ALU nop operation
4633 pipe_class ialu_nop_A1() %{
4634 single_instruction;
4635 A1 : R;
4636 %}
4637
4638 // Integer Multiply reg-reg operation
4639 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4640 single_instruction;
4641 dst : E(write);
4642 src1 : R(read);
4643 src2 : R(read);
4644 MS : R(5);
4645 %}
4646
4647 // Integer Multiply reg-imm operation
4648 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4649 single_instruction;
4650 dst : E(write);
4651 src1 : R(read);
4652 MS : R(5);
4653 %}
4654
4655 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4656 single_instruction;
4657 dst : E(write)+4;
4658 src1 : R(read);
4659 src2 : R(read);
4660 MS : R(6);
4661 %}
4662
4663 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4664 single_instruction;
4665 dst : E(write)+4;
4666 src1 : R(read);
4667 MS : R(6);
4668 %}
4669
4670 // Integer Divide reg-reg
4671 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4672 instruction_count(1); multiple_bundles;
4673 dst : E(write);
4674 temp : E(write);
4675 src1 : R(read);
4676 src2 : R(read);
4677 temp : R(read);
4678 MS : R(38);
4679 %}
4680
4681 // Integer Divide reg-imm
4682 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4683 instruction_count(1); multiple_bundles;
4684 dst : E(write);
4685 temp : E(write);
4686 src1 : R(read);
4687 temp : R(read);
4688 MS : R(38);
4689 %}
4690
4691 // Long Divide
4692 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4693 dst : E(write)+71;
4694 src1 : R(read);
4695 src2 : R(read)+1;
4696 MS : R(70);
4697 %}
4698
4699 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4700 dst : E(write)+71;
4701 src1 : R(read);
4702 MS : R(70);
4703 %}
4704
4705 // Floating Point Add Float
4706 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4707 single_instruction;
4708 dst : X(write);
4709 src1 : E(read);
4710 src2 : E(read);
4711 FA : R;
4712 %}
4713
4714 // Floating Point Add Double
4715 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4716 single_instruction;
4717 dst : X(write);
4718 src1 : E(read);
4719 src2 : E(read);
4720 FA : R;
4721 %}
4722
4723 // Floating Point Conditional Move based on integer flags
4724 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4725 single_instruction;
4726 dst : X(write);
4727 src : E(read);
4728 cr : R(read);
4729 FA : R(2);
4730 BR : R(2);
4731 %}
4732
4733 // Floating Point Conditional Move based on integer flags
4734 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4735 single_instruction;
4736 dst : X(write);
4737 src : E(read);
4738 cr : R(read);
4739 FA : R(2);
4740 BR : R(2);
4741 %}
4742
4743 // Floating Point Multiply Float
4744 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4745 single_instruction;
4746 dst : X(write);
4747 src1 : E(read);
4748 src2 : E(read);
4749 FM : R;
4750 %}
4751
4752 // Floating Point Multiply Double
4753 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4754 single_instruction;
4755 dst : X(write);
4756 src1 : E(read);
4757 src2 : E(read);
4758 FM : R;
4759 %}
4760
4761 // Floating Point Divide Float
4762 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4763 single_instruction;
4764 dst : X(write);
4765 src1 : E(read);
4766 src2 : E(read);
4767 FM : R;
4768 FDIV : C(14);
4769 %}
4770
4771 // Floating Point Divide Double
4772 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4773 single_instruction;
4774 dst : X(write);
4775 src1 : E(read);
4776 src2 : E(read);
4777 FM : R;
4778 FDIV : C(17);
4779 %}
4780
4781 // Floating Point Move/Negate/Abs Float
4782 pipe_class faddF_reg(regF dst, regF src) %{
4783 single_instruction;
4784 dst : W(write);
4785 src : E(read);
4786 FA : R(1);
4787 %}
4788
4789 // Floating Point Move/Negate/Abs Double
4790 pipe_class faddD_reg(regD dst, regD src) %{
4791 single_instruction;
4792 dst : W(write);
4793 src : E(read);
4794 FA : R;
4795 %}
4796
4797 // Floating Point Convert F->D
4798 pipe_class fcvtF2D(regD dst, regF src) %{
4799 single_instruction;
4800 dst : X(write);
4801 src : E(read);
4802 FA : R;
4803 %}
4804
4805 // Floating Point Convert I->D
4806 pipe_class fcvtI2D(regD dst, regF src) %{
4807 single_instruction;
4808 dst : X(write);
4809 src : E(read);
4810 FA : R;
4811 %}
4812
4813 // Floating Point Convert LHi->D
4814 pipe_class fcvtLHi2D(regD dst, regD src) %{
4815 single_instruction;
4816 dst : X(write);
4817 src : E(read);
4818 FA : R;
4819 %}
4820
4821 // Floating Point Convert L->D
4822 pipe_class fcvtL2D(regD dst, regF src) %{
4823 single_instruction;
4824 dst : X(write);
4825 src : E(read);
4826 FA : R;
4827 %}
4828
4829 // Floating Point Convert L->F
4830 pipe_class fcvtL2F(regD dst, regF src) %{
4831 single_instruction;
4832 dst : X(write);
4833 src : E(read);
4834 FA : R;
4835 %}
4836
4837 // Floating Point Convert D->F
4838 pipe_class fcvtD2F(regD dst, regF src) %{
4839 single_instruction;
4840 dst : X(write);
4841 src : E(read);
4842 FA : R;
4843 %}
4844
4845 // Floating Point Convert I->L
4846 pipe_class fcvtI2L(regD dst, regF src) %{
4847 single_instruction;
4848 dst : X(write);
4849 src : E(read);
4850 FA : R;
4851 %}
4852
4853 // Floating Point Convert D->F
4854 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4855 instruction_count(1); multiple_bundles;
4856 dst : X(write)+6;
4857 src : E(read);
4858 FA : R;
4859 %}
4860
4861 // Floating Point Convert D->L
4862 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4863 instruction_count(1); multiple_bundles;
4864 dst : X(write)+6;
4865 src : E(read);
4866 FA : R;
4867 %}
4868
4869 // Floating Point Convert F->I
4870 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4871 instruction_count(1); multiple_bundles;
4872 dst : X(write)+6;
4873 src : E(read);
4874 FA : R;
4875 %}
4876
4877 // Floating Point Convert F->L
4878 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4879 instruction_count(1); multiple_bundles;
4880 dst : X(write)+6;
4881 src : E(read);
4882 FA : R;
4883 %}
4884
4885 // Floating Point Convert I->F
4886 pipe_class fcvtI2F(regF dst, regF src) %{
4887 single_instruction;
4888 dst : X(write);
4889 src : E(read);
4890 FA : R;
4891 %}
4892
4893 // Floating Point Compare
4894 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4895 single_instruction;
4896 cr : X(write);
4897 src1 : E(read);
4898 src2 : E(read);
4899 FA : R;
4900 %}
4901
4902 // Floating Point Compare
4903 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4904 single_instruction;
4905 cr : X(write);
4906 src1 : E(read);
4907 src2 : E(read);
4908 FA : R;
4909 %}
4910
4911 // Floating Add Nop
4912 pipe_class fadd_nop() %{
4913 single_instruction;
4914 FA : R;
4915 %}
4916
4917 // Integer Store to Memory
4918 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4919 single_instruction;
4920 mem : R(read);
4921 src : C(read);
4922 MS : R;
4923 %}
4924
4925 // Integer Store to Memory
4926 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4927 single_instruction;
4928 mem : R(read);
4929 src : C(read);
4930 MS : R;
4931 %}
4932
4933 // Integer Store Zero to Memory
4934 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4935 single_instruction;
4936 mem : R(read);
4937 MS : R;
4938 %}
4939
4940 // Special Stack Slot Store
4941 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4942 single_instruction;
4943 stkSlot : R(read);
4944 src : C(read);
4945 MS : R;
4946 %}
4947
4948 // Special Stack Slot Store
4949 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4950 instruction_count(2); multiple_bundles;
4951 stkSlot : R(read);
4952 src : C(read);
4953 MS : R(2);
4954 %}
4955
4956 // Float Store
4957 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4958 single_instruction;
4959 mem : R(read);
4960 src : C(read);
4961 MS : R;
4962 %}
4963
4964 // Float Store
4965 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4966 single_instruction;
4967 mem : R(read);
4968 MS : R;
4969 %}
4970
4971 // Double Store
4972 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4973 instruction_count(1);
4974 mem : R(read);
4975 src : C(read);
4976 MS : R;
4977 %}
4978
4979 // Double Store
4980 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4981 single_instruction;
4982 mem : R(read);
4983 MS : R;
4984 %}
4985
4986 // Special Stack Slot Float Store
4987 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4988 single_instruction;
4989 stkSlot : R(read);
4990 src : C(read);
4991 MS : R;
4992 %}
4993
4994 // Special Stack Slot Double Store
4995 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4996 single_instruction;
4997 stkSlot : R(read);
4998 src : C(read);
4999 MS : R;
5000 %}
5001
5002 // Integer Load (when sign bit propagation not needed)
5003 pipe_class iload_mem(iRegI dst, memory mem) %{
5004 single_instruction;
5005 mem : R(read);
5006 dst : C(write);
5007 MS : R;
5008 %}
5009
5010 // Integer Load from stack operand
5011 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5012 single_instruction;
5013 mem : R(read);
5014 dst : C(write);
5015 MS : R;
5016 %}
5017
5018 // Integer Load (when sign bit propagation or masking is needed)
5019 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5020 single_instruction;
5021 mem : R(read);
5022 dst : M(write);
5023 MS : R;
5024 %}
5025
5026 // Float Load
5027 pipe_class floadF_mem(regF dst, memory mem) %{
5028 single_instruction;
5029 mem : R(read);
5030 dst : M(write);
5031 MS : R;
5032 %}
5033
5034 // Float Load
5035 pipe_class floadD_mem(regD dst, memory mem) %{
5036 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5037 mem : R(read);
5038 dst : M(write);
5039 MS : R;
5040 %}
5041
5042 // Float Load
5043 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5044 single_instruction;
5045 stkSlot : R(read);
5046 dst : M(write);
5047 MS : R;
5048 %}
5049
5050 // Float Load
5051 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5052 single_instruction;
5053 stkSlot : R(read);
5054 dst : M(write);
5055 MS : R;
5056 %}
5057
5058 // Memory Nop
5059 pipe_class mem_nop() %{
5060 single_instruction;
5061 MS : R;
5062 %}
5063
5064 pipe_class sethi(iRegP dst, immI src) %{
5065 single_instruction;
5066 dst : E(write);
5067 IALU : R;
5068 %}
5069
5070 pipe_class loadPollP(iRegP poll) %{
5071 single_instruction;
5072 poll : R(read);
5073 MS : R;
5074 %}
5075
5076 pipe_class br(Universe br, label labl) %{
5077 single_instruction_with_delay_slot;
5078 BR : R;
5079 %}
5080
5081 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5082 single_instruction_with_delay_slot;
5083 cr : E(read);
5084 BR : R;
5085 %}
5086
5087 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5088 single_instruction_with_delay_slot;
5089 op1 : E(read);
5090 BR : R;
5091 MS : R;
5092 %}
5093
5094 // Compare and branch
5095 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5096 instruction_count(2); has_delay_slot;
5097 cr : E(write);
5098 src1 : R(read);
5099 src2 : R(read);
5100 IALU : R;
5101 BR : R;
5102 %}
5103
5104 // Compare and branch
5105 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5106 instruction_count(2); has_delay_slot;
5107 cr : E(write);
5108 src1 : R(read);
5109 IALU : R;
5110 BR : R;
5111 %}
5112
5113 // Compare and branch using cbcond
5114 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5115 single_instruction;
5116 src1 : E(read);
5117 src2 : E(read);
5118 IALU : R;
5119 BR : R;
5120 %}
5121
5122 // Compare and branch using cbcond
5123 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5124 single_instruction;
5125 src1 : E(read);
5126 IALU : R;
5127 BR : R;
5128 %}
5129
5130 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5131 single_instruction_with_delay_slot;
5132 cr : E(read);
5133 BR : R;
5134 %}
5135
5136 pipe_class br_nop() %{
5137 single_instruction;
5138 BR : R;
5139 %}
5140
5141 pipe_class simple_call(method meth) %{
5142 instruction_count(2); multiple_bundles; force_serialization;
5143 fixed_latency(100);
5144 BR : R(1);
5145 MS : R(1);
5146 A0 : R(1);
5147 %}
5148
5149 pipe_class compiled_call(method meth) %{
5150 instruction_count(1); multiple_bundles; force_serialization;
5151 fixed_latency(100);
5152 MS : R(1);
5153 %}
5154
5155 pipe_class call(method meth) %{
5156 instruction_count(0); multiple_bundles; force_serialization;
5157 fixed_latency(100);
5158 %}
5159
5160 pipe_class tail_call(Universe ignore, label labl) %{
5161 single_instruction; has_delay_slot;
5162 fixed_latency(100);
5163 BR : R(1);
5164 MS : R(1);
5165 %}
5166
5167 pipe_class ret(Universe ignore) %{
5168 single_instruction; has_delay_slot;
5169 BR : R(1);
5170 MS : R(1);
5171 %}
5172
5173 pipe_class ret_poll(g3RegP poll) %{
5174 instruction_count(3); has_delay_slot;
5175 poll : E(read);
5176 MS : R;
5177 %}
5178
5179 // The real do-nothing guy
5180 pipe_class empty( ) %{
5181 instruction_count(0);
5182 %}
5183
5184 pipe_class long_memory_op() %{
5185 instruction_count(0); multiple_bundles; force_serialization;
5186 fixed_latency(25);
5187 MS : R(1);
5188 %}
5189
5190 // Check-cast
5191 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5192 array : R(read);
5193 match : R(read);
5194 IALU : R(2);
5195 BR : R(2);
5196 MS : R;
5197 %}
5198
5199 // Convert FPU flags into +1,0,-1
5200 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5201 src1 : E(read);
5202 src2 : E(read);
5203 dst : E(write);
5204 FA : R;
5205 MS : R(2);
5206 BR : R(2);
5207 %}
5208
5209 // Compare for p < q, and conditionally add y
5210 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5211 p : E(read);
5212 q : E(read);
5213 y : E(read);
5214 IALU : R(3)
5215 %}
5216
5217 // Perform a compare, then move conditionally in a branch delay slot.
5218 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5219 src2 : E(read);
5220 srcdst : E(read);
5221 IALU : R;
5222 BR : R;
5223 %}
5224
5225 // Define the class for the Nop node
5226 define %{
5227 MachNop = ialu_nop;
5228 %}
5229
5230 %}
5231
5232 //----------INSTRUCTIONS-------------------------------------------------------
5233
5234 //------------Special Stack Slot instructions - no match rules-----------------
5235 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5236 // No match rule to avoid chain rule match.
5237 effect(DEF dst, USE src);
5238 ins_cost(MEMORY_REF_COST);
5239 format %{ "LDF $src,$dst\t! stkI to regF" %}
5240 opcode(Assembler::ldf_op3);
5241 ins_encode(simple_form3_mem_reg(src, dst));
5242 ins_pipe(floadF_stk);
5243 %}
5244
5245 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5246 // No match rule to avoid chain rule match.
5247 effect(DEF dst, USE src);
5248 ins_cost(MEMORY_REF_COST);
5249 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5250 opcode(Assembler::lddf_op3);
5251 ins_encode(simple_form3_mem_reg(src, dst));
5252 ins_pipe(floadD_stk);
5253 %}
5254
5255 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5256 // No match rule to avoid chain rule match.
5257 effect(DEF dst, USE src);
5258 ins_cost(MEMORY_REF_COST);
5259 format %{ "STF $src,$dst\t! regF to stkI" %}
5260 opcode(Assembler::stf_op3);
5261 ins_encode(simple_form3_mem_reg(dst, src));
5262 ins_pipe(fstoreF_stk_reg);
5263 %}
5264
5265 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5266 // No match rule to avoid chain rule match.
5267 effect(DEF dst, USE src);
5268 ins_cost(MEMORY_REF_COST);
5269 format %{ "STDF $src,$dst\t! regD to stkL" %}
5270 opcode(Assembler::stdf_op3);
5271 ins_encode(simple_form3_mem_reg(dst, src));
5272 ins_pipe(fstoreD_stk_reg);
5273 %}
5274
5275 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5276 effect(DEF dst, USE src);
5277 ins_cost(MEMORY_REF_COST*2);
5278 format %{ "STW $src,$dst.hi\t! long\n\t"
5279 "STW R_G0,$dst.lo" %}
5280 opcode(Assembler::stw_op3);
5281 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5282 ins_pipe(lstoreI_stk_reg);
5283 %}
5284
5285 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5286 // No match rule to avoid chain rule match.
5287 effect(DEF dst, USE src);
5288 ins_cost(MEMORY_REF_COST);
5289 format %{ "STX $src,$dst\t! regL to stkD" %}
5290 opcode(Assembler::stx_op3);
5291 ins_encode(simple_form3_mem_reg( dst, src ) );
5292 ins_pipe(istore_stk_reg);
5293 %}
5294
5295 //---------- Chain stack slots between similar types --------
5296
5297 // Load integer from stack slot
5298 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5299 match(Set dst src);
5300 ins_cost(MEMORY_REF_COST);
5301
5302 format %{ "LDUW $src,$dst\t!stk" %}
5303 opcode(Assembler::lduw_op3);
5304 ins_encode(simple_form3_mem_reg( src, dst ) );
5305 ins_pipe(iload_mem);
5306 %}
5307
5308 // Store integer to stack slot
5309 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5310 match(Set dst src);
5311 ins_cost(MEMORY_REF_COST);
5312
5313 format %{ "STW $src,$dst\t!stk" %}
5314 opcode(Assembler::stw_op3);
5315 ins_encode(simple_form3_mem_reg( dst, src ) );
5316 ins_pipe(istore_mem_reg);
5317 %}
5318
5319 // Load long from stack slot
5320 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5321 match(Set dst src);
5322
5323 ins_cost(MEMORY_REF_COST);
5324 format %{ "LDX $src,$dst\t! long" %}
5325 opcode(Assembler::ldx_op3);
5326 ins_encode(simple_form3_mem_reg( src, dst ) );
5327 ins_pipe(iload_mem);
5328 %}
5329
5330 // Store long to stack slot
5331 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5332 match(Set dst src);
5333
5334 ins_cost(MEMORY_REF_COST);
5335 format %{ "STX $src,$dst\t! long" %}
5336 opcode(Assembler::stx_op3);
5337 ins_encode(simple_form3_mem_reg( dst, src ) );
5338 ins_pipe(istore_mem_reg);
5339 %}
5340
5341 #ifdef _LP64
5342 // Load pointer from stack slot, 64-bit encoding
5343 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5344 match(Set dst src);
5345 ins_cost(MEMORY_REF_COST);
5346 format %{ "LDX $src,$dst\t!ptr" %}
5347 opcode(Assembler::ldx_op3);
5348 ins_encode(simple_form3_mem_reg( src, dst ) );
5349 ins_pipe(iload_mem);
5350 %}
5351
5352 // Store pointer to stack slot
5353 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5354 match(Set dst src);
5355 ins_cost(MEMORY_REF_COST);
5356 format %{ "STX $src,$dst\t!ptr" %}
5357 opcode(Assembler::stx_op3);
5358 ins_encode(simple_form3_mem_reg( dst, src ) );
5359 ins_pipe(istore_mem_reg);
5360 %}
5361 #else // _LP64
5362 // Load pointer from stack slot, 32-bit encoding
5363 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5364 match(Set dst src);
5365 ins_cost(MEMORY_REF_COST);
5366 format %{ "LDUW $src,$dst\t!ptr" %}
5367 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5368 ins_encode(simple_form3_mem_reg( src, dst ) );
5369 ins_pipe(iload_mem);
5370 %}
5371
5372 // Store pointer to stack slot
5373 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5374 match(Set dst src);
5375 ins_cost(MEMORY_REF_COST);
5376 format %{ "STW $src,$dst\t!ptr" %}
5377 opcode(Assembler::stw_op3, Assembler::ldst_op);
5378 ins_encode(simple_form3_mem_reg( dst, src ) );
5379 ins_pipe(istore_mem_reg);
5380 %}
5381 #endif // _LP64
5382
5383 //------------Special Nop instructions for bundling - no match rules-----------
5384 // Nop using the A0 functional unit
5385 instruct Nop_A0() %{
5386 ins_cost(0);
5387
5388 format %{ "NOP ! Alu Pipeline" %}
5389 opcode(Assembler::or_op3, Assembler::arith_op);
5390 ins_encode( form2_nop() );
5391 ins_pipe(ialu_nop_A0);
5392 %}
5393
5394 // Nop using the A1 functional unit
5395 instruct Nop_A1( ) %{
5396 ins_cost(0);
5397
5398 format %{ "NOP ! Alu Pipeline" %}
5399 opcode(Assembler::or_op3, Assembler::arith_op);
5400 ins_encode( form2_nop() );
5401 ins_pipe(ialu_nop_A1);
5402 %}
5403
5404 // Nop using the memory functional unit
5405 instruct Nop_MS( ) %{
5406 ins_cost(0);
5407
5408 format %{ "NOP ! Memory Pipeline" %}
5409 ins_encode( emit_mem_nop );
5410 ins_pipe(mem_nop);
5411 %}
5412
5413 // Nop using the floating add functional unit
5414 instruct Nop_FA( ) %{
5415 ins_cost(0);
5416
5417 format %{ "NOP ! Floating Add Pipeline" %}
5418 ins_encode( emit_fadd_nop );
5419 ins_pipe(fadd_nop);
5420 %}
5421
5422 // Nop using the branch functional unit
5423 instruct Nop_BR( ) %{
5424 ins_cost(0);
5425
5426 format %{ "NOP ! Branch Pipeline" %}
5427 ins_encode( emit_br_nop );
5428 ins_pipe(br_nop);
5429 %}
5430
5431 //----------Load/Store/Move Instructions---------------------------------------
5432 //----------Load Instructions--------------------------------------------------
5433 // Load Byte (8bit signed)
5434 instruct loadB(iRegI dst, memory mem) %{
5435 match(Set dst (LoadB mem));
5436 ins_cost(MEMORY_REF_COST);
5437
5438 size(4);
5439 format %{ "LDSB $mem,$dst\t! byte" %}
5440 ins_encode %{
5441 __ ldsb($mem$$Address, $dst$$Register);
5442 %}
5443 ins_pipe(iload_mask_mem);
5444 %}
5445
5446 // Load Byte (8bit signed) into a Long Register
5447 instruct loadB2L(iRegL dst, memory mem) %{
5448 match(Set dst (ConvI2L (LoadB mem)));
5449 ins_cost(MEMORY_REF_COST);
5450
5451 size(4);
5452 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5453 ins_encode %{
5454 __ ldsb($mem$$Address, $dst$$Register);
5455 %}
5456 ins_pipe(iload_mask_mem);
5457 %}
5458
5459 // Load Unsigned Byte (8bit UNsigned) into an int reg
5460 instruct loadUB(iRegI dst, memory mem) %{
5461 match(Set dst (LoadUB mem));
5462 ins_cost(MEMORY_REF_COST);
5463
5464 size(4);
5465 format %{ "LDUB $mem,$dst\t! ubyte" %}
5466 ins_encode %{
5467 __ ldub($mem$$Address, $dst$$Register);
5468 %}
5469 ins_pipe(iload_mem);
5470 %}
5471
5472 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5473 instruct loadUB2L(iRegL dst, memory mem) %{
5474 match(Set dst (ConvI2L (LoadUB mem)));
5475 ins_cost(MEMORY_REF_COST);
5476
5477 size(4);
5478 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5479 ins_encode %{
5480 __ ldub($mem$$Address, $dst$$Register);
5481 %}
5482 ins_pipe(iload_mem);
5483 %}
5484
5485 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5486 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5487 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5488 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5489
5490 size(2*4);
5491 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5492 "AND $dst,right_n_bits($mask, 8),$dst" %}
5493 ins_encode %{
5494 __ ldub($mem$$Address, $dst$$Register);
5495 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5496 %}
5497 ins_pipe(iload_mem);
5498 %}
5499
5500 // Load Short (16bit signed)
5501 instruct loadS(iRegI dst, memory mem) %{
5502 match(Set dst (LoadS mem));
5503 ins_cost(MEMORY_REF_COST);
5504
5505 size(4);
5506 format %{ "LDSH $mem,$dst\t! short" %}
5507 ins_encode %{
5508 __ ldsh($mem$$Address, $dst$$Register);
5509 %}
5510 ins_pipe(iload_mask_mem);
5511 %}
5512
5513 // Load Short (16 bit signed) to Byte (8 bit signed)
5514 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5515 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5516 ins_cost(MEMORY_REF_COST);
5517
5518 size(4);
5519
5520 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5521 ins_encode %{
5522 __ ldsb($mem$$Address, $dst$$Register, 1);
5523 %}
5524 ins_pipe(iload_mask_mem);
5525 %}
5526
5527 // Load Short (16bit signed) into a Long Register
5528 instruct loadS2L(iRegL dst, memory mem) %{
5529 match(Set dst (ConvI2L (LoadS mem)));
5530 ins_cost(MEMORY_REF_COST);
5531
5532 size(4);
5533 format %{ "LDSH $mem,$dst\t! short -> long" %}
5534 ins_encode %{
5535 __ ldsh($mem$$Address, $dst$$Register);
5536 %}
5537 ins_pipe(iload_mask_mem);
5538 %}
5539
5540 // Load Unsigned Short/Char (16bit UNsigned)
5541 instruct loadUS(iRegI dst, memory mem) %{
5542 match(Set dst (LoadUS mem));
5543 ins_cost(MEMORY_REF_COST);
5544
5545 size(4);
5546 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5547 ins_encode %{
5548 __ lduh($mem$$Address, $dst$$Register);
5549 %}
5550 ins_pipe(iload_mem);
5551 %}
5552
5553 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5554 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5555 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5556 ins_cost(MEMORY_REF_COST);
5557
5558 size(4);
5559 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5560 ins_encode %{
5561 __ ldsb($mem$$Address, $dst$$Register, 1);
5562 %}
5563 ins_pipe(iload_mask_mem);
5564 %}
5565
5566 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5567 instruct loadUS2L(iRegL dst, memory mem) %{
5568 match(Set dst (ConvI2L (LoadUS mem)));
5569 ins_cost(MEMORY_REF_COST);
5570
5571 size(4);
5572 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5573 ins_encode %{
5574 __ lduh($mem$$Address, $dst$$Register);
5575 %}
5576 ins_pipe(iload_mem);
5577 %}
5578
5579 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5580 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5581 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5582 ins_cost(MEMORY_REF_COST);
5583
5584 size(4);
5585 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5586 ins_encode %{
5587 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5588 %}
5589 ins_pipe(iload_mem);
5590 %}
5591
5592 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5593 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5594 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5595 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5596
5597 size(2*4);
5598 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5599 "AND $dst,$mask,$dst" %}
5600 ins_encode %{
5601 Register Rdst = $dst$$Register;
5602 __ lduh($mem$$Address, Rdst);
5603 __ and3(Rdst, $mask$$constant, Rdst);
5604 %}
5605 ins_pipe(iload_mem);
5606 %}
5607
5608 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5609 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5610 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5611 effect(TEMP dst, TEMP tmp);
5612 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5613
5614 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5615 "SET right_n_bits($mask, 16),$tmp\n\t"
5616 "AND $dst,$tmp,$dst" %}
5617 ins_encode %{
5618 Register Rdst = $dst$$Register;
5619 Register Rtmp = $tmp$$Register;
5620 __ lduh($mem$$Address, Rdst);
5621 __ set($mask$$constant & right_n_bits(16), Rtmp);
5622 __ and3(Rdst, Rtmp, Rdst);
5623 %}
5624 ins_pipe(iload_mem);
5625 %}
5626
5627 // Load Integer
5628 instruct loadI(iRegI dst, memory mem) %{
5629 match(Set dst (LoadI mem));
5630 ins_cost(MEMORY_REF_COST);
5631
5632 size(4);
5633 format %{ "LDUW $mem,$dst\t! int" %}
5634 ins_encode %{
5635 __ lduw($mem$$Address, $dst$$Register);
5636 %}
5637 ins_pipe(iload_mem);
5638 %}
5639
5640 // Load Integer to Byte (8 bit signed)
5641 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5642 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5643 ins_cost(MEMORY_REF_COST);
5644
5645 size(4);
5646
5647 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5648 ins_encode %{
5649 __ ldsb($mem$$Address, $dst$$Register, 3);
5650 %}
5651 ins_pipe(iload_mask_mem);
5652 %}
5653
5654 // Load Integer to Unsigned Byte (8 bit UNsigned)
5655 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5656 match(Set dst (AndI (LoadI mem) mask));
5657 ins_cost(MEMORY_REF_COST);
5658
5659 size(4);
5660
5661 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5662 ins_encode %{
5663 __ ldub($mem$$Address, $dst$$Register, 3);
5664 %}
5665 ins_pipe(iload_mask_mem);
5666 %}
5667
5668 // Load Integer to Short (16 bit signed)
5669 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5670 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5671 ins_cost(MEMORY_REF_COST);
5672
5673 size(4);
5674
5675 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5676 ins_encode %{
5677 __ ldsh($mem$$Address, $dst$$Register, 2);
5678 %}
5679 ins_pipe(iload_mask_mem);
5680 %}
5681
5682 // Load Integer to Unsigned Short (16 bit UNsigned)
5683 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5684 match(Set dst (AndI (LoadI mem) mask));
5685 ins_cost(MEMORY_REF_COST);
5686
5687 size(4);
5688
5689 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5690 ins_encode %{
5691 __ lduh($mem$$Address, $dst$$Register, 2);
5692 %}
5693 ins_pipe(iload_mask_mem);
5694 %}
5695
5696 // Load Integer into a Long Register
5697 instruct loadI2L(iRegL dst, memory mem) %{
5698 match(Set dst (ConvI2L (LoadI mem)));
5699 ins_cost(MEMORY_REF_COST);
5700
5701 size(4);
5702 format %{ "LDSW $mem,$dst\t! int -> long" %}
5703 ins_encode %{
5704 __ ldsw($mem$$Address, $dst$$Register);
5705 %}
5706 ins_pipe(iload_mask_mem);
5707 %}
5708
5709 // Load Integer with mask 0xFF into a Long Register
5710 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5711 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5712 ins_cost(MEMORY_REF_COST);
5713
5714 size(4);
5715 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5716 ins_encode %{
5717 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5718 %}
5719 ins_pipe(iload_mem);
5720 %}
5721
5722 // Load Integer with mask 0xFFFF into a Long Register
5723 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5724 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5725 ins_cost(MEMORY_REF_COST);
5726
5727 size(4);
5728 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5729 ins_encode %{
5730 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5731 %}
5732 ins_pipe(iload_mem);
5733 %}
5734
5735 // Load Integer with a 12-bit mask into a Long Register
5736 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5737 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5738 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5739
5740 size(2*4);
5741 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5742 "AND $dst,$mask,$dst" %}
5743 ins_encode %{
5744 Register Rdst = $dst$$Register;
5745 __ lduw($mem$$Address, Rdst);
5746 __ and3(Rdst, $mask$$constant, Rdst);
5747 %}
5748 ins_pipe(iload_mem);
5749 %}
5750
5751 // Load Integer with a 31-bit mask into a Long Register
5752 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5753 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5754 effect(TEMP dst, TEMP tmp);
5755 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5756
5757 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5758 "SET $mask,$tmp\n\t"
5759 "AND $dst,$tmp,$dst" %}
5760 ins_encode %{
5761 Register Rdst = $dst$$Register;
5762 Register Rtmp = $tmp$$Register;
5763 __ lduw($mem$$Address, Rdst);
5764 __ set($mask$$constant, Rtmp);
5765 __ and3(Rdst, Rtmp, Rdst);
5766 %}
5767 ins_pipe(iload_mem);
5768 %}
5769
5770 // Load Unsigned Integer into a Long Register
5771 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5772 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5773 ins_cost(MEMORY_REF_COST);
5774
5775 size(4);
5776 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5777 ins_encode %{
5778 __ lduw($mem$$Address, $dst$$Register);
5779 %}
5780 ins_pipe(iload_mem);
5781 %}
5782
5783 // Load Long - aligned
5784 instruct loadL(iRegL dst, memory mem ) %{
5785 match(Set dst (LoadL mem));
5786 ins_cost(MEMORY_REF_COST);
5787
5788 size(4);
5789 format %{ "LDX $mem,$dst\t! long" %}
5790 ins_encode %{
5791 __ ldx($mem$$Address, $dst$$Register);
5792 %}
5793 ins_pipe(iload_mem);
5794 %}
5795
5796 // Load Long - UNaligned
5797 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5798 match(Set dst (LoadL_unaligned mem));
5799 effect(KILL tmp);
5800 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5801 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5802 "\tLDUW $mem ,$dst\n"
5803 "\tSLLX #32, $dst, $dst\n"
5804 "\tOR $dst, R_O7, $dst" %}
5805 opcode(Assembler::lduw_op3);
5806 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5807 ins_pipe(iload_mem);
5808 %}
5809
5810 // Load Range
5811 instruct loadRange(iRegI dst, memory mem) %{
5812 match(Set dst (LoadRange mem));
5813 ins_cost(MEMORY_REF_COST);
5814
5815 format %{ "LDUW $mem,$dst\t! range" %}
5816 opcode(Assembler::lduw_op3);
5817 ins_encode(simple_form3_mem_reg( mem, dst ) );
5818 ins_pipe(iload_mem);
5819 %}
5820
5821 // Load Integer into %f register (for fitos/fitod)
5822 instruct loadI_freg(regF dst, memory mem) %{
5823 match(Set dst (LoadI mem));
5824 ins_cost(MEMORY_REF_COST);
5825
5826 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5827 opcode(Assembler::ldf_op3);
5828 ins_encode(simple_form3_mem_reg( mem, dst ) );
5829 ins_pipe(floadF_mem);
5830 %}
5831
5832 // Load Pointer
5833 instruct loadP(iRegP dst, memory mem) %{
5834 match(Set dst (LoadP mem));
5835 ins_cost(MEMORY_REF_COST);
5836 size(4);
5837
5838 #ifndef _LP64
5839 format %{ "LDUW $mem,$dst\t! ptr" %}
5840 ins_encode %{
5841 __ lduw($mem$$Address, $dst$$Register);
5842 %}
5843 #else
5844 format %{ "LDX $mem,$dst\t! ptr" %}
5845 ins_encode %{
5846 __ ldx($mem$$Address, $dst$$Register);
5847 %}
5848 #endif
5849 ins_pipe(iload_mem);
5850 %}
5851
5852 // Load Compressed Pointer
5853 instruct loadN(iRegN dst, memory mem) %{
5854 match(Set dst (LoadN mem));
5855 ins_cost(MEMORY_REF_COST);
5856 size(4);
5857
5858 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5859 ins_encode %{
5860 __ lduw($mem$$Address, $dst$$Register);
5861 %}
5862 ins_pipe(iload_mem);
5863 %}
5864
5865 // Load Klass Pointer
5866 instruct loadKlass(iRegP dst, memory mem) %{
5867 match(Set dst (LoadKlass mem));
5868 ins_cost(MEMORY_REF_COST);
5869 size(4);
5870
5871 #ifndef _LP64
5872 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5873 ins_encode %{
5874 __ lduw($mem$$Address, $dst$$Register);
5875 %}
5876 #else
5877 format %{ "LDX $mem,$dst\t! klass ptr" %}
5878 ins_encode %{
5879 __ ldx($mem$$Address, $dst$$Register);
5880 %}
5881 #endif
5882 ins_pipe(iload_mem);
5883 %}
5884
5885 // Load narrow Klass Pointer
5886 instruct loadNKlass(iRegN dst, memory mem) %{
5887 match(Set dst (LoadNKlass mem));
5888 ins_cost(MEMORY_REF_COST);
5889 size(4);
5890
5891 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5892 ins_encode %{
5893 __ lduw($mem$$Address, $dst$$Register);
5894 %}
5895 ins_pipe(iload_mem);
5896 %}
5897
5898 // Load Double
5899 instruct loadD(regD dst, memory mem) %{
5900 match(Set dst (LoadD mem));
5901 ins_cost(MEMORY_REF_COST);
5902
5903 format %{ "LDDF $mem,$dst" %}
5904 opcode(Assembler::lddf_op3);
5905 ins_encode(simple_form3_mem_reg( mem, dst ) );
5906 ins_pipe(floadD_mem);
5907 %}
5908
5909 // Load Double - UNaligned
5910 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5911 match(Set dst (LoadD_unaligned mem));
5912 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5913 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5914 "\tLDF $mem+4,$dst.lo\t!" %}
5915 opcode(Assembler::ldf_op3);
5916 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5917 ins_pipe(iload_mem);
5918 %}
5919
5920 // Load Float
5921 instruct loadF(regF dst, memory mem) %{
5922 match(Set dst (LoadF mem));
5923 ins_cost(MEMORY_REF_COST);
5924
5925 format %{ "LDF $mem,$dst" %}
5926 opcode(Assembler::ldf_op3);
5927 ins_encode(simple_form3_mem_reg( mem, dst ) );
5928 ins_pipe(floadF_mem);
5929 %}
5930
5931 // Load Constant
5932 instruct loadConI( iRegI dst, immI src ) %{
5933 match(Set dst src);
5934 ins_cost(DEFAULT_COST * 3/2);
5935 format %{ "SET $src,$dst" %}
5936 ins_encode( Set32(src, dst) );
5937 ins_pipe(ialu_hi_lo_reg);
5938 %}
5939
5940 instruct loadConI13( iRegI dst, immI13 src ) %{
5941 match(Set dst src);
5942
5943 size(4);
5944 format %{ "MOV $src,$dst" %}
5945 ins_encode( Set13( src, dst ) );
5946 ins_pipe(ialu_imm);
5947 %}
5948
5949 #ifndef _LP64
5950 instruct loadConP(iRegP dst, immP con) %{
5951 match(Set dst con);
5952 ins_cost(DEFAULT_COST * 3/2);
5953 format %{ "SET $con,$dst\t!ptr" %}
5954 ins_encode %{
5955 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5956 intptr_t val = $con$$constant;
5957 if (constant_reloc == relocInfo::oop_type) {
5958 __ set_oop_constant((jobject) val, $dst$$Register);
5959 } else if (constant_reloc == relocInfo::metadata_type) {
5960 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5961 } else { // non-oop pointers, e.g. card mark base, heap top
5962 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5963 __ set(val, $dst$$Register);
5964 }
5965 %}
5966 ins_pipe(loadConP);
5967 %}
5968 #else
5969 instruct loadConP_set(iRegP dst, immP_set con) %{
5970 match(Set dst con);
5971 ins_cost(DEFAULT_COST * 3/2);
5972 format %{ "SET $con,$dst\t! ptr" %}
5973 ins_encode %{
5974 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5975 intptr_t val = $con$$constant;
5976 if (constant_reloc == relocInfo::oop_type) {
5977 __ set_oop_constant((jobject) val, $dst$$Register);
5978 } else if (constant_reloc == relocInfo::metadata_type) {
5979 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5980 } else { // non-oop pointers, e.g. card mark base, heap top
5981 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5982 __ set(val, $dst$$Register);
5983 }
5984 %}
5985 ins_pipe(loadConP);
5986 %}
5987
5988 instruct loadConP_load(iRegP dst, immP_load con) %{
5989 match(Set dst con);
5990 ins_cost(MEMORY_REF_COST);
5991 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5992 ins_encode %{
5993 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5994 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5995 %}
5996 ins_pipe(loadConP);
5997 %}
5998
5999 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6000 match(Set dst con);
6001 ins_cost(DEFAULT_COST * 3/2);
6002 format %{ "SET $con,$dst\t! non-oop ptr" %}
6003 ins_encode %{
6004 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
6005 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
6006 } else {
6007 __ set($con$$constant, $dst$$Register);
6008 }
6009 %}
6010 ins_pipe(loadConP);
6011 %}
6012 #endif // _LP64
6013
6014 instruct loadConP0(iRegP dst, immP0 src) %{
6015 match(Set dst src);
6016
6017 size(4);
6018 format %{ "CLR $dst\t!ptr" %}
6019 ins_encode %{
6020 __ clr($dst$$Register);
6021 %}
6022 ins_pipe(ialu_imm);
6023 %}
6024
6025 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6026 match(Set dst src);
6027 ins_cost(DEFAULT_COST);
6028 format %{ "SET $src,$dst\t!ptr" %}
6029 ins_encode %{
6030 AddressLiteral polling_page(os::get_polling_page());
6031 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6032 %}
6033 ins_pipe(loadConP_poll);
6034 %}
6035
6036 instruct loadConN0(iRegN dst, immN0 src) %{
6037 match(Set dst src);
6038
6039 size(4);
6040 format %{ "CLR $dst\t! compressed NULL ptr" %}
6041 ins_encode %{
6042 __ clr($dst$$Register);
6043 %}
6044 ins_pipe(ialu_imm);
6045 %}
6046
6047 instruct loadConN(iRegN dst, immN src) %{
6048 match(Set dst src);
6049 ins_cost(DEFAULT_COST * 3/2);
6050 format %{ "SET $src,$dst\t! compressed ptr" %}
6051 ins_encode %{
6052 Register dst = $dst$$Register;
6053 __ set_narrow_oop((jobject)$src$$constant, dst);
6054 %}
6055 ins_pipe(ialu_hi_lo_reg);
6056 %}
6057
6058 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6059 match(Set dst src);
6060 ins_cost(DEFAULT_COST * 3/2);
6061 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6062 ins_encode %{
6063 Register dst = $dst$$Register;
6064 __ set_narrow_klass((Klass*)$src$$constant, dst);
6065 %}
6066 ins_pipe(ialu_hi_lo_reg);
6067 %}
6068
6069 // Materialize long value (predicated by immL_cheap).
6070 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6071 match(Set dst con);
6072 effect(KILL tmp);
6073 ins_cost(DEFAULT_COST * 3);
6074 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6075 ins_encode %{
6076 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6077 %}
6078 ins_pipe(loadConL);
6079 %}
6080
6081 // Load long value from constant table (predicated by immL_expensive).
6082 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6083 match(Set dst con);
6084 ins_cost(MEMORY_REF_COST);
6085 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6086 ins_encode %{
6087 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6088 __ ldx($constanttablebase, con_offset, $dst$$Register);
6089 %}
6090 ins_pipe(loadConL);
6091 %}
6092
6093 instruct loadConL0( iRegL dst, immL0 src ) %{
6094 match(Set dst src);
6095 ins_cost(DEFAULT_COST);
6096 size(4);
6097 format %{ "CLR $dst\t! long" %}
6098 ins_encode( Set13( src, dst ) );
6099 ins_pipe(ialu_imm);
6100 %}
6101
6102 instruct loadConL13( iRegL dst, immL13 src ) %{
6103 match(Set dst src);
6104 ins_cost(DEFAULT_COST * 2);
6105
6106 size(4);
6107 format %{ "MOV $src,$dst\t! long" %}
6108 ins_encode( Set13( src, dst ) );
6109 ins_pipe(ialu_imm);
6110 %}
6111
6112 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6113 match(Set dst con);
6114 effect(KILL tmp);
6115 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6116 ins_encode %{
6117 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6118 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6119 %}
6120 ins_pipe(loadConFD);
6121 %}
6122
6123 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6124 match(Set dst con);
6125 effect(KILL tmp);
6126 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6127 ins_encode %{
6128 // XXX This is a quick fix for 6833573.
6129 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6130 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6131 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6132 %}
6133 ins_pipe(loadConFD);
6134 %}
6135
6136 // Prefetch instructions for allocation.
6137 // Must be safe to execute with invalid address (cannot fault).
6138
6139 instruct prefetchAlloc( memory mem ) %{
6140 predicate(AllocatePrefetchInstr == 0);
6141 match( PrefetchAllocation mem );
6142 ins_cost(MEMORY_REF_COST);
6143
6144 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6145 opcode(Assembler::prefetch_op3);
6146 ins_encode( form3_mem_prefetch_write( mem ) );
6147 ins_pipe(iload_mem);
6148 %}
6149
6150 // Use BIS instruction to prefetch for allocation.
6151 // Could fault, need space at the end of TLAB.
6152 instruct prefetchAlloc_bis( iRegP dst ) %{
6153 predicate(AllocatePrefetchInstr == 1);
6154 match( PrefetchAllocation dst );
6155 ins_cost(MEMORY_REF_COST);
6156 size(4);
6157
6158 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6159 ins_encode %{
6160 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6161 %}
6162 ins_pipe(istore_mem_reg);
6163 %}
6164
6165 // Next code is used for finding next cache line address to prefetch.
6166 #ifndef _LP64
6167 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6168 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6169 ins_cost(DEFAULT_COST);
6170 size(4);
6171
6172 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6173 ins_encode %{
6174 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6175 %}
6176 ins_pipe(ialu_reg_imm);
6177 %}
6178 #else
6179 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6180 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6181 ins_cost(DEFAULT_COST);
6182 size(4);
6183
6184 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6185 ins_encode %{
6186 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6187 %}
6188 ins_pipe(ialu_reg_imm);
6189 %}
6190 #endif
6191
6192 //----------Store Instructions-------------------------------------------------
6193 // Store Byte
6194 instruct storeB(memory mem, iRegI src) %{
6195 match(Set mem (StoreB mem src));
6196 ins_cost(MEMORY_REF_COST);
6197
6198 format %{ "STB $src,$mem\t! byte" %}
6199 opcode(Assembler::stb_op3);
6200 ins_encode(simple_form3_mem_reg( mem, src ) );
6201 ins_pipe(istore_mem_reg);
6202 %}
6203
6204 instruct storeB0(memory mem, immI0 src) %{
6205 match(Set mem (StoreB mem src));
6206 ins_cost(MEMORY_REF_COST);
6207
6208 format %{ "STB $src,$mem\t! byte" %}
6209 opcode(Assembler::stb_op3);
6210 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6211 ins_pipe(istore_mem_zero);
6212 %}
6213
6214 instruct storeCM0(memory mem, immI0 src) %{
6215 match(Set mem (StoreCM mem src));
6216 ins_cost(MEMORY_REF_COST);
6217
6218 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6219 opcode(Assembler::stb_op3);
6220 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6221 ins_pipe(istore_mem_zero);
6222 %}
6223
6224 // Store Char/Short
6225 instruct storeC(memory mem, iRegI src) %{
6226 match(Set mem (StoreC mem src));
6227 ins_cost(MEMORY_REF_COST);
6228
6229 format %{ "STH $src,$mem\t! short" %}
6230 opcode(Assembler::sth_op3);
6231 ins_encode(simple_form3_mem_reg( mem, src ) );
6232 ins_pipe(istore_mem_reg);
6233 %}
6234
6235 instruct storeC0(memory mem, immI0 src) %{
6236 match(Set mem (StoreC mem src));
6237 ins_cost(MEMORY_REF_COST);
6238
6239 format %{ "STH $src,$mem\t! short" %}
6240 opcode(Assembler::sth_op3);
6241 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6242 ins_pipe(istore_mem_zero);
6243 %}
6244
6245 // Store Integer
6246 instruct storeI(memory mem, iRegI src) %{
6247 match(Set mem (StoreI mem src));
6248 ins_cost(MEMORY_REF_COST);
6249
6250 format %{ "STW $src,$mem" %}
6251 opcode(Assembler::stw_op3);
6252 ins_encode(simple_form3_mem_reg( mem, src ) );
6253 ins_pipe(istore_mem_reg);
6254 %}
6255
6256 // Store Long
6257 instruct storeL(memory mem, iRegL src) %{
6258 match(Set mem (StoreL mem src));
6259 ins_cost(MEMORY_REF_COST);
6260 format %{ "STX $src,$mem\t! long" %}
6261 opcode(Assembler::stx_op3);
6262 ins_encode(simple_form3_mem_reg( mem, src ) );
6263 ins_pipe(istore_mem_reg);
6264 %}
6265
6266 instruct storeI0(memory mem, immI0 src) %{
6267 match(Set mem (StoreI mem src));
6268 ins_cost(MEMORY_REF_COST);
6269
6270 format %{ "STW $src,$mem" %}
6271 opcode(Assembler::stw_op3);
6272 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6273 ins_pipe(istore_mem_zero);
6274 %}
6275
6276 instruct storeL0(memory mem, immL0 src) %{
6277 match(Set mem (StoreL mem src));
6278 ins_cost(MEMORY_REF_COST);
6279
6280 format %{ "STX $src,$mem" %}
6281 opcode(Assembler::stx_op3);
6282 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6283 ins_pipe(istore_mem_zero);
6284 %}
6285
6286 // Store Integer from float register (used after fstoi)
6287 instruct storeI_Freg(memory mem, regF src) %{
6288 match(Set mem (StoreI mem src));
6289 ins_cost(MEMORY_REF_COST);
6290
6291 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6292 opcode(Assembler::stf_op3);
6293 ins_encode(simple_form3_mem_reg( mem, src ) );
6294 ins_pipe(fstoreF_mem_reg);
6295 %}
6296
6297 // Store Pointer
6298 instruct storeP(memory dst, sp_ptr_RegP src) %{
6299 match(Set dst (StoreP dst src));
6300 ins_cost(MEMORY_REF_COST);
6301
6302 #ifndef _LP64
6303 format %{ "STW $src,$dst\t! ptr" %}
6304 opcode(Assembler::stw_op3, 0, REGP_OP);
6305 #else
6306 format %{ "STX $src,$dst\t! ptr" %}
6307 opcode(Assembler::stx_op3, 0, REGP_OP);
6308 #endif
6309 ins_encode( form3_mem_reg( dst, src ) );
6310 ins_pipe(istore_mem_spORreg);
6311 %}
6312
6313 instruct storeP0(memory dst, immP0 src) %{
6314 match(Set dst (StoreP dst src));
6315 ins_cost(MEMORY_REF_COST);
6316
6317 #ifndef _LP64
6318 format %{ "STW $src,$dst\t! ptr" %}
6319 opcode(Assembler::stw_op3, 0, REGP_OP);
6320 #else
6321 format %{ "STX $src,$dst\t! ptr" %}
6322 opcode(Assembler::stx_op3, 0, REGP_OP);
6323 #endif
6324 ins_encode( form3_mem_reg( dst, R_G0 ) );
6325 ins_pipe(istore_mem_zero);
6326 %}
6327
6328 // Store Compressed Pointer
6329 instruct storeN(memory dst, iRegN src) %{
6330 match(Set dst (StoreN dst src));
6331 ins_cost(MEMORY_REF_COST);
6332 size(4);
6333
6334 format %{ "STW $src,$dst\t! compressed ptr" %}
6335 ins_encode %{
6336 Register base = as_Register($dst$$base);
6337 Register index = as_Register($dst$$index);
6338 Register src = $src$$Register;
6339 if (index != G0) {
6340 __ stw(src, base, index);
6341 } else {
6342 __ stw(src, base, $dst$$disp);
6343 }
6344 %}
6345 ins_pipe(istore_mem_spORreg);
6346 %}
6347
6348 instruct storeNKlass(memory dst, iRegN src) %{
6349 match(Set dst (StoreNKlass dst src));
6350 ins_cost(MEMORY_REF_COST);
6351 size(4);
6352
6353 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6354 ins_encode %{
6355 Register base = as_Register($dst$$base);
6356 Register index = as_Register($dst$$index);
6357 Register src = $src$$Register;
6358 if (index != G0) {
6359 __ stw(src, base, index);
6360 } else {
6361 __ stw(src, base, $dst$$disp);
6362 }
6363 %}
6364 ins_pipe(istore_mem_spORreg);
6365 %}
6366
6367 instruct storeN0(memory dst, immN0 src) %{
6368 match(Set dst (StoreN dst src));
6369 ins_cost(MEMORY_REF_COST);
6370 size(4);
6371
6372 format %{ "STW $src,$dst\t! compressed ptr" %}
6373 ins_encode %{
6374 Register base = as_Register($dst$$base);
6375 Register index = as_Register($dst$$index);
6376 if (index != G0) {
6377 __ stw(0, base, index);
6378 } else {
6379 __ stw(0, base, $dst$$disp);
6380 }
6381 %}
6382 ins_pipe(istore_mem_zero);
6383 %}
6384
6385 // Store Double
6386 instruct storeD( memory mem, regD src) %{
6387 match(Set mem (StoreD mem src));
6388 ins_cost(MEMORY_REF_COST);
6389
6390 format %{ "STDF $src,$mem" %}
6391 opcode(Assembler::stdf_op3);
6392 ins_encode(simple_form3_mem_reg( mem, src ) );
6393 ins_pipe(fstoreD_mem_reg);
6394 %}
6395
6396 instruct storeD0( memory mem, immD0 src) %{
6397 match(Set mem (StoreD mem src));
6398 ins_cost(MEMORY_REF_COST);
6399
6400 format %{ "STX $src,$mem" %}
6401 opcode(Assembler::stx_op3);
6402 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6403 ins_pipe(fstoreD_mem_zero);
6404 %}
6405
6406 // Store Float
6407 instruct storeF( memory mem, regF src) %{
6408 match(Set mem (StoreF mem src));
6409 ins_cost(MEMORY_REF_COST);
6410
6411 format %{ "STF $src,$mem" %}
6412 opcode(Assembler::stf_op3);
6413 ins_encode(simple_form3_mem_reg( mem, src ) );
6414 ins_pipe(fstoreF_mem_reg);
6415 %}
6416
6417 instruct storeF0( memory mem, immF0 src) %{
6418 match(Set mem (StoreF mem src));
6419 ins_cost(MEMORY_REF_COST);
6420
6421 format %{ "STW $src,$mem\t! storeF0" %}
6422 opcode(Assembler::stw_op3);
6423 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6424 ins_pipe(fstoreF_mem_zero);
6425 %}
6426
6427 // Convert oop pointer into compressed form
6428 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6429 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6430 match(Set dst (EncodeP src));
6431 format %{ "encode_heap_oop $src, $dst" %}
6432 ins_encode %{
6433 __ encode_heap_oop($src$$Register, $dst$$Register);
6434 %}
6435 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6436 ins_pipe(ialu_reg);
6437 %}
6438
6439 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6440 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6441 match(Set dst (EncodeP src));
6442 format %{ "encode_heap_oop_not_null $src, $dst" %}
6443 ins_encode %{
6444 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6445 %}
6446 ins_pipe(ialu_reg);
6447 %}
6448
6449 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6450 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6451 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6452 match(Set dst (DecodeN src));
6453 format %{ "decode_heap_oop $src, $dst" %}
6454 ins_encode %{
6455 __ decode_heap_oop($src$$Register, $dst$$Register);
6456 %}
6457 ins_pipe(ialu_reg);
6458 %}
6459
6460 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6461 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6462 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6463 match(Set dst (DecodeN src));
6464 format %{ "decode_heap_oop_not_null $src, $dst" %}
6465 ins_encode %{
6466 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6467 %}
6468 ins_pipe(ialu_reg);
6469 %}
6470
6471 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6472 match(Set dst (EncodePKlass src));
6473 format %{ "encode_klass_not_null $src, $dst" %}
6474 ins_encode %{
6475 __ encode_klass_not_null($src$$Register, $dst$$Register);
6476 %}
6477 ins_pipe(ialu_reg);
6478 %}
6479
6480 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6481 match(Set dst (DecodeNKlass src));
6482 format %{ "decode_klass_not_null $src, $dst" %}
6483 ins_encode %{
6484 __ decode_klass_not_null($src$$Register, $dst$$Register);
6485 %}
6486 ins_pipe(ialu_reg);
6487 %}
6488
6489 //----------MemBar Instructions-----------------------------------------------
6490 // Memory barrier flavors
6491
6492 instruct membar_acquire() %{
6493 match(MemBarAcquire);
6494 match(LoadFence);
6495 ins_cost(4*MEMORY_REF_COST);
6496
6497 size(0);
6498 format %{ "MEMBAR-acquire" %}
6499 ins_encode( enc_membar_acquire );
6500 ins_pipe(long_memory_op);
6501 %}
6502
6503 instruct membar_acquire_lock() %{
6504 match(MemBarAcquireLock);
6505 ins_cost(0);
6506
6507 size(0);
6508 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6509 ins_encode( );
6510 ins_pipe(empty);
6511 %}
6512
6513 instruct membar_release() %{
6514 match(MemBarRelease);
6515 match(StoreFence);
6516 ins_cost(4*MEMORY_REF_COST);
6517
6518 size(0);
6519 format %{ "MEMBAR-release" %}
6520 ins_encode( enc_membar_release );
6521 ins_pipe(long_memory_op);
6522 %}
6523
6524 instruct membar_release_lock() %{
6525 match(MemBarReleaseLock);
6526 ins_cost(0);
6527
6528 size(0);
6529 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6530 ins_encode( );
6531 ins_pipe(empty);
6532 %}
6533
6534 instruct membar_volatile() %{
6535 match(MemBarVolatile);
6536 ins_cost(4*MEMORY_REF_COST);
6537
6538 size(4);
6539 format %{ "MEMBAR-volatile" %}
6540 ins_encode( enc_membar_volatile );
6541 ins_pipe(long_memory_op);
6542 %}
6543
6544 instruct unnecessary_membar_volatile() %{
6545 match(MemBarVolatile);
6546 predicate(Matcher::post_store_load_barrier(n));
6547 ins_cost(0);
6548
6549 size(0);
6550 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6551 ins_encode( );
6552 ins_pipe(empty);
6553 %}
6554
6555 instruct membar_storestore() %{
6556 match(MemBarStoreStore);
6557 ins_cost(0);
6558
6559 size(0);
6560 format %{ "!MEMBAR-storestore (empty encoding)" %}
6561 ins_encode( );
6562 ins_pipe(empty);
6563 %}
6564
6565 //----------Register Move Instructions-----------------------------------------
6566 instruct roundDouble_nop(regD dst) %{
6567 match(Set dst (RoundDouble dst));
6568 ins_cost(0);
6569 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6570 ins_encode( );
6571 ins_pipe(empty);
6572 %}
6573
6574
6575 instruct roundFloat_nop(regF dst) %{
6576 match(Set dst (RoundFloat dst));
6577 ins_cost(0);
6578 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6579 ins_encode( );
6580 ins_pipe(empty);
6581 %}
6582
6583
6584 // Cast Index to Pointer for unsafe natives
6585 instruct castX2P(iRegX src, iRegP dst) %{
6586 match(Set dst (CastX2P src));
6587
6588 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6589 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6590 ins_pipe(ialu_reg);
6591 %}
6592
6593 // Cast Pointer to Index for unsafe natives
6594 instruct castP2X(iRegP src, iRegX dst) %{
6595 match(Set dst (CastP2X src));
6596
6597 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6598 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6599 ins_pipe(ialu_reg);
6600 %}
6601
6602 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6603 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6604 match(Set stkSlot src); // chain rule
6605 ins_cost(MEMORY_REF_COST);
6606 format %{ "STDF $src,$stkSlot\t!stk" %}
6607 opcode(Assembler::stdf_op3);
6608 ins_encode(simple_form3_mem_reg(stkSlot, src));
6609 ins_pipe(fstoreD_stk_reg);
6610 %}
6611
6612 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6613 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6614 match(Set dst stkSlot); // chain rule
6615 ins_cost(MEMORY_REF_COST);
6616 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6617 opcode(Assembler::lddf_op3);
6618 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6619 ins_pipe(floadD_stk);
6620 %}
6621
6622 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6623 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6624 match(Set stkSlot src); // chain rule
6625 ins_cost(MEMORY_REF_COST);
6626 format %{ "STF $src,$stkSlot\t!stk" %}
6627 opcode(Assembler::stf_op3);
6628 ins_encode(simple_form3_mem_reg(stkSlot, src));
6629 ins_pipe(fstoreF_stk_reg);
6630 %}
6631
6632 //----------Conditional Move---------------------------------------------------
6633 // Conditional move
6634 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6635 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6636 ins_cost(150);
6637 format %{ "MOV$cmp $pcc,$src,$dst" %}
6638 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6639 ins_pipe(ialu_reg);
6640 %}
6641
6642 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6643 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6644 ins_cost(140);
6645 format %{ "MOV$cmp $pcc,$src,$dst" %}
6646 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6647 ins_pipe(ialu_imm);
6648 %}
6649
6650 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6651 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6652 ins_cost(150);
6653 size(4);
6654 format %{ "MOV$cmp $icc,$src,$dst" %}
6655 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6656 ins_pipe(ialu_reg);
6657 %}
6658
6659 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6660 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6661 ins_cost(140);
6662 size(4);
6663 format %{ "MOV$cmp $icc,$src,$dst" %}
6664 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6665 ins_pipe(ialu_imm);
6666 %}
6667
6668 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6669 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6670 ins_cost(150);
6671 size(4);
6672 format %{ "MOV$cmp $icc,$src,$dst" %}
6673 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6674 ins_pipe(ialu_reg);
6675 %}
6676
6677 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6678 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6679 ins_cost(140);
6680 size(4);
6681 format %{ "MOV$cmp $icc,$src,$dst" %}
6682 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6683 ins_pipe(ialu_imm);
6684 %}
6685
6686 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6687 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6688 ins_cost(150);
6689 size(4);
6690 format %{ "MOV$cmp $fcc,$src,$dst" %}
6691 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6692 ins_pipe(ialu_reg);
6693 %}
6694
6695 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6696 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6697 ins_cost(140);
6698 size(4);
6699 format %{ "MOV$cmp $fcc,$src,$dst" %}
6700 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6701 ins_pipe(ialu_imm);
6702 %}
6703
6704 // Conditional move for RegN. Only cmov(reg,reg).
6705 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6706 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6707 ins_cost(150);
6708 format %{ "MOV$cmp $pcc,$src,$dst" %}
6709 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6710 ins_pipe(ialu_reg);
6711 %}
6712
6713 // This instruction also works with CmpN so we don't need cmovNN_reg.
6714 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6715 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6716 ins_cost(150);
6717 size(4);
6718 format %{ "MOV$cmp $icc,$src,$dst" %}
6719 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6720 ins_pipe(ialu_reg);
6721 %}
6722
6723 // This instruction also works with CmpN so we don't need cmovNN_reg.
6724 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6725 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6726 ins_cost(150);
6727 size(4);
6728 format %{ "MOV$cmp $icc,$src,$dst" %}
6729 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6730 ins_pipe(ialu_reg);
6731 %}
6732
6733 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6734 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6735 ins_cost(150);
6736 size(4);
6737 format %{ "MOV$cmp $fcc,$src,$dst" %}
6738 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6739 ins_pipe(ialu_reg);
6740 %}
6741
6742 // Conditional move
6743 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6744 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6745 ins_cost(150);
6746 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6747 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6748 ins_pipe(ialu_reg);
6749 %}
6750
6751 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6752 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6753 ins_cost(140);
6754 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6755 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6756 ins_pipe(ialu_imm);
6757 %}
6758
6759 // This instruction also works with CmpN so we don't need cmovPN_reg.
6760 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6761 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6762 ins_cost(150);
6763
6764 size(4);
6765 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6766 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6767 ins_pipe(ialu_reg);
6768 %}
6769
6770 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6771 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6772 ins_cost(150);
6773
6774 size(4);
6775 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6776 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6777 ins_pipe(ialu_reg);
6778 %}
6779
6780 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6781 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6782 ins_cost(140);
6783
6784 size(4);
6785 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6786 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6787 ins_pipe(ialu_imm);
6788 %}
6789
6790 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6791 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6792 ins_cost(140);
6793
6794 size(4);
6795 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6796 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6797 ins_pipe(ialu_imm);
6798 %}
6799
6800 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6801 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6802 ins_cost(150);
6803 size(4);
6804 format %{ "MOV$cmp $fcc,$src,$dst" %}
6805 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6806 ins_pipe(ialu_imm);
6807 %}
6808
6809 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6810 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6811 ins_cost(140);
6812 size(4);
6813 format %{ "MOV$cmp $fcc,$src,$dst" %}
6814 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6815 ins_pipe(ialu_imm);
6816 %}
6817
6818 // Conditional move
6819 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6820 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6821 ins_cost(150);
6822 opcode(0x101);
6823 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6824 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6825 ins_pipe(int_conditional_float_move);
6826 %}
6827
6828 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6829 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6830 ins_cost(150);
6831
6832 size(4);
6833 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6834 opcode(0x101);
6835 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6836 ins_pipe(int_conditional_float_move);
6837 %}
6838
6839 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6840 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6841 ins_cost(150);
6842
6843 size(4);
6844 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6845 opcode(0x101);
6846 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6847 ins_pipe(int_conditional_float_move);
6848 %}
6849
6850 // Conditional move,
6851 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6852 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6853 ins_cost(150);
6854 size(4);
6855 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6856 opcode(0x1);
6857 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6858 ins_pipe(int_conditional_double_move);
6859 %}
6860
6861 // Conditional move
6862 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6863 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6864 ins_cost(150);
6865 size(4);
6866 opcode(0x102);
6867 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6868 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6869 ins_pipe(int_conditional_double_move);
6870 %}
6871
6872 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6873 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6874 ins_cost(150);
6875
6876 size(4);
6877 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6878 opcode(0x102);
6879 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6880 ins_pipe(int_conditional_double_move);
6881 %}
6882
6883 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6884 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6885 ins_cost(150);
6886
6887 size(4);
6888 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6889 opcode(0x102);
6890 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6891 ins_pipe(int_conditional_double_move);
6892 %}
6893
6894 // Conditional move,
6895 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6896 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6897 ins_cost(150);
6898 size(4);
6899 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6900 opcode(0x2);
6901 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6902 ins_pipe(int_conditional_double_move);
6903 %}
6904
6905 // Conditional move
6906 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6907 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6908 ins_cost(150);
6909 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6910 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6911 ins_pipe(ialu_reg);
6912 %}
6913
6914 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6915 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6916 ins_cost(140);
6917 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6918 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6919 ins_pipe(ialu_imm);
6920 %}
6921
6922 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6923 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6924 ins_cost(150);
6925
6926 size(4);
6927 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6928 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6929 ins_pipe(ialu_reg);
6930 %}
6931
6932
6933 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6934 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6935 ins_cost(150);
6936
6937 size(4);
6938 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6939 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6940 ins_pipe(ialu_reg);
6941 %}
6942
6943
6944 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6945 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6946 ins_cost(150);
6947
6948 size(4);
6949 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6950 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6951 ins_pipe(ialu_reg);
6952 %}
6953
6954
6955
6956 //----------OS and Locking Instructions----------------------------------------
6957
6958 // This name is KNOWN by the ADLC and cannot be changed.
6959 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6960 // for this guy.
6961 instruct tlsLoadP(g2RegP dst) %{
6962 match(Set dst (ThreadLocal));
6963
6964 size(0);
6965 ins_cost(0);
6966 format %{ "# TLS is in G2" %}
6967 ins_encode( /*empty encoding*/ );
6968 ins_pipe(ialu_none);
6969 %}
6970
6971 instruct checkCastPP( iRegP dst ) %{
6972 match(Set dst (CheckCastPP dst));
6973
6974 size(0);
6975 format %{ "# checkcastPP of $dst" %}
6976 ins_encode( /*empty encoding*/ );
6977 ins_pipe(empty);
6978 %}
6979
6980
6981 instruct castPP( iRegP dst ) %{
6982 match(Set dst (CastPP dst));
6983 format %{ "# castPP of $dst" %}
6984 ins_encode( /*empty encoding*/ );
6985 ins_pipe(empty);
6986 %}
6987
6988 instruct castII( iRegI dst ) %{
6989 match(Set dst (CastII dst));
6990 format %{ "# castII of $dst" %}
6991 ins_encode( /*empty encoding*/ );
6992 ins_cost(0);
6993 ins_pipe(empty);
6994 %}
6995
6996 //----------Arithmetic Instructions--------------------------------------------
6997 // Addition Instructions
6998 // Register Addition
6999 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7000 match(Set dst (AddI src1 src2));
7001
7002 size(4);
7003 format %{ "ADD $src1,$src2,$dst" %}
7004 ins_encode %{
7005 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7006 %}
7007 ins_pipe(ialu_reg_reg);
7008 %}
7009
7010 // Immediate Addition
7011 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7012 match(Set dst (AddI src1 src2));
7013
7014 size(4);
7015 format %{ "ADD $src1,$src2,$dst" %}
7016 opcode(Assembler::add_op3, Assembler::arith_op);
7017 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7018 ins_pipe(ialu_reg_imm);
7019 %}
7020
7021 // Pointer Register Addition
7022 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7023 match(Set dst (AddP src1 src2));
7024
7025 size(4);
7026 format %{ "ADD $src1,$src2,$dst" %}
7027 opcode(Assembler::add_op3, Assembler::arith_op);
7028 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7029 ins_pipe(ialu_reg_reg);
7030 %}
7031
7032 // Pointer Immediate Addition
7033 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7034 match(Set dst (AddP src1 src2));
7035
7036 size(4);
7037 format %{ "ADD $src1,$src2,$dst" %}
7038 opcode(Assembler::add_op3, Assembler::arith_op);
7039 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7040 ins_pipe(ialu_reg_imm);
7041 %}
7042
7043 // Long Addition
7044 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7045 match(Set dst (AddL src1 src2));
7046
7047 size(4);
7048 format %{ "ADD $src1,$src2,$dst\t! long" %}
7049 opcode(Assembler::add_op3, Assembler::arith_op);
7050 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7051 ins_pipe(ialu_reg_reg);
7052 %}
7053
7054 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7055 match(Set dst (AddL src1 con));
7056
7057 size(4);
7058 format %{ "ADD $src1,$con,$dst" %}
7059 opcode(Assembler::add_op3, Assembler::arith_op);
7060 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7061 ins_pipe(ialu_reg_imm);
7062 %}
7063
7064 //----------Conditional_store--------------------------------------------------
7065 // Conditional-store of the updated heap-top.
7066 // Used during allocation of the shared heap.
7067 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7068
7069 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7070 instruct loadPLocked(iRegP dst, memory mem) %{
7071 match(Set dst (LoadPLocked mem));
7072 ins_cost(MEMORY_REF_COST);
7073
7074 #ifndef _LP64
7075 format %{ "LDUW $mem,$dst\t! ptr" %}
7076 opcode(Assembler::lduw_op3, 0, REGP_OP);
7077 #else
7078 format %{ "LDX $mem,$dst\t! ptr" %}
7079 opcode(Assembler::ldx_op3, 0, REGP_OP);
7080 #endif
7081 ins_encode( form3_mem_reg( mem, dst ) );
7082 ins_pipe(iload_mem);
7083 %}
7084
7085 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7086 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7087 effect( KILL newval );
7088 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7089 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7090 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7091 ins_pipe( long_memory_op );
7092 %}
7093
7094 // Conditional-store of an int value.
7095 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7096 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7097 effect( KILL newval );
7098 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7099 "CMP $oldval,$newval\t\t! See if we made progress" %}
7100 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7101 ins_pipe( long_memory_op );
7102 %}
7103
7104 // Conditional-store of a long value.
7105 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7106 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7107 effect( KILL newval );
7108 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7109 "CMP $oldval,$newval\t\t! See if we made progress" %}
7110 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7111 ins_pipe( long_memory_op );
7112 %}
7113
7114 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7115
7116 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7117 predicate(VM_Version::supports_cx8());
7118 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7119 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7120 format %{
7121 "MOV $newval,O7\n\t"
7122 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7123 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7124 "MOV 1,$res\n\t"
7125 "MOVne xcc,R_G0,$res"
7126 %}
7127 ins_encode( enc_casx(mem_ptr, oldval, newval),
7128 enc_lflags_ne_to_boolean(res) );
7129 ins_pipe( long_memory_op );
7130 %}
7131
7132
7133 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7134 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7135 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7136 format %{
7137 "MOV $newval,O7\n\t"
7138 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7139 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7140 "MOV 1,$res\n\t"
7141 "MOVne icc,R_G0,$res"
7142 %}
7143 ins_encode( enc_casi(mem_ptr, oldval, newval),
7144 enc_iflags_ne_to_boolean(res) );
7145 ins_pipe( long_memory_op );
7146 %}
7147
7148 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7149 #ifdef _LP64
7150 predicate(VM_Version::supports_cx8());
7151 #endif
7152 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7153 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7154 format %{
7155 "MOV $newval,O7\n\t"
7156 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7157 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7158 "MOV 1,$res\n\t"
7159 "MOVne xcc,R_G0,$res"
7160 %}
7161 #ifdef _LP64
7162 ins_encode( enc_casx(mem_ptr, oldval, newval),
7163 enc_lflags_ne_to_boolean(res) );
7164 #else
7165 ins_encode( enc_casi(mem_ptr, oldval, newval),
7166 enc_iflags_ne_to_boolean(res) );
7167 #endif
7168 ins_pipe( long_memory_op );
7169 %}
7170
7171 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7172 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7173 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7174 format %{
7175 "MOV $newval,O7\n\t"
7176 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7177 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7178 "MOV 1,$res\n\t"
7179 "MOVne icc,R_G0,$res"
7180 %}
7181 ins_encode( enc_casi(mem_ptr, oldval, newval),
7182 enc_iflags_ne_to_boolean(res) );
7183 ins_pipe( long_memory_op );
7184 %}
7185
7186 instruct xchgI( memory mem, iRegI newval) %{
7187 match(Set newval (GetAndSetI mem newval));
7188 format %{ "SWAP [$mem],$newval" %}
7189 size(4);
7190 ins_encode %{
7191 __ swap($mem$$Address, $newval$$Register);
7192 %}
7193 ins_pipe( long_memory_op );
7194 %}
7195
7196 #ifndef _LP64
7197 instruct xchgP( memory mem, iRegP newval) %{
7198 match(Set newval (GetAndSetP mem newval));
7199 format %{ "SWAP [$mem],$newval" %}
7200 size(4);
7201 ins_encode %{
7202 __ swap($mem$$Address, $newval$$Register);
7203 %}
7204 ins_pipe( long_memory_op );
7205 %}
7206 #endif
7207
7208 instruct xchgN( memory mem, iRegN newval) %{
7209 match(Set newval (GetAndSetN mem newval));
7210 format %{ "SWAP [$mem],$newval" %}
7211 size(4);
7212 ins_encode %{
7213 __ swap($mem$$Address, $newval$$Register);
7214 %}
7215 ins_pipe( long_memory_op );
7216 %}
7217
7218 //---------------------
7219 // Subtraction Instructions
7220 // Register Subtraction
7221 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7222 match(Set dst (SubI src1 src2));
7223
7224 size(4);
7225 format %{ "SUB $src1,$src2,$dst" %}
7226 opcode(Assembler::sub_op3, Assembler::arith_op);
7227 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7228 ins_pipe(ialu_reg_reg);
7229 %}
7230
7231 // Immediate Subtraction
7232 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7233 match(Set dst (SubI src1 src2));
7234
7235 size(4);
7236 format %{ "SUB $src1,$src2,$dst" %}
7237 opcode(Assembler::sub_op3, Assembler::arith_op);
7238 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7239 ins_pipe(ialu_reg_imm);
7240 %}
7241
7242 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7243 match(Set dst (SubI zero src2));
7244
7245 size(4);
7246 format %{ "NEG $src2,$dst" %}
7247 opcode(Assembler::sub_op3, Assembler::arith_op);
7248 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7249 ins_pipe(ialu_zero_reg);
7250 %}
7251
7252 // Long subtraction
7253 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7254 match(Set dst (SubL src1 src2));
7255
7256 size(4);
7257 format %{ "SUB $src1,$src2,$dst\t! long" %}
7258 opcode(Assembler::sub_op3, Assembler::arith_op);
7259 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7260 ins_pipe(ialu_reg_reg);
7261 %}
7262
7263 // Immediate Subtraction
7264 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7265 match(Set dst (SubL src1 con));
7266
7267 size(4);
7268 format %{ "SUB $src1,$con,$dst\t! long" %}
7269 opcode(Assembler::sub_op3, Assembler::arith_op);
7270 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7271 ins_pipe(ialu_reg_imm);
7272 %}
7273
7274 // Long negation
7275 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7276 match(Set dst (SubL zero src2));
7277
7278 size(4);
7279 format %{ "NEG $src2,$dst\t! long" %}
7280 opcode(Assembler::sub_op3, Assembler::arith_op);
7281 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7282 ins_pipe(ialu_zero_reg);
7283 %}
7284
7285 // Multiplication Instructions
7286 // Integer Multiplication
7287 // Register Multiplication
7288 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7289 match(Set dst (MulI src1 src2));
7290
7291 size(4);
7292 format %{ "MULX $src1,$src2,$dst" %}
7293 opcode(Assembler::mulx_op3, Assembler::arith_op);
7294 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7295 ins_pipe(imul_reg_reg);
7296 %}
7297
7298 // Immediate Multiplication
7299 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7300 match(Set dst (MulI src1 src2));
7301
7302 size(4);
7303 format %{ "MULX $src1,$src2,$dst" %}
7304 opcode(Assembler::mulx_op3, Assembler::arith_op);
7305 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7306 ins_pipe(imul_reg_imm);
7307 %}
7308
7309 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7310 match(Set dst (MulL src1 src2));
7311 ins_cost(DEFAULT_COST * 5);
7312 size(4);
7313 format %{ "MULX $src1,$src2,$dst\t! long" %}
7314 opcode(Assembler::mulx_op3, Assembler::arith_op);
7315 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7316 ins_pipe(mulL_reg_reg);
7317 %}
7318
7319 // Immediate Multiplication
7320 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7321 match(Set dst (MulL src1 src2));
7322 ins_cost(DEFAULT_COST * 5);
7323 size(4);
7324 format %{ "MULX $src1,$src2,$dst" %}
7325 opcode(Assembler::mulx_op3, Assembler::arith_op);
7326 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7327 ins_pipe(mulL_reg_imm);
7328 %}
7329
7330 // Integer Division
7331 // Register Division
7332 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7333 match(Set dst (DivI src1 src2));
7334 ins_cost((2+71)*DEFAULT_COST);
7335
7336 format %{ "SRA $src2,0,$src2\n\t"
7337 "SRA $src1,0,$src1\n\t"
7338 "SDIVX $src1,$src2,$dst" %}
7339 ins_encode( idiv_reg( src1, src2, dst ) );
7340 ins_pipe(sdiv_reg_reg);
7341 %}
7342
7343 // Immediate Division
7344 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7345 match(Set dst (DivI src1 src2));
7346 ins_cost((2+71)*DEFAULT_COST);
7347
7348 format %{ "SRA $src1,0,$src1\n\t"
7349 "SDIVX $src1,$src2,$dst" %}
7350 ins_encode( idiv_imm( src1, src2, dst ) );
7351 ins_pipe(sdiv_reg_imm);
7352 %}
7353
7354 //----------Div-By-10-Expansion------------------------------------------------
7355 // Extract hi bits of a 32x32->64 bit multiply.
7356 // Expand rule only, not matched
7357 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7358 effect( DEF dst, USE src1, USE src2 );
7359 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7360 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7361 ins_encode( enc_mul_hi(dst,src1,src2));
7362 ins_pipe(sdiv_reg_reg);
7363 %}
7364
7365 // Magic constant, reciprocal of 10
7366 instruct loadConI_x66666667(iRegIsafe dst) %{
7367 effect( DEF dst );
7368
7369 size(8);
7370 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7371 ins_encode( Set32(0x66666667, dst) );
7372 ins_pipe(ialu_hi_lo_reg);
7373 %}
7374
7375 // Register Shift Right Arithmetic Long by 32-63
7376 instruct sra_31( iRegI dst, iRegI src ) %{
7377 effect( DEF dst, USE src );
7378 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7379 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7380 ins_pipe(ialu_reg_reg);
7381 %}
7382
7383 // Arithmetic Shift Right by 8-bit immediate
7384 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7385 effect( DEF dst, USE src );
7386 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7387 opcode(Assembler::sra_op3, Assembler::arith_op);
7388 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7389 ins_pipe(ialu_reg_imm);
7390 %}
7391
7392 // Integer DIV with 10
7393 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7394 match(Set dst (DivI src div));
7395 ins_cost((6+6)*DEFAULT_COST);
7396 expand %{
7397 iRegIsafe tmp1; // Killed temps;
7398 iRegIsafe tmp2; // Killed temps;
7399 iRegI tmp3; // Killed temps;
7400 iRegI tmp4; // Killed temps;
7401 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7402 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7403 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7404 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7405 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7406 %}
7407 %}
7408
7409 // Register Long Division
7410 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7411 match(Set dst (DivL src1 src2));
7412 ins_cost(DEFAULT_COST*71);
7413 size(4);
7414 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7415 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7416 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7417 ins_pipe(divL_reg_reg);
7418 %}
7419
7420 // Register Long Division
7421 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7422 match(Set dst (DivL src1 src2));
7423 ins_cost(DEFAULT_COST*71);
7424 size(4);
7425 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7426 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7427 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7428 ins_pipe(divL_reg_imm);
7429 %}
7430
7431 // Integer Remainder
7432 // Register Remainder
7433 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7434 match(Set dst (ModI src1 src2));
7435 effect( KILL ccr, KILL temp);
7436
7437 format %{ "SREM $src1,$src2,$dst" %}
7438 ins_encode( irem_reg(src1, src2, dst, temp) );
7439 ins_pipe(sdiv_reg_reg);
7440 %}
7441
7442 // Immediate Remainder
7443 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7444 match(Set dst (ModI src1 src2));
7445 effect( KILL ccr, KILL temp);
7446
7447 format %{ "SREM $src1,$src2,$dst" %}
7448 ins_encode( irem_imm(src1, src2, dst, temp) );
7449 ins_pipe(sdiv_reg_imm);
7450 %}
7451
7452 // Register Long Remainder
7453 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7454 effect(DEF dst, USE src1, USE src2);
7455 size(4);
7456 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7457 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7458 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7459 ins_pipe(divL_reg_reg);
7460 %}
7461
7462 // Register Long Division
7463 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7464 effect(DEF dst, USE src1, USE src2);
7465 size(4);
7466 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7467 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7468 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7469 ins_pipe(divL_reg_imm);
7470 %}
7471
7472 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7473 effect(DEF dst, USE src1, USE src2);
7474 size(4);
7475 format %{ "MULX $src1,$src2,$dst\t! long" %}
7476 opcode(Assembler::mulx_op3, Assembler::arith_op);
7477 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7478 ins_pipe(mulL_reg_reg);
7479 %}
7480
7481 // Immediate Multiplication
7482 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7483 effect(DEF dst, USE src1, USE src2);
7484 size(4);
7485 format %{ "MULX $src1,$src2,$dst" %}
7486 opcode(Assembler::mulx_op3, Assembler::arith_op);
7487 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7488 ins_pipe(mulL_reg_imm);
7489 %}
7490
7491 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7492 effect(DEF dst, USE src1, USE src2);
7493 size(4);
7494 format %{ "SUB $src1,$src2,$dst\t! long" %}
7495 opcode(Assembler::sub_op3, Assembler::arith_op);
7496 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7497 ins_pipe(ialu_reg_reg);
7498 %}
7499
7500 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7501 effect(DEF dst, USE src1, USE src2);
7502 size(4);
7503 format %{ "SUB $src1,$src2,$dst\t! long" %}
7504 opcode(Assembler::sub_op3, Assembler::arith_op);
7505 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7506 ins_pipe(ialu_reg_reg);
7507 %}
7508
7509 // Register Long Remainder
7510 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7511 match(Set dst (ModL src1 src2));
7512 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7513 expand %{
7514 iRegL tmp1;
7515 iRegL tmp2;
7516 divL_reg_reg_1(tmp1, src1, src2);
7517 mulL_reg_reg_1(tmp2, tmp1, src2);
7518 subL_reg_reg_1(dst, src1, tmp2);
7519 %}
7520 %}
7521
7522 // Register Long Remainder
7523 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7524 match(Set dst (ModL src1 src2));
7525 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7526 expand %{
7527 iRegL tmp1;
7528 iRegL tmp2;
7529 divL_reg_imm13_1(tmp1, src1, src2);
7530 mulL_reg_imm13_1(tmp2, tmp1, src2);
7531 subL_reg_reg_2 (dst, src1, tmp2);
7532 %}
7533 %}
7534
7535 // Integer Shift Instructions
7536 // Register Shift Left
7537 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7538 match(Set dst (LShiftI src1 src2));
7539
7540 size(4);
7541 format %{ "SLL $src1,$src2,$dst" %}
7542 opcode(Assembler::sll_op3, Assembler::arith_op);
7543 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7544 ins_pipe(ialu_reg_reg);
7545 %}
7546
7547 // Register Shift Left Immediate
7548 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7549 match(Set dst (LShiftI src1 src2));
7550
7551 size(4);
7552 format %{ "SLL $src1,$src2,$dst" %}
7553 opcode(Assembler::sll_op3, Assembler::arith_op);
7554 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7555 ins_pipe(ialu_reg_imm);
7556 %}
7557
7558 // Register Shift Left
7559 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7560 match(Set dst (LShiftL src1 src2));
7561
7562 size(4);
7563 format %{ "SLLX $src1,$src2,$dst" %}
7564 opcode(Assembler::sllx_op3, Assembler::arith_op);
7565 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7566 ins_pipe(ialu_reg_reg);
7567 %}
7568
7569 // Register Shift Left Immediate
7570 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7571 match(Set dst (LShiftL src1 src2));
7572
7573 size(4);
7574 format %{ "SLLX $src1,$src2,$dst" %}
7575 opcode(Assembler::sllx_op3, Assembler::arith_op);
7576 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7577 ins_pipe(ialu_reg_imm);
7578 %}
7579
7580 // Register Arithmetic Shift Right
7581 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7582 match(Set dst (RShiftI src1 src2));
7583 size(4);
7584 format %{ "SRA $src1,$src2,$dst" %}
7585 opcode(Assembler::sra_op3, Assembler::arith_op);
7586 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7587 ins_pipe(ialu_reg_reg);
7588 %}
7589
7590 // Register Arithmetic Shift Right Immediate
7591 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7592 match(Set dst (RShiftI src1 src2));
7593
7594 size(4);
7595 format %{ "SRA $src1,$src2,$dst" %}
7596 opcode(Assembler::sra_op3, Assembler::arith_op);
7597 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7598 ins_pipe(ialu_reg_imm);
7599 %}
7600
7601 // Register Shift Right Arithmatic Long
7602 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7603 match(Set dst (RShiftL src1 src2));
7604
7605 size(4);
7606 format %{ "SRAX $src1,$src2,$dst" %}
7607 opcode(Assembler::srax_op3, Assembler::arith_op);
7608 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7609 ins_pipe(ialu_reg_reg);
7610 %}
7611
7612 // Register Shift Left Immediate
7613 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7614 match(Set dst (RShiftL src1 src2));
7615
7616 size(4);
7617 format %{ "SRAX $src1,$src2,$dst" %}
7618 opcode(Assembler::srax_op3, Assembler::arith_op);
7619 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7620 ins_pipe(ialu_reg_imm);
7621 %}
7622
7623 // Register Shift Right
7624 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7625 match(Set dst (URShiftI src1 src2));
7626
7627 size(4);
7628 format %{ "SRL $src1,$src2,$dst" %}
7629 opcode(Assembler::srl_op3, Assembler::arith_op);
7630 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7631 ins_pipe(ialu_reg_reg);
7632 %}
7633
7634 // Register Shift Right Immediate
7635 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7636 match(Set dst (URShiftI src1 src2));
7637
7638 size(4);
7639 format %{ "SRL $src1,$src2,$dst" %}
7640 opcode(Assembler::srl_op3, Assembler::arith_op);
7641 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7642 ins_pipe(ialu_reg_imm);
7643 %}
7644
7645 // Register Shift Right
7646 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7647 match(Set dst (URShiftL src1 src2));
7648
7649 size(4);
7650 format %{ "SRLX $src1,$src2,$dst" %}
7651 opcode(Assembler::srlx_op3, Assembler::arith_op);
7652 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7653 ins_pipe(ialu_reg_reg);
7654 %}
7655
7656 // Register Shift Right Immediate
7657 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7658 match(Set dst (URShiftL src1 src2));
7659
7660 size(4);
7661 format %{ "SRLX $src1,$src2,$dst" %}
7662 opcode(Assembler::srlx_op3, Assembler::arith_op);
7663 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7664 ins_pipe(ialu_reg_imm);
7665 %}
7666
7667 // Register Shift Right Immediate with a CastP2X
7668 #ifdef _LP64
7669 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7670 match(Set dst (URShiftL (CastP2X src1) src2));
7671 size(4);
7672 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7673 opcode(Assembler::srlx_op3, Assembler::arith_op);
7674 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7675 ins_pipe(ialu_reg_imm);
7676 %}
7677 #else
7678 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7679 match(Set dst (URShiftI (CastP2X src1) src2));
7680 size(4);
7681 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7682 opcode(Assembler::srl_op3, Assembler::arith_op);
7683 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7684 ins_pipe(ialu_reg_imm);
7685 %}
7686 #endif
7687
7688
7689 //----------Floating Point Arithmetic Instructions-----------------------------
7690
7691 // Add float single precision
7692 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7693 match(Set dst (AddF src1 src2));
7694
7695 size(4);
7696 format %{ "FADDS $src1,$src2,$dst" %}
7697 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7698 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7699 ins_pipe(faddF_reg_reg);
7700 %}
7701
7702 // Add float double precision
7703 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7704 match(Set dst (AddD src1 src2));
7705
7706 size(4);
7707 format %{ "FADDD $src1,$src2,$dst" %}
7708 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7709 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7710 ins_pipe(faddD_reg_reg);
7711 %}
7712
7713 // Sub float single precision
7714 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7715 match(Set dst (SubF src1 src2));
7716
7717 size(4);
7718 format %{ "FSUBS $src1,$src2,$dst" %}
7719 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7720 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7721 ins_pipe(faddF_reg_reg);
7722 %}
7723
7724 // Sub float double precision
7725 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7726 match(Set dst (SubD src1 src2));
7727
7728 size(4);
7729 format %{ "FSUBD $src1,$src2,$dst" %}
7730 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7731 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7732 ins_pipe(faddD_reg_reg);
7733 %}
7734
7735 // Mul float single precision
7736 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7737 match(Set dst (MulF src1 src2));
7738
7739 size(4);
7740 format %{ "FMULS $src1,$src2,$dst" %}
7741 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7742 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7743 ins_pipe(fmulF_reg_reg);
7744 %}
7745
7746 // Mul float double precision
7747 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7748 match(Set dst (MulD src1 src2));
7749
7750 size(4);
7751 format %{ "FMULD $src1,$src2,$dst" %}
7752 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7753 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7754 ins_pipe(fmulD_reg_reg);
7755 %}
7756
7757 // Div float single precision
7758 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7759 match(Set dst (DivF src1 src2));
7760
7761 size(4);
7762 format %{ "FDIVS $src1,$src2,$dst" %}
7763 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7764 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7765 ins_pipe(fdivF_reg_reg);
7766 %}
7767
7768 // Div float double precision
7769 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7770 match(Set dst (DivD src1 src2));
7771
7772 size(4);
7773 format %{ "FDIVD $src1,$src2,$dst" %}
7774 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7775 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7776 ins_pipe(fdivD_reg_reg);
7777 %}
7778
7779 // Absolute float double precision
7780 instruct absD_reg(regD dst, regD src) %{
7781 match(Set dst (AbsD src));
7782
7783 format %{ "FABSd $src,$dst" %}
7784 ins_encode(fabsd(dst, src));
7785 ins_pipe(faddD_reg);
7786 %}
7787
7788 // Absolute float single precision
7789 instruct absF_reg(regF dst, regF src) %{
7790 match(Set dst (AbsF src));
7791
7792 format %{ "FABSs $src,$dst" %}
7793 ins_encode(fabss(dst, src));
7794 ins_pipe(faddF_reg);
7795 %}
7796
7797 instruct negF_reg(regF dst, regF src) %{
7798 match(Set dst (NegF src));
7799
7800 size(4);
7801 format %{ "FNEGs $src,$dst" %}
7802 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7803 ins_encode(form3_opf_rs2F_rdF(src, dst));
7804 ins_pipe(faddF_reg);
7805 %}
7806
7807 instruct negD_reg(regD dst, regD src) %{
7808 match(Set dst (NegD src));
7809
7810 format %{ "FNEGd $src,$dst" %}
7811 ins_encode(fnegd(dst, src));
7812 ins_pipe(faddD_reg);
7813 %}
7814
7815 // Sqrt float double precision
7816 instruct sqrtF_reg_reg(regF dst, regF src) %{
7817 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7818
7819 size(4);
7820 format %{ "FSQRTS $src,$dst" %}
7821 ins_encode(fsqrts(dst, src));
7822 ins_pipe(fdivF_reg_reg);
7823 %}
7824
7825 // Sqrt float double precision
7826 instruct sqrtD_reg_reg(regD dst, regD src) %{
7827 match(Set dst (SqrtD src));
7828
7829 size(4);
7830 format %{ "FSQRTD $src,$dst" %}
7831 ins_encode(fsqrtd(dst, src));
7832 ins_pipe(fdivD_reg_reg);
7833 %}
7834
7835 //----------Logical Instructions-----------------------------------------------
7836 // And Instructions
7837 // Register And
7838 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7839 match(Set dst (AndI src1 src2));
7840
7841 size(4);
7842 format %{ "AND $src1,$src2,$dst" %}
7843 opcode(Assembler::and_op3, Assembler::arith_op);
7844 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7845 ins_pipe(ialu_reg_reg);
7846 %}
7847
7848 // Immediate And
7849 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7850 match(Set dst (AndI src1 src2));
7851
7852 size(4);
7853 format %{ "AND $src1,$src2,$dst" %}
7854 opcode(Assembler::and_op3, Assembler::arith_op);
7855 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7856 ins_pipe(ialu_reg_imm);
7857 %}
7858
7859 // Register And Long
7860 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7861 match(Set dst (AndL src1 src2));
7862
7863 ins_cost(DEFAULT_COST);
7864 size(4);
7865 format %{ "AND $src1,$src2,$dst\t! long" %}
7866 opcode(Assembler::and_op3, Assembler::arith_op);
7867 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7868 ins_pipe(ialu_reg_reg);
7869 %}
7870
7871 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7872 match(Set dst (AndL src1 con));
7873
7874 ins_cost(DEFAULT_COST);
7875 size(4);
7876 format %{ "AND $src1,$con,$dst\t! long" %}
7877 opcode(Assembler::and_op3, Assembler::arith_op);
7878 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7879 ins_pipe(ialu_reg_imm);
7880 %}
7881
7882 // Or Instructions
7883 // Register Or
7884 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7885 match(Set dst (OrI src1 src2));
7886
7887 size(4);
7888 format %{ "OR $src1,$src2,$dst" %}
7889 opcode(Assembler::or_op3, Assembler::arith_op);
7890 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7891 ins_pipe(ialu_reg_reg);
7892 %}
7893
7894 // Immediate Or
7895 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7896 match(Set dst (OrI src1 src2));
7897
7898 size(4);
7899 format %{ "OR $src1,$src2,$dst" %}
7900 opcode(Assembler::or_op3, Assembler::arith_op);
7901 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7902 ins_pipe(ialu_reg_imm);
7903 %}
7904
7905 // Register Or Long
7906 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7907 match(Set dst (OrL src1 src2));
7908
7909 ins_cost(DEFAULT_COST);
7910 size(4);
7911 format %{ "OR $src1,$src2,$dst\t! long" %}
7912 opcode(Assembler::or_op3, Assembler::arith_op);
7913 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7914 ins_pipe(ialu_reg_reg);
7915 %}
7916
7917 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7918 match(Set dst (OrL src1 con));
7919 ins_cost(DEFAULT_COST*2);
7920
7921 ins_cost(DEFAULT_COST);
7922 size(4);
7923 format %{ "OR $src1,$con,$dst\t! long" %}
7924 opcode(Assembler::or_op3, Assembler::arith_op);
7925 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7926 ins_pipe(ialu_reg_imm);
7927 %}
7928
7929 #ifndef _LP64
7930
7931 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7932 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7933 match(Set dst (OrI src1 (CastP2X src2)));
7934
7935 size(4);
7936 format %{ "OR $src1,$src2,$dst" %}
7937 opcode(Assembler::or_op3, Assembler::arith_op);
7938 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7939 ins_pipe(ialu_reg_reg);
7940 %}
7941
7942 #else
7943
7944 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7945 match(Set dst (OrL src1 (CastP2X src2)));
7946
7947 ins_cost(DEFAULT_COST);
7948 size(4);
7949 format %{ "OR $src1,$src2,$dst\t! long" %}
7950 opcode(Assembler::or_op3, Assembler::arith_op);
7951 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7952 ins_pipe(ialu_reg_reg);
7953 %}
7954
7955 #endif
7956
7957 // Xor Instructions
7958 // Register Xor
7959 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7960 match(Set dst (XorI src1 src2));
7961
7962 size(4);
7963 format %{ "XOR $src1,$src2,$dst" %}
7964 opcode(Assembler::xor_op3, Assembler::arith_op);
7965 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7966 ins_pipe(ialu_reg_reg);
7967 %}
7968
7969 // Immediate Xor
7970 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7971 match(Set dst (XorI src1 src2));
7972
7973 size(4);
7974 format %{ "XOR $src1,$src2,$dst" %}
7975 opcode(Assembler::xor_op3, Assembler::arith_op);
7976 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7977 ins_pipe(ialu_reg_imm);
7978 %}
7979
7980 // Register Xor Long
7981 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7982 match(Set dst (XorL src1 src2));
7983
7984 ins_cost(DEFAULT_COST);
7985 size(4);
7986 format %{ "XOR $src1,$src2,$dst\t! long" %}
7987 opcode(Assembler::xor_op3, Assembler::arith_op);
7988 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7989 ins_pipe(ialu_reg_reg);
7990 %}
7991
7992 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7993 match(Set dst (XorL src1 con));
7994
7995 ins_cost(DEFAULT_COST);
7996 size(4);
7997 format %{ "XOR $src1,$con,$dst\t! long" %}
7998 opcode(Assembler::xor_op3, Assembler::arith_op);
7999 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8000 ins_pipe(ialu_reg_imm);
8001 %}
8002
8003 //----------Convert to Boolean-------------------------------------------------
8004 // Nice hack for 32-bit tests but doesn't work for
8005 // 64-bit pointers.
8006 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8007 match(Set dst (Conv2B src));
8008 effect( KILL ccr );
8009 ins_cost(DEFAULT_COST*2);
8010 format %{ "CMP R_G0,$src\n\t"
8011 "ADDX R_G0,0,$dst" %}
8012 ins_encode( enc_to_bool( src, dst ) );
8013 ins_pipe(ialu_reg_ialu);
8014 %}
8015
8016 #ifndef _LP64
8017 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8018 match(Set dst (Conv2B src));
8019 effect( KILL ccr );
8020 ins_cost(DEFAULT_COST*2);
8021 format %{ "CMP R_G0,$src\n\t"
8022 "ADDX R_G0,0,$dst" %}
8023 ins_encode( enc_to_bool( src, dst ) );
8024 ins_pipe(ialu_reg_ialu);
8025 %}
8026 #else
8027 instruct convP2B( iRegI dst, iRegP src ) %{
8028 match(Set dst (Conv2B src));
8029 ins_cost(DEFAULT_COST*2);
8030 format %{ "MOV $src,$dst\n\t"
8031 "MOVRNZ $src,1,$dst" %}
8032 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8033 ins_pipe(ialu_clr_and_mover);
8034 %}
8035 #endif
8036
8037 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8038 match(Set dst (CmpLTMask src zero));
8039 effect(KILL ccr);
8040 size(4);
8041 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8042 ins_encode %{
8043 __ sra($src$$Register, 31, $dst$$Register);
8044 %}
8045 ins_pipe(ialu_reg_imm);
8046 %}
8047
8048 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8049 match(Set dst (CmpLTMask p q));
8050 effect( KILL ccr );
8051 ins_cost(DEFAULT_COST*4);
8052 format %{ "CMP $p,$q\n\t"
8053 "MOV #0,$dst\n\t"
8054 "BLT,a .+8\n\t"
8055 "MOV #-1,$dst" %}
8056 ins_encode( enc_ltmask(p,q,dst) );
8057 ins_pipe(ialu_reg_reg_ialu);
8058 %}
8059
8060 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8061 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8062 effect(KILL ccr, TEMP tmp);
8063 ins_cost(DEFAULT_COST*3);
8064
8065 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8066 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8067 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8068 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8069 ins_pipe(cadd_cmpltmask);
8070 %}
8071
8072 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8073 match(Set p (AndI (CmpLTMask p q) y));
8074 effect(KILL ccr);
8075 ins_cost(DEFAULT_COST*3);
8076
8077 format %{ "CMP $p,$q\n\t"
8078 "MOV $y,$p\n\t"
8079 "MOVge G0,$p" %}
8080 ins_encode %{
8081 __ cmp($p$$Register, $q$$Register);
8082 __ mov($y$$Register, $p$$Register);
8083 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8084 %}
8085 ins_pipe(ialu_reg_reg_ialu);
8086 %}
8087
8088 //-----------------------------------------------------------------
8089 // Direct raw moves between float and general registers using VIS3.
8090
8091 // ins_pipe(faddF_reg);
8092 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8093 predicate(UseVIS >= 3);
8094 match(Set dst (MoveF2I src));
8095
8096 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8097 ins_encode %{
8098 __ movstouw($src$$FloatRegister, $dst$$Register);
8099 %}
8100 ins_pipe(ialu_reg_reg);
8101 %}
8102
8103 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8104 predicate(UseVIS >= 3);
8105 match(Set dst (MoveI2F src));
8106
8107 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8108 ins_encode %{
8109 __ movwtos($src$$Register, $dst$$FloatRegister);
8110 %}
8111 ins_pipe(ialu_reg_reg);
8112 %}
8113
8114 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8115 predicate(UseVIS >= 3);
8116 match(Set dst (MoveD2L src));
8117
8118 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8119 ins_encode %{
8120 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8121 %}
8122 ins_pipe(ialu_reg_reg);
8123 %}
8124
8125 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8126 predicate(UseVIS >= 3);
8127 match(Set dst (MoveL2D src));
8128
8129 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8130 ins_encode %{
8131 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8132 %}
8133 ins_pipe(ialu_reg_reg);
8134 %}
8135
8136
8137 // Raw moves between float and general registers using stack.
8138
8139 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8140 match(Set dst (MoveF2I src));
8141 effect(DEF dst, USE src);
8142 ins_cost(MEMORY_REF_COST);
8143
8144 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8145 opcode(Assembler::lduw_op3);
8146 ins_encode(simple_form3_mem_reg( src, dst ) );
8147 ins_pipe(iload_mem);
8148 %}
8149
8150 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8151 match(Set dst (MoveI2F src));
8152 effect(DEF dst, USE src);
8153 ins_cost(MEMORY_REF_COST);
8154
8155 format %{ "LDF $src,$dst\t! MoveI2F" %}
8156 opcode(Assembler::ldf_op3);
8157 ins_encode(simple_form3_mem_reg(src, dst));
8158 ins_pipe(floadF_stk);
8159 %}
8160
8161 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8162 match(Set dst (MoveD2L src));
8163 effect(DEF dst, USE src);
8164 ins_cost(MEMORY_REF_COST);
8165
8166 format %{ "LDX $src,$dst\t! MoveD2L" %}
8167 opcode(Assembler::ldx_op3);
8168 ins_encode(simple_form3_mem_reg( src, dst ) );
8169 ins_pipe(iload_mem);
8170 %}
8171
8172 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8173 match(Set dst (MoveL2D src));
8174 effect(DEF dst, USE src);
8175 ins_cost(MEMORY_REF_COST);
8176
8177 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8178 opcode(Assembler::lddf_op3);
8179 ins_encode(simple_form3_mem_reg(src, dst));
8180 ins_pipe(floadD_stk);
8181 %}
8182
8183 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8184 match(Set dst (MoveF2I src));
8185 effect(DEF dst, USE src);
8186 ins_cost(MEMORY_REF_COST);
8187
8188 format %{ "STF $src,$dst\t! MoveF2I" %}
8189 opcode(Assembler::stf_op3);
8190 ins_encode(simple_form3_mem_reg(dst, src));
8191 ins_pipe(fstoreF_stk_reg);
8192 %}
8193
8194 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8195 match(Set dst (MoveI2F src));
8196 effect(DEF dst, USE src);
8197 ins_cost(MEMORY_REF_COST);
8198
8199 format %{ "STW $src,$dst\t! MoveI2F" %}
8200 opcode(Assembler::stw_op3);
8201 ins_encode(simple_form3_mem_reg( dst, src ) );
8202 ins_pipe(istore_mem_reg);
8203 %}
8204
8205 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8206 match(Set dst (MoveD2L src));
8207 effect(DEF dst, USE src);
8208 ins_cost(MEMORY_REF_COST);
8209
8210 format %{ "STDF $src,$dst\t! MoveD2L" %}
8211 opcode(Assembler::stdf_op3);
8212 ins_encode(simple_form3_mem_reg(dst, src));
8213 ins_pipe(fstoreD_stk_reg);
8214 %}
8215
8216 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8217 match(Set dst (MoveL2D src));
8218 effect(DEF dst, USE src);
8219 ins_cost(MEMORY_REF_COST);
8220
8221 format %{ "STX $src,$dst\t! MoveL2D" %}
8222 opcode(Assembler::stx_op3);
8223 ins_encode(simple_form3_mem_reg( dst, src ) );
8224 ins_pipe(istore_mem_reg);
8225 %}
8226
8227
8228 //----------Arithmetic Conversion Instructions---------------------------------
8229 // The conversions operations are all Alpha sorted. Please keep it that way!
8230
8231 instruct convD2F_reg(regF dst, regD src) %{
8232 match(Set dst (ConvD2F src));
8233 size(4);
8234 format %{ "FDTOS $src,$dst" %}
8235 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8236 ins_encode(form3_opf_rs2D_rdF(src, dst));
8237 ins_pipe(fcvtD2F);
8238 %}
8239
8240
8241 // Convert a double to an int in a float register.
8242 // If the double is a NAN, stuff a zero in instead.
8243 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8244 effect(DEF dst, USE src, KILL fcc0);
8245 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8246 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8247 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8248 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8249 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8250 "skip:" %}
8251 ins_encode(form_d2i_helper(src,dst));
8252 ins_pipe(fcvtD2I);
8253 %}
8254
8255 instruct convD2I_stk(stackSlotI dst, regD src) %{
8256 match(Set dst (ConvD2I src));
8257 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8258 expand %{
8259 regF tmp;
8260 convD2I_helper(tmp, src);
8261 regF_to_stkI(dst, tmp);
8262 %}
8263 %}
8264
8265 instruct convD2I_reg(iRegI dst, regD src) %{
8266 predicate(UseVIS >= 3);
8267 match(Set dst (ConvD2I src));
8268 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8269 expand %{
8270 regF tmp;
8271 convD2I_helper(tmp, src);
8272 MoveF2I_reg_reg(dst, tmp);
8273 %}
8274 %}
8275
8276
8277 // Convert a double to a long in a double register.
8278 // If the double is a NAN, stuff a zero in instead.
8279 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8280 effect(DEF dst, USE src, KILL fcc0);
8281 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8282 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8283 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8284 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8285 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8286 "skip:" %}
8287 ins_encode(form_d2l_helper(src,dst));
8288 ins_pipe(fcvtD2L);
8289 %}
8290
8291 instruct convD2L_stk(stackSlotL dst, regD src) %{
8292 match(Set dst (ConvD2L src));
8293 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8294 expand %{
8295 regD tmp;
8296 convD2L_helper(tmp, src);
8297 regD_to_stkL(dst, tmp);
8298 %}
8299 %}
8300
8301 instruct convD2L_reg(iRegL dst, regD src) %{
8302 predicate(UseVIS >= 3);
8303 match(Set dst (ConvD2L src));
8304 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8305 expand %{
8306 regD tmp;
8307 convD2L_helper(tmp, src);
8308 MoveD2L_reg_reg(dst, tmp);
8309 %}
8310 %}
8311
8312
8313 instruct convF2D_reg(regD dst, regF src) %{
8314 match(Set dst (ConvF2D src));
8315 format %{ "FSTOD $src,$dst" %}
8316 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8317 ins_encode(form3_opf_rs2F_rdD(src, dst));
8318 ins_pipe(fcvtF2D);
8319 %}
8320
8321
8322 // Convert a float to an int in a float register.
8323 // If the float is a NAN, stuff a zero in instead.
8324 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8325 effect(DEF dst, USE src, KILL fcc0);
8326 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8327 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8328 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8329 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8330 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8331 "skip:" %}
8332 ins_encode(form_f2i_helper(src,dst));
8333 ins_pipe(fcvtF2I);
8334 %}
8335
8336 instruct convF2I_stk(stackSlotI dst, regF src) %{
8337 match(Set dst (ConvF2I src));
8338 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8339 expand %{
8340 regF tmp;
8341 convF2I_helper(tmp, src);
8342 regF_to_stkI(dst, tmp);
8343 %}
8344 %}
8345
8346 instruct convF2I_reg(iRegI dst, regF src) %{
8347 predicate(UseVIS >= 3);
8348 match(Set dst (ConvF2I src));
8349 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8350 expand %{
8351 regF tmp;
8352 convF2I_helper(tmp, src);
8353 MoveF2I_reg_reg(dst, tmp);
8354 %}
8355 %}
8356
8357
8358 // Convert a float to a long in a float register.
8359 // If the float is a NAN, stuff a zero in instead.
8360 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8361 effect(DEF dst, USE src, KILL fcc0);
8362 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8363 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8364 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8365 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8366 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8367 "skip:" %}
8368 ins_encode(form_f2l_helper(src,dst));
8369 ins_pipe(fcvtF2L);
8370 %}
8371
8372 instruct convF2L_stk(stackSlotL dst, regF src) %{
8373 match(Set dst (ConvF2L src));
8374 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8375 expand %{
8376 regD tmp;
8377 convF2L_helper(tmp, src);
8378 regD_to_stkL(dst, tmp);
8379 %}
8380 %}
8381
8382 instruct convF2L_reg(iRegL dst, regF src) %{
8383 predicate(UseVIS >= 3);
8384 match(Set dst (ConvF2L src));
8385 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8386 expand %{
8387 regD tmp;
8388 convF2L_helper(tmp, src);
8389 MoveD2L_reg_reg(dst, tmp);
8390 %}
8391 %}
8392
8393
8394 instruct convI2D_helper(regD dst, regF tmp) %{
8395 effect(USE tmp, DEF dst);
8396 format %{ "FITOD $tmp,$dst" %}
8397 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8398 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8399 ins_pipe(fcvtI2D);
8400 %}
8401
8402 instruct convI2D_stk(stackSlotI src, regD dst) %{
8403 match(Set dst (ConvI2D src));
8404 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8405 expand %{
8406 regF tmp;
8407 stkI_to_regF(tmp, src);
8408 convI2D_helper(dst, tmp);
8409 %}
8410 %}
8411
8412 instruct convI2D_reg(regD_low dst, iRegI src) %{
8413 predicate(UseVIS >= 3);
8414 match(Set dst (ConvI2D src));
8415 expand %{
8416 regF tmp;
8417 MoveI2F_reg_reg(tmp, src);
8418 convI2D_helper(dst, tmp);
8419 %}
8420 %}
8421
8422 instruct convI2D_mem(regD_low dst, memory mem) %{
8423 match(Set dst (ConvI2D (LoadI mem)));
8424 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8425 format %{ "LDF $mem,$dst\n\t"
8426 "FITOD $dst,$dst" %}
8427 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8428 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8429 ins_pipe(floadF_mem);
8430 %}
8431
8432
8433 instruct convI2F_helper(regF dst, regF tmp) %{
8434 effect(DEF dst, USE tmp);
8435 format %{ "FITOS $tmp,$dst" %}
8436 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8437 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8438 ins_pipe(fcvtI2F);
8439 %}
8440
8441 instruct convI2F_stk(regF dst, stackSlotI src) %{
8442 match(Set dst (ConvI2F src));
8443 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8444 expand %{
8445 regF tmp;
8446 stkI_to_regF(tmp,src);
8447 convI2F_helper(dst, tmp);
8448 %}
8449 %}
8450
8451 instruct convI2F_reg(regF dst, iRegI src) %{
8452 predicate(UseVIS >= 3);
8453 match(Set dst (ConvI2F src));
8454 ins_cost(DEFAULT_COST);
8455 expand %{
8456 regF tmp;
8457 MoveI2F_reg_reg(tmp, src);
8458 convI2F_helper(dst, tmp);
8459 %}
8460 %}
8461
8462 instruct convI2F_mem( regF dst, memory mem ) %{
8463 match(Set dst (ConvI2F (LoadI mem)));
8464 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8465 format %{ "LDF $mem,$dst\n\t"
8466 "FITOS $dst,$dst" %}
8467 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8468 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8469 ins_pipe(floadF_mem);
8470 %}
8471
8472
8473 instruct convI2L_reg(iRegL dst, iRegI src) %{
8474 match(Set dst (ConvI2L src));
8475 size(4);
8476 format %{ "SRA $src,0,$dst\t! int->long" %}
8477 opcode(Assembler::sra_op3, Assembler::arith_op);
8478 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8479 ins_pipe(ialu_reg_reg);
8480 %}
8481
8482 // Zero-extend convert int to long
8483 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8484 match(Set dst (AndL (ConvI2L src) mask) );
8485 size(4);
8486 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8487 opcode(Assembler::srl_op3, Assembler::arith_op);
8488 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8489 ins_pipe(ialu_reg_reg);
8490 %}
8491
8492 // Zero-extend long
8493 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8494 match(Set dst (AndL src mask) );
8495 size(4);
8496 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8497 opcode(Assembler::srl_op3, Assembler::arith_op);
8498 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8499 ins_pipe(ialu_reg_reg);
8500 %}
8501
8502
8503 //-----------
8504 // Long to Double conversion using V8 opcodes.
8505 // Still useful because cheetah traps and becomes
8506 // amazingly slow for some common numbers.
8507
8508 // Magic constant, 0x43300000
8509 instruct loadConI_x43300000(iRegI dst) %{
8510 effect(DEF dst);
8511 size(4);
8512 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8513 ins_encode(SetHi22(0x43300000, dst));
8514 ins_pipe(ialu_none);
8515 %}
8516
8517 // Magic constant, 0x41f00000
8518 instruct loadConI_x41f00000(iRegI dst) %{
8519 effect(DEF dst);
8520 size(4);
8521 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8522 ins_encode(SetHi22(0x41f00000, dst));
8523 ins_pipe(ialu_none);
8524 %}
8525
8526 // Construct a double from two float halves
8527 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8528 effect(DEF dst, USE src1, USE src2);
8529 size(8);
8530 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8531 "FMOVS $src2.lo,$dst.lo" %}
8532 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8533 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8534 ins_pipe(faddD_reg_reg);
8535 %}
8536
8537 // Convert integer in high half of a double register (in the lower half of
8538 // the double register file) to double
8539 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8540 effect(DEF dst, USE src);
8541 size(4);
8542 format %{ "FITOD $src,$dst" %}
8543 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8544 ins_encode(form3_opf_rs2D_rdD(src, dst));
8545 ins_pipe(fcvtLHi2D);
8546 %}
8547
8548 // Add float double precision
8549 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8550 effect(DEF dst, USE src1, USE src2);
8551 size(4);
8552 format %{ "FADDD $src1,$src2,$dst" %}
8553 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8554 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8555 ins_pipe(faddD_reg_reg);
8556 %}
8557
8558 // Sub float double precision
8559 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8560 effect(DEF dst, USE src1, USE src2);
8561 size(4);
8562 format %{ "FSUBD $src1,$src2,$dst" %}
8563 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8564 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8565 ins_pipe(faddD_reg_reg);
8566 %}
8567
8568 // Mul float double precision
8569 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8570 effect(DEF dst, USE src1, USE src2);
8571 size(4);
8572 format %{ "FMULD $src1,$src2,$dst" %}
8573 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8574 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8575 ins_pipe(fmulD_reg_reg);
8576 %}
8577
8578 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8579 match(Set dst (ConvL2D src));
8580 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8581
8582 expand %{
8583 regD_low tmpsrc;
8584 iRegI ix43300000;
8585 iRegI ix41f00000;
8586 stackSlotL lx43300000;
8587 stackSlotL lx41f00000;
8588 regD_low dx43300000;
8589 regD dx41f00000;
8590 regD tmp1;
8591 regD_low tmp2;
8592 regD tmp3;
8593 regD tmp4;
8594
8595 stkL_to_regD(tmpsrc, src);
8596
8597 loadConI_x43300000(ix43300000);
8598 loadConI_x41f00000(ix41f00000);
8599 regI_to_stkLHi(lx43300000, ix43300000);
8600 regI_to_stkLHi(lx41f00000, ix41f00000);
8601 stkL_to_regD(dx43300000, lx43300000);
8602 stkL_to_regD(dx41f00000, lx41f00000);
8603
8604 convI2D_regDHi_regD(tmp1, tmpsrc);
8605 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8606 subD_regD_regD(tmp3, tmp2, dx43300000);
8607 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8608 addD_regD_regD(dst, tmp3, tmp4);
8609 %}
8610 %}
8611
8612 // Long to Double conversion using fast fxtof
8613 instruct convL2D_helper(regD dst, regD tmp) %{
8614 effect(DEF dst, USE tmp);
8615 size(4);
8616 format %{ "FXTOD $tmp,$dst" %}
8617 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8618 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8619 ins_pipe(fcvtL2D);
8620 %}
8621
8622 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8623 predicate(VM_Version::has_fast_fxtof());
8624 match(Set dst (ConvL2D src));
8625 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8626 expand %{
8627 regD tmp;
8628 stkL_to_regD(tmp, src);
8629 convL2D_helper(dst, tmp);
8630 %}
8631 %}
8632
8633 instruct convL2D_reg(regD dst, iRegL src) %{
8634 predicate(UseVIS >= 3);
8635 match(Set dst (ConvL2D src));
8636 expand %{
8637 regD tmp;
8638 MoveL2D_reg_reg(tmp, src);
8639 convL2D_helper(dst, tmp);
8640 %}
8641 %}
8642
8643 // Long to Float conversion using fast fxtof
8644 instruct convL2F_helper(regF dst, regD tmp) %{
8645 effect(DEF dst, USE tmp);
8646 size(4);
8647 format %{ "FXTOS $tmp,$dst" %}
8648 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8649 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8650 ins_pipe(fcvtL2F);
8651 %}
8652
8653 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8654 match(Set dst (ConvL2F src));
8655 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8656 expand %{
8657 regD tmp;
8658 stkL_to_regD(tmp, src);
8659 convL2F_helper(dst, tmp);
8660 %}
8661 %}
8662
8663 instruct convL2F_reg(regF dst, iRegL src) %{
8664 predicate(UseVIS >= 3);
8665 match(Set dst (ConvL2F src));
8666 ins_cost(DEFAULT_COST);
8667 expand %{
8668 regD tmp;
8669 MoveL2D_reg_reg(tmp, src);
8670 convL2F_helper(dst, tmp);
8671 %}
8672 %}
8673
8674 //-----------
8675
8676 instruct convL2I_reg(iRegI dst, iRegL src) %{
8677 match(Set dst (ConvL2I src));
8678 #ifndef _LP64
8679 format %{ "MOV $src.lo,$dst\t! long->int" %}
8680 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8681 ins_pipe(ialu_move_reg_I_to_L);
8682 #else
8683 size(4);
8684 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8685 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8686 ins_pipe(ialu_reg);
8687 #endif
8688 %}
8689
8690 // Register Shift Right Immediate
8691 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8692 match(Set dst (ConvL2I (RShiftL src cnt)));
8693
8694 size(4);
8695 format %{ "SRAX $src,$cnt,$dst" %}
8696 opcode(Assembler::srax_op3, Assembler::arith_op);
8697 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8698 ins_pipe(ialu_reg_imm);
8699 %}
8700
8701 //----------Control Flow Instructions------------------------------------------
8702 // Compare Instructions
8703 // Compare Integers
8704 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8705 match(Set icc (CmpI op1 op2));
8706 effect( DEF icc, USE op1, USE op2 );
8707
8708 size(4);
8709 format %{ "CMP $op1,$op2" %}
8710 opcode(Assembler::subcc_op3, Assembler::arith_op);
8711 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8712 ins_pipe(ialu_cconly_reg_reg);
8713 %}
8714
8715 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8716 match(Set icc (CmpU op1 op2));
8717
8718 size(4);
8719 format %{ "CMP $op1,$op2\t! unsigned" %}
8720 opcode(Assembler::subcc_op3, Assembler::arith_op);
8721 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8722 ins_pipe(ialu_cconly_reg_reg);
8723 %}
8724
8725 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8726 match(Set icc (CmpI op1 op2));
8727 effect( DEF icc, USE op1 );
8728
8729 size(4);
8730 format %{ "CMP $op1,$op2" %}
8731 opcode(Assembler::subcc_op3, Assembler::arith_op);
8732 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8733 ins_pipe(ialu_cconly_reg_imm);
8734 %}
8735
8736 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8737 match(Set icc (CmpI (AndI op1 op2) zero));
8738
8739 size(4);
8740 format %{ "BTST $op2,$op1" %}
8741 opcode(Assembler::andcc_op3, Assembler::arith_op);
8742 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8743 ins_pipe(ialu_cconly_reg_reg_zero);
8744 %}
8745
8746 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8747 match(Set icc (CmpI (AndI op1 op2) zero));
8748
8749 size(4);
8750 format %{ "BTST $op2,$op1" %}
8751 opcode(Assembler::andcc_op3, Assembler::arith_op);
8752 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8753 ins_pipe(ialu_cconly_reg_imm_zero);
8754 %}
8755
8756 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8757 match(Set xcc (CmpL op1 op2));
8758 effect( DEF xcc, USE op1, USE op2 );
8759
8760 size(4);
8761 format %{ "CMP $op1,$op2\t\t! long" %}
8762 opcode(Assembler::subcc_op3, Assembler::arith_op);
8763 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8764 ins_pipe(ialu_cconly_reg_reg);
8765 %}
8766
8767 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8768 match(Set xcc (CmpL op1 con));
8769 effect( DEF xcc, USE op1, USE con );
8770
8771 size(4);
8772 format %{ "CMP $op1,$con\t\t! long" %}
8773 opcode(Assembler::subcc_op3, Assembler::arith_op);
8774 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8775 ins_pipe(ialu_cconly_reg_reg);
8776 %}
8777
8778 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8779 match(Set xcc (CmpL (AndL op1 op2) zero));
8780 effect( DEF xcc, USE op1, USE op2 );
8781
8782 size(4);
8783 format %{ "BTST $op1,$op2\t\t! long" %}
8784 opcode(Assembler::andcc_op3, Assembler::arith_op);
8785 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8786 ins_pipe(ialu_cconly_reg_reg);
8787 %}
8788
8789 // useful for checking the alignment of a pointer:
8790 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8791 match(Set xcc (CmpL (AndL op1 con) zero));
8792 effect( DEF xcc, USE op1, USE con );
8793
8794 size(4);
8795 format %{ "BTST $op1,$con\t\t! long" %}
8796 opcode(Assembler::andcc_op3, Assembler::arith_op);
8797 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8798 ins_pipe(ialu_cconly_reg_reg);
8799 %}
8800
8801 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8802 match(Set icc (CmpU op1 op2));
8803
8804 size(4);
8805 format %{ "CMP $op1,$op2\t! unsigned" %}
8806 opcode(Assembler::subcc_op3, Assembler::arith_op);
8807 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8808 ins_pipe(ialu_cconly_reg_imm);
8809 %}
8810
8811 // Compare Pointers
8812 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8813 match(Set pcc (CmpP op1 op2));
8814
8815 size(4);
8816 format %{ "CMP $op1,$op2\t! ptr" %}
8817 opcode(Assembler::subcc_op3, Assembler::arith_op);
8818 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8819 ins_pipe(ialu_cconly_reg_reg);
8820 %}
8821
8822 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8823 match(Set pcc (CmpP op1 op2));
8824
8825 size(4);
8826 format %{ "CMP $op1,$op2\t! ptr" %}
8827 opcode(Assembler::subcc_op3, Assembler::arith_op);
8828 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8829 ins_pipe(ialu_cconly_reg_imm);
8830 %}
8831
8832 // Compare Narrow oops
8833 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8834 match(Set icc (CmpN op1 op2));
8835
8836 size(4);
8837 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8838 opcode(Assembler::subcc_op3, Assembler::arith_op);
8839 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8840 ins_pipe(ialu_cconly_reg_reg);
8841 %}
8842
8843 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8844 match(Set icc (CmpN op1 op2));
8845
8846 size(4);
8847 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8848 opcode(Assembler::subcc_op3, Assembler::arith_op);
8849 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8850 ins_pipe(ialu_cconly_reg_imm);
8851 %}
8852
8853 //----------Max and Min--------------------------------------------------------
8854 // Min Instructions
8855 // Conditional move for min
8856 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8857 effect( USE_DEF op2, USE op1, USE icc );
8858
8859 size(4);
8860 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8861 opcode(Assembler::less);
8862 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8863 ins_pipe(ialu_reg_flags);
8864 %}
8865
8866 // Min Register with Register.
8867 instruct minI_eReg(iRegI op1, iRegI op2) %{
8868 match(Set op2 (MinI op1 op2));
8869 ins_cost(DEFAULT_COST*2);
8870 expand %{
8871 flagsReg icc;
8872 compI_iReg(icc,op1,op2);
8873 cmovI_reg_lt(op2,op1,icc);
8874 %}
8875 %}
8876
8877 // Max Instructions
8878 // Conditional move for max
8879 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8880 effect( USE_DEF op2, USE op1, USE icc );
8881 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8882 opcode(Assembler::greater);
8883 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8884 ins_pipe(ialu_reg_flags);
8885 %}
8886
8887 // Max Register with Register
8888 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8889 match(Set op2 (MaxI op1 op2));
8890 ins_cost(DEFAULT_COST*2);
8891 expand %{
8892 flagsReg icc;
8893 compI_iReg(icc,op1,op2);
8894 cmovI_reg_gt(op2,op1,icc);
8895 %}
8896 %}
8897
8898
8899 //----------Float Compares----------------------------------------------------
8900 // Compare floating, generate condition code
8901 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8902 match(Set fcc (CmpF src1 src2));
8903
8904 size(4);
8905 format %{ "FCMPs $fcc,$src1,$src2" %}
8906 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8907 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8908 ins_pipe(faddF_fcc_reg_reg_zero);
8909 %}
8910
8911 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8912 match(Set fcc (CmpD src1 src2));
8913
8914 size(4);
8915 format %{ "FCMPd $fcc,$src1,$src2" %}
8916 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8917 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8918 ins_pipe(faddD_fcc_reg_reg_zero);
8919 %}
8920
8921
8922 // Compare floating, generate -1,0,1
8923 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8924 match(Set dst (CmpF3 src1 src2));
8925 effect(KILL fcc0);
8926 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8927 format %{ "fcmpl $dst,$src1,$src2" %}
8928 // Primary = float
8929 opcode( true );
8930 ins_encode( floating_cmp( dst, src1, src2 ) );
8931 ins_pipe( floating_cmp );
8932 %}
8933
8934 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8935 match(Set dst (CmpD3 src1 src2));
8936 effect(KILL fcc0);
8937 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8938 format %{ "dcmpl $dst,$src1,$src2" %}
8939 // Primary = double (not float)
8940 opcode( false );
8941 ins_encode( floating_cmp( dst, src1, src2 ) );
8942 ins_pipe( floating_cmp );
8943 %}
8944
8945 //----------Branches---------------------------------------------------------
8946 // Jump
8947 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8948 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8949 match(Jump switch_val);
8950 effect(TEMP table);
8951
8952 ins_cost(350);
8953
8954 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8955 "LD [O7 + $switch_val], O7\n\t"
8956 "JUMP O7" %}
8957 ins_encode %{
8958 // Calculate table address into a register.
8959 Register table_reg;
8960 Register label_reg = O7;
8961 // If we are calculating the size of this instruction don't trust
8962 // zero offsets because they might change when
8963 // MachConstantBaseNode decides to optimize the constant table
8964 // base.
8965 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8966 table_reg = $constanttablebase;
8967 } else {
8968 table_reg = O7;
8969 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8970 __ add($constanttablebase, con_offset, table_reg);
8971 }
8972
8973 // Jump to base address + switch value
8974 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8975 __ jmp(label_reg, G0);
8976 __ delayed()->nop();
8977 %}
8978 ins_pipe(ialu_reg_reg);
8979 %}
8980
8981 // Direct Branch. Use V8 version with longer range.
8982 instruct branch(label labl) %{
8983 match(Goto);
8984 effect(USE labl);
8985
8986 size(8);
8987 ins_cost(BRANCH_COST);
8988 format %{ "BA $labl" %}
8989 ins_encode %{
8990 Label* L = $labl$$label;
8991 __ ba(*L);
8992 __ delayed()->nop();
8993 %}
8994 ins_avoid_back_to_back(AVOID_BEFORE);
8995 ins_pipe(br);
8996 %}
8997
8998 // Direct Branch, short with no delay slot
8999 instruct branch_short(label labl) %{
9000 match(Goto);
9001 predicate(UseCBCond);
9002 effect(USE labl);
9003
9004 size(4);
9005 ins_cost(BRANCH_COST);
9006 format %{ "BA $labl\t! short branch" %}
9007 ins_encode %{
9008 Label* L = $labl$$label;
9009 assert(__ use_cbcond(*L), "back to back cbcond");
9010 __ ba_short(*L);
9011 %}
9012 ins_short_branch(1);
9013 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9014 ins_pipe(cbcond_reg_imm);
9015 %}
9016
9017 // Conditional Direct Branch
9018 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9019 match(If cmp icc);
9020 effect(USE labl);
9021
9022 size(8);
9023 ins_cost(BRANCH_COST);
9024 format %{ "BP$cmp $icc,$labl" %}
9025 // Prim = bits 24-22, Secnd = bits 31-30
9026 ins_encode( enc_bp( labl, cmp, icc ) );
9027 ins_avoid_back_to_back(AVOID_BEFORE);
9028 ins_pipe(br_cc);
9029 %}
9030
9031 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9032 match(If cmp icc);
9033 effect(USE labl);
9034
9035 ins_cost(BRANCH_COST);
9036 format %{ "BP$cmp $icc,$labl" %}
9037 // Prim = bits 24-22, Secnd = bits 31-30
9038 ins_encode( enc_bp( labl, cmp, icc ) );
9039 ins_avoid_back_to_back(AVOID_BEFORE);
9040 ins_pipe(br_cc);
9041 %}
9042
9043 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9044 match(If cmp pcc);
9045 effect(USE labl);
9046
9047 size(8);
9048 ins_cost(BRANCH_COST);
9049 format %{ "BP$cmp $pcc,$labl" %}
9050 ins_encode %{
9051 Label* L = $labl$$label;
9052 Assembler::Predict predict_taken =
9053 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9054
9055 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9056 __ delayed()->nop();
9057 %}
9058 ins_avoid_back_to_back(AVOID_BEFORE);
9059 ins_pipe(br_cc);
9060 %}
9061
9062 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9063 match(If cmp fcc);
9064 effect(USE labl);
9065
9066 size(8);
9067 ins_cost(BRANCH_COST);
9068 format %{ "FBP$cmp $fcc,$labl" %}
9069 ins_encode %{
9070 Label* L = $labl$$label;
9071 Assembler::Predict predict_taken =
9072 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9073
9074 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9075 __ delayed()->nop();
9076 %}
9077 ins_avoid_back_to_back(AVOID_BEFORE);
9078 ins_pipe(br_fcc);
9079 %}
9080
9081 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9082 match(CountedLoopEnd cmp icc);
9083 effect(USE labl);
9084
9085 size(8);
9086 ins_cost(BRANCH_COST);
9087 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9088 // Prim = bits 24-22, Secnd = bits 31-30
9089 ins_encode( enc_bp( labl, cmp, icc ) );
9090 ins_avoid_back_to_back(AVOID_BEFORE);
9091 ins_pipe(br_cc);
9092 %}
9093
9094 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9095 match(CountedLoopEnd cmp icc);
9096 effect(USE labl);
9097
9098 size(8);
9099 ins_cost(BRANCH_COST);
9100 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9101 // Prim = bits 24-22, Secnd = bits 31-30
9102 ins_encode( enc_bp( labl, cmp, icc ) );
9103 ins_avoid_back_to_back(AVOID_BEFORE);
9104 ins_pipe(br_cc);
9105 %}
9106
9107 // Compare and branch instructions
9108 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9109 match(If cmp (CmpI op1 op2));
9110 effect(USE labl, KILL icc);
9111
9112 size(12);
9113 ins_cost(BRANCH_COST);
9114 format %{ "CMP $op1,$op2\t! int\n\t"
9115 "BP$cmp $labl" %}
9116 ins_encode %{
9117 Label* L = $labl$$label;
9118 Assembler::Predict predict_taken =
9119 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9120 __ cmp($op1$$Register, $op2$$Register);
9121 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9122 __ delayed()->nop();
9123 %}
9124 ins_pipe(cmp_br_reg_reg);
9125 %}
9126
9127 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9128 match(If cmp (CmpI op1 op2));
9129 effect(USE labl, KILL icc);
9130
9131 size(12);
9132 ins_cost(BRANCH_COST);
9133 format %{ "CMP $op1,$op2\t! int\n\t"
9134 "BP$cmp $labl" %}
9135 ins_encode %{
9136 Label* L = $labl$$label;
9137 Assembler::Predict predict_taken =
9138 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9139 __ cmp($op1$$Register, $op2$$constant);
9140 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9141 __ delayed()->nop();
9142 %}
9143 ins_pipe(cmp_br_reg_imm);
9144 %}
9145
9146 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9147 match(If cmp (CmpU op1 op2));
9148 effect(USE labl, KILL icc);
9149
9150 size(12);
9151 ins_cost(BRANCH_COST);
9152 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9153 "BP$cmp $labl" %}
9154 ins_encode %{
9155 Label* L = $labl$$label;
9156 Assembler::Predict predict_taken =
9157 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9158 __ cmp($op1$$Register, $op2$$Register);
9159 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9160 __ delayed()->nop();
9161 %}
9162 ins_pipe(cmp_br_reg_reg);
9163 %}
9164
9165 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9166 match(If cmp (CmpU op1 op2));
9167 effect(USE labl, KILL icc);
9168
9169 size(12);
9170 ins_cost(BRANCH_COST);
9171 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9172 "BP$cmp $labl" %}
9173 ins_encode %{
9174 Label* L = $labl$$label;
9175 Assembler::Predict predict_taken =
9176 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9177 __ cmp($op1$$Register, $op2$$constant);
9178 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9179 __ delayed()->nop();
9180 %}
9181 ins_pipe(cmp_br_reg_imm);
9182 %}
9183
9184 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9185 match(If cmp (CmpL op1 op2));
9186 effect(USE labl, KILL xcc);
9187
9188 size(12);
9189 ins_cost(BRANCH_COST);
9190 format %{ "CMP $op1,$op2\t! long\n\t"
9191 "BP$cmp $labl" %}
9192 ins_encode %{
9193 Label* L = $labl$$label;
9194 Assembler::Predict predict_taken =
9195 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9196 __ cmp($op1$$Register, $op2$$Register);
9197 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9198 __ delayed()->nop();
9199 %}
9200 ins_pipe(cmp_br_reg_reg);
9201 %}
9202
9203 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9204 match(If cmp (CmpL op1 op2));
9205 effect(USE labl, KILL xcc);
9206
9207 size(12);
9208 ins_cost(BRANCH_COST);
9209 format %{ "CMP $op1,$op2\t! long\n\t"
9210 "BP$cmp $labl" %}
9211 ins_encode %{
9212 Label* L = $labl$$label;
9213 Assembler::Predict predict_taken =
9214 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9215 __ cmp($op1$$Register, $op2$$constant);
9216 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9217 __ delayed()->nop();
9218 %}
9219 ins_pipe(cmp_br_reg_imm);
9220 %}
9221
9222 // Compare Pointers and branch
9223 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9224 match(If cmp (CmpP op1 op2));
9225 effect(USE labl, KILL pcc);
9226
9227 size(12);
9228 ins_cost(BRANCH_COST);
9229 format %{ "CMP $op1,$op2\t! ptr\n\t"
9230 "B$cmp $labl" %}
9231 ins_encode %{
9232 Label* L = $labl$$label;
9233 Assembler::Predict predict_taken =
9234 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9235 __ cmp($op1$$Register, $op2$$Register);
9236 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9237 __ delayed()->nop();
9238 %}
9239 ins_pipe(cmp_br_reg_reg);
9240 %}
9241
9242 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9243 match(If cmp (CmpP op1 null));
9244 effect(USE labl, KILL pcc);
9245
9246 size(12);
9247 ins_cost(BRANCH_COST);
9248 format %{ "CMP $op1,0\t! ptr\n\t"
9249 "B$cmp $labl" %}
9250 ins_encode %{
9251 Label* L = $labl$$label;
9252 Assembler::Predict predict_taken =
9253 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9254 __ cmp($op1$$Register, G0);
9255 // bpr() is not used here since it has shorter distance.
9256 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9257 __ delayed()->nop();
9258 %}
9259 ins_pipe(cmp_br_reg_reg);
9260 %}
9261
9262 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9263 match(If cmp (CmpN op1 op2));
9264 effect(USE labl, KILL icc);
9265
9266 size(12);
9267 ins_cost(BRANCH_COST);
9268 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9269 "BP$cmp $labl" %}
9270 ins_encode %{
9271 Label* L = $labl$$label;
9272 Assembler::Predict predict_taken =
9273 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9274 __ cmp($op1$$Register, $op2$$Register);
9275 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9276 __ delayed()->nop();
9277 %}
9278 ins_pipe(cmp_br_reg_reg);
9279 %}
9280
9281 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9282 match(If cmp (CmpN op1 null));
9283 effect(USE labl, KILL icc);
9284
9285 size(12);
9286 ins_cost(BRANCH_COST);
9287 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9288 "BP$cmp $labl" %}
9289 ins_encode %{
9290 Label* L = $labl$$label;
9291 Assembler::Predict predict_taken =
9292 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9293 __ cmp($op1$$Register, G0);
9294 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9295 __ delayed()->nop();
9296 %}
9297 ins_pipe(cmp_br_reg_reg);
9298 %}
9299
9300 // Loop back branch
9301 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9302 match(CountedLoopEnd cmp (CmpI op1 op2));
9303 effect(USE labl, KILL icc);
9304
9305 size(12);
9306 ins_cost(BRANCH_COST);
9307 format %{ "CMP $op1,$op2\t! int\n\t"
9308 "BP$cmp $labl\t! Loop end" %}
9309 ins_encode %{
9310 Label* L = $labl$$label;
9311 Assembler::Predict predict_taken =
9312 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9313 __ cmp($op1$$Register, $op2$$Register);
9314 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9315 __ delayed()->nop();
9316 %}
9317 ins_pipe(cmp_br_reg_reg);
9318 %}
9319
9320 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9321 match(CountedLoopEnd cmp (CmpI op1 op2));
9322 effect(USE labl, KILL icc);
9323
9324 size(12);
9325 ins_cost(BRANCH_COST);
9326 format %{ "CMP $op1,$op2\t! int\n\t"
9327 "BP$cmp $labl\t! Loop end" %}
9328 ins_encode %{
9329 Label* L = $labl$$label;
9330 Assembler::Predict predict_taken =
9331 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9332 __ cmp($op1$$Register, $op2$$constant);
9333 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9334 __ delayed()->nop();
9335 %}
9336 ins_pipe(cmp_br_reg_imm);
9337 %}
9338
9339 // Short compare and branch instructions
9340 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9341 match(If cmp (CmpI op1 op2));
9342 predicate(UseCBCond);
9343 effect(USE labl, KILL icc);
9344
9345 size(4);
9346 ins_cost(BRANCH_COST);
9347 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9348 ins_encode %{
9349 Label* L = $labl$$label;
9350 assert(__ use_cbcond(*L), "back to back cbcond");
9351 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9352 %}
9353 ins_short_branch(1);
9354 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9355 ins_pipe(cbcond_reg_reg);
9356 %}
9357
9358 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9359 match(If cmp (CmpI op1 op2));
9360 predicate(UseCBCond);
9361 effect(USE labl, KILL icc);
9362
9363 size(4);
9364 ins_cost(BRANCH_COST);
9365 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9366 ins_encode %{
9367 Label* L = $labl$$label;
9368 assert(__ use_cbcond(*L), "back to back cbcond");
9369 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9370 %}
9371 ins_short_branch(1);
9372 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9373 ins_pipe(cbcond_reg_imm);
9374 %}
9375
9376 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9377 match(If cmp (CmpU op1 op2));
9378 predicate(UseCBCond);
9379 effect(USE labl, KILL icc);
9380
9381 size(4);
9382 ins_cost(BRANCH_COST);
9383 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9384 ins_encode %{
9385 Label* L = $labl$$label;
9386 assert(__ use_cbcond(*L), "back to back cbcond");
9387 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9388 %}
9389 ins_short_branch(1);
9390 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9391 ins_pipe(cbcond_reg_reg);
9392 %}
9393
9394 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9395 match(If cmp (CmpU op1 op2));
9396 predicate(UseCBCond);
9397 effect(USE labl, KILL icc);
9398
9399 size(4);
9400 ins_cost(BRANCH_COST);
9401 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9402 ins_encode %{
9403 Label* L = $labl$$label;
9404 assert(__ use_cbcond(*L), "back to back cbcond");
9405 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9406 %}
9407 ins_short_branch(1);
9408 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9409 ins_pipe(cbcond_reg_imm);
9410 %}
9411
9412 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9413 match(If cmp (CmpL op1 op2));
9414 predicate(UseCBCond);
9415 effect(USE labl, KILL xcc);
9416
9417 size(4);
9418 ins_cost(BRANCH_COST);
9419 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9420 ins_encode %{
9421 Label* L = $labl$$label;
9422 assert(__ use_cbcond(*L), "back to back cbcond");
9423 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9424 %}
9425 ins_short_branch(1);
9426 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9427 ins_pipe(cbcond_reg_reg);
9428 %}
9429
9430 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9431 match(If cmp (CmpL op1 op2));
9432 predicate(UseCBCond);
9433 effect(USE labl, KILL xcc);
9434
9435 size(4);
9436 ins_cost(BRANCH_COST);
9437 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9438 ins_encode %{
9439 Label* L = $labl$$label;
9440 assert(__ use_cbcond(*L), "back to back cbcond");
9441 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9442 %}
9443 ins_short_branch(1);
9444 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9445 ins_pipe(cbcond_reg_imm);
9446 %}
9447
9448 // Compare Pointers and branch
9449 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9450 match(If cmp (CmpP op1 op2));
9451 predicate(UseCBCond);
9452 effect(USE labl, KILL pcc);
9453
9454 size(4);
9455 ins_cost(BRANCH_COST);
9456 #ifdef _LP64
9457 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9458 #else
9459 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9460 #endif
9461 ins_encode %{
9462 Label* L = $labl$$label;
9463 assert(__ use_cbcond(*L), "back to back cbcond");
9464 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9465 %}
9466 ins_short_branch(1);
9467 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9468 ins_pipe(cbcond_reg_reg);
9469 %}
9470
9471 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9472 match(If cmp (CmpP op1 null));
9473 predicate(UseCBCond);
9474 effect(USE labl, KILL pcc);
9475
9476 size(4);
9477 ins_cost(BRANCH_COST);
9478 #ifdef _LP64
9479 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9480 #else
9481 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9482 #endif
9483 ins_encode %{
9484 Label* L = $labl$$label;
9485 assert(__ use_cbcond(*L), "back to back cbcond");
9486 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9487 %}
9488 ins_short_branch(1);
9489 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9490 ins_pipe(cbcond_reg_reg);
9491 %}
9492
9493 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9494 match(If cmp (CmpN op1 op2));
9495 predicate(UseCBCond);
9496 effect(USE labl, KILL icc);
9497
9498 size(4);
9499 ins_cost(BRANCH_COST);
9500 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9501 ins_encode %{
9502 Label* L = $labl$$label;
9503 assert(__ use_cbcond(*L), "back to back cbcond");
9504 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9505 %}
9506 ins_short_branch(1);
9507 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9508 ins_pipe(cbcond_reg_reg);
9509 %}
9510
9511 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9512 match(If cmp (CmpN op1 null));
9513 predicate(UseCBCond);
9514 effect(USE labl, KILL icc);
9515
9516 size(4);
9517 ins_cost(BRANCH_COST);
9518 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9519 ins_encode %{
9520 Label* L = $labl$$label;
9521 assert(__ use_cbcond(*L), "back to back cbcond");
9522 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9523 %}
9524 ins_short_branch(1);
9525 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9526 ins_pipe(cbcond_reg_reg);
9527 %}
9528
9529 // Loop back branch
9530 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9531 match(CountedLoopEnd cmp (CmpI op1 op2));
9532 predicate(UseCBCond);
9533 effect(USE labl, KILL icc);
9534
9535 size(4);
9536 ins_cost(BRANCH_COST);
9537 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9538 ins_encode %{
9539 Label* L = $labl$$label;
9540 assert(__ use_cbcond(*L), "back to back cbcond");
9541 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9542 %}
9543 ins_short_branch(1);
9544 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9545 ins_pipe(cbcond_reg_reg);
9546 %}
9547
9548 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9549 match(CountedLoopEnd cmp (CmpI op1 op2));
9550 predicate(UseCBCond);
9551 effect(USE labl, KILL icc);
9552
9553 size(4);
9554 ins_cost(BRANCH_COST);
9555 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9556 ins_encode %{
9557 Label* L = $labl$$label;
9558 assert(__ use_cbcond(*L), "back to back cbcond");
9559 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9560 %}
9561 ins_short_branch(1);
9562 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9563 ins_pipe(cbcond_reg_imm);
9564 %}
9565
9566 // Branch-on-register tests all 64 bits. We assume that values
9567 // in 64-bit registers always remains zero or sign extended
9568 // unless our code munges the high bits. Interrupts can chop
9569 // the high order bits to zero or sign at any time.
9570 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9571 match(If cmp (CmpI op1 zero));
9572 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9573 effect(USE labl);
9574
9575 size(8);
9576 ins_cost(BRANCH_COST);
9577 format %{ "BR$cmp $op1,$labl" %}
9578 ins_encode( enc_bpr( labl, cmp, op1 ) );
9579 ins_avoid_back_to_back(AVOID_BEFORE);
9580 ins_pipe(br_reg);
9581 %}
9582
9583 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9584 match(If cmp (CmpP op1 null));
9585 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9586 effect(USE labl);
9587
9588 size(8);
9589 ins_cost(BRANCH_COST);
9590 format %{ "BR$cmp $op1,$labl" %}
9591 ins_encode( enc_bpr( labl, cmp, op1 ) );
9592 ins_avoid_back_to_back(AVOID_BEFORE);
9593 ins_pipe(br_reg);
9594 %}
9595
9596 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9597 match(If cmp (CmpL op1 zero));
9598 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9599 effect(USE labl);
9600
9601 size(8);
9602 ins_cost(BRANCH_COST);
9603 format %{ "BR$cmp $op1,$labl" %}
9604 ins_encode( enc_bpr( labl, cmp, op1 ) );
9605 ins_avoid_back_to_back(AVOID_BEFORE);
9606 ins_pipe(br_reg);
9607 %}
9608
9609
9610 // ============================================================================
9611 // Long Compare
9612 //
9613 // Currently we hold longs in 2 registers. Comparing such values efficiently
9614 // is tricky. The flavor of compare used depends on whether we are testing
9615 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9616 // The GE test is the negated LT test. The LE test can be had by commuting
9617 // the operands (yielding a GE test) and then negating; negate again for the
9618 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9619 // NE test is negated from that.
9620
9621 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9622 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9623 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9624 // are collapsed internally in the ADLC's dfa-gen code. The match for
9625 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9626 // foo match ends up with the wrong leaf. One fix is to not match both
9627 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9628 // both forms beat the trinary form of long-compare and both are very useful
9629 // on Intel which has so few registers.
9630
9631 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9632 match(If cmp xcc);
9633 effect(USE labl);
9634
9635 size(8);
9636 ins_cost(BRANCH_COST);
9637 format %{ "BP$cmp $xcc,$labl" %}
9638 ins_encode %{
9639 Label* L = $labl$$label;
9640 Assembler::Predict predict_taken =
9641 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9642
9643 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9644 __ delayed()->nop();
9645 %}
9646 ins_avoid_back_to_back(AVOID_BEFORE);
9647 ins_pipe(br_cc);
9648 %}
9649
9650 // Manifest a CmpL3 result in an integer register. Very painful.
9651 // This is the test to avoid.
9652 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9653 match(Set dst (CmpL3 src1 src2) );
9654 effect( KILL ccr );
9655 ins_cost(6*DEFAULT_COST);
9656 size(24);
9657 format %{ "CMP $src1,$src2\t\t! long\n"
9658 "\tBLT,a,pn done\n"
9659 "\tMOV -1,$dst\t! delay slot\n"
9660 "\tBGT,a,pn done\n"
9661 "\tMOV 1,$dst\t! delay slot\n"
9662 "\tCLR $dst\n"
9663 "done:" %}
9664 ins_encode( cmpl_flag(src1,src2,dst) );
9665 ins_pipe(cmpL_reg);
9666 %}
9667
9668 // Conditional move
9669 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9670 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9671 ins_cost(150);
9672 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9673 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9674 ins_pipe(ialu_reg);
9675 %}
9676
9677 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9678 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9679 ins_cost(140);
9680 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9681 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9682 ins_pipe(ialu_imm);
9683 %}
9684
9685 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9686 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9687 ins_cost(150);
9688 format %{ "MOV$cmp $xcc,$src,$dst" %}
9689 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9690 ins_pipe(ialu_reg);
9691 %}
9692
9693 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9694 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9695 ins_cost(140);
9696 format %{ "MOV$cmp $xcc,$src,$dst" %}
9697 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9698 ins_pipe(ialu_imm);
9699 %}
9700
9701 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9702 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9703 ins_cost(150);
9704 format %{ "MOV$cmp $xcc,$src,$dst" %}
9705 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9706 ins_pipe(ialu_reg);
9707 %}
9708
9709 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9710 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9711 ins_cost(150);
9712 format %{ "MOV$cmp $xcc,$src,$dst" %}
9713 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9714 ins_pipe(ialu_reg);
9715 %}
9716
9717 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9718 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9719 ins_cost(140);
9720 format %{ "MOV$cmp $xcc,$src,$dst" %}
9721 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9722 ins_pipe(ialu_imm);
9723 %}
9724
9725 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9726 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9727 ins_cost(150);
9728 opcode(0x101);
9729 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9730 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9731 ins_pipe(int_conditional_float_move);
9732 %}
9733
9734 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9735 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9736 ins_cost(150);
9737 opcode(0x102);
9738 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9739 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9740 ins_pipe(int_conditional_float_move);
9741 %}
9742
9743 // ============================================================================
9744 // Safepoint Instruction
9745 instruct safePoint_poll(iRegP poll) %{
9746 match(SafePoint poll);
9747 effect(USE poll);
9748
9749 size(4);
9750 #ifdef _LP64
9751 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9752 #else
9753 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9754 #endif
9755 ins_encode %{
9756 __ relocate(relocInfo::poll_type);
9757 __ ld_ptr($poll$$Register, 0, G0);
9758 %}
9759 ins_pipe(loadPollP);
9760 %}
9761
9762 // ============================================================================
9763 // Call Instructions
9764 // Call Java Static Instruction
9765 instruct CallStaticJavaDirect( method meth ) %{
9766 match(CallStaticJava);
9767 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9768 effect(USE meth);
9769
9770 size(8);
9771 ins_cost(CALL_COST);
9772 format %{ "CALL,static ; NOP ==> " %}
9773 ins_encode( Java_Static_Call( meth ), call_epilog );
9774 ins_avoid_back_to_back(AVOID_BEFORE);
9775 ins_pipe(simple_call);
9776 %}
9777
9778 // Call Java Static Instruction (method handle version)
9779 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9780 match(CallStaticJava);
9781 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9782 effect(USE meth, KILL l7_mh_SP_save);
9783
9784 size(16);
9785 ins_cost(CALL_COST);
9786 format %{ "CALL,static/MethodHandle" %}
9787 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9788 ins_pipe(simple_call);
9789 %}
9790
9791 // Call Java Dynamic Instruction
9792 instruct CallDynamicJavaDirect( method meth ) %{
9793 match(CallDynamicJava);
9794 effect(USE meth);
9795
9796 ins_cost(CALL_COST);
9797 format %{ "SET (empty),R_G5\n\t"
9798 "CALL,dynamic ; NOP ==> " %}
9799 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9800 ins_pipe(call);
9801 %}
9802
9803 // Call Runtime Instruction
9804 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9805 match(CallRuntime);
9806 effect(USE meth, KILL l7);
9807 ins_cost(CALL_COST);
9808 format %{ "CALL,runtime" %}
9809 ins_encode( Java_To_Runtime( meth ),
9810 call_epilog, adjust_long_from_native_call );
9811 ins_avoid_back_to_back(AVOID_BEFORE);
9812 ins_pipe(simple_call);
9813 %}
9814
9815 // Call runtime without safepoint - same as CallRuntime
9816 instruct CallLeafDirect(method meth, l7RegP l7) %{
9817 match(CallLeaf);
9818 effect(USE meth, KILL l7);
9819 ins_cost(CALL_COST);
9820 format %{ "CALL,runtime leaf" %}
9821 ins_encode( Java_To_Runtime( meth ),
9822 call_epilog,
9823 adjust_long_from_native_call );
9824 ins_avoid_back_to_back(AVOID_BEFORE);
9825 ins_pipe(simple_call);
9826 %}
9827
9828 // Call runtime without safepoint - same as CallLeaf
9829 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9830 match(CallLeafNoFP);
9831 effect(USE meth, KILL l7);
9832 ins_cost(CALL_COST);
9833 format %{ "CALL,runtime leaf nofp" %}
9834 ins_encode( Java_To_Runtime( meth ),
9835 call_epilog,
9836 adjust_long_from_native_call );
9837 ins_avoid_back_to_back(AVOID_BEFORE);
9838 ins_pipe(simple_call);
9839 %}
9840
9841 // Tail Call; Jump from runtime stub to Java code.
9842 // Also known as an 'interprocedural jump'.
9843 // Target of jump will eventually return to caller.
9844 // TailJump below removes the return address.
9845 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9846 match(TailCall jump_target method_oop );
9847
9848 ins_cost(CALL_COST);
9849 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9850 ins_encode(form_jmpl(jump_target));
9851 ins_avoid_back_to_back(AVOID_BEFORE);
9852 ins_pipe(tail_call);
9853 %}
9854
9855
9856 // Return Instruction
9857 instruct Ret() %{
9858 match(Return);
9859
9860 // The epilogue node did the ret already.
9861 size(0);
9862 format %{ "! return" %}
9863 ins_encode();
9864 ins_pipe(empty);
9865 %}
9866
9867
9868 // Tail Jump; remove the return address; jump to target.
9869 // TailCall above leaves the return address around.
9870 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9871 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9872 // "restore" before this instruction (in Epilogue), we need to materialize it
9873 // in %i0.
9874 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9875 match( TailJump jump_target ex_oop );
9876 ins_cost(CALL_COST);
9877 format %{ "! discard R_O7\n\t"
9878 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9879 ins_encode(form_jmpl_set_exception_pc(jump_target));
9880 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9881 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9882 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9883 ins_avoid_back_to_back(AVOID_BEFORE);
9884 ins_pipe(tail_call);
9885 %}
9886
9887 // Create exception oop: created by stack-crawling runtime code.
9888 // Created exception is now available to this handler, and is setup
9889 // just prior to jumping to this handler. No code emitted.
9890 instruct CreateException( o0RegP ex_oop )
9891 %{
9892 match(Set ex_oop (CreateEx));
9893 ins_cost(0);
9894
9895 size(0);
9896 // use the following format syntax
9897 format %{ "! exception oop is in R_O0; no code emitted" %}
9898 ins_encode();
9899 ins_pipe(empty);
9900 %}
9901
9902
9903 // Rethrow exception:
9904 // The exception oop will come in the first argument position.
9905 // Then JUMP (not call) to the rethrow stub code.
9906 instruct RethrowException()
9907 %{
9908 match(Rethrow);
9909 ins_cost(CALL_COST);
9910
9911 // use the following format syntax
9912 format %{ "Jmp rethrow_stub" %}
9913 ins_encode(enc_rethrow);
9914 ins_avoid_back_to_back(AVOID_BEFORE);
9915 ins_pipe(tail_call);
9916 %}
9917
9918
9919 // Die now
9920 instruct ShouldNotReachHere( )
9921 %{
9922 match(Halt);
9923 ins_cost(CALL_COST);
9924
9925 size(4);
9926 // Use the following format syntax
9927 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9928 ins_encode( form2_illtrap() );
9929 ins_pipe(tail_call);
9930 %}
9931
9932 // ============================================================================
9933 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9934 // array for an instance of the superklass. Set a hidden internal cache on a
9935 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9936 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9937 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9938 match(Set index (PartialSubtypeCheck sub super));
9939 effect( KILL pcc, KILL o7 );
9940 ins_cost(DEFAULT_COST*10);
9941 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9942 ins_encode( enc_PartialSubtypeCheck() );
9943 ins_avoid_back_to_back(AVOID_BEFORE);
9944 ins_pipe(partial_subtype_check_pipe);
9945 %}
9946
9947 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9948 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9949 effect( KILL idx, KILL o7 );
9950 ins_cost(DEFAULT_COST*10);
9951 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9952 ins_encode( enc_PartialSubtypeCheck() );
9953 ins_avoid_back_to_back(AVOID_BEFORE);
9954 ins_pipe(partial_subtype_check_pipe);
9955 %}
9956
9957
9958 // ============================================================================
9959 // inlined locking and unlocking
9960
9961 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9962 match(Set pcc (FastLock object box));
9963
9964 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9965 ins_cost(100);
9966
9967 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9968 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9969 ins_pipe(long_memory_op);
9970 %}
9971
9972
9973 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9974 match(Set pcc (FastUnlock object box));
9975 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9976 ins_cost(100);
9977
9978 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9979 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9980 ins_pipe(long_memory_op);
9981 %}
9982
9983 // The encodings are generic.
9984 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9985 predicate(!use_block_zeroing(n->in(2)) );
9986 match(Set dummy (ClearArray cnt base));
9987 effect(TEMP temp, KILL ccr);
9988 ins_cost(300);
9989 format %{ "MOV $cnt,$temp\n"
9990 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9991 " BRge loop\t\t! Clearing loop\n"
9992 " STX G0,[$base+$temp]\t! delay slot" %}
9993
9994 ins_encode %{
9995 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9996 Register nof_bytes_arg = $cnt$$Register;
9997 Register nof_bytes_tmp = $temp$$Register;
9998 Register base_pointer_arg = $base$$Register;
9999
10000 Label loop;
10001 __ mov(nof_bytes_arg, nof_bytes_tmp);
10002
10003 // Loop and clear, walking backwards through the array.
10004 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10005 __ bind(loop);
10006 __ deccc(nof_bytes_tmp, 8);
10007 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10008 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10009 // %%%% this mini-loop must not cross a cache boundary!
10010 %}
10011 ins_pipe(long_memory_op);
10012 %}
10013
10014 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10015 predicate(use_block_zeroing(n->in(2)));
10016 match(Set dummy (ClearArray cnt base));
10017 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10018 ins_cost(300);
10019 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10020
10021 ins_encode %{
10022
10023 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10024 Register to = $base$$Register;
10025 Register count = $cnt$$Register;
10026
10027 Label Ldone;
10028 __ nop(); // Separate short branches
10029 // Use BIS for zeroing (temp is not used).
10030 __ bis_zeroing(to, count, G0, Ldone);
10031 __ bind(Ldone);
10032
10033 %}
10034 ins_pipe(long_memory_op);
10035 %}
10036
10037 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10038 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10039 match(Set dummy (ClearArray cnt base));
10040 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10041 ins_cost(300);
10042 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10043
10044 ins_encode %{
10045
10046 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10047 Register to = $base$$Register;
10048 Register count = $cnt$$Register;
10049 Register temp = $tmp$$Register;
10050
10051 Label Ldone;
10052 __ nop(); // Separate short branches
10053 // Use BIS for zeroing
10054 __ bis_zeroing(to, count, temp, Ldone);
10055 __ bind(Ldone);
10056
10057 %}
10058 ins_pipe(long_memory_op);
10059 %}
10060
10061 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10062 o7RegI tmp, flagsReg ccr) %{
10063 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10064 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10065 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10066 ins_cost(300);
10067 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10068 ins_encode %{
10069 __ string_compare($str1$$Register, $str2$$Register,
10070 $cnt1$$Register, $cnt2$$Register,
10071 $tmp$$Register, $tmp$$Register,
10072 $result$$Register, StrIntrinsicNode::LL);
10073 %}
10074 ins_pipe(long_memory_op);
10075 %}
10076
10077 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10078 o7RegI tmp, flagsReg ccr) %{
10079 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10080 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10081 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10082 ins_cost(300);
10083 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10084 ins_encode %{
10085 __ string_compare($str1$$Register, $str2$$Register,
10086 $cnt1$$Register, $cnt2$$Register,
10087 $tmp$$Register, $tmp$$Register,
10088 $result$$Register, StrIntrinsicNode::UU);
10089 %}
10090 ins_pipe(long_memory_op);
10091 %}
10092
10093 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10094 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10095 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10096 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10097 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10098 ins_cost(300);
10099 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10100 ins_encode %{
10101 __ string_compare($str1$$Register, $str2$$Register,
10102 $cnt1$$Register, $cnt2$$Register,
10103 $tmp1$$Register, $tmp2$$Register,
10104 $result$$Register, StrIntrinsicNode::LU);
10105 %}
10106 ins_pipe(long_memory_op);
10107 %}
10108
10109 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10110 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10111 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10112 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10113 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10114 ins_cost(300);
10115 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10116 ins_encode %{
10117 __ string_compare($str2$$Register, $str1$$Register,
10118 $cnt2$$Register, $cnt1$$Register,
10119 $tmp1$$Register, $tmp2$$Register,
10120 $result$$Register, StrIntrinsicNode::UL);
10121 %}
10122 ins_pipe(long_memory_op);
10123 %}
10124
10125 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10126 o7RegI tmp, flagsReg ccr) %{
10127 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10128 match(Set result (StrEquals (Binary str1 str2) cnt));
10129 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10130 ins_cost(300);
10131 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10132 ins_encode %{
10133 __ array_equals(false, $str1$$Register, $str2$$Register,
10134 $cnt$$Register, $tmp$$Register,
10135 $result$$Register, true /* byte */);
10136 %}
10137 ins_pipe(long_memory_op);
10138 %}
10139
10140 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10141 o7RegI tmp, flagsReg ccr) %{
10142 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10143 match(Set result (StrEquals (Binary str1 str2) cnt));
10144 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10145 ins_cost(300);
10146 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10147 ins_encode %{
10148 __ array_equals(false, $str1$$Register, $str2$$Register,
10149 $cnt$$Register, $tmp$$Register,
10150 $result$$Register, false /* byte */);
10151 %}
10152 ins_pipe(long_memory_op);
10153 %}
10154
10155 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10156 o7RegI tmp2, flagsReg ccr) %{
10157 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10158 match(Set result (AryEq ary1 ary2));
10159 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10160 ins_cost(300);
10161 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10162 ins_encode %{
10163 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10164 $tmp1$$Register, $tmp2$$Register,
10165 $result$$Register, true /* byte */);
10166 %}
10167 ins_pipe(long_memory_op);
10168 %}
10169
10170 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10171 o7RegI tmp2, flagsReg ccr) %{
10172 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10173 match(Set result (AryEq ary1 ary2));
10174 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10175 ins_cost(300);
10176 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10177 ins_encode %{
10178 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10179 $tmp1$$Register, $tmp2$$Register,
10180 $result$$Register, false /* byte */);
10181 %}
10182 ins_pipe(long_memory_op);
10183 %}
10184
10185 instruct has_negatives(o0RegP pAryR, g3RegI iSizeR, notemp_iRegI resultR,
10186 iRegL tmp1L, iRegL tmp2L, iRegL tmp3L, iRegL tmp4L,
10187 flagsReg ccr)
10188 %{
10189 match(Set resultR (HasNegatives pAryR iSizeR));
10190 effect(TEMP resultR, TEMP tmp1L, TEMP tmp2L, TEMP tmp3L, TEMP tmp4L, USE pAryR, USE iSizeR, KILL ccr);
10191 format %{ "has negatives byte[] $pAryR,$iSizeR -> $resultR // KILL $tmp1L,$tmp2L,$tmp3L,$tmp4L" %}
10192 ins_encode %{
10193 __ has_negatives($pAryR$$Register, $iSizeR$$Register,
10194 $resultR$$Register,
10195 $tmp1L$$Register, $tmp2L$$Register,
10196 $tmp3L$$Register, $tmp4L$$Register);
10197 %}
10198 ins_pipe(long_memory_op);
10199 %}
10200
10201 // char[] to byte[] compression
10202 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10203 predicate(UseVIS < 3);
10204 match(Set result (StrCompressedCopy src (Binary dst len)));
10205 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10206 ins_cost(300);
10207 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10208 ins_encode %{
10209 Label Ldone;
10210 __ signx($len$$Register);
10211 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10212 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10213 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10214 __ bind(Ldone);
10215 %}
10216 ins_pipe(long_memory_op);
10217 %}
10218
10219 // fast char[] to byte[] compression using VIS instructions
10220 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10221 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10222 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10223 predicate(UseVIS >= 3);
10224 match(Set result (StrCompressedCopy src (Binary dst len)));
10225 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10226 ins_cost(300);
10227 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10228 ins_encode %{
10229 Label Ldone;
10230 __ signx($len$$Register);
10231 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10232 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10233 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10234 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10235 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10236 __ bind(Ldone);
10237 %}
10238 ins_pipe(long_memory_op);
10239 %}
10240
10241 // byte[] to char[] inflation
10242 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10243 iRegL tmp, flagsReg ccr) %{
10244 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10245 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10246 ins_cost(300);
10247 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10248 ins_encode %{
10249 Label Ldone;
10250 __ signx($len$$Register);
10251 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10252 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10253 __ bind(Ldone);
10254 %}
10255 ins_pipe(long_memory_op);
10256 %}
10257
10258 // fast byte[] to char[] inflation using VIS instructions
10259 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10260 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10261 predicate(UseVIS >= 3);
10262 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10263 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10264 ins_cost(300);
10265 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10266 ins_encode %{
10267 Label Ldone;
10268 __ signx($len$$Register);
10269 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10270 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10271 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10272 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10273 __ bind(Ldone);
10274 %}
10275 ins_pipe(long_memory_op);
10276 %}
10277
10278
10279 //---------- Zeros Count Instructions ------------------------------------------
10280
10281 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10282 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10283 match(Set dst (CountLeadingZerosI src));
10284 effect(TEMP dst, TEMP tmp, KILL cr);
10285
10286 // x |= (x >> 1);
10287 // x |= (x >> 2);
10288 // x |= (x >> 4);
10289 // x |= (x >> 8);
10290 // x |= (x >> 16);
10291 // return (WORDBITS - popc(x));
10292 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10293 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10294 "OR $dst,$tmp,$dst\n\t"
10295 "SRL $dst,2,$tmp\n\t"
10296 "OR $dst,$tmp,$dst\n\t"
10297 "SRL $dst,4,$tmp\n\t"
10298 "OR $dst,$tmp,$dst\n\t"
10299 "SRL $dst,8,$tmp\n\t"
10300 "OR $dst,$tmp,$dst\n\t"
10301 "SRL $dst,16,$tmp\n\t"
10302 "OR $dst,$tmp,$dst\n\t"
10303 "POPC $dst,$dst\n\t"
10304 "MOV 32,$tmp\n\t"
10305 "SUB $tmp,$dst,$dst" %}
10306 ins_encode %{
10307 Register Rdst = $dst$$Register;
10308 Register Rsrc = $src$$Register;
10309 Register Rtmp = $tmp$$Register;
10310 __ srl(Rsrc, 1, Rtmp);
10311 __ srl(Rsrc, 0, Rdst);
10312 __ or3(Rdst, Rtmp, Rdst);
10313 __ srl(Rdst, 2, Rtmp);
10314 __ or3(Rdst, Rtmp, Rdst);
10315 __ srl(Rdst, 4, Rtmp);
10316 __ or3(Rdst, Rtmp, Rdst);
10317 __ srl(Rdst, 8, Rtmp);
10318 __ or3(Rdst, Rtmp, Rdst);
10319 __ srl(Rdst, 16, Rtmp);
10320 __ or3(Rdst, Rtmp, Rdst);
10321 __ popc(Rdst, Rdst);
10322 __ mov(BitsPerInt, Rtmp);
10323 __ sub(Rtmp, Rdst, Rdst);
10324 %}
10325 ins_pipe(ialu_reg);
10326 %}
10327
10328 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10329 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10330 match(Set dst (CountLeadingZerosL src));
10331 effect(TEMP dst, TEMP tmp, KILL cr);
10332
10333 // x |= (x >> 1);
10334 // x |= (x >> 2);
10335 // x |= (x >> 4);
10336 // x |= (x >> 8);
10337 // x |= (x >> 16);
10338 // x |= (x >> 32);
10339 // return (WORDBITS - popc(x));
10340 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10341 "OR $src,$tmp,$dst\n\t"
10342 "SRLX $dst,2,$tmp\n\t"
10343 "OR $dst,$tmp,$dst\n\t"
10344 "SRLX $dst,4,$tmp\n\t"
10345 "OR $dst,$tmp,$dst\n\t"
10346 "SRLX $dst,8,$tmp\n\t"
10347 "OR $dst,$tmp,$dst\n\t"
10348 "SRLX $dst,16,$tmp\n\t"
10349 "OR $dst,$tmp,$dst\n\t"
10350 "SRLX $dst,32,$tmp\n\t"
10351 "OR $dst,$tmp,$dst\n\t"
10352 "POPC $dst,$dst\n\t"
10353 "MOV 64,$tmp\n\t"
10354 "SUB $tmp,$dst,$dst" %}
10355 ins_encode %{
10356 Register Rdst = $dst$$Register;
10357 Register Rsrc = $src$$Register;
10358 Register Rtmp = $tmp$$Register;
10359 __ srlx(Rsrc, 1, Rtmp);
10360 __ or3( Rsrc, Rtmp, Rdst);
10361 __ srlx(Rdst, 2, Rtmp);
10362 __ or3( Rdst, Rtmp, Rdst);
10363 __ srlx(Rdst, 4, Rtmp);
10364 __ or3( Rdst, Rtmp, Rdst);
10365 __ srlx(Rdst, 8, Rtmp);
10366 __ or3( Rdst, Rtmp, Rdst);
10367 __ srlx(Rdst, 16, Rtmp);
10368 __ or3( Rdst, Rtmp, Rdst);
10369 __ srlx(Rdst, 32, Rtmp);
10370 __ or3( Rdst, Rtmp, Rdst);
10371 __ popc(Rdst, Rdst);
10372 __ mov(BitsPerLong, Rtmp);
10373 __ sub(Rtmp, Rdst, Rdst);
10374 %}
10375 ins_pipe(ialu_reg);
10376 %}
10377
10378 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10379 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10380 match(Set dst (CountTrailingZerosI src));
10381 effect(TEMP dst, KILL cr);
10382
10383 // return popc(~x & (x - 1));
10384 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10385 "ANDN $dst,$src,$dst\n\t"
10386 "SRL $dst,R_G0,$dst\n\t"
10387 "POPC $dst,$dst" %}
10388 ins_encode %{
10389 Register Rdst = $dst$$Register;
10390 Register Rsrc = $src$$Register;
10391 __ sub(Rsrc, 1, Rdst);
10392 __ andn(Rdst, Rsrc, Rdst);
10393 __ srl(Rdst, G0, Rdst);
10394 __ popc(Rdst, Rdst);
10395 %}
10396 ins_pipe(ialu_reg);
10397 %}
10398
10399 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10400 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10401 match(Set dst (CountTrailingZerosL src));
10402 effect(TEMP dst, KILL cr);
10403
10404 // return popc(~x & (x - 1));
10405 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10406 "ANDN $dst,$src,$dst\n\t"
10407 "POPC $dst,$dst" %}
10408 ins_encode %{
10409 Register Rdst = $dst$$Register;
10410 Register Rsrc = $src$$Register;
10411 __ sub(Rsrc, 1, Rdst);
10412 __ andn(Rdst, Rsrc, Rdst);
10413 __ popc(Rdst, Rdst);
10414 %}
10415 ins_pipe(ialu_reg);
10416 %}
10417
10418
10419 //---------- Population Count Instructions -------------------------------------
10420
10421 instruct popCountI(iRegIsafe dst, iRegI src) %{
10422 predicate(UsePopCountInstruction);
10423 match(Set dst (PopCountI src));
10424
10425 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10426 "POPC $dst, $dst" %}
10427 ins_encode %{
10428 __ srl($src$$Register, G0, $dst$$Register);
10429 __ popc($dst$$Register, $dst$$Register);
10430 %}
10431 ins_pipe(ialu_reg);
10432 %}
10433
10434 // Note: Long.bitCount(long) returns an int.
10435 instruct popCountL(iRegIsafe dst, iRegL src) %{
10436 predicate(UsePopCountInstruction);
10437 match(Set dst (PopCountL src));
10438
10439 format %{ "POPC $src, $dst" %}
10440 ins_encode %{
10441 __ popc($src$$Register, $dst$$Register);
10442 %}
10443 ins_pipe(ialu_reg);
10444 %}
10445
10446
10447 // ============================================================================
10448 //------------Bytes reverse--------------------------------------------------
10449
10450 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10451 match(Set dst (ReverseBytesI src));
10452
10453 // Op cost is artificially doubled to make sure that load or store
10454 // instructions are preferred over this one which requires a spill
10455 // onto a stack slot.
10456 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10457 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10458
10459 ins_encode %{
10460 __ set($src$$disp + STACK_BIAS, O7);
10461 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10462 %}
10463 ins_pipe( iload_mem );
10464 %}
10465
10466 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10467 match(Set dst (ReverseBytesL src));
10468
10469 // Op cost is artificially doubled to make sure that load or store
10470 // instructions are preferred over this one which requires a spill
10471 // onto a stack slot.
10472 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10473 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10474
10475 ins_encode %{
10476 __ set($src$$disp + STACK_BIAS, O7);
10477 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10478 %}
10479 ins_pipe( iload_mem );
10480 %}
10481
10482 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10483 match(Set dst (ReverseBytesUS src));
10484
10485 // Op cost is artificially doubled to make sure that load or store
10486 // instructions are preferred over this one which requires a spill
10487 // onto a stack slot.
10488 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10489 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10490
10491 ins_encode %{
10492 // the value was spilled as an int so bias the load
10493 __ set($src$$disp + STACK_BIAS + 2, O7);
10494 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10495 %}
10496 ins_pipe( iload_mem );
10497 %}
10498
10499 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10500 match(Set dst (ReverseBytesS src));
10501
10502 // Op cost is artificially doubled to make sure that load or store
10503 // instructions are preferred over this one which requires a spill
10504 // onto a stack slot.
10505 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10506 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10507
10508 ins_encode %{
10509 // the value was spilled as an int so bias the load
10510 __ set($src$$disp + STACK_BIAS + 2, O7);
10511 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10512 %}
10513 ins_pipe( iload_mem );
10514 %}
10515
10516 // Load Integer reversed byte order
10517 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10518 match(Set dst (ReverseBytesI (LoadI src)));
10519
10520 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10521 size(4);
10522 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10523
10524 ins_encode %{
10525 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10526 %}
10527 ins_pipe(iload_mem);
10528 %}
10529
10530 // Load Long - aligned and reversed
10531 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10532 match(Set dst (ReverseBytesL (LoadL src)));
10533
10534 ins_cost(MEMORY_REF_COST);
10535 size(4);
10536 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10537
10538 ins_encode %{
10539 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10540 %}
10541 ins_pipe(iload_mem);
10542 %}
10543
10544 // Load unsigned short / char reversed byte order
10545 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10546 match(Set dst (ReverseBytesUS (LoadUS src)));
10547
10548 ins_cost(MEMORY_REF_COST);
10549 size(4);
10550 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10551
10552 ins_encode %{
10553 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10554 %}
10555 ins_pipe(iload_mem);
10556 %}
10557
10558 // Load short reversed byte order
10559 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10560 match(Set dst (ReverseBytesS (LoadS src)));
10561
10562 ins_cost(MEMORY_REF_COST);
10563 size(4);
10564 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10565
10566 ins_encode %{
10567 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10568 %}
10569 ins_pipe(iload_mem);
10570 %}
10571
10572 // Store Integer reversed byte order
10573 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10574 match(Set dst (StoreI dst (ReverseBytesI src)));
10575
10576 ins_cost(MEMORY_REF_COST);
10577 size(4);
10578 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10579
10580 ins_encode %{
10581 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10582 %}
10583 ins_pipe(istore_mem_reg);
10584 %}
10585
10586 // Store Long reversed byte order
10587 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10588 match(Set dst (StoreL dst (ReverseBytesL src)));
10589
10590 ins_cost(MEMORY_REF_COST);
10591 size(4);
10592 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10593
10594 ins_encode %{
10595 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10596 %}
10597 ins_pipe(istore_mem_reg);
10598 %}
10599
10600 // Store unsighed short/char reversed byte order
10601 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10602 match(Set dst (StoreC dst (ReverseBytesUS src)));
10603
10604 ins_cost(MEMORY_REF_COST);
10605 size(4);
10606 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10607
10608 ins_encode %{
10609 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10610 %}
10611 ins_pipe(istore_mem_reg);
10612 %}
10613
10614 // Store short reversed byte order
10615 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10616 match(Set dst (StoreC dst (ReverseBytesS src)));
10617
10618 ins_cost(MEMORY_REF_COST);
10619 size(4);
10620 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10621
10622 ins_encode %{
10623 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10624 %}
10625 ins_pipe(istore_mem_reg);
10626 %}
10627
10628 // ====================VECTOR INSTRUCTIONS=====================================
10629
10630 // Load Aligned Packed values into a Double Register
10631 instruct loadV8(regD dst, memory mem) %{
10632 predicate(n->as_LoadVector()->memory_size() == 8);
10633 match(Set dst (LoadVector mem));
10634 ins_cost(MEMORY_REF_COST);
10635 size(4);
10636 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10637 ins_encode %{
10638 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10639 %}
10640 ins_pipe(floadD_mem);
10641 %}
10642
10643 // Store Vector in Double register to memory
10644 instruct storeV8(memory mem, regD src) %{
10645 predicate(n->as_StoreVector()->memory_size() == 8);
10646 match(Set mem (StoreVector mem src));
10647 ins_cost(MEMORY_REF_COST);
10648 size(4);
10649 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10650 ins_encode %{
10651 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10652 %}
10653 ins_pipe(fstoreD_mem_reg);
10654 %}
10655
10656 // Store Zero into vector in memory
10657 instruct storeV8B_zero(memory mem, immI0 zero) %{
10658 predicate(n->as_StoreVector()->memory_size() == 8);
10659 match(Set mem (StoreVector mem (ReplicateB zero)));
10660 ins_cost(MEMORY_REF_COST);
10661 size(4);
10662 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10663 ins_encode %{
10664 __ stx(G0, $mem$$Address);
10665 %}
10666 ins_pipe(fstoreD_mem_zero);
10667 %}
10668
10669 instruct storeV4S_zero(memory mem, immI0 zero) %{
10670 predicate(n->as_StoreVector()->memory_size() == 8);
10671 match(Set mem (StoreVector mem (ReplicateS zero)));
10672 ins_cost(MEMORY_REF_COST);
10673 size(4);
10674 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10675 ins_encode %{
10676 __ stx(G0, $mem$$Address);
10677 %}
10678 ins_pipe(fstoreD_mem_zero);
10679 %}
10680
10681 instruct storeV2I_zero(memory mem, immI0 zero) %{
10682 predicate(n->as_StoreVector()->memory_size() == 8);
10683 match(Set mem (StoreVector mem (ReplicateI zero)));
10684 ins_cost(MEMORY_REF_COST);
10685 size(4);
10686 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10687 ins_encode %{
10688 __ stx(G0, $mem$$Address);
10689 %}
10690 ins_pipe(fstoreD_mem_zero);
10691 %}
10692
10693 instruct storeV2F_zero(memory mem, immF0 zero) %{
10694 predicate(n->as_StoreVector()->memory_size() == 8);
10695 match(Set mem (StoreVector mem (ReplicateF zero)));
10696 ins_cost(MEMORY_REF_COST);
10697 size(4);
10698 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10699 ins_encode %{
10700 __ stx(G0, $mem$$Address);
10701 %}
10702 ins_pipe(fstoreD_mem_zero);
10703 %}
10704
10705 // Replicate scalar to packed byte values into Double register
10706 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10707 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10708 match(Set dst (ReplicateB src));
10709 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10710 format %{ "SLLX $src,56,$tmp\n\t"
10711 "SRLX $tmp, 8,$tmp2\n\t"
10712 "OR $tmp,$tmp2,$tmp\n\t"
10713 "SRLX $tmp,16,$tmp2\n\t"
10714 "OR $tmp,$tmp2,$tmp\n\t"
10715 "SRLX $tmp,32,$tmp2\n\t"
10716 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10717 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10718 ins_encode %{
10719 Register Rsrc = $src$$Register;
10720 Register Rtmp = $tmp$$Register;
10721 Register Rtmp2 = $tmp2$$Register;
10722 __ sllx(Rsrc, 56, Rtmp);
10723 __ srlx(Rtmp, 8, Rtmp2);
10724 __ or3 (Rtmp, Rtmp2, Rtmp);
10725 __ srlx(Rtmp, 16, Rtmp2);
10726 __ or3 (Rtmp, Rtmp2, Rtmp);
10727 __ srlx(Rtmp, 32, Rtmp2);
10728 __ or3 (Rtmp, Rtmp2, Rtmp);
10729 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10730 %}
10731 ins_pipe(ialu_reg);
10732 %}
10733
10734 // Replicate scalar to packed byte values into Double stack
10735 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10736 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10737 match(Set dst (ReplicateB src));
10738 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10739 format %{ "SLLX $src,56,$tmp\n\t"
10740 "SRLX $tmp, 8,$tmp2\n\t"
10741 "OR $tmp,$tmp2,$tmp\n\t"
10742 "SRLX $tmp,16,$tmp2\n\t"
10743 "OR $tmp,$tmp2,$tmp\n\t"
10744 "SRLX $tmp,32,$tmp2\n\t"
10745 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10746 "STX $tmp,$dst\t! regL to stkD" %}
10747 ins_encode %{
10748 Register Rsrc = $src$$Register;
10749 Register Rtmp = $tmp$$Register;
10750 Register Rtmp2 = $tmp2$$Register;
10751 __ sllx(Rsrc, 56, Rtmp);
10752 __ srlx(Rtmp, 8, Rtmp2);
10753 __ or3 (Rtmp, Rtmp2, Rtmp);
10754 __ srlx(Rtmp, 16, Rtmp2);
10755 __ or3 (Rtmp, Rtmp2, Rtmp);
10756 __ srlx(Rtmp, 32, Rtmp2);
10757 __ or3 (Rtmp, Rtmp2, Rtmp);
10758 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10759 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10760 %}
10761 ins_pipe(ialu_reg);
10762 %}
10763
10764 // Replicate scalar constant to packed byte values in Double register
10765 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10766 predicate(n->as_Vector()->length() == 8);
10767 match(Set dst (ReplicateB con));
10768 effect(KILL tmp);
10769 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10770 ins_encode %{
10771 // XXX This is a quick fix for 6833573.
10772 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10773 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10774 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10775 %}
10776 ins_pipe(loadConFD);
10777 %}
10778
10779 // Replicate scalar to packed char/short values into Double register
10780 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10781 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10782 match(Set dst (ReplicateS src));
10783 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10784 format %{ "SLLX $src,48,$tmp\n\t"
10785 "SRLX $tmp,16,$tmp2\n\t"
10786 "OR $tmp,$tmp2,$tmp\n\t"
10787 "SRLX $tmp,32,$tmp2\n\t"
10788 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10789 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10790 ins_encode %{
10791 Register Rsrc = $src$$Register;
10792 Register Rtmp = $tmp$$Register;
10793 Register Rtmp2 = $tmp2$$Register;
10794 __ sllx(Rsrc, 48, Rtmp);
10795 __ srlx(Rtmp, 16, Rtmp2);
10796 __ or3 (Rtmp, Rtmp2, Rtmp);
10797 __ srlx(Rtmp, 32, Rtmp2);
10798 __ or3 (Rtmp, Rtmp2, Rtmp);
10799 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10800 %}
10801 ins_pipe(ialu_reg);
10802 %}
10803
10804 // Replicate scalar to packed char/short values into Double stack
10805 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10806 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10807 match(Set dst (ReplicateS src));
10808 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10809 format %{ "SLLX $src,48,$tmp\n\t"
10810 "SRLX $tmp,16,$tmp2\n\t"
10811 "OR $tmp,$tmp2,$tmp\n\t"
10812 "SRLX $tmp,32,$tmp2\n\t"
10813 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10814 "STX $tmp,$dst\t! regL to stkD" %}
10815 ins_encode %{
10816 Register Rsrc = $src$$Register;
10817 Register Rtmp = $tmp$$Register;
10818 Register Rtmp2 = $tmp2$$Register;
10819 __ sllx(Rsrc, 48, Rtmp);
10820 __ srlx(Rtmp, 16, Rtmp2);
10821 __ or3 (Rtmp, Rtmp2, Rtmp);
10822 __ srlx(Rtmp, 32, Rtmp2);
10823 __ or3 (Rtmp, Rtmp2, Rtmp);
10824 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10825 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10826 %}
10827 ins_pipe(ialu_reg);
10828 %}
10829
10830 // Replicate scalar constant to packed char/short values in Double register
10831 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10832 predicate(n->as_Vector()->length() == 4);
10833 match(Set dst (ReplicateS con));
10834 effect(KILL tmp);
10835 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10836 ins_encode %{
10837 // XXX This is a quick fix for 6833573.
10838 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10839 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10840 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10841 %}
10842 ins_pipe(loadConFD);
10843 %}
10844
10845 // Replicate scalar to packed int values into Double register
10846 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10847 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10848 match(Set dst (ReplicateI src));
10849 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10850 format %{ "SLLX $src,32,$tmp\n\t"
10851 "SRLX $tmp,32,$tmp2\n\t"
10852 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10853 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10854 ins_encode %{
10855 Register Rsrc = $src$$Register;
10856 Register Rtmp = $tmp$$Register;
10857 Register Rtmp2 = $tmp2$$Register;
10858 __ sllx(Rsrc, 32, Rtmp);
10859 __ srlx(Rtmp, 32, Rtmp2);
10860 __ or3 (Rtmp, Rtmp2, Rtmp);
10861 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10862 %}
10863 ins_pipe(ialu_reg);
10864 %}
10865
10866 // Replicate scalar to packed int values into Double stack
10867 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10868 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10869 match(Set dst (ReplicateI src));
10870 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10871 format %{ "SLLX $src,32,$tmp\n\t"
10872 "SRLX $tmp,32,$tmp2\n\t"
10873 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10874 "STX $tmp,$dst\t! regL to stkD" %}
10875 ins_encode %{
10876 Register Rsrc = $src$$Register;
10877 Register Rtmp = $tmp$$Register;
10878 Register Rtmp2 = $tmp2$$Register;
10879 __ sllx(Rsrc, 32, Rtmp);
10880 __ srlx(Rtmp, 32, Rtmp2);
10881 __ or3 (Rtmp, Rtmp2, Rtmp);
10882 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10883 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10884 %}
10885 ins_pipe(ialu_reg);
10886 %}
10887
10888 // Replicate scalar zero constant to packed int values in Double register
10889 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10890 predicate(n->as_Vector()->length() == 2);
10891 match(Set dst (ReplicateI con));
10892 effect(KILL tmp);
10893 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10894 ins_encode %{
10895 // XXX This is a quick fix for 6833573.
10896 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10897 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10898 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10899 %}
10900 ins_pipe(loadConFD);
10901 %}
10902
10903 // Replicate scalar to packed float values into Double stack
10904 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10905 predicate(n->as_Vector()->length() == 2);
10906 match(Set dst (ReplicateF src));
10907 ins_cost(MEMORY_REF_COST*2);
10908 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10909 "STF $src,$dst.lo" %}
10910 opcode(Assembler::stf_op3);
10911 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10912 ins_pipe(fstoreF_stk_reg);
10913 %}
10914
10915 // Replicate scalar zero constant to packed float values in Double register
10916 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10917 predicate(n->as_Vector()->length() == 2);
10918 match(Set dst (ReplicateF con));
10919 effect(KILL tmp);
10920 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10921 ins_encode %{
10922 // XXX This is a quick fix for 6833573.
10923 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10924 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10925 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10926 %}
10927 ins_pipe(loadConFD);
10928 %}
10929
10930 //----------PEEPHOLE RULES-----------------------------------------------------
10931 // These must follow all instruction definitions as they use the names
10932 // defined in the instructions definitions.
10933 //
10934 // peepmatch ( root_instr_name [preceding_instruction]* );
10935 //
10936 // peepconstraint %{
10937 // (instruction_number.operand_name relational_op instruction_number.operand_name
10938 // [, ...] );
10939 // // instruction numbers are zero-based using left to right order in peepmatch
10940 //
10941 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10942 // // provide an instruction_number.operand_name for each operand that appears
10943 // // in the replacement instruction's match rule
10944 //
10945 // ---------VM FLAGS---------------------------------------------------------
10946 //
10947 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10948 //
10949 // Each peephole rule is given an identifying number starting with zero and
10950 // increasing by one in the order seen by the parser. An individual peephole
10951 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10952 // on the command-line.
10953 //
10954 // ---------CURRENT LIMITATIONS----------------------------------------------
10955 //
10956 // Only match adjacent instructions in same basic block
10957 // Only equality constraints
10958 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10959 // Only one replacement instruction
10960 //
10961 // ---------EXAMPLE----------------------------------------------------------
10962 //
10963 // // pertinent parts of existing instructions in architecture description
10964 // instruct movI(eRegI dst, eRegI src) %{
10965 // match(Set dst (CopyI src));
10966 // %}
10967 //
10968 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10969 // match(Set dst (AddI dst src));
10970 // effect(KILL cr);
10971 // %}
10972 //
10973 // // Change (inc mov) to lea
10974 // peephole %{
10975 // // increment preceeded by register-register move
10976 // peepmatch ( incI_eReg movI );
10977 // // require that the destination register of the increment
10978 // // match the destination register of the move
10979 // peepconstraint ( 0.dst == 1.dst );
10980 // // construct a replacement instruction that sets
10981 // // the destination to ( move's source register + one )
10982 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10983 // %}
10984 //
10985
10986 // // Change load of spilled value to only a spill
10987 // instruct storeI(memory mem, eRegI src) %{
10988 // match(Set mem (StoreI mem src));
10989 // %}
10990 //
10991 // instruct loadI(eRegI dst, memory mem) %{
10992 // match(Set dst (LoadI mem));
10993 // %}
10994 //
10995 // peephole %{
10996 // peepmatch ( loadI storeI );
10997 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10998 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10999 // %}
11000
11001 //----------SMARTSPILL RULES---------------------------------------------------
11002 // These must follow all instruction definitions as they use the names
11003 // defined in the instructions definitions.
11004 //
11005 // SPARC will probably not have any of these rules due to RISC instruction set.
11006
11007 //----------PIPELINE-----------------------------------------------------------
11008 // Rules which define the behavior of the target architectures pipeline.