1435 // No CMOVF/CMOVD with SSE/SSE2
1436 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1437
1438 // Does the CPU require late expand (see block.cpp for description of late expand)?
1439 const bool Matcher::require_postalloc_expand = false;
1440
1441 // Do we need to mask the count passed to shift instructions or does
1442 // the cpu only look at the lower 5/6 bits anyway?
1443 const bool Matcher::need_masked_shift_count = false;
1444
1445 bool Matcher::narrow_oop_use_complex_address() {
1446 ShouldNotCallThis();
1447 return true;
1448 }
1449
1450 bool Matcher::narrow_klass_use_complex_address() {
1451 ShouldNotCallThis();
1452 return true;
1453 }
1454
1455
1456 // Is it better to copy float constants, or load them directly from memory?
1457 // Intel can load a float constant from a direct address, requiring no
1458 // extra registers. Most RISCs will have to materialize an address into a
1459 // register first, so they would do better to copy the constant from stack.
1460 const bool Matcher::rematerialize_float_constants = true;
1461
1462 // If CPU can load and store mis-aligned doubles directly then no fixup is
1463 // needed. Else we split the double into 2 integer pieces and move it
1464 // piece-by-piece. Only happens when passing doubles into C code as the
1465 // Java calling convention forces doubles to be aligned.
1466 const bool Matcher::misaligned_doubles_ok = true;
1467
1468
1469 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1470 // Get the memory operand from the node
1471 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1472 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1473 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1474 uint opcnt = 1; // First operand
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1435 // No CMOVF/CMOVD with SSE/SSE2
1436 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1437
1438 // Does the CPU require late expand (see block.cpp for description of late expand)?
1439 const bool Matcher::require_postalloc_expand = false;
1440
1441 // Do we need to mask the count passed to shift instructions or does
1442 // the cpu only look at the lower 5/6 bits anyway?
1443 const bool Matcher::need_masked_shift_count = false;
1444
1445 bool Matcher::narrow_oop_use_complex_address() {
1446 ShouldNotCallThis();
1447 return true;
1448 }
1449
1450 bool Matcher::narrow_klass_use_complex_address() {
1451 ShouldNotCallThis();
1452 return true;
1453 }
1454
1455 bool Matcher::const_oop_prefer_decode() {
1456 ShouldNotCallThis();
1457 return true;
1458 }
1459
1460 bool Matcher::const_klass_prefer_decode() {
1461 ShouldNotCallThis();
1462 return true;
1463 }
1464
1465 // Is it better to copy float constants, or load them directly from memory?
1466 // Intel can load a float constant from a direct address, requiring no
1467 // extra registers. Most RISCs will have to materialize an address into a
1468 // register first, so they would do better to copy the constant from stack.
1469 const bool Matcher::rematerialize_float_constants = true;
1470
1471 // If CPU can load and store mis-aligned doubles directly then no fixup is
1472 // needed. Else we split the double into 2 integer pieces and move it
1473 // piece-by-piece. Only happens when passing doubles into C code as the
1474 // Java calling convention forces doubles to be aligned.
1475 const bool Matcher::misaligned_doubles_ok = true;
1476
1477
1478 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1479 // Get the memory operand from the node
1480 uint numopnds = node->num_opnds(); // Virtual call for number of operands
1481 uint skipped = node->oper_input_base(); // Sum of leaves skipped so far
1482 assert( idx >= skipped, "idx too low in pd_implicit_null_fixup" );
1483 uint opcnt = 1; // First operand
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