689 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
690 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
691 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
692
693 // Instruction synchronization
694 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
695 // Memory barriers
696 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
697 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
698
699 // Wait instructions for polling.
700 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1),
701
702 // Trap instructions
703 TDI_OPCODE = (2u << OPCODE_SHIFT),
704 TWI_OPCODE = (3u << OPCODE_SHIFT),
705 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
706 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
707
708 // Atomics.
709 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
710 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
711 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1),
712 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
713 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1),
714 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1)
715
716 };
717
718 // Trap instructions TO bits
719 enum trap_to_bits {
720 // single bits
721 traptoLessThanSigned = 1 << 4, // 0, left end
722 traptoGreaterThanSigned = 1 << 3,
723 traptoEqual = 1 << 2,
724 traptoLessThanUnsigned = 1 << 1,
725 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
726
727 // compound ones
728 traptoUnconditional = (traptoLessThanSigned |
729 traptoGreaterThanSigned |
730 traptoEqual |
731 traptoLessThanUnsigned |
1779 // - fence orders Store|Store, (maps to sync)
1780 // Load|Store,
1781 // Load|Load,
1782 // Store|Load
1783 //
1784 private:
1785 inline void sync(int l);
1786 public:
1787 inline void sync();
1788 inline void lwsync();
1789 inline void ptesync();
1790 inline void eieio();
1791 inline void isync();
1792 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1793
1794 // Wait instructions for polling. Attention: May result in SIGILL.
1795 inline void wait();
1796 inline void waitrsv(); // >=Power7
1797
1798 // atomics
1799 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1800 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1801 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1802 inline bool lxarx_hint_exclusive_access();
1803 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1804 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1805 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1806 inline void stwcx_( Register s, Register a, Register b);
1807 inline void stdcx_( Register s, Register a, Register b);
1808 inline void stqcx_( Register s, Register a, Register b);
1809
1810 // Instructions for adjusting thread priority for simultaneous
1811 // multithreading (SMT) on Power5.
1812 private:
1813 inline void smt_prio_very_low();
1814 inline void smt_prio_medium_high();
1815 inline void smt_prio_high();
1816
1817 public:
1818 inline void smt_prio_low();
1819 inline void smt_prio_medium_low();
1820 inline void smt_prio_medium();
1821 // >= Power7
1822 inline void smt_yield();
1823 inline void smt_mdoio();
1824 inline void smt_mdoom();
1825 // >= Power8
2152 inline void stb( Register d, int si16);
2153 inline void stdx( Register d, Register s2);
2154 inline void std( Register d, int si16);
2155
2156 // PPC 2, section 3.2.1 Instruction Cache Instructions
2157 inline void icbi( Register s2);
2158 // PPC 2, section 3.2.2 Data Cache Instructions
2159 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
2160 inline void dcbz( Register s2);
2161 inline void dcbst( Register s2);
2162 inline void dcbf( Register s2);
2163 // dcache read hint
2164 inline void dcbt( Register s2);
2165 inline void dcbtct( Register s2, int ct);
2166 inline void dcbtds( Register s2, int ds);
2167 // dcache write hint
2168 inline void dcbtst( Register s2);
2169 inline void dcbtstct(Register s2, int ct);
2170
2171 // Atomics: use ra0mem to disallow R0 as base.
2172 inline void lwarx_unchecked(Register d, Register b, int eh1);
2173 inline void ldarx_unchecked(Register d, Register b, int eh1);
2174 inline void lqarx_unchecked(Register d, Register b, int eh1);
2175 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2176 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2177 inline void lqarx( Register d, Register b, bool hint_exclusive_access);
2178 inline void stwcx_(Register s, Register b);
2179 inline void stdcx_(Register s, Register b);
2180 inline void stqcx_(Register s, Register b);
2181 inline void lfs( FloatRegister d, int si16);
2182 inline void lfsx( FloatRegister d, Register b);
2183 inline void lfd( FloatRegister d, int si16);
2184 inline void lfdx( FloatRegister d, Register b);
2185 inline void stfs( FloatRegister s, int si16);
2186 inline void stfsx( FloatRegister s, Register b);
2187 inline void stfd( FloatRegister s, int si16);
2188 inline void stfdx( FloatRegister s, Register b);
2189 inline void lvebx( VectorRegister d, Register s2);
2190 inline void lvehx( VectorRegister d, Register s2);
2191 inline void lvewx( VectorRegister d, Register s2);
2192 inline void lvx( VectorRegister d, Register s2);
2193 inline void lvxl( VectorRegister d, Register s2);
2194 inline void stvebx(VectorRegister d, Register s2);
2195 inline void stvehx(VectorRegister d, Register s2);
2196 inline void stvewx(VectorRegister d, Register s2);
2197 inline void stvx( VectorRegister d, Register s2);
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689 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1),
690 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1),
691 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1),
692
693 // Instruction synchronization
694 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1),
695 // Memory barriers
696 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1),
697 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1),
698
699 // Wait instructions for polling.
700 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1),
701
702 // Trap instructions
703 TDI_OPCODE = (2u << OPCODE_SHIFT),
704 TWI_OPCODE = (3u << OPCODE_SHIFT),
705 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1),
706 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1),
707
708 // Atomics.
709 LBARX_OPCODE = (31u << OPCODE_SHIFT | 52u << 1),
710 LHARX_OPCODE = (31u << OPCODE_SHIFT | 116u << 1),
711 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1),
712 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1),
713 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1),
714 STBCX_OPCODE = (31u << OPCODE_SHIFT | 694u << 1),
715 STHCX_OPCODE = (31u << OPCODE_SHIFT | 726u << 1),
716 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1),
717 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1),
718 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1)
719
720 };
721
722 // Trap instructions TO bits
723 enum trap_to_bits {
724 // single bits
725 traptoLessThanSigned = 1 << 4, // 0, left end
726 traptoGreaterThanSigned = 1 << 3,
727 traptoEqual = 1 << 2,
728 traptoLessThanUnsigned = 1 << 1,
729 traptoGreaterThanUnsigned = 1 << 0, // 4, right end
730
731 // compound ones
732 traptoUnconditional = (traptoLessThanSigned |
733 traptoGreaterThanSigned |
734 traptoEqual |
735 traptoLessThanUnsigned |
1783 // - fence orders Store|Store, (maps to sync)
1784 // Load|Store,
1785 // Load|Load,
1786 // Store|Load
1787 //
1788 private:
1789 inline void sync(int l);
1790 public:
1791 inline void sync();
1792 inline void lwsync();
1793 inline void ptesync();
1794 inline void eieio();
1795 inline void isync();
1796 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8)
1797
1798 // Wait instructions for polling. Attention: May result in SIGILL.
1799 inline void wait();
1800 inline void waitrsv(); // >=Power7
1801
1802 // atomics
1803 inline void lbarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
1804 inline void lharx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
1805 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1806 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0);
1807 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8
1808 inline bool lxarx_hint_exclusive_access();
1809 inline void lbarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1810 inline void lharx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1811 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1812 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1813 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false);
1814 inline void stbcx_( Register s, Register a, Register b);
1815 inline void sthcx_( Register s, Register a, Register b);
1816 inline void stwcx_( Register s, Register a, Register b);
1817 inline void stdcx_( Register s, Register a, Register b);
1818 inline void stqcx_( Register s, Register a, Register b);
1819
1820 // Instructions for adjusting thread priority for simultaneous
1821 // multithreading (SMT) on Power5.
1822 private:
1823 inline void smt_prio_very_low();
1824 inline void smt_prio_medium_high();
1825 inline void smt_prio_high();
1826
1827 public:
1828 inline void smt_prio_low();
1829 inline void smt_prio_medium_low();
1830 inline void smt_prio_medium();
1831 // >= Power7
1832 inline void smt_yield();
1833 inline void smt_mdoio();
1834 inline void smt_mdoom();
1835 // >= Power8
2162 inline void stb( Register d, int si16);
2163 inline void stdx( Register d, Register s2);
2164 inline void std( Register d, int si16);
2165
2166 // PPC 2, section 3.2.1 Instruction Cache Instructions
2167 inline void icbi( Register s2);
2168 // PPC 2, section 3.2.2 Data Cache Instructions
2169 //inlinevoid dcba( Register s2); // Instruction for embedded processor only.
2170 inline void dcbz( Register s2);
2171 inline void dcbst( Register s2);
2172 inline void dcbf( Register s2);
2173 // dcache read hint
2174 inline void dcbt( Register s2);
2175 inline void dcbtct( Register s2, int ct);
2176 inline void dcbtds( Register s2, int ds);
2177 // dcache write hint
2178 inline void dcbtst( Register s2);
2179 inline void dcbtstct(Register s2, int ct);
2180
2181 // Atomics: use ra0mem to disallow R0 as base.
2182 inline void lbarx_unchecked(Register d, Register b, int eh1);
2183 inline void lharx_unchecked(Register d, Register b, int eh1);
2184 inline void lwarx_unchecked(Register d, Register b, int eh1);
2185 inline void ldarx_unchecked(Register d, Register b, int eh1);
2186 inline void lqarx_unchecked(Register d, Register b, int eh1);
2187 inline void lbarx( Register d, Register b, bool hint_exclusive_access);
2188 inline void lharx( Register d, Register b, bool hint_exclusive_access);
2189 inline void lwarx( Register d, Register b, bool hint_exclusive_access);
2190 inline void ldarx( Register d, Register b, bool hint_exclusive_access);
2191 inline void lqarx( Register d, Register b, bool hint_exclusive_access);
2192 inline void stbcx_(Register s, Register b);
2193 inline void sthcx_(Register s, Register b);
2194 inline void stwcx_(Register s, Register b);
2195 inline void stdcx_(Register s, Register b);
2196 inline void stqcx_(Register s, Register b);
2197 inline void lfs( FloatRegister d, int si16);
2198 inline void lfsx( FloatRegister d, Register b);
2199 inline void lfd( FloatRegister d, int si16);
2200 inline void lfdx( FloatRegister d, Register b);
2201 inline void stfs( FloatRegister s, int si16);
2202 inline void stfsx( FloatRegister s, Register b);
2203 inline void stfd( FloatRegister s, int si16);
2204 inline void stfdx( FloatRegister s, Register b);
2205 inline void lvebx( VectorRegister d, Register s2);
2206 inline void lvehx( VectorRegister d, Register s2);
2207 inline void lvewx( VectorRegister d, Register s2);
2208 inline void lvx( VectorRegister d, Register s2);
2209 inline void lvxl( VectorRegister d, Register s2);
2210 inline void stvebx(VectorRegister d, Register s2);
2211 inline void stvehx(VectorRegister d, Register s2);
2212 inline void stvewx(VectorRegister d, Register s2);
2213 inline void stvx( VectorRegister d, Register s2);
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