src/cpu/ppc/vm/assembler_ppc.hpp

rev 11928 : 8164920: ppc: enhancement of CRC32 intrinsic
Reviewed-by: mdoerr
Contributed-by: Hiroshi H Horii <horii@jp.ibm.com>

@@ -504,10 +504,12 @@
     LVSR_OPCODE    = (31u << OPCODE_SHIFT |   38u << 1),
 
     // Vector-Scalar (VSX) instruction support.
     LXVD2X_OPCODE  = (31u << OPCODE_SHIFT |  844u << 1),
     STXVD2X_OPCODE = (31u << OPCODE_SHIFT |  972u << 1),
+    MTVSRD_OPCODE  = (31u << OPCODE_SHIFT |  179u << 1),
+    MFVSRD_OPCODE  = (31u << OPCODE_SHIFT |   51u << 1),
 
     // Vector Permute and Formatting
     VPKPX_OPCODE   = (4u  << OPCODE_SHIFT |  782u     ),
     VPKSHSS_OPCODE = (4u  << OPCODE_SHIFT |  398u     ),
     VPKSWSS_OPCODE = (4u  << OPCODE_SHIFT |  462u     ),

@@ -2097,10 +2099,12 @@
   inline void mfvscr(   VectorRegister d);
 
   // Vector-Scalar (VSX) instructions.
   inline void lxvd2x(   VectorSRegister d, Register a, Register b);
   inline void stxvd2x(  VectorSRegister d, Register a, Register b);
+  inline void mtvrd(    VectorRegister  d, Register a);
+  inline void mfvrd(    Register        a, VectorRegister d);
 
   // AES (introduced with Power 8)
   inline void vcipher(     VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
   inline void vncipher(    VectorRegister d, VectorRegister a, VectorRegister b);