1 /*
2 * Copyright (c) 2000, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "c1/c1_Compilation.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "ci/ciArrayKlass.hpp"
33 #include "ci/ciInstance.hpp"
34 #include "gc/shared/collectedHeap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/cardTableModRefBS.hpp"
37 #include "nativeInst_ppc.hpp"
38 #include "oops/objArrayKlass.hpp"
39 #include "runtime/sharedRuntime.hpp"
40
41 #define __ _masm->
42
43
44 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
45
46
47 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
48 Unimplemented(); return false; // Currently not used on this platform.
49 }
50
51
52 LIR_Opr LIR_Assembler::receiverOpr() {
53 return FrameMap::R3_oop_opr;
54 }
55
56
57 LIR_Opr LIR_Assembler::osrBufferPointer() {
58 return FrameMap::R3_opr;
59 }
60
61
62 // This specifies the stack pointer decrement needed to build the frame.
63 int LIR_Assembler::initial_frame_size_in_bytes() const {
64 return in_bytes(frame_map()->framesize_in_bytes());
65 }
66
67
68 // Inline cache check: the inline cached class is in inline_cache_reg;
69 // we fetch the class of the receiver and compare it with the cached class.
70 // If they do not match we jump to slow case.
71 int LIR_Assembler::check_icache() {
72 int offset = __ offset();
73 __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
74 return offset;
75 }
76
77
78 void LIR_Assembler::osr_entry() {
79 // On-stack-replacement entry sequence:
80 //
81 // 1. Create a new compiled activation.
82 // 2. Initialize local variables in the compiled activation. The expression
83 // stack must be empty at the osr_bci; it is not initialized.
84 // 3. Jump to the continuation address in compiled code to resume execution.
85
86 // OSR entry point
87 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
88 BlockBegin* osr_entry = compilation()->hir()->osr_entry();
89 ValueStack* entry_state = osr_entry->end()->state();
90 int number_of_locks = entry_state->locks_size();
91
92 // Create a frame for the compiled activation.
93 __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
94
95 // OSR buffer is
96 //
97 // locals[nlocals-1..0]
98 // monitors[number_of_locks-1..0]
99 //
100 // Locals is a direct copy of the interpreter frame so in the osr buffer
101 // the first slot in the local array is the last local from the interpreter
102 // and the last slot is local[0] (receiver) from the interpreter.
103 //
104 // Similarly with locks. The first lock slot in the osr buffer is the nth lock
105 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
106 // in the interpreter frame (the method lock if a sync method).
107
108 // Initialize monitors in the compiled activation.
109 // R3: pointer to osr buffer
110 //
111 // All other registers are dead at this point and the locals will be
112 // copied into place by code emitted in the IR.
113
114 Register OSR_buf = osrBufferPointer()->as_register();
115 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
116 int monitor_offset = BytesPerWord * method()->max_locals() +
117 (2 * BytesPerWord) * (number_of_locks - 1);
118 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
119 // the OSR buffer using 2 word entries: first the lock and then
120 // the oop.
121 for (int i = 0; i < number_of_locks; i++) {
122 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
123 #ifdef ASSERT
124 // Verify the interpreter's monitor has a non-null object.
125 {
126 Label L;
127 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
128 __ cmpdi(CCR0, R0, 0);
129 __ bne(CCR0, L);
130 __ stop("locked object is NULL");
131 __ bind(L);
132 }
133 #endif // ASSERT
134 // Copy the lock field into the compiled activation.
135 Address ml = frame_map()->address_for_monitor_lock(i),
136 mo = frame_map()->address_for_monitor_object(i);
137 assert(ml.index() == noreg && mo.index() == noreg, "sanity");
138 __ ld(R0, slot_offset + 0, OSR_buf);
139 __ std(R0, ml.disp(), ml.base());
140 __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
141 __ std(R0, mo.disp(), mo.base());
142 }
143 }
144 }
145
146
147 int LIR_Assembler::emit_exception_handler() {
148 // If the last instruction is a call (typically to do a throw which
149 // is coming at the end after block reordering) the return address
150 // must still point into the code area in order to avoid assertion
151 // failures when searching for the corresponding bci => add a nop
152 // (was bug 5/14/1999 - gri).
153 __ nop();
154
155 // Generate code for the exception handler.
156 address handler_base = __ start_a_stub(exception_handler_size());
157
158 if (handler_base == NULL) {
159 // Not enough space left for the handler.
160 bailout("exception handler overflow");
161 return -1;
162 }
163
164 int offset = code_offset();
165 address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
166 //__ load_const_optimized(R0, entry_point);
167 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
168 __ mtctr(R0);
169 __ bctr();
170
171 guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
172 __ end_a_stub();
173
174 return offset;
175 }
176
177
178 // Emit the code to remove the frame from the stack in the exception
179 // unwind path.
180 int LIR_Assembler::emit_unwind_handler() {
181 _masm->block_comment("Unwind handler");
182
183 int offset = code_offset();
184 bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
185 const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
186
187 // Fetch the exception from TLS and clear out exception related thread state.
188 __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
189 __ li(R0, 0);
190 __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
191 __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
192
193 __ bind(_unwind_handler_entry);
194 __ verify_not_null_oop(Rexception);
195 if (preserve_exception) { __ mr(Rexception_save, Rexception); }
196
197 // Perform needed unlocking
198 MonitorExitStub* stub = NULL;
199 if (method()->is_synchronized()) {
200 monitor_address(0, FrameMap::R4_opr);
201 stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
202 __ unlock_object(R5, R6, R4, *stub->entry());
203 __ bind(*stub->continuation());
204 }
205
206 if (compilation()->env()->dtrace_method_probes()) {
207 Unimplemented();
208 }
209
210 // Dispatch to the unwind logic.
211 address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
212 //__ load_const_optimized(R0, unwind_stub);
213 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
214 if (preserve_exception) { __ mr(Rexception, Rexception_save); }
215 __ mtctr(R0);
216 __ bctr();
217
218 // Emit the slow path assembly.
219 if (stub != NULL) {
220 stub->emit_code(this);
221 }
222
223 return offset;
224 }
225
226
227 int LIR_Assembler::emit_deopt_handler() {
228 // If the last instruction is a call (typically to do a throw which
229 // is coming at the end after block reordering) the return address
230 // must still point into the code area in order to avoid assertion
231 // failures when searching for the corresponding bci => add a nop
232 // (was bug 5/14/1999 - gri).
233 __ nop();
234
235 // Generate code for deopt handler.
236 address handler_base = __ start_a_stub(deopt_handler_size());
237
238 if (handler_base == NULL) {
239 // Not enough space left for the handler.
240 bailout("deopt handler overflow");
241 return -1;
242 }
243
244 int offset = code_offset();
245 __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
246
247 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
248 __ end_a_stub();
249
250 return offset;
251 }
252
253
254 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
255 if (o == NULL) {
256 __ li(reg, 0);
257 } else {
258 AddressLiteral addrlit = __ constant_oop_address(o);
259 __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
260 }
261 }
262
263
264 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
265 // Allocate a new index in table to hold the object once it's been patched.
266 int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
267 PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
268
269 AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
270 __ load_const(reg, addrlit, R0);
271
272 patching_epilog(patch, lir_patch_normal, reg, info);
273 }
274
275
276 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
277 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
278 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
279 }
280
281
282 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
283 // Allocate a new index in table to hold the klass once it's been patched.
284 int index = __ oop_recorder()->allocate_metadata_index(NULL);
285 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
286
287 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
288 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
289 __ load_const(reg, addrlit, R0);
290
291 patching_epilog(patch, lir_patch_normal, reg, info);
292 }
293
294
295 void LIR_Assembler::emit_op3(LIR_Op3* op) {
296 const bool is_int = op->result_opr()->is_single_cpu();
297 Register Rdividend = is_int ? op->in_opr1()->as_register() : op->in_opr1()->as_register_lo();
298 Register Rdivisor = noreg;
299 Register Rscratch = op->in_opr3()->as_register();
300 Register Rresult = is_int ? op->result_opr()->as_register() : op->result_opr()->as_register_lo();
301 long divisor = -1;
302
303 if (op->in_opr2()->is_register()) {
304 Rdivisor = is_int ? op->in_opr2()->as_register() : op->in_opr2()->as_register_lo();
305 } else {
306 divisor = is_int ? op->in_opr2()->as_constant_ptr()->as_jint()
307 : op->in_opr2()->as_constant_ptr()->as_jlong();
308 }
309
310 assert(Rdividend != Rscratch, "");
311 assert(Rdivisor != Rscratch, "");
312 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
313
314 if (Rdivisor == noreg) {
315 if (divisor == 1) { // stupid, but can happen
316 if (op->code() == lir_idiv) {
317 __ mr_if_needed(Rresult, Rdividend);
318 } else {
319 __ li(Rresult, 0);
320 }
321
322 } else if (is_power_of_2(divisor)) {
323 // Convert division by a power of two into some shifts and logical operations.
324 int log2 = log2_intptr(divisor);
325
326 // Round towards 0.
327 if (divisor == 2) {
328 if (is_int) {
329 __ srwi(Rscratch, Rdividend, 31);
330 } else {
331 __ srdi(Rscratch, Rdividend, 63);
332 }
333 } else {
334 if (is_int) {
335 __ srawi(Rscratch, Rdividend, 31);
336 } else {
337 __ sradi(Rscratch, Rdividend, 63);
338 }
339 __ clrldi(Rscratch, Rscratch, 64-log2);
340 }
341 __ add(Rscratch, Rdividend, Rscratch);
342
343 if (op->code() == lir_idiv) {
344 if (is_int) {
345 __ srawi(Rresult, Rscratch, log2);
346 } else {
347 __ sradi(Rresult, Rscratch, log2);
348 }
349 } else { // lir_irem
350 __ clrrdi(Rscratch, Rscratch, log2);
351 __ sub(Rresult, Rdividend, Rscratch);
352 }
353
354 } else if (divisor == -1) {
355 if (op->code() == lir_idiv) {
356 __ neg(Rresult, Rdividend);
357 } else {
358 __ li(Rresult, 0);
359 }
360
361 } else {
362 __ load_const_optimized(Rscratch, divisor);
363 if (op->code() == lir_idiv) {
364 if (is_int) {
365 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
366 } else {
367 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
368 }
369 } else {
370 assert(Rscratch != R0, "need both");
371 if (is_int) {
372 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
373 __ mullw(Rscratch, R0, Rscratch);
374 } else {
375 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
376 __ mulld(Rscratch, R0, Rscratch);
377 }
378 __ sub(Rresult, Rdividend, Rscratch);
379 }
380
381 }
382 return;
383 }
384
385 Label regular, done;
386 if (is_int) {
387 __ cmpwi(CCR0, Rdivisor, -1);
388 } else {
389 __ cmpdi(CCR0, Rdivisor, -1);
390 }
391 __ bne(CCR0, regular);
392 if (op->code() == lir_idiv) {
393 __ neg(Rresult, Rdividend);
394 __ b(done);
395 __ bind(regular);
396 if (is_int) {
397 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
398 } else {
399 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
400 }
401 } else { // lir_irem
402 __ li(Rresult, 0);
403 __ b(done);
404 __ bind(regular);
405 if (is_int) {
406 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
407 __ mullw(Rscratch, Rscratch, Rdivisor);
408 } else {
409 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
410 __ mulld(Rscratch, Rscratch, Rdivisor);
411 }
412 __ sub(Rresult, Rdividend, Rscratch);
413 }
414 __ bind(done);
415 }
416
417
418 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
419 #ifdef ASSERT
420 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
421 if (op->block() != NULL) _branch_target_blocks.append(op->block());
422 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
423 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
424 #endif
425
426 Label *L = op->label();
427 if (op->cond() == lir_cond_always) {
428 __ b(*L);
429 } else {
430 Label done;
431 bool is_unordered = false;
432 if (op->code() == lir_cond_float_branch) {
433 assert(op->ublock() != NULL, "must have unordered successor");
434 is_unordered = true;
435 } else {
436 assert(op->code() == lir_branch, "just checking");
437 }
438
439 bool positive = false;
440 Assembler::Condition cond = Assembler::equal;
441 switch (op->cond()) {
442 case lir_cond_equal: positive = true ; cond = Assembler::equal ; is_unordered = false; break;
443 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; is_unordered = false; break;
444 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
445 case lir_cond_belowEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
446 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
447 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
448 case lir_cond_aboveEqual: assert(op->code() != lir_cond_float_branch, ""); // fallthru
449 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
450 default: ShouldNotReachHere();
451 }
452 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
453 int bi = Assembler::bi0(BOOL_RESULT, cond);
454 if (is_unordered) {
455 if (positive) {
456 if (op->ublock() == op->block()) {
457 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
458 }
459 } else {
460 if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
461 }
462 }
463 __ bc_far_optimized(bo, bi, *L);
464 __ bind(done);
465 }
466 }
467
468
469 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
470 Bytecodes::Code code = op->bytecode();
471 LIR_Opr src = op->in_opr(),
472 dst = op->result_opr();
473
474 switch(code) {
475 case Bytecodes::_i2l: {
476 __ extsw(dst->as_register_lo(), src->as_register());
477 break;
478 }
479 case Bytecodes::_l2i: {
480 __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
481 break;
482 }
483 case Bytecodes::_i2b: {
484 __ extsb(dst->as_register(), src->as_register());
485 break;
486 }
487 case Bytecodes::_i2c: {
488 __ clrldi(dst->as_register(), src->as_register(), 64-16);
489 break;
490 }
491 case Bytecodes::_i2s: {
492 __ extsh(dst->as_register(), src->as_register());
493 break;
494 }
495 case Bytecodes::_i2d:
496 case Bytecodes::_l2d: {
497 __ fcfid(dst->as_double_reg(), src->as_double_reg()); // via mem
498 break;
499 }
500 case Bytecodes::_i2f: {
501 FloatRegister rdst = dst->as_float_reg();
502 FloatRegister rsrc = src->as_double_reg(); // via mem
503 if (VM_Version::has_fcfids()) {
504 __ fcfids(rdst, rsrc);
505 } else {
506 __ fcfid(rdst, rsrc);
507 __ frsp(rdst, rdst);
508 }
509 break;
510 }
511 case Bytecodes::_l2f: { // >= Power7
512 assert(VM_Version::has_fcfids(), "fcfid+frsp needs fixup code to avoid rounding incompatibility");
513 __ fcfids(dst->as_float_reg(), src->as_double_reg()); // via mem
514 break;
515 }
516 case Bytecodes::_f2d: {
517 __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
518 break;
519 }
520 case Bytecodes::_d2f: {
521 __ frsp(dst->as_float_reg(), src->as_double_reg());
522 break;
523 }
524 case Bytecodes::_d2i:
525 case Bytecodes::_f2i: {
526 FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
527 Address addr = frame_map()->address_for_slot(dst->double_stack_ix());
528 Label L;
529 // Result must be 0 if value is NaN; test by comparing value to itself.
530 __ fcmpu(CCR0, rsrc, rsrc);
531 __ li(R0, 0); // 0 in case of NAN
532 __ std(R0, addr.disp(), addr.base());
533 __ bso(CCR0, L);
534 __ fctiwz(rsrc, rsrc); // USE_KILL
535 __ stfd(rsrc, addr.disp(), addr.base());
536 __ bind(L);
537 break;
538 }
539 case Bytecodes::_d2l:
540 case Bytecodes::_f2l: {
541 FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
542 Address addr = frame_map()->address_for_slot(dst->double_stack_ix());
543 Label L;
544 // Result must be 0 if value is NaN; test by comparing value to itself.
545 __ fcmpu(CCR0, rsrc, rsrc);
546 __ li(R0, 0); // 0 in case of NAN
547 __ std(R0, addr.disp(), addr.base());
548 __ bso(CCR0, L);
549 __ fctidz(rsrc, rsrc); // USE_KILL
550 __ stfd(rsrc, addr.disp(), addr.base());
551 __ bind(L);
552 break;
553 }
554
555 default: ShouldNotReachHere();
556 }
557 }
558
559
560 void LIR_Assembler::align_call(LIR_Code) {
561 // do nothing since all instructions are word aligned on ppc
562 }
563
564
565 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
566 int start_offset = __ offset();
567 // Put the entry point as a constant into the constant pool.
568 const address entry_point_toc_addr = __ address_constant(target, RelocationHolder::none);
569 if (entry_point_toc_addr == NULL) {
570 bailout("const section overflow");
571 return false;
572 }
573 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
574
575 // Emit the trampoline stub which will be related to the branch-and-link below.
576 address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
577 if (!stub) {
578 bailout("no space for trampoline stub");
579 return false;
580 }
581 return true;
582 }
583
584
585 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
586 assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
587
588 bool success = emit_trampoline_stub_for_call(op->addr());
589 if (!success) { return; }
590
591 __ relocate(rtype);
592 // Note: At this point we do not have the address of the trampoline
593 // stub, and the entry point might be too far away for bl, so __ pc()
594 // serves as dummy and the bl will be patched later.
595 __ code()->set_insts_mark();
596 __ bl(__ pc());
597 add_call_info(code_offset(), op->info());
598 }
599
600
601 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
602 __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
603
604 // Virtual call relocation will point to ic load.
605 address virtual_call_meta_addr = __ pc();
606 // Load a clear inline cache.
607 AddressLiteral empty_ic((address) Universe::non_oop_word());
608 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
609 if (!success) {
610 bailout("const section overflow");
611 return;
612 }
613 // Call to fixup routine. Fixup routine uses ScopeDesc info
614 // to determine who we intended to call.
615 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
616
617 success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
618 if (!success) { return; }
619
620 // Note: At this point we do not have the address of the trampoline
621 // stub, and the entry point might be too far away for bl, so __ pc()
622 // serves as dummy and the bl will be patched later.
623 __ bl(__ pc());
624 add_call_info(code_offset(), op->info());
625 }
626
627
628 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
629 ShouldNotReachHere(); // ic_call is used instead.
630 }
631
632
633 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
634 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
635 __ null_check(addr, stub->entry());
636 append_code_stub(stub);
637 }
638
639
640 // Attention: caller must encode oop if needed
641 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
642 int store_offset;
643 if (!Assembler::is_simm16(offset)) {
644 // For offsets larger than a simm16 we setup the offset.
645 assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
646 __ load_const_optimized(R0, offset);
647 store_offset = store(from_reg, base, R0, type, wide);
648 } else {
649 store_offset = code_offset();
650 switch (type) {
651 case T_BOOLEAN: // fall through
652 case T_BYTE : __ stb(from_reg->as_register(), offset, base); break;
653 case T_CHAR :
654 case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
655 case T_INT : __ stw(from_reg->as_register(), offset, base); break;
656 case T_LONG : __ std(from_reg->as_register_lo(), offset, base); break;
657 case T_ADDRESS:
658 case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
659 case T_ARRAY : // fall through
660 case T_OBJECT:
661 {
662 if (UseCompressedOops && !wide) {
663 // Encoding done in caller
664 __ stw(from_reg->as_register(), offset, base);
665 } else {
666 __ std(from_reg->as_register(), offset, base);
667 }
668 __ verify_oop(from_reg->as_register());
669 break;
670 }
671 case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
672 case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
673 default : ShouldNotReachHere();
674 }
675 }
676 return store_offset;
677 }
678
679
680 // Attention: caller must encode oop if needed
681 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
682 int store_offset = code_offset();
683 switch (type) {
684 case T_BOOLEAN: // fall through
685 case T_BYTE : __ stbx(from_reg->as_register(), base, disp); break;
686 case T_CHAR :
687 case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
688 case T_INT : __ stwx(from_reg->as_register(), base, disp); break;
689 case T_LONG :
690 #ifdef _LP64
691 __ stdx(from_reg->as_register_lo(), base, disp);
692 #else
693 Unimplemented();
694 #endif
695 break;
696 case T_ADDRESS:
697 __ stdx(from_reg->as_register(), base, disp);
698 break;
699 case T_ARRAY : // fall through
700 case T_OBJECT:
701 {
702 if (UseCompressedOops && !wide) {
703 // Encoding done in caller.
704 __ stwx(from_reg->as_register(), base, disp);
705 } else {
706 __ stdx(from_reg->as_register(), base, disp);
707 }
708 __ verify_oop(from_reg->as_register()); // kills R0
709 break;
710 }
711 case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
712 case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
713 default : ShouldNotReachHere();
714 }
715 return store_offset;
716 }
717
718
719 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
720 int load_offset;
721 if (!Assembler::is_simm16(offset)) {
722 // For offsets larger than a simm16 we setup the offset.
723 __ load_const_optimized(R0, offset);
724 load_offset = load(base, R0, to_reg, type, wide);
725 } else {
726 load_offset = code_offset();
727 switch(type) {
728 case T_BOOLEAN: // fall through
729 case T_BYTE : __ lbz(to_reg->as_register(), offset, base);
730 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
731 case T_CHAR : __ lhz(to_reg->as_register(), offset, base); break;
732 case T_SHORT : __ lha(to_reg->as_register(), offset, base); break;
733 case T_INT : __ lwa(to_reg->as_register(), offset, base); break;
734 case T_LONG : __ ld(to_reg->as_register_lo(), offset, base); break;
735 case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
736 case T_ADDRESS:
737 if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
738 __ lwz(to_reg->as_register(), offset, base);
739 __ decode_klass_not_null(to_reg->as_register());
740 } else {
741 __ ld(to_reg->as_register(), offset, base);
742 }
743 break;
744 case T_ARRAY : // fall through
745 case T_OBJECT:
746 {
747 if (UseCompressedOops && !wide) {
748 __ lwz(to_reg->as_register(), offset, base);
749 __ decode_heap_oop(to_reg->as_register());
750 } else {
751 __ ld(to_reg->as_register(), offset, base);
752 }
753 __ verify_oop(to_reg->as_register());
754 break;
755 }
756 case T_FLOAT: __ lfs(to_reg->as_float_reg(), offset, base); break;
757 case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
758 default : ShouldNotReachHere();
759 }
760 }
761 return load_offset;
762 }
763
764
765 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
766 int load_offset = code_offset();
767 switch(type) {
768 case T_BOOLEAN: // fall through
769 case T_BYTE : __ lbzx(to_reg->as_register(), base, disp);
770 __ extsb(to_reg->as_register(), to_reg->as_register()); break;
771 case T_CHAR : __ lhzx(to_reg->as_register(), base, disp); break;
772 case T_SHORT : __ lhax(to_reg->as_register(), base, disp); break;
773 case T_INT : __ lwax(to_reg->as_register(), base, disp); break;
774 case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
775 case T_ARRAY : // fall through
776 case T_OBJECT:
777 {
778 if (UseCompressedOops && !wide) {
779 __ lwzx(to_reg->as_register(), base, disp);
780 __ decode_heap_oop(to_reg->as_register());
781 } else {
782 __ ldx(to_reg->as_register(), base, disp);
783 }
784 __ verify_oop(to_reg->as_register());
785 break;
786 }
787 case T_FLOAT: __ lfsx(to_reg->as_float_reg() , base, disp); break;
788 case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
789 case T_LONG :
790 #ifdef _LP64
791 __ ldx(to_reg->as_register_lo(), base, disp);
792 #else
793 Unimplemented();
794 #endif
795 break;
796 default : ShouldNotReachHere();
797 }
798 return load_offset;
799 }
800
801
802 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
803 LIR_Const* c = src->as_constant_ptr();
804 Register src_reg = R0;
805 switch (c->type()) {
806 case T_INT:
807 case T_FLOAT: {
808 int value = c->as_jint_bits();
809 __ load_const_optimized(src_reg, value);
810 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
811 __ stw(src_reg, addr.disp(), addr.base());
812 break;
813 }
814 case T_ADDRESS: {
815 int value = c->as_jint_bits();
816 __ load_const_optimized(src_reg, value);
817 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
818 __ std(src_reg, addr.disp(), addr.base());
819 break;
820 }
821 case T_OBJECT: {
822 jobject2reg(c->as_jobject(), src_reg);
823 Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
824 __ std(src_reg, addr.disp(), addr.base());
825 break;
826 }
827 case T_LONG:
828 case T_DOUBLE: {
829 int value = c->as_jlong_bits();
830 __ load_const_optimized(src_reg, value);
831 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
832 __ std(src_reg, addr.disp(), addr.base());
833 break;
834 }
835 default:
836 Unimplemented();
837 }
838 }
839
840
841 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
842 LIR_Const* c = src->as_constant_ptr();
843 LIR_Address* addr = dest->as_address_ptr();
844 Register base = addr->base()->as_pointer_register();
845 LIR_Opr tmp = LIR_OprFact::illegalOpr;
846 int offset = -1;
847 // Null check for large offsets in LIRGenerator::do_StoreField.
848 bool needs_explicit_null_check = !ImplicitNullChecks;
849
850 if (info != NULL && needs_explicit_null_check) {
851 explicit_null_check(base, info);
852 }
853
854 switch (c->type()) {
855 case T_FLOAT: type = T_INT;
856 case T_INT:
857 case T_ADDRESS: {
858 tmp = FrameMap::R0_opr;
859 __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
860 break;
861 }
862 case T_DOUBLE: type = T_LONG;
863 case T_LONG: {
864 tmp = FrameMap::R0_long_opr;
865 __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
866 break;
867 }
868 case T_OBJECT: {
869 tmp = FrameMap::R0_opr;
870 if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
871 AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
872 __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
873 __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
874 __ ori(R0, R0, oop_addr.value() & 0xffff);
875 } else {
876 jobject2reg(c->as_jobject(), R0);
877 }
878 break;
879 }
880 default:
881 Unimplemented();
882 }
883
884 // Handle either reg+reg or reg+disp address.
885 if (addr->index()->is_valid()) {
886 assert(addr->disp() == 0, "must be zero");
887 offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
888 } else {
889 assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
890 offset = store(tmp, base, addr->disp(), type, wide, false);
891 }
892
893 if (info != NULL) {
894 assert(offset != -1, "offset should've been set");
895 if (!needs_explicit_null_check) {
896 add_debug_info_for_null_check(offset, info);
897 }
898 }
899 }
900
901
902 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
903 LIR_Const* c = src->as_constant_ptr();
904 LIR_Opr to_reg = dest;
905
906 switch (c->type()) {
907 case T_INT: {
908 assert(patch_code == lir_patch_none, "no patching handled here");
909 __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
910 break;
911 }
912 case T_ADDRESS: {
913 assert(patch_code == lir_patch_none, "no patching handled here");
914 __ load_const_optimized(dest->as_register(), c->as_jint(), R0); // Yes, as_jint ...
915 break;
916 }
917 case T_LONG: {
918 assert(patch_code == lir_patch_none, "no patching handled here");
919 __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
920 break;
921 }
922
923 case T_OBJECT: {
924 if (patch_code == lir_patch_none) {
925 jobject2reg(c->as_jobject(), to_reg->as_register());
926 } else {
927 jobject2reg_with_patching(to_reg->as_register(), info);
928 }
929 break;
930 }
931
932 case T_METADATA:
933 {
934 if (patch_code == lir_patch_none) {
935 metadata2reg(c->as_metadata(), to_reg->as_register());
936 } else {
937 klass2reg_with_patching(to_reg->as_register(), info);
938 }
939 }
940 break;
941
942 case T_FLOAT:
943 {
944 if (to_reg->is_single_fpu()) {
945 address const_addr = __ float_constant(c->as_jfloat());
946 if (const_addr == NULL) {
947 bailout("const section overflow");
948 break;
949 }
950 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
951 __ relocate(rspec);
952 __ load_const(R0, const_addr);
953 __ lfsx(to_reg->as_float_reg(), R0);
954 } else {
955 assert(to_reg->is_single_cpu(), "Must be a cpu register.");
956 __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
957 }
958 }
959 break;
960
961 case T_DOUBLE:
962 {
963 if (to_reg->is_double_fpu()) {
964 address const_addr = __ double_constant(c->as_jdouble());
965 if (const_addr == NULL) {
966 bailout("const section overflow");
967 break;
968 }
969 RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
970 __ relocate(rspec);
971 __ load_const(R0, const_addr);
972 __ lfdx(to_reg->as_double_reg(), R0);
973 } else {
974 assert(to_reg->is_double_cpu(), "Must be a long register.");
975 __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
976 }
977 }
978 break;
979
980 default:
981 ShouldNotReachHere();
982 }
983 }
984
985
986 Address LIR_Assembler::as_Address(LIR_Address* addr) {
987 Unimplemented(); return Address();
988 }
989
990
991 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
992 if (addr->index()->is_illegal()) {
993 return (RegisterOrConstant)(addr->disp());
994 } else {
995 return (RegisterOrConstant)(addr->index()->as_pointer_register());
996 }
997 }
998
999
1000 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1001 const Register tmp = R0;
1002 switch (type) {
1003 case T_INT:
1004 case T_FLOAT: {
1005 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1006 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1007 __ lwz(tmp, from.disp(), from.base());
1008 __ stw(tmp, to.disp(), to.base());
1009 break;
1010 }
1011 case T_ADDRESS:
1012 case T_OBJECT: {
1013 Address from = frame_map()->address_for_slot(src->single_stack_ix());
1014 Address to = frame_map()->address_for_slot(dest->single_stack_ix());
1015 __ ld(tmp, from.disp(), from.base());
1016 __ std(tmp, to.disp(), to.base());
1017 break;
1018 }
1019 case T_LONG:
1020 case T_DOUBLE: {
1021 Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1022 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix());
1023 __ ld(tmp, from.disp(), from.base());
1024 __ std(tmp, to.disp(), to.base());
1025 break;
1026 }
1027
1028 default:
1029 ShouldNotReachHere();
1030 }
1031 }
1032
1033
1034 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1035 Unimplemented(); return Address();
1036 }
1037
1038
1039 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1040 Unimplemented(); return Address();
1041 }
1042
1043
1044 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1045 LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1046
1047 assert(type != T_METADATA, "load of metadata ptr not supported");
1048 LIR_Address* addr = src_opr->as_address_ptr();
1049 LIR_Opr to_reg = dest;
1050
1051 Register src = addr->base()->as_pointer_register();
1052 Register disp_reg = noreg;
1053 int disp_value = addr->disp();
1054 bool needs_patching = (patch_code != lir_patch_none);
1055 // null check for large offsets in LIRGenerator::do_LoadField
1056 bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1057
1058 if (info != NULL && needs_explicit_null_check) {
1059 explicit_null_check(src, info);
1060 }
1061
1062 if (addr->base()->type() == T_OBJECT) {
1063 __ verify_oop(src);
1064 }
1065
1066 PatchingStub* patch = NULL;
1067 if (needs_patching) {
1068 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1069 assert(!to_reg->is_double_cpu() ||
1070 patch_code == lir_patch_none ||
1071 patch_code == lir_patch_normal, "patching doesn't match register");
1072 }
1073
1074 if (addr->index()->is_illegal()) {
1075 if (!Assembler::is_simm16(disp_value)) {
1076 if (needs_patching) {
1077 __ load_const32(R0, 0); // patchable int
1078 } else {
1079 __ load_const_optimized(R0, disp_value);
1080 }
1081 disp_reg = R0;
1082 }
1083 } else {
1084 disp_reg = addr->index()->as_pointer_register();
1085 assert(disp_value == 0, "can't handle 3 operand addresses");
1086 }
1087
1088 // Remember the offset of the load. The patching_epilog must be done
1089 // before the call to add_debug_info, otherwise the PcDescs don't get
1090 // entered in increasing order.
1091 int offset;
1092
1093 if (disp_reg == noreg) {
1094 assert(Assembler::is_simm16(disp_value), "should have set this up");
1095 offset = load(src, disp_value, to_reg, type, wide, unaligned);
1096 } else {
1097 assert(!unaligned, "unexpected");
1098 offset = load(src, disp_reg, to_reg, type, wide);
1099 }
1100
1101 if (patch != NULL) {
1102 patching_epilog(patch, patch_code, src, info);
1103 }
1104 if (info != NULL && !needs_explicit_null_check) {
1105 add_debug_info_for_null_check(offset, info);
1106 }
1107 }
1108
1109
1110 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1111 Address addr;
1112 if (src->is_single_word()) {
1113 addr = frame_map()->address_for_slot(src->single_stack_ix());
1114 } else if (src->is_double_word()) {
1115 addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1116 }
1117
1118 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1119 load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1120 }
1121
1122
1123 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1124 Address addr;
1125 if (dest->is_single_word()) {
1126 addr = frame_map()->address_for_slot(dest->single_stack_ix());
1127 } else if (dest->is_double_word()) {
1128 addr = frame_map()->address_for_slot(dest->double_stack_ix());
1129 }
1130 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1131 store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1132 }
1133
1134
1135 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1136 if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1137 if (from_reg->is_double_fpu()) {
1138 // double to double moves
1139 assert(to_reg->is_double_fpu(), "should match");
1140 __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1141 } else {
1142 // float to float moves
1143 assert(to_reg->is_single_fpu(), "should match");
1144 __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1145 }
1146 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1147 if (from_reg->is_double_cpu()) {
1148 __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1149 } else if (to_reg->is_double_cpu()) {
1150 // int to int moves
1151 __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1152 } else {
1153 // int to int moves
1154 __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1155 }
1156 } else {
1157 ShouldNotReachHere();
1158 }
1159 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1160 __ verify_oop(to_reg->as_register());
1161 }
1162 }
1163
1164
1165 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1166 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1167 bool wide, bool unaligned) {
1168 assert(type != T_METADATA, "store of metadata ptr not supported");
1169 LIR_Address* addr = dest->as_address_ptr();
1170
1171 Register src = addr->base()->as_pointer_register();
1172 Register disp_reg = noreg;
1173 int disp_value = addr->disp();
1174 bool needs_patching = (patch_code != lir_patch_none);
1175 bool compress_oop = (type == T_ARRAY || type == T_OBJECT) && UseCompressedOops && !wide &&
1176 Universe::narrow_oop_mode() != Universe::UnscaledNarrowOop;
1177 bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1178 bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1179 // Null check for large offsets in LIRGenerator::do_StoreField.
1180 bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1181
1182 if (info != NULL && needs_explicit_null_check) {
1183 explicit_null_check(src, info);
1184 }
1185
1186 if (addr->base()->is_oop_register()) {
1187 __ verify_oop(src);
1188 }
1189
1190 PatchingStub* patch = NULL;
1191 if (needs_patching) {
1192 patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1193 assert(!from_reg->is_double_cpu() ||
1194 patch_code == lir_patch_none ||
1195 patch_code == lir_patch_normal, "patching doesn't match register");
1196 }
1197
1198 if (addr->index()->is_illegal()) {
1199 if (load_disp) {
1200 disp_reg = use_R29 ? R29_TOC : R0;
1201 if (needs_patching) {
1202 __ load_const32(disp_reg, 0); // patchable int
1203 } else {
1204 __ load_const_optimized(disp_reg, disp_value);
1205 }
1206 }
1207 } else {
1208 disp_reg = addr->index()->as_pointer_register();
1209 assert(disp_value == 0, "can't handle 3 operand addresses");
1210 }
1211
1212 // remember the offset of the store. The patching_epilog must be done
1213 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1214 // entered in increasing order.
1215 int offset;
1216
1217 if (compress_oop) {
1218 Register co = __ encode_heap_oop(R0, from_reg->as_register());
1219 from_reg = FrameMap::as_opr(co);
1220 }
1221
1222 if (disp_reg == noreg) {
1223 assert(Assembler::is_simm16(disp_value), "should have set this up");
1224 offset = store(from_reg, src, disp_value, type, wide, unaligned);
1225 } else {
1226 assert(!unaligned, "unexpected");
1227 offset = store(from_reg, src, disp_reg, type, wide);
1228 }
1229
1230 if (use_R29) {
1231 __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1232 }
1233
1234 if (patch != NULL) {
1235 patching_epilog(patch, patch_code, src, info);
1236 }
1237
1238 if (info != NULL && !needs_explicit_null_check) {
1239 add_debug_info_for_null_check(offset, info);
1240 }
1241 }
1242
1243
1244 void LIR_Assembler::return_op(LIR_Opr result) {
1245 const Register return_pc = R31; // Must survive C-call to enable_stack_reserved_zone().
1246 const Register polling_page = R12;
1247
1248 // Pop the stack before the safepoint code.
1249 int frame_size = initial_frame_size_in_bytes();
1250 if (Assembler::is_simm(frame_size, 16)) {
1251 __ addi(R1_SP, R1_SP, frame_size);
1252 } else {
1253 __ pop_frame();
1254 }
1255
1256 if (LoadPollAddressFromThread) {
1257 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1258 Unimplemented();
1259 } else {
1260 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page(), R0); // TODO: PPC port: get_standard_polling_page()
1261 }
1262
1263 // Restore return pc relative to callers' sp.
1264 __ ld(return_pc, _abi(lr), R1_SP);
1265 // Move return pc to LR.
1266 __ mtlr(return_pc);
1267
1268 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1269 __ reserved_stack_check(return_pc);
1270 }
1271
1272 // We need to mark the code position where the load from the safepoint
1273 // polling page was emitted as relocInfo::poll_return_type here.
1274 __ relocate(relocInfo::poll_return_type);
1275 __ load_from_polling_page(polling_page);
1276
1277 // Return.
1278 __ blr();
1279 }
1280
1281
1282 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1283
1284 if (LoadPollAddressFromThread) {
1285 const Register poll_addr = tmp->as_register();
1286 // TODO: PPC port __ ld(poll_addr, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1287 Unimplemented();
1288 __ relocate(relocInfo::poll_type); // XXX
1289 guarantee(info != NULL, "Shouldn't be NULL");
1290 int offset = __ offset();
1291 add_debug_info_for_branch(info);
1292 __ load_from_polling_page(poll_addr);
1293 return offset;
1294 }
1295
1296 __ load_const_optimized(tmp->as_register(), (intptr_t)os::get_polling_page(), R0); // TODO: PPC port: get_standard_polling_page()
1297 if (info != NULL) {
1298 add_debug_info_for_branch(info);
1299 }
1300 int offset = __ offset();
1301 __ relocate(relocInfo::poll_type);
1302 __ load_from_polling_page(tmp->as_register());
1303
1304 return offset;
1305 }
1306
1307
1308 void LIR_Assembler::emit_static_call_stub() {
1309 address call_pc = __ pc();
1310 address stub = __ start_a_stub(static_call_stub_size());
1311 if (stub == NULL) {
1312 bailout("static call stub overflow");
1313 return;
1314 }
1315
1316 // For java_to_interp stubs we use R11_scratch1 as scratch register
1317 // and in call trampoline stubs we use R12_scratch2. This way we
1318 // can distinguish them (see is_NativeCallTrampolineStub_at()).
1319 const Register reg_scratch = R11_scratch1;
1320
1321 // Create a static stub relocation which relates this stub
1322 // with the call instruction at insts_call_instruction_offset in the
1323 // instructions code-section.
1324 int start = __ offset();
1325 __ relocate(static_stub_Relocation::spec(call_pc));
1326
1327 // Now, create the stub's code:
1328 // - load the TOC
1329 // - load the inline cache oop from the constant pool
1330 // - load the call target from the constant pool
1331 // - call
1332 __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1333 AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1334 bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1335
1336 if (ReoptimizeCallSequences) {
1337 __ b64_patchable((address)-1, relocInfo::none);
1338 } else {
1339 AddressLiteral a((address)-1);
1340 success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1341 __ mtctr(reg_scratch);
1342 __ bctr();
1343 }
1344 if (!success) {
1345 bailout("const section overflow");
1346 return;
1347 }
1348
1349 assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1350 __ end_a_stub();
1351 }
1352
1353
1354 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1355 bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1356 if (opr1->is_single_fpu()) {
1357 __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1358 } else if (opr1->is_double_fpu()) {
1359 __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1360 } else if (opr1->is_single_cpu()) {
1361 if (opr2->is_constant()) {
1362 switch (opr2->as_constant_ptr()->type()) {
1363 case T_INT:
1364 {
1365 jint con = opr2->as_constant_ptr()->as_jint();
1366 if (unsigned_comp) {
1367 if (Assembler::is_uimm(con, 16)) {
1368 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1369 } else {
1370 __ load_const_optimized(R0, con);
1371 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1372 }
1373 } else {
1374 if (Assembler::is_simm(con, 16)) {
1375 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1376 } else {
1377 __ load_const_optimized(R0, con);
1378 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1379 }
1380 }
1381 }
1382 break;
1383
1384 case T_OBJECT:
1385 // There are only equal/notequal comparisons on objects.
1386 {
1387 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1388 jobject con = opr2->as_constant_ptr()->as_jobject();
1389 if (con == NULL) {
1390 __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1391 } else {
1392 jobject2reg(con, R0);
1393 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1394 }
1395 }
1396 break;
1397
1398 default:
1399 ShouldNotReachHere();
1400 break;
1401 }
1402 } else {
1403 if (opr2->is_address()) {
1404 DEBUG_ONLY( Unimplemented(); ) // Seems to be unused at the moment.
1405 LIR_Address *addr = opr2->as_address_ptr();
1406 BasicType type = addr->type();
1407 if (type == T_OBJECT) { __ ld(R0, index_or_disp(addr), addr->base()->as_register()); }
1408 else { __ lwa(R0, index_or_disp(addr), addr->base()->as_register()); }
1409 __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1410 } else {
1411 if (unsigned_comp) {
1412 __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1413 } else {
1414 __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1415 }
1416 }
1417 }
1418 } else if (opr1->is_double_cpu()) {
1419 if (opr2->is_constant()) {
1420 jlong con = opr2->as_constant_ptr()->as_jlong();
1421 if (unsigned_comp) {
1422 if (Assembler::is_uimm(con, 16)) {
1423 __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1424 } else {
1425 __ load_const_optimized(R0, con);
1426 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1427 }
1428 } else {
1429 if (Assembler::is_simm(con, 16)) {
1430 __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1431 } else {
1432 __ load_const_optimized(R0, con);
1433 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1434 }
1435 }
1436 } else if (opr2->is_register()) {
1437 if (unsigned_comp) {
1438 __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1439 } else {
1440 __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1441 }
1442 } else {
1443 ShouldNotReachHere();
1444 }
1445 } else if (opr1->is_address()) {
1446 DEBUG_ONLY( Unimplemented(); ) // Seems to be unused at the moment.
1447 LIR_Address * addr = opr1->as_address_ptr();
1448 BasicType type = addr->type();
1449 assert (opr2->is_constant(), "Checking");
1450 if (type == T_OBJECT) { __ ld(R0, index_or_disp(addr), addr->base()->as_register()); }
1451 else { __ lwa(R0, index_or_disp(addr), addr->base()->as_register()); }
1452 __ cmpdi(BOOL_RESULT, R0, opr2->as_constant_ptr()->as_jint());
1453 } else {
1454 ShouldNotReachHere();
1455 }
1456 }
1457
1458
1459 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1460 const Register Rdst = dst->as_register();
1461 Label done;
1462 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1463 bool is_unordered_less = (code == lir_ucmp_fd2i);
1464 if (left->is_single_fpu()) {
1465 __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1466 } else if (left->is_double_fpu()) {
1467 __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1468 } else {
1469 ShouldNotReachHere();
1470 }
1471 __ li(Rdst, is_unordered_less ? -1 : 1);
1472 __ bso(CCR0, done);
1473 } else if (code == lir_cmp_l2i) {
1474 __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1475 } else {
1476 ShouldNotReachHere();
1477 }
1478 __ mfcr(R0); // set bit 32..33 as follows: <: 0b10, =: 0b00, >: 0b01
1479 __ srwi(Rdst, R0, 30);
1480 __ srawi(R0, R0, 31);
1481 __ orr(Rdst, R0, Rdst); // set result as follows: <: -1, =: 0, >: 1
1482 __ bind(done);
1483 }
1484
1485
1486 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1487 if (src->is_constant()) {
1488 lasm->const2reg(src, dst, lir_patch_none, NULL);
1489 } else if (src->is_register()) {
1490 lasm->reg2reg(src, dst);
1491 } else if (src->is_stack()) {
1492 lasm->stack2reg(src, dst, dst->type());
1493 } else {
1494 ShouldNotReachHere();
1495 }
1496 }
1497
1498
1499 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1500 if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1501 load_to_reg(this, opr1, result); // Condition doesn't matter.
1502 return;
1503 }
1504
1505 bool positive = false;
1506 Assembler::Condition cond = Assembler::equal;
1507 switch (condition) {
1508 case lir_cond_equal: positive = true ; cond = Assembler::equal ; break;
1509 case lir_cond_notEqual: positive = false; cond = Assembler::equal ; break;
1510 case lir_cond_less: positive = true ; cond = Assembler::less ; break;
1511 case lir_cond_belowEqual:
1512 case lir_cond_lessEqual: positive = false; cond = Assembler::greater; break;
1513 case lir_cond_greater: positive = true ; cond = Assembler::greater; break;
1514 case lir_cond_aboveEqual:
1515 case lir_cond_greaterEqual: positive = false; cond = Assembler::less ; break;
1516 default: ShouldNotReachHere();
1517 }
1518
1519 // Try to use isel on >=Power7.
1520 if (VM_Version::has_isel() && result->is_cpu_register()) {
1521 bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1522 const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1523
1524 // We can use result_reg to load one operand if not already in register.
1525 Register first = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1526 second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1527
1528 if (first != second) {
1529 if (!o1_is_reg) {
1530 load_to_reg(this, opr1, result);
1531 }
1532
1533 if (!o2_is_reg) {
1534 load_to_reg(this, opr2, result);
1535 }
1536
1537 __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1538 return;
1539 }
1540 } // isel
1541
1542 load_to_reg(this, opr1, result);
1543
1544 Label skip;
1545 int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1546 int bi = Assembler::bi0(BOOL_RESULT, cond);
1547 __ bc(bo, bi, skip);
1548
1549 load_to_reg(this, opr2, result);
1550 __ bind(skip);
1551 }
1552
1553
1554 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1555 CodeEmitInfo* info, bool pop_fpu_stack) {
1556 assert(info == NULL, "unused on this code path");
1557 assert(left->is_register(), "wrong items state");
1558 assert(dest->is_register(), "wrong items state");
1559
1560 if (right->is_register()) {
1561 if (dest->is_float_kind()) {
1562
1563 FloatRegister lreg, rreg, res;
1564 if (right->is_single_fpu()) {
1565 lreg = left->as_float_reg();
1566 rreg = right->as_float_reg();
1567 res = dest->as_float_reg();
1568 switch (code) {
1569 case lir_add: __ fadds(res, lreg, rreg); break;
1570 case lir_sub: __ fsubs(res, lreg, rreg); break;
1571 case lir_mul: // fall through
1572 case lir_mul_strictfp: __ fmuls(res, lreg, rreg); break;
1573 case lir_div: // fall through
1574 case lir_div_strictfp: __ fdivs(res, lreg, rreg); break;
1575 default: ShouldNotReachHere();
1576 }
1577 } else {
1578 lreg = left->as_double_reg();
1579 rreg = right->as_double_reg();
1580 res = dest->as_double_reg();
1581 switch (code) {
1582 case lir_add: __ fadd(res, lreg, rreg); break;
1583 case lir_sub: __ fsub(res, lreg, rreg); break;
1584 case lir_mul: // fall through
1585 case lir_mul_strictfp: __ fmul(res, lreg, rreg); break;
1586 case lir_div: // fall through
1587 case lir_div_strictfp: __ fdiv(res, lreg, rreg); break;
1588 default: ShouldNotReachHere();
1589 }
1590 }
1591
1592 } else if (dest->is_double_cpu()) {
1593
1594 Register dst_lo = dest->as_register_lo();
1595 Register op1_lo = left->as_pointer_register();
1596 Register op2_lo = right->as_pointer_register();
1597
1598 switch (code) {
1599 case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1600 case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1601 case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1602 default: ShouldNotReachHere();
1603 }
1604 } else {
1605 assert (right->is_single_cpu(), "Just Checking");
1606
1607 Register lreg = left->as_register();
1608 Register res = dest->as_register();
1609 Register rreg = right->as_register();
1610 switch (code) {
1611 case lir_add: __ add (res, lreg, rreg); break;
1612 case lir_sub: __ sub (res, lreg, rreg); break;
1613 case lir_mul: __ mullw(res, lreg, rreg); break;
1614 default: ShouldNotReachHere();
1615 }
1616 }
1617 } else {
1618 assert (right->is_constant(), "must be constant");
1619
1620 if (dest->is_single_cpu()) {
1621 Register lreg = left->as_register();
1622 Register res = dest->as_register();
1623 int simm16 = right->as_constant_ptr()->as_jint();
1624
1625 switch (code) {
1626 case lir_sub: assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1627 simm16 = -simm16;
1628 case lir_add: if (res == lreg && simm16 == 0) break;
1629 __ addi(res, lreg, simm16); break;
1630 case lir_mul: if (res == lreg && simm16 == 1) break;
1631 __ mulli(res, lreg, simm16); break;
1632 default: ShouldNotReachHere();
1633 }
1634 } else {
1635 Register lreg = left->as_pointer_register();
1636 Register res = dest->as_register_lo();
1637 long con = right->as_constant_ptr()->as_jlong();
1638 assert(Assembler::is_simm16(con), "must be simm16");
1639
1640 switch (code) {
1641 case lir_sub: assert(Assembler::is_simm16(-con), "cannot encode"); // see do_ArithmeticOp_Long
1642 con = -con;
1643 case lir_add: if (res == lreg && con == 0) break;
1644 __ addi(res, lreg, (int)con); break;
1645 case lir_mul: if (res == lreg && con == 1) break;
1646 __ mulli(res, lreg, (int)con); break;
1647 default: ShouldNotReachHere();
1648 }
1649 }
1650 }
1651 }
1652
1653
1654 void LIR_Assembler::fpop() {
1655 Unimplemented();
1656 // do nothing
1657 }
1658
1659
1660 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1661 switch (code) {
1662 case lir_sqrt: {
1663 __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1664 break;
1665 }
1666 case lir_abs: {
1667 __ fabs(dest->as_double_reg(), value->as_double_reg());
1668 break;
1669 }
1670 default: {
1671 ShouldNotReachHere();
1672 break;
1673 }
1674 }
1675 }
1676
1677
1678 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1679 if (right->is_constant()) { // see do_LogicOp
1680 long uimm;
1681 Register d, l;
1682 if (dest->is_single_cpu()) {
1683 uimm = right->as_constant_ptr()->as_jint();
1684 d = dest->as_register();
1685 l = left->as_register();
1686 } else {
1687 uimm = right->as_constant_ptr()->as_jlong();
1688 d = dest->as_register_lo();
1689 l = left->as_register_lo();
1690 }
1691 long uimms = (unsigned long)uimm >> 16,
1692 uimmss = (unsigned long)uimm >> 32;
1693
1694 switch (code) {
1695 case lir_logic_and:
1696 if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2_long(uimm)) {
1697 __ andi(d, l, uimm); // special cases
1698 } else if (uimms != 0) { __ andis_(d, l, uimms); }
1699 else { __ andi_(d, l, uimm); }
1700 break;
1701
1702 case lir_logic_or:
1703 if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1704 else { __ ori(d, l, uimm); }
1705 break;
1706
1707 case lir_logic_xor:
1708 if (uimm == -1) { __ nand(d, l, l); } // special case
1709 else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1710 else { __ xori(d, l, uimm); }
1711 break;
1712
1713 default: ShouldNotReachHere();
1714 }
1715 } else {
1716 assert(right->is_register(), "right should be in register");
1717
1718 if (dest->is_single_cpu()) {
1719 switch (code) {
1720 case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1721 case lir_logic_or: __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1722 case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1723 default: ShouldNotReachHere();
1724 }
1725 } else {
1726 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1727 left->as_register_lo();
1728 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1729 right->as_register_lo();
1730
1731 switch (code) {
1732 case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1733 case lir_logic_or: __ orr (dest->as_register_lo(), l, r); break;
1734 case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1735 default: ShouldNotReachHere();
1736 }
1737 }
1738 }
1739 }
1740
1741
1742 int LIR_Assembler::shift_amount(BasicType t) {
1743 int elem_size = type2aelembytes(t);
1744 switch (elem_size) {
1745 case 1 : return 0;
1746 case 2 : return 1;
1747 case 4 : return 2;
1748 case 8 : return 3;
1749 }
1750 ShouldNotReachHere();
1751 return -1;
1752 }
1753
1754
1755 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1756 info->add_register_oop(exceptionOop);
1757
1758 // Reuse the debug info from the safepoint poll for the throw op itself.
1759 address pc_for_athrow = __ pc();
1760 int pc_for_athrow_offset = __ offset();
1761 //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1762 //__ relocate(rspec);
1763 //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1764 __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1765 add_call_info(pc_for_athrow_offset, info); // for exception handler
1766
1767 address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1768 : Runtime1::handle_exception_nofpu_id);
1769 //__ load_const_optimized(R0, stub);
1770 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1771 __ mtctr(R0);
1772 __ bctr();
1773 }
1774
1775
1776 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1777 // Note: Not used with EnableDebuggingOnDemand.
1778 assert(exceptionOop->as_register() == R3, "should match");
1779 __ b(_unwind_handler_entry);
1780 }
1781
1782
1783 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1784 Register src = op->src()->as_register();
1785 Register dst = op->dst()->as_register();
1786 Register src_pos = op->src_pos()->as_register();
1787 Register dst_pos = op->dst_pos()->as_register();
1788 Register length = op->length()->as_register();
1789 Register tmp = op->tmp()->as_register();
1790 Register tmp2 = R0;
1791
1792 int flags = op->flags();
1793 ciArrayKlass* default_type = op->expected_type();
1794 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1795 if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1796
1797 // Set up the arraycopy stub information.
1798 ArrayCopyStub* stub = op->stub();
1799 const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1800
1801 // Always do stub if no type information is available. It's ok if
1802 // the known type isn't loaded since the code sanity checks
1803 // in debug mode and the type isn't required when we know the exact type
1804 // also check that the type is an array type.
1805 if (op->expected_type() == NULL) {
1806 assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1807 length->is_nonvolatile(), "must preserve");
1808 // 3 parms are int. Convert to long.
1809 __ mr(R3_ARG1, src);
1810 __ extsw(R4_ARG2, src_pos);
1811 __ mr(R5_ARG3, dst);
1812 __ extsw(R6_ARG4, dst_pos);
1813 __ extsw(R7_ARG5, length);
1814 address copyfunc_addr = StubRoutines::generic_arraycopy();
1815
1816 if (copyfunc_addr == NULL) { // Use C version if stub was not generated.
1817 address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
1818 __ call_c_with_frame_resize(entry, frame_resize);
1819 } else {
1820 #ifndef PRODUCT
1821 if (PrintC1Statistics) {
1822 address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1823 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1824 __ lwz(R11_scratch1, simm16_offs, tmp);
1825 __ addi(R11_scratch1, R11_scratch1, 1);
1826 __ stw(R11_scratch1, simm16_offs, tmp);
1827 }
1828 #endif
1829 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1830
1831 __ nand(tmp, R3_RET, R3_RET);
1832 __ subf(length, tmp, length);
1833 __ add(src_pos, tmp, src_pos);
1834 __ add(dst_pos, tmp, dst_pos);
1835 }
1836
1837 __ cmpwi(CCR0, R3_RET, 0);
1838 __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1839 __ bind(*stub->continuation());
1840 return;
1841 }
1842
1843 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1844 Label cont, slow, copyfunc;
1845
1846 bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1847 LIR_OpArrayCopy::dst_null_check |
1848 LIR_OpArrayCopy::src_pos_positive_check |
1849 LIR_OpArrayCopy::dst_pos_positive_check |
1850 LIR_OpArrayCopy::length_positive_check);
1851
1852 // Use only one conditional branch for simple checks.
1853 if (simple_check_flag_set) {
1854 ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1855
1856 // Make sure src and dst are non-null.
1857 if (flags & LIR_OpArrayCopy::src_null_check) {
1858 __ cmpdi(combined_check, src, 0);
1859 tmp_check = CCR0;
1860 }
1861
1862 if (flags & LIR_OpArrayCopy::dst_null_check) {
1863 __ cmpdi(tmp_check, dst, 0);
1864 if (tmp_check != combined_check) {
1865 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1866 }
1867 tmp_check = CCR0;
1868 }
1869
1870 // Clear combined_check.eq if not already used.
1871 if (tmp_check == combined_check) {
1872 __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1873 tmp_check = CCR0;
1874 }
1875
1876 if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1877 // Test src_pos register.
1878 __ cmpwi(tmp_check, src_pos, 0);
1879 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1880 }
1881
1882 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1883 // Test dst_pos register.
1884 __ cmpwi(tmp_check, dst_pos, 0);
1885 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1886 }
1887
1888 if (flags & LIR_OpArrayCopy::length_positive_check) {
1889 // Make sure length isn't negative.
1890 __ cmpwi(tmp_check, length, 0);
1891 __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1892 }
1893
1894 __ beq(combined_check, slow);
1895 }
1896
1897 // If the compiler was not able to prove that exact type of the source or the destination
1898 // of the arraycopy is an array type, check at runtime if the source or the destination is
1899 // an instance type.
1900 if (flags & LIR_OpArrayCopy::type_check) {
1901 if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1902 __ load_klass(tmp, dst);
1903 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1904 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1905 __ bge(CCR0, slow);
1906 }
1907
1908 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1909 __ load_klass(tmp, src);
1910 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1911 __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1912 __ bge(CCR0, slow);
1913 }
1914 }
1915
1916 // Higher 32bits must be null.
1917 __ extsw(length, length);
1918
1919 __ extsw(src_pos, src_pos);
1920 if (flags & LIR_OpArrayCopy::src_range_check) {
1921 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1922 __ add(tmp, length, src_pos);
1923 __ cmpld(CCR0, tmp2, tmp);
1924 __ ble(CCR0, slow);
1925 }
1926
1927 __ extsw(dst_pos, dst_pos);
1928 if (flags & LIR_OpArrayCopy::dst_range_check) {
1929 __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1930 __ add(tmp, length, dst_pos);
1931 __ cmpld(CCR0, tmp2, tmp);
1932 __ ble(CCR0, slow);
1933 }
1934
1935 int shift = shift_amount(basic_type);
1936
1937 if (!(flags & LIR_OpArrayCopy::type_check)) {
1938 __ b(cont);
1939 } else {
1940 // We don't know the array types are compatible.
1941 if (basic_type != T_OBJECT) {
1942 // Simple test for basic type arrays.
1943 if (UseCompressedClassPointers) {
1944 // We don't need decode because we just need to compare.
1945 __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
1946 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1947 __ cmpw(CCR0, tmp, tmp2);
1948 } else {
1949 __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
1950 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
1951 __ cmpd(CCR0, tmp, tmp2);
1952 }
1953 __ beq(CCR0, cont);
1954 } else {
1955 // For object arrays, if src is a sub class of dst then we can
1956 // safely do the copy.
1957 address copyfunc_addr = StubRoutines::checkcast_arraycopy();
1958
1959 const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
1960 assert_different_registers(tmp, tmp2, sub_klass, super_klass);
1961
1962 __ load_klass(sub_klass, src);
1963 __ load_klass(super_klass, dst);
1964
1965 __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
1966 &cont, copyfunc_addr != NULL ? ©func : &slow, NULL);
1967
1968 address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
1969 //__ load_const_optimized(tmp, slow_stc, tmp2);
1970 __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
1971 __ mtctr(tmp);
1972 __ bctrl(); // sets CR0
1973 __ beq(CCR0, cont);
1974
1975 if (copyfunc_addr != NULL) { // Use stub if available.
1976 __ bind(copyfunc);
1977 // Src is not a sub class of dst so we have to do a
1978 // per-element check.
1979 int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
1980 if ((flags & mask) != mask) {
1981 assert(flags & mask, "one of the two should be known to be an object array");
1982
1983 if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1984 __ load_klass(tmp, src);
1985 } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1986 __ load_klass(tmp, dst);
1987 }
1988
1989 __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1990
1991 jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
1992 __ load_const_optimized(tmp, objArray_lh);
1993 __ cmpw(CCR0, tmp, tmp2);
1994 __ bne(CCR0, slow);
1995 }
1996
1997 Register src_ptr = R3_ARG1;
1998 Register dst_ptr = R4_ARG2;
1999 Register len = R5_ARG3;
2000 Register chk_off = R6_ARG4;
2001 Register super_k = R7_ARG5;
2002
2003 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2004 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2005 if (shift == 0) {
2006 __ add(src_ptr, src_pos, src_ptr);
2007 __ add(dst_ptr, dst_pos, dst_ptr);
2008 } else {
2009 __ sldi(tmp, src_pos, shift);
2010 __ sldi(tmp2, dst_pos, shift);
2011 __ add(src_ptr, tmp, src_ptr);
2012 __ add(dst_ptr, tmp2, dst_ptr);
2013 }
2014
2015 __ load_klass(tmp, dst);
2016 __ mr(len, length);
2017
2018 int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2019 __ ld(super_k, ek_offset, tmp);
2020
2021 int sco_offset = in_bytes(Klass::super_check_offset_offset());
2022 __ lwz(chk_off, sco_offset, super_k);
2023
2024 __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2025
2026 #ifndef PRODUCT
2027 if (PrintC1Statistics) {
2028 Label failed;
2029 __ cmpwi(CCR0, R3_RET, 0);
2030 __ bne(CCR0, failed);
2031 address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2032 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2033 __ lwz(R11_scratch1, simm16_offs, tmp);
2034 __ addi(R11_scratch1, R11_scratch1, 1);
2035 __ stw(R11_scratch1, simm16_offs, tmp);
2036 __ bind(failed);
2037 }
2038 #endif
2039
2040 __ nand(tmp, R3_RET, R3_RET);
2041 __ cmpwi(CCR0, R3_RET, 0);
2042 __ beq(CCR0, *stub->continuation());
2043
2044 #ifndef PRODUCT
2045 if (PrintC1Statistics) {
2046 address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2047 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2048 __ lwz(R11_scratch1, simm16_offs, tmp);
2049 __ addi(R11_scratch1, R11_scratch1, 1);
2050 __ stw(R11_scratch1, simm16_offs, tmp);
2051 }
2052 #endif
2053
2054 __ subf(length, tmp, length);
2055 __ add(src_pos, tmp, src_pos);
2056 __ add(dst_pos, tmp, dst_pos);
2057 }
2058 }
2059 }
2060 __ bind(slow);
2061 __ b(*stub->entry());
2062 __ bind(cont);
2063
2064 #ifdef ASSERT
2065 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2066 // Sanity check the known type with the incoming class. For the
2067 // primitive case the types must match exactly with src.klass and
2068 // dst.klass each exactly matching the default type. For the
2069 // object array case, if no type check is needed then either the
2070 // dst type is exactly the expected type and the src type is a
2071 // subtype which we can't check or src is the same array as dst
2072 // but not necessarily exactly of type default_type.
2073 Label known_ok, halt;
2074 metadata2reg(op->expected_type()->constant_encoding(), tmp);
2075 if (UseCompressedClassPointers) {
2076 // Tmp holds the default type. It currently comes uncompressed after the
2077 // load of a constant, so encode it.
2078 __ encode_klass_not_null(tmp);
2079 // Load the raw value of the dst klass, since we will be comparing
2080 // uncompressed values directly.
2081 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2082 __ cmpw(CCR0, tmp, tmp2);
2083 if (basic_type != T_OBJECT) {
2084 __ bne(CCR0, halt);
2085 // Load the raw value of the src klass.
2086 __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2087 __ cmpw(CCR0, tmp, tmp2);
2088 __ beq(CCR0, known_ok);
2089 } else {
2090 __ beq(CCR0, known_ok);
2091 __ cmpw(CCR0, src, dst);
2092 __ beq(CCR0, known_ok);
2093 }
2094 } else {
2095 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2096 __ cmpd(CCR0, tmp, tmp2);
2097 if (basic_type != T_OBJECT) {
2098 __ bne(CCR0, halt);
2099 // Load the raw value of the src klass.
2100 __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2101 __ cmpd(CCR0, tmp, tmp2);
2102 __ beq(CCR0, known_ok);
2103 } else {
2104 __ beq(CCR0, known_ok);
2105 __ cmpd(CCR0, src, dst);
2106 __ beq(CCR0, known_ok);
2107 }
2108 }
2109 __ bind(halt);
2110 __ stop("incorrect type information in arraycopy");
2111 __ bind(known_ok);
2112 }
2113 #endif
2114
2115 #ifndef PRODUCT
2116 if (PrintC1Statistics) {
2117 address counter = Runtime1::arraycopy_count_address(basic_type);
2118 int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2119 __ lwz(R11_scratch1, simm16_offs, tmp);
2120 __ addi(R11_scratch1, R11_scratch1, 1);
2121 __ stw(R11_scratch1, simm16_offs, tmp);
2122 }
2123 #endif
2124
2125 Register src_ptr = R3_ARG1;
2126 Register dst_ptr = R4_ARG2;
2127 Register len = R5_ARG3;
2128
2129 __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2130 __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2131 if (shift == 0) {
2132 __ add(src_ptr, src_pos, src_ptr);
2133 __ add(dst_ptr, dst_pos, dst_ptr);
2134 } else {
2135 __ sldi(tmp, src_pos, shift);
2136 __ sldi(tmp2, dst_pos, shift);
2137 __ add(src_ptr, tmp, src_ptr);
2138 __ add(dst_ptr, tmp2, dst_ptr);
2139 }
2140
2141 bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2142 bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2143 const char *name;
2144 address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2145
2146 // Arraycopy stubs takes a length in number of elements, so don't scale it.
2147 __ mr(len, length);
2148 __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2149
2150 __ bind(*stub->continuation());
2151 }
2152
2153
2154 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2155 if (dest->is_single_cpu()) {
2156 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2157 #ifdef _LP64
2158 if (left->type() == T_OBJECT) {
2159 switch (code) {
2160 case lir_shl: __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2161 case lir_shr: __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2162 case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2163 default: ShouldNotReachHere();
2164 }
2165 } else
2166 #endif
2167 switch (code) {
2168 case lir_shl: __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2169 case lir_shr: __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2170 case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2171 default: ShouldNotReachHere();
2172 }
2173 } else {
2174 __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2175 switch (code) {
2176 case lir_shl: __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2177 case lir_shr: __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2178 case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2179 default: ShouldNotReachHere();
2180 }
2181 }
2182 }
2183
2184
2185 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2186 #ifdef _LP64
2187 if (left->type() == T_OBJECT) {
2188 count = count & 63; // Shouldn't shift by more than sizeof(intptr_t).
2189 if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2190 else {
2191 switch (code) {
2192 case lir_shl: __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2193 case lir_shr: __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2194 case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2195 default: ShouldNotReachHere();
2196 }
2197 }
2198 return;
2199 }
2200 #endif
2201
2202 if (dest->is_single_cpu()) {
2203 count = count & 0x1F; // Java spec
2204 if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2205 else {
2206 switch (code) {
2207 case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2208 case lir_shr: __ srawi(dest->as_register(), left->as_register(), count); break;
2209 case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2210 default: ShouldNotReachHere();
2211 }
2212 }
2213 } else if (dest->is_double_cpu()) {
2214 count = count & 63; // Java spec
2215 if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2216 else {
2217 switch (code) {
2218 case lir_shl: __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2219 case lir_shr: __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2220 case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2221 default: ShouldNotReachHere();
2222 }
2223 }
2224 } else {
2225 ShouldNotReachHere();
2226 }
2227 }
2228
2229
2230 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2231 if (op->init_check()) {
2232 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2233 explicit_null_check(op->klass()->as_register(), op->stub()->info());
2234 } else {
2235 add_debug_info_for_null_check_here(op->stub()->info());
2236 }
2237 __ lbz(op->tmp1()->as_register(),
2238 in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2239 __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2240 __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2241 }
2242 __ allocate_object(op->obj()->as_register(),
2243 op->tmp1()->as_register(),
2244 op->tmp2()->as_register(),
2245 op->tmp3()->as_register(),
2246 op->header_size(),
2247 op->object_size(),
2248 op->klass()->as_register(),
2249 *op->stub()->entry());
2250
2251 __ bind(*op->stub()->continuation());
2252 __ verify_oop(op->obj()->as_register());
2253 }
2254
2255
2256 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2257 LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2258 if (UseSlowPath ||
2259 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2260 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2261 __ b(*op->stub()->entry());
2262 } else {
2263 __ allocate_array(op->obj()->as_register(),
2264 op->len()->as_register(),
2265 op->tmp1()->as_register(),
2266 op->tmp2()->as_register(),
2267 op->tmp3()->as_register(),
2268 arrayOopDesc::header_size(op->type()),
2269 type2aelembytes(op->type()),
2270 op->klass()->as_register(),
2271 *op->stub()->entry());
2272 }
2273 __ bind(*op->stub()->continuation());
2274 }
2275
2276
2277 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2278 ciMethodData *md, ciProfileData *data,
2279 Register recv, Register tmp1, Label* update_done) {
2280 uint i;
2281 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2282 Label next_test;
2283 // See if the receiver is receiver[n].
2284 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2285 __ verify_klass_ptr(tmp1);
2286 __ cmpd(CCR0, recv, tmp1);
2287 __ bne(CCR0, next_test);
2288
2289 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2290 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2291 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2292 __ b(*update_done);
2293
2294 __ bind(next_test);
2295 }
2296
2297 // Didn't find receiver; find next empty slot and fill it in.
2298 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2299 Label next_test;
2300 __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2301 __ cmpdi(CCR0, tmp1, 0);
2302 __ bne(CCR0, next_test);
2303 __ li(tmp1, DataLayout::counter_increment);
2304 __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2305 __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2306 __ b(*update_done);
2307
2308 __ bind(next_test);
2309 }
2310 }
2311
2312
2313 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2314 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2315 md = method->method_data_or_null();
2316 assert(md != NULL, "Sanity");
2317 data = md->bci_to_data(bci);
2318 assert(data != NULL, "need data for checkcast");
2319 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2320 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2321 // The offset is large so bias the mdo by the base of the slot so
2322 // that the ld can use simm16s to reference the slots of the data.
2323 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2324 }
2325 }
2326
2327
2328 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2329 Register obj = op->object()->as_register();
2330 Register k_RInfo = op->tmp1()->as_register();
2331 Register klass_RInfo = op->tmp2()->as_register();
2332 Register Rtmp1 = op->tmp3()->as_register();
2333 Register dst = op->result_opr()->as_register();
2334 ciKlass* k = op->klass();
2335 bool should_profile = op->should_profile();
2336 bool move_obj_to_dst = (op->code() == lir_checkcast);
2337 // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2338 bool reg_conflict = (obj == k_RInfo || obj == klass_RInfo || obj == Rtmp1);
2339 bool restore_obj = move_obj_to_dst && reg_conflict;
2340
2341 __ cmpdi(CCR0, obj, 0);
2342 if (move_obj_to_dst || reg_conflict) {
2343 __ mr_if_needed(dst, obj);
2344 if (reg_conflict) { obj = dst; }
2345 }
2346
2347 ciMethodData* md;
2348 ciProfileData* data;
2349 int mdo_offset_bias = 0;
2350 if (should_profile) {
2351 ciMethod* method = op->profiled_method();
2352 assert(method != NULL, "Should have method");
2353 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2354
2355 Register mdo = k_RInfo;
2356 Register data_val = Rtmp1;
2357 Label not_null;
2358 __ bne(CCR0, not_null);
2359 metadata2reg(md->constant_encoding(), mdo);
2360 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2361 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2362 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2363 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2364 __ b(*obj_is_null);
2365 __ bind(not_null);
2366 } else {
2367 __ beq(CCR0, *obj_is_null);
2368 }
2369
2370 // get object class
2371 __ load_klass(klass_RInfo, obj);
2372
2373 if (k->is_loaded()) {
2374 metadata2reg(k->constant_encoding(), k_RInfo);
2375 } else {
2376 klass2reg_with_patching(k_RInfo, op->info_for_patch());
2377 }
2378
2379 Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2380 Label *failure_target = should_profile ? &profile_cast_failure : failure;
2381 Label *success_target = should_profile ? &profile_cast_success : success;
2382
2383 if (op->fast_check()) {
2384 assert_different_registers(klass_RInfo, k_RInfo);
2385 __ cmpd(CCR0, k_RInfo, klass_RInfo);
2386 if (should_profile) {
2387 __ bne(CCR0, *failure_target);
2388 // Fall through to success case.
2389 } else {
2390 __ beq(CCR0, *success);
2391 // Fall through to failure case.
2392 }
2393 } else {
2394 bool need_slow_path = true;
2395 if (k->is_loaded()) {
2396 if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2397 need_slow_path = false;
2398 }
2399 // Perform the fast part of the checking logic.
2400 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2401 failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2402 } else {
2403 // Perform the fast part of the checking logic.
2404 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2405 }
2406 if (!need_slow_path) {
2407 if (!should_profile) { __ b(*success); }
2408 } else {
2409 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2410 address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2411 //__ load_const_optimized(Rtmp1, entry, R0);
2412 __ calculate_address_from_global_toc(Rtmp1, entry, true, true, false);
2413 __ mtctr(Rtmp1);
2414 __ bctrl(); // sets CR0
2415 if (should_profile) {
2416 __ bne(CCR0, *failure_target);
2417 // Fall through to success case.
2418 } else {
2419 __ beq(CCR0, *success);
2420 // Fall through to failure case.
2421 }
2422 }
2423 }
2424
2425 if (should_profile) {
2426 Register mdo = k_RInfo, recv = klass_RInfo;
2427 assert_different_registers(mdo, recv, Rtmp1);
2428 __ bind(profile_cast_success);
2429 metadata2reg(md->constant_encoding(), mdo);
2430 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2431 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2432 __ b(*success);
2433
2434 // Cast failure case.
2435 __ bind(profile_cast_failure);
2436 metadata2reg(md->constant_encoding(), mdo);
2437 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2438 __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2439 __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2440 __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2441 }
2442
2443 __ bind(*failure);
2444
2445 if (restore_obj) {
2446 __ mr(op->object()->as_register(), dst);
2447 // Fall through to failure case.
2448 }
2449 }
2450
2451
2452 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2453 LIR_Code code = op->code();
2454 if (code == lir_store_check) {
2455 Register value = op->object()->as_register();
2456 Register array = op->array()->as_register();
2457 Register k_RInfo = op->tmp1()->as_register();
2458 Register klass_RInfo = op->tmp2()->as_register();
2459 Register Rtmp1 = op->tmp3()->as_register();
2460 bool should_profile = op->should_profile();
2461
2462 __ verify_oop(value);
2463 CodeStub* stub = op->stub();
2464 // Check if it needs to be profiled.
2465 ciMethodData* md;
2466 ciProfileData* data;
2467 int mdo_offset_bias = 0;
2468 if (should_profile) {
2469 ciMethod* method = op->profiled_method();
2470 assert(method != NULL, "Should have method");
2471 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2472 }
2473 Label profile_cast_success, failure, done;
2474 Label *success_target = should_profile ? &profile_cast_success : &done;
2475
2476 __ cmpdi(CCR0, value, 0);
2477 if (should_profile) {
2478 Label not_null;
2479 __ bne(CCR0, not_null);
2480 Register mdo = k_RInfo;
2481 Register data_val = Rtmp1;
2482 metadata2reg(md->constant_encoding(), mdo);
2483 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2484 __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2485 __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2486 __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2487 __ b(done);
2488 __ bind(not_null);
2489 } else {
2490 __ beq(CCR0, done);
2491 }
2492 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2493 explicit_null_check(array, op->info_for_exception());
2494 } else {
2495 add_debug_info_for_null_check_here(op->info_for_exception());
2496 }
2497 __ load_klass(k_RInfo, array);
2498 __ load_klass(klass_RInfo, value);
2499
2500 // Get instance klass.
2501 __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2502 // Perform the fast part of the checking logic.
2503 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2504
2505 // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2506 const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2507 //__ load_const_optimized(R0, slow_path);
2508 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2509 __ mtctr(R0);
2510 __ bctrl(); // sets CR0
2511 if (!should_profile) {
2512 __ beq(CCR0, done);
2513 __ bind(failure);
2514 } else {
2515 __ bne(CCR0, failure);
2516 // Fall through to the success case.
2517
2518 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2519 assert_different_registers(value, mdo, recv, tmp1);
2520 __ bind(profile_cast_success);
2521 metadata2reg(md->constant_encoding(), mdo);
2522 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2523 __ load_klass(recv, value);
2524 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2525 __ b(done);
2526
2527 // Cast failure case.
2528 __ bind(failure);
2529 metadata2reg(md->constant_encoding(), mdo);
2530 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2531 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2532 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2533 __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2534 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2535 }
2536 __ b(*stub->entry());
2537 __ bind(done);
2538
2539 } else if (code == lir_checkcast) {
2540 Label success, failure;
2541 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success); // Moves obj to dst.
2542 __ b(*op->stub()->entry());
2543 __ align(32, 12);
2544 __ bind(success);
2545 } else if (code == lir_instanceof) {
2546 Register dst = op->result_opr()->as_register();
2547 Label success, failure, done;
2548 emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2549 __ li(dst, 0);
2550 __ b(done);
2551 __ align(32, 12);
2552 __ bind(success);
2553 __ li(dst, 1);
2554 __ bind(done);
2555 } else {
2556 ShouldNotReachHere();
2557 }
2558 }
2559
2560
2561 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2562 Register addr = op->addr()->as_pointer_register();
2563 Register cmp_value = noreg, new_value = noreg;
2564 bool is_64bit = false;
2565
2566 if (op->code() == lir_cas_long) {
2567 cmp_value = op->cmp_value()->as_register_lo();
2568 new_value = op->new_value()->as_register_lo();
2569 is_64bit = true;
2570 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2571 cmp_value = op->cmp_value()->as_register();
2572 new_value = op->new_value()->as_register();
2573 if (op->code() == lir_cas_obj) {
2574 if (UseCompressedOops) {
2575 Register t1 = op->tmp1()->as_register();
2576 Register t2 = op->tmp2()->as_register();
2577 cmp_value = __ encode_heap_oop(t1, cmp_value);
2578 new_value = __ encode_heap_oop(t2, new_value);
2579 } else {
2580 is_64bit = true;
2581 }
2582 }
2583 } else {
2584 Unimplemented();
2585 }
2586
2587 if (is_64bit) {
2588 __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2589 MacroAssembler::MemBarNone,
2590 MacroAssembler::cmpxchgx_hint_atomic_update(),
2591 noreg, NULL, /*check without ldarx first*/true);
2592 } else {
2593 __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2594 MacroAssembler::MemBarNone,
2595 MacroAssembler::cmpxchgx_hint_atomic_update(),
2596 noreg, /*check without ldarx first*/true);
2597 }
2598
2599 if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2600 __ isync();
2601 } else {
2602 __ sync();
2603 }
2604 }
2605
2606
2607 void LIR_Assembler::set_24bit_FPU() {
2608 Unimplemented();
2609 }
2610
2611 void LIR_Assembler::reset_FPU() {
2612 Unimplemented();
2613 }
2614
2615
2616 void LIR_Assembler::breakpoint() {
2617 __ illtrap();
2618 }
2619
2620
2621 void LIR_Assembler::push(LIR_Opr opr) {
2622 Unimplemented();
2623 }
2624
2625 void LIR_Assembler::pop(LIR_Opr opr) {
2626 Unimplemented();
2627 }
2628
2629
2630 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2631 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2632 Register dst = dst_opr->as_register();
2633 Register reg = mon_addr.base();
2634 int offset = mon_addr.disp();
2635 // Compute pointer to BasicLock.
2636 __ add_const_optimized(dst, reg, offset);
2637 }
2638
2639
2640 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2641 Register obj = op->obj_opr()->as_register();
2642 Register hdr = op->hdr_opr()->as_register();
2643 Register lock = op->lock_opr()->as_register();
2644
2645 // Obj may not be an oop.
2646 if (op->code() == lir_lock) {
2647 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2648 if (UseFastLocking) {
2649 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2650 // Add debug info for NullPointerException only if one is possible.
2651 if (op->info() != NULL) {
2652 if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2653 explicit_null_check(obj, op->info());
2654 } else {
2655 add_debug_info_for_null_check_here(op->info());
2656 }
2657 }
2658 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2659 } else {
2660 // always do slow locking
2661 // note: The slow locking code could be inlined here, however if we use
2662 // slow locking, speed doesn't matter anyway and this solution is
2663 // simpler and requires less duplicated code - additionally, the
2664 // slow locking code is the same in either case which simplifies
2665 // debugging.
2666 __ b(*op->stub()->entry());
2667 }
2668 } else {
2669 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2670 if (UseFastLocking) {
2671 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2672 __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2673 } else {
2674 // always do slow unlocking
2675 // note: The slow unlocking code could be inlined here, however if we use
2676 // slow unlocking, speed doesn't matter anyway and this solution is
2677 // simpler and requires less duplicated code - additionally, the
2678 // slow unlocking code is the same in either case which simplifies
2679 // debugging.
2680 __ b(*op->stub()->entry());
2681 }
2682 }
2683 __ bind(*op->stub()->continuation());
2684 }
2685
2686
2687 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2688 ciMethod* method = op->profiled_method();
2689 int bci = op->profiled_bci();
2690 ciMethod* callee = op->profiled_callee();
2691
2692 // Update counter for all call types.
2693 ciMethodData* md = method->method_data_or_null();
2694 assert(md != NULL, "Sanity");
2695 ciProfileData* data = md->bci_to_data(bci);
2696 assert(data->is_CounterData(), "need CounterData for calls");
2697 assert(op->mdo()->is_single_cpu(), "mdo must be allocated");
2698 Register mdo = op->mdo()->as_register();
2699 #ifdef _LP64
2700 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2701 Register tmp1 = op->tmp1()->as_register_lo();
2702 #else
2703 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2704 Register tmp1 = op->tmp1()->as_register();
2705 #endif
2706 metadata2reg(md->constant_encoding(), mdo);
2707 int mdo_offset_bias = 0;
2708 if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2709 data->size_in_bytes())) {
2710 // The offset is large so bias the mdo by the base of the slot so
2711 // that the ld can use simm16s to reference the slots of the data.
2712 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2713 __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2714 }
2715
2716 Bytecodes::Code bc = method->java_code_at_bci(bci);
2717 const bool callee_is_static = callee->is_loaded() && callee->is_static();
2718 // Perform additional virtual call profiling for invokevirtual and
2719 // invokeinterface bytecodes.
2720 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2721 !callee_is_static && // Required for optimized MH invokes.
2722 C1ProfileVirtualCalls) {
2723 assert(op->recv()->is_single_cpu(), "recv must be allocated");
2724 Register recv = op->recv()->as_register();
2725 assert_different_registers(mdo, tmp1, recv);
2726 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2727 ciKlass* known_klass = op->known_holder();
2728 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2729 // We know the type that will be seen at this call site; we can
2730 // statically update the MethodData* rather than needing to do
2731 // dynamic tests on the receiver type.
2732
2733 // NOTE: we should probably put a lock around this search to
2734 // avoid collisions by concurrent compilations.
2735 ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2736 uint i;
2737 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2738 ciKlass* receiver = vc_data->receiver(i);
2739 if (known_klass->equals(receiver)) {
2740 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2741 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2742 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2743 return;
2744 }
2745 }
2746
2747 // Receiver type not found in profile data; select an empty slot.
2748
2749 // Note that this is less efficient than it should be because it
2750 // always does a write to the receiver part of the
2751 // VirtualCallData rather than just the first time.
2752 for (i = 0; i < VirtualCallData::row_limit(); i++) {
2753 ciKlass* receiver = vc_data->receiver(i);
2754 if (receiver == NULL) {
2755 metadata2reg(known_klass->constant_encoding(), tmp1);
2756 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2757
2758 __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2759 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2760 __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2761 return;
2762 }
2763 }
2764 } else {
2765 __ load_klass(recv, recv);
2766 Label update_done;
2767 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2768 // Receiver did not match any saved receiver and there is no empty row for it.
2769 // Increment total counter to indicate polymorphic case.
2770 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2771 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2772 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2773
2774 __ bind(update_done);
2775 }
2776 } else {
2777 // Static call
2778 __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2779 __ addi(tmp1, tmp1, DataLayout::counter_increment);
2780 __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2781 }
2782 }
2783
2784
2785 void LIR_Assembler::align_backward_branch_target() {
2786 __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2787 }
2788
2789
2790 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2791 Unimplemented();
2792 }
2793
2794
2795 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2796 assert(left->is_register(), "can only handle registers");
2797
2798 if (left->is_single_cpu()) {
2799 __ neg(dest->as_register(), left->as_register());
2800 } else if (left->is_single_fpu()) {
2801 __ fneg(dest->as_float_reg(), left->as_float_reg());
2802 } else if (left->is_double_fpu()) {
2803 __ fneg(dest->as_double_reg(), left->as_double_reg());
2804 } else {
2805 assert (left->is_double_cpu(), "Must be a long");
2806 __ neg(dest->as_register_lo(), left->as_register_lo());
2807 }
2808 }
2809
2810
2811 void LIR_Assembler::fxch(int i) {
2812 Unimplemented();
2813 }
2814
2815 void LIR_Assembler::fld(int i) {
2816 Unimplemented();
2817 }
2818
2819 void LIR_Assembler::ffree(int i) {
2820 Unimplemented();
2821 }
2822
2823
2824 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2825 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2826 // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2827 if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2828 dest == Runtime1::entry_for(Runtime1::new_multi_array_id )) {
2829 //__ load_const_optimized(R0, dest);
2830 __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2831 __ mtctr(R0);
2832 __ bctrl();
2833 assert(info != NULL, "sanity");
2834 add_call_info_here(info);
2835 return;
2836 }
2837
2838 __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2839 if (info != NULL) {
2840 add_call_info_here(info);
2841 }
2842 }
2843
2844
2845 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2846 ShouldNotReachHere(); // Not needed on _LP64.
2847 }
2848
2849 void LIR_Assembler::membar() {
2850 __ fence();
2851 }
2852
2853 void LIR_Assembler::membar_acquire() {
2854 __ acquire();
2855 }
2856
2857 void LIR_Assembler::membar_release() {
2858 __ release();
2859 }
2860
2861 void LIR_Assembler::membar_loadload() {
2862 __ membar(Assembler::LoadLoad);
2863 }
2864
2865 void LIR_Assembler::membar_storestore() {
2866 __ membar(Assembler::StoreStore);
2867 }
2868
2869 void LIR_Assembler::membar_loadstore() {
2870 __ membar(Assembler::LoadStore);
2871 }
2872
2873 void LIR_Assembler::membar_storeload() {
2874 __ membar(Assembler::StoreLoad);
2875 }
2876
2877 void LIR_Assembler::on_spin_wait() {
2878 Unimplemented();
2879 }
2880
2881 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
2882 LIR_Address* addr = addr_opr->as_address_ptr();
2883 assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2884 if (addr->index()->is_illegal()) {
2885 __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2886 } else {
2887 assert(addr->disp() == 0, "can't have both: index and disp");
2888 __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2889 }
2890 }
2891
2892
2893 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2894 ShouldNotReachHere();
2895 }
2896
2897
2898 #ifdef ASSERT
2899 // Emit run-time assertion.
2900 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2901 Unimplemented();
2902 }
2903 #endif
2904
2905
2906 void LIR_Assembler::peephole(LIR_List* lir) {
2907 // Optimize instruction pairs before emitting.
2908 LIR_OpList* inst = lir->instructions_list();
2909 for (int i = 1; i < inst->length(); i++) {
2910 LIR_Op* op = inst->at(i);
2911
2912 // 2 register-register-moves
2913 if (op->code() == lir_move) {
2914 LIR_Opr in2 = ((LIR_Op1*)op)->in_opr(),
2915 res2 = ((LIR_Op1*)op)->result_opr();
2916 if (in2->is_register() && res2->is_register()) {
2917 LIR_Op* prev = inst->at(i - 1);
2918 if (prev && prev->code() == lir_move) {
2919 LIR_Opr in1 = ((LIR_Op1*)prev)->in_opr(),
2920 res1 = ((LIR_Op1*)prev)->result_opr();
2921 if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2922 inst->remove_at(i);
2923 }
2924 }
2925 }
2926 }
2927
2928 }
2929 return;
2930 }
2931
2932
2933 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2934 const Register Rptr = src->as_pointer_register(),
2935 Rtmp = tmp->as_register();
2936 Register Rco = noreg;
2937 if (UseCompressedOops && data->is_oop()) {
2938 Rco = __ encode_heap_oop(Rtmp, data->as_register());
2939 }
2940
2941 Label Lretry;
2942 __ bind(Lretry);
2943
2944 if (data->type() == T_INT) {
2945 const Register Rold = dest->as_register(),
2946 Rsrc = data->as_register();
2947 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2948 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2949 if (code == lir_xadd) {
2950 __ add(Rtmp, Rsrc, Rold);
2951 __ stwcx_(Rtmp, Rptr);
2952 } else {
2953 __ stwcx_(Rsrc, Rptr);
2954 }
2955 } else if (data->is_oop()) {
2956 assert(code == lir_xchg, "xadd for oops");
2957 const Register Rold = dest->as_register();
2958 if (UseCompressedOops) {
2959 assert_different_registers(Rptr, Rold, Rco);
2960 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2961 __ stwcx_(Rco, Rptr);
2962 } else {
2963 const Register Robj = data->as_register();
2964 assert_different_registers(Rptr, Rold, Robj);
2965 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2966 __ stdcx_(Robj, Rptr);
2967 }
2968 } else if (data->type() == T_LONG) {
2969 const Register Rold = dest->as_register_lo(),
2970 Rsrc = data->as_register_lo();
2971 assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
2972 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
2973 if (code == lir_xadd) {
2974 __ add(Rtmp, Rsrc, Rold);
2975 __ stdcx_(Rtmp, Rptr);
2976 } else {
2977 __ stdcx_(Rsrc, Rptr);
2978 }
2979 } else {
2980 ShouldNotReachHere();
2981 }
2982
2983 if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
2984 __ bne_predict_not_taken(CCR0, Lretry);
2985 } else {
2986 __ bne( CCR0, Lretry);
2987 }
2988
2989 if (UseCompressedOops && data->is_oop()) {
2990 __ decode_heap_oop(dest->as_register());
2991 }
2992 }
2993
2994
2995 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2996 Register obj = op->obj()->as_register();
2997 Register tmp = op->tmp()->as_pointer_register();
2998 LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
2999 ciKlass* exact_klass = op->exact_klass();
3000 intptr_t current_klass = op->current_klass();
3001 bool not_null = op->not_null();
3002 bool no_conflict = op->no_conflict();
3003
3004 Label Lupdate, Ldo_update, Ldone;
3005
3006 bool do_null = !not_null;
3007 bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3008 bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3009
3010 assert(do_null || do_update, "why are we here?");
3011 assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3012
3013 __ verify_oop(obj);
3014
3015 if (do_null) {
3016 if (!TypeEntries::was_null_seen(current_klass)) {
3017 __ cmpdi(CCR0, obj, 0);
3018 __ bne(CCR0, Lupdate);
3019 __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3020 __ ori(R0, R0, TypeEntries::null_seen);
3021 if (do_update) {
3022 __ b(Ldo_update);
3023 } else {
3024 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3025 }
3026 } else {
3027 if (do_update) {
3028 __ cmpdi(CCR0, obj, 0);
3029 __ beq(CCR0, Ldone);
3030 }
3031 }
3032 #ifdef ASSERT
3033 } else {
3034 __ cmpdi(CCR0, obj, 0);
3035 __ bne(CCR0, Lupdate);
3036 __ stop("unexpect null obj", 0x9652);
3037 #endif
3038 }
3039
3040 __ bind(Lupdate);
3041 if (do_update) {
3042 Label Lnext;
3043 const Register klass = R29_TOC; // kill and reload
3044 bool klass_reg_used = false;
3045 #ifdef ASSERT
3046 if (exact_klass != NULL) {
3047 Label ok;
3048 klass_reg_used = true;
3049 __ load_klass(klass, obj);
3050 metadata2reg(exact_klass->constant_encoding(), R0);
3051 __ cmpd(CCR0, klass, R0);
3052 __ beq(CCR0, ok);
3053 __ stop("exact klass and actual klass differ", 0x8564);
3054 __ bind(ok);
3055 }
3056 #endif
3057
3058 if (!no_conflict) {
3059 if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3060 klass_reg_used = true;
3061 if (exact_klass != NULL) {
3062 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3063 metadata2reg(exact_klass->constant_encoding(), klass);
3064 } else {
3065 __ load_klass(klass, obj);
3066 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3067 }
3068
3069 // Like InterpreterMacroAssembler::profile_obj_type
3070 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3071 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3072 __ cmpd(CCR1, R0, klass);
3073 // Klass seen before, nothing to do (regardless of unknown bit).
3074 //beq(CCR1, do_nothing);
3075
3076 __ andi_(R0, klass, TypeEntries::type_unknown);
3077 // Already unknown. Nothing to do anymore.
3078 //bne(CCR0, do_nothing);
3079 __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3080 __ beq(CCR0, Lnext);
3081
3082 if (TypeEntries::is_type_none(current_klass)) {
3083 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3084 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3085 __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3086 }
3087
3088 } else {
3089 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3090 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3091
3092 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3093 __ andi_(R0, tmp, TypeEntries::type_unknown);
3094 // Already unknown. Nothing to do anymore.
3095 __ bne(CCR0, Lnext);
3096 }
3097
3098 // Different than before. Cannot keep accurate profile.
3099 __ ori(R0, tmp, TypeEntries::type_unknown);
3100 } else {
3101 // There's a single possible klass at this profile point
3102 assert(exact_klass != NULL, "should be");
3103 __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3104
3105 if (TypeEntries::is_type_none(current_klass)) {
3106 klass_reg_used = true;
3107 metadata2reg(exact_klass->constant_encoding(), klass);
3108
3109 __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3110 // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3111 __ cmpd(CCR1, R0, klass);
3112 // Klass seen before, nothing to do (regardless of unknown bit).
3113 __ beq(CCR1, Lnext);
3114 #ifdef ASSERT
3115 {
3116 Label ok;
3117 __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3118 __ beq(CCR0, ok); // First time here.
3119
3120 __ stop("unexpected profiling mismatch", 0x7865);
3121 __ bind(ok);
3122 }
3123 #endif
3124 // First time here. Set profile type.
3125 __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3126 } else {
3127 assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3128 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3129
3130 // Already unknown. Nothing to do anymore.
3131 __ andi_(R0, tmp, TypeEntries::type_unknown);
3132 __ bne(CCR0, Lnext);
3133
3134 // Different than before. Cannot keep accurate profile.
3135 __ ori(R0, tmp, TypeEntries::type_unknown);
3136 }
3137 }
3138
3139 __ bind(Ldo_update);
3140 __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3141
3142 __ bind(Lnext);
3143 if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3144 }
3145 __ bind(Ldone);
3146 }
3147
3148
3149 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3150 assert(op->crc()->is_single_cpu(), "crc must be register");
3151 assert(op->val()->is_single_cpu(), "byte value must be register");
3152 assert(op->result_opr()->is_single_cpu(), "result must be register");
3153 Register crc = op->crc()->as_register();
3154 Register val = op->val()->as_register();
3155 Register res = op->result_opr()->as_register();
3156
3157 assert_different_registers(val, crc, res);
3158
3159 __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3160 __ nand(crc, crc, crc); // ~crc
3161 __ update_byte_crc32(crc, val, res);
3162 __ nand(res, crc, crc); // ~crc
3163 }
3164
3165 #undef __