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src/cpu/ppc/vm/ppc.ad

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rev 12409 : 8171244: PPC64: Make interpreter's math entries consistent with C1 and C2 and support FMA
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*** 9567,9576 **** --- 9567,9719 ---- // PPC results are already "rounded" (i.e., normal-format IEEE). ins_encode( /*empty*/ ); ins_pipe(pipe_class_default); %} + + // Multiply-Accumulate + // src1 * src2 + src3 + instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{ + predicate(UseFMA); + match(Set dst (FmaF src3 (Binary src1 src2))); + + format %{ "FMADDS $dst, $src1, $src2, $src3" %} + size(4); + ins_encode %{ + // TODO: PPC port $archOpcode(ppc64Opcode_fmadds); + __ fmadds(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg), + as_FloatRegister($src3$$reg)); + %} + ins_pipe(pipe_class_default); + %} + + // src1 * src2 + src3 + instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ + predicate(UseFMA); + match(Set dst (FmaD src3 (Binary src1 src2))); + + format %{ "FMADD $dst, $src1, $src2, $src3" %} + size(4); + ins_encode %{ + // TODO: PPC port $archOpcode(ppc64Opcode_fmadd); + __ fmadd(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg), + as_FloatRegister($src3$$reg)); + %} + ins_pipe(pipe_class_default); + %} + + // -src1 * src2 + src3 = -(src1*src2-src3) + instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{ + predicate(UseFMA); + match(Set dst (FmaF src3 (Binary (NegF src1) src2))); + match(Set dst (FmaF src3 (Binary src1 (NegF src2)))); + + format %{ "FNMSUBS $dst, $src1, $src2, $src3" %} + size(4); + ins_encode %{ + // TODO: PPC port $archOpcode(ppc64Opcode_fnmsubs); + __ fnmsubs(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg), + as_FloatRegister($src3$$reg)); + %} + ins_pipe(pipe_class_default); + %} + + // -src1 * src2 + src3 = -(src1*src2-src3) + instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ + predicate(UseFMA); + match(Set dst (FmaD src3 (Binary (NegD src1) src2))); + match(Set dst (FmaD src3 (Binary src1 (NegD src2)))); + + format %{ "FNMSUB $dst, $src1, $src2, $src3" %} + size(4); + ins_encode %{ + // TODO: PPC port $archOpcode(ppc64Opcode_fnmsub); + __ fnmsub(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg), + as_FloatRegister($src3$$reg)); + %} + ins_pipe(pipe_class_default); + %} + + // -src1 * src2 - src3 = -(src1*src2+src3) + instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{ + predicate(UseFMA); + match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2))); + match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2)))); + + format %{ "FNMADDS $dst, $src1, $src2, $src3" %} + size(4); + ins_encode %{ + // TODO: PPC port $archOpcode(ppc64Opcode_fnmadds); + __ fnmadds(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg), + as_FloatRegister($src3$$reg)); + %} + ins_pipe(pipe_class_default); + %} + + // -src1 * src2 - src3 = -(src1*src2+src3) + instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ + predicate(UseFMA); + match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2))); + match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2)))); + + format %{ "FNMADD $dst, $src1, $src2, $src3" %} + size(4); + ins_encode %{ + // TODO: PPC port $archOpcode(ppc64Opcode_fnmadd); + __ fnmadd(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg), + as_FloatRegister($src3$$reg)); + %} + ins_pipe(pipe_class_default); + %} + + // src1 * src2 - src3 + instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{ + predicate(UseFMA); + match(Set dst (FmaF (NegF src3) (Binary src1 src2))); + + format %{ "FMSUBS $dst, $src1, $src2, $src3" %} + size(4); + ins_encode %{ + // TODO: PPC port $archOpcode(ppc64Opcode_fmsubs); + __ fmsubs(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg), + as_FloatRegister($src3$$reg)); + %} + ins_pipe(pipe_class_default); + %} + + // src1 * src2 - src3 + instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{ + predicate(UseFMA); + match(Set dst (FmaD (NegD src3) (Binary src1 src2))); + + format %{ "FMSUB $dst, $src1, $src2, $src3" %} + size(4); + ins_encode %{ + // TODO: PPC port $archOpcode(ppc64Opcode_fmsub); + __ fmsub(as_FloatRegister($dst$$reg), + as_FloatRegister($src1$$reg), + as_FloatRegister($src2$$reg), + as_FloatRegister($src3$$reg)); + %} + ins_pipe(pipe_class_default); + %} + + //----------Logical Instructions----------------------------------------------- // And Instructions // Register And
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