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src/cpu/ppc/vm/ppc.ad

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rev 12409 : 8171244: PPC64: Make interpreter's math entries consistent with C1 and C2 and support FMA
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9552   ins_cost(0);
9553 
9554   format %{ " -- \t// RoundDouble not needed - empty" %}
9555   size(0);
9556   // PPC results are already "rounded" (i.e., normal-format IEEE).
9557   ins_encode( /*empty*/ );
9558   ins_pipe(pipe_class_default);
9559 %}
9560 
9561 instruct roundFloat_nop(regF dst) %{
9562   match(Set dst (RoundFloat dst));
9563   ins_cost(0);
9564 
9565   format %{ " -- \t// RoundFloat not needed - empty" %}
9566   size(0);
9567   // PPC results are already "rounded" (i.e., normal-format IEEE).
9568   ins_encode( /*empty*/ );
9569   ins_pipe(pipe_class_default);
9570 %}
9571 















































































































































9572 //----------Logical Instructions-----------------------------------------------
9573 
9574 // And Instructions
9575 
9576 // Register And
9577 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9578   match(Set dst (AndI src1 src2));
9579   format %{ "AND     $dst, $src1, $src2" %}
9580   size(4);
9581   ins_encode %{
9582     // TODO: PPC port $archOpcode(ppc64Opcode_and);
9583     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9584   %}
9585   ins_pipe(pipe_class_default);
9586 %}
9587 
9588 // Left shifted Immediate And
9589 instruct andI_reg_immIhi16(iRegIdst dst, iRegIsrc src1, immIhi16  src2, flagsRegCR0 cr0) %{
9590   match(Set dst (AndI src1 src2));
9591   effect(KILL cr0);




9552   ins_cost(0);
9553 
9554   format %{ " -- \t// RoundDouble not needed - empty" %}
9555   size(0);
9556   // PPC results are already "rounded" (i.e., normal-format IEEE).
9557   ins_encode( /*empty*/ );
9558   ins_pipe(pipe_class_default);
9559 %}
9560 
9561 instruct roundFloat_nop(regF dst) %{
9562   match(Set dst (RoundFloat dst));
9563   ins_cost(0);
9564 
9565   format %{ " -- \t// RoundFloat not needed - empty" %}
9566   size(0);
9567   // PPC results are already "rounded" (i.e., normal-format IEEE).
9568   ins_encode( /*empty*/ );
9569   ins_pipe(pipe_class_default);
9570 %}
9571 
9572 
9573 // Multiply-Accumulate
9574 // src1 * src2 + src3
9575 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9576   predicate(UseFMA);
9577   match(Set dst (FmaF src3 (Binary src1 src2)));
9578 
9579   format %{ "FMADDS  $dst, $src1, $src2, $src3" %}
9580   size(4);
9581   ins_encode %{
9582     // TODO: PPC port $archOpcode(ppc64Opcode_fmadds);
9583     __ fmadds(as_FloatRegister($dst$$reg),
9584               as_FloatRegister($src1$$reg),
9585               as_FloatRegister($src2$$reg),
9586               as_FloatRegister($src3$$reg));
9587   %}
9588   ins_pipe(pipe_class_default);
9589 %}
9590 
9591 // src1 * src2 + src3
9592 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9593   predicate(UseFMA);
9594   match(Set dst (FmaD src3 (Binary src1 src2)));
9595 
9596   format %{ "FMADD   $dst, $src1, $src2, $src3" %}
9597   size(4);
9598   ins_encode %{
9599     // TODO: PPC port $archOpcode(ppc64Opcode_fmadd);
9600     __ fmadd(as_FloatRegister($dst$$reg),
9601              as_FloatRegister($src1$$reg),
9602              as_FloatRegister($src2$$reg),
9603              as_FloatRegister($src3$$reg));
9604   %}
9605   ins_pipe(pipe_class_default);
9606 %}
9607 
9608 // -src1 * src2 + src3 = -(src1*src2-src3)
9609 instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9610   predicate(UseFMA);
9611   match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
9612   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
9613 
9614   format %{ "FNMSUBS $dst, $src1, $src2, $src3" %}
9615   size(4);
9616   ins_encode %{
9617     // TODO: PPC port $archOpcode(ppc64Opcode_fnmsubs);
9618     __ fnmsubs(as_FloatRegister($dst$$reg),
9619                as_FloatRegister($src1$$reg),
9620                as_FloatRegister($src2$$reg),
9621                as_FloatRegister($src3$$reg));
9622   %}
9623   ins_pipe(pipe_class_default);
9624 %}
9625 
9626 // -src1 * src2 + src3 = -(src1*src2-src3)
9627 instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9628   predicate(UseFMA);
9629   match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
9630   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
9631 
9632   format %{ "FNMSUB  $dst, $src1, $src2, $src3" %}
9633   size(4);
9634   ins_encode %{
9635     // TODO: PPC port $archOpcode(ppc64Opcode_fnmsub);
9636     __ fnmsub(as_FloatRegister($dst$$reg),
9637               as_FloatRegister($src1$$reg),
9638               as_FloatRegister($src2$$reg),
9639               as_FloatRegister($src3$$reg));
9640   %}
9641   ins_pipe(pipe_class_default);
9642 %}
9643 
9644 // -src1 * src2 - src3 = -(src1*src2+src3)
9645 instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9646   predicate(UseFMA);
9647   match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
9648   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
9649 
9650   format %{ "FNMADDS $dst, $src1, $src2, $src3" %}
9651   size(4);
9652   ins_encode %{
9653     // TODO: PPC port $archOpcode(ppc64Opcode_fnmadds);
9654     __ fnmadds(as_FloatRegister($dst$$reg),
9655                as_FloatRegister($src1$$reg),
9656                as_FloatRegister($src2$$reg),
9657                as_FloatRegister($src3$$reg));
9658   %}
9659   ins_pipe(pipe_class_default);
9660 %}
9661 
9662 // -src1 * src2 - src3 = -(src1*src2+src3)
9663 instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9664   predicate(UseFMA);
9665   match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
9666   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
9667 
9668   format %{ "FNMADD  $dst, $src1, $src2, $src3" %}
9669   size(4);
9670   ins_encode %{
9671     // TODO: PPC port $archOpcode(ppc64Opcode_fnmadd);
9672     __ fnmadd(as_FloatRegister($dst$$reg),
9673               as_FloatRegister($src1$$reg),
9674               as_FloatRegister($src2$$reg),
9675               as_FloatRegister($src3$$reg));
9676   %}
9677   ins_pipe(pipe_class_default);
9678 %}
9679 
9680 // src1 * src2 - src3
9681 instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9682   predicate(UseFMA);
9683   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
9684 
9685   format %{ "FMSUBS  $dst, $src1, $src2, $src3" %}
9686   size(4);
9687   ins_encode %{
9688     // TODO: PPC port $archOpcode(ppc64Opcode_fmsubs);
9689     __ fmsubs(as_FloatRegister($dst$$reg),
9690               as_FloatRegister($src1$$reg),
9691               as_FloatRegister($src2$$reg),
9692               as_FloatRegister($src3$$reg));
9693   %}
9694   ins_pipe(pipe_class_default);
9695 %}
9696 
9697 // src1 * src2 - src3
9698 instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9699   predicate(UseFMA);
9700   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
9701 
9702   format %{ "FMSUB   $dst, $src1, $src2, $src3" %}
9703   size(4);
9704   ins_encode %{
9705     // TODO: PPC port $archOpcode(ppc64Opcode_fmsub);
9706     __ fmsub(as_FloatRegister($dst$$reg),
9707              as_FloatRegister($src1$$reg),
9708              as_FloatRegister($src2$$reg),
9709              as_FloatRegister($src3$$reg));
9710   %}
9711   ins_pipe(pipe_class_default);
9712 %}
9713 
9714 
9715 //----------Logical Instructions-----------------------------------------------
9716 
9717 // And Instructions
9718 
9719 // Register And
9720 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9721   match(Set dst (AndI src1 src2));
9722   format %{ "AND     $dst, $src1, $src2" %}
9723   size(4);
9724   ins_encode %{
9725     // TODO: PPC port $archOpcode(ppc64Opcode_and);
9726     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9727   %}
9728   ins_pipe(pipe_class_default);
9729 %}
9730 
9731 // Left shifted Immediate And
9732 instruct andI_reg_immIhi16(iRegIdst dst, iRegIsrc src1, immIhi16  src2, flagsRegCR0 cr0) %{
9733   match(Set dst (AndI src1 src2));
9734   effect(KILL cr0);


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