1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #include "precompiled.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "asm/macroAssembler.inline.hpp" 29 #include "compiler/disassembler.hpp" 30 #include "memory/resourceArea.hpp" 31 #include "runtime/java.hpp" 32 #include "runtime/os.hpp" 33 #include "runtime/stubCodeGenerator.hpp" 34 #include "utilities/defaultStream.hpp" 35 #include "utilities/globalDefinitions.hpp" 36 #include "vm_version_ppc.hpp" 37 38 # include <sys/sysinfo.h> 39 40 bool VM_Version::_is_determine_features_test_running = false; 41 uint64_t VM_Version::_dscr_val = 0; 42 43 #define MSG(flag) \ 44 if (flag && !FLAG_IS_DEFAULT(flag)) \ 45 jio_fprintf(defaultStream::error_stream(), \ 46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \ 47 " -XX:+" #flag " will be disabled!\n"); 48 49 void VM_Version::initialize() { 50 51 // Test which instructions are supported and measure cache line size. 52 determine_features(); 53 54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features. 55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) { 56 if (VM_Version::has_lqarx()) { 57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8); 58 } else if (VM_Version::has_popcntw()) { 59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7); 60 } else if (VM_Version::has_cmpb()) { 61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6); 62 } else if (VM_Version::has_popcntb()) { 63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5); 64 } else { 65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0); 66 } 67 } 68 69 bool PowerArchitecturePPC64_ok = false; 70 switch (PowerArchitecturePPC64) { 71 case 8: if (!VM_Version::has_lqarx() ) break; 72 case 7: if (!VM_Version::has_popcntw()) break; 73 case 6: if (!VM_Version::has_cmpb() ) break; 74 case 5: if (!VM_Version::has_popcntb()) break; 75 case 0: PowerArchitecturePPC64_ok = true; break; 76 default: break; 77 } 78 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to " 79 UINTX_FORMAT " on this machine", PowerArchitecturePPC64); 80 81 // Power 8: Configure Data Stream Control Register. 82 if (has_mfdscr()) { 83 config_dscr(); 84 } 85 86 if (!UseSIGTRAP) { 87 MSG(TrapBasedICMissChecks); 88 MSG(TrapBasedNotEntrantChecks); 89 MSG(TrapBasedNullChecks); 90 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false); 91 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false); 92 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false); 93 } 94 95 #ifdef COMPILER2 96 if (!UseSIGTRAP) { 97 MSG(TrapBasedRangeChecks); 98 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false); 99 } 100 101 // On Power6 test for section size. 102 if (PowerArchitecturePPC64 == 6) { 103 determine_section_size(); 104 // TODO: PPC port } else { 105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20; 106 } 107 108 MaxVectorSize = 8; 109 #endif 110 111 // Create and print feature-string. 112 char buf[(num_features+1) * 16]; // Max 16 chars per feature. 113 jio_snprintf(buf, sizeof(buf), 114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s", 115 (has_fsqrt() ? " fsqrt" : ""), 116 (has_isel() ? " isel" : ""), 117 (has_lxarxeh() ? " lxarxeh" : ""), 118 (has_cmpb() ? " cmpb" : ""), 119 //(has_mftgpr()? " mftgpr" : ""), 120 (has_popcntb() ? " popcntb" : ""), 121 (has_popcntw() ? " popcntw" : ""), 122 (has_fcfids() ? " fcfids" : ""), 123 (has_vand() ? " vand" : ""), 124 (has_lqarx() ? " lqarx" : ""), 125 (has_vcipher() ? " aes" : ""), 126 (has_vpmsumb() ? " vpmsumb" : ""), 127 (has_tcheck() ? " tcheck" : ""), 128 (has_mfdscr() ? " mfdscr" : ""), 129 (has_vsx() ? " vsx" : "") 130 // Make sure number of %s matches num_features! 131 ); 132 _features_string = os::strdup(buf); 133 if (Verbose) { 134 print_features(); 135 } 136 137 // PPC64 supports 8-byte compare-exchange operations (see 138 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr) 139 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile). 140 _supports_cx8 = true; 141 142 // Used by C1. 143 _supports_atomic_getset4 = true; 144 _supports_atomic_getadd4 = true; 145 _supports_atomic_getset8 = true; 146 _supports_atomic_getadd8 = true; 147 148 UseSSE = 0; // Only on x86 and x64 149 150 intx cache_line_size = L1_data_cache_line_size(); 151 152 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1; 153 154 if (AllocatePrefetchStyle == 4) { 155 AllocatePrefetchStepSize = cache_line_size; // Need exact value. 156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default. 157 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined? 158 } else { 159 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size; 160 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value. 161 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined? 162 } 163 164 assert(AllocatePrefetchLines > 0, "invalid value"); 165 if (AllocatePrefetchLines < 1) { // Set valid value in product VM. 166 AllocatePrefetchLines = 1; // Conservative value. 167 } 168 169 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) { 170 AllocatePrefetchStyle = 1; // Fall back if inappropriate. 171 } 172 173 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive"); 174 175 // Implementation does not use any of the vector instructions 176 // available with Power8. Their exploitation is still pending. 177 if (!UseCRC32Intrinsics) { 178 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) { 179 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true); 180 } 181 } 182 183 if (UseCRC32CIntrinsics) { 184 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) 185 warning("CRC32C intrinsics are not available on this CPU"); 186 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false); 187 } 188 189 // The AES intrinsic stubs require AES instruction support. 190 #if defined(VM_LITTLE_ENDIAN) 191 if (has_vcipher()) { 192 if (FLAG_IS_DEFAULT(UseAES)) { 193 UseAES = true; 194 } 195 } else if (UseAES) { 196 if (!FLAG_IS_DEFAULT(UseAES)) 197 warning("AES instructions are not available on this CPU"); 198 FLAG_SET_DEFAULT(UseAES, false); 199 } 200 201 if (UseAES && has_vcipher()) { 202 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) { 203 UseAESIntrinsics = true; 204 } 205 } else if (UseAESIntrinsics) { 206 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 207 warning("AES intrinsics are not available on this CPU"); 208 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 209 } 210 211 #else 212 if (UseAES) { 213 warning("AES instructions are not available on this CPU"); 214 FLAG_SET_DEFAULT(UseAES, false); 215 } 216 if (UseAESIntrinsics) { 217 if (!FLAG_IS_DEFAULT(UseAESIntrinsics)) 218 warning("AES intrinsics are not available on this CPU"); 219 FLAG_SET_DEFAULT(UseAESIntrinsics, false); 220 } 221 #endif 222 223 if (UseAESCTRIntrinsics) { 224 warning("AES/CTR intrinsics are not available on this CPU"); 225 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false); 226 } 227 228 if (UseGHASHIntrinsics) { 229 warning("GHASH intrinsics are not available on this CPU"); 230 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false); 231 } 232 233 if (FLAG_IS_DEFAULT(UseFMA)) { 234 FLAG_SET_DEFAULT(UseFMA, true); 235 } 236 237 if (UseSHA) { 238 warning("SHA instructions are not available on this CPU"); 239 FLAG_SET_DEFAULT(UseSHA, false); 240 } 241 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) { 242 warning("SHA intrinsics are not available on this CPU"); 243 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false); 244 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false); 245 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false); 246 } 247 248 if (UseAdler32Intrinsics) { 249 warning("Adler32Intrinsics not available on this CPU."); 250 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false); 251 } 252 253 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) { 254 UseMultiplyToLenIntrinsic = true; 255 } 256 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) { 257 UseMontgomeryMultiplyIntrinsic = true; 258 } 259 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) { 260 UseMontgomerySquareIntrinsic = true; 261 } 262 263 if (UseVectorizedMismatchIntrinsic) { 264 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU."); 265 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false); 266 } 267 268 269 // Adjust RTM (Restricted Transactional Memory) flags. 270 if (UseRTMLocking) { 271 // If CPU or OS are too old: 272 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 273 // setting during arguments processing. See use_biased_locking(). 274 // VM_Version_init() is executed after UseBiasedLocking is used 275 // in Thread::allocate(). 276 if (!has_tcheck()) { 277 vm_exit_during_initialization("RTM instructions are not available on this CPU"); 278 } 279 bool os_too_old = true; 280 #ifdef AIX 281 // Actually, this is supported since AIX 7.1.. Unfortunately, this first 282 // contained bugs, so that it can only be enabled after AIX 7.1.3.30. 283 // The Java property os.version, which is used in RTM tests to decide 284 // whether the feature is available, only knows major and minor versions. 285 // We don't want to change this property, as user code might depend on it. 286 // So the tests can not check on subversion 3.30, and we only enable RTM 287 // with AIX 7.2. 288 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2. 289 os_too_old = false; 290 } 291 #endif 292 #ifdef LINUX 293 // At least Linux kernel 4.2, as the problematic behavior of syscalls 294 // being called in the middle of a transaction has been addressed. 295 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894 296 // in Linux kernel source tree: https://goo.gl/Kc5i7A 297 if (os::Linux::os_version_is_known()) { 298 if (os::Linux::os_version() >= 0x040200) 299 os_too_old = false; 300 } else { 301 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown."); 302 } 303 #endif 304 if (os_too_old) { 305 vm_exit_during_initialization("RTM is not supported on this OS version."); 306 } 307 } 308 309 if (UseRTMLocking) { 310 #if INCLUDE_RTM_OPT 311 if (!UnlockExperimentalVMOptions) { 312 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. " 313 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag."); 314 } else { 315 warning("UseRTMLocking is only available as experimental option on this platform."); 316 } 317 if (!FLAG_IS_CMDLINE(UseRTMLocking)) { 318 // RTM locking should be used only for applications with 319 // high lock contention. For now we do not use it by default. 320 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line"); 321 } 322 if (!is_power_of_2(RTMTotalCountIncrRate)) { 323 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64"); 324 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64); 325 } 326 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) { 327 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50"); 328 FLAG_SET_DEFAULT(RTMAbortRatio, 50); 329 } 330 guarantee(RTMSpinLoopCount > 0, "unsupported"); 331 #else 332 // Only C2 does RTM locking optimization. 333 // Can't continue because UseRTMLocking affects UseBiasedLocking flag 334 // setting during arguments processing. See use_biased_locking(). 335 vm_exit_during_initialization("RTM locking optimization is not supported in this VM"); 336 #endif 337 } else { // !UseRTMLocking 338 if (UseRTMForStackLocks) { 339 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) { 340 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off"); 341 } 342 FLAG_SET_DEFAULT(UseRTMForStackLocks, false); 343 } 344 if (UseRTMDeopt) { 345 FLAG_SET_DEFAULT(UseRTMDeopt, false); 346 } 347 if (PrintPreciseRTMLockingStatistics) { 348 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false); 349 } 350 } 351 352 // This machine allows unaligned memory accesses 353 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) { 354 FLAG_SET_DEFAULT(UseUnalignedAccesses, true); 355 } 356 } 357 358 bool VM_Version::use_biased_locking() { 359 #if INCLUDE_RTM_OPT 360 // RTM locking is most useful when there is high lock contention and 361 // low data contention. With high lock contention the lock is usually 362 // inflated and biased locking is not suitable for that case. 363 // RTM locking code requires that biased locking is off. 364 // Note: we can't switch off UseBiasedLocking in get_processor_features() 365 // because it is used by Thread::allocate() which is called before 366 // VM_Version::initialize(). 367 if (UseRTMLocking && UseBiasedLocking) { 368 if (FLAG_IS_DEFAULT(UseBiasedLocking)) { 369 FLAG_SET_DEFAULT(UseBiasedLocking, false); 370 } else { 371 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." ); 372 UseBiasedLocking = false; 373 } 374 } 375 #endif 376 return UseBiasedLocking; 377 } 378 379 void VM_Version::print_features() { 380 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size()); 381 } 382 383 #ifdef COMPILER2 384 // Determine section size on power6: If section size is 8 instructions, 385 // there should be a difference between the two testloops of ~15 %. If 386 // no difference is detected the section is assumed to be 32 instructions. 387 void VM_Version::determine_section_size() { 388 389 int unroll = 80; 390 391 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord; 392 393 // Allocate space for the code. 394 ResourceMark rm; 395 CodeBuffer cb("detect_section_size", code_size, 0); 396 MacroAssembler* a = new MacroAssembler(&cb); 397 398 uint32_t *code = (uint32_t *)a->pc(); 399 // Emit code. 400 void (*test1)() = (void(*)())(void *)a->function_entry(); 401 402 Label l1; 403 404 a->li(R4, 1); 405 a->sldi(R4, R4, 28); 406 a->b(l1); 407 a->align(CodeEntryAlignment); 408 409 a->bind(l1); 410 411 for (int i = 0; i < unroll; i++) { 412 // Schleife 1 413 // ------- sector 0 ------------ 414 // ;; 0 415 a->nop(); // 1 416 a->fpnop0(); // 2 417 a->fpnop1(); // 3 418 a->addi(R4,R4, -1); // 4 419 420 // ;; 1 421 a->nop(); // 5 422 a->fmr(F6, F6); // 6 423 a->fmr(F7, F7); // 7 424 a->endgroup(); // 8 425 // ------- sector 8 ------------ 426 427 // ;; 2 428 a->nop(); // 9 429 a->nop(); // 10 430 a->fmr(F8, F8); // 11 431 a->fmr(F9, F9); // 12 432 433 // ;; 3 434 a->nop(); // 13 435 a->fmr(F10, F10); // 14 436 a->fmr(F11, F11); // 15 437 a->endgroup(); // 16 438 // -------- sector 16 ------------- 439 440 // ;; 4 441 a->nop(); // 17 442 a->nop(); // 18 443 a->fmr(F15, F15); // 19 444 a->fmr(F16, F16); // 20 445 446 // ;; 5 447 a->nop(); // 21 448 a->fmr(F17, F17); // 22 449 a->fmr(F18, F18); // 23 450 a->endgroup(); // 24 451 // ------- sector 24 ------------ 452 453 // ;; 6 454 a->nop(); // 25 455 a->nop(); // 26 456 a->fmr(F19, F19); // 27 457 a->fmr(F20, F20); // 28 458 459 // ;; 7 460 a->nop(); // 29 461 a->fmr(F21, F21); // 30 462 a->fmr(F22, F22); // 31 463 a->brnop0(); // 32 464 465 // ------- sector 32 ------------ 466 } 467 468 // ;; 8 469 a->cmpdi(CCR0, R4, unroll); // 33 470 a->bge(CCR0, l1); // 34 471 a->blr(); 472 473 // Emit code. 474 void (*test2)() = (void(*)())(void *)a->function_entry(); 475 // uint32_t *code = (uint32_t *)a->pc(); 476 477 Label l2; 478 479 a->li(R4, 1); 480 a->sldi(R4, R4, 28); 481 a->b(l2); 482 a->align(CodeEntryAlignment); 483 484 a->bind(l2); 485 486 for (int i = 0; i < unroll; i++) { 487 // Schleife 2 488 // ------- sector 0 ------------ 489 // ;; 0 490 a->brnop0(); // 1 491 a->nop(); // 2 492 //a->cmpdi(CCR0, R4, unroll); 493 a->fpnop0(); // 3 494 a->fpnop1(); // 4 495 a->addi(R4,R4, -1); // 5 496 497 // ;; 1 498 499 a->nop(); // 6 500 a->fmr(F6, F6); // 7 501 a->fmr(F7, F7); // 8 502 // ------- sector 8 --------------- 503 504 // ;; 2 505 a->endgroup(); // 9 506 507 // ;; 3 508 a->nop(); // 10 509 a->nop(); // 11 510 a->fmr(F8, F8); // 12 511 512 // ;; 4 513 a->fmr(F9, F9); // 13 514 a->nop(); // 14 515 a->fmr(F10, F10); // 15 516 517 // ;; 5 518 a->fmr(F11, F11); // 16 519 // -------- sector 16 ------------- 520 521 // ;; 6 522 a->endgroup(); // 17 523 524 // ;; 7 525 a->nop(); // 18 526 a->nop(); // 19 527 a->fmr(F15, F15); // 20 528 529 // ;; 8 530 a->fmr(F16, F16); // 21 531 a->nop(); // 22 532 a->fmr(F17, F17); // 23 533 534 // ;; 9 535 a->fmr(F18, F18); // 24 536 // -------- sector 24 ------------- 537 538 // ;; 10 539 a->endgroup(); // 25 540 541 // ;; 11 542 a->nop(); // 26 543 a->nop(); // 27 544 a->fmr(F19, F19); // 28 545 546 // ;; 12 547 a->fmr(F20, F20); // 29 548 a->nop(); // 30 549 a->fmr(F21, F21); // 31 550 551 // ;; 13 552 a->fmr(F22, F22); // 32 553 } 554 555 // -------- sector 32 ------------- 556 // ;; 14 557 a->cmpdi(CCR0, R4, unroll); // 33 558 a->bge(CCR0, l2); // 34 559 560 a->blr(); 561 uint32_t *code_end = (uint32_t *)a->pc(); 562 a->flush(); 563 564 double loop1_seconds,loop2_seconds, rel_diff; 565 uint64_t start1, stop1; 566 567 start1 = os::current_thread_cpu_time(false); 568 (*test1)(); 569 stop1 = os::current_thread_cpu_time(false); 570 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0); 571 572 573 start1 = os::current_thread_cpu_time(false); 574 (*test2)(); 575 stop1 = os::current_thread_cpu_time(false); 576 577 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0); 578 579 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100; 580 581 if (PrintAssembly) { 582 ttyLocker ttyl; 583 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 584 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 585 tty->print_cr("Time loop1 :%f", loop1_seconds); 586 tty->print_cr("Time loop2 :%f", loop2_seconds); 587 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff); 588 589 if (rel_diff > 12.0) { 590 tty->print_cr("Section Size 8 Instructions"); 591 } else{ 592 tty->print_cr("Section Size 32 Instructions or Power5"); 593 } 594 } 595 596 #if 0 // TODO: PPC port 597 // Set sector size (if not set explicitly). 598 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) { 599 if (rel_diff > 12.0) { 600 PdScheduling::power6SectorSize = 0x20; 601 } else { 602 PdScheduling::power6SectorSize = 0x80; 603 } 604 } else if (Power6SectorSize128PPC64) { 605 PdScheduling::power6SectorSize = 0x80; 606 } else { 607 PdScheduling::power6SectorSize = 0x20; 608 } 609 #endif 610 if (UsePower6SchedulerPPC64) Unimplemented(); 611 } 612 #endif // COMPILER2 613 614 void VM_Version::determine_features() { 615 #if defined(ABI_ELFv2) 616 // 1 InstWord per call for the blr instruction. 617 const int code_size = (num_features+1+2*1)*BytesPerInstWord; 618 #else 619 // 7 InstWords for each call (function descriptor + blr instruction). 620 const int code_size = (num_features+1+2*7)*BytesPerInstWord; 621 #endif 622 int features = 0; 623 624 // create test area 625 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size). 626 char test_area[BUFFER_SIZE]; 627 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1]; 628 629 // Allocate space for the code. 630 ResourceMark rm; 631 CodeBuffer cb("detect_cpu_features", code_size, 0); 632 MacroAssembler* a = new MacroAssembler(&cb); 633 634 // Must be set to true so we can generate the test code. 635 _features = VM_Version::all_features_m; 636 637 // Emit code. 638 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry(); 639 uint32_t *code = (uint32_t *)a->pc(); 640 // Don't use R0 in ldarx. 641 // Keep R3_ARG1 unmodified, it contains &field (see below). 642 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below). 643 a->fsqrt(F3, F4); // code[0] -> fsqrt_m 644 a->fsqrts(F3, F4); // code[1] -> fsqrts_m 645 a->isel(R7, R5, R6, 0); // code[2] -> isel_m 646 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m 647 a->cmpb(R7, R5, R6); // code[4] -> cmpb 648 a->popcntb(R7, R5); // code[5] -> popcntb 649 a->popcntw(R7, R5); // code[6] -> popcntw 650 a->fcfids(F3, F4); // code[7] -> fcfids 651 a->vand(VR0, VR0, VR0); // code[8] -> vand 652 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16 653 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m 654 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher 655 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb 656 a->tcheck(0); // code[12] -> tcheck 657 a->mfdscr(R0); // code[13] -> mfdscr 658 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx 659 a->blr(); 660 661 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it. 662 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry(); 663 a->dcbz(R3_ARG1); // R3_ARG1 = addr 664 a->blr(); 665 666 uint32_t *code_end = (uint32_t *)a->pc(); 667 a->flush(); 668 _features = VM_Version::unknown_m; 669 670 // Print the detection code. 671 if (PrintAssembly) { 672 ttyLocker ttyl; 673 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code)); 674 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 675 } 676 677 // Measure cache line size. 678 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF. 679 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle. 680 int count = 0; // count zeroed bytes 681 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++; 682 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2"); 683 _L1_data_cache_line_size = count; 684 685 // Execute code. Illegal instructions will be replaced by 0 in the signal handler. 686 VM_Version::_is_determine_features_test_running = true; 687 // We must align the first argument to 16 bytes because of the lqarx check. 688 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0); 689 VM_Version::_is_determine_features_test_running = false; 690 691 // determine which instructions are legal. 692 int feature_cntr = 0; 693 if (code[feature_cntr++]) features |= fsqrt_m; 694 if (code[feature_cntr++]) features |= fsqrts_m; 695 if (code[feature_cntr++]) features |= isel_m; 696 if (code[feature_cntr++]) features |= lxarxeh_m; 697 if (code[feature_cntr++]) features |= cmpb_m; 698 if (code[feature_cntr++]) features |= popcntb_m; 699 if (code[feature_cntr++]) features |= popcntw_m; 700 if (code[feature_cntr++]) features |= fcfids_m; 701 if (code[feature_cntr++]) features |= vand_m; 702 if (code[feature_cntr++]) features |= lqarx_m; 703 if (code[feature_cntr++]) features |= vcipher_m; 704 if (code[feature_cntr++]) features |= vpmsumb_m; 705 if (code[feature_cntr++]) features |= tcheck_m; 706 if (code[feature_cntr++]) features |= mfdscr_m; 707 if (code[feature_cntr++]) features |= vsx_m; 708 709 // Print the detection code. 710 if (PrintAssembly) { 711 ttyLocker ttyl; 712 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code)); 713 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 714 } 715 716 _features = features; 717 } 718 719 // Power 8: Configure Data Stream Control Register. 720 void VM_Version::config_dscr() { 721 // 7 InstWords for each call (function descriptor + blr instruction). 722 const int code_size = (2+2*7)*BytesPerInstWord; 723 724 // Allocate space for the code. 725 ResourceMark rm; 726 CodeBuffer cb("config_dscr", code_size, 0); 727 MacroAssembler* a = new MacroAssembler(&cb); 728 729 // Emit code. 730 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry(); 731 uint32_t *code = (uint32_t *)a->pc(); 732 a->mfdscr(R3); 733 a->blr(); 734 735 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry(); 736 a->mtdscr(R3); 737 a->blr(); 738 739 uint32_t *code_end = (uint32_t *)a->pc(); 740 a->flush(); 741 742 // Print the detection code. 743 if (PrintAssembly) { 744 ttyLocker ttyl; 745 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code)); 746 Disassembler::decode((u_char*)code, (u_char*)code_end, tty); 747 } 748 749 // Apply the configuration if needed. 750 _dscr_val = (*get_dscr)(); 751 if (Verbose) { 752 tty->print_cr("dscr value was 0x%lx" , _dscr_val); 753 } 754 bool change_requested = false; 755 if (DSCR_PPC64 != (uintx)-1) { 756 _dscr_val = DSCR_PPC64; 757 change_requested = true; 758 } 759 if (DSCR_DPFD_PPC64 <= 7) { 760 uint64_t mask = 0x7; 761 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) { 762 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64); 763 change_requested = true; 764 } 765 } 766 if (DSCR_URG_PPC64 <= 7) { 767 uint64_t mask = 0x7 << 6; 768 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) { 769 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6); 770 change_requested = true; 771 } 772 } 773 if (change_requested) { 774 (*set_dscr)(_dscr_val); 775 if (Verbose) { 776 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)()); 777 } 778 } 779 } 780 781 static uint64_t saved_features = 0; 782 783 void VM_Version::allow_all() { 784 saved_features = _features; 785 _features = all_features_m; 786 } 787 788 void VM_Version::revert() { 789 _features = saved_features; 790 }