275
276 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
277 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
278 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
279 }
280
281
282 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
283 // Allocate a new index in table to hold the klass once it's been patched.
284 int index = __ oop_recorder()->allocate_metadata_index(NULL);
285 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
286
287 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
288 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
289 __ load_const(reg, addrlit, R0);
290
291 patching_epilog(patch, lir_patch_normal, reg, info);
292 }
293
294
295 void LIR_Assembler::emit_op3(LIR_Op3* op) {
296 const bool is_int = op->result_opr()->is_single_cpu();
297 Register Rdividend = is_int ? op->in_opr1()->as_register() : op->in_opr1()->as_register_lo();
298 Register Rdivisor = noreg;
299 Register Rscratch = op->in_opr3()->as_register();
300 Register Rresult = is_int ? op->result_opr()->as_register() : op->result_opr()->as_register_lo();
301 long divisor = -1;
302
303 if (op->in_opr2()->is_register()) {
304 Rdivisor = is_int ? op->in_opr2()->as_register() : op->in_opr2()->as_register_lo();
305 } else {
306 divisor = is_int ? op->in_opr2()->as_constant_ptr()->as_jint()
307 : op->in_opr2()->as_constant_ptr()->as_jlong();
308 }
309
310 assert(Rdividend != Rscratch, "");
311 assert(Rdivisor != Rscratch, "");
312 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv");
313
314 if (Rdivisor == noreg) {
315 if (divisor == 1) { // stupid, but can happen
316 if (op->code() == lir_idiv) {
317 __ mr_if_needed(Rresult, Rdividend);
318 } else {
319 __ li(Rresult, 0);
320 }
321
322 } else if (is_power_of_2(divisor)) {
323 // Convert division by a power of two into some shifts and logical operations.
324 int log2 = log2_intptr(divisor);
325
326 // Round towards 0.
327 if (divisor == 2) {
328 if (is_int) {
329 __ srwi(Rscratch, Rdividend, 31);
330 } else {
331 __ srdi(Rscratch, Rdividend, 63);
332 }
333 } else {
334 if (is_int) {
335 __ srawi(Rscratch, Rdividend, 31);
336 } else {
337 __ sradi(Rscratch, Rdividend, 63);
338 }
339 __ clrldi(Rscratch, Rscratch, 64-log2);
340 }
341 __ add(Rscratch, Rdividend, Rscratch);
342
343 if (op->code() == lir_idiv) {
344 if (is_int) {
345 __ srawi(Rresult, Rscratch, log2);
346 } else {
347 __ sradi(Rresult, Rscratch, log2);
348 }
349 } else { // lir_irem
350 __ clrrdi(Rscratch, Rscratch, log2);
351 __ sub(Rresult, Rdividend, Rscratch);
352 }
353
354 } else if (divisor == -1) {
355 if (op->code() == lir_idiv) {
356 __ neg(Rresult, Rdividend);
357 } else {
358 __ li(Rresult, 0);
359 }
360
361 } else {
362 __ load_const_optimized(Rscratch, divisor);
363 if (op->code() == lir_idiv) {
364 if (is_int) {
365 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
366 } else {
367 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
368 }
369 } else {
370 assert(Rscratch != R0, "need both");
371 if (is_int) {
372 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
373 __ mullw(Rscratch, R0, Rscratch);
374 } else {
375 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
376 __ mulld(Rscratch, R0, Rscratch);
377 }
378 __ sub(Rresult, Rdividend, Rscratch);
379 }
380
381 }
382 return;
383 }
384
385 Label regular, done;
386 if (is_int) {
387 __ cmpwi(CCR0, Rdivisor, -1);
388 } else {
389 __ cmpdi(CCR0, Rdivisor, -1);
390 }
391 __ bne(CCR0, regular);
392 if (op->code() == lir_idiv) {
393 __ neg(Rresult, Rdividend);
394 __ b(done);
395 __ bind(regular);
396 if (is_int) {
397 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
398 } else {
399 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
400 }
401 } else { // lir_irem
402 __ li(Rresult, 0);
403 __ b(done);
404 __ bind(regular);
405 if (is_int) {
406 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
407 __ mullw(Rscratch, Rscratch, Rdivisor);
408 } else {
409 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
410 __ mulld(Rscratch, Rscratch, Rdivisor);
411 }
412 __ sub(Rresult, Rdividend, Rscratch);
413 }
414 __ bind(done);
415 }
416
417
418 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
419 #ifdef ASSERT
420 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
421 if (op->block() != NULL) _branch_target_blocks.append(op->block());
422 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
423 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
424 #endif
425
426 Label *L = op->label();
427 if (op->cond() == lir_cond_always) {
428 __ b(*L);
429 } else {
430 Label done;
431 bool is_unordered = false;
432 if (op->code() == lir_cond_float_branch) {
433 assert(op->ublock() != NULL, "must have unordered successor");
434 is_unordered = true;
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275
276 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
277 AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
278 __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
279 }
280
281
282 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
283 // Allocate a new index in table to hold the klass once it's been patched.
284 int index = __ oop_recorder()->allocate_metadata_index(NULL);
285 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
286
287 AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
288 assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
289 __ load_const(reg, addrlit, R0);
290
291 patching_epilog(patch, lir_patch_normal, reg, info);
292 }
293
294
295 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
296 const bool is_int = result->is_single_cpu();
297 Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
298 Register Rdivisor = noreg;
299 Register Rscratch = temp->as_register();
300 Register Rresult = is_int ? result->as_register() : result->as_register_lo();
301 long divisor = -1;
302
303 if (right->is_register()) {
304 Rdivisor = is_int ? right->as_register() : right->as_register_lo();
305 } else {
306 divisor = is_int ? right->as_constant_ptr()->as_jint()
307 : right->as_constant_ptr()->as_jlong();
308 }
309
310 assert(Rdividend != Rscratch, "");
311 assert(Rdivisor != Rscratch, "");
312 assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
313
314 if (Rdivisor == noreg) {
315 if (divisor == 1) { // stupid, but can happen
316 if (code == lir_idiv) {
317 __ mr_if_needed(Rresult, Rdividend);
318 } else {
319 __ li(Rresult, 0);
320 }
321
322 } else if (is_power_of_2(divisor)) {
323 // Convert division by a power of two into some shifts and logical operations.
324 int log2 = log2_intptr(divisor);
325
326 // Round towards 0.
327 if (divisor == 2) {
328 if (is_int) {
329 __ srwi(Rscratch, Rdividend, 31);
330 } else {
331 __ srdi(Rscratch, Rdividend, 63);
332 }
333 } else {
334 if (is_int) {
335 __ srawi(Rscratch, Rdividend, 31);
336 } else {
337 __ sradi(Rscratch, Rdividend, 63);
338 }
339 __ clrldi(Rscratch, Rscratch, 64-log2);
340 }
341 __ add(Rscratch, Rdividend, Rscratch);
342
343 if (code == lir_idiv) {
344 if (is_int) {
345 __ srawi(Rresult, Rscratch, log2);
346 } else {
347 __ sradi(Rresult, Rscratch, log2);
348 }
349 } else { // lir_irem
350 __ clrrdi(Rscratch, Rscratch, log2);
351 __ sub(Rresult, Rdividend, Rscratch);
352 }
353
354 } else if (divisor == -1) {
355 if (code == lir_idiv) {
356 __ neg(Rresult, Rdividend);
357 } else {
358 __ li(Rresult, 0);
359 }
360
361 } else {
362 __ load_const_optimized(Rscratch, divisor);
363 if (code == lir_idiv) {
364 if (is_int) {
365 __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
366 } else {
367 __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
368 }
369 } else {
370 assert(Rscratch != R0, "need both");
371 if (is_int) {
372 __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
373 __ mullw(Rscratch, R0, Rscratch);
374 } else {
375 __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
376 __ mulld(Rscratch, R0, Rscratch);
377 }
378 __ sub(Rresult, Rdividend, Rscratch);
379 }
380
381 }
382 return;
383 }
384
385 Label regular, done;
386 if (is_int) {
387 __ cmpwi(CCR0, Rdivisor, -1);
388 } else {
389 __ cmpdi(CCR0, Rdivisor, -1);
390 }
391 __ bne(CCR0, regular);
392 if (code == lir_idiv) {
393 __ neg(Rresult, Rdividend);
394 __ b(done);
395 __ bind(regular);
396 if (is_int) {
397 __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
398 } else {
399 __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
400 }
401 } else { // lir_irem
402 __ li(Rresult, 0);
403 __ b(done);
404 __ bind(regular);
405 if (is_int) {
406 __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
407 __ mullw(Rscratch, Rscratch, Rdivisor);
408 } else {
409 __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
410 __ mulld(Rscratch, Rscratch, Rdivisor);
411 }
412 __ sub(Rresult, Rdividend, Rscratch);
413 }
414 __ bind(done);
415 }
416
417
418 void LIR_Assembler::emit_op3(LIR_Op3* op) {
419 switch (op->code()) {
420 case lir_idiv:
421 case lir_irem:
422 arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
423 op->result_opr(), op->info());
424 break;
425 case lir_fmad:
426 __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
427 op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
428 break;
429 case lir_fmaf:
430 __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
431 op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
432 break;
433 default: ShouldNotReachHere(); break;
434 }
435 }
436
437
438 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
439 #ifdef ASSERT
440 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
441 if (op->block() != NULL) _branch_target_blocks.append(op->block());
442 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
443 assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
444 #endif
445
446 Label *L = op->label();
447 if (op->cond() == lir_cond_always) {
448 __ b(*L);
449 } else {
450 Label done;
451 bool is_unordered = false;
452 if (op->code() == lir_cond_float_branch) {
453 assert(op->ublock() != NULL, "must have unordered successor");
454 is_unordered = true;
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