9552 ins_cost(0);
9553
9554 format %{ " -- \t// RoundDouble not needed - empty" %}
9555 size(0);
9556 // PPC results are already "rounded" (i.e., normal-format IEEE).
9557 ins_encode( /*empty*/ );
9558 ins_pipe(pipe_class_default);
9559 %}
9560
9561 instruct roundFloat_nop(regF dst) %{
9562 match(Set dst (RoundFloat dst));
9563 ins_cost(0);
9564
9565 format %{ " -- \t// RoundFloat not needed - empty" %}
9566 size(0);
9567 // PPC results are already "rounded" (i.e., normal-format IEEE).
9568 ins_encode( /*empty*/ );
9569 ins_pipe(pipe_class_default);
9570 %}
9571
9572 //----------Logical Instructions-----------------------------------------------
9573
9574 // And Instructions
9575
9576 // Register And
9577 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9578 match(Set dst (AndI src1 src2));
9579 format %{ "AND $dst, $src1, $src2" %}
9580 size(4);
9581 ins_encode %{
9582 // TODO: PPC port $archOpcode(ppc64Opcode_and);
9583 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9584 %}
9585 ins_pipe(pipe_class_default);
9586 %}
9587
9588 // Left shifted Immediate And
9589 instruct andI_reg_immIhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2, flagsRegCR0 cr0) %{
9590 match(Set dst (AndI src1 src2));
9591 effect(KILL cr0);
|
9552 ins_cost(0);
9553
9554 format %{ " -- \t// RoundDouble not needed - empty" %}
9555 size(0);
9556 // PPC results are already "rounded" (i.e., normal-format IEEE).
9557 ins_encode( /*empty*/ );
9558 ins_pipe(pipe_class_default);
9559 %}
9560
9561 instruct roundFloat_nop(regF dst) %{
9562 match(Set dst (RoundFloat dst));
9563 ins_cost(0);
9564
9565 format %{ " -- \t// RoundFloat not needed - empty" %}
9566 size(0);
9567 // PPC results are already "rounded" (i.e., normal-format IEEE).
9568 ins_encode( /*empty*/ );
9569 ins_pipe(pipe_class_default);
9570 %}
9571
9572
9573 // Multiply-Accumulate
9574 // src1 * src2 + src3
9575 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9576 match(Set dst (FmaF src3 (Binary src1 src2)));
9577
9578 format %{ "FMADDS $dst, $src1, $src2, $src3" %}
9579 size(4);
9580 ins_encode %{
9581 // TODO: PPC port $archOpcode(ppc64Opcode_fmadds);
9582 __ fmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9583 %}
9584 ins_pipe(pipe_class_default);
9585 %}
9586
9587 // src1 * src2 + src3
9588 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9589 match(Set dst (FmaD src3 (Binary src1 src2)));
9590
9591 format %{ "FMADD $dst, $src1, $src2, $src3" %}
9592 size(4);
9593 ins_encode %{
9594 // TODO: PPC port $archOpcode(ppc64Opcode_fmadd);
9595 __ fmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9596 %}
9597 ins_pipe(pipe_class_default);
9598 %}
9599
9600 // -src1 * src2 + src3 = -(src1*src2-src3)
9601 instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9602 match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
9603 match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
9604
9605 format %{ "FNMSUBS $dst, $src1, $src2, $src3" %}
9606 size(4);
9607 ins_encode %{
9608 // TODO: PPC port $archOpcode(ppc64Opcode_fnmsubs);
9609 __ fnmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9610 %}
9611 ins_pipe(pipe_class_default);
9612 %}
9613
9614 // -src1 * src2 + src3 = -(src1*src2-src3)
9615 instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9616 match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
9617 match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
9618
9619 format %{ "FNMSUB $dst, $src1, $src2, $src3" %}
9620 size(4);
9621 ins_encode %{
9622 // TODO: PPC port $archOpcode(ppc64Opcode_fnmsub);
9623 __ fnmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9624 %}
9625 ins_pipe(pipe_class_default);
9626 %}
9627
9628 // -src1 * src2 - src3 = -(src1*src2+src3)
9629 instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9630 match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
9631 match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
9632
9633 format %{ "FNMADDS $dst, $src1, $src2, $src3" %}
9634 size(4);
9635 ins_encode %{
9636 // TODO: PPC port $archOpcode(ppc64Opcode_fnmadds);
9637 __ fnmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9638 %}
9639 ins_pipe(pipe_class_default);
9640 %}
9641
9642 // -src1 * src2 - src3 = -(src1*src2+src3)
9643 instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9644 match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
9645 match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
9646
9647 format %{ "FNMADD $dst, $src1, $src2, $src3" %}
9648 size(4);
9649 ins_encode %{
9650 // TODO: PPC port $archOpcode(ppc64Opcode_fnmadd);
9651 __ fnmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9652 %}
9653 ins_pipe(pipe_class_default);
9654 %}
9655
9656 // src1 * src2 - src3
9657 instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9658 match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
9659
9660 format %{ "FMSUBS $dst, $src1, $src2, $src3" %}
9661 size(4);
9662 ins_encode %{
9663 // TODO: PPC port $archOpcode(ppc64Opcode_fmsubs);
9664 __ fmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9665 %}
9666 ins_pipe(pipe_class_default);
9667 %}
9668
9669 // src1 * src2 - src3
9670 instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9671 match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
9672
9673 format %{ "FMSUB $dst, $src1, $src2, $src3" %}
9674 size(4);
9675 ins_encode %{
9676 // TODO: PPC port $archOpcode(ppc64Opcode_fmsub);
9677 __ fmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9678 %}
9679 ins_pipe(pipe_class_default);
9680 %}
9681
9682
9683 //----------Logical Instructions-----------------------------------------------
9684
9685 // And Instructions
9686
9687 // Register And
9688 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9689 match(Set dst (AndI src1 src2));
9690 format %{ "AND $dst, $src1, $src2" %}
9691 size(4);
9692 ins_encode %{
9693 // TODO: PPC port $archOpcode(ppc64Opcode_and);
9694 __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9695 %}
9696 ins_pipe(pipe_class_default);
9697 %}
9698
9699 // Left shifted Immediate And
9700 instruct andI_reg_immIhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2, flagsRegCR0 cr0) %{
9701 match(Set dst (AndI src1 src2));
9702 effect(KILL cr0);
|