1 /*
2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "utilities/defaultStream.hpp"
35 #include "utilities/globalDefinitions.hpp"
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 bool VM_Version::_is_determine_features_test_running = false;
41 uint64_t VM_Version::_dscr_val = 0;
42
43 #define MSG(flag) \
44 if (flag && !FLAG_IS_DEFAULT(flag)) \
45 jio_fprintf(defaultStream::error_stream(), \
46 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
47 " -XX:+" #flag " will be disabled!\n");
48
49 void VM_Version::initialize() {
50
51 // Test which instructions are supported and measure cache line size.
52 determine_features();
53
54 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
55 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
56 if (VM_Version::has_lqarx()) {
57 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
58 } else if (VM_Version::has_popcntw()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
60 } else if (VM_Version::has_cmpb()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
62 } else if (VM_Version::has_popcntb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
64 } else {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
66 }
67 }
68
69 bool PowerArchitecturePPC64_ok = false;
70 switch (PowerArchitecturePPC64) {
71 case 8: if (!VM_Version::has_lqarx() ) break;
72 case 7: if (!VM_Version::has_popcntw()) break;
73 case 6: if (!VM_Version::has_cmpb() ) break;
74 case 5: if (!VM_Version::has_popcntb()) break;
75 case 0: PowerArchitecturePPC64_ok = true; break;
76 default: break;
77 }
78 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
79 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
80
81 // Power 8: Configure Data Stream Control Register.
82 if (has_mfdscr()) {
83 config_dscr();
84 }
85
86 if (!UseSIGTRAP) {
87 MSG(TrapBasedICMissChecks);
88 MSG(TrapBasedNotEntrantChecks);
89 MSG(TrapBasedNullChecks);
90 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
91 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
92 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
93 }
94
95 #ifdef COMPILER2
96 if (!UseSIGTRAP) {
97 MSG(TrapBasedRangeChecks);
98 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
99 }
100
101 // On Power6 test for section size.
102 if (PowerArchitecturePPC64 == 6) {
103 determine_section_size();
104 // TODO: PPC port } else {
105 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
106 }
107
108 MaxVectorSize = 8;
109 #endif
110
111 // Create and print feature-string.
112 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
113 jio_snprintf(buf, sizeof(buf),
114 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
115 (has_fsqrt() ? " fsqrt" : ""),
116 (has_isel() ? " isel" : ""),
117 (has_lxarxeh() ? " lxarxeh" : ""),
118 (has_cmpb() ? " cmpb" : ""),
119 //(has_mftgpr()? " mftgpr" : ""),
120 (has_popcntb() ? " popcntb" : ""),
121 (has_popcntw() ? " popcntw" : ""),
122 (has_fcfids() ? " fcfids" : ""),
123 (has_vand() ? " vand" : ""),
124 (has_lqarx() ? " lqarx" : ""),
125 (has_vcipher() ? " aes" : ""),
126 (has_vpmsumb() ? " vpmsumb" : ""),
127 (has_tcheck() ? " tcheck" : ""),
128 (has_mfdscr() ? " mfdscr" : ""),
129 (has_vsx() ? " vsx" : "")
130 // Make sure number of %s matches num_features!
131 );
132 _features_string = os::strdup(buf);
133 if (Verbose) {
134 print_features();
135 }
136
137 // PPC64 supports 8-byte compare-exchange operations (see
138 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
139 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
140 _supports_cx8 = true;
141
142 // Used by C1.
143 _supports_atomic_getset4 = true;
144 _supports_atomic_getadd4 = true;
145 _supports_atomic_getset8 = true;
146 _supports_atomic_getadd8 = true;
147
148 UseSSE = 0; // Only on x86 and x64
149
150 intx cache_line_size = L1_data_cache_line_size();
151
152 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
153
154 if (AllocatePrefetchStyle == 4) {
155 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
157 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
158 } else {
159 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
160 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
161 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
162 }
163
164 assert(AllocatePrefetchLines > 0, "invalid value");
165 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
166 AllocatePrefetchLines = 1; // Conservative value.
167 }
168
169 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
170 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
171 }
172
173 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
174
175 // Implementation does not use any of the vector instructions
176 // available with Power8. Their exploitation is still pending.
177 if (!UseCRC32Intrinsics) {
178 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
179 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
180 }
181 }
182
183 if (UseCRC32CIntrinsics) {
184 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
185 warning("CRC32C intrinsics are not available on this CPU");
186 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
187 }
188
189 // The AES intrinsic stubs require AES instruction support.
190 #if defined(VM_LITTLE_ENDIAN)
191 if (has_vcipher()) {
192 if (FLAG_IS_DEFAULT(UseAES)) {
193 UseAES = true;
194 }
195 } else if (UseAES) {
196 if (!FLAG_IS_DEFAULT(UseAES))
197 warning("AES instructions are not available on this CPU");
198 FLAG_SET_DEFAULT(UseAES, false);
199 }
200
201 if (UseAES && has_vcipher()) {
202 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
203 UseAESIntrinsics = true;
204 }
205 } else if (UseAESIntrinsics) {
206 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
207 warning("AES intrinsics are not available on this CPU");
208 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
209 }
210
211 #else
212 if (UseAES) {
213 warning("AES instructions are not available on this CPU");
214 FLAG_SET_DEFAULT(UseAES, false);
215 }
216 if (UseAESIntrinsics) {
217 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
218 warning("AES intrinsics are not available on this CPU");
219 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
220 }
221 #endif
222
223 if (UseAESCTRIntrinsics) {
224 warning("AES/CTR intrinsics are not available on this CPU");
225 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
226 }
227
228 if (UseGHASHIntrinsics) {
229 warning("GHASH intrinsics are not available on this CPU");
230 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
231 }
232
233 if (UseFMA) {
234 warning("FMA instructions are not available on this CPU");
235 FLAG_SET_DEFAULT(UseFMA, false);
236 }
237
238 if (UseSHA) {
239 warning("SHA instructions are not available on this CPU");
240 FLAG_SET_DEFAULT(UseSHA, false);
241 }
242 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
243 warning("SHA intrinsics are not available on this CPU");
244 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
245 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
246 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
247 }
248
249 if (UseAdler32Intrinsics) {
250 warning("Adler32Intrinsics not available on this CPU.");
251 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
252 }
253
254 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
255 UseMultiplyToLenIntrinsic = true;
256 }
257 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
258 UseMontgomeryMultiplyIntrinsic = true;
259 }
260 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
261 UseMontgomerySquareIntrinsic = true;
262 }
263
264 if (UseVectorizedMismatchIntrinsic) {
265 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
266 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
267 }
268
269
270 // Adjust RTM (Restricted Transactional Memory) flags.
271 if (UseRTMLocking) {
272 // If CPU or OS are too old:
273 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
274 // setting during arguments processing. See use_biased_locking().
275 // VM_Version_init() is executed after UseBiasedLocking is used
276 // in Thread::allocate().
277 if (!has_tcheck()) {
278 vm_exit_during_initialization("RTM instructions are not available on this CPU");
279 }
280 bool os_too_old = true;
281 #ifdef AIX
282 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
283 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
284 // The Java property os.version, which is used in RTM tests to decide
285 // whether the feature is available, only knows major and minor versions.
286 // We don't want to change this property, as user code might depend on it.
287 // So the tests can not check on subversion 3.30, and we only enable RTM
288 // with AIX 7.2.
289 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
290 os_too_old = false;
291 }
292 #endif
293 #ifdef LINUX
294 // At least Linux kernel 4.2, as the problematic behavior of syscalls
295 // being called in the middle of a transaction has been addressed.
296 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894
297 // in Linux kernel source tree: https://goo.gl/Kc5i7A
298 if (os::Linux::os_version_is_known()) {
299 if (os::Linux::os_version() >= 0x040200)
300 os_too_old = false;
301 } else {
302 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown.");
303 }
304 #endif
305 if (os_too_old) {
306 vm_exit_during_initialization("RTM is not supported on this OS version.");
307 }
308 }
309
310 if (UseRTMLocking) {
311 #if INCLUDE_RTM_OPT
312 if (!UnlockExperimentalVMOptions) {
313 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
314 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
315 } else {
316 warning("UseRTMLocking is only available as experimental option on this platform.");
317 }
318 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
319 // RTM locking should be used only for applications with
320 // high lock contention. For now we do not use it by default.
321 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
322 }
323 if (!is_power_of_2(RTMTotalCountIncrRate)) {
324 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
325 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
326 }
327 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
328 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
329 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
330 }
331 guarantee(RTMSpinLoopCount > 0, "unsupported");
332 #else
333 // Only C2 does RTM locking optimization.
334 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
335 // setting during arguments processing. See use_biased_locking().
336 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
337 #endif
338 } else { // !UseRTMLocking
339 if (UseRTMForStackLocks) {
340 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
341 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
342 }
343 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
344 }
345 if (UseRTMDeopt) {
346 FLAG_SET_DEFAULT(UseRTMDeopt, false);
347 }
348 if (PrintPreciseRTMLockingStatistics) {
349 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
350 }
351 }
352
353 // This machine allows unaligned memory accesses
354 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
355 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
356 }
357 }
358
359 bool VM_Version::use_biased_locking() {
360 #if INCLUDE_RTM_OPT
361 // RTM locking is most useful when there is high lock contention and
362 // low data contention. With high lock contention the lock is usually
363 // inflated and biased locking is not suitable for that case.
364 // RTM locking code requires that biased locking is off.
365 // Note: we can't switch off UseBiasedLocking in get_processor_features()
366 // because it is used by Thread::allocate() which is called before
367 // VM_Version::initialize().
368 if (UseRTMLocking && UseBiasedLocking) {
369 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
370 FLAG_SET_DEFAULT(UseBiasedLocking, false);
371 } else {
372 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
373 UseBiasedLocking = false;
374 }
375 }
376 #endif
377 return UseBiasedLocking;
378 }
379
380 void VM_Version::print_features() {
381 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
382 }
383
384 #ifdef COMPILER2
385 // Determine section size on power6: If section size is 8 instructions,
386 // there should be a difference between the two testloops of ~15 %. If
387 // no difference is detected the section is assumed to be 32 instructions.
388 void VM_Version::determine_section_size() {
389
390 int unroll = 80;
391
392 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
393
394 // Allocate space for the code.
395 ResourceMark rm;
396 CodeBuffer cb("detect_section_size", code_size, 0);
397 MacroAssembler* a = new MacroAssembler(&cb);
398
399 uint32_t *code = (uint32_t *)a->pc();
400 // Emit code.
401 void (*test1)() = (void(*)())(void *)a->function_entry();
402
403 Label l1;
404
405 a->li(R4, 1);
406 a->sldi(R4, R4, 28);
407 a->b(l1);
408 a->align(CodeEntryAlignment);
409
410 a->bind(l1);
411
412 for (int i = 0; i < unroll; i++) {
413 // Schleife 1
414 // ------- sector 0 ------------
415 // ;; 0
416 a->nop(); // 1
417 a->fpnop0(); // 2
418 a->fpnop1(); // 3
419 a->addi(R4,R4, -1); // 4
420
421 // ;; 1
422 a->nop(); // 5
423 a->fmr(F6, F6); // 6
424 a->fmr(F7, F7); // 7
425 a->endgroup(); // 8
426 // ------- sector 8 ------------
427
428 // ;; 2
429 a->nop(); // 9
430 a->nop(); // 10
431 a->fmr(F8, F8); // 11
432 a->fmr(F9, F9); // 12
433
434 // ;; 3
435 a->nop(); // 13
436 a->fmr(F10, F10); // 14
437 a->fmr(F11, F11); // 15
438 a->endgroup(); // 16
439 // -------- sector 16 -------------
440
441 // ;; 4
442 a->nop(); // 17
443 a->nop(); // 18
444 a->fmr(F15, F15); // 19
445 a->fmr(F16, F16); // 20
446
447 // ;; 5
448 a->nop(); // 21
449 a->fmr(F17, F17); // 22
450 a->fmr(F18, F18); // 23
451 a->endgroup(); // 24
452 // ------- sector 24 ------------
453
454 // ;; 6
455 a->nop(); // 25
456 a->nop(); // 26
457 a->fmr(F19, F19); // 27
458 a->fmr(F20, F20); // 28
459
460 // ;; 7
461 a->nop(); // 29
462 a->fmr(F21, F21); // 30
463 a->fmr(F22, F22); // 31
464 a->brnop0(); // 32
465
466 // ------- sector 32 ------------
467 }
468
469 // ;; 8
470 a->cmpdi(CCR0, R4, unroll); // 33
471 a->bge(CCR0, l1); // 34
472 a->blr();
473
474 // Emit code.
475 void (*test2)() = (void(*)())(void *)a->function_entry();
476 // uint32_t *code = (uint32_t *)a->pc();
477
478 Label l2;
479
480 a->li(R4, 1);
481 a->sldi(R4, R4, 28);
482 a->b(l2);
483 a->align(CodeEntryAlignment);
484
485 a->bind(l2);
486
487 for (int i = 0; i < unroll; i++) {
488 // Schleife 2
489 // ------- sector 0 ------------
490 // ;; 0
491 a->brnop0(); // 1
492 a->nop(); // 2
493 //a->cmpdi(CCR0, R4, unroll);
494 a->fpnop0(); // 3
495 a->fpnop1(); // 4
496 a->addi(R4,R4, -1); // 5
497
498 // ;; 1
499
500 a->nop(); // 6
501 a->fmr(F6, F6); // 7
502 a->fmr(F7, F7); // 8
503 // ------- sector 8 ---------------
504
505 // ;; 2
506 a->endgroup(); // 9
507
508 // ;; 3
509 a->nop(); // 10
510 a->nop(); // 11
511 a->fmr(F8, F8); // 12
512
513 // ;; 4
514 a->fmr(F9, F9); // 13
515 a->nop(); // 14
516 a->fmr(F10, F10); // 15
517
518 // ;; 5
519 a->fmr(F11, F11); // 16
520 // -------- sector 16 -------------
521
522 // ;; 6
523 a->endgroup(); // 17
524
525 // ;; 7
526 a->nop(); // 18
527 a->nop(); // 19
528 a->fmr(F15, F15); // 20
529
530 // ;; 8
531 a->fmr(F16, F16); // 21
532 a->nop(); // 22
533 a->fmr(F17, F17); // 23
534
535 // ;; 9
536 a->fmr(F18, F18); // 24
537 // -------- sector 24 -------------
538
539 // ;; 10
540 a->endgroup(); // 25
541
542 // ;; 11
543 a->nop(); // 26
544 a->nop(); // 27
545 a->fmr(F19, F19); // 28
546
547 // ;; 12
548 a->fmr(F20, F20); // 29
549 a->nop(); // 30
550 a->fmr(F21, F21); // 31
551
552 // ;; 13
553 a->fmr(F22, F22); // 32
554 }
555
556 // -------- sector 32 -------------
557 // ;; 14
558 a->cmpdi(CCR0, R4, unroll); // 33
559 a->bge(CCR0, l2); // 34
560
561 a->blr();
562 uint32_t *code_end = (uint32_t *)a->pc();
563 a->flush();
564
565 double loop1_seconds,loop2_seconds, rel_diff;
566 uint64_t start1, stop1;
567
568 start1 = os::current_thread_cpu_time(false);
569 (*test1)();
570 stop1 = os::current_thread_cpu_time(false);
571 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
572
573
574 start1 = os::current_thread_cpu_time(false);
575 (*test2)();
576 stop1 = os::current_thread_cpu_time(false);
577
578 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
579
580 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
581
582 if (PrintAssembly) {
583 ttyLocker ttyl;
584 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
585 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
586 tty->print_cr("Time loop1 :%f", loop1_seconds);
587 tty->print_cr("Time loop2 :%f", loop2_seconds);
588 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
589
590 if (rel_diff > 12.0) {
591 tty->print_cr("Section Size 8 Instructions");
592 } else{
593 tty->print_cr("Section Size 32 Instructions or Power5");
594 }
595 }
596
597 #if 0 // TODO: PPC port
598 // Set sector size (if not set explicitly).
599 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
600 if (rel_diff > 12.0) {
601 PdScheduling::power6SectorSize = 0x20;
602 } else {
603 PdScheduling::power6SectorSize = 0x80;
604 }
605 } else if (Power6SectorSize128PPC64) {
606 PdScheduling::power6SectorSize = 0x80;
607 } else {
608 PdScheduling::power6SectorSize = 0x20;
609 }
610 #endif
611 if (UsePower6SchedulerPPC64) Unimplemented();
612 }
613 #endif // COMPILER2
614
615 void VM_Version::determine_features() {
616 #if defined(ABI_ELFv2)
617 // 1 InstWord per call for the blr instruction.
618 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
619 #else
620 // 7 InstWords for each call (function descriptor + blr instruction).
621 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
622 #endif
623 int features = 0;
624
625 // create test area
626 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
627 char test_area[BUFFER_SIZE];
628 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
629
630 // Allocate space for the code.
631 ResourceMark rm;
632 CodeBuffer cb("detect_cpu_features", code_size, 0);
633 MacroAssembler* a = new MacroAssembler(&cb);
634
635 // Must be set to true so we can generate the test code.
636 _features = VM_Version::all_features_m;
637
638 // Emit code.
639 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
640 uint32_t *code = (uint32_t *)a->pc();
641 // Don't use R0 in ldarx.
642 // Keep R3_ARG1 unmodified, it contains &field (see below).
643 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
644 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
645 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
646 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
647 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
648 a->cmpb(R7, R5, R6); // code[4] -> cmpb
649 a->popcntb(R7, R5); // code[5] -> popcntb
650 a->popcntw(R7, R5); // code[6] -> popcntw
651 a->fcfids(F3, F4); // code[7] -> fcfids
652 a->vand(VR0, VR0, VR0); // code[8] -> vand
653 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
654 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
655 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
656 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
657 a->tcheck(0); // code[12] -> tcheck
658 a->mfdscr(R0); // code[13] -> mfdscr
659 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx
660 a->blr();
661
662 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
663 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
664 a->dcbz(R3_ARG1); // R3_ARG1 = addr
665 a->blr();
666
667 uint32_t *code_end = (uint32_t *)a->pc();
668 a->flush();
669 _features = VM_Version::unknown_m;
670
671 // Print the detection code.
672 if (PrintAssembly) {
673 ttyLocker ttyl;
674 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
675 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
676 }
677
678 // Measure cache line size.
679 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
680 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
681 int count = 0; // count zeroed bytes
682 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
683 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
684 _L1_data_cache_line_size = count;
685
686 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
687 VM_Version::_is_determine_features_test_running = true;
688 // We must align the first argument to 16 bytes because of the lqarx check.
689 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
690 VM_Version::_is_determine_features_test_running = false;
691
692 // determine which instructions are legal.
693 int feature_cntr = 0;
694 if (code[feature_cntr++]) features |= fsqrt_m;
695 if (code[feature_cntr++]) features |= fsqrts_m;
696 if (code[feature_cntr++]) features |= isel_m;
697 if (code[feature_cntr++]) features |= lxarxeh_m;
698 if (code[feature_cntr++]) features |= cmpb_m;
699 if (code[feature_cntr++]) features |= popcntb_m;
700 if (code[feature_cntr++]) features |= popcntw_m;
701 if (code[feature_cntr++]) features |= fcfids_m;
702 if (code[feature_cntr++]) features |= vand_m;
703 if (code[feature_cntr++]) features |= lqarx_m;
704 if (code[feature_cntr++]) features |= vcipher_m;
705 if (code[feature_cntr++]) features |= vpmsumb_m;
706 if (code[feature_cntr++]) features |= tcheck_m;
707 if (code[feature_cntr++]) features |= mfdscr_m;
708 if (code[feature_cntr++]) features |= vsx_m;
709
710 // Print the detection code.
711 if (PrintAssembly) {
712 ttyLocker ttyl;
713 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
714 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
715 }
716
717 _features = features;
718 }
719
720 // Power 8: Configure Data Stream Control Register.
721 void VM_Version::config_dscr() {
722 // 7 InstWords for each call (function descriptor + blr instruction).
723 const int code_size = (2+2*7)*BytesPerInstWord;
724
725 // Allocate space for the code.
726 ResourceMark rm;
727 CodeBuffer cb("config_dscr", code_size, 0);
728 MacroAssembler* a = new MacroAssembler(&cb);
729
730 // Emit code.
731 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
732 uint32_t *code = (uint32_t *)a->pc();
733 a->mfdscr(R3);
734 a->blr();
735
736 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
737 a->mtdscr(R3);
738 a->blr();
739
740 uint32_t *code_end = (uint32_t *)a->pc();
741 a->flush();
742
743 // Print the detection code.
744 if (PrintAssembly) {
745 ttyLocker ttyl;
746 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
747 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
748 }
749
750 // Apply the configuration if needed.
751 _dscr_val = (*get_dscr)();
752 if (Verbose) {
753 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
754 }
755 bool change_requested = false;
756 if (DSCR_PPC64 != (uintx)-1) {
757 _dscr_val = DSCR_PPC64;
758 change_requested = true;
759 }
760 if (DSCR_DPFD_PPC64 <= 7) {
761 uint64_t mask = 0x7;
762 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
763 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
764 change_requested = true;
765 }
766 }
767 if (DSCR_URG_PPC64 <= 7) {
768 uint64_t mask = 0x7 << 6;
769 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
770 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
771 change_requested = true;
772 }
773 }
774 if (change_requested) {
775 (*set_dscr)(_dscr_val);
776 if (Verbose) {
777 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
778 }
779 }
780 }
781
782 static uint64_t saved_features = 0;
783
784 void VM_Version::allow_all() {
785 saved_features = _features;
786 _features = all_features_m;
787 }
788
789 void VM_Version::revert() {
790 _features = saved_features;
791 }