1 /*
2 * Copyright (c) 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_S390_VM_ASSEMBLER_S390_HPP
27 #define CPU_S390_VM_ASSEMBLER_S390_HPP
28
29 #undef LUCY_DBG
30
31 #define NearLabel Label
32
33 // Immediate is an abstraction to represent the various immediate
34 // operands which exist on z/Architecture. Neither this class nor
35 // instances hereof have an own state. It consists of methods only.
36 class Immediate VALUE_OBJ_CLASS_SPEC {
37
38 public:
39 static bool is_simm(int64_t x, unsigned int nbits) {
40 // nbits < 2 --> false
41 // nbits >= 64 --> true
42 assert(2 <= nbits && nbits < 64, "Don't call, use statically known result.");
43 const int64_t min = -(1L << (nbits-1));
44 const int64_t maxplus1 = (1L << (nbits-1));
45 return min <= x && x < maxplus1;
46 }
47 static bool is_simm32(int64_t x) {
48 return is_simm(x, 32);
49 }
50 static bool is_simm20(int64_t x) {
51 return is_simm(x, 20);
52 }
53 static bool is_simm16(int64_t x) {
54 return is_simm(x, 16);
55 }
56 static bool is_simm8(int64_t x) {
57 return is_simm(x, 8);
58 }
59
60 // Test if x is within signed immediate range for nbits.
61 static bool is_uimm(int64_t x, unsigned int nbits) {
62 // nbits == 0 --> false
63 // nbits >= 64 --> true
64 assert(1 <= nbits && nbits < 64, "don't call, use statically known result");
65 const uint64_t xu = (unsigned long)x;
66 const uint64_t maxplus1 = 1UL << nbits;
67 return xu < maxplus1; // Unsigned comparison. Negative inputs appear to be very large.
68 }
69 static bool is_uimm32(int64_t x) {
70 return is_uimm(x, 32);
71 }
72 static bool is_uimm16(int64_t x) {
73 return is_uimm(x, 16);
74 }
75 static bool is_uimm12(int64_t x) {
76 return is_uimm(x, 12);
77 }
78 static bool is_uimm8(int64_t x) {
79 return is_uimm(x, 8);
80 }
81 };
82
83 // Displacement is an abstraction to represent the various
84 // displacements which exist with addresses on z/ArchiTecture.
85 // Neither this class nor instances hereof have an own state. It
86 // consists of methods only.
87 class Displacement VALUE_OBJ_CLASS_SPEC {
88
89 public: // These tests are used outside the (Macro)Assembler world, e.g. in ad-file.
90
91 static bool is_longDisp(int64_t x) { // Fits in a 20-bit displacement field.
92 return Immediate::is_simm20(x);
93 }
94 static bool is_shortDisp(int64_t x) { // Fits in a 12-bit displacement field.
95 return Immediate::is_uimm12(x);
96 }
97 static bool is_validDisp(int64_t x) { // Is a valid displacement, regardless of length constraints.
98 return is_longDisp(x);
99 }
100 };
101
102 // RelAddr is an abstraction to represent relative addresses in the
103 // form they are used on z/Architecture for instructions which access
104 // their operand with pc-relative addresses. Neither this class nor
105 // instances hereof have an own state. It consists of methods only.
106 class RelAddr VALUE_OBJ_CLASS_SPEC {
107
108 private: // No public use at all. Solely for (Macro)Assembler.
109
110 static bool is_in_range_of_RelAddr(address target, address pc, bool shortForm) {
111 // Guard against illegal branch targets, e.g. -1. Occurrences in
112 // CompiledStaticCall and ad-file. Do not assert (it's a test
113 // function!). Just return false in case of illegal operands.
114 if ((((uint64_t)target) & 0x0001L) != 0) return false;
115 if ((((uint64_t)pc) & 0x0001L) != 0) return false;
116
117 if (shortForm) {
118 return Immediate::is_simm((int64_t)(target-pc), 17); // Relative short addresses can reach +/- 2**16 bytes.
119 } else {
120 return Immediate::is_simm((int64_t)(target-pc), 33); // Relative long addresses can reach +/- 2**32 bytes.
121 }
122 }
123
124 static bool is_in_range_of_RelAddr16(address target, address pc) {
125 return is_in_range_of_RelAddr(target, pc, true);
126 }
127 static bool is_in_range_of_RelAddr16(ptrdiff_t distance) {
128 return is_in_range_of_RelAddr((address)distance, 0, true);
129 }
130
131 static bool is_in_range_of_RelAddr32(address target, address pc) {
132 return is_in_range_of_RelAddr(target, pc, false);
133 }
134 static bool is_in_range_of_RelAddr32(ptrdiff_t distance) {
135 return is_in_range_of_RelAddr((address)distance, 0, false);
136 }
137
138 static int pcrel_off(address target, address pc, bool shortForm) {
139 assert(((uint64_t)target & 0x0001L) == 0, "target of a relative address must be aligned");
140 assert(((uint64_t)pc & 0x0001L) == 0, "origin of a relative address must be aligned");
141
142 if ((target == NULL) || (target == pc)) {
143 return 0; // Yet unknown branch destination.
144 } else {
145 guarantee(is_in_range_of_RelAddr(target, pc, shortForm), "target not within reach");
146 return (int)((target - pc)>>1);
147 }
148 }
149
150 static int pcrel_off16(address target, address pc) {
151 return pcrel_off(target, pc, true);
152 }
153 static int pcrel_off16(ptrdiff_t distance) {
154 return pcrel_off((address)distance, 0, true);
155 }
156
157 static int pcrel_off32(address target, address pc) {
158 return pcrel_off(target, pc, false);
159 }
160 static int pcrel_off32(ptrdiff_t distance) {
161 return pcrel_off((address)distance, 0, false);
162 }
163
164 static ptrdiff_t inv_pcrel_off16(int offset) {
165 return ((ptrdiff_t)offset)<<1;
166 }
167
168 static ptrdiff_t inv_pcrel_off32(int offset) {
169 return ((ptrdiff_t)offset)<<1;
170 }
171
172 friend class Assembler;
173 friend class MacroAssembler;
174 friend class NativeGeneralJump;
175 };
176
177 // Address is an abstraction used to represent a memory location
178 // as passed to Z assembler instructions.
179 //
180 // Note: A register location is represented via a Register, not
181 // via an address for efficiency & simplicity reasons.
182 class Address VALUE_OBJ_CLASS_SPEC {
183 private:
184 Register _base; // Base register.
185 Register _index; // Index register
186 intptr_t _disp; // Constant displacement.
187
188 public:
189 Address() :
190 _base(noreg),
191 _index(noreg),
192 _disp(0) {}
193
194 Address(Register base, Register index, intptr_t disp = 0) :
195 _base(base),
196 _index(index),
197 _disp(disp) {}
198
199 Address(Register base, intptr_t disp = 0) :
200 _base(base),
201 _index(noreg),
202 _disp(disp) {}
203
204 Address(Register base, RegisterOrConstant roc, intptr_t disp = 0) :
205 _base(base),
206 _index(noreg),
207 _disp(disp) {
208 if (roc.is_constant()) _disp += roc.as_constant(); else _index = roc.as_register();
209 }
210
211 #ifdef ASSERT
212 // ByteSize is only a class when ASSERT is defined, otherwise it's an int.
213 Address(Register base, ByteSize disp) :
214 _base(base),
215 _index(noreg),
216 _disp(in_bytes(disp)) {}
217
218 Address(Register base, Register index, ByteSize disp) :
219 _base(base),
220 _index(index),
221 _disp(in_bytes(disp)) {}
222 #endif
223
224 // Aborts if disp is a register and base and index are set already.
225 Address plus_disp(RegisterOrConstant disp) const {
226 Address a = (*this);
227 a._disp += disp.constant_or_zero();
228 if (disp.is_register()) {
229 if (a._index == noreg) {
230 a._index = disp.as_register();
231 } else {
232 guarantee(_base == noreg, "can not encode"); a._base = disp.as_register();
233 }
234 }
235 return a;
236 }
237
238 // A call to this is generated by adlc for replacement variable $xxx$$Address.
239 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
240
241 bool is_same_address(Address a) const {
242 return _base == a._base && _index == a._index && _disp == a._disp;
243 }
244
245 // testers
246 bool has_base() const { return _base != noreg; }
247 bool has_index() const { return _index != noreg; }
248 bool has_disp() const { return true; } // There is no "invalid" value.
249
250 bool is_disp12() const { return Immediate::is_uimm12(disp()); }
251 bool is_disp20() const { return Immediate::is_simm20(disp()); }
252 bool is_RSform() { return has_base() && !has_index() && is_disp12(); }
253 bool is_RSYform() { return has_base() && !has_index() && is_disp20(); }
254 bool is_RXform() { return has_base() && has_index() && is_disp12(); }
255 bool is_RXEform() { return has_base() && has_index() && is_disp12(); }
256 bool is_RXYform() { return has_base() && has_index() && is_disp20(); }
257
258 bool uses(Register r) { return _base == r || _index == r; };
259
260 // accessors
261 Register base() const { return _base; }
262 Register baseOrR0() const { assert(_base != Z_R0, ""); return _base == noreg ? Z_R0 : _base; }
263 Register index() const { return _index; }
264 Register indexOrR0() const { assert(_index != Z_R0, ""); return _index == noreg ? Z_R0 : _index; }
265 intptr_t disp() const { return _disp; }
266 // Specific version for short displacement instructions.
267 int disp12() const {
268 assert(is_disp12(), "displacement out of range for uimm12");
269 return _disp;
270 }
271 // Specific version for long displacement instructions.
272 int disp20() const {
273 assert(is_disp20(), "displacement out of range for simm20");
274 return _disp;
275 }
276 intptr_t value() const { return _disp; }
277
278 friend class Assembler;
279 };
280
281 class AddressLiteral VALUE_OBJ_CLASS_SPEC {
282 private:
283 address _address;
284 RelocationHolder _rspec;
285
286 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) {
287 switch (rtype) {
288 case relocInfo::external_word_type:
289 return external_word_Relocation::spec(addr);
290 case relocInfo::internal_word_type:
291 return internal_word_Relocation::spec(addr);
292 case relocInfo::opt_virtual_call_type:
293 return opt_virtual_call_Relocation::spec();
294 case relocInfo::static_call_type:
295 return static_call_Relocation::spec();
296 case relocInfo::runtime_call_w_cp_type:
297 return runtime_call_w_cp_Relocation::spec();
298 case relocInfo::none:
299 return RelocationHolder();
300 default:
301 ShouldNotReachHere();
302 return RelocationHolder();
303 }
304 }
305
306 protected:
307 // creation
308 AddressLiteral() : _address(NULL), _rspec(NULL) {}
309
310 public:
311 AddressLiteral(address addr, RelocationHolder const& rspec)
312 : _address(addr),
313 _rspec(rspec) {}
314
315 // Some constructors to avoid casting at the call site.
316 AddressLiteral(jobject obj, RelocationHolder const& rspec)
317 : _address((address) obj),
318 _rspec(rspec) {}
319
320 AddressLiteral(intptr_t value, RelocationHolder const& rspec)
321 : _address((address) value),
322 _rspec(rspec) {}
323
324 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none)
325 : _address((address) addr),
326 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
327
328 // Some constructors to avoid casting at the call site.
329 AddressLiteral(address* addr, relocInfo::relocType rtype = relocInfo::none)
330 : _address((address) addr),
331 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
332
333 AddressLiteral(bool* addr, relocInfo::relocType rtype = relocInfo::none)
334 : _address((address) addr),
335 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
336
337 AddressLiteral(const bool* addr, relocInfo::relocType rtype = relocInfo::none)
338 : _address((address) addr),
339 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
340
341 AddressLiteral(signed char* addr, relocInfo::relocType rtype = relocInfo::none)
342 : _address((address) addr),
343 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
344
345 AddressLiteral(int* addr, relocInfo::relocType rtype = relocInfo::none)
346 : _address((address) addr),
347 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
348
349 AddressLiteral(intptr_t addr, relocInfo::relocType rtype = relocInfo::none)
350 : _address((address) addr),
351 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
352
353 AddressLiteral(intptr_t* addr, relocInfo::relocType rtype = relocInfo::none)
354 : _address((address) addr),
355 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
356
357 AddressLiteral(oop addr, relocInfo::relocType rtype = relocInfo::none)
358 : _address((address) addr),
359 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
360
361 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none)
362 : _address((address) addr),
363 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
364
365 AddressLiteral(float* addr, relocInfo::relocType rtype = relocInfo::none)
366 : _address((address) addr),
367 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
368
369 AddressLiteral(double* addr, relocInfo::relocType rtype = relocInfo::none)
370 : _address((address) addr),
371 _rspec(rspec_from_rtype(rtype, (address) addr)) {}
372
373 intptr_t value() const { return (intptr_t) _address; }
374
375 const relocInfo::relocType rtype() const { return _rspec.type(); }
376 const RelocationHolder& rspec() const { return _rspec; }
377
378 RelocationHolder rspec(int offset) const {
379 return offset == 0 ? _rspec : _rspec.plus(offset);
380 }
381 };
382
383 // Convenience classes
384 class ExternalAddress: public AddressLiteral {
385 private:
386 static relocInfo::relocType reloc_for_target(address target) {
387 // Sometimes ExternalAddress is used for values which aren't
388 // exactly addresses, like the card table base.
389 // External_word_type can't be used for values in the first page
390 // so just skip the reloc in that case.
391 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
392 }
393
394 public:
395 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target( target)) {}
396 ExternalAddress(oop* target) : AddressLiteral(target, reloc_for_target((address) target)) {}
397 };
398
399 // Argument is an abstraction used to represent an outgoing actual
400 // argument or an incoming formal parameter, whether it resides in
401 // memory or in a register, in a manner consistent with the
402 // z/Architecture Application Binary Interface, or ABI. This is often
403 // referred to as the native or C calling convention.
404 class Argument VALUE_OBJ_CLASS_SPEC {
405 private:
406 int _number;
407 bool _is_in;
408
409 public:
410 enum {
411 // Only 5 registers may contain integer parameters.
412 n_register_parameters = 5,
413 // Can have up to 4 floating registers.
414 n_float_register_parameters = 4
415 };
416
417 // creation
418 Argument(int number, bool is_in) : _number(number), _is_in(is_in) {}
419 Argument(int number) : _number(number) {}
420
421 int number() const { return _number; }
422
423 Argument successor() const { return Argument(number() + 1); }
424
425 // Locating register-based arguments:
426 bool is_register() const { return _number < n_register_parameters; }
427
428 // Locating Floating Point register-based arguments:
429 bool is_float_register() const { return _number < n_float_register_parameters; }
430
431 FloatRegister as_float_register() const {
432 assert(is_float_register(), "must be a register argument");
433 return as_FloatRegister((number() *2) + 1);
434 }
435
436 FloatRegister as_double_register() const {
437 assert(is_float_register(), "must be a register argument");
438 return as_FloatRegister((number() *2));
439 }
440
441 Register as_register() const {
442 assert(is_register(), "must be a register argument");
443 return as_Register(number() + Z_ARG1->encoding());
444 }
445
446 // debugging
447 const char* name() const;
448
449 friend class Assembler;
450 };
451
452
453 // The z/Architecture Assembler: Pure assembler doing NO optimizations
454 // on the instruction level; i.e., what you write is what you get. The
455 // Assembler is generating code into a CodeBuffer.
456 class Assembler : public AbstractAssembler {
457 protected:
458
459 friend class AbstractAssembler;
460 friend class AddressLiteral;
461
462 // Code patchers need various routines like inv_wdisp().
463 friend class NativeInstruction;
464 #ifndef COMPILER2
465 friend class NativeGeneralJump;
466 #endif
467 friend class Relocation;
468
469 public:
470
471 // Addressing
472
473 // address calculation
474 #define LA_ZOPC (unsigned int)(0x41 << 24)
475 #define LAY_ZOPC (unsigned long)(0xe3L << 40 | 0x71L)
476 #define LARL_ZOPC (unsigned long)(0xc0L << 40 | 0x00L << 32)
477
478
479 // Data Transfer
480
481 // register to register transfer
482 #define LR_ZOPC (unsigned int)(24 << 8)
483 #define LBR_ZOPC (unsigned int)(0xb926 << 16)
484 #define LHR_ZOPC (unsigned int)(0xb927 << 16)
485 #define LGBR_ZOPC (unsigned int)(0xb906 << 16)
486 #define LGHR_ZOPC (unsigned int)(0xb907 << 16)
487 #define LGFR_ZOPC (unsigned int)(0xb914 << 16)
488 #define LGR_ZOPC (unsigned int)(0xb904 << 16)
489
490 #define LLHR_ZOPC (unsigned int)(0xb995 << 16)
491 #define LLGCR_ZOPC (unsigned int)(0xb984 << 16)
492 #define LLGHR_ZOPC (unsigned int)(0xb985 << 16)
493 #define LLGTR_ZOPC (unsigned int)(185 << 24 | 23 << 16)
494 #define LLGFR_ZOPC (unsigned int)(185 << 24 | 22 << 16)
495
496 #define LTR_ZOPC (unsigned int)(18 << 8)
497 #define LTGFR_ZOPC (unsigned int)(185 << 24 | 18 << 16)
498 #define LTGR_ZOPC (unsigned int)(185 << 24 | 2 << 16)
499
500 #define LER_ZOPC (unsigned int)(56 << 8)
501 #define LEDBR_ZOPC (unsigned int)(179 << 24 | 68 << 16)
502 #define LEXBR_ZOPC (unsigned int)(179 << 24 | 70 << 16)
503 #define LDEBR_ZOPC (unsigned int)(179 << 24 | 4 << 16)
504 #define LDR_ZOPC (unsigned int)(40 << 8)
505 #define LDXBR_ZOPC (unsigned int)(179 << 24 | 69 << 16)
506 #define LXEBR_ZOPC (unsigned int)(179 << 24 | 6 << 16)
507 #define LXDBR_ZOPC (unsigned int)(179 << 24 | 5 << 16)
508 #define LXR_ZOPC (unsigned int)(179 << 24 | 101 << 16)
509 #define LTEBR_ZOPC (unsigned int)(179 << 24 | 2 << 16)
510 #define LTDBR_ZOPC (unsigned int)(179 << 24 | 18 << 16)
511 #define LTXBR_ZOPC (unsigned int)(179 << 24 | 66 << 16)
512
513 #define LRVR_ZOPC (unsigned int)(0xb91f << 16)
514 #define LRVGR_ZOPC (unsigned int)(0xb90f << 16)
515
516 #define LDGR_ZOPC (unsigned int)(0xb3c1 << 16) // z10
517 #define LGDR_ZOPC (unsigned int)(0xb3cd << 16) // z10
518
519 #define LOCR_ZOPC (unsigned int)(0xb9f2 << 16) // z196
520 #define LOCGR_ZOPC (unsigned int)(0xb9e2 << 16) // z196
521
522 // immediate to register transfer
523 #define IIHH_ZOPC (unsigned int)(165 << 24)
524 #define IIHL_ZOPC (unsigned int)(165 << 24 | 1 << 16)
525 #define IILH_ZOPC (unsigned int)(165 << 24 | 2 << 16)
526 #define IILL_ZOPC (unsigned int)(165 << 24 | 3 << 16)
527 #define IIHF_ZOPC (unsigned long)(0xc0L << 40 | 8L << 32)
528 #define IILF_ZOPC (unsigned long)(0xc0L << 40 | 9L << 32)
529 #define LLIHH_ZOPC (unsigned int)(165 << 24 | 12 << 16)
530 #define LLIHL_ZOPC (unsigned int)(165 << 24 | 13 << 16)
531 #define LLILH_ZOPC (unsigned int)(165 << 24 | 14 << 16)
532 #define LLILL_ZOPC (unsigned int)(165 << 24 | 15 << 16)
533 #define LLIHF_ZOPC (unsigned long)(0xc0L << 40 | 14L << 32)
534 #define LLILF_ZOPC (unsigned long)(0xc0L << 40 | 15L << 32)
535 #define LHI_ZOPC (unsigned int)(167 << 24 | 8 << 16)
536 #define LGHI_ZOPC (unsigned int)(167 << 24 | 9 << 16)
537 #define LGFI_ZOPC (unsigned long)(0xc0L << 40 | 1L << 32)
538
539 #define LZER_ZOPC (unsigned int)(0xb374 << 16)
540 #define LZDR_ZOPC (unsigned int)(0xb375 << 16)
541
542 // LOAD: memory to register transfer
543 #define LB_ZOPC (unsigned long)(227L << 40 | 118L)
544 #define LH_ZOPC (unsigned int)(72 << 24)
545 #define LHY_ZOPC (unsigned long)(227L << 40 | 120L)
546 #define L_ZOPC (unsigned int)(88 << 24)
547 #define LY_ZOPC (unsigned long)(227L << 40 | 88L)
548 #define LT_ZOPC (unsigned long)(0xe3L << 40 | 0x12L)
549 #define LGB_ZOPC (unsigned long)(227L << 40 | 119L)
550 #define LGH_ZOPC (unsigned long)(227L << 40 | 21L)
551 #define LGF_ZOPC (unsigned long)(227L << 40 | 20L)
552 #define LG_ZOPC (unsigned long)(227L << 40 | 4L)
553 #define LTG_ZOPC (unsigned long)(0xe3L << 40 | 0x02L)
554 #define LTGF_ZOPC (unsigned long)(0xe3L << 40 | 0x32L)
555
556 #define LLC_ZOPC (unsigned long)(0xe3L << 40 | 0x94L)
557 #define LLH_ZOPC (unsigned long)(0xe3L << 40 | 0x95L)
558 #define LLGT_ZOPC (unsigned long)(227L << 40 | 23L)
559 #define LLGC_ZOPC (unsigned long)(227L << 40 | 144L)
560 #define LLGH_ZOPC (unsigned long)(227L << 40 | 145L)
561 #define LLGF_ZOPC (unsigned long)(227L << 40 | 22L)
562
563 #define IC_ZOPC (unsigned int)(0x43 << 24)
564 #define ICY_ZOPC (unsigned long)(0xe3L << 40 | 0x73L)
565 #define ICM_ZOPC (unsigned int)(0xbf << 24)
566 #define ICMY_ZOPC (unsigned long)(0xebL << 40 | 0x81L)
567 #define ICMH_ZOPC (unsigned long)(0xebL << 40 | 0x80L)
568
569 #define LRVH_ZOPC (unsigned long)(0xe3L << 40 | 0x1fL)
570 #define LRV_ZOPC (unsigned long)(0xe3L << 40 | 0x1eL)
571 #define LRVG_ZOPC (unsigned long)(0xe3L << 40 | 0x0fL)
572
573
574 // LOAD relative: memory to register transfer
575 #define LHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x05L << 32) // z10
576 #define LRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0dL << 32) // z10
577 #define LGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x04L << 32) // z10
578 #define LGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0cL << 32) // z10
579 #define LGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x08L << 32) // z10
580
581 #define LLHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x02L << 32) // z10
582 #define LLGHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x06L << 32) // z10
583 #define LLGFRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0eL << 32) // z10
584
585 #define LOC_ZOPC (unsigned long)(0xebL << 40 | 0xf2L) // z196
586 #define LOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe2L) // z196
587
588 #define LMG_ZOPC (unsigned long)(235L << 40 | 4L)
589
590 #define LE_ZOPC (unsigned int)(0x78 << 24)
591 #define LEY_ZOPC (unsigned long)(237L << 40 | 100L)
592 #define LDEB_ZOPC (unsigned long)(237L << 40 | 4)
593 #define LD_ZOPC (unsigned int)(0x68 << 24)
594 #define LDY_ZOPC (unsigned long)(237L << 40 | 101L)
595 #define LXEB_ZOPC (unsigned long)(237L << 40 | 6)
596 #define LXDB_ZOPC (unsigned long)(237L << 40 | 5)
597
598 // STORE: register to memory transfer
599 #define STC_ZOPC (unsigned int)(0x42 << 24)
600 #define STCY_ZOPC (unsigned long)(227L << 40 | 114L)
601 #define STH_ZOPC (unsigned int)(64 << 24)
602 #define STHY_ZOPC (unsigned long)(227L << 40 | 112L)
603 #define ST_ZOPC (unsigned int)(80 << 24)
604 #define STY_ZOPC (unsigned long)(227L << 40 | 80L)
605 #define STG_ZOPC (unsigned long)(227L << 40 | 36L)
606
607 #define STCM_ZOPC (unsigned long)(0xbeL << 24)
608 #define STCMY_ZOPC (unsigned long)(0xebL << 40 | 0x2dL)
609 #define STCMH_ZOPC (unsigned long)(0xebL << 40 | 0x2cL)
610
611 // STORE relative: memory to register transfer
612 #define STHRL_ZOPC (unsigned long)(0xc4L << 40 | 0x07L << 32) // z10
613 #define STRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0fL << 32) // z10
614 #define STGRL_ZOPC (unsigned long)(0xc4L << 40 | 0x0bL << 32) // z10
615
616 #define STOC_ZOPC (unsigned long)(0xebL << 40 | 0xf3L) // z196
617 #define STOCG_ZOPC (unsigned long)(0xebL << 40 | 0xe3L) // z196
618
619 #define STMG_ZOPC (unsigned long)(235L << 40 | 36L)
620
621 #define STE_ZOPC (unsigned int)(0x70 << 24)
622 #define STEY_ZOPC (unsigned long)(237L << 40 | 102L)
623 #define STD_ZOPC (unsigned int)(0x60 << 24)
624 #define STDY_ZOPC (unsigned long)(237L << 40 | 103L)
625
626 // MOVE: immediate to memory transfer
627 #define MVHHI_ZOPC (unsigned long)(0xe5L << 40 | 0x44L << 32) // z10
628 #define MVHI_ZOPC (unsigned long)(0xe5L << 40 | 0x4cL << 32) // z10
629 #define MVGHI_ZOPC (unsigned long)(0xe5L << 40 | 0x48L << 32) // z10
630
631
632 // ALU operations
633
634 // Load Positive
635 #define LPR_ZOPC (unsigned int)(16 << 8)
636 #define LPGFR_ZOPC (unsigned int)(185 << 24 | 16 << 16)
637 #define LPGR_ZOPC (unsigned int)(185 << 24)
638 #define LPEBR_ZOPC (unsigned int)(179 << 24)
639 #define LPDBR_ZOPC (unsigned int)(179 << 24 | 16 << 16)
640 #define LPXBR_ZOPC (unsigned int)(179 << 24 | 64 << 16)
641
642 // Load Negative
643 #define LNR_ZOPC (unsigned int)(17 << 8)
644 #define LNGFR_ZOPC (unsigned int)(185 << 24 | 17 << 16)
645 #define LNGR_ZOPC (unsigned int)(185 << 24 | 1 << 16)
646 #define LNEBR_ZOPC (unsigned int)(179 << 24 | 1 << 16)
647 #define LNDBR_ZOPC (unsigned int)(179 << 24 | 17 << 16)
648 #define LNXBR_ZOPC (unsigned int)(179 << 24 | 65 << 16)
649
650 // Load Complement
651 #define LCR_ZOPC (unsigned int)(19 << 8)
652 #define LCGFR_ZOPC (unsigned int)(185 << 24 | 19 << 16)
653 #define LCGR_ZOPC (unsigned int)(185 << 24 | 3 << 16)
654 #define LCEBR_ZOPC (unsigned int)(179 << 24 | 3 << 16)
655 #define LCDBR_ZOPC (unsigned int)(179 << 24 | 19 << 16)
656 #define LCXBR_ZOPC (unsigned int)(179 << 24 | 67 << 16)
657
658 // Add
659 // RR, signed
660 #define AR_ZOPC (unsigned int)(26 << 8)
661 #define AGFR_ZOPC (unsigned int)(0xb9 << 24 | 0x18 << 16)
662 #define AGR_ZOPC (unsigned int)(0xb9 << 24 | 0x08 << 16)
663 // RRF, signed
664 #define ARK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f8 << 16)
665 #define AGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e8 << 16)
666 // RI, signed
667 #define AHI_ZOPC (unsigned int)(167 << 24 | 10 << 16)
668 #define AFI_ZOPC (unsigned long)(0xc2L << 40 | 9L << 32)
669 #define AGHI_ZOPC (unsigned int)(167 << 24 | 11 << 16)
670 #define AGFI_ZOPC (unsigned long)(0xc2L << 40 | 8L << 32)
671 // RIE, signed
672 #define AHIK_ZOPC (unsigned long)(0xecL << 40 | 0x00d8L)
673 #define AGHIK_ZOPC (unsigned long)(0xecL << 40 | 0x00d9L)
674 #define AIH_ZOPC (unsigned long)(0xccL << 40 | 0x08L << 32)
675 // RM, signed
676 #define AHY_ZOPC (unsigned long)(227L << 40 | 122L)
677 #define A_ZOPC (unsigned int)(90 << 24)
678 #define AY_ZOPC (unsigned long)(227L << 40 | 90L)
679 #define AGF_ZOPC (unsigned long)(227L << 40 | 24L)
680 #define AG_ZOPC (unsigned long)(227L << 40 | 8L)
681 // In-memory arithmetic (add signed, add logical with signed immediate).
682 // MI, signed
683 #define ASI_ZOPC (unsigned long)(0xebL << 40 | 0x6aL)
684 #define AGSI_ZOPC (unsigned long)(0xebL << 40 | 0x7aL)
685
686 // RR, Logical
687 #define ALR_ZOPC (unsigned int)(30 << 8)
688 #define ALGFR_ZOPC (unsigned int)(185 << 24 | 26 << 16)
689 #define ALGR_ZOPC (unsigned int)(185 << 24 | 10 << 16)
690 #define ALCGR_ZOPC (unsigned int)(185 << 24 | 136 << 16)
691 // RRF, Logical
692 #define ALRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00fa << 16)
693 #define ALGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00ea << 16)
694 // RI, Logical
695 #define ALFI_ZOPC (unsigned long)(0xc2L << 40 | 0x0bL << 32)
696 #define ALGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x0aL << 32)
697 // RIE, Logical
698 #define ALHSIK_ZOPC (unsigned long)(0xecL << 40 | 0x00daL)
699 #define ALGHSIK_ZOPC (unsigned long)(0xecL << 40 | 0x00dbL)
700 // RM, Logical
701 #define AL_ZOPC (unsigned int)(0x5e << 24)
702 #define ALY_ZOPC (unsigned long)(227L << 40 | 94L)
703 #define ALGF_ZOPC (unsigned long)(227L << 40 | 26L)
704 #define ALG_ZOPC (unsigned long)(227L << 40 | 10L)
705 // In-memory arithmetic (add signed, add logical with signed immediate).
706 // MI, Logical
707 #define ALSI_ZOPC (unsigned long)(0xebL << 40 | 0x6eL)
708 #define ALGSI_ZOPC (unsigned long)(0xebL << 40 | 0x7eL)
709
710 // RR, BFP
711 #define AEBR_ZOPC (unsigned int)(179 << 24 | 10 << 16)
712 #define ADBR_ZOPC (unsigned int)(179 << 24 | 26 << 16)
713 #define AXBR_ZOPC (unsigned int)(179 << 24 | 74 << 16)
714 // RM, BFP
715 #define AEB_ZOPC (unsigned long)(237L << 40 | 10)
716 #define ADB_ZOPC (unsigned long)(237L << 40 | 26)
717
718 // Subtract
719 // RR, signed
720 #define SR_ZOPC (unsigned int)(27 << 8)
721 #define SGFR_ZOPC (unsigned int)(185 << 24 | 25 << 16)
722 #define SGR_ZOPC (unsigned int)(185 << 24 | 9 << 16)
723 // RRF, signed
724 #define SRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f9 << 16)
725 #define SGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e9 << 16)
726 // RM, signed
727 #define SH_ZOPC (unsigned int)(0x4b << 24)
728 #define SHY_ZOPC (unsigned long)(227L << 40 | 123L)
729 #define S_ZOPC (unsigned int)(0x5B << 24)
730 #define SY_ZOPC (unsigned long)(227L << 40 | 91L)
731 #define SGF_ZOPC (unsigned long)(227L << 40 | 25)
732 #define SG_ZOPC (unsigned long)(227L << 40 | 9)
733 // RR, Logical
734 #define SLR_ZOPC (unsigned int)(31 << 8)
735 #define SLGFR_ZOPC (unsigned int)(185 << 24 | 27 << 16)
736 #define SLGR_ZOPC (unsigned int)(185 << 24 | 11 << 16)
737 // RIL, Logical
738 #define SLFI_ZOPC (unsigned long)(0xc2L << 40 | 0x05L << 32)
739 #define SLGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x04L << 32)
740 // RRF, Logical
741 #define SLRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00fb << 16)
742 #define SLGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00eb << 16)
743 // RM, Logical
744 #define SLY_ZOPC (unsigned long)(227L << 40 | 95L)
745 #define SLGF_ZOPC (unsigned long)(227L << 40 | 27L)
746 #define SLG_ZOPC (unsigned long)(227L << 40 | 11L)
747
748 // RR, BFP
749 #define SEBR_ZOPC (unsigned int)(179 << 24 | 11 << 16)
750 #define SDBR_ZOPC (unsigned int)(179 << 24 | 27 << 16)
751 #define SXBR_ZOPC (unsigned int)(179 << 24 | 75 << 16)
752 // RM, BFP
753 #define SEB_ZOPC (unsigned long)(237L << 40 | 11)
754 #define SDB_ZOPC (unsigned long)(237L << 40 | 27)
755
756 // Multiply
757 // RR, signed
758 #define MR_ZOPC (unsigned int)(28 << 8)
759 #define MSR_ZOPC (unsigned int)(178 << 24 | 82 << 16)
760 #define MSGFR_ZOPC (unsigned int)(185 << 24 | 28 << 16)
761 #define MSGR_ZOPC (unsigned int)(185 << 24 | 12 << 16)
762 // RI, signed
763 #define MHI_ZOPC (unsigned int)(167 << 24 | 12 << 16)
764 #define MGHI_ZOPC (unsigned int)(167 << 24 | 13 << 16)
765 #define MSFI_ZOPC (unsigned long)(0xc2L << 40 | 0x01L << 32) // z10
766 #define MSGFI_ZOPC (unsigned long)(0xc2L << 40 | 0x00L << 32) // z10
767 // RM, signed
768 #define M_ZOPC (unsigned int)(92 << 24)
769 #define MS_ZOPC (unsigned int)(0x71 << 24)
770 #define MHY_ZOPC (unsigned long)(0xe3L<< 40 | 0x7cL)
771 #define MSY_ZOPC (unsigned long)(227L << 40 | 81L)
772 #define MSGF_ZOPC (unsigned long)(227L << 40 | 28L)
773 #define MSG_ZOPC (unsigned long)(227L << 40 | 12L)
774 // RR, unsigned
775 #define MLR_ZOPC (unsigned int)(185 << 24 | 150 << 16)
776 #define MLGR_ZOPC (unsigned int)(185 << 24 | 134 << 16)
777 // RM, unsigned
778 #define ML_ZOPC (unsigned long)(227L << 40 | 150L)
779 #define MLG_ZOPC (unsigned long)(227L << 40 | 134L)
780
781 // RR, BFP
782 #define MEEBR_ZOPC (unsigned int)(179 << 24 | 23 << 16)
783 #define MDEBR_ZOPC (unsigned int)(179 << 24 | 12 << 16)
784 #define MDBR_ZOPC (unsigned int)(179 << 24 | 28 << 16)
785 #define MXDBR_ZOPC (unsigned int)(179 << 24 | 7 << 16)
786 #define MXBR_ZOPC (unsigned int)(179 << 24 | 76 << 16)
787 // RM, BFP
788 #define MEEB_ZOPC (unsigned long)(237L << 40 | 23)
789 #define MDEB_ZOPC (unsigned long)(237L << 40 | 12)
790 #define MDB_ZOPC (unsigned long)(237L << 40 | 28)
791 #define MXDB_ZOPC (unsigned long)(237L << 40 | 7)
792
793 // Multiply-Add
794 #define MAEBR_ZOPC (unsigned int)(179 << 24 | 14 << 16)
795 #define MADBR_ZOPC (unsigned int)(179 << 24 | 30 << 16)
796 #define MSEBR_ZOPC (unsigned int)(179 << 24 | 15 << 16)
797 #define MSDBR_ZOPC (unsigned int)(179 << 24 | 31 << 16)
798 #define MAEB_ZOPC (unsigned long)(237L << 40 | 14)
799 #define MADB_ZOPC (unsigned long)(237L << 40 | 30)
800 #define MSEB_ZOPC (unsigned long)(237L << 40 | 15)
801 #define MSDB_ZOPC (unsigned long)(237L << 40 | 31)
802
803 // Divide
804 // RR, signed
805 #define DSGFR_ZOPC (unsigned int)(0xb91d << 16)
806 #define DSGR_ZOPC (unsigned int)(0xb90d << 16)
807 // RM, signed
808 #define D_ZOPC (unsigned int)(93 << 24)
809 #define DSGF_ZOPC (unsigned long)(227L << 40 | 29L)
810 #define DSG_ZOPC (unsigned long)(227L << 40 | 13L)
811 // RR, unsigned
812 #define DLR_ZOPC (unsigned int)(185 << 24 | 151 << 16)
813 #define DLGR_ZOPC (unsigned int)(185 << 24 | 135 << 16)
814 // RM, unsigned
815 #define DL_ZOPC (unsigned long)(227L << 40 | 151L)
816 #define DLG_ZOPC (unsigned long)(227L << 40 | 135L)
817
818 // RR, BFP
819 #define DEBR_ZOPC (unsigned int)(179 << 24 | 13 << 16)
820 #define DDBR_ZOPC (unsigned int)(179 << 24 | 29 << 16)
821 #define DXBR_ZOPC (unsigned int)(179 << 24 | 77 << 16)
822 // RM, BFP
823 #define DEB_ZOPC (unsigned long)(237L << 40 | 13)
824 #define DDB_ZOPC (unsigned long)(237L << 40 | 29)
825
826 // Square Root
827 // RR, BFP
828 #define SQEBR_ZOPC (unsigned int)(0xb314 << 16)
829 #define SQDBR_ZOPC (unsigned int)(0xb315 << 16)
830 #define SQXBR_ZOPC (unsigned int)(0xb316 << 16)
831 // RM, BFP
832 #define SQEB_ZOPC (unsigned long)(237L << 40 | 20)
833 #define SQDB_ZOPC (unsigned long)(237L << 40 | 21)
834
835 // Compare and Test
836 // RR, signed
837 #define CR_ZOPC (unsigned int)(25 << 8)
838 #define CGFR_ZOPC (unsigned int)(185 << 24 | 48 << 16)
839 #define CGR_ZOPC (unsigned int)(185 << 24 | 32 << 16)
840 // RI, signed
841 #define CHI_ZOPC (unsigned int)(167 << 24 | 14 << 16)
842 #define CFI_ZOPC (unsigned long)(0xc2L << 40 | 0xdL << 32)
843 #define CGHI_ZOPC (unsigned int)(167 << 24 | 15 << 16)
844 #define CGFI_ZOPC (unsigned long)(0xc2L << 40 | 0xcL << 32)
845 // RM, signed
846 #define CH_ZOPC (unsigned int)(0x49 << 24)
847 #define CHY_ZOPC (unsigned long)(227L << 40 | 121L)
848 #define C_ZOPC (unsigned int)(0x59 << 24)
849 #define CY_ZOPC (unsigned long)(227L << 40 | 89L)
850 #define CGF_ZOPC (unsigned long)(227L << 40 | 48L)
851 #define CG_ZOPC (unsigned long)(227L << 40 | 32L)
852 // RR, unsigned
853 #define CLR_ZOPC (unsigned int)(21 << 8)
854 #define CLGFR_ZOPC (unsigned int)(185 << 24 | 49 << 16)
855 #define CLGR_ZOPC (unsigned int)(185 << 24 | 33 << 16)
856 // RIL, unsigned
857 #define CLFI_ZOPC (unsigned long)(0xc2L << 40 | 0xfL << 32)
858 #define CLGFI_ZOPC (unsigned long)(0xc2L << 40 | 0xeL << 32)
859 // RM, unsigned
860 #define CL_ZOPC (unsigned int)(0x55 << 24)
861 #define CLY_ZOPC (unsigned long)(227L << 40 | 85L)
862 #define CLGF_ZOPC (unsigned long)(227L << 40 | 49L)
863 #define CLG_ZOPC (unsigned long)(227L << 40 | 33L)
864 // RI, unsigned
865 #define TMHH_ZOPC (unsigned int)(167 << 24 | 2 << 16)
866 #define TMHL_ZOPC (unsigned int)(167 << 24 | 3 << 16)
867 #define TMLH_ZOPC (unsigned int)(167 << 24)
868 #define TMLL_ZOPC (unsigned int)(167 << 24 | 1 << 16)
869
870 // RR, BFP
871 #define CEBR_ZOPC (unsigned int)(179 << 24 | 9 << 16)
872 #define CDBR_ZOPC (unsigned int)(179 << 24 | 25 << 16)
873 #define CXBR_ZOPC (unsigned int)(179 << 24 | 73 << 16)
874 // RM, BFP
875 #define CEB_ZOPC (unsigned long)(237L << 40 | 9)
876 #define CDB_ZOPC (unsigned long)(237L << 40 | 25)
877
878 // Shift
879 // arithmetic
880 #define SLA_ZOPC (unsigned int)(139 << 24)
881 #define SLAG_ZOPC (unsigned long)(235L << 40 | 11L)
882 #define SRA_ZOPC (unsigned int)(138 << 24)
883 #define SRAG_ZOPC (unsigned long)(235L << 40 | 10L)
884 // logical
885 #define SLL_ZOPC (unsigned int)(137 << 24)
886 #define SLLG_ZOPC (unsigned long)(235L << 40 | 13L)
887 #define SRL_ZOPC (unsigned int)(136 << 24)
888 #define SRLG_ZOPC (unsigned long)(235L << 40 | 12L)
889
890 // Rotate, then AND/XOR/OR/insert
891 // rotate
892 #define RLL_ZOPC (unsigned long)(0xebL << 40 | 0x1dL) // z10
893 #define RLLG_ZOPC (unsigned long)(0xebL << 40 | 0x1cL) // z10
894 // rotate and {AND|XOR|OR|INS}
895 #define RNSBG_ZOPC (unsigned long)(0xecL << 40 | 0x54L) // z196
896 #define RXSBG_ZOPC (unsigned long)(0xecL << 40 | 0x57L) // z196
897 #define ROSBG_ZOPC (unsigned long)(0xecL << 40 | 0x56L) // z196
898 #define RISBG_ZOPC (unsigned long)(0xecL << 40 | 0x55L) // z196
899
900 // AND
901 // RR, signed
902 #define NR_ZOPC (unsigned int)(20 << 8)
903 #define NGR_ZOPC (unsigned int)(185 << 24 | 128 << 16)
904 // RRF, signed
905 #define NRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f4 << 16)
906 #define NGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e4 << 16)
907 // RI, signed
908 #define NIHH_ZOPC (unsigned int)(165 << 24 | 4 << 16)
909 #define NIHL_ZOPC (unsigned int)(165 << 24 | 5 << 16)
910 #define NILH_ZOPC (unsigned int)(165 << 24 | 6 << 16)
911 #define NILL_ZOPC (unsigned int)(165 << 24 | 7 << 16)
912 #define NIHF_ZOPC (unsigned long)(0xc0L << 40 | 10L << 32)
913 #define NILF_ZOPC (unsigned long)(0xc0L << 40 | 11L << 32)
914 // RM, signed
915 #define N_ZOPC (unsigned int)(0x54 << 24)
916 #define NY_ZOPC (unsigned long)(227L << 40 | 84L)
917 #define NG_ZOPC (unsigned long)(227L << 40 | 128L)
918
919 // OR
920 // RR, signed
921 #define OR_ZOPC (unsigned int)(22 << 8)
922 #define OGR_ZOPC (unsigned int)(185 << 24 | 129 << 16)
923 // RRF, signed
924 #define ORK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f6 << 16)
925 #define OGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e6 << 16)
926 // RI, signed
927 #define OIHH_ZOPC (unsigned int)(165 << 24 | 8 << 16)
928 #define OIHL_ZOPC (unsigned int)(165 << 24 | 9 << 16)
929 #define OILH_ZOPC (unsigned int)(165 << 24 | 10 << 16)
930 #define OILL_ZOPC (unsigned int)(165 << 24 | 11 << 16)
931 #define OIHF_ZOPC (unsigned long)(0xc0L << 40 | 12L << 32)
932 #define OILF_ZOPC (unsigned long)(0xc0L << 40 | 13L << 32)
933 // RM, signed
934 #define O_ZOPC (unsigned int)(0x56 << 24)
935 #define OY_ZOPC (unsigned long)(227L << 40 | 86L)
936 #define OG_ZOPC (unsigned long)(227L << 40 | 129L)
937
938 // XOR
939 // RR, signed
940 #define XR_ZOPC (unsigned int)(23 << 8)
941 #define XGR_ZOPC (unsigned int)(185 << 24 | 130 << 16)
942 // RRF, signed
943 #define XRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00f7 << 16)
944 #define XGRK_ZOPC (unsigned int)(0xb9 << 24 | 0x00e7 << 16)
945 // RI, signed
946 #define XIHF_ZOPC (unsigned long)(0xc0L << 40 | 6L << 32)
947 #define XILF_ZOPC (unsigned long)(0xc0L << 40 | 7L << 32)
948 // RM, signed
949 #define X_ZOPC (unsigned int)(0x57 << 24)
950 #define XY_ZOPC (unsigned long)(227L << 40 | 87L)
951 #define XG_ZOPC (unsigned long)(227L << 40 | 130L)
952
953
954 // Data Conversion
955
956 // INT to BFP
957 #define CEFBR_ZOPC (unsigned int)(179 << 24 | 148 << 16)
958 #define CDFBR_ZOPC (unsigned int)(179 << 24 | 149 << 16)
959 #define CXFBR_ZOPC (unsigned int)(179 << 24 | 150 << 16)
960 #define CEGBR_ZOPC (unsigned int)(179 << 24 | 164 << 16)
961 #define CDGBR_ZOPC (unsigned int)(179 << 24 | 165 << 16)
962 #define CXGBR_ZOPC (unsigned int)(179 << 24 | 166 << 16)
963 // BFP to INT
964 #define CFEBR_ZOPC (unsigned int)(179 << 24 | 152 << 16)
965 #define CFDBR_ZOPC (unsigned int)(179 << 24 | 153 << 16)
966 #define CFXBR_ZOPC (unsigned int)(179 << 24 | 154 << 16)
967 #define CGEBR_ZOPC (unsigned int)(179 << 24 | 168 << 16)
968 #define CGDBR_ZOPC (unsigned int)(179 << 24 | 169 << 16)
969 #define CGXBR_ZOPC (unsigned int)(179 << 24 | 170 << 16)
970 // INT to DEC
971 #define CVD_ZOPC (unsigned int)(0x4e << 24)
972 #define CVDY_ZOPC (unsigned long)(0xe3L << 40 | 0x26L)
973 #define CVDG_ZOPC (unsigned long)(0xe3L << 40 | 0x2eL)
974
975
976 // BFP Control
977
978 #define SRNM_ZOPC (unsigned int)(178 << 24 | 153 << 16)
979 #define EFPC_ZOPC (unsigned int)(179 << 24 | 140 << 16)
980 #define SFPC_ZOPC (unsigned int)(179 << 24 | 132 << 16)
981 #define STFPC_ZOPC (unsigned int)(178 << 24 | 156 << 16)
982 #define LFPC_ZOPC (unsigned int)(178 << 24 | 157 << 16)
983
984
985 // Branch Instructions
986
987 // Register
988 #define BCR_ZOPC (unsigned int)(7 << 8)
989 #define BALR_ZOPC (unsigned int)(5 << 8)
990 #define BASR_ZOPC (unsigned int)(13 << 8)
991 #define BCTGR_ZOPC (unsigned long)(0xb946 << 16)
992 // Absolute
993 #define BC_ZOPC (unsigned int)(71 << 24)
994 #define BAL_ZOPC (unsigned int)(69 << 24)
995 #define BAS_ZOPC (unsigned int)(77 << 24)
996 #define BXH_ZOPC (unsigned int)(134 << 24)
997 #define BXHG_ZOPC (unsigned long)(235L << 40 | 68)
998 // Relative
999 #define BRC_ZOPC (unsigned int)(167 << 24 | 4 << 16)
1000 #define BRCL_ZOPC (unsigned long)(192L << 40 | 4L << 32)
1001 #define BRAS_ZOPC (unsigned int)(167 << 24 | 5 << 16)
1002 #define BRASL_ZOPC (unsigned long)(192L << 40 | 5L << 32)
1003 #define BRCT_ZOPC (unsigned int)(167 << 24 | 6 << 16)
1004 #define BRCTG_ZOPC (unsigned int)(167 << 24 | 7 << 16)
1005 #define BRXH_ZOPC (unsigned int)(132 << 24)
1006 #define BRXHG_ZOPC (unsigned long)(236L << 40 | 68)
1007 #define BRXLE_ZOPC (unsigned int)(133 << 24)
1008 #define BRXLG_ZOPC (unsigned long)(236L << 40 | 69)
1009
1010
1011 // Compare and Branch Instructions
1012
1013 // signed comp reg/reg, branch Absolute
1014 #define CRB_ZOPC (unsigned long)(0xecL << 40 | 0xf6L) // z10
1015 #define CGRB_ZOPC (unsigned long)(0xecL << 40 | 0xe4L) // z10
1016 // signed comp reg/reg, branch Relative
1017 #define CRJ_ZOPC (unsigned long)(0xecL << 40 | 0x76L) // z10
1018 #define CGRJ_ZOPC (unsigned long)(0xecL << 40 | 0x64L) // z10
1019 // signed comp reg/imm, branch absolute
1020 #define CIB_ZOPC (unsigned long)(0xecL << 40 | 0xfeL) // z10
1021 #define CGIB_ZOPC (unsigned long)(0xecL << 40 | 0xfcL) // z10
1022 // signed comp reg/imm, branch relative
1023 #define CIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7eL) // z10
1024 #define CGIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7cL) // z10
1025
1026 // unsigned comp reg/reg, branch Absolute
1027 #define CLRB_ZOPC (unsigned long)(0xecL << 40 | 0xf7L) // z10
1028 #define CLGRB_ZOPC (unsigned long)(0xecL << 40 | 0xe5L) // z10
1029 // unsigned comp reg/reg, branch Relative
1030 #define CLRJ_ZOPC (unsigned long)(0xecL << 40 | 0x77L) // z10
1031 #define CLGRJ_ZOPC (unsigned long)(0xecL << 40 | 0x65L) // z10
1032 // unsigned comp reg/imm, branch absolute
1033 #define CLIB_ZOPC (unsigned long)(0xecL << 40 | 0xffL) // z10
1034 #define CLGIB_ZOPC (unsigned long)(0xecL << 40 | 0xfdL) // z10
1035 // unsigned comp reg/imm, branch relative
1036 #define CLIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7fL) // z10
1037 #define CLGIJ_ZOPC (unsigned long)(0xecL << 40 | 0x7dL) // z10
1038
1039 // comp reg/reg, trap
1040 #define CRT_ZOPC (unsigned int)(0xb972 << 16) // z10
1041 #define CGRT_ZOPC (unsigned int)(0xb960 << 16) // z10
1042 #define CLRT_ZOPC (unsigned int)(0xb973 << 16) // z10
1043 #define CLGRT_ZOPC (unsigned int)(0xb961 << 16) // z10
1044 // comp reg/imm, trap
1045 #define CIT_ZOPC (unsigned long)(0xecL << 40 | 0x72L) // z10
1046 #define CGIT_ZOPC (unsigned long)(0xecL << 40 | 0x70L) // z10
1047 #define CLFIT_ZOPC (unsigned long)(0xecL << 40 | 0x73L) // z10
1048 #define CLGIT_ZOPC (unsigned long)(0xecL << 40 | 0x71L) // z10
1049
1050
1051 // Direct Memory Operations
1052
1053 // Compare
1054 #define CLI_ZOPC (unsigned int)(0x95 << 24)
1055 #define CLIY_ZOPC (unsigned long)(0xebL << 40 | 0x55L)
1056 #define CLC_ZOPC (unsigned long)(0xd5L << 40)
1057 #define CLCL_ZOPC (unsigned int)(0x0f << 8)
1058 #define CLCLE_ZOPC (unsigned int)(0xa9 << 24)
1059 #define CLCLU_ZOPC (unsigned long)(0xebL << 40 | 0x8fL)
1060
1061 // Move
1062 #define MVI_ZOPC (unsigned int)(0x92 << 24)
1063 #define MVIY_ZOPC (unsigned long)(0xebL << 40 | 0x52L)
1064 #define MVC_ZOPC (unsigned long)(0xd2L << 40)
1065 #define MVCL_ZOPC (unsigned int)(0x0e << 8)
1066 #define MVCLE_ZOPC (unsigned int)(0xa8 << 24)
1067
1068 // Test
1069 #define TM_ZOPC (unsigned int)(0x91 << 24)
1070 #define TMY_ZOPC (unsigned long)(0xebL << 40 | 0x51L)
1071
1072 // AND
1073 #define NI_ZOPC (unsigned int)(0x94 << 24)
1074 #define NIY_ZOPC (unsigned long)(0xebL << 40 | 0x54L)
1075 #define NC_ZOPC (unsigned long)(0xd4L << 40)
1076
1077 // OR
1078 #define OI_ZOPC (unsigned int)(0x96 << 24)
1079 #define OIY_ZOPC (unsigned long)(0xebL << 40 | 0x56L)
1080 #define OC_ZOPC (unsigned long)(0xd6L << 40)
1081
1082 // XOR
1083 #define XI_ZOPC (unsigned int)(0x97 << 24)
1084 #define XIY_ZOPC (unsigned long)(0xebL << 40 | 0x57L)
1085 #define XC_ZOPC (unsigned long)(0xd7L << 40)
1086
1087 // Search String
1088 #define SRST_ZOPC (unsigned int)(178 << 24 | 94 << 16)
1089 #define SRSTU_ZOPC (unsigned int)(185 << 24 | 190 << 16)
1090
1091 // Translate characters
1092 #define TROO_ZOPC (unsigned int)(0xb9 << 24 | 0x93 << 16)
1093 #define TROT_ZOPC (unsigned int)(0xb9 << 24 | 0x92 << 16)
1094 #define TRTO_ZOPC (unsigned int)(0xb9 << 24 | 0x91 << 16)
1095 #define TRTT_ZOPC (unsigned int)(0xb9 << 24 | 0x90 << 16)
1096
1097
1098 // Miscellaneous Operations
1099
1100 // Execute
1101 #define EX_ZOPC (unsigned int)(68L << 24)
1102 #define EXRL_ZOPC (unsigned long)(0xc6L << 40 | 0x00L << 32) // z10
1103
1104 // Compare and Swap
1105 #define CS_ZOPC (unsigned int)(0xba << 24)
1106 #define CSY_ZOPC (unsigned long)(0xebL << 40 | 0x14L)
1107 #define CSG_ZOPC (unsigned long)(0xebL << 40 | 0x30L)
1108
1109 // Interlocked-Update
1110 #define LAA_ZOPC (unsigned long)(0xebL << 40 | 0xf8L) // z196
1111 #define LAAG_ZOPC (unsigned long)(0xebL << 40 | 0xe8L) // z196
1112 #define LAAL_ZOPC (unsigned long)(0xebL << 40 | 0xfaL) // z196
1113 #define LAALG_ZOPC (unsigned long)(0xebL << 40 | 0xeaL) // z196
1114 #define LAN_ZOPC (unsigned long)(0xebL << 40 | 0xf4L) // z196
1115 #define LANG_ZOPC (unsigned long)(0xebL << 40 | 0xe4L) // z196
1116 #define LAX_ZOPC (unsigned long)(0xebL << 40 | 0xf7L) // z196
1117 #define LAXG_ZOPC (unsigned long)(0xebL << 40 | 0xe7L) // z196
1118 #define LAO_ZOPC (unsigned long)(0xebL << 40 | 0xf6L) // z196
1119 #define LAOG_ZOPC (unsigned long)(0xebL << 40 | 0xe6L) // z196
1120
1121 // System Functions
1122 #define STCK_ZOPC (unsigned int)(0xb2 << 24 | 0x05 << 16)
1123 #define STCKF_ZOPC (unsigned int)(0xb2 << 24 | 0x7c << 16)
1124 #define STFLE_ZOPC (unsigned int)(0xb2 << 24 | 0xb0 << 16)
1125 #define ECTG_ZOPC (unsigned long)(0xc8L <<40 | 0x01L << 32) // z10
1126 #define ECAG_ZOPC (unsigned long)(0xebL <<40 | 0x4cL) // z10
1127
1128 // Execution Prediction
1129 #define PFD_ZOPC (unsigned long)(0xe3L <<40 | 0x36L) // z10
1130 #define PFDRL_ZOPC (unsigned long)(0xc6L <<40 | 0x02L << 32) // z10
1131 #define BPP_ZOPC (unsigned long)(0xc7L <<40) // branch prediction preload -- EC12
1132 #define BPRP_ZOPC (unsigned long)(0xc5L <<40) // branch prediction preload -- EC12
1133
1134 // Transaction Control
1135 #define TBEGIN_ZOPC (unsigned long)(0xe560L << 32) // tx begin -- EC12
1136 #define TBEGINC_ZOPC (unsigned long)(0xe561L << 32) // tx begin (constrained) -- EC12
1137 #define TEND_ZOPC (unsigned int)(0xb2f8 << 16) // tx end -- EC12
1138 #define TABORT_ZOPC (unsigned int)(0xb2fc << 16) // tx abort -- EC12
1139 #define ETND_ZOPC (unsigned int)(0xb2ec << 16) // tx nesting depth -- EC12
1140 #define PPA_ZOPC (unsigned int)(0xb2e8 << 16) // tx processor assist -- EC12
1141
1142 // Crypto and Checksum
1143 #define CKSM_ZOPC (unsigned int)(0xb2 << 24 | 0x41 << 16) // checksum. This is NOT CRC32
1144 #define KM_ZOPC (unsigned int)(0xb9 << 24 | 0x2e << 16) // cipher
1145 #define KMC_ZOPC (unsigned int)(0xb9 << 24 | 0x2f << 16) // cipher
1146 #define KIMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3e << 16) // SHA (msg digest)
1147 #define KLMD_ZOPC (unsigned int)(0xb9 << 24 | 0x3f << 16) // SHA (msg digest)
1148 #define KMAC_ZOPC (unsigned int)(0xb9 << 24 | 0x1e << 16) // Message Authentication Code
1149
1150 // Various
1151 #define TCEB_ZOPC (unsigned long)(237L << 40 | 16)
1152 #define TCDB_ZOPC (unsigned long)(237L << 40 | 17)
1153 #define TAM_ZOPC (unsigned long)(267)
1154
1155 #define FLOGR_ZOPC (unsigned int)(0xb9 << 24 | 0x83 << 16)
1156 #define POPCNT_ZOPC (unsigned int)(0xb9e1 << 16)
1157 #define AHHHR_ZOPC (unsigned int)(0xb9c8 << 16)
1158 #define AHHLR_ZOPC (unsigned int)(0xb9d8 << 16)
1159
1160
1161 // OpCode field masks
1162
1163 #define RI_MASK (unsigned int)(0xff << 24 | 0x0f << 16)
1164 #define RRE_MASK (unsigned int)(0xff << 24 | 0xff << 16)
1165 #define RSI_MASK (unsigned int)(0xff << 24)
1166 #define RIE_MASK (unsigned long)(0xffL << 40 | 0xffL)
1167 #define RIL_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32)
1168
1169 #define BASR_MASK (unsigned int)(0xff << 8)
1170 #define BCR_MASK (unsigned int)(0xff << 8)
1171 #define BRC_MASK (unsigned int)(0xff << 24 | 0x0f << 16)
1172 #define LGHI_MASK (unsigned int)(0xff << 24 | 0x0f << 16)
1173 #define LLI_MASK (unsigned int)(0xff << 24 | 0x0f << 16)
1174 #define II_MASK (unsigned int)(0xff << 24 | 0x0f << 16)
1175 #define LLIF_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32)
1176 #define IIF_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32)
1177 #define BRASL_MASK (unsigned long)(0xffL << 40 | 0x0fL << 32)
1178 #define TM_MASK (unsigned int)(0xff << 24)
1179 #define TMY_MASK (unsigned long)(0xffL << 40 | 0xffL)
1180 #define LB_MASK (unsigned long)(0xffL << 40 | 0xffL)
1181 #define LH_MASK (unsigned int)(0xff << 24)
1182 #define L_MASK (unsigned int)(0xff << 24)
1183 #define LY_MASK (unsigned long)(0xffL << 40 | 0xffL)
1184 #define LG_MASK (unsigned long)(0xffL << 40 | 0xffL)
1185 #define LLGH_MASK (unsigned long)(0xffL << 40 | 0xffL)
1186 #define LLGF_MASK (unsigned long)(0xffL << 40 | 0xffL)
1187 #define SLAG_MASK (unsigned long)(0xffL << 40 | 0xffL)
1188 #define LARL_MASK (unsigned long)(0xff0fL << 32)
1189 #define LGRL_MASK (unsigned long)(0xff0fL << 32)
1190 #define LE_MASK (unsigned int)(0xff << 24)
1191 #define LD_MASK (unsigned int)(0xff << 24)
1192 #define ST_MASK (unsigned int)(0xff << 24)
1193 #define STC_MASK (unsigned int)(0xff << 24)
1194 #define STG_MASK (unsigned long)(0xffL << 40 | 0xffL)
1195 #define STH_MASK (unsigned int)(0xff << 24)
1196 #define STE_MASK (unsigned int)(0xff << 24)
1197 #define STD_MASK (unsigned int)(0xff << 24)
1198 #define CMPBRANCH_MASK (unsigned long)(0xffL << 40 | 0xffL)
1199 #define REL_LONG_MASK (unsigned long)(0xff0fL << 32)
1200
1201 public:
1202 // Condition code masks. Details:
1203 // - Mask bit#3 must be zero for all compare and branch/trap instructions to ensure
1204 // future compatibility.
1205 // - For all arithmetic instructions which set the condition code, mask bit#3
1206 // indicates overflow ("unordered" in float operations).
1207 // - "unordered" float comparison results have to be treated as low.
1208 // - When overflow/unordered is detected, none of the branch conditions is true,
1209 // except for bcondOverflow/bcondNotOrdered and bcondAlways.
1210 // - For INT comparisons, the inverse condition can be calculated as (14-cond).
1211 // - For FLOAT comparisons, the inverse condition can be calculated as (15-cond).
1212 enum branch_condition {
1213 bcondNever = 0,
1214 bcondAlways = 15,
1215
1216 // Specific names. Make use of lightweight sync.
1217 // Full and lightweight sync operation.
1218 bcondFullSync = 15,
1219 bcondLightSync = 14,
1220 bcondNop = 0,
1221
1222 // arithmetic compare instructions
1223 // arithmetic load and test, insert instructions
1224 // Mask bit#3 must be zero for future compatibility.
1225 bcondEqual = 8,
1226 bcondNotEqual = 6,
1227 bcondLow = 4,
1228 bcondNotLow = 10,
1229 bcondHigh = 2,
1230 bcondNotHigh = 12,
1231 // arithmetic calculation instructions
1232 // Mask bit#3 indicates overflow if detected by instr.
1233 // Mask bit#3 = 0 (overflow is not handled by compiler).
1234 bcondOverflow = 1,
1235 bcondNotOverflow = 14,
1236 bcondZero = bcondEqual,
1237 bcondNotZero = bcondNotEqual,
1238 bcondNegative = bcondLow,
1239 bcondNotNegative = bcondNotLow,
1240 bcondPositive = bcondHigh,
1241 bcondNotPositive = bcondNotHigh,
1242 bcondNotOrdered = 1, // float comparisons
1243 bcondOrdered = 14, // float comparisons
1244 bcondLowOrNotOrdered = bcondLow|bcondNotOrdered, // float comparisons
1245 bcondHighOrNotOrdered = bcondHigh|bcondNotOrdered, // float comparisons
1246 // unsigned arithmetic calculation instructions
1247 // Mask bit#0 is not used by these instructions.
1248 // There is no indication of overflow for these instr.
1249 bcondLogZero = 2,
1250 bcondLogNotZero = 5,
1251 bcondLogNotZero_Borrow = 4,
1252 bcondLogNotZero_NoBorrow = 1,
1253 // string search instructions
1254 bcondFound = 4,
1255 bcondNotFound = 2,
1256 bcondInterrupted = 1,
1257 // bit test instructions
1258 bcondAllZero = 8,
1259 bcondMixed = 6,
1260 bcondAllOne = 1,
1261 bcondNotAllZero = 7 // for tmll
1262 };
1263
1264 enum Condition {
1265 // z/Architecture
1266 negative = 0,
1267 less = 0,
1268 positive = 1,
1269 greater = 1,
1270 zero = 2,
1271 equal = 2,
1272 summary_overflow = 3,
1273 };
1274
1275 // Rounding mode for float-2-int conversions.
1276 enum RoundingMode {
1277 current_mode = 0, // Mode taken from FPC register.
1278 biased_to_nearest = 1,
1279 to_nearest = 4,
1280 to_zero = 5,
1281 to_plus_infinity = 6,
1282 to_minus_infinity = 7
1283 };
1284
1285 // Inverse condition code, i.e. determine "15 - cc" for a given condition code cc.
1286 static branch_condition inverse_condition(branch_condition cc);
1287 static branch_condition inverse_float_condition(branch_condition cc);
1288
1289
1290 //-----------------------------------------------
1291 // instruction property getter methods
1292 //-----------------------------------------------
1293
1294 // Calculate length of instruction.
1295 static int instr_len(unsigned char *instr);
1296
1297 // Longest instructions are 6 bytes on z/Architecture.
1298 static int instr_maxlen() { return 6; }
1299
1300 // Average instruction is 4 bytes on z/Architecture (just a guess).
1301 static int instr_avglen() { return 4; }
1302
1303 // Shortest instructions are 2 bytes on z/Architecture.
1304 static int instr_minlen() { return 2; }
1305
1306 // Move instruction at pc right-justified into passed long int.
1307 // Return instr len in bytes as function result.
1308 static unsigned int get_instruction(unsigned char *pc, unsigned long *instr);
1309
1310 // Move instruction in passed (long int) into storage at pc.
1311 // This code is _NOT_ MT-safe!!
1312 static void set_instruction(unsigned char *pc, unsigned long instr, unsigned int len) {
1313 memcpy(pc, ((unsigned char *)&instr)+sizeof(unsigned long)-len, len);
1314 }
1315
1316
1317 //------------------------------------------
1318 // instruction field test methods
1319 //------------------------------------------
1320
1321 // Only used once in s390.ad to implement Matcher::is_short_branch_offset().
1322 static bool is_within_range_of_RelAddr16(address target, address origin) {
1323 return RelAddr::is_in_range_of_RelAddr16(target, origin);
1324 }
1325
1326
1327 //----------------------------------
1328 // some diagnostic output
1329 //----------------------------------
1330
1331 static void print_dbg_msg(outputStream* out, unsigned long inst, const char* msg, int ilen) PRODUCT_RETURN;
1332 static void dump_code_range(outputStream* out, address pc, const unsigned int range, const char* msg = " ") PRODUCT_RETURN;
1333
1334 protected:
1335
1336 //-------------------------------------------------------
1337 // instruction field helper methods (internal)
1338 //-------------------------------------------------------
1339
1340 // Return a mask of 1s between hi_bit and lo_bit (inclusive).
1341 static long fmask(unsigned int hi_bit, unsigned int lo_bit) {
1342 assert(hi_bit >= lo_bit && hi_bit < 48, "bad bits");
1343 return ((1L<<(hi_bit-lo_bit+1)) - 1) << lo_bit;
1344 }
1345
1346 // extract u_field
1347 // unsigned value
1348 static long inv_u_field(long x, int hi_bit, int lo_bit) {
1349 return (x & fmask(hi_bit, lo_bit)) >> lo_bit;
1350 }
1351
1352 // extract s_field
1353 // Signed value, may need sign extension.
1354 static long inv_s_field(long x, int hi_bit, int lo_bit) {
1355 x = inv_u_field(x, hi_bit, lo_bit);
1356 // Highest extracted bit set -> sign extension.
1357 return (x >= (1L<<(hi_bit-lo_bit)) ? x | ((-1L)<<(hi_bit-lo_bit)) : x);
1358 }
1359
1360 // Extract primary opcode from instruction.
1361 static int z_inv_op(int x) { return inv_u_field(x, 31, 24); }
1362 static int z_inv_op(long x) { return inv_u_field(x, 47, 40); }
1363
1364 static int inv_reg( long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-4); } // Regs are encoded in 4 bits.
1365 static int inv_mask(long x, int s, int len) { return inv_u_field(x, (len-s)-1, (len-s)-8); } // Mask is 8 bits long.
1366 static int inv_simm16_48(long x) { return (inv_s_field(x, 31, 16)); } // 6-byte instructions only
1367 static int inv_simm16(long x) { return (inv_s_field(x, 15, 0)); } // 4-byte instructions only
1368 static int inv_simm20(long x) { return (inv_u_field(x, 27, 16) | // 6-byte instructions only
1369 inv_s_field(x, 15, 8)<<12); }
1370 static int inv_simm32(long x) { return (inv_s_field(x, 31, 0)); } // 6-byte instructions only
1371 static int inv_uimm12(long x) { return (inv_u_field(x, 11, 0)); } // 4-byte instructions only
1372
1373 // Encode u_field from long value.
1374 static long u_field(long x, int hi_bit, int lo_bit) {
1375 long r = x << lo_bit;
1376 assert((r & ~fmask(hi_bit, lo_bit)) == 0, "value out of range");
1377 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking");
1378 return r;
1379 }
1380
1381 public:
1382
1383 //--------------------------------------------------
1384 // instruction field construction methods
1385 //--------------------------------------------------
1386
1387 // Compute relative address (32 bit) for branch.
1388 // Only used once in nativeInst_s390.cpp.
1389 static intptr_t z_pcrel_off(address dest, address pc) {
1390 return RelAddr::pcrel_off32(dest, pc);
1391 }
1392
1393 // Extract 20-bit signed displacement.
1394 // Only used in disassembler_s390.cpp for temp enhancements.
1395 static int inv_simm20_xx(address iLoc) {
1396 unsigned long instr = 0;
1397 unsigned long iLen = get_instruction(iLoc, &instr);
1398 return inv_simm20(instr);
1399 }
1400
1401 // unsigned immediate, in low bits, nbits long
1402 static long uimm(long x, int nbits) {
1403 assert(Immediate::is_uimm(x, nbits), "unsigned constant out of range");
1404 return x & fmask(nbits - 1, 0);
1405 }
1406
1407 // Cast '1' to long to avoid sign extension if nbits = 32.
1408 // signed immediate, in low bits, nbits long
1409 static long simm(long x, int nbits) {
1410 assert(Immediate::is_simm(x, nbits), "value out of range");
1411 return x & fmask(nbits - 1, 0);
1412 }
1413
1414 static long imm(int64_t x, int nbits) {
1415 // Assert that x can be represented with nbits bits ignoring the sign bits,
1416 // i.e. the more higher bits should all be 0 or 1.
1417 assert((x >> nbits) == 0 || (x >> nbits) == -1, "value out of range");
1418 return x & fmask(nbits-1, 0);
1419 }
1420
1421 // A 20-bit displacement is only in instructions of the
1422 // RSY, RXY, or SIY format. In these instructions, the D
1423 // field consists of a DL (low) field in bit positions 20-31
1424 // and of a DH (high) field in bit positions 32-39. The
1425 // value of the displacement is formed by appending the
1426 // contents of the DH field to the left of the contents of
1427 // the DL field.
1428 static long simm20(int64_t ui20) {
1429 assert(Immediate::is_simm(ui20, 20), "value out of range");
1430 return ( ((ui20 & 0xfffL) << (48-32)) | // DL
1431 (((ui20 >> 12) & 0xffL) << (48-40))); // DH
1432 }
1433
1434 static long reg(Register r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); }
1435 static long reg(int r, int s, int len) { return u_field(r, (len-s)-1, (len-s)-4); }
1436 static long regt(Register r, int s, int len) { return reg(r, s, len); }
1437 static long regz(Register r, int s, int len) { assert(r != Z_R0, "cannot use register R0 in memory access"); return reg(r, s, len); }
1438
1439 static long uimm4( int64_t ui4, int s, int len) { return uimm(ui4, 4) << (len-s-4); }
1440 static long uimm6( int64_t ui6, int s, int len) { return uimm(ui6, 6) << (len-s-6); }
1441 static long uimm8( int64_t ui8, int s, int len) { return uimm(ui8, 8) << (len-s-8); }
1442 static long uimm12(int64_t ui12, int s, int len) { return uimm(ui12, 12) << (len-s-12); }
1443 static long uimm16(int64_t ui16, int s, int len) { return uimm(ui16, 16) << (len-s-16); }
1444 static long uimm32(int64_t ui32, int s, int len) { return uimm((unsigned)ui32, 32) << (len-s-32); } // prevent sign extension
1445
1446 static long simm8( int64_t si8, int s, int len) { return simm(si8, 8) << (len-s-8); }
1447 static long simm12(int64_t si12, int s, int len) { return simm(si12, 12) << (len-s-12); }
1448 static long simm16(int64_t si16, int s, int len) { return simm(si16, 16) << (len-s-16); }
1449 static long simm24(int64_t si24, int s, int len) { return simm(si24, 24) << (len-s-24); }
1450 static long simm32(int64_t si32, int s, int len) { return simm(si32, 32) << (len-s-32); }
1451
1452 static long imm8( int64_t i8, int s, int len) { return imm(i8, 8) << (len-s-8); }
1453 static long imm12(int64_t i12, int s, int len) { return imm(i12, 12) << (len-s-12); }
1454 static long imm16(int64_t i16, int s, int len) { return imm(i16, 16) << (len-s-16); }
1455 static long imm24(int64_t i24, int s, int len) { return imm(i24, 24) << (len-s-24); }
1456 static long imm32(int64_t i32, int s, int len) { return imm(i32, 32) << (len-s-32); }
1457
1458 static long fregt(FloatRegister r, int s, int len) { return freg(r,s,len); }
1459 static long freg( FloatRegister r, int s, int len) { return u_field(r->encoding(), (len-s)-1, (len-s)-4); }
1460
1461 // Rounding mode for float-2-int conversions.
1462 static long rounding_mode(RoundingMode m, int s, int len) {
1463 assert(m != 2 && m != 3, "invalid mode");
1464 return uimm(m, 4) << (len-s-4);
1465 }
1466
1467 //--------------------------------------------
1468 // instruction field getter methods
1469 //--------------------------------------------
1470
1471 static int get_imm32(address a, int instruction_number) {
1472 int imm;
1473 int *p =((int *)(a + 2 + 6 * instruction_number));
1474 imm = *p;
1475 return imm;
1476 }
1477
1478 static short get_imm16(address a, int instruction_number) {
1479 short imm;
1480 short *p =((short *)a) + 2 * instruction_number + 1;
1481 imm = *p;
1482 return imm;
1483 }
1484
1485
1486 //--------------------------------------------
1487 // instruction field setter methods
1488 //--------------------------------------------
1489
1490 static void set_imm32(address a, int64_t s) {
1491 assert(Immediate::is_simm32(s) || Immediate::is_uimm32(s), "to big");
1492 int* p = (int *) (a + 2);
1493 *p = s;
1494 }
1495
1496 static void set_imm16(int* instr, int64_t s) {
1497 assert(Immediate::is_simm16(s) || Immediate::is_uimm16(s), "to big");
1498 short* p = ((short *)instr) + 1;
1499 *p = s;
1500 }
1501
1502 public:
1503
1504 static unsigned int align(unsigned int x, unsigned int a) { return ((x + (a - 1)) & ~(a - 1)); }
1505 static bool is_aligned(unsigned int x, unsigned int a) { return (0 == x % a); }
1506
1507 inline void emit_16(int x);
1508 inline void emit_32(int x);
1509 inline void emit_48(long x);
1510
1511 // Compare and control flow instructions
1512 // =====================================
1513
1514 // See also commodity routines compare64_and_branch(), compare32_and_branch().
1515
1516 // compare instructions
1517 // compare register
1518 inline void z_cr( Register r1, Register r2); // compare (r1, r2) ; int32
1519 inline void z_cgr( Register r1, Register r2); // compare (r1, r2) ; int64
1520 inline void z_cgfr(Register r1, Register r2); // compare (r1, r2) ; int64 <--> int32
1521 // compare immediate
1522 inline void z_chi( Register r1, int64_t i2); // compare (r1, i2_imm16) ; int32
1523 inline void z_cfi( Register r1, int64_t i2); // compare (r1, i2_imm32) ; int32
1524 inline void z_cghi(Register r1, int64_t i2); // compare (r1, i2_imm16) ; int64
1525 inline void z_cgfi(Register r1, int64_t i2); // compare (r1, i2_imm32) ; int64
1526 // compare memory
1527 inline void z_ch( Register r1, const Address &a); // compare (r1, *(a)) ; int32 <--> int16
1528 inline void z_ch( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm12+x2+b2)) ; int32 <--> int16
1529 inline void z_c( Register r1, const Address &a); // compare (r1, *(a)) ; int32
1530 inline void z_c( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm12+x2+b2)) ; int32
1531 inline void z_cy( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; int32
1532 inline void z_cy( Register r1, int64_t d2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; int32
1533 inline void z_cy( Register r1, const Address& a); // compare (r1, *(a)) ; int32
1534 //inline void z_cgf(Register r1,const Address &a); // compare (r1, *(a)) ; int64 <--> int32
1535 //inline void z_cgf(Register r1,int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2)) ; int64 <--> int32
1536 inline void z_cg( Register r1, const Address &a); // compare (r1, *(a)) ; int64
1537 inline void z_cg( Register r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm20+x2+b2)) ; int64
1538
1539 // compare logical instructions
1540 // compare register
1541 inline void z_clr( Register r1, Register r2); // compare (r1, r2) ; uint32
1542 inline void z_clgr( Register r1, Register r2); // compare (r1, r2) ; uint64
1543 // compare immediate
1544 inline void z_clfi( Register r1, int64_t i2); // compare (r1, i2_uimm32) ; uint32
1545 inline void z_clgfi(Register r1, int64_t i2); // compare (r1, i2_uimm32) ; uint64
1546 inline void z_cl( Register r1, const Address &a); // compare (r1, *(a) ; uint32
1547 inline void z_cl( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm12+x2+b2) ; uint32
1548 inline void z_cly( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_uimm20+x2+b2)) ; uint32
1549 inline void z_cly( Register r1, int64_t d2, Register b2); // compare (r1, *(d2_uimm20+x2+b2)) ; uint32
1550 inline void z_cly( Register r1, const Address& a); // compare (r1, *(a)) ; uint32
1551 inline void z_clg( Register r1, const Address &a); // compare (r1, *(a) ; uint64
1552 inline void z_clg( Register r1, int64_t d2, Register x2, Register b2);// compare (r1, *(d2_imm20+x2+b2) ; uint64
1553
1554 // test under mask
1555 inline void z_tmll(Register r1, int64_t i2); // test under mask, see docu
1556 inline void z_tmlh(Register r1, int64_t i2); // test under mask, see docu
1557 inline void z_tmhl(Register r1, int64_t i2); // test under mask, see docu
1558 inline void z_tmhh(Register r1, int64_t i2); // test under mask, see docu
1559
1560 // branch instructions
1561 inline void z_bc( branch_condition m1, int64_t d2, Register x2, Register b2);// branch m1 ? pc = (d2_uimm12+x2+b2)
1562 inline void z_bcr( branch_condition m1, Register r2); // branch (m1 && r2!=R0) ? pc = r2
1563 inline void z_brc( branch_condition i1, int64_t i2); // branch i1 ? pc = pc + i2_imm16
1564 inline void z_brc( branch_condition i1, address a); // branch i1 ? pc = a
1565 inline void z_brc( branch_condition i1, Label& L); // branch i1 ? pc = Label
1566 //inline void z_brcl(branch_condition i1, int64_t i2); // branch i1 ? pc = pc + i2_imm32
1567 inline void z_brcl(branch_condition i1, address a); // branch i1 ? pc = a
1568 inline void z_brcl(branch_condition i1, Label& L); // branch i1 ? pc = Label
1569 inline void z_bctgr(Register r1, Register r2); // branch on count r1 -= 1; (r1!=0) ? pc = r2 ; r1 is int64
1570
1571 // branch unconditional / always
1572 inline void z_br(Register r2); // branch to r2, nop if r2 == Z_R0
1573
1574
1575 // See also commodity routines compare64_and_branch(), compare32_and_branch().
1576 // signed comparison and branch
1577 inline void z_crb( Register r1, Register r2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 r2) ? goto b4+d4 ; int32 -- z10
1578 inline void z_cgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 r2) ? goto b4+d4 ; int64 -- z10
1579 inline void z_crj( Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; int32 -- z10
1580 inline void z_crj( Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; int32 -- z10
1581 inline void z_cgrj(Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; int64 -- z10
1582 inline void z_cgrj(Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; int64 -- z10
1583 inline void z_cib( Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_imm8) ? goto b4+d4 ; int32 -- z10
1584 inline void z_cgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_imm8) ? goto b4+d4 ; int64 -- z10
1585 inline void z_cij( Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_imm8) ? goto L ; int32 -- z10
1586 inline void z_cij( Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_imm8) ? goto (pc+a4<<1) ; int32 -- z10
1587 inline void z_cgij(Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_imm8) ? goto L ; int64 -- z10
1588 inline void z_cgij(Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_imm8) ? goto (pc+a4<<1) ; int64 -- z10
1589 // unsigned comparison and branch
1590 inline void z_clrb( Register r1, Register r2, branch_condition m3, int64_t d4, Register b4);// (r1 m3 r2) ? goto b4+d4 ; uint32 -- z10
1591 inline void z_clgrb(Register r1, Register r2, branch_condition m3, int64_t d4, Register b4);// (r1 m3 r2) ? goto b4+d4 ; uint64 -- z10
1592 inline void z_clrj( Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; uint32 -- z10
1593 inline void z_clrj( Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; uint32 -- z10
1594 inline void z_clgrj(Register r1, Register r2, branch_condition m3, Label& L); // (r1 m3 r2) ? goto L ; uint64 -- z10
1595 inline void z_clgrj(Register r1, Register r2, branch_condition m3, address a4); // (r1 m3 r2) ? goto (pc+a4<<1) ; uint64 -- z10
1596 inline void z_clib( Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_uimm8) ? goto b4+d4 ; uint32 -- z10
1597 inline void z_clgib(Register r1, int64_t i2, branch_condition m3, int64_t d4, Register b4); // (r1 m3 i2_uimm8) ? goto b4+d4 ; uint64 -- z10
1598 inline void z_clij( Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_uimm8) ? goto L ; uint32 -- z10
1599 inline void z_clij( Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_uimm8) ? goto (pc+a4<<1) ; uint32 -- z10
1600 inline void z_clgij(Register r1, int64_t i2, branch_condition m3, Label& L); // (r1 m3 i2_uimm8) ? goto L ; uint64 -- z10
1601 inline void z_clgij(Register r1, int64_t i2, branch_condition m3, address a4); // (r1 m3 i2_uimm8) ? goto (pc+a4<<1) ; uint64 -- z10
1602
1603 // Compare and trap instructions.
1604 // signed comparison
1605 inline void z_crt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; int32 -- z10
1606 inline void z_cgrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; int64 -- z10
1607 inline void z_cit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_imm16) ? trap ; int32 -- z10
1608 inline void z_cgit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_imm16) ? trap ; int64 -- z10
1609 // unsigned comparison
1610 inline void z_clrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; uint32 -- z10
1611 inline void z_clgrt(Register r1, Register r2, int64_t m3); // (r1 m3 r2) ? trap ; uint64 -- z10
1612 inline void z_clfit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_uimm16) ? trap ; uint32 -- z10
1613 inline void z_clgit(Register r1, int64_t i2, int64_t m3); // (r1 m3 i2_uimm16) ? trap ; uint64 -- z10
1614
1615 inline void z_illtrap();
1616 inline void z_illtrap(int id);
1617 inline void z_illtrap_eyecatcher(unsigned short xpattern, unsigned short pattern);
1618
1619
1620 // load address, add for addresses
1621 // ===============================
1622
1623 // The versions without suffix z assert that the base reg is != Z_R0.
1624 // Z_R0 is interpreted as constant '0'. The variants with Address operand
1625 // check this automatically, so no two versions are needed.
1626 inline void z_layz(Register r1, int64_t d2, Register x2, Register b2); // Special version. Allows Z_R0 as base reg.
1627 inline void z_lay(Register r1, const Address &a); // r1 = a
1628 inline void z_lay(Register r1, int64_t d2, Register x2, Register b2); // r1 = d2_imm20+x2+b2
1629 inline void z_laz(Register r1, int64_t d2, Register x2, Register b2); // Special version. Allows Z_R0 as base reg.
1630 inline void z_la(Register r1, const Address &a); // r1 = a ; unsigned immediate!
1631 inline void z_la(Register r1, int64_t d2, Register x2, Register b2); // r1 = d2_uimm12+x2+b2 ; unsigned immediate!
1632 inline void z_larl(Register r1, int64_t i2); // r1 = pc + i2_imm32<<1;
1633 inline void z_larl(Register r1, address a2); // r1 = pc + i2_imm32<<1;
1634
1635 // Load instructions for integers
1636 // ==============================
1637
1638 // Address as base + index + offset
1639 inline void z_lb( Register r1, const Address &a); // load r1 = *(a) ; int32 <- int8
1640 inline void z_lb( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 <- int8
1641 inline void z_lh( Register r1, const Address &a); // load r1 = *(a) ; int32 <- int16
1642 inline void z_lh( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2); int32 <- int16
1643 inline void z_lhy(Register r1, const Address &a); // load r1 = *(a) ; int32 <- int16
1644 inline void z_lhy(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32 <- int16
1645 inline void z_l( Register r1, const Address& a); // load r1 = *(a) ; int32
1646 inline void z_l( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2); int32
1647 inline void z_ly( Register r1, const Address& a); // load r1 = *(a) ; int32
1648 inline void z_ly( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int32
1649
1650 inline void z_lgb(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int8
1651 inline void z_lgb(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int8
1652 inline void z_lgh(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int16
1653 inline void z_lgh(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm12+x2+b2) ; int64 <- int16
1654 inline void z_lgf(Register r1, const Address &a); // load r1 = *(a) ; int64 <- int32
1655 inline void z_lgf(Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int32
1656 inline void z_lg( Register r1, const Address& a); // load r1 = *(a) ; int64 <- int64
1657 inline void z_lg( Register r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; int64 <- int64
1658
1659 // load and test
1660 inline void z_lt( Register r1, const Address &a); // load and test r1 = *(a) ; int32
1661 inline void z_lt( Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int32
1662 inline void z_ltg( Register r1, const Address &a); // load and test r1 = *(a) ; int64
1663 inline void z_ltg( Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int64
1664 inline void z_ltgf(Register r1, const Address &a); // load and test r1 = *(a) ; int64 <- int32
1665 inline void z_ltgf(Register r1, int64_t d2, Register x2, Register b2);// load and test r1 = *(d2_imm20+x2+b2) ; int64 <- int32
1666
1667 // load unsigned integer - zero extended
1668 inline void z_llc( Register r1, const Address& a); // load r1 = *(a) ; uint32 <- uint8
1669 inline void z_llc( Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint32 <- uint8
1670 inline void z_llh( Register r1, const Address& a); // load r1 = *(a) ; uint32 <- uint16
1671 inline void z_llh( Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint32 <- uint16
1672 inline void z_llgc(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint8
1673 inline void z_llgc(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint8
1674 inline void z_llgc( Register r1, int64_t d2, Register b2); // load r1 = *(d2_imm20+b2) ; uint64 <- uint8
1675 inline void z_llgh(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint16
1676 inline void z_llgh(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint16
1677 inline void z_llgf(Register r1, const Address& a); // load r1 = *(a) ; uint64 <- uint32
1678 inline void z_llgf(Register r1, int64_t d2, Register x2, Register b2);// load r1 = *(d2_imm20+x2+b2) ; uint64 <- uint32
1679
1680 // pc relative addressing
1681 inline void z_lhrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int32 <- int16 -- z10
1682 inline void z_lrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int32 -- z10
1683 inline void z_lghrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 <- int16 -- z10
1684 inline void z_lgfrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 <- int32 -- z10
1685 inline void z_lgrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; int64 -- z10
1686
1687 inline void z_llhrl( Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint32 <- uint16 -- z10
1688 inline void z_llghrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint64 <- uint16 -- z10
1689 inline void z_llgfrl(Register r1, int64_t i2); // load r1 = *(pc + i2_imm32<<1) ; uint64 <- uint32 -- z10
1690
1691 // Store instructions for integers
1692 // ===============================
1693
1694 // Address as base + index + offset
1695 inline void z_stc( Register r1, const Address &d); // store *(a) = r1 ; int8
1696 inline void z_stc( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int8
1697 inline void z_stcy(Register r1, const Address &d); // store *(a) = r1 ; int8
1698 inline void z_stcy(Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int8
1699 inline void z_sth( Register r1, const Address &d); // store *(a) = r1 ; int16
1700 inline void z_sth( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int16
1701 inline void z_sthy(Register r1, const Address &d); // store *(a) = r1 ; int16
1702 inline void z_sthy(Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int16
1703 inline void z_st( Register r1, const Address &d); // store *(a) = r1 ; int32
1704 inline void z_st( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int32
1705 inline void z_sty( Register r1, const Address &d); // store *(a) = r1 ; int32
1706 inline void z_sty( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; int32
1707 inline void z_stg( Register r1, const Address &d); // store *(a) = r1 ; int64
1708 inline void z_stg( Register r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; int64
1709
1710 inline void z_stcm( Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask
1711 inline void z_stcmy(Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask
1712 inline void z_stcmh(Register r1, int64_t m3, int64_t d2, Register b2); // store character under mask
1713
1714 // pc relative addressing
1715 inline void z_sthrl(Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int16 -- z10
1716 inline void z_strl( Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int32 -- z10
1717 inline void z_stgrl(Register r1, int64_t i2); // store *(pc + i2_imm32<<1) = r1 ; int64 -- z10
1718
1719
1720 // Load and store immediates
1721 // =========================
1722
1723 // load immediate
1724 inline void z_lhi( Register r1, int64_t i2); // r1 = i2_imm16 ; int32 <- int16
1725 inline void z_lghi(Register r1, int64_t i2); // r1 = i2_imm16 ; int64 <- int16
1726 inline void z_lgfi(Register r1, int64_t i2); // r1 = i2_imm32 ; int64 <- int32
1727
1728 inline void z_llihf(Register r1, int64_t i2); // r1 = i2_imm32 ; uint64 <- (uint32<<32)
1729 inline void z_llilf(Register r1, int64_t i2); // r1 = i2_imm32 ; uint64 <- uint32
1730 inline void z_llihh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<48)
1731 inline void z_llihl(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<32)
1732 inline void z_llilh(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- (uint16<<16)
1733 inline void z_llill(Register r1, int64_t i2); // r1 = i2_imm16 ; uint64 <- uint16
1734
1735 // insert immediate
1736 inline void z_ic( Register r1, int64_t d2, Register x2, Register b2); // insert character
1737 inline void z_icy( Register r1, int64_t d2, Register x2, Register b2); // insert character
1738 inline void z_icm( Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask
1739 inline void z_icmy(Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask
1740 inline void z_icmh(Register r1, int64_t m3, int64_t d2, Register b2); // insert character under mask
1741
1742 inline void z_iihh(Register r1, int64_t i2); // insert immediate r1[ 0-15] = i2_imm16
1743 inline void z_iihl(Register r1, int64_t i2); // insert immediate r1[16-31] = i2_imm16
1744 inline void z_iilh(Register r1, int64_t i2); // insert immediate r1[32-47] = i2_imm16
1745 inline void z_iill(Register r1, int64_t i2); // insert immediate r1[48-63] = i2_imm16
1746 inline void z_iihf(Register r1, int64_t i2); // insert immediate r1[32-63] = i2_imm32
1747 inline void z_iilf(Register r1, int64_t i2); // insert immediate r1[ 0-31] = i2_imm32
1748
1749 // store immediate
1750 inline void z_mvhhi(const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int16
1751 inline void z_mvhhi(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int16
1752 inline void z_mvhi( const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int32
1753 inline void z_mvhi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int32
1754 inline void z_mvghi(const Address &d, int64_t i2); // store *(d) = i2_imm16 ; int64
1755 inline void z_mvghi(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm16 ; int64
1756
1757 // Move and Convert instructions
1758 // =============================
1759
1760 // move, sign extend
1761 inline void z_lbr(Register r1, Register r2); // move r1 = r2 ; int32 <- int8
1762 inline void z_lhr( Register r1, Register r2); // move r1 = r2 ; int32 <- int16
1763 inline void z_lr(Register r1, Register r2); // move r1 = r2 ; int32, no sign extension
1764 inline void z_lgbr(Register r1, Register r2); // move r1 = r2 ; int64 <- int8
1765 inline void z_lghr(Register r1, Register r2); // move r1 = r2 ; int64 <- int16
1766 inline void z_lgfr(Register r1, Register r2); // move r1 = r2 ; int64 <- int32
1767 inline void z_lgr(Register r1, Register r2); // move r1 = r2 ; int64
1768 // move, zero extend
1769 inline void z_llhr( Register r1, Register r2); // move r1 = r2 ; uint32 <- uint16
1770 inline void z_llgcr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint8
1771 inline void z_llghr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint16
1772 inline void z_llgfr(Register r1, Register r2); // move r1 = r2 ; uint64 <- uint32
1773
1774 // move and test register
1775 inline void z_ltr(Register r1, Register r2); // load/move and test r1 = r2; int32
1776 inline void z_ltgr(Register r1, Register r2); // load/move and test r1 = r2; int64
1777 inline void z_ltgfr(Register r1, Register r2); // load/move and test r1 = r2; int64 <-- int32
1778
1779 // move and byte-reverse
1780 inline void z_lrvr( Register r1, Register r2); // move and reverse byte order r1 = r2; int32
1781 inline void z_lrvgr(Register r1, Register r2); // move and reverse byte order r1 = r2; int64
1782
1783
1784 // Arithmetic instructions (Integer only)
1785 // ======================================
1786 // For float arithmetic instructions scroll further down
1787 // Add logical differs in the condition codes set!
1788
1789 // add registers
1790 inline void z_ar( Register r1, Register r2); // add r1 = r1 + r2 ; int32
1791 inline void z_agr( Register r1, Register r2); // add r1 = r1 + r2 ; int64
1792 inline void z_agfr( Register r1, Register r2); // add r1 = r1 + r2 ; int64 <- int32
1793 inline void z_ark( Register r1, Register r2, Register r3); // add r1 = r2 + r3 ; int32
1794 inline void z_agrk( Register r1, Register r2, Register r3); // add r1 = r2 + r3 ; int64
1795
1796 inline void z_alr( Register r1, Register r2); // add logical r1 = r1 + r2 ; int32
1797 inline void z_algr( Register r1, Register r2); // add logical r1 = r1 + r2 ; int64
1798 inline void z_algfr(Register r1, Register r2); // add logical r1 = r1 + r2 ; int64 <- int32
1799 inline void z_alrk( Register r1, Register r2, Register r3); // add logical r1 = r2 + r3 ; int32
1800 inline void z_algrk(Register r1, Register r2, Register r3); // add logical r1 = r2 + r3 ; int64
1801 inline void z_alcgr(Register r1, Register r2); // add logical with carry r1 = r1 + r2 + c ; int64
1802
1803 // add immediate
1804 inline void z_ahi( Register r1, int64_t i2); // add r1 = r1 + i2_imm16 ; int32
1805 inline void z_afi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32
1806 inline void z_alfi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32
1807 inline void z_aghi( Register r1, int64_t i2); // add logical r1 = r1 + i2_imm16 ; int64
1808 inline void z_agfi( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int64
1809 inline void z_algfi(Register r1, int64_t i2); // add logical r1 = r1 + i2_imm32 ; int64
1810 inline void z_ahik( Register r1, Register r3, int64_t i2); // add r1 = r3 + i2_imm16 ; int32
1811 inline void z_aghik(Register r1, Register r3, int64_t i2); // add r1 = r3 + i2_imm16 ; int64
1812 inline void z_aih( Register r1, int64_t i2); // add r1 = r1 + i2_imm32 ; int32 (HiWord)
1813
1814 // add memory
1815 inline void z_a( Register r1, int64_t d2, Register x2, Register b2); // add r1 = r1 + *(d2_uimm12+s2+b2) ; int32
1816 inline void z_ay( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+s2+b2) ; int32
1817 inline void z_ag( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+s2+b2) ; int64
1818 inline void z_agf( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 <- int32
1819 inline void z_al( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_uimm12+x2+b2) ; int32
1820 inline void z_aly( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int32
1821 inline void z_alg( Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64
1822 inline void z_algf(Register r1, int64_t d2, Register x2, Register b2);// add r1 = r1 + *(d2_imm20+x2+b2) ; int64 <- int32
1823 inline void z_a( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32
1824 inline void z_ay( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32
1825 inline void z_al( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32
1826 inline void z_aly( Register r1, const Address& a); // add r1 = r1 + *(a) ; int32
1827 inline void z_ag( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64
1828 inline void z_agf( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 <- int32
1829 inline void z_alg( Register r1, const Address& a); // add r1 = r1 + *(a) ; int64
1830 inline void z_algf(Register r1, const Address& a); // add r1 = r1 + *(a) ; int64 <- int32
1831
1832
1833 inline void z_alhsik( Register r1, Register r3, int64_t i2); // add logical r1 = r3 + i2_imm16 ; int32
1834 inline void z_alghsik(Register r1, Register r3, int64_t i2); // add logical r1 = r3 + i2_imm16 ; int64
1835
1836 inline void z_asi( int64_t d1, Register b1, int64_t i2); // add *(d1_imm20+b1) += i2_imm8 ; int32 -- z10
1837 inline void z_agsi( int64_t d1, Register b1, int64_t i2); // add *(d1_imm20+b1) += i2_imm8 ; int64 -- z10
1838 inline void z_alsi( int64_t d1, Register b1, int64_t i2); // add logical *(d1_imm20+b1) += i2_imm8 ; uint32 -- z10
1839 inline void z_algsi(int64_t d1, Register b1, int64_t i2); // add logical *(d1_imm20+b1) += i2_imm8 ; uint64 -- z10
1840 inline void z_asi( const Address& d, int64_t i2); // add *(d) += i2_imm8 ; int32 -- z10
1841 inline void z_agsi( const Address& d, int64_t i2); // add *(d) += i2_imm8 ; int64 -- z10
1842 inline void z_alsi( const Address& d, int64_t i2); // add logical *(d) += i2_imm8 ; uint32 -- z10
1843 inline void z_algsi(const Address& d, int64_t i2); // add logical *(d) += i2_imm8 ; uint64 -- z10
1844
1845 // negate
1846 inline void z_lcr( Register r1, Register r2 = noreg); // neg r1 = -r2 ; int32
1847 inline void z_lcgr( Register r1, Register r2 = noreg); // neg r1 = -r2 ; int64
1848 inline void z_lcgfr(Register r1, Register r2); // neg r1 = -r2 ; int64 <- int32
1849 inline void z_lnr( Register r1, Register r2 = noreg); // neg r1 = -|r2| ; int32
1850 inline void z_lngr( Register r1, Register r2 = noreg); // neg r1 = -|r2| ; int64
1851 inline void z_lngfr(Register r1, Register r2); // neg r1 = -|r2| ; int64 <- int32
1852
1853 // subtract intstructions
1854 // sub registers
1855 inline void z_sr( Register r1, Register r2); // sub r1 = r1 - r2 ; int32
1856 inline void z_sgr( Register r1, Register r2); // sub r1 = r1 - r2 ; int64
1857 inline void z_sgfr( Register r1, Register r2); // sub r1 = r1 - r2 ; int64 <- int32
1858 inline void z_srk( Register r1, Register r2, Register r3); // sub r1 = r2 - r3 ; int32
1859 inline void z_sgrk( Register r1, Register r2, Register r3); // sub r1 = r2 - r3 ; int64
1860
1861 inline void z_slr( Register r1, Register r2); // sub logical r1 = r1 - r2 ; int32
1862 inline void z_slgr( Register r1, Register r2); // sub logical r1 = r1 - r2 ; int64
1863 inline void z_slgfr(Register r1, Register r2); // sub logical r1 = r1 - r2 ; int64 <- int32
1864 inline void z_slrk( Register r1, Register r2, Register r3); // sub logical r1 = r2 - r3 ; int32
1865 inline void z_slgrk(Register r1, Register r2, Register r3); // sub logical r1 = r2 - r3 ; int64
1866 inline void z_slfi( Register r1, int64_t i2); // sub logical r1 = r1 - i2_uimm32 ; int32
1867 inline void z_slgfi(Register r1, int64_t i2); // add logical r1 = r1 - i2_uimm32 ; int64
1868
1869 // sub memory
1870 inline void z_s( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32
1871 inline void z_sy( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 + *(d2_imm20+s2+b2) ; int32
1872 inline void z_sg( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int64
1873 inline void z_sgf( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int64 - int32
1874 inline void z_slg( Register r1, int64_t d2, Register x2, Register b2); // sub logical r1 = r1 - *(d2_imm20+x2+b2) ; uint64
1875 inline void z_slgf(Register r1, int64_t d2, Register x2, Register b2); // sub logical r1 = r1 - *(d2_imm20+x2+b2) ; uint64 - uint32
1876 inline void z_s( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int32
1877 inline void z_sy( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int32
1878 inline void z_sg( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int64
1879 inline void z_sgf( Register r1, const Address& a); // sub r1 = r1 - *(a) ; int64 - int32
1880 inline void z_slg( Register r1, const Address& a); // sub r1 = r1 - *(a) ; uint64
1881 inline void z_slgf(Register r1, const Address& a); // sub r1 = r1 - *(a) ; uint64 - uint32
1882
1883 inline void z_sh( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 - int16
1884 inline void z_shy( Register r1, int64_t d2, Register x2, Register b2); // sub r1 = r1 - *(d2_imm20+x2+b2) ; int32 - int16
1885 inline void z_sh( Register r1, const Address &a); // sub r1 = r1 - *(d2_imm12+x2+b2) ; int32 - int16
1886 inline void z_shy( Register r1, const Address &a); // sub r1 = r1 - *(d2_imm20+x2+b2) ; int32 - int16
1887
1888 // Multiplication instructions
1889 // mul registers
1890 inline void z_msr( Register r1, Register r2); // mul r1 = r1 * r2 ; int32
1891 inline void z_msgr( Register r1, Register r2); // mul r1 = r1 * r2 ; int64
1892 inline void z_msgfr(Register r1, Register r2); // mul r1 = r1 * r2 ; int64 <- int32
1893 inline void z_mlr( Register r1, Register r2); // mul r1 = r1 * r2 ; int32 unsigned
1894 inline void z_mlgr( Register r1, Register r2); // mul r1 = r1 * r2 ; int64 unsigned
1895 // mul register - memory
1896 inline void z_mhy( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2)
1897 inline void z_msy( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2)
1898 inline void z_msg( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2)
1899 inline void z_msgf(Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2)
1900 inline void z_ml( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2)
1901 inline void z_mlg( Register r1, int64_t d2, Register x2, Register b2); // mul r1 = r1 * *(d2+x2+b2)
1902 inline void z_mhy( Register r1, const Address& a); // mul r1 = r1 * *(a)
1903 inline void z_msy( Register r1, const Address& a); // mul r1 = r1 * *(a)
1904 inline void z_msg( Register r1, const Address& a); // mul r1 = r1 * *(a)
1905 inline void z_msgf(Register r1, const Address& a); // mul r1 = r1 * *(a)
1906 inline void z_ml( Register r1, const Address& a); // mul r1 = r1 * *(a)
1907 inline void z_mlg( Register r1, const Address& a); // mul r1 = r1 * *(a)
1908
1909 inline void z_msfi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm32; int32 -- z10
1910 inline void z_msgfi(Register r1, int64_t i2); // mult r1 = r1 * i2_imm32; int64 -- z10
1911 inline void z_mhi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int32
1912 inline void z_mghi( Register r1, int64_t i2); // mult r1 = r1 * i2_imm16; int64
1913
1914 // Division instructions
1915 inline void z_dsgr( Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair!
1916 inline void z_dsgfr(Register r1, Register r2); // div r1 = r1 / r2 ; int64/int32 needs reg pair!
1917
1918
1919 // Logic instructions
1920 // ===================
1921
1922 // and
1923 inline void z_n( Register r1, int64_t d2, Register x2, Register b2);
1924 inline void z_ny( Register r1, int64_t d2, Register x2, Register b2);
1925 inline void z_ng( Register r1, int64_t d2, Register x2, Register b2);
1926 inline void z_n( Register r1, const Address& a);
1927 inline void z_ny( Register r1, const Address& a);
1928 inline void z_ng( Register r1, const Address& a);
1929
1930 inline void z_nr( Register r1, Register r2); // and r1 = r1 & r2 ; int32
1931 inline void z_ngr( Register r1, Register r2); // and r1 = r1 & r2 ; int64
1932 inline void z_nrk( Register r1, Register r2, Register r3); // and r1 = r2 & r3 ; int32
1933 inline void z_ngrk(Register r1, Register r2, Register r3); // and r1 = r2 & r3 ; int64
1934
1935 inline void z_nihh(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 0-15
1936 inline void z_nihl(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 16-31
1937 inline void z_nilh(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 32-47
1938 inline void z_nill(Register r1, int64_t i2); // and r1 = r1 & i2_imm16 ; and only for bits 48-63
1939 inline void z_nihf(Register r1, int64_t i2); // and r1 = r1 & i2_imm32 ; and only for bits 0-31
1940 inline void z_nilf(Register r1, int64_t i2); // and r1 = r1 & i2_imm32 ; and only for bits 32-63 see also MacroAssembler::nilf.
1941
1942 // or
1943 inline void z_o( Register r1, int64_t d2, Register x2, Register b2);
1944 inline void z_oy( Register r1, int64_t d2, Register x2, Register b2);
1945 inline void z_og( Register r1, int64_t d2, Register x2, Register b2);
1946 inline void z_o( Register r1, const Address& a);
1947 inline void z_oy( Register r1, const Address& a);
1948 inline void z_og( Register r1, const Address& a);
1949
1950 inline void z_or( Register r1, Register r2); // or r1 = r1 | r2; int32
1951 inline void z_ogr( Register r1, Register r2); // or r1 = r1 | r2; int64
1952 inline void z_ork( Register r1, Register r2, Register r3); // or r1 = r2 | r3 ; int32
1953 inline void z_ogrk(Register r1, Register r2, Register r3); // or r1 = r2 | r3 ; int64
1954
1955 inline void z_oihh(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 0-15
1956 inline void z_oihl(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 16-31
1957 inline void z_oilh(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 32-47
1958 inline void z_oill(Register r1, int64_t i2); // or r1 = r1 | i2_imm16 ; or only for bits 48-63
1959 inline void z_oihf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 0-31
1960 inline void z_oilf(Register r1, int64_t i2); // or r1 = r1 | i2_imm32 ; or only for bits 32-63
1961
1962 // xor
1963 inline void z_x( Register r1, int64_t d2, Register x2, Register b2);
1964 inline void z_xy( Register r1, int64_t d2, Register x2, Register b2);
1965 inline void z_xg( Register r1, int64_t d2, Register x2, Register b2);
1966 inline void z_x( Register r1, const Address& a);
1967 inline void z_xy( Register r1, const Address& a);
1968 inline void z_xg( Register r1, const Address& a);
1969
1970 inline void z_xr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int32
1971 inline void z_xgr( Register r1, Register r2); // xor r1 = r1 ^ r2 ; int64
1972 inline void z_xrk( Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int32
1973 inline void z_xgrk(Register r1, Register r2, Register r3); // xor r1 = r2 ^ r3 ; int64
1974
1975 inline void z_xihf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 0-31
1976 inline void z_xilf(Register r1, int64_t i2); // xor r1 = r1 ^ i2_imm32 ; or only for bits 32-63
1977
1978 // shift
1979 inline void z_sla( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, only 31 bits shifted, sign preserved!
1980 inline void z_slag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, only 63 bits shifted, sign preserved!
1981 inline void z_sra( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, sign extended
1982 inline void z_srag(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, sign extended
1983 inline void z_sll( Register r1, int64_t d2, Register b2=Z_R0); // shift left r1 = r1 << ((d2+b2)&0x3f) ; int32, zeros added
1984 inline void z_sllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift left r1 = r3 << ((d2+b2)&0x3f) ; int64, zeros added
1985 inline void z_srl( Register r1, int64_t d2, Register b2=Z_R0); // shift right r1 = r1 >> ((d2+b2)&0x3f) ; int32, zero extended
1986 inline void z_srlg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // shift right r1 = r3 >> ((d2+b2)&0x3f) ; int64, zero extended
1987
1988 // rotate
1989 inline void z_rll( Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int32 -- z10
1990 inline void z_rllg(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // rot r1 = r3 << (d2+b2 & 0x3f) ; int64 -- z10
1991
1992 // rotate the AND/XOR/OR/insert
1993 inline void z_rnsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then AND selected bits -- z196
1994 inline void z_rxsbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then XOR selected bits -- z196
1995 inline void z_rosbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool test_only = false); // rotate then OR selected bits -- z196
1996 inline void z_risbg( Register r1, Register r2, int64_t spos3, int64_t epos4, int64_t nrot5, bool zero_rest = false); // rotate then INS selected bits -- z196
1997
1998
1999 // memory-immediate instructions (8-bit immediate)
2000 // ===============================================
2001
2002 inline void z_cli( int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8
2003 inline void z_mvi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8
2004 inline void z_tm( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8
2005 inline void z_ni( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8
2006 inline void z_oi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) |= i2_imm8 ; int8
2007 inline void z_xi( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) ^= i2_imm8 ; int8
2008 inline void z_cliy(int64_t d1, Register b1, int64_t i2); // compare *(d1_imm12+b1) ^= i2_imm8 ; int8
2009 inline void z_mviy(int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) = i2_imm8 ; int8
2010 inline void z_tmy( int64_t d1, Register b1, int64_t i2); // test *(d1_imm12+b1) against mask i2_imm8 ; int8
2011 inline void z_niy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) &= i2_imm8 ; int8
2012 inline void z_oiy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) |= i2_imm8 ; int8
2013 inline void z_xiy( int64_t d1, Register b1, int64_t i2); // store *(d1_imm12+b1) ^= i2_imm8 ; int8
2014 inline void z_cli( const Address& a, int64_t imm8); // compare *(a) ^= imm8 ; int8
2015 inline void z_mvi( const Address& a, int64_t imm8); // store *(a) = imm8 ; int8
2016 inline void z_tm( const Address& a, int64_t imm8); // test *(a) against mask imm8 ; int8
2017 inline void z_ni( const Address& a, int64_t imm8); // store *(a) &= imm8 ; int8
2018 inline void z_oi( const Address& a, int64_t imm8); // store *(a) |= imm8 ; int8
2019 inline void z_xi( const Address& a, int64_t imm8); // store *(a) ^= imm8 ; int8
2020 inline void z_cliy(const Address& a, int64_t imm8); // compare *(a) ^= imm8 ; int8
2021 inline void z_mviy(const Address& a, int64_t imm8); // store *(a) = imm8 ; int8
2022 inline void z_tmy( const Address& a, int64_t imm8); // test *(a) against mask imm8 ; int8
2023 inline void z_niy( const Address& a, int64_t imm8); // store *(a) &= imm8 ; int8
2024 inline void z_oiy( const Address& a, int64_t imm8); // store *(a) |= imm8 ; int8
2025 inline void z_xiy( const Address& a, int64_t imm8); // store *(a) ^= imm8 ; int8
2026
2027
2028 //------------------------------
2029 // Interlocked-Update
2030 //------------------------------
2031 inline void z_laa( Register r1, Register r3, int64_t d2, Register b2); // load and add int32, signed -- z196
2032 inline void z_laag( Register r1, Register r3, int64_t d2, Register b2); // load and add int64, signed -- z196
2033 inline void z_laal( Register r1, Register r3, int64_t d2, Register b2); // load and add int32, unsigned -- z196
2034 inline void z_laalg(Register r1, Register r3, int64_t d2, Register b2); // load and add int64, unsigned -- z196
2035 inline void z_lan( Register r1, Register r3, int64_t d2, Register b2); // load and and int32 -- z196
2036 inline void z_lang( Register r1, Register r3, int64_t d2, Register b2); // load and and int64 -- z196
2037 inline void z_lax( Register r1, Register r3, int64_t d2, Register b2); // load and xor int32 -- z196
2038 inline void z_laxg( Register r1, Register r3, int64_t d2, Register b2); // load and xor int64 -- z196
2039 inline void z_lao( Register r1, Register r3, int64_t d2, Register b2); // load and or int32 -- z196
2040 inline void z_laog( Register r1, Register r3, int64_t d2, Register b2); // load and or int64 -- z196
2041
2042 inline void z_laa( Register r1, Register r3, const Address& a); // load and add int32, signed -- z196
2043 inline void z_laag( Register r1, Register r3, const Address& a); // load and add int64, signed -- z196
2044 inline void z_laal( Register r1, Register r3, const Address& a); // load and add int32, unsigned -- z196
2045 inline void z_laalg(Register r1, Register r3, const Address& a); // load and add int64, unsigned -- z196
2046 inline void z_lan( Register r1, Register r3, const Address& a); // load and and int32 -- z196
2047 inline void z_lang( Register r1, Register r3, const Address& a); // load and and int64 -- z196
2048 inline void z_lax( Register r1, Register r3, const Address& a); // load and xor int32 -- z196
2049 inline void z_laxg( Register r1, Register r3, const Address& a); // load and xor int64 -- z196
2050 inline void z_lao( Register r1, Register r3, const Address& a); // load and or int32 -- z196
2051 inline void z_laog( Register r1, Register r3, const Address& a); // load and or int64 -- z196
2052
2053 //--------------------------------
2054 // Execution Prediction
2055 //--------------------------------
2056 inline void z_pfd( int64_t m1, int64_t d2, Register x2, Register b2); // prefetch
2057 inline void z_pfd( int64_t m1, Address a);
2058 inline void z_pfdrl(int64_t m1, int64_t i2); // prefetch
2059 inline void z_bpp( int64_t m1, int64_t i2, int64_t d3, Register b3); // branch prediction -- EC12
2060 inline void z_bprp( int64_t m1, int64_t i2, int64_t i3); // branch prediction -- EC12
2061
2062 //-------------------------------
2063 // Transaction Control
2064 //-------------------------------
2065 inline void z_tbegin(int64_t d1, Register b1, int64_t i2); // begin transaction -- EC12
2066 inline void z_tbeginc(int64_t d1, Register b1, int64_t i2); // begin transaction (constrained) -- EC12
2067 inline void z_tend(); // end transaction -- EC12
2068 inline void z_tabort(int64_t d2, Register b2); // abort transaction -- EC12
2069 inline void z_etnd(Register r1); // extract tx nesting depth -- EC12
2070 inline void z_ppa(Register r1, Register r2, int64_t m3); // perform processor assist -- EC12
2071
2072 //---------------------------------
2073 // Conditional Execution
2074 //---------------------------------
2075 inline void z_locr( Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int32 -- z196
2076 inline void z_locgr(Register r1, Register r2, branch_condition cc); // if (cc) load r1 = r2 ; int64 -- z196
2077 inline void z_loc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int32 -- z196
2078 inline void z_locg( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) load r1 = *(d2_simm20+b2) ; int64 -- z196
2079 inline void z_loc( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int32 -- z196
2080 inline void z_locg( Register r1, const Address& a, branch_condition cc); // if (cc) load r1 = *(a) ; int64 -- z196
2081 inline void z_stoc( Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int32 -- z196
2082 inline void z_stocg(Register r1, int64_t d2, Register b2, branch_condition cc); // if (cc) store *(d2_simm20+b2) = r1 ; int64 -- z196
2083
2084
2085 // Complex CISC instructions
2086 // ==========================
2087
2088 inline void z_cksm(Register r1, Register r2); // checksum. This is NOT CRC32
2089 inline void z_km( Register r1, Register r2); // cipher message
2090 inline void z_kmc( Register r1, Register r2); // cipher message with chaining
2091 inline void z_kimd(Register r1, Register r2); // msg digest (SHA)
2092 inline void z_klmd(Register r1, Register r2); // msg digest (SHA)
2093 inline void z_kmac(Register r1, Register r2); // msg authentication code
2094
2095 inline void z_ex(Register r1, int64_t d2, Register x2, Register b2);// execute
2096 inline void z_exrl(Register r1, int64_t i2); // execute relative long -- z10
2097 inline void z_exrl(Register r1, address a2); // execute relative long -- z10
2098
2099 inline void z_ectg(int64_t d1, Register b1, int64_t d2, Register b2, Register r3); // extract cpu time
2100 inline void z_ecag(Register r1, Register r3, int64_t d2, Register b2); // extract CPU attribute
2101
2102 inline void z_srst(Register r1, Register r2); // search string
2103 inline void z_srstu(Register r1, Register r2); // search string unicode
2104
2105 inline void z_mvc(const Address& d, const Address& s, int64_t l); // move l bytes
2106 inline void z_mvc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // move l+1 bytes
2107 inline void z_mvcle(Register r1, Register r3, int64_t d2, Register b2=Z_R0); // move region of memory
2108
2109 inline void z_stfle(int64_t d2, Register b2); // store facility list extended
2110
2111 inline void z_nc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// and *(d1+b1) = *(d1+l+b1) & *(d2+b2) ; d1, d2: uimm12, ands l+1 bytes
2112 inline void z_oc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// or *(d1+b1) = *(d1+l+b1) | *(d2+b2) ; d1, d2: uimm12, ors l+1 bytes
2113 inline void z_xc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2);// xor *(d1+b1) = *(d1+l+b1) ^ *(d2+b2) ; d1, d2: uimm12, xors l+1 bytes
2114 inline void z_nc(Address dst, int64_t len, Address src2); // and *dst = *dst & *src2, ands len bytes in memory
2115 inline void z_oc(Address dst, int64_t len, Address src2); // or *dst = *dst | *src2, ors len bytes in memory
2116 inline void z_xc(Address dst, int64_t len, Address src2); // xor *dst = *dst ^ *src2, xors len bytes in memory
2117
2118 // compare instructions
2119 inline void z_clc(int64_t d1, int64_t l, Register b1, int64_t d2, Register b2); // compare (*(d1_uimm12+b1), *(d1_uimm12+b1)) ; compare l bytes
2120 inline void z_clcle(Register r1, Register r3, int64_t d2, Register b2); // compare logical long extended, see docu
2121 inline void z_clclu(Register r1, Register r3, int64_t d2, Register b2); // compare logical long unicode, see docu
2122
2123 // Translate characters
2124 inline void z_troo(Register r1, Register r2, int64_t m3);
2125 inline void z_trot(Register r1, Register r2, int64_t m3);
2126 inline void z_trto(Register r1, Register r2, int64_t m3);
2127 inline void z_trtt(Register r1, Register r2, int64_t m3);
2128
2129
2130 // Floatingpoint instructions
2131 // ==========================
2132
2133 // compare instructions
2134 inline void z_cebr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; float
2135 inline void z_ceb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; float
2136 inline void z_ceb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; float
2137 inline void z_cdbr(FloatRegister r1, FloatRegister r2); // compare (r1, r2) ; double
2138 inline void z_cdb(FloatRegister r1, int64_t d2, Register x2, Register b2); // compare (r1, *(d2_imm12+x2+b2)) ; double
2139 inline void z_cdb(FloatRegister r1, const Address &a); // compare (r1, *(d2_imm12+x2+b2)) ; double
2140
2141 // load instructions
2142 inline void z_le( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; float
2143 inline void z_ley(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; float
2144 inline void z_ld( FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_uimm12+x2+b2) ; double
2145 inline void z_ldy(FloatRegister r1, int64_t d2, Register x2, Register b2); // load r1 = *(d2_imm20+x2+b2) ; double
2146 inline void z_le( FloatRegister r1, const Address &a); // load r1 = *(a) ; float
2147 inline void z_ley(FloatRegister r1, const Address &a); // load r1 = *(a) ; float
2148 inline void z_ld( FloatRegister r1, const Address &a); // load r1 = *(a) ; double
2149 inline void z_ldy(FloatRegister r1, const Address &a); // load r1 = *(a) ; double
2150
2151 // store instructions
2152 inline void z_ste( FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; float
2153 inline void z_stey(FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; float
2154 inline void z_std( FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_uimm12+x2+b2) = r1 ; double
2155 inline void z_stdy(FloatRegister r1, int64_t d2, Register x2, Register b2); // store *(d2_imm20+x2+b2) = r1 ; double
2156 inline void z_ste( FloatRegister r1, const Address &a); // store *(a) = r1 ; float
2157 inline void z_stey(FloatRegister r1, const Address &a); // store *(a) = r1 ; float
2158 inline void z_std( FloatRegister r1, const Address &a); // store *(a) = r1 ; double
2159 inline void z_stdy(FloatRegister r1, const Address &a); // store *(a) = r1 ; double
2160
2161 // load and store immediates
2162 inline void z_lzer(FloatRegister r1); // r1 = 0 ; single
2163 inline void z_lzdr(FloatRegister r1); // r1 = 0 ; double
2164
2165 // Move and Convert instructions
2166 inline void z_ler(FloatRegister r1, FloatRegister r2); // move r1 = r2 ; float
2167 inline void z_ldr(FloatRegister r1, FloatRegister r2); // move r1 = r2 ; double
2168 inline void z_ledbr(FloatRegister r1, FloatRegister r2); // conv / round r1 = r2 ; float <- double
2169 inline void z_ldebr(FloatRegister r1, FloatRegister r2); // conv r1 = r2 ; double <- float
2170
2171 // move between integer and float registers
2172 inline void z_cefbr( FloatRegister r1, Register r2); // r1 = r2; float <-- int32
2173 inline void z_cdfbr( FloatRegister r1, Register r2); // r1 = r2; double <-- int32
2174 inline void z_cegbr( FloatRegister r1, Register r2); // r1 = r2; float <-- int64
2175 inline void z_cdgbr( FloatRegister r1, Register r2); // r1 = r2; double <-- int64
2176
2177 // rounding mode for float-2-int conversions
2178 inline void z_cfebr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int32 <-- float
2179 inline void z_cfdbr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int32 <-- double
2180 inline void z_cgebr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int64 <-- float
2181 inline void z_cgdbr(Register r1, FloatRegister r2, RoundingMode m); // conv r1 = r2 ; int64 <-- double
2182
2183 inline void z_ldgr(FloatRegister r1, Register r2); // fr1 = r2 ; what kind of conversion? -- z10
2184 inline void z_lgdr(Register r1, FloatRegister r2); // r1 = fr2 ; what kind of conversion? -- z10
2185
2186
2187 // ADD
2188 inline void z_aebr(FloatRegister f1, FloatRegister f2); // f1 = f1 + f2 ; float
2189 inline void z_adbr(FloatRegister f1, FloatRegister f2); // f1 = f1 + f2 ; double
2190 inline void z_aeb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 + *(d2+x2+b2) ; float
2191 inline void z_adb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 + *(d2+x2+b2) ; double
2192 inline void z_aeb( FloatRegister f1, const Address& a); // f1 = f1 + *(a) ; float
2193 inline void z_adb( FloatRegister f1, const Address& a); // f1 = f1 + *(a) ; double
2194
2195 // SUB
2196 inline void z_sebr(FloatRegister f1, FloatRegister f2); // f1 = f1 - f2 ; float
2197 inline void z_sdbr(FloatRegister f1, FloatRegister f2); // f1 = f1 - f2 ; double
2198 inline void z_seb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 - *(d2+x2+b2) ; float
2199 inline void z_sdb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 - *(d2+x2+b2) ; double
2200 inline void z_seb( FloatRegister f1, const Address& a); // f1 = f1 - *(a) ; float
2201 inline void z_sdb( FloatRegister f1, const Address& a); // f1 = f1 - *(a) ; double
2202 // negate
2203 inline void z_lcebr(FloatRegister r1, FloatRegister r2); // neg r1 = -r2 ; float
2204 inline void z_lcdbr(FloatRegister r1, FloatRegister r2); // neg r1 = -r2 ; double
2205
2206 // Absolute value, monadic if fr2 == noreg.
2207 inline void z_lpdbr( FloatRegister fr1, FloatRegister fr2 = fnoreg); // fr1 = |fr2|
2208
2209
2210 // MUL
2211 inline void z_meebr(FloatRegister f1, FloatRegister f2); // f1 = f1 * f2 ; float
2212 inline void z_mdbr( FloatRegister f1, FloatRegister f2); // f1 = f1 * f2 ; double
2213 inline void z_meeb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 * *(d2+x2+b2) ; float
2214 inline void z_mdb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 * *(d2+x2+b2) ; double
2215 inline void z_meeb( FloatRegister f1, const Address& a);
2216 inline void z_mdb( FloatRegister f1, const Address& a);
2217
2218 // MUL-ADD
2219 inline void z_maebr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 + f1 ; float
2220 inline void z_madbr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 + f1 ; double
2221 inline void z_msebr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 - f1 ; float
2222 inline void z_msdbr(FloatRegister f1, FloatRegister f3, FloatRegister f2); // f1 = f3 * f2 - f1 ; double
2223 inline void z_maeb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) + f1 ; float
2224 inline void z_madb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) + f1 ; double
2225 inline void z_mseb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) - f1 ; float
2226 inline void z_msdb(FloatRegister f1, FloatRegister f3, int64_t d2, Register x2, Register b2); // f1 = f3 * *(d2+x2+b2) - f1 ; double
2227 inline void z_maeb(FloatRegister f1, FloatRegister f3, const Address& a);
2228 inline void z_madb(FloatRegister f1, FloatRegister f3, const Address& a);
2229 inline void z_mseb(FloatRegister f1, FloatRegister f3, const Address& a);
2230 inline void z_msdb(FloatRegister f1, FloatRegister f3, const Address& a);
2231
2232 // DIV
2233 inline void z_debr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; float
2234 inline void z_ddbr( FloatRegister f1, FloatRegister f2); // f1 = f1 / f2 ; double
2235 inline void z_deb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 / *(d2+x2+b2) ; float
2236 inline void z_ddb( FloatRegister f1, int64_t d2, Register x2, Register b2); // f1 = f1 / *(d2+x2+b2) ; double
2237 inline void z_deb( FloatRegister f1, const Address& a); // f1 = f1 / *(a) ; float
2238 inline void z_ddb( FloatRegister f1, const Address& a); // f1 = f1 / *(a) ; double
2239
2240 // square root
2241 inline void z_sqdbr(FloatRegister fr1, FloatRegister fr2); // fr1 = sqrt(fr2) ; double
2242 inline void z_sqdb( FloatRegister fr1, int64_t d2, Register x2, Register b2); // fr1 = srqt( *(d2+x2+b2)
2243 inline void z_sqdb( FloatRegister fr1, int64_t d2, Register b2); // fr1 = srqt( *(d2+b2)
2244
2245 // Nop instruction
2246 // ===============
2247
2248 // branch never (nop)
2249 inline void z_nop();
2250
2251 // ===============================================================================================
2252
2253 // Simplified emitters:
2254 // ====================
2255
2256
2257 // Some memory instructions without index register (just convenience).
2258 inline void z_layz(Register r1, int64_t d2, Register b2 = Z_R0);
2259 inline void z_lay(Register r1, int64_t d2, Register b2);
2260 inline void z_laz(Register r1, int64_t d2, Register b2);
2261 inline void z_la(Register r1, int64_t d2, Register b2);
2262 inline void z_l(Register r1, int64_t d2, Register b2);
2263 inline void z_ly(Register r1, int64_t d2, Register b2);
2264 inline void z_lg(Register r1, int64_t d2, Register b2);
2265 inline void z_st(Register r1, int64_t d2, Register b2);
2266 inline void z_sty(Register r1, int64_t d2, Register b2);
2267 inline void z_stg(Register r1, int64_t d2, Register b2);
2268 inline void z_lgf(Register r1, int64_t d2, Register b2);
2269 inline void z_lgh(Register r1, int64_t d2, Register b2);
2270 inline void z_llgh(Register r1, int64_t d2, Register b2);
2271 inline void z_llgf(Register r1, int64_t d2, Register b2);
2272 inline void z_lgb(Register r1, int64_t d2, Register b2);
2273 inline void z_cl( Register r1, int64_t d2, Register b2);
2274 inline void z_c(Register r1, int64_t d2, Register b2);
2275 inline void z_cg(Register r1, int64_t d2, Register b2);
2276 inline void z_sh(Register r1, int64_t d2, Register b2);
2277 inline void z_shy(Register r1, int64_t d2, Register b2);
2278 inline void z_ste(FloatRegister r1, int64_t d2, Register b2);
2279 inline void z_std(FloatRegister r1, int64_t d2, Register b2);
2280 inline void z_stdy(FloatRegister r1, int64_t d2, Register b2);
2281 inline void z_stey(FloatRegister r1, int64_t d2, Register b2);
2282 inline void z_ld(FloatRegister r1, int64_t d2, Register b2);
2283 inline void z_ldy(FloatRegister r1, int64_t d2, Register b2);
2284 inline void z_le(FloatRegister r1, int64_t d2, Register b2);
2285 inline void z_ley(FloatRegister r1, int64_t d2, Register b2);
2286
2287 inline void z_agf(Register r1, int64_t d2, Register b2);
2288
2289 inline void z_exrl(Register r1, Label& L);
2290 inline void z_larl(Register r1, Label& L);
2291 inline void z_bru( Label& L);
2292 inline void z_brul(Label& L);
2293 inline void z_brul(address a);
2294 inline void z_brh( Label& L);
2295 inline void z_brl( Label& L);
2296 inline void z_bre( Label& L);
2297 inline void z_brnh(Label& L);
2298 inline void z_brnl(Label& L);
2299 inline void z_brne(Label& L);
2300 inline void z_brz( Label& L);
2301 inline void z_brnz(Label& L);
2302 inline void z_brnaz(Label& L);
2303 inline void z_braz(Label& L);
2304 inline void z_brnp(Label& L);
2305
2306 inline void z_btrue( Label& L);
2307 inline void z_bfalse(Label& L);
2308
2309 inline void z_brno( Label& L);
2310
2311
2312 inline void z_basr(Register r1, Register r2);
2313 inline void z_brasl(Register r1, address a);
2314 inline void z_brct(Register r1, address a);
2315 inline void z_brct(Register r1, Label& L);
2316
2317 inline void z_brxh(Register r1, Register r3, address a);
2318 inline void z_brxh(Register r1, Register r3, Label& L);
2319
2320 inline void z_brxle(Register r1, Register r3, address a);
2321 inline void z_brxle(Register r1, Register r3, Label& L);
2322
2323 inline void z_brxhg(Register r1, Register r3, address a);
2324 inline void z_brxhg(Register r1, Register r3, Label& L);
2325
2326 inline void z_brxlg(Register r1, Register r3, address a);
2327 inline void z_brxlg(Register r1, Register r3, Label& L);
2328
2329 // Ppopulation count intrinsics.
2330 inline void z_flogr(Register r1, Register r2); // find leftmost one
2331 inline void z_popcnt(Register r1, Register r2); // population count
2332 inline void z_ahhhr(Register r1, Register r2, Register r3); // ADD halfword high high
2333 inline void z_ahhlr(Register r1, Register r2, Register r3); // ADD halfword high low
2334
2335 inline void z_tam();
2336 inline void z_stck(int64_t d2, Register b2);
2337 inline void z_stckf(int64_t d2, Register b2);
2338 inline void z_stmg(Register r1, Register r3, int64_t d2, Register b2);
2339 inline void z_lmg(Register r1, Register r3, int64_t d2, Register b2);
2340
2341 inline void z_cs( Register r1, Register r3, int64_t d2, Register b2);
2342 inline void z_csy(Register r1, Register r3, int64_t d2, Register b2);
2343 inline void z_csg(Register r1, Register r3, int64_t d2, Register b2);
2344 inline void z_cs( Register r1, Register r3, const Address& a);
2345 inline void z_csy(Register r1, Register r3, const Address& a);
2346 inline void z_csg(Register r1, Register r3, const Address& a);
2347
2348 inline void z_cvd(Register r1, int64_t d2, Register x2, Register b2);
2349 inline void z_cvdg(Register r1, int64_t d2, Register x2, Register b2);
2350 inline void z_cvd(Register r1, int64_t d2, Register b2);
2351 inline void z_cvdg(Register r1, int64_t d2, Register b2);
2352
2353 // Instruction queries:
2354 // instruction properties and recognize emitted instructions
2355 // ===========================================================
2356
2357 static int nop_size() { return 2; }
2358
2359 static int z_brul_size() { return 6; }
2360
2361 static bool is_z_basr(short x) {
2362 return (BASR_ZOPC == (x & BASR_MASK));
2363 }
2364 static bool is_z_algr(long x) {
2365 return (ALGR_ZOPC == (x & RRE_MASK));
2366 }
2367 static bool is_z_lb(long x) {
2368 return (LB_ZOPC == (x & LB_MASK));
2369 }
2370 static bool is_z_lh(int x) {
2371 return (LH_ZOPC == (x & LH_MASK));
2372 }
2373 static bool is_z_l(int x) {
2374 return (L_ZOPC == (x & L_MASK));
2375 }
2376 static bool is_z_lgr(long x) {
2377 return (LGR_ZOPC == (x & RRE_MASK));
2378 }
2379 static bool is_z_ly(long x) {
2380 return (LY_ZOPC == (x & LY_MASK));
2381 }
2382 static bool is_z_lg(long x) {
2383 return (LG_ZOPC == (x & LG_MASK));
2384 }
2385 static bool is_z_llgh(long x) {
2386 return (LLGH_ZOPC == (x & LLGH_MASK));
2387 }
2388 static bool is_z_llgf(long x) {
2389 return (LLGF_ZOPC == (x & LLGF_MASK));
2390 }
2391 static bool is_z_le(int x) {
2392 return (LE_ZOPC == (x & LE_MASK));
2393 }
2394 static bool is_z_ld(int x) {
2395 return (LD_ZOPC == (x & LD_MASK));
2396 }
2397 static bool is_z_st(int x) {
2398 return (ST_ZOPC == (x & ST_MASK));
2399 }
2400 static bool is_z_stc(int x) {
2401 return (STC_ZOPC == (x & STC_MASK));
2402 }
2403 static bool is_z_stg(long x) {
2404 return (STG_ZOPC == (x & STG_MASK));
2405 }
2406 static bool is_z_sth(int x) {
2407 return (STH_ZOPC == (x & STH_MASK));
2408 }
2409 static bool is_z_ste(int x) {
2410 return (STE_ZOPC == (x & STE_MASK));
2411 }
2412 static bool is_z_std(int x) {
2413 return (STD_ZOPC == (x & STD_MASK));
2414 }
2415 static bool is_z_slag(long x) {
2416 return (SLAG_ZOPC == (x & SLAG_MASK));
2417 }
2418 static bool is_z_tmy(long x) {
2419 return (TMY_ZOPC == (x & TMY_MASK));
2420 }
2421 static bool is_z_tm(long x) {
2422 return ((unsigned int)TM_ZOPC == (x & (unsigned int)TM_MASK));
2423 }
2424 static bool is_z_bcr(long x) {
2425 return (BCR_ZOPC == (x & BCR_MASK));
2426 }
2427 static bool is_z_nop(long x) {
2428 return is_z_bcr(x) && ((x & 0x00ff) == 0);
2429 }
2430 static bool is_z_nop(address x) {
2431 return is_z_nop(* (short *) x);
2432 }
2433 static bool is_z_br(long x) {
2434 return is_z_bcr(x) && ((x & 0x00f0) == 0x00f0);
2435 }
2436 static bool is_z_brc(long x, int cond) {
2437 return ((unsigned int)BRC_ZOPC == (x & BRC_MASK)) && ((cond<<20) == (x & 0x00f00000U));
2438 }
2439 // Make use of lightweight sync.
2440 static bool is_z_sync_full(long x) {
2441 return is_z_bcr(x) && (((x & 0x00f0)>>4)==bcondFullSync) && ((x & 0x000f)==0x0000);
2442 }
2443 static bool is_z_sync_light(long x) {
2444 return is_z_bcr(x) && (((x & 0x00f0)>>4)==bcondLightSync) && ((x & 0x000f)==0x0000);
2445 }
2446 static bool is_z_sync(long x) {
2447 return is_z_sync_full(x) || is_z_sync_light(x);
2448 }
2449
2450 static bool is_z_brasl(long x) {
2451 return (BRASL_ZOPC == (x & BRASL_MASK));
2452 }
2453 static bool is_z_brasl(address a) {
2454 long x = (*((long *)a))>>16;
2455 return is_z_brasl(x);
2456 }
2457 static bool is_z_larl(long x) {
2458 return (LARL_ZOPC == (x & LARL_MASK));
2459 }
2460 static bool is_z_lgrl(long x) {
2461 return (LGRL_ZOPC == (x & LGRL_MASK));
2462 }
2463 static bool is_z_lgrl(address a) {
2464 long x = (*((long *)a))>>16;
2465 return is_z_lgrl(x);
2466 }
2467
2468 static bool is_z_lghi(unsigned long x) {
2469 return (unsigned int)LGHI_ZOPC == (x & (unsigned int)LGHI_MASK);
2470 }
2471
2472 static bool is_z_llill(unsigned long x) {
2473 return (unsigned int)LLILL_ZOPC == (x & (unsigned int)LLI_MASK);
2474 }
2475 static bool is_z_llilh(unsigned long x) {
2476 return (unsigned int)LLILH_ZOPC == (x & (unsigned int)LLI_MASK);
2477 }
2478 static bool is_z_llihl(unsigned long x) {
2479 return (unsigned int)LLIHL_ZOPC == (x & (unsigned int)LLI_MASK);
2480 }
2481 static bool is_z_llihh(unsigned long x) {
2482 return (unsigned int)LLIHH_ZOPC == (x & (unsigned int)LLI_MASK);
2483 }
2484 static bool is_z_llilf(unsigned long x) {
2485 return LLILF_ZOPC == (x & LLIF_MASK);
2486 }
2487 static bool is_z_llihf(unsigned long x) {
2488 return LLIHF_ZOPC == (x & LLIF_MASK);
2489 }
2490
2491 static bool is_z_iill(unsigned long x) {
2492 return (unsigned int)IILL_ZOPC == (x & (unsigned int)II_MASK);
2493 }
2494 static bool is_z_iilh(unsigned long x) {
2495 return (unsigned int)IILH_ZOPC == (x & (unsigned int)II_MASK);
2496 }
2497 static bool is_z_iihl(unsigned long x) {
2498 return (unsigned int)IIHL_ZOPC == (x & (unsigned int)II_MASK);
2499 }
2500 static bool is_z_iihh(unsigned long x) {
2501 return (unsigned int)IIHH_ZOPC == (x & (unsigned int)II_MASK);
2502 }
2503 static bool is_z_iilf(unsigned long x) {
2504 return IILF_ZOPC == (x & IIF_MASK);
2505 }
2506 static bool is_z_iihf(unsigned long x) {
2507 return IIHF_ZOPC == (x & IIF_MASK);
2508 }
2509
2510 static inline bool is_equal(unsigned long inst, unsigned long idef);
2511 static inline bool is_equal(unsigned long inst, unsigned long idef, unsigned long imask);
2512 static inline bool is_equal(address iloc, unsigned long idef);
2513 static inline bool is_equal(address iloc, unsigned long idef, unsigned long imask);
2514
2515 static inline bool is_sigtrap_range_check(address pc);
2516 static inline bool is_sigtrap_zero_check(address pc);
2517
2518 //-----------------
2519 // memory barriers
2520 //-----------------
2521 // machine barrier instructions:
2522 //
2523 // - z_sync Two-way memory barrier, aka fence.
2524 // Only load-after-store-order is not guaranteed in the
2525 // z/Architecture memory model, i.e. only 'fence' is needed.
2526 //
2527 // semantic barrier instructions:
2528 // (as defined in orderAccess.hpp)
2529 //
2530 // - z_release orders Store|Store, empty implementation
2531 // Load|Store
2532 // - z_acquire orders Load|Store, empty implementation
2533 // Load|Load
2534 // - z_fence orders Store|Store, implemented as z_sync.
2535 // Load|Store,
2536 // Load|Load,
2537 // Store|Load
2538 //
2539 // For this implementation to be correct, we need H/W fixes on (very) old H/W:
2540 // For z990, it is Driver-55: MCL232 in the J13484 (i390/ML) Stream.
2541 // For z9, it is Driver-67: MCL065 in the G40963 (i390/ML) Stream.
2542 // These drivers are a prereq. Otherwise, memory synchronization will not work.
2543
2544 inline void z_sync();
2545 inline void z_release();
2546 inline void z_acquire();
2547 inline void z_fence();
2548
2549 // Creation
2550 Assembler(CodeBuffer* code) : AbstractAssembler(code) { }
2551
2552 };
2553
2554 #endif // CPU_S390_VM_ASSEMBLER_S390_HPP