7232 // CC unchanged by MUL.
7233 ins_cost(ALU_REG_COST);
7234 size(4);
7235 format %{ "MDBR $dst,$src" %}
7236 opcode(MDBR_ZOPC);
7237 ins_encode(z_rreform(dst, src));
7238 ins_pipe(pipe_class_dummy);
7239 %}
7240
7241 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7242 match(Set dst (MulD dst (LoadD src)));
7243 // CC unchanged by MUL.
7244 ins_cost(ALU_MEMORY_COST);
7245 size(6);
7246 format %{ "MDB $dst,$src\t # doubleMemory" %}
7247 opcode(MDB_ZOPC);
7248 ins_encode(z_form_rt_memFP(dst, src));
7249 ins_pipe(pipe_class_dummy);
7250 %}
7251
7252 // DIV
7253
7254 // Div float single precision
7255 instruct divF_reg_reg(regF dst, regF src) %{
7256 match(Set dst (DivF dst src));
7257 // CC unchanged by DIV.
7258 ins_cost(ALU_REG_COST);
7259 size(4);
7260 format %{ "DEBR $dst,$src" %}
7261 opcode(DEBR_ZOPC);
7262 ins_encode(z_rreform(dst, src));
7263 ins_pipe(pipe_class_dummy);
7264 %}
7265
7266 instruct divF_reg_mem(regF dst, memoryRX src)%{
7267 match(Set dst (DivF dst (LoadF src)));
7268 // CC unchanged by DIV.
7269 ins_cost(ALU_MEMORY_COST);
7270 size(6);
7271 format %{ "DEB $dst,$src\t # floatMemory" %}
|
7232 // CC unchanged by MUL.
7233 ins_cost(ALU_REG_COST);
7234 size(4);
7235 format %{ "MDBR $dst,$src" %}
7236 opcode(MDBR_ZOPC);
7237 ins_encode(z_rreform(dst, src));
7238 ins_pipe(pipe_class_dummy);
7239 %}
7240
7241 instruct mulD_reg_mem(regD dst, memoryRX src)%{
7242 match(Set dst (MulD dst (LoadD src)));
7243 // CC unchanged by MUL.
7244 ins_cost(ALU_MEMORY_COST);
7245 size(6);
7246 format %{ "MDB $dst,$src\t # doubleMemory" %}
7247 opcode(MDB_ZOPC);
7248 ins_encode(z_form_rt_memFP(dst, src));
7249 ins_pipe(pipe_class_dummy);
7250 %}
7251
7252 // Multiply-Accumulate
7253 // src1 * src2 + src3
7254 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
7255 match(Set dst (FmaF dst (Binary src1 src2)));
7256 // CC unchanged by MUL-ADD.
7257 ins_cost(ALU_REG_COST);
7258 size(4);
7259 format %{ "MAEBR $dst, $src1, $src2" %}
7260 ins_encode %{
7261 __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7262 %}
7263 ins_pipe(pipe_class_dummy);
7264 %}
7265
7266 // src1 * src2 + src3
7267 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
7268 match(Set dst (FmaD dst (Binary src1 src2)));
7269 // CC unchanged by MUL-ADD.
7270 ins_cost(ALU_REG_COST);
7271 size(4);
7272 format %{ "MADBR $dst, $src1, $src2" %}
7273 ins_encode %{
7274 __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7275 %}
7276 ins_pipe(pipe_class_dummy);
7277 %}
7278
7279 // src1 * src2 - src3
7280 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
7281 match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
7282 // CC unchanged by MUL-ADD.
7283 ins_cost(ALU_REG_COST);
7284 size(4);
7285 format %{ "MSEBR $dst, $src1, $src2" %}
7286 ins_encode %{
7287 __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7288 %}
7289 ins_pipe(pipe_class_dummy);
7290 %}
7291
7292 // src1 * src2 - src3
7293 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
7294 match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
7295 // CC unchanged by MUL-ADD.
7296 ins_cost(ALU_REG_COST);
7297 size(4);
7298 format %{ "MSDBR $dst, $src1, $src2" %}
7299 ins_encode %{
7300 __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
7301 %}
7302 ins_pipe(pipe_class_dummy);
7303 %}
7304
7305 // src1 * src2 + src3
7306 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7307 match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
7308 // CC unchanged by MUL-ADD.
7309 ins_cost(ALU_MEMORY_COST);
7310 size(6);
7311 format %{ "MAEB $dst, $src1, $src2" %}
7312 ins_encode %{
7313 __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
7314 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7315 %}
7316 ins_pipe(pipe_class_dummy);
7317 %}
7318
7319 // src1 * src2 + src3
7320 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7321 match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
7322 // CC unchanged by MUL-ADD.
7323 ins_cost(ALU_MEMORY_COST);
7324 size(6);
7325 format %{ "MADB $dst, $src1, $src2" %}
7326 ins_encode %{
7327 __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
7328 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7329 %}
7330 ins_pipe(pipe_class_dummy);
7331 %}
7332
7333 // src1 * src2 - src3
7334 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
7335 match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
7336 // CC unchanged by MUL-ADD.
7337 ins_cost(ALU_MEMORY_COST);
7338 size(6);
7339 format %{ "MSEB $dst, $src1, $src2" %}
7340 ins_encode %{
7341 __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
7342 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7343 %}
7344 ins_pipe(pipe_class_dummy);
7345 %}
7346
7347 // src1 * src2 - src3
7348 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
7349 match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
7350 // CC unchanged by MUL-ADD.
7351 ins_cost(ALU_MEMORY_COST);
7352 size(6);
7353 format %{ "MSDB $dst, $src1, $src2" %}
7354 ins_encode %{
7355 __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
7356 Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
7357 %}
7358 ins_pipe(pipe_class_dummy);
7359 %}
7360
7361 // src1 * src2 + src3
7362 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7363 match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
7364 // CC unchanged by MUL-ADD.
7365 ins_cost(ALU_MEMORY_COST);
7366 size(6);
7367 format %{ "MAEB $dst, $src1, $src2" %}
7368 ins_encode %{
7369 __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
7370 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7371 %}
7372 ins_pipe(pipe_class_dummy);
7373 %}
7374
7375 // src1 * src2 + src3
7376 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7377 match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
7378 // CC unchanged by MUL-ADD.
7379 ins_cost(ALU_MEMORY_COST);
7380 size(6);
7381 format %{ "MADB $dst, $src1, $src2" %}
7382 ins_encode %{
7383 __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
7384 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7385 %}
7386 ins_pipe(pipe_class_dummy);
7387 %}
7388
7389 // src1 * src2 - src3
7390 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
7391 match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
7392 // CC unchanged by MUL-ADD.
7393 ins_cost(ALU_MEMORY_COST);
7394 size(6);
7395 format %{ "MSEB $dst, $src1, $src2" %}
7396 ins_encode %{
7397 __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
7398 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7399 %}
7400 ins_pipe(pipe_class_dummy);
7401 %}
7402
7403 // src1 * src2 - src3
7404 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
7405 match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
7406 // CC unchanged by MUL-ADD.
7407 ins_cost(ALU_MEMORY_COST);
7408 size(6);
7409 format %{ "MSDB $dst, $src1, $src2" %}
7410 ins_encode %{
7411 __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
7412 Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
7413 %}
7414 ins_pipe(pipe_class_dummy);
7415 %}
7416
7417 // DIV
7418
7419 // Div float single precision
7420 instruct divF_reg_reg(regF dst, regF src) %{
7421 match(Set dst (DivF dst src));
7422 // CC unchanged by DIV.
7423 ins_cost(ALU_REG_COST);
7424 size(4);
7425 format %{ "DEBR $dst,$src" %}
7426 opcode(DEBR_ZOPC);
7427 ins_encode(z_rreform(dst, src));
7428 ins_pipe(pipe_class_dummy);
7429 %}
7430
7431 instruct divF_reg_mem(regF dst, memoryRX src)%{
7432 match(Set dst (DivF dst (LoadF src)));
7433 // CC unchanged by DIV.
7434 ins_cost(ALU_MEMORY_COST);
7435 size(6);
7436 format %{ "DEB $dst,$src\t # floatMemory" %}
|