1 /*
2 * Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "memory/allocation.inline.hpp"
27 #include "opto/ad.hpp"
28 #include "opto/block.hpp"
29 #include "opto/c2compiler.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/cfgnode.hpp"
32 #include "opto/machnode.hpp"
33 #include "opto/runtime.hpp"
34 #include "opto/chaitin.hpp"
35 #include "runtime/sharedRuntime.hpp"
36
37 // Optimization - Graph Style
38
39 // Check whether val is not-null-decoded compressed oop,
40 // i.e. will grab into the base of the heap if it represents NULL.
41 static bool accesses_heap_base_zone(Node *val) {
42 if (Universe::narrow_oop_base() > 0) { // Implies UseCompressedOops.
43 if (val && val->is_Mach()) {
44 if (val->as_Mach()->ideal_Opcode() == Op_DecodeN) {
45 // This assumes all Decodes with TypePtr::NotNull are matched to nodes that
46 // decode NULL to point to the heap base (Decode_NN).
47 if (val->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull) {
48 return true;
49 }
50 }
51 // Must recognize load operation with Decode matched in memory operand.
52 // We should not reach here exept for PPC/AIX, as os::zero_page_read_protected()
53 // returns true everywhere else. On PPC, no such memory operands
54 // exist, therefore we did not yet implement a check for such operands.
55 NOT_AIX(Unimplemented());
56 }
57 }
58 return false;
59 }
60
61 static bool needs_explicit_null_check_for_read(Node *val) {
62 // On some OSes (AIX) the page at address 0 is only write protected.
63 // If so, only Store operations will trap.
64 if (os::zero_page_read_protected()) {
65 return false; // Implicit null check will work.
66 }
67 // Also a read accessing the base of a heap-based compressed heap will trap.
68 if (accesses_heap_base_zone(val) && // Hits the base zone page.
69 Universe::narrow_oop_use_implicit_null_checks()) { // Base zone page is protected.
70 return false;
71 }
72
73 return true;
74 }
75
76 //------------------------------implicit_null_check----------------------------
77 // Detect implicit-null-check opportunities. Basically, find NULL checks
78 // with suitable memory ops nearby. Use the memory op to do the NULL check.
79 // I can generate a memory op if there is not one nearby.
80 // The proj is the control projection for the not-null case.
81 // The val is the pointer being checked for nullness or
82 // decodeHeapOop_not_null node if it did not fold into address.
83 void PhaseCFG::implicit_null_check(Block* block, Node *proj, Node *val, int allowed_reasons) {
84 // Assume if null check need for 0 offset then always needed
85 // Intel solaris doesn't support any null checks yet and no
86 // mechanism exists (yet) to set the switches at an os_cpu level
87 if( !ImplicitNullChecks || MacroAssembler::needs_explicit_null_check(0)) return;
88
89 // Make sure the ptr-is-null path appears to be uncommon!
90 float f = block->end()->as_MachIf()->_prob;
91 if( proj->Opcode() == Op_IfTrue ) f = 1.0f - f;
92 if( f > PROB_UNLIKELY_MAG(4) ) return;
93
94 uint bidx = 0; // Capture index of value into memop
95 bool was_store; // Memory op is a store op
96
97 // Get the successor block for if the test ptr is non-null
98 Block* not_null_block; // this one goes with the proj
99 Block* null_block;
100 if (block->get_node(block->number_of_nodes()-1) == proj) {
101 null_block = block->_succs[0];
102 not_null_block = block->_succs[1];
103 } else {
104 assert(block->get_node(block->number_of_nodes()-2) == proj, "proj is one or the other");
105 not_null_block = block->_succs[0];
106 null_block = block->_succs[1];
107 }
108 while (null_block->is_Empty() == Block::empty_with_goto) {
109 null_block = null_block->_succs[0];
110 }
111
112 // Search the exception block for an uncommon trap.
113 // (See Parse::do_if and Parse::do_ifnull for the reason
114 // we need an uncommon trap. Briefly, we need a way to
115 // detect failure of this optimization, as in 6366351.)
116 {
117 bool found_trap = false;
118 for (uint i1 = 0; i1 < null_block->number_of_nodes(); i1++) {
119 Node* nn = null_block->get_node(i1);
120 if (nn->is_MachCall() &&
121 nn->as_MachCall()->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
122 const Type* trtype = nn->in(TypeFunc::Parms)->bottom_type();
123 if (trtype->isa_int() && trtype->is_int()->is_con()) {
124 jint tr_con = trtype->is_int()->get_con();
125 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
126 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
127 assert((int)reason < (int)BitsPerInt, "recode bit map");
128 if (is_set_nth_bit(allowed_reasons, (int) reason)
129 && action != Deoptimization::Action_none) {
130 // This uncommon trap is sure to recompile, eventually.
131 // When that happens, C->too_many_traps will prevent
132 // this transformation from happening again.
133 found_trap = true;
134 }
135 }
136 break;
137 }
138 }
139 if (!found_trap) {
140 // We did not find an uncommon trap.
141 return;
142 }
143 }
144
145 // Check for decodeHeapOop_not_null node which did not fold into address
146 bool is_decoden = ((intptr_t)val) & 1;
147 val = (Node*)(((intptr_t)val) & ~1);
148
149 assert(!is_decoden || (val->in(0) == NULL) && val->is_Mach() &&
150 (val->as_Mach()->ideal_Opcode() == Op_DecodeN), "sanity");
151
152 // Search the successor block for a load or store who's base value is also
153 // the tested value. There may be several.
154 Node_List *out = new Node_List(Thread::current()->resource_area());
155 MachNode *best = NULL; // Best found so far
156 for (DUIterator i = val->outs(); val->has_out(i); i++) {
157 Node *m = val->out(i);
158 if( !m->is_Mach() ) continue;
159 MachNode *mach = m->as_Mach();
160 was_store = false;
161 int iop = mach->ideal_Opcode();
162 switch( iop ) {
163 case Op_LoadB:
164 case Op_LoadUB:
165 case Op_LoadUS:
166 case Op_LoadD:
167 case Op_LoadF:
168 case Op_LoadI:
169 case Op_LoadL:
170 case Op_LoadP:
171 case Op_LoadN:
172 case Op_LoadS:
173 case Op_LoadKlass:
174 case Op_LoadNKlass:
175 case Op_LoadRange:
176 case Op_LoadD_unaligned:
177 case Op_LoadL_unaligned:
178 assert(mach->in(2) == val, "should be address");
179 break;
180 case Op_StoreB:
181 case Op_StoreC:
182 case Op_StoreCM:
183 case Op_StoreD:
184 case Op_StoreF:
185 case Op_StoreI:
186 case Op_StoreL:
187 case Op_StoreP:
188 case Op_StoreN:
189 case Op_StoreNKlass:
190 was_store = true; // Memory op is a store op
191 // Stores will have their address in slot 2 (memory in slot 1).
192 // If the value being nul-checked is in another slot, it means we
193 // are storing the checked value, which does NOT check the value!
194 if( mach->in(2) != val ) continue;
195 break; // Found a memory op?
196 case Op_StrComp:
197 case Op_StrEquals:
198 case Op_StrIndexOf:
199 case Op_StrIndexOfChar:
200 case Op_AryEq:
201 case Op_StrInflatedCopy:
202 case Op_StrCompressedCopy:
203 case Op_EncodeISOArray:
204 case Op_HasNegatives:
205 // Not a legit memory op for implicit null check regardless of
206 // embedded loads
207 continue;
208 default: // Also check for embedded loads
209 if( !mach->needs_anti_dependence_check() )
210 continue; // Not an memory op; skip it
211 if( must_clone[iop] ) {
212 // Do not move nodes which produce flags because
213 // RA will try to clone it to place near branch and
214 // it will cause recompilation, see clone_node().
215 continue;
216 }
217 {
218 // Check that value is used in memory address in
219 // instructions with embedded load (CmpP val1,(val2+off)).
220 Node* base;
221 Node* index;
222 const MachOper* oper = mach->memory_inputs(base, index);
223 if (oper == NULL || oper == (MachOper*)-1) {
224 continue; // Not an memory op; skip it
225 }
226 if (val == base ||
227 val == index && val->bottom_type()->isa_narrowoop()) {
228 break; // Found it
229 } else {
230 continue; // Skip it
231 }
232 }
233 break;
234 }
235
236 // On some OSes (AIX) the page at address 0 is only write protected.
237 // If so, only Store operations will trap.
238 // But a read accessing the base of a heap-based compressed heap will trap.
239 if (!was_store && needs_explicit_null_check_for_read(val)) {
240 continue;
241 }
242
243 // Check that node's control edge is not-null block's head or dominates it,
244 // otherwise we can't hoist it because there are other control dependencies.
245 Node* ctrl = mach->in(0);
246 if (ctrl != NULL && !(ctrl == not_null_block->head() ||
247 get_block_for_node(ctrl)->dominates(not_null_block))) {
248 continue;
249 }
250
251 // check if the offset is not too high for implicit exception
252 {
253 intptr_t offset = 0;
254 const TypePtr *adr_type = NULL; // Do not need this return value here
255 const Node* base = mach->get_base_and_disp(offset, adr_type);
256 if (base == NULL || base == NodeSentinel) {
257 // Narrow oop address doesn't have base, only index
258 if( val->bottom_type()->isa_narrowoop() &&
259 MacroAssembler::needs_explicit_null_check(offset) )
260 continue; // Give up if offset is beyond page size
261 // cannot reason about it; is probably not implicit null exception
262 } else {
263 const TypePtr* tptr;
264 if (UseCompressedOops && (Universe::narrow_oop_shift() == 0 ||
265 Universe::narrow_klass_shift() == 0)) {
266 // 32-bits narrow oop can be the base of address expressions
267 tptr = base->get_ptr_type();
268 } else {
269 // only regular oops are expected here
270 tptr = base->bottom_type()->is_ptr();
271 }
272 // Give up if offset is not a compile-time constant
273 if( offset == Type::OffsetBot || tptr->_offset == Type::OffsetBot )
274 continue;
275 offset += tptr->_offset; // correct if base is offseted
276 if( MacroAssembler::needs_explicit_null_check(offset) )
277 continue; // Give up is reference is beyond 4K page size
278 }
279 }
280
281 // Check ctrl input to see if the null-check dominates the memory op
282 Block *cb = get_block_for_node(mach);
283 cb = cb->_idom; // Always hoist at least 1 block
284 if( !was_store ) { // Stores can be hoisted only one block
285 while( cb->_dom_depth > (block->_dom_depth + 1))
286 cb = cb->_idom; // Hoist loads as far as we want
287 // The non-null-block should dominate the memory op, too. Live
288 // range spilling will insert a spill in the non-null-block if it is
289 // needs to spill the memory op for an implicit null check.
290 if (cb->_dom_depth == (block->_dom_depth + 1)) {
291 if (cb != not_null_block) continue;
292 cb = cb->_idom;
293 }
294 }
295 if( cb != block ) continue;
296
297 // Found a memory user; see if it can be hoisted to check-block
298 uint vidx = 0; // Capture index of value into memop
299 uint j;
300 for( j = mach->req()-1; j > 0; j-- ) {
301 if( mach->in(j) == val ) {
302 vidx = j;
303 // Ignore DecodeN val which could be hoisted to where needed.
304 if( is_decoden ) continue;
305 }
306 // Block of memory-op input
307 Block *inb = get_block_for_node(mach->in(j));
308 Block *b = block; // Start from nul check
309 while( b != inb && b->_dom_depth > inb->_dom_depth )
310 b = b->_idom; // search upwards for input
311 // See if input dominates null check
312 if( b != inb )
313 break;
314 }
315 if( j > 0 )
316 continue;
317 Block *mb = get_block_for_node(mach);
318 // Hoisting stores requires more checks for the anti-dependence case.
319 // Give up hoisting if we have to move the store past any load.
320 if( was_store ) {
321 Block *b = mb; // Start searching here for a local load
322 // mach use (faulting) trying to hoist
323 // n might be blocker to hoisting
324 while( b != block ) {
325 uint k;
326 for( k = 1; k < b->number_of_nodes(); k++ ) {
327 Node *n = b->get_node(k);
328 if( n->needs_anti_dependence_check() &&
329 n->in(LoadNode::Memory) == mach->in(StoreNode::Memory) )
330 break; // Found anti-dependent load
331 }
332 if( k < b->number_of_nodes() )
333 break; // Found anti-dependent load
334 // Make sure control does not do a merge (would have to check allpaths)
335 if( b->num_preds() != 2 ) break;
336 b = get_block_for_node(b->pred(1)); // Move up to predecessor block
337 }
338 if( b != block ) continue;
339 }
340
341 // Make sure this memory op is not already being used for a NullCheck
342 Node *e = mb->end();
343 if( e->is_MachNullCheck() && e->in(1) == mach )
344 continue; // Already being used as a NULL check
345
346 // Found a candidate! Pick one with least dom depth - the highest
347 // in the dom tree should be closest to the null check.
348 if (best == NULL || get_block_for_node(mach)->_dom_depth < get_block_for_node(best)->_dom_depth) {
349 best = mach;
350 bidx = vidx;
351 }
352 }
353 // No candidate!
354 if (best == NULL) {
355 return;
356 }
357
358 // ---- Found an implicit null check
359 #ifndef PRODUCT
360 extern int implicit_null_checks;
361 implicit_null_checks++;
362 #endif
363
364 if( is_decoden ) {
365 // Check if we need to hoist decodeHeapOop_not_null first.
366 Block *valb = get_block_for_node(val);
367 if( block != valb && block->_dom_depth < valb->_dom_depth ) {
368 // Hoist it up to the end of the test block.
369 valb->find_remove(val);
370 block->add_inst(val);
371 map_node_to_block(val, block);
372 // DecodeN on x86 may kill flags. Check for flag-killing projections
373 // that also need to be hoisted.
374 for (DUIterator_Fast jmax, j = val->fast_outs(jmax); j < jmax; j++) {
375 Node* n = val->fast_out(j);
376 if( n->is_MachProj() ) {
377 get_block_for_node(n)->find_remove(n);
378 block->add_inst(n);
379 map_node_to_block(n, block);
380 }
381 }
382 }
383 }
384 // Hoist the memory candidate up to the end of the test block.
385 Block *old_block = get_block_for_node(best);
386 old_block->find_remove(best);
387 block->add_inst(best);
388 map_node_to_block(best, block);
389
390 // Move the control dependence if it is pinned to not-null block.
391 // Don't change it in other cases: NULL or dominating control.
392 if (best->in(0) == not_null_block->head()) {
393 // Set it to control edge of null check.
394 best->set_req(0, proj->in(0)->in(0));
395 }
396
397 // Check for flag-killing projections that also need to be hoisted
398 // Should be DU safe because no edge updates.
399 for (DUIterator_Fast jmax, j = best->fast_outs(jmax); j < jmax; j++) {
400 Node* n = best->fast_out(j);
401 if( n->is_MachProj() ) {
402 get_block_for_node(n)->find_remove(n);
403 block->add_inst(n);
404 map_node_to_block(n, block);
405 }
406 }
407
408 // proj==Op_True --> ne test; proj==Op_False --> eq test.
409 // One of two graph shapes got matched:
410 // (IfTrue (If (Bool NE (CmpP ptr NULL))))
411 // (IfFalse (If (Bool EQ (CmpP ptr NULL))))
412 // NULL checks are always branch-if-eq. If we see a IfTrue projection
413 // then we are replacing a 'ne' test with a 'eq' NULL check test.
414 // We need to flip the projections to keep the same semantics.
415 if( proj->Opcode() == Op_IfTrue ) {
416 // Swap order of projections in basic block to swap branch targets
417 Node *tmp1 = block->get_node(block->end_idx()+1);
418 Node *tmp2 = block->get_node(block->end_idx()+2);
419 block->map_node(tmp2, block->end_idx()+1);
420 block->map_node(tmp1, block->end_idx()+2);
421 Node *tmp = new Node(C->top()); // Use not NULL input
422 tmp1->replace_by(tmp);
423 tmp2->replace_by(tmp1);
424 tmp->replace_by(tmp2);
425 tmp->destruct();
426 }
427
428 // Remove the existing null check; use a new implicit null check instead.
429 // Since schedule-local needs precise def-use info, we need to correct
430 // it as well.
431 Node *old_tst = proj->in(0);
432 MachNode *nul_chk = new MachNullCheckNode(old_tst->in(0),best,bidx);
433 block->map_node(nul_chk, block->end_idx());
434 map_node_to_block(nul_chk, block);
435 // Redirect users of old_test to nul_chk
436 for (DUIterator_Last i2min, i2 = old_tst->last_outs(i2min); i2 >= i2min; --i2)
437 old_tst->last_out(i2)->set_req(0, nul_chk);
438 // Clean-up any dead code
439 for (uint i3 = 0; i3 < old_tst->req(); i3++) {
440 Node* in = old_tst->in(i3);
441 old_tst->set_req(i3, NULL);
442 if (in->outcnt() == 0) {
443 // Remove dead input node
444 in->disconnect_inputs(NULL, C);
445 block->find_remove(in);
446 }
447 }
448
449 latency_from_uses(nul_chk);
450 latency_from_uses(best);
451
452 // insert anti-dependences to defs in this block
453 if (! best->needs_anti_dependence_check()) {
454 for (uint k = 1; k < block->number_of_nodes(); k++) {
455 Node *n = block->get_node(k);
456 if (n->needs_anti_dependence_check() &&
457 n->in(LoadNode::Memory) == best->in(StoreNode::Memory)) {
458 // Found anti-dependent load
459 insert_anti_dependences(block, n);
460 }
461 }
462 }
463 }
464
465
466 //------------------------------select-----------------------------------------
467 // Select a nice fellow from the worklist to schedule next. If there is only
468 // one choice, then use it. Projections take top priority for correctness
469 // reasons - if I see a projection, then it is next. There are a number of
470 // other special cases, for instructions that consume condition codes, et al.
471 // These are chosen immediately. Some instructions are required to immediately
472 // precede the last instruction in the block, and these are taken last. Of the
473 // remaining cases (most), choose the instruction with the greatest latency
474 // (that is, the most number of pseudo-cycles required to the end of the
475 // routine). If there is a tie, choose the instruction with the most inputs.
476 Node* PhaseCFG::select(
477 Block* block,
478 Node_List &worklist,
479 GrowableArray<int> &ready_cnt,
480 VectorSet &next_call,
481 uint sched_slot,
482 intptr_t* recalc_pressure_nodes) {
483
484 // If only a single entry on the stack, use it
485 uint cnt = worklist.size();
486 if (cnt == 1) {
487 Node *n = worklist[0];
488 worklist.map(0,worklist.pop());
489 return n;
490 }
491
492 uint choice = 0; // Bigger is most important
493 uint latency = 0; // Bigger is scheduled first
494 uint score = 0; // Bigger is better
495 int idx = -1; // Index in worklist
496 int cand_cnt = 0; // Candidate count
497 bool block_size_threshold_ok = (block->number_of_nodes() > 10) ? true : false;
498
499 for( uint i=0; i<cnt; i++ ) { // Inspect entire worklist
500 // Order in worklist is used to break ties.
501 // See caller for how this is used to delay scheduling
502 // of induction variable increments to after the other
503 // uses of the phi are scheduled.
504 Node *n = worklist[i]; // Get Node on worklist
505
506 int iop = n->is_Mach() ? n->as_Mach()->ideal_Opcode() : 0;
507 if( n->is_Proj() || // Projections always win
508 n->Opcode()== Op_Con || // So does constant 'Top'
509 iop == Op_CreateEx || // Create-exception must start block
510 iop == Op_CheckCastPP
511 ) {
512 worklist.map(i,worklist.pop());
513 return n;
514 }
515
516 // Final call in a block must be adjacent to 'catch'
517 Node *e = block->end();
518 if( e->is_Catch() && e->in(0)->in(0) == n )
519 continue;
520
521 // Memory op for an implicit null check has to be at the end of the block
522 if( e->is_MachNullCheck() && e->in(1) == n )
523 continue;
524
525 // Schedule IV increment last.
526 if (e->is_Mach() && e->as_Mach()->ideal_Opcode() == Op_CountedLoopEnd) {
527 // Cmp might be matched into CountedLoopEnd node.
528 Node *cmp = (e->in(1)->ideal_reg() == Op_RegFlags) ? e->in(1) : e;
529 if (cmp->req() > 1 && cmp->in(1) == n && n->is_iteratively_computed()) {
530 continue;
531 }
532 }
533
534 uint n_choice = 2;
535
536 // See if this instruction is consumed by a branch. If so, then (as the
537 // branch is the last instruction in the basic block) force it to the
538 // end of the basic block
539 if ( must_clone[iop] ) {
540 // See if any use is a branch
541 bool found_machif = false;
542
543 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
544 Node* use = n->fast_out(j);
545
546 // The use is a conditional branch, make them adjacent
547 if (use->is_MachIf() && get_block_for_node(use) == block) {
548 found_machif = true;
549 break;
550 }
551
552 // More than this instruction pending for successor to be ready,
553 // don't choose this if other opportunities are ready
554 if (ready_cnt.at(use->_idx) > 1)
555 n_choice = 1;
556 }
557
558 // loop terminated, prefer not to use this instruction
559 if (found_machif)
560 continue;
561 }
562
563 // See if this has a predecessor that is "must_clone", i.e. sets the
564 // condition code. If so, choose this first
565 for (uint j = 0; j < n->req() ; j++) {
566 Node *inn = n->in(j);
567 if (inn) {
568 if (inn->is_Mach() && must_clone[inn->as_Mach()->ideal_Opcode()] ) {
569 n_choice = 3;
570 break;
571 }
572 }
573 }
574
575 // MachTemps should be scheduled last so they are near their uses
576 if (n->is_MachTemp()) {
577 n_choice = 1;
578 }
579
580 uint n_latency = get_latency_for_node(n);
581 uint n_score = n->req(); // Many inputs get high score to break ties
582
583 if (OptoRegScheduling && block_size_threshold_ok) {
584 if (recalc_pressure_nodes[n->_idx] == 0x7fff7fff) {
585 _regalloc->_scratch_int_pressure.init(_regalloc->_sched_int_pressure.high_pressure_limit());
586 _regalloc->_scratch_float_pressure.init(_regalloc->_sched_float_pressure.high_pressure_limit());
587 // simulate the notion that we just picked this node to schedule
588 n->add_flag(Node::Flag_is_scheduled);
589 // now caculate its effect upon the graph if we did
590 adjust_register_pressure(n, block, recalc_pressure_nodes, false);
591 // return its state for finalize in case somebody else wins
592 n->remove_flag(Node::Flag_is_scheduled);
593 // now save the two final pressure components of register pressure, limiting pressure calcs to short size
594 short int_pressure = (short)_regalloc->_scratch_int_pressure.current_pressure();
595 short float_pressure = (short)_regalloc->_scratch_float_pressure.current_pressure();
596 recalc_pressure_nodes[n->_idx] = int_pressure;
597 recalc_pressure_nodes[n->_idx] |= (float_pressure << 16);
598 }
599
600 if (_scheduling_for_pressure) {
601 latency = n_latency;
602 if (n_choice != 3) {
603 // Now evaluate each register pressure component based on threshold in the score.
604 // In general the defining register type will dominate the score, ergo we will not see register pressure grow on both banks
605 // on a single instruction, but we might see it shrink on both banks.
606 // For each use of register that has a register class that is over the high pressure limit, we build n_score up for
607 // live ranges that terminate on this instruction.
608 if (_regalloc->_sched_int_pressure.current_pressure() > _regalloc->_sched_int_pressure.high_pressure_limit()) {
609 short int_pressure = (short)recalc_pressure_nodes[n->_idx];
610 n_score = (int_pressure < 0) ? ((score + n_score) - int_pressure) : (int_pressure > 0) ? 1 : n_score;
611 }
612 if (_regalloc->_sched_float_pressure.current_pressure() > _regalloc->_sched_float_pressure.high_pressure_limit()) {
613 short float_pressure = (short)(recalc_pressure_nodes[n->_idx] >> 16);
614 n_score = (float_pressure < 0) ? ((score + n_score) - float_pressure) : (float_pressure > 0) ? 1 : n_score;
615 }
616 } else {
617 // make sure we choose these candidates
618 score = 0;
619 }
620 }
621 }
622
623 // Keep best latency found
624 cand_cnt++;
625 if (choice < n_choice ||
626 (choice == n_choice &&
627 ((StressLCM && Compile::randomized_select(cand_cnt)) ||
628 (!StressLCM &&
629 (latency < n_latency ||
630 (latency == n_latency &&
631 (score < n_score))))))) {
632 choice = n_choice;
633 latency = n_latency;
634 score = n_score;
635 idx = i; // Also keep index in worklist
636 }
637 } // End of for all ready nodes in worklist
638
639 assert(idx >= 0, "index should be set");
640 Node *n = worklist[(uint)idx]; // Get the winner
641
642 worklist.map((uint)idx, worklist.pop()); // Compress worklist
643 return n;
644 }
645
646 //-------------------------adjust_register_pressure----------------------------
647 void PhaseCFG::adjust_register_pressure(Node* n, Block* block, intptr_t* recalc_pressure_nodes, bool finalize_mode) {
648 PhaseLive* liveinfo = _regalloc->get_live();
649 IndexSet* liveout = liveinfo->live(block);
650 // first adjust the register pressure for the sources
651 for (uint i = 1; i < n->req(); i++) {
652 bool lrg_ends = false;
653 Node *src_n = n->in(i);
654 if (src_n == NULL) continue;
655 if (!src_n->is_Mach()) continue;
656 uint src = _regalloc->_lrg_map.find(src_n);
657 if (src == 0) continue;
658 LRG& lrg_src = _regalloc->lrgs(src);
659 // detect if the live range ends or not
660 if (liveout->member(src) == false) {
661 lrg_ends = true;
662 for (DUIterator_Fast jmax, j = src_n->fast_outs(jmax); j < jmax; j++) {
663 Node* m = src_n->fast_out(j); // Get user
664 if (m == n) continue;
665 if (!m->is_Mach()) continue;
666 MachNode *mach = m->as_Mach();
667 bool src_matches = false;
668 int iop = mach->ideal_Opcode();
669
670 switch (iop) {
671 case Op_StoreB:
672 case Op_StoreC:
673 case Op_StoreCM:
674 case Op_StoreD:
675 case Op_StoreF:
676 case Op_StoreI:
677 case Op_StoreL:
678 case Op_StoreP:
679 case Op_StoreN:
680 case Op_StoreVector:
681 case Op_StoreNKlass:
682 for (uint k = 1; k < m->req(); k++) {
683 Node *in = m->in(k);
684 if (in == src_n) {
685 src_matches = true;
686 break;
687 }
688 }
689 break;
690
691 default:
692 src_matches = true;
693 break;
694 }
695
696 // If we have a store as our use, ignore the non source operands
697 if (src_matches == false) continue;
698
699 // Mark every unscheduled use which is not n with a recalculation
700 if ((get_block_for_node(m) == block) && (!m->is_scheduled())) {
701 if (finalize_mode && !m->is_Phi()) {
702 recalc_pressure_nodes[m->_idx] = 0x7fff7fff;
703 }
704 lrg_ends = false;
705 }
706 }
707 }
708 // if none, this live range ends and we can adjust register pressure
709 if (lrg_ends) {
710 if (finalize_mode) {
711 _regalloc->lower_pressure(block, 0, lrg_src, NULL, _regalloc->_sched_int_pressure, _regalloc->_sched_float_pressure);
712 } else {
713 _regalloc->lower_pressure(block, 0, lrg_src, NULL, _regalloc->_scratch_int_pressure, _regalloc->_scratch_float_pressure);
714 }
715 }
716 }
717
718 // now add the register pressure from the dest and evaluate which heuristic we should use:
719 // 1.) The default, latency scheduling
720 // 2.) Register pressure scheduling based on the high pressure limit threshold for int or float register stacks
721 uint dst = _regalloc->_lrg_map.find(n);
722 if (dst != 0) {
723 LRG& lrg_dst = _regalloc->lrgs(dst);
724 if (finalize_mode) {
725 _regalloc->raise_pressure(block, lrg_dst, _regalloc->_sched_int_pressure, _regalloc->_sched_float_pressure);
726 // check to see if we fall over the register pressure cliff here
727 if (_regalloc->_sched_int_pressure.current_pressure() > _regalloc->_sched_int_pressure.high_pressure_limit()) {
728 _scheduling_for_pressure = true;
729 } else if (_regalloc->_sched_float_pressure.current_pressure() > _regalloc->_sched_float_pressure.high_pressure_limit()) {
730 _scheduling_for_pressure = true;
731 } else {
732 // restore latency scheduling mode
733 _scheduling_for_pressure = false;
734 }
735 } else {
736 _regalloc->raise_pressure(block, lrg_dst, _regalloc->_scratch_int_pressure, _regalloc->_scratch_float_pressure);
737 }
738 }
739 }
740
741 //------------------------------set_next_call----------------------------------
742 void PhaseCFG::set_next_call(Block* block, Node* n, VectorSet& next_call) {
743 if( next_call.test_set(n->_idx) ) return;
744 for( uint i=0; i<n->len(); i++ ) {
745 Node *m = n->in(i);
746 if( !m ) continue; // must see all nodes in block that precede call
747 if (get_block_for_node(m) == block) {
748 set_next_call(block, m, next_call);
749 }
750 }
751 }
752
753 //------------------------------needed_for_next_call---------------------------
754 // Set the flag 'next_call' for each Node that is needed for the next call to
755 // be scheduled. This flag lets me bias scheduling so Nodes needed for the
756 // next subroutine call get priority - basically it moves things NOT needed
757 // for the next call till after the call. This prevents me from trying to
758 // carry lots of stuff live across a call.
759 void PhaseCFG::needed_for_next_call(Block* block, Node* this_call, VectorSet& next_call) {
760 // Find the next control-defining Node in this block
761 Node* call = NULL;
762 for (DUIterator_Fast imax, i = this_call->fast_outs(imax); i < imax; i++) {
763 Node* m = this_call->fast_out(i);
764 if (get_block_for_node(m) == block && // Local-block user
765 m != this_call && // Not self-start node
766 m->is_MachCall()) {
767 call = m;
768 break;
769 }
770 }
771 if (call == NULL) return; // No next call (e.g., block end is near)
772 // Set next-call for all inputs to this call
773 set_next_call(block, call, next_call);
774 }
775
776 //------------------------------add_call_kills-------------------------------------
777 // helper function that adds caller save registers to MachProjNode
778 static void add_call_kills(MachProjNode *proj, RegMask& regs, const char* save_policy, bool exclude_soe) {
779 // Fill in the kill mask for the call
780 for( OptoReg::Name r = OptoReg::Name(0); r < _last_Mach_Reg; r=OptoReg::add(r,1) ) {
781 if( !regs.Member(r) ) { // Not already defined by the call
782 // Save-on-call register?
783 if ((save_policy[r] == 'C') ||
784 (save_policy[r] == 'A') ||
785 ((save_policy[r] == 'E') && exclude_soe)) {
786 proj->_rout.Insert(r);
787 }
788 }
789 }
790 }
791
792
793 //------------------------------sched_call-------------------------------------
794 uint PhaseCFG::sched_call(Block* block, uint node_cnt, Node_List& worklist, GrowableArray<int>& ready_cnt, MachCallNode* mcall, VectorSet& next_call) {
795 RegMask regs;
796
797 // Schedule all the users of the call right now. All the users are
798 // projection Nodes, so they must be scheduled next to the call.
799 // Collect all the defined registers.
800 for (DUIterator_Fast imax, i = mcall->fast_outs(imax); i < imax; i++) {
801 Node* n = mcall->fast_out(i);
802 assert( n->is_MachProj(), "" );
803 int n_cnt = ready_cnt.at(n->_idx)-1;
804 ready_cnt.at_put(n->_idx, n_cnt);
805 assert( n_cnt == 0, "" );
806 // Schedule next to call
807 block->map_node(n, node_cnt++);
808 // Collect defined registers
809 regs.OR(n->out_RegMask());
810 // Check for scheduling the next control-definer
811 if( n->bottom_type() == Type::CONTROL )
812 // Warm up next pile of heuristic bits
813 needed_for_next_call(block, n, next_call);
814
815 // Children of projections are now all ready
816 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
817 Node* m = n->fast_out(j); // Get user
818 if(get_block_for_node(m) != block) {
819 continue;
820 }
821 if( m->is_Phi() ) continue;
822 int m_cnt = ready_cnt.at(m->_idx) - 1;
823 ready_cnt.at_put(m->_idx, m_cnt);
824 if( m_cnt == 0 )
825 worklist.push(m);
826 }
827
828 }
829
830 // Act as if the call defines the Frame Pointer.
831 // Certainly the FP is alive and well after the call.
832 regs.Insert(_matcher.c_frame_pointer());
833
834 // Set all registers killed and not already defined by the call.
835 uint r_cnt = mcall->tf()->range()->cnt();
836 int op = mcall->ideal_Opcode();
837 MachProjNode *proj = new MachProjNode( mcall, r_cnt+1, RegMask::Empty, MachProjNode::fat_proj );
838 map_node_to_block(proj, block);
839 block->insert_node(proj, node_cnt++);
840
841 // Select the right register save policy.
842 const char *save_policy = NULL;
843 switch (op) {
844 case Op_CallRuntime:
845 case Op_CallLeaf:
846 case Op_CallLeafNoFP:
847 // Calling C code so use C calling convention
848 save_policy = _matcher._c_reg_save_policy;
849 break;
850
851 case Op_CallStaticJava:
852 case Op_CallDynamicJava:
853 // Calling Java code so use Java calling convention
854 save_policy = _matcher._register_save_policy;
855 break;
856
857 default:
858 ShouldNotReachHere();
859 }
860
861 // When using CallRuntime mark SOE registers as killed by the call
862 // so values that could show up in the RegisterMap aren't live in a
863 // callee saved register since the register wouldn't know where to
864 // find them. CallLeaf and CallLeafNoFP are ok because they can't
865 // have debug info on them. Strictly speaking this only needs to be
866 // done for oops since idealreg2debugmask takes care of debug info
867 // references but there no way to handle oops differently than other
868 // pointers as far as the kill mask goes.
869 bool exclude_soe = op == Op_CallRuntime;
870
871 // If the call is a MethodHandle invoke, we need to exclude the
872 // register which is used to save the SP value over MH invokes from
873 // the mask. Otherwise this register could be used for
874 // deoptimization information.
875 if (op == Op_CallStaticJava) {
876 MachCallStaticJavaNode* mcallstaticjava = (MachCallStaticJavaNode*) mcall;
877 if (mcallstaticjava->_method_handle_invoke)
878 proj->_rout.OR(Matcher::method_handle_invoke_SP_save_mask());
879 }
880
881 add_call_kills(proj, regs, save_policy, exclude_soe);
882
883 return node_cnt;
884 }
885
886
887 //------------------------------schedule_local---------------------------------
888 // Topological sort within a block. Someday become a real scheduler.
889 bool PhaseCFG::schedule_local(Block* block, GrowableArray<int>& ready_cnt, VectorSet& next_call, intptr_t *recalc_pressure_nodes) {
890 // Already "sorted" are the block start Node (as the first entry), and
891 // the block-ending Node and any trailing control projections. We leave
892 // these alone. PhiNodes and ParmNodes are made to follow the block start
893 // Node. Everything else gets topo-sorted.
894
895 #ifndef PRODUCT
896 if (trace_opto_pipelining()) {
897 tty->print_cr("# --- schedule_local B%d, before: ---", block->_pre_order);
898 for (uint i = 0;i < block->number_of_nodes(); i++) {
899 tty->print("# ");
900 block->get_node(i)->fast_dump();
901 }
902 tty->print_cr("#");
903 }
904 #endif
905
906 // RootNode is already sorted
907 if (block->number_of_nodes() == 1) {
908 return true;
909 }
910
911 bool block_size_threshold_ok = (block->number_of_nodes() > 10) ? true : false;
912
913 // We track the uses of local definitions as input dependences so that
914 // we know when a given instruction is avialable to be scheduled.
915 uint i;
916 if (OptoRegScheduling && block_size_threshold_ok) {
917 for (i = 1; i < block->number_of_nodes(); i++) { // setup nodes for pressure calc
918 Node *n = block->get_node(i);
919 n->remove_flag(Node::Flag_is_scheduled);
920 if (!n->is_Phi()) {
921 recalc_pressure_nodes[n->_idx] = 0x7fff7fff;
922 }
923 }
924 }
925
926 // Move PhiNodes and ParmNodes from 1 to cnt up to the start
927 uint node_cnt = block->end_idx();
928 uint phi_cnt = 1;
929 for( i = 1; i<node_cnt; i++ ) { // Scan for Phi
930 Node *n = block->get_node(i);
931 if( n->is_Phi() || // Found a PhiNode or ParmNode
932 (n->is_Proj() && n->in(0) == block->head()) ) {
933 // Move guy at 'phi_cnt' to the end; makes a hole at phi_cnt
934 block->map_node(block->get_node(phi_cnt), i);
935 block->map_node(n, phi_cnt++); // swap Phi/Parm up front
936 if (OptoRegScheduling && block_size_threshold_ok) {
937 // mark n as scheduled
938 n->add_flag(Node::Flag_is_scheduled);
939 }
940 } else { // All others
941 // Count block-local inputs to 'n'
942 uint cnt = n->len(); // Input count
943 uint local = 0;
944 for( uint j=0; j<cnt; j++ ) {
945 Node *m = n->in(j);
946 if( m && get_block_for_node(m) == block && !m->is_top() )
947 local++; // One more block-local input
948 }
949 ready_cnt.at_put(n->_idx, local); // Count em up
950
951 #ifdef ASSERT
952 if( UseConcMarkSweepGC || UseG1GC ) {
953 if( n->is_Mach() && n->as_Mach()->ideal_Opcode() == Op_StoreCM ) {
954 // Check the precedence edges
955 for (uint prec = n->req(); prec < n->len(); prec++) {
956 Node* oop_store = n->in(prec);
957 if (oop_store != NULL) {
958 assert(get_block_for_node(oop_store)->_dom_depth <= block->_dom_depth, "oop_store must dominate card-mark");
959 }
960 }
961 }
962 }
963 #endif
964
965 // A few node types require changing a required edge to a precedence edge
966 // before allocation.
967 if( n->is_Mach() && n->req() > TypeFunc::Parms &&
968 (n->as_Mach()->ideal_Opcode() == Op_MemBarAcquire ||
969 n->as_Mach()->ideal_Opcode() == Op_MemBarVolatile) ) {
970 // MemBarAcquire could be created without Precedent edge.
971 // del_req() replaces the specified edge with the last input edge
972 // and then removes the last edge. If the specified edge > number of
973 // edges the last edge will be moved outside of the input edges array
974 // and the edge will be lost. This is why this code should be
975 // executed only when Precedent (== TypeFunc::Parms) edge is present.
976 Node *x = n->in(TypeFunc::Parms);
977 if (x != NULL && get_block_for_node(x) == block && n->find_prec_edge(x) != -1) {
978 // Old edge to node within same block will get removed, but no precedence
979 // edge will get added because it already exists. Update ready count.
980 int cnt = ready_cnt.at(n->_idx);
981 assert(cnt > 1, "MemBar node %d must not get ready here", n->_idx);
982 ready_cnt.at_put(n->_idx, cnt-1);
983 }
984 n->del_req(TypeFunc::Parms);
985 n->add_prec(x);
986 }
987 }
988 }
989 for(uint i2=i; i2< block->number_of_nodes(); i2++ ) // Trailing guys get zapped count
990 ready_cnt.at_put(block->get_node(i2)->_idx, 0);
991
992 // All the prescheduled guys do not hold back internal nodes
993 uint i3;
994 for (i3 = 0; i3 < phi_cnt; i3++) { // For all pre-scheduled
995 Node *n = block->get_node(i3); // Get pre-scheduled
996 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
997 Node* m = n->fast_out(j);
998 if (get_block_for_node(m) == block) { // Local-block user
999 int m_cnt = ready_cnt.at(m->_idx)-1;
1000 if (OptoRegScheduling && block_size_threshold_ok) {
1001 // mark m as scheduled
1002 if (m_cnt < 0) {
1003 m->add_flag(Node::Flag_is_scheduled);
1004 }
1005 }
1006 ready_cnt.at_put(m->_idx, m_cnt); // Fix ready count
1007 }
1008 }
1009 }
1010
1011 Node_List delay;
1012 // Make a worklist
1013 Node_List worklist;
1014 for(uint i4=i3; i4<node_cnt; i4++ ) { // Put ready guys on worklist
1015 Node *m = block->get_node(i4);
1016 if( !ready_cnt.at(m->_idx) ) { // Zero ready count?
1017 if (m->is_iteratively_computed()) {
1018 // Push induction variable increments last to allow other uses
1019 // of the phi to be scheduled first. The select() method breaks
1020 // ties in scheduling by worklist order.
1021 delay.push(m);
1022 } else if (m->is_Mach() && m->as_Mach()->ideal_Opcode() == Op_CreateEx) {
1023 // Force the CreateEx to the top of the list so it's processed
1024 // first and ends up at the start of the block.
1025 worklist.insert(0, m);
1026 } else {
1027 worklist.push(m); // Then on to worklist!
1028 }
1029 }
1030 }
1031 while (delay.size()) {
1032 Node* d = delay.pop();
1033 worklist.push(d);
1034 }
1035
1036 if (OptoRegScheduling && block_size_threshold_ok) {
1037 // To stage register pressure calculations we need to examine the live set variables
1038 // breaking them up by register class to compartmentalize the calculations.
1039 uint float_pressure = Matcher::float_pressure(FLOATPRESSURE);
1040 _regalloc->_sched_int_pressure.init(INTPRESSURE);
1041 _regalloc->_sched_float_pressure.init(float_pressure);
1042 _regalloc->_scratch_int_pressure.init(INTPRESSURE);
1043 _regalloc->_scratch_float_pressure.init(float_pressure);
1044
1045 _regalloc->compute_entry_block_pressure(block);
1046 }
1047
1048 // Warm up the 'next_call' heuristic bits
1049 needed_for_next_call(block, block->head(), next_call);
1050
1051 #ifndef PRODUCT
1052 if (trace_opto_pipelining()) {
1053 for (uint j=0; j< block->number_of_nodes(); j++) {
1054 Node *n = block->get_node(j);
1055 int idx = n->_idx;
1056 tty->print("# ready cnt:%3d ", ready_cnt.at(idx));
1057 tty->print("latency:%3d ", get_latency_for_node(n));
1058 tty->print("%4d: %s\n", idx, n->Name());
1059 }
1060 }
1061 #endif
1062
1063 uint max_idx = (uint)ready_cnt.length();
1064 // Pull from worklist and schedule
1065 while( worklist.size() ) { // Worklist is not ready
1066
1067 #ifndef PRODUCT
1068 if (trace_opto_pipelining()) {
1069 tty->print("# ready list:");
1070 for( uint i=0; i<worklist.size(); i++ ) { // Inspect entire worklist
1071 Node *n = worklist[i]; // Get Node on worklist
1072 tty->print(" %d", n->_idx);
1073 }
1074 tty->cr();
1075 }
1076 #endif
1077
1078 // Select and pop a ready guy from worklist
1079 Node* n = select(block, worklist, ready_cnt, next_call, phi_cnt, recalc_pressure_nodes);
1080 block->map_node(n, phi_cnt++); // Schedule him next
1081
1082 if (OptoRegScheduling && block_size_threshold_ok) {
1083 n->add_flag(Node::Flag_is_scheduled);
1084
1085 // Now adjust the resister pressure with the node we selected
1086 if (!n->is_Phi()) {
1087 adjust_register_pressure(n, block, recalc_pressure_nodes, true);
1088 }
1089 }
1090
1091 #ifndef PRODUCT
1092 if (trace_opto_pipelining()) {
1093 tty->print("# select %d: %s", n->_idx, n->Name());
1094 tty->print(", latency:%d", get_latency_for_node(n));
1095 n->dump();
1096 if (Verbose) {
1097 tty->print("# ready list:");
1098 for( uint i=0; i<worklist.size(); i++ ) { // Inspect entire worklist
1099 Node *n = worklist[i]; // Get Node on worklist
1100 tty->print(" %d", n->_idx);
1101 }
1102 tty->cr();
1103 }
1104 }
1105
1106 #endif
1107 if( n->is_MachCall() ) {
1108 MachCallNode *mcall = n->as_MachCall();
1109 phi_cnt = sched_call(block, phi_cnt, worklist, ready_cnt, mcall, next_call);
1110 continue;
1111 }
1112
1113 if (n->is_Mach() && n->as_Mach()->has_call()) {
1114 RegMask regs;
1115 regs.Insert(_matcher.c_frame_pointer());
1116 regs.OR(n->out_RegMask());
1117
1118 MachProjNode *proj = new MachProjNode( n, 1, RegMask::Empty, MachProjNode::fat_proj );
1119 map_node_to_block(proj, block);
1120 block->insert_node(proj, phi_cnt++);
1121
1122 add_call_kills(proj, regs, _matcher._c_reg_save_policy, false);
1123 }
1124
1125 // Children are now all ready
1126 for (DUIterator_Fast i5max, i5 = n->fast_outs(i5max); i5 < i5max; i5++) {
1127 Node* m = n->fast_out(i5); // Get user
1128 if (get_block_for_node(m) != block) {
1129 continue;
1130 }
1131 if( m->is_Phi() ) continue;
1132 if (m->_idx >= max_idx) { // new node, skip it
1133 assert(m->is_MachProj() && n->is_Mach() && n->as_Mach()->has_call(), "unexpected node types");
1134 continue;
1135 }
1136 int m_cnt = ready_cnt.at(m->_idx) - 1;
1137 ready_cnt.at_put(m->_idx, m_cnt);
1138 if( m_cnt == 0 )
1139 worklist.push(m);
1140 }
1141 }
1142
1143 if( phi_cnt != block->end_idx() ) {
1144 // did not schedule all. Retry, Bailout, or Die
1145 if (C->subsume_loads() == true && !C->failing()) {
1146 // Retry with subsume_loads == false
1147 // If this is the first failure, the sentinel string will "stick"
1148 // to the Compile object, and the C2Compiler will see it and retry.
1149 C->record_failure(C2Compiler::retry_no_subsuming_loads());
1150 } else {
1151 assert(false, "graph should be schedulable");
1152 }
1153 // assert( phi_cnt == end_idx(), "did not schedule all" );
1154 return false;
1155 }
1156
1157 if (OptoRegScheduling && block_size_threshold_ok) {
1158 _regalloc->compute_exit_block_pressure(block);
1159 block->_reg_pressure = _regalloc->_sched_int_pressure.final_pressure();
1160 block->_freg_pressure = _regalloc->_sched_float_pressure.final_pressure();
1161 }
1162
1163 #ifndef PRODUCT
1164 if (trace_opto_pipelining()) {
1165 tty->print_cr("#");
1166 tty->print_cr("# after schedule_local");
1167 for (uint i = 0;i < block->number_of_nodes();i++) {
1168 tty->print("# ");
1169 block->get_node(i)->fast_dump();
1170 }
1171 tty->print_cr("# ");
1172
1173 if (OptoRegScheduling && block_size_threshold_ok) {
1174 tty->print_cr("# pressure info : %d", block->_pre_order);
1175 _regalloc->print_pressure_info(_regalloc->_sched_int_pressure, "int register info");
1176 _regalloc->print_pressure_info(_regalloc->_sched_float_pressure, "float register info");
1177 }
1178 tty->cr();
1179 }
1180 #endif
1181
1182 return true;
1183 }
1184
1185 //--------------------------catch_cleanup_fix_all_inputs-----------------------
1186 static void catch_cleanup_fix_all_inputs(Node *use, Node *old_def, Node *new_def) {
1187 for (uint l = 0; l < use->len(); l++) {
1188 if (use->in(l) == old_def) {
1189 if (l < use->req()) {
1190 use->set_req(l, new_def);
1191 } else {
1192 use->rm_prec(l);
1193 use->add_prec(new_def);
1194 l--;
1195 }
1196 }
1197 }
1198 }
1199
1200 //------------------------------catch_cleanup_find_cloned_def------------------
1201 Node* PhaseCFG::catch_cleanup_find_cloned_def(Block *use_blk, Node *def, Block *def_blk, int n_clone_idx) {
1202 assert( use_blk != def_blk, "Inter-block cleanup only");
1203
1204 // The use is some block below the Catch. Find and return the clone of the def
1205 // that dominates the use. If there is no clone in a dominating block, then
1206 // create a phi for the def in a dominating block.
1207
1208 // Find which successor block dominates this use. The successor
1209 // blocks must all be single-entry (from the Catch only; I will have
1210 // split blocks to make this so), hence they all dominate.
1211 while( use_blk->_dom_depth > def_blk->_dom_depth+1 )
1212 use_blk = use_blk->_idom;
1213
1214 // Find the successor
1215 Node *fixup = NULL;
1216
1217 uint j;
1218 for( j = 0; j < def_blk->_num_succs; j++ )
1219 if( use_blk == def_blk->_succs[j] )
1220 break;
1221
1222 if( j == def_blk->_num_succs ) {
1223 // Block at same level in dom-tree is not a successor. It needs a
1224 // PhiNode, the PhiNode uses from the def and IT's uses need fixup.
1225 Node_Array inputs = new Node_List(Thread::current()->resource_area());
1226 for(uint k = 1; k < use_blk->num_preds(); k++) {
1227 Block* block = get_block_for_node(use_blk->pred(k));
1228 inputs.map(k, catch_cleanup_find_cloned_def(block, def, def_blk, n_clone_idx));
1229 }
1230
1231 // Check to see if the use_blk already has an identical phi inserted.
1232 // If it exists, it will be at the first position since all uses of a
1233 // def are processed together.
1234 Node *phi = use_blk->get_node(1);
1235 if( phi->is_Phi() ) {
1236 fixup = phi;
1237 for (uint k = 1; k < use_blk->num_preds(); k++) {
1238 if (phi->in(k) != inputs[k]) {
1239 // Not a match
1240 fixup = NULL;
1241 break;
1242 }
1243 }
1244 }
1245
1246 // If an existing PhiNode was not found, make a new one.
1247 if (fixup == NULL) {
1248 Node *new_phi = PhiNode::make(use_blk->head(), def);
1249 use_blk->insert_node(new_phi, 1);
1250 map_node_to_block(new_phi, use_blk);
1251 for (uint k = 1; k < use_blk->num_preds(); k++) {
1252 new_phi->set_req(k, inputs[k]);
1253 }
1254 fixup = new_phi;
1255 }
1256
1257 } else {
1258 // Found the use just below the Catch. Make it use the clone.
1259 fixup = use_blk->get_node(n_clone_idx);
1260 }
1261
1262 return fixup;
1263 }
1264
1265 //--------------------------catch_cleanup_intra_block--------------------------
1266 // Fix all input edges in use that reference "def". The use is in the same
1267 // block as the def and both have been cloned in each successor block.
1268 static void catch_cleanup_intra_block(Node *use, Node *def, Block *blk, int beg, int n_clone_idx) {
1269
1270 // Both the use and def have been cloned. For each successor block,
1271 // get the clone of the use, and make its input the clone of the def
1272 // found in that block.
1273
1274 uint use_idx = blk->find_node(use);
1275 uint offset_idx = use_idx - beg;
1276 for( uint k = 0; k < blk->_num_succs; k++ ) {
1277 // Get clone in each successor block
1278 Block *sb = blk->_succs[k];
1279 Node *clone = sb->get_node(offset_idx+1);
1280 assert( clone->Opcode() == use->Opcode(), "" );
1281
1282 // Make use-clone reference the def-clone
1283 catch_cleanup_fix_all_inputs(clone, def, sb->get_node(n_clone_idx));
1284 }
1285 }
1286
1287 //------------------------------catch_cleanup_inter_block---------------------
1288 // Fix all input edges in use that reference "def". The use is in a different
1289 // block than the def.
1290 void PhaseCFG::catch_cleanup_inter_block(Node *use, Block *use_blk, Node *def, Block *def_blk, int n_clone_idx) {
1291 if( !use_blk ) return; // Can happen if the use is a precedence edge
1292
1293 Node *new_def = catch_cleanup_find_cloned_def(use_blk, def, def_blk, n_clone_idx);
1294 catch_cleanup_fix_all_inputs(use, def, new_def);
1295 }
1296
1297 //------------------------------call_catch_cleanup-----------------------------
1298 // If we inserted any instructions between a Call and his CatchNode,
1299 // clone the instructions on all paths below the Catch.
1300 void PhaseCFG::call_catch_cleanup(Block* block) {
1301
1302 // End of region to clone
1303 uint end = block->end_idx();
1304 if( !block->get_node(end)->is_Catch() ) return;
1305 // Start of region to clone
1306 uint beg = end;
1307 while(!block->get_node(beg-1)->is_MachProj() ||
1308 !block->get_node(beg-1)->in(0)->is_MachCall() ) {
1309 beg--;
1310 assert(beg > 0,"Catch cleanup walking beyond block boundary");
1311 }
1312 // Range of inserted instructions is [beg, end)
1313 if( beg == end ) return;
1314
1315 // Clone along all Catch output paths. Clone area between the 'beg' and
1316 // 'end' indices.
1317 for( uint i = 0; i < block->_num_succs; i++ ) {
1318 Block *sb = block->_succs[i];
1319 // Clone the entire area; ignoring the edge fixup for now.
1320 for( uint j = end; j > beg; j-- ) {
1321 Node *clone = block->get_node(j-1)->clone();
1322 sb->insert_node(clone, 1);
1323 map_node_to_block(clone, sb);
1324 if (clone->needs_anti_dependence_check()) {
1325 insert_anti_dependences(sb, clone);
1326 }
1327 }
1328 }
1329
1330
1331 // Fixup edges. Check the def-use info per cloned Node
1332 for(uint i2 = beg; i2 < end; i2++ ) {
1333 uint n_clone_idx = i2-beg+1; // Index of clone of n in each successor block
1334 Node *n = block->get_node(i2); // Node that got cloned
1335 // Need DU safe iterator because of edge manipulation in calls.
1336 Unique_Node_List *out = new Unique_Node_List(Thread::current()->resource_area());
1337 for (DUIterator_Fast j1max, j1 = n->fast_outs(j1max); j1 < j1max; j1++) {
1338 out->push(n->fast_out(j1));
1339 }
1340 uint max = out->size();
1341 for (uint j = 0; j < max; j++) {// For all users
1342 Node *use = out->pop();
1343 Block *buse = get_block_for_node(use);
1344 if( use->is_Phi() ) {
1345 for( uint k = 1; k < use->req(); k++ )
1346 if( use->in(k) == n ) {
1347 Block* b = get_block_for_node(buse->pred(k));
1348 Node *fixup = catch_cleanup_find_cloned_def(b, n, block, n_clone_idx);
1349 use->set_req(k, fixup);
1350 }
1351 } else {
1352 if (block == buse) {
1353 catch_cleanup_intra_block(use, n, block, beg, n_clone_idx);
1354 } else {
1355 catch_cleanup_inter_block(use, buse, n, block, n_clone_idx);
1356 }
1357 }
1358 } // End for all users
1359
1360 } // End of for all Nodes in cloned area
1361
1362 // Remove the now-dead cloned ops
1363 for(uint i3 = beg; i3 < end; i3++ ) {
1364 block->get_node(beg)->disconnect_inputs(NULL, C);
1365 block->remove_node(beg);
1366 }
1367
1368 // If the successor blocks have a CreateEx node, move it back to the top
1369 for(uint i4 = 0; i4 < block->_num_succs; i4++ ) {
1370 Block *sb = block->_succs[i4];
1371 uint new_cnt = end - beg;
1372 // Remove any newly created, but dead, nodes.
1373 for( uint j = new_cnt; j > 0; j-- ) {
1374 Node *n = sb->get_node(j);
1375 if (n->outcnt() == 0 &&
1376 (!n->is_Proj() || n->as_Proj()->in(0)->outcnt() == 1) ){
1377 n->disconnect_inputs(NULL, C);
1378 sb->remove_node(j);
1379 new_cnt--;
1380 }
1381 }
1382 // If any newly created nodes remain, move the CreateEx node to the top
1383 if (new_cnt > 0) {
1384 Node *cex = sb->get_node(1+new_cnt);
1385 if( cex->is_Mach() && cex->as_Mach()->ideal_Opcode() == Op_CreateEx ) {
1386 sb->remove_node(1+new_cnt);
1387 sb->insert_node(cex, 1);
1388 }
1389 }
1390 }
1391 }