src/cpu/ppc/vm/assembler_ppc.hpp

rev 13142 : 8181809: PPC64: Leverage mtfprd/mffprd on POWER8
Reviewed-by: mdoerr, simonis
Contributed-by: Matthew Brandyberry <mbrandy@linux.vnet.ibm.com>

*** 1,8 ****
  /*
!  * Copyright (c) 2002, 2016, Oracle and/or its affiliates. All rights reserved.
!  * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,8 ----
  /*
!  * Copyright (c) 2002, 2017, Oracle and/or its affiliates. All rights reserved.
!  * Copyright (c) 2012, 2017 SAP SE. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 509,518 ****
--- 509,519 ----
      // Vector-Scalar (VSX) instruction support.
      LXVD2X_OPCODE  = (31u << OPCODE_SHIFT |  844u << 1),
      STXVD2X_OPCODE = (31u << OPCODE_SHIFT |  972u << 1),
      MTVSRD_OPCODE  = (31u << OPCODE_SHIFT |  179u << 1),
      MFVSRD_OPCODE  = (31u << OPCODE_SHIFT |   51u << 1),
+     MTVSRWA_OPCODE = (31u << OPCODE_SHIFT |  211u << 1),
  
      // Vector Permute and Formatting
      VPKPX_OPCODE   = (4u  << OPCODE_SHIFT |  782u     ),
      VPKSHSS_OPCODE = (4u  << OPCODE_SHIFT |  398u     ),
      VPKSWSS_OPCODE = (4u  << OPCODE_SHIFT |  462u     ),
*** 2136,2145 ****
--- 2137,2151 ----
    inline void stxvd2x(  VectorSRegister d, Register a);
    inline void stxvd2x(  VectorSRegister d, Register a, Register b);
    inline void mtvrd(    VectorRegister  d, Register a);
    inline void mfvrd(    Register        a, VectorRegister d);
  
+   // Vector-Scalar (VSX) instructions.
+   inline void mtfprd(   FloatRegister   d, Register a);
+   inline void mtfprwa(  FloatRegister   d, Register a);
+   inline void mffprd(   Register        a, FloatRegister d);
+ 
    // AES (introduced with Power 8)
    inline void vcipher(     VectorRegister d, VectorRegister a, VectorRegister b);
    inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
    inline void vncipher(    VectorRegister d, VectorRegister a, VectorRegister b);
    inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);