1 /*
2 * Copyright (c) 2002, 2016, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2016 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
494 // Vector instruction support for >= Power6
495 // Vector Storage Access
496 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
497 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
498 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
499 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
500 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
501 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
502 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
503 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
504 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
505 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
506 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
507 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
508
509 // Vector-Scalar (VSX) instruction support.
510 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
511 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
512 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
513 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
514
515 // Vector Permute and Formatting
516 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
517 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
518 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
519 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
520 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
521 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
522 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
523 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
524 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
525 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
526 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
527 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
528 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
529 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
530 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
531
532 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
533 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
2120 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
2121 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
2122 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
2123 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
2124 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
2125 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
2126 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
2127 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
2128 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
2129 // Vector Floating-Point not implemented yet
2130 inline void mtvscr( VectorRegister b);
2131 inline void mfvscr( VectorRegister d);
2132
2133 // Vector-Scalar (VSX) instructions.
2134 inline void lxvd2x( VectorSRegister d, Register a);
2135 inline void lxvd2x( VectorSRegister d, Register a, Register b);
2136 inline void stxvd2x( VectorSRegister d, Register a);
2137 inline void stxvd2x( VectorSRegister d, Register a, Register b);
2138 inline void mtvrd( VectorRegister d, Register a);
2139 inline void mfvrd( Register a, VectorRegister d);
2140
2141 // AES (introduced with Power 8)
2142 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2143 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2144 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
2145 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2146 inline void vsbox( VectorRegister d, VectorRegister a);
2147
2148 // SHA (introduced with Power 8)
2149 // Not yet implemented.
2150
2151 // Vector Binary Polynomial Multiplication (introduced with Power 8)
2152 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
2153 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
2154 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
2155 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
2156
2157 // Vector Permute and Xor (introduced with Power 8)
2158 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2159
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1 /*
2 * Copyright (c) 2002, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2017 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
494 // Vector instruction support for >= Power6
495 // Vector Storage Access
496 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1),
497 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1),
498 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1),
499 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1),
500 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1),
501 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1),
502 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1),
503 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1),
504 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1),
505 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1),
506 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1),
507 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1),
508
509 // Vector-Scalar (VSX) instruction support.
510 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1),
511 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1),
512 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1),
513 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1),
514 MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1),
515
516 // Vector Permute and Formatting
517 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ),
518 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ),
519 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ),
520 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ),
521 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ),
522 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ),
523 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ),
524 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ),
525 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ),
526 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ),
527 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ),
528 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ),
529 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ),
530 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ),
531 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ),
532
533 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ),
534 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ),
2121 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b);
2122 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b);
2123 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b);
2124 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b);
2125 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b);
2126 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b);
2127 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b);
2128 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b);
2129 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b);
2130 // Vector Floating-Point not implemented yet
2131 inline void mtvscr( VectorRegister b);
2132 inline void mfvscr( VectorRegister d);
2133
2134 // Vector-Scalar (VSX) instructions.
2135 inline void lxvd2x( VectorSRegister d, Register a);
2136 inline void lxvd2x( VectorSRegister d, Register a, Register b);
2137 inline void stxvd2x( VectorSRegister d, Register a);
2138 inline void stxvd2x( VectorSRegister d, Register a, Register b);
2139 inline void mtvrd( VectorRegister d, Register a);
2140 inline void mfvrd( Register a, VectorRegister d);
2141
2142 // Vector-Scalar (VSX) instructions.
2143 inline void mtfprd( FloatRegister d, Register a);
2144 inline void mtfprwa( FloatRegister d, Register a);
2145 inline void mffprd( Register a, FloatRegister d);
2146
2147 // AES (introduced with Power 8)
2148 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b);
2149 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b);
2150 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b);
2151 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b);
2152 inline void vsbox( VectorRegister d, VectorRegister a);
2153
2154 // SHA (introduced with Power 8)
2155 // Not yet implemented.
2156
2157 // Vector Binary Polynomial Multiplication (introduced with Power 8)
2158 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b);
2159 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b);
2160 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
2161 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b);
2162
2163 // Vector Permute and Xor (introduced with Power 8)
2164 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c);
2165
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