rev 13142 : 8181809: PPC64: Leverage mtfprd/mffprd on POWER8
Reviewed-by: mdoerr, simonis
Contributed-by: Matthew Brandyberry <mbrandy@linux.vnet.ibm.com>

   1 /*
   2  * Copyright (c) 2000, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2017, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "c1/c1_Compilation.hpp"
  28 #include "c1/c1_LIRAssembler.hpp"
  29 #include "c1/c1_MacroAssembler.hpp"
  30 #include "c1/c1_Runtime1.hpp"
  31 #include "c1/c1_ValueStack.hpp"
  32 #include "ci/ciArrayKlass.hpp"
  33 #include "ci/ciInstance.hpp"
  34 #include "gc/shared/collectedHeap.hpp"
  35 #include "gc/shared/barrierSet.hpp"
  36 #include "gc/shared/cardTableModRefBS.hpp"
  37 #include "nativeInst_ppc.hpp"
  38 #include "oops/objArrayKlass.hpp"
  39 #include "runtime/sharedRuntime.hpp"
  40 
  41 #define __ _masm->
  42 
  43 
  44 const ConditionRegister LIR_Assembler::BOOL_RESULT = CCR5;
  45 
  46 
  47 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
  48   Unimplemented(); return false; // Currently not used on this platform.
  49 }
  50 
  51 
  52 LIR_Opr LIR_Assembler::receiverOpr() {
  53   return FrameMap::R3_oop_opr;
  54 }
  55 
  56 
  57 LIR_Opr LIR_Assembler::osrBufferPointer() {
  58   return FrameMap::R3_opr;
  59 }
  60 
  61 
  62 // This specifies the stack pointer decrement needed to build the frame.
  63 int LIR_Assembler::initial_frame_size_in_bytes() const {
  64   return in_bytes(frame_map()->framesize_in_bytes());
  65 }
  66 
  67 
  68 // Inline cache check: the inline cached class is in inline_cache_reg;
  69 // we fetch the class of the receiver and compare it with the cached class.
  70 // If they do not match we jump to slow case.
  71 int LIR_Assembler::check_icache() {
  72   int offset = __ offset();
  73   __ inline_cache_check(R3_ARG1, R19_inline_cache_reg);
  74   return offset;
  75 }
  76 
  77 
  78 void LIR_Assembler::osr_entry() {
  79   // On-stack-replacement entry sequence:
  80   //
  81   //   1. Create a new compiled activation.
  82   //   2. Initialize local variables in the compiled activation. The expression
  83   //      stack must be empty at the osr_bci; it is not initialized.
  84   //   3. Jump to the continuation address in compiled code to resume execution.
  85 
  86   // OSR entry point
  87   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
  88   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
  89   ValueStack* entry_state = osr_entry->end()->state();
  90   int number_of_locks = entry_state->locks_size();
  91 
  92   // Create a frame for the compiled activation.
  93   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
  94 
  95   // OSR buffer is
  96   //
  97   // locals[nlocals-1..0]
  98   // monitors[number_of_locks-1..0]
  99   //
 100   // Locals is a direct copy of the interpreter frame so in the osr buffer
 101   // the first slot in the local array is the last local from the interpreter
 102   // and the last slot is local[0] (receiver) from the interpreter.
 103   //
 104   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 105   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 106   // in the interpreter frame (the method lock if a sync method).
 107 
 108   // Initialize monitors in the compiled activation.
 109   //   R3: pointer to osr buffer
 110   //
 111   // All other registers are dead at this point and the locals will be
 112   // copied into place by code emitted in the IR.
 113 
 114   Register OSR_buf = osrBufferPointer()->as_register();
 115   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 116     int monitor_offset = BytesPerWord * method()->max_locals() +
 117       (2 * BytesPerWord) * (number_of_locks - 1);
 118     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 119     // the OSR buffer using 2 word entries: first the lock and then
 120     // the oop.
 121     for (int i = 0; i < number_of_locks; i++) {
 122       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 123 #ifdef ASSERT
 124       // Verify the interpreter's monitor has a non-null object.
 125       {
 126         Label L;
 127         __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 128         __ cmpdi(CCR0, R0, 0);
 129         __ bne(CCR0, L);
 130         __ stop("locked object is NULL");
 131         __ bind(L);
 132       }
 133 #endif // ASSERT
 134       // Copy the lock field into the compiled activation.
 135       Address ml = frame_map()->address_for_monitor_lock(i),
 136               mo = frame_map()->address_for_monitor_object(i);
 137       assert(ml.index() == noreg && mo.index() == noreg, "sanity");
 138       __ ld(R0, slot_offset + 0, OSR_buf);
 139       __ std(R0, ml.disp(), ml.base());
 140       __ ld(R0, slot_offset + 1*BytesPerWord, OSR_buf);
 141       __ std(R0, mo.disp(), mo.base());
 142     }
 143   }
 144 }
 145 
 146 
 147 int LIR_Assembler::emit_exception_handler() {
 148   // If the last instruction is a call (typically to do a throw which
 149   // is coming at the end after block reordering) the return address
 150   // must still point into the code area in order to avoid assertion
 151   // failures when searching for the corresponding bci => add a nop
 152   // (was bug 5/14/1999 - gri).
 153   __ nop();
 154 
 155   // Generate code for the exception handler.
 156   address handler_base = __ start_a_stub(exception_handler_size());
 157 
 158   if (handler_base == NULL) {
 159     // Not enough space left for the handler.
 160     bailout("exception handler overflow");
 161     return -1;
 162   }
 163 
 164   int offset = code_offset();
 165   address entry_point = CAST_FROM_FN_PTR(address, Runtime1::entry_for(Runtime1::handle_exception_from_callee_id));
 166   //__ load_const_optimized(R0, entry_point);
 167   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(entry_point));
 168   __ mtctr(R0);
 169   __ bctr();
 170 
 171   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 172   __ end_a_stub();
 173 
 174   return offset;
 175 }
 176 
 177 
 178 // Emit the code to remove the frame from the stack in the exception
 179 // unwind path.
 180 int LIR_Assembler::emit_unwind_handler() {
 181   _masm->block_comment("Unwind handler");
 182 
 183   int offset = code_offset();
 184   bool preserve_exception = method()->is_synchronized() || compilation()->env()->dtrace_method_probes();
 185   const Register Rexception = R3 /*LIRGenerator::exceptionOopOpr()*/, Rexception_save = R31;
 186 
 187   // Fetch the exception from TLS and clear out exception related thread state.
 188   __ ld(Rexception, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 189   __ li(R0, 0);
 190   __ std(R0, in_bytes(JavaThread::exception_oop_offset()), R16_thread);
 191   __ std(R0, in_bytes(JavaThread::exception_pc_offset()), R16_thread);
 192 
 193   __ bind(_unwind_handler_entry);
 194   __ verify_not_null_oop(Rexception);
 195   if (preserve_exception) { __ mr(Rexception_save, Rexception); }
 196 
 197   // Perform needed unlocking
 198   MonitorExitStub* stub = NULL;
 199   if (method()->is_synchronized()) {
 200     monitor_address(0, FrameMap::R4_opr);
 201     stub = new MonitorExitStub(FrameMap::R4_opr, true, 0);
 202     __ unlock_object(R5, R6, R4, *stub->entry());
 203     __ bind(*stub->continuation());
 204   }
 205 
 206   if (compilation()->env()->dtrace_method_probes()) {
 207     Unimplemented();
 208   }
 209 
 210   // Dispatch to the unwind logic.
 211   address unwind_stub = Runtime1::entry_for(Runtime1::unwind_exception_id);
 212   //__ load_const_optimized(R0, unwind_stub);
 213   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(unwind_stub));
 214   if (preserve_exception) { __ mr(Rexception, Rexception_save); }
 215   __ mtctr(R0);
 216   __ bctr();
 217 
 218   // Emit the slow path assembly.
 219   if (stub != NULL) {
 220     stub->emit_code(this);
 221   }
 222 
 223   return offset;
 224 }
 225 
 226 
 227 int LIR_Assembler::emit_deopt_handler() {
 228   // If the last instruction is a call (typically to do a throw which
 229   // is coming at the end after block reordering) the return address
 230   // must still point into the code area in order to avoid assertion
 231   // failures when searching for the corresponding bci => add a nop
 232   // (was bug 5/14/1999 - gri).
 233   __ nop();
 234 
 235   // Generate code for deopt handler.
 236   address handler_base = __ start_a_stub(deopt_handler_size());
 237 
 238   if (handler_base == NULL) {
 239     // Not enough space left for the handler.
 240     bailout("deopt handler overflow");
 241     return -1;
 242   }
 243 
 244   int offset = code_offset();
 245   __ bl64_patchable(SharedRuntime::deopt_blob()->unpack(), relocInfo::runtime_call_type);
 246 
 247   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 248   __ end_a_stub();
 249 
 250   return offset;
 251 }
 252 
 253 
 254 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 255   if (o == NULL) {
 256     __ li(reg, 0);
 257   } else {
 258     AddressLiteral addrlit = __ constant_oop_address(o);
 259     __ load_const(reg, addrlit, (reg != R0) ? R0 : noreg);
 260   }
 261 }
 262 
 263 
 264 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 265   // Allocate a new index in table to hold the object once it's been patched.
 266   int oop_index = __ oop_recorder()->allocate_oop_index(NULL);
 267   PatchingStub* patch = new PatchingStub(_masm, patching_id(info), oop_index);
 268 
 269   AddressLiteral addrlit((address)NULL, oop_Relocation::spec(oop_index));
 270   __ load_const(reg, addrlit, R0);
 271 
 272   patching_epilog(patch, lir_patch_normal, reg, info);
 273 }
 274 
 275 
 276 void LIR_Assembler::metadata2reg(Metadata* o, Register reg) {
 277   AddressLiteral md = __ constant_metadata_address(o); // Notify OOP recorder (don't need the relocation)
 278   __ load_const_optimized(reg, md.value(), (reg != R0) ? R0 : noreg);
 279 }
 280 
 281 
 282 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo *info) {
 283   // Allocate a new index in table to hold the klass once it's been patched.
 284   int index = __ oop_recorder()->allocate_metadata_index(NULL);
 285   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, index);
 286 
 287   AddressLiteral addrlit((address)NULL, metadata_Relocation::spec(index));
 288   assert(addrlit.rspec().type() == relocInfo::metadata_type, "must be an metadata reloc");
 289   __ load_const(reg, addrlit, R0);
 290 
 291   patching_epilog(patch, lir_patch_normal, reg, info);
 292 }
 293 
 294 
 295 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
 296   const bool is_int = result->is_single_cpu();
 297   Register Rdividend = is_int ? left->as_register() : left->as_register_lo();
 298   Register Rdivisor  = noreg;
 299   Register Rscratch  = temp->as_register();
 300   Register Rresult   = is_int ? result->as_register() : result->as_register_lo();
 301   long divisor = -1;
 302 
 303   if (right->is_register()) {
 304     Rdivisor = is_int ? right->as_register() : right->as_register_lo();
 305   } else {
 306     divisor = is_int ? right->as_constant_ptr()->as_jint()
 307                      : right->as_constant_ptr()->as_jlong();
 308   }
 309 
 310   assert(Rdividend != Rscratch, "");
 311   assert(Rdivisor  != Rscratch, "");
 312   assert(code == lir_idiv || code == lir_irem, "Must be irem or idiv");
 313 
 314   if (Rdivisor == noreg) {
 315     if (divisor == 1) { // stupid, but can happen
 316       if (code == lir_idiv) {
 317         __ mr_if_needed(Rresult, Rdividend);
 318       } else {
 319         __ li(Rresult, 0);
 320       }
 321 
 322     } else if (is_power_of_2(divisor)) {
 323       // Convert division by a power of two into some shifts and logical operations.
 324       int log2 = log2_intptr(divisor);
 325 
 326       // Round towards 0.
 327       if (divisor == 2) {
 328         if (is_int) {
 329           __ srwi(Rscratch, Rdividend, 31);
 330         } else {
 331           __ srdi(Rscratch, Rdividend, 63);
 332         }
 333       } else {
 334         if (is_int) {
 335           __ srawi(Rscratch, Rdividend, 31);
 336         } else {
 337           __ sradi(Rscratch, Rdividend, 63);
 338         }
 339         __ clrldi(Rscratch, Rscratch, 64-log2);
 340       }
 341       __ add(Rscratch, Rdividend, Rscratch);
 342 
 343       if (code == lir_idiv) {
 344         if (is_int) {
 345           __ srawi(Rresult, Rscratch, log2);
 346         } else {
 347           __ sradi(Rresult, Rscratch, log2);
 348         }
 349       } else { // lir_irem
 350         __ clrrdi(Rscratch, Rscratch, log2);
 351         __ sub(Rresult, Rdividend, Rscratch);
 352       }
 353 
 354     } else if (divisor == -1) {
 355       if (code == lir_idiv) {
 356         __ neg(Rresult, Rdividend);
 357       } else {
 358         __ li(Rresult, 0);
 359       }
 360 
 361     } else {
 362       __ load_const_optimized(Rscratch, divisor);
 363       if (code == lir_idiv) {
 364         if (is_int) {
 365           __ divw(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 366         } else {
 367           __ divd(Rresult, Rdividend, Rscratch); // Can't divide minint/-1.
 368         }
 369       } else {
 370         assert(Rscratch != R0, "need both");
 371         if (is_int) {
 372           __ divw(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 373           __ mullw(Rscratch, R0, Rscratch);
 374         } else {
 375           __ divd(R0, Rdividend, Rscratch); // Can't divide minint/-1.
 376           __ mulld(Rscratch, R0, Rscratch);
 377         }
 378         __ sub(Rresult, Rdividend, Rscratch);
 379       }
 380 
 381     }
 382     return;
 383   }
 384 
 385   Label regular, done;
 386   if (is_int) {
 387     __ cmpwi(CCR0, Rdivisor, -1);
 388   } else {
 389     __ cmpdi(CCR0, Rdivisor, -1);
 390   }
 391   __ bne(CCR0, regular);
 392   if (code == lir_idiv) {
 393     __ neg(Rresult, Rdividend);
 394     __ b(done);
 395     __ bind(regular);
 396     if (is_int) {
 397       __ divw(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 398     } else {
 399       __ divd(Rresult, Rdividend, Rdivisor); // Can't divide minint/-1.
 400     }
 401   } else { // lir_irem
 402     __ li(Rresult, 0);
 403     __ b(done);
 404     __ bind(regular);
 405     if (is_int) {
 406       __ divw(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 407       __ mullw(Rscratch, Rscratch, Rdivisor);
 408     } else {
 409       __ divd(Rscratch, Rdividend, Rdivisor); // Can't divide minint/-1.
 410       __ mulld(Rscratch, Rscratch, Rdivisor);
 411     }
 412     __ sub(Rresult, Rdividend, Rscratch);
 413   }
 414   __ bind(done);
 415 }
 416 
 417 
 418 void LIR_Assembler::emit_op3(LIR_Op3* op) {
 419   switch (op->code()) {
 420   case lir_idiv:
 421   case lir_irem:
 422     arithmetic_idiv(op->code(), op->in_opr1(), op->in_opr2(), op->in_opr3(),
 423                     op->result_opr(), op->info());
 424     break;
 425   case lir_fmad:
 426     __ fmadd(op->result_opr()->as_double_reg(), op->in_opr1()->as_double_reg(),
 427              op->in_opr2()->as_double_reg(), op->in_opr3()->as_double_reg());
 428     break;
 429   case lir_fmaf:
 430     __ fmadds(op->result_opr()->as_float_reg(), op->in_opr1()->as_float_reg(),
 431               op->in_opr2()->as_float_reg(), op->in_opr3()->as_float_reg());
 432     break;
 433   default: ShouldNotReachHere(); break;
 434   }
 435 }
 436 
 437 
 438 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
 439 #ifdef ASSERT
 440   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
 441   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
 442   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
 443   assert(op->info() == NULL, "shouldn't have CodeEmitInfo");
 444 #endif
 445 
 446   Label *L = op->label();
 447   if (op->cond() == lir_cond_always) {
 448     __ b(*L);
 449   } else {
 450     Label done;
 451     bool is_unordered = false;
 452     if (op->code() == lir_cond_float_branch) {
 453       assert(op->ublock() != NULL, "must have unordered successor");
 454       is_unordered = true;
 455     } else {
 456       assert(op->code() == lir_branch, "just checking");
 457     }
 458 
 459     bool positive = false;
 460     Assembler::Condition cond = Assembler::equal;
 461     switch (op->cond()) {
 462       case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; is_unordered = false; break;
 463       case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; is_unordered = false; break;
 464       case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
 465       case lir_cond_belowEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 466       case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
 467       case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
 468       case lir_cond_aboveEqual:   assert(op->code() != lir_cond_float_branch, ""); // fallthru
 469       case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
 470       default:                    ShouldNotReachHere();
 471     }
 472     int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
 473     int bi = Assembler::bi0(BOOL_RESULT, cond);
 474     if (is_unordered) {
 475       if (positive) {
 476         if (op->ublock() == op->block()) {
 477           __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(BOOL_RESULT, Assembler::summary_overflow), *L);
 478         }
 479       } else {
 480         if (op->ublock() != op->block()) { __ bso(BOOL_RESULT, done); }
 481       }
 482     }
 483     __ bc_far_optimized(bo, bi, *L);
 484     __ bind(done);
 485   }
 486 }
 487 
 488 
 489 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
 490   Bytecodes::Code code = op->bytecode();
 491   LIR_Opr src = op->in_opr(),
 492           dst = op->result_opr();
 493 
 494   switch(code) {
 495     case Bytecodes::_i2l: {
 496       __ extsw(dst->as_register_lo(), src->as_register());
 497       break;
 498     }
 499     case Bytecodes::_l2i: {
 500       __ mr_if_needed(dst->as_register(), src->as_register_lo()); // high bits are garbage
 501       break;
 502     }
 503     case Bytecodes::_i2b: {
 504       __ extsb(dst->as_register(), src->as_register());
 505       break;
 506     }
 507     case Bytecodes::_i2c: {
 508       __ clrldi(dst->as_register(), src->as_register(), 64-16);
 509       break;
 510     }
 511     case Bytecodes::_i2s: {
 512       __ extsh(dst->as_register(), src->as_register());
 513       break;
 514     }
 515     case Bytecodes::_i2d:
 516     case Bytecodes::_l2d: {
 517       bool src_in_memory = !VM_Version::has_mtfprd();
 518       FloatRegister rdst = dst->as_double_reg();
 519       FloatRegister rsrc;
 520       if (src_in_memory) {
 521         rsrc = src->as_double_reg(); // via mem
 522       } else {
 523         // move src to dst register
 524         if (code == Bytecodes::_i2d) {
 525           __ mtfprwa(rdst, src->as_register());
 526         } else {
 527           __ mtfprd(rdst, src->as_register_lo());
 528         }
 529         rsrc = rdst;
 530       }
 531       __ fcfid(rdst, rsrc);
 532       break;
 533     }
 534     case Bytecodes::_i2f:
 535     case Bytecodes::_l2f: {
 536       bool src_in_memory = !VM_Version::has_mtfprd();
 537       FloatRegister rdst = dst->as_float_reg();
 538       FloatRegister rsrc;
 539       if (src_in_memory) {
 540         rsrc = src->as_double_reg(); // via mem
 541       } else {
 542         // move src to dst register
 543         if (code == Bytecodes::_i2f) {
 544           __ mtfprwa(rdst, src->as_register());
 545         } else {
 546           __ mtfprd(rdst, src->as_register_lo());
 547         }
 548         rsrc = rdst;
 549       }
 550       if (VM_Version::has_fcfids()) {
 551         __ fcfids(rdst, rsrc);
 552       } else {
 553         assert(code == Bytecodes::_i2f, "fcfid+frsp needs fixup code to avoid rounding incompatibility");
 554         __ fcfid(rdst, rsrc);
 555         __ frsp(rdst, rdst);
 556       }
 557       break;
 558     }





 559     case Bytecodes::_f2d: {
 560       __ fmr_if_needed(dst->as_double_reg(), src->as_float_reg());
 561       break;
 562     }
 563     case Bytecodes::_d2f: {
 564       __ frsp(dst->as_float_reg(), src->as_double_reg());
 565       break;
 566     }
 567     case Bytecodes::_d2i:
 568     case Bytecodes::_f2i: {
 569       bool dst_in_memory = !VM_Version::has_mtfprd();
 570       FloatRegister rsrc = (code == Bytecodes::_d2i) ? src->as_double_reg() : src->as_float_reg();
 571       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 572       Label L;
 573       // Result must be 0 if value is NaN; test by comparing value to itself.
 574       __ fcmpu(CCR0, rsrc, rsrc);
 575       if (dst_in_memory) {
 576         __ li(R0, 0); // 0 in case of NAN
 577         __ std(R0, addr.disp(), addr.base());
 578       } else {
 579         __ li(dst->as_register(), 0);
 580       }
 581       __ bso(CCR0, L);
 582       __ fctiwz(rsrc, rsrc); // USE_KILL
 583       if (dst_in_memory) {
 584         __ stfd(rsrc, addr.disp(), addr.base());
 585       } else {
 586         __ mffprd(dst->as_register(), rsrc);
 587       }
 588       __ bind(L);
 589       break;
 590     }
 591     case Bytecodes::_d2l:
 592     case Bytecodes::_f2l: {
 593       bool dst_in_memory = !VM_Version::has_mtfprd();
 594       FloatRegister rsrc = (code == Bytecodes::_d2l) ? src->as_double_reg() : src->as_float_reg();
 595       Address       addr = dst_in_memory ? frame_map()->address_for_slot(dst->double_stack_ix()) : NULL;
 596       Label L;
 597       // Result must be 0 if value is NaN; test by comparing value to itself.
 598       __ fcmpu(CCR0, rsrc, rsrc);
 599       if (dst_in_memory) {
 600         __ li(R0, 0); // 0 in case of NAN
 601         __ std(R0, addr.disp(), addr.base());
 602       } else {
 603         __ li(dst->as_register_lo(), 0);
 604       }
 605       __ bso(CCR0, L);
 606       __ fctidz(rsrc, rsrc); // USE_KILL
 607       if (dst_in_memory) {
 608         __ stfd(rsrc, addr.disp(), addr.base());
 609       } else {
 610         __ mffprd(dst->as_register_lo(), rsrc);
 611       }
 612       __ bind(L);
 613       break;
 614     }
 615 
 616     default: ShouldNotReachHere();
 617   }
 618 }
 619 
 620 
 621 void LIR_Assembler::align_call(LIR_Code) {
 622   // do nothing since all instructions are word aligned on ppc
 623 }
 624 
 625 
 626 bool LIR_Assembler::emit_trampoline_stub_for_call(address target, Register Rtoc) {
 627   int start_offset = __ offset();
 628   // Put the entry point as a constant into the constant pool.
 629   const address entry_point_toc_addr   = __ address_constant(target, RelocationHolder::none);
 630   if (entry_point_toc_addr == NULL) {
 631     bailout("const section overflow");
 632     return false;
 633   }
 634   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
 635 
 636   // Emit the trampoline stub which will be related to the branch-and-link below.
 637   address stub = __ emit_trampoline_stub(entry_point_toc_offset, start_offset, Rtoc);
 638   if (!stub) {
 639     bailout("no space for trampoline stub");
 640     return false;
 641   }
 642   return true;
 643 }
 644 
 645 
 646 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
 647   assert(rtype==relocInfo::opt_virtual_call_type || rtype==relocInfo::static_call_type, "unexpected rtype");
 648 
 649   bool success = emit_trampoline_stub_for_call(op->addr());
 650   if (!success) { return; }
 651 
 652   __ relocate(rtype);
 653   // Note: At this point we do not have the address of the trampoline
 654   // stub, and the entry point might be too far away for bl, so __ pc()
 655   // serves as dummy and the bl will be patched later.
 656   __ code()->set_insts_mark();
 657   __ bl(__ pc());
 658   add_call_info(code_offset(), op->info());
 659 }
 660 
 661 
 662 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
 663   __ calculate_address_from_global_toc(R2_TOC, __ method_toc());
 664 
 665   // Virtual call relocation will point to ic load.
 666   address virtual_call_meta_addr = __ pc();
 667   // Load a clear inline cache.
 668   AddressLiteral empty_ic((address) Universe::non_oop_word());
 669   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, empty_ic, R2_TOC);
 670   if (!success) {
 671     bailout("const section overflow");
 672     return;
 673   }
 674   // Call to fixup routine. Fixup routine uses ScopeDesc info
 675   // to determine who we intended to call.
 676   __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
 677 
 678   success = emit_trampoline_stub_for_call(op->addr(), R2_TOC);
 679   if (!success) { return; }
 680 
 681   // Note: At this point we do not have the address of the trampoline
 682   // stub, and the entry point might be too far away for bl, so __ pc()
 683   // serves as dummy and the bl will be patched later.
 684   __ bl(__ pc());
 685   add_call_info(code_offset(), op->info());
 686 }
 687 
 688 
 689 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
 690   ShouldNotReachHere(); // ic_call is used instead.
 691 }
 692 
 693 
 694 void LIR_Assembler::explicit_null_check(Register addr, CodeEmitInfo* info) {
 695   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(code_offset(), info);
 696   __ null_check(addr, stub->entry());
 697   append_code_stub(stub);
 698 }
 699 
 700 
 701 // Attention: caller must encode oop if needed
 702 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool wide, bool unaligned) {
 703   int store_offset;
 704   if (!Assembler::is_simm16(offset)) {
 705     // For offsets larger than a simm16 we setup the offset.
 706     assert(wide && !from_reg->is_same_register(FrameMap::R0_opr), "large offset only supported in special case");
 707     __ load_const_optimized(R0, offset);
 708     store_offset = store(from_reg, base, R0, type, wide);
 709   } else {
 710     store_offset = code_offset();
 711     switch (type) {
 712       case T_BOOLEAN: // fall through
 713       case T_BYTE  : __ stb(from_reg->as_register(), offset, base); break;
 714       case T_CHAR  :
 715       case T_SHORT : __ sth(from_reg->as_register(), offset, base); break;
 716       case T_INT   : __ stw(from_reg->as_register(), offset, base); break;
 717       case T_LONG  : __ std(from_reg->as_register_lo(), offset, base); break;
 718       case T_ADDRESS:
 719       case T_METADATA: __ std(from_reg->as_register(), offset, base); break;
 720       case T_ARRAY : // fall through
 721       case T_OBJECT:
 722         {
 723           if (UseCompressedOops && !wide) {
 724             // Encoding done in caller
 725             __ stw(from_reg->as_register(), offset, base);
 726           } else {
 727             __ std(from_reg->as_register(), offset, base);
 728           }
 729           __ verify_oop(from_reg->as_register());
 730           break;
 731         }
 732       case T_FLOAT : __ stfs(from_reg->as_float_reg(), offset, base); break;
 733       case T_DOUBLE: __ stfd(from_reg->as_double_reg(), offset, base); break;
 734       default      : ShouldNotReachHere();
 735     }
 736   }
 737   return store_offset;
 738 }
 739 
 740 
 741 // Attention: caller must encode oop if needed
 742 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type, bool wide) {
 743   int store_offset = code_offset();
 744   switch (type) {
 745     case T_BOOLEAN: // fall through
 746     case T_BYTE  : __ stbx(from_reg->as_register(), base, disp); break;
 747     case T_CHAR  :
 748     case T_SHORT : __ sthx(from_reg->as_register(), base, disp); break;
 749     case T_INT   : __ stwx(from_reg->as_register(), base, disp); break;
 750     case T_LONG  :
 751 #ifdef _LP64
 752       __ stdx(from_reg->as_register_lo(), base, disp);
 753 #else
 754       Unimplemented();
 755 #endif
 756       break;
 757     case T_ADDRESS:
 758       __ stdx(from_reg->as_register(), base, disp);
 759       break;
 760     case T_ARRAY : // fall through
 761     case T_OBJECT:
 762       {
 763         if (UseCompressedOops && !wide) {
 764           // Encoding done in caller.
 765           __ stwx(from_reg->as_register(), base, disp);
 766         } else {
 767           __ stdx(from_reg->as_register(), base, disp);
 768         }
 769         __ verify_oop(from_reg->as_register()); // kills R0
 770         break;
 771       }
 772     case T_FLOAT : __ stfsx(from_reg->as_float_reg(), base, disp); break;
 773     case T_DOUBLE: __ stfdx(from_reg->as_double_reg(), base, disp); break;
 774     default      : ShouldNotReachHere();
 775   }
 776   return store_offset;
 777 }
 778 
 779 
 780 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool wide, bool unaligned) {
 781   int load_offset;
 782   if (!Assembler::is_simm16(offset)) {
 783     // For offsets larger than a simm16 we setup the offset.
 784     __ load_const_optimized(R0, offset);
 785     load_offset = load(base, R0, to_reg, type, wide);
 786   } else {
 787     load_offset = code_offset();
 788     switch(type) {
 789       case T_BOOLEAN: // fall through
 790       case T_BYTE  :   __ lbz(to_reg->as_register(), offset, base);
 791                        __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 792       case T_CHAR  :   __ lhz(to_reg->as_register(), offset, base); break;
 793       case T_SHORT :   __ lha(to_reg->as_register(), offset, base); break;
 794       case T_INT   :   __ lwa(to_reg->as_register(), offset, base); break;
 795       case T_LONG  :   __ ld(to_reg->as_register_lo(), offset, base); break;
 796       case T_METADATA: __ ld(to_reg->as_register(), offset, base); break;
 797       case T_ADDRESS:
 798         if (offset == oopDesc::klass_offset_in_bytes() && UseCompressedClassPointers) {
 799           __ lwz(to_reg->as_register(), offset, base);
 800           __ decode_klass_not_null(to_reg->as_register());
 801         } else {
 802           __ ld(to_reg->as_register(), offset, base);
 803         }
 804         break;
 805       case T_ARRAY : // fall through
 806       case T_OBJECT:
 807         {
 808           if (UseCompressedOops && !wide) {
 809             __ lwz(to_reg->as_register(), offset, base);
 810             __ decode_heap_oop(to_reg->as_register());
 811           } else {
 812             __ ld(to_reg->as_register(), offset, base);
 813           }
 814           __ verify_oop(to_reg->as_register());
 815           break;
 816         }
 817       case T_FLOAT:  __ lfs(to_reg->as_float_reg(), offset, base); break;
 818       case T_DOUBLE: __ lfd(to_reg->as_double_reg(), offset, base); break;
 819       default      : ShouldNotReachHere();
 820     }
 821   }
 822   return load_offset;
 823 }
 824 
 825 
 826 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type, bool wide) {
 827   int load_offset = code_offset();
 828   switch(type) {
 829     case T_BOOLEAN: // fall through
 830     case T_BYTE  :  __ lbzx(to_reg->as_register(), base, disp);
 831                     __ extsb(to_reg->as_register(), to_reg->as_register()); break;
 832     case T_CHAR  :  __ lhzx(to_reg->as_register(), base, disp); break;
 833     case T_SHORT :  __ lhax(to_reg->as_register(), base, disp); break;
 834     case T_INT   :  __ lwax(to_reg->as_register(), base, disp); break;
 835     case T_ADDRESS: __ ldx(to_reg->as_register(), base, disp); break;
 836     case T_ARRAY : // fall through
 837     case T_OBJECT:
 838       {
 839         if (UseCompressedOops && !wide) {
 840           __ lwzx(to_reg->as_register(), base, disp);
 841           __ decode_heap_oop(to_reg->as_register());
 842         } else {
 843           __ ldx(to_reg->as_register(), base, disp);
 844         }
 845         __ verify_oop(to_reg->as_register());
 846         break;
 847       }
 848     case T_FLOAT:  __ lfsx(to_reg->as_float_reg() , base, disp); break;
 849     case T_DOUBLE: __ lfdx(to_reg->as_double_reg(), base, disp); break;
 850     case T_LONG  :
 851 #ifdef _LP64
 852       __ ldx(to_reg->as_register_lo(), base, disp);
 853 #else
 854       Unimplemented();
 855 #endif
 856       break;
 857     default      : ShouldNotReachHere();
 858   }
 859   return load_offset;
 860 }
 861 
 862 
 863 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 864   LIR_Const* c = src->as_constant_ptr();
 865   Register src_reg = R0;
 866   switch (c->type()) {
 867     case T_INT:
 868     case T_FLOAT: {
 869       int value = c->as_jint_bits();
 870       __ load_const_optimized(src_reg, value);
 871       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 872       __ stw(src_reg, addr.disp(), addr.base());
 873       break;
 874     }
 875     case T_ADDRESS: {
 876       int value = c->as_jint_bits();
 877       __ load_const_optimized(src_reg, value);
 878       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 879       __ std(src_reg, addr.disp(), addr.base());
 880       break;
 881     }
 882     case T_OBJECT: {
 883       jobject2reg(c->as_jobject(), src_reg);
 884       Address addr = frame_map()->address_for_slot(dest->single_stack_ix());
 885       __ std(src_reg, addr.disp(), addr.base());
 886       break;
 887     }
 888     case T_LONG:
 889     case T_DOUBLE: {
 890       int value = c->as_jlong_bits();
 891       __ load_const_optimized(src_reg, value);
 892       Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix());
 893       __ std(src_reg, addr.disp(), addr.base());
 894       break;
 895     }
 896     default:
 897       Unimplemented();
 898   }
 899 }
 900 
 901 
 902 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 903   LIR_Const* c = src->as_constant_ptr();
 904   LIR_Address* addr = dest->as_address_ptr();
 905   Register base = addr->base()->as_pointer_register();
 906   LIR_Opr tmp = LIR_OprFact::illegalOpr;
 907   int offset = -1;
 908   // Null check for large offsets in LIRGenerator::do_StoreField.
 909   bool needs_explicit_null_check = !ImplicitNullChecks;
 910 
 911   if (info != NULL && needs_explicit_null_check) {
 912     explicit_null_check(base, info);
 913   }
 914 
 915   switch (c->type()) {
 916     case T_FLOAT: type = T_INT;
 917     case T_INT:
 918     case T_ADDRESS: {
 919       tmp = FrameMap::R0_opr;
 920       __ load_const_optimized(tmp->as_register(), c->as_jint_bits());
 921       break;
 922     }
 923     case T_DOUBLE: type = T_LONG;
 924     case T_LONG: {
 925       tmp = FrameMap::R0_long_opr;
 926       __ load_const_optimized(tmp->as_register_lo(), c->as_jlong_bits());
 927       break;
 928     }
 929     case T_OBJECT: {
 930       tmp = FrameMap::R0_opr;
 931       if (UseCompressedOops && !wide && c->as_jobject() != NULL) {
 932         AddressLiteral oop_addr = __ constant_oop_address(c->as_jobject());
 933         __ lis(R0, oop_addr.value() >> 16); // Don't care about sign extend (will use stw).
 934         __ relocate(oop_addr.rspec(), /*compressed format*/ 1);
 935         __ ori(R0, R0, oop_addr.value() & 0xffff);
 936       } else {
 937         jobject2reg(c->as_jobject(), R0);
 938       }
 939       break;
 940     }
 941     default:
 942       Unimplemented();
 943   }
 944 
 945   // Handle either reg+reg or reg+disp address.
 946   if (addr->index()->is_valid()) {
 947     assert(addr->disp() == 0, "must be zero");
 948     offset = store(tmp, base, addr->index()->as_pointer_register(), type, wide);
 949   } else {
 950     assert(Assembler::is_simm16(addr->disp()), "can't handle larger addresses");
 951     offset = store(tmp, base, addr->disp(), type, wide, false);
 952   }
 953 
 954   if (info != NULL) {
 955     assert(offset != -1, "offset should've been set");
 956     if (!needs_explicit_null_check) {
 957       add_debug_info_for_null_check(offset, info);
 958     }
 959   }
 960 }
 961 
 962 
 963 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 964   LIR_Const* c = src->as_constant_ptr();
 965   LIR_Opr to_reg = dest;
 966 
 967   switch (c->type()) {
 968     case T_INT: {
 969       assert(patch_code == lir_patch_none, "no patching handled here");
 970       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);
 971       break;
 972     }
 973     case T_ADDRESS: {
 974       assert(patch_code == lir_patch_none, "no patching handled here");
 975       __ load_const_optimized(dest->as_register(), c->as_jint(), R0);  // Yes, as_jint ...
 976       break;
 977     }
 978     case T_LONG: {
 979       assert(patch_code == lir_patch_none, "no patching handled here");
 980       __ load_const_optimized(dest->as_register_lo(), c->as_jlong(), R0);
 981       break;
 982     }
 983 
 984     case T_OBJECT: {
 985       if (patch_code == lir_patch_none) {
 986         jobject2reg(c->as_jobject(), to_reg->as_register());
 987       } else {
 988         jobject2reg_with_patching(to_reg->as_register(), info);
 989       }
 990       break;
 991     }
 992 
 993     case T_METADATA:
 994       {
 995         if (patch_code == lir_patch_none) {
 996           metadata2reg(c->as_metadata(), to_reg->as_register());
 997         } else {
 998           klass2reg_with_patching(to_reg->as_register(), info);
 999         }
1000       }
1001       break;
1002 
1003     case T_FLOAT:
1004       {
1005         if (to_reg->is_single_fpu()) {
1006           address const_addr = __ float_constant(c->as_jfloat());
1007           if (const_addr == NULL) {
1008             bailout("const section overflow");
1009             break;
1010           }
1011           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1012           __ relocate(rspec);
1013           __ load_const(R0, const_addr);
1014           __ lfsx(to_reg->as_float_reg(), R0);
1015         } else {
1016           assert(to_reg->is_single_cpu(), "Must be a cpu register.");
1017           __ load_const_optimized(to_reg->as_register(), jint_cast(c->as_jfloat()), R0);
1018         }
1019       }
1020       break;
1021 
1022     case T_DOUBLE:
1023       {
1024         if (to_reg->is_double_fpu()) {
1025           address const_addr = __ double_constant(c->as_jdouble());
1026           if (const_addr == NULL) {
1027             bailout("const section overflow");
1028             break;
1029           }
1030           RelocationHolder rspec = internal_word_Relocation::spec(const_addr);
1031           __ relocate(rspec);
1032           __ load_const(R0, const_addr);
1033           __ lfdx(to_reg->as_double_reg(), R0);
1034         } else {
1035           assert(to_reg->is_double_cpu(), "Must be a long register.");
1036           __ load_const_optimized(to_reg->as_register_lo(), jlong_cast(c->as_jdouble()), R0);
1037         }
1038       }
1039       break;
1040 
1041     default:
1042       ShouldNotReachHere();
1043   }
1044 }
1045 
1046 
1047 Address LIR_Assembler::as_Address(LIR_Address* addr) {
1048   Unimplemented(); return Address();
1049 }
1050 
1051 
1052 inline RegisterOrConstant index_or_disp(LIR_Address* addr) {
1053   if (addr->index()->is_illegal()) {
1054     return (RegisterOrConstant)(addr->disp());
1055   } else {
1056     return (RegisterOrConstant)(addr->index()->as_pointer_register());
1057   }
1058 }
1059 
1060 
1061 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1062   const Register tmp = R0;
1063   switch (type) {
1064     case T_INT:
1065     case T_FLOAT: {
1066       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1067       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1068       __ lwz(tmp, from.disp(), from.base());
1069       __ stw(tmp, to.disp(), to.base());
1070       break;
1071     }
1072     case T_ADDRESS:
1073     case T_OBJECT: {
1074       Address from = frame_map()->address_for_slot(src->single_stack_ix());
1075       Address to   = frame_map()->address_for_slot(dest->single_stack_ix());
1076       __ ld(tmp, from.disp(), from.base());
1077       __ std(tmp, to.disp(), to.base());
1078       break;
1079     }
1080     case T_LONG:
1081     case T_DOUBLE: {
1082       Address from = frame_map()->address_for_double_slot(src->double_stack_ix());
1083       Address to   = frame_map()->address_for_double_slot(dest->double_stack_ix());
1084       __ ld(tmp, from.disp(), from.base());
1085       __ std(tmp, to.disp(), to.base());
1086       break;
1087     }
1088 
1089     default:
1090       ShouldNotReachHere();
1091   }
1092 }
1093 
1094 
1095 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
1096   Unimplemented(); return Address();
1097 }
1098 
1099 
1100 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
1101   Unimplemented(); return Address();
1102 }
1103 
1104 
1105 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type,
1106                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool unaligned) {
1107 
1108   assert(type != T_METADATA, "load of metadata ptr not supported");
1109   LIR_Address* addr = src_opr->as_address_ptr();
1110   LIR_Opr to_reg = dest;
1111 
1112   Register src = addr->base()->as_pointer_register();
1113   Register disp_reg = noreg;
1114   int disp_value = addr->disp();
1115   bool needs_patching = (patch_code != lir_patch_none);
1116   // null check for large offsets in LIRGenerator::do_LoadField
1117   bool needs_explicit_null_check = !os::zero_page_read_protected() || !ImplicitNullChecks;
1118 
1119   if (info != NULL && needs_explicit_null_check) {
1120     explicit_null_check(src, info);
1121   }
1122 
1123   if (addr->base()->type() == T_OBJECT) {
1124     __ verify_oop(src);
1125   }
1126 
1127   PatchingStub* patch = NULL;
1128   if (needs_patching) {
1129     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1130     assert(!to_reg->is_double_cpu() ||
1131            patch_code == lir_patch_none ||
1132            patch_code == lir_patch_normal, "patching doesn't match register");
1133   }
1134 
1135   if (addr->index()->is_illegal()) {
1136     if (!Assembler::is_simm16(disp_value)) {
1137       if (needs_patching) {
1138         __ load_const32(R0, 0); // patchable int
1139       } else {
1140         __ load_const_optimized(R0, disp_value);
1141       }
1142       disp_reg = R0;
1143     }
1144   } else {
1145     disp_reg = addr->index()->as_pointer_register();
1146     assert(disp_value == 0, "can't handle 3 operand addresses");
1147   }
1148 
1149   // Remember the offset of the load. The patching_epilog must be done
1150   // before the call to add_debug_info, otherwise the PcDescs don't get
1151   // entered in increasing order.
1152   int offset;
1153 
1154   if (disp_reg == noreg) {
1155     assert(Assembler::is_simm16(disp_value), "should have set this up");
1156     offset = load(src, disp_value, to_reg, type, wide, unaligned);
1157   } else {
1158     assert(!unaligned, "unexpected");
1159     offset = load(src, disp_reg, to_reg, type, wide);
1160   }
1161 
1162   if (patch != NULL) {
1163     patching_epilog(patch, patch_code, src, info);
1164   }
1165   if (info != NULL && !needs_explicit_null_check) {
1166     add_debug_info_for_null_check(offset, info);
1167   }
1168 }
1169 
1170 
1171 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1172   Address addr;
1173   if (src->is_single_word()) {
1174     addr = frame_map()->address_for_slot(src->single_stack_ix());
1175   } else if (src->is_double_word())  {
1176     addr = frame_map()->address_for_double_slot(src->double_stack_ix());
1177   }
1178 
1179   bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1180   load(addr.base(), addr.disp(), dest, dest->type(), true /*wide*/, unaligned);
1181 }
1182 
1183 
1184 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
1185   Address addr;
1186   if (dest->is_single_word()) {
1187     addr = frame_map()->address_for_slot(dest->single_stack_ix());
1188   } else if (dest->is_double_word())  {
1189     addr = frame_map()->address_for_slot(dest->double_stack_ix());
1190   }
1191   bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0;
1192   store(from_reg, addr.base(), addr.disp(), from_reg->type(), true /*wide*/, unaligned);
1193 }
1194 
1195 
1196 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) {
1197   if (from_reg->is_float_kind() && to_reg->is_float_kind()) {
1198     if (from_reg->is_double_fpu()) {
1199       // double to double moves
1200       assert(to_reg->is_double_fpu(), "should match");
1201       __ fmr_if_needed(to_reg->as_double_reg(), from_reg->as_double_reg());
1202     } else {
1203       // float to float moves
1204       assert(to_reg->is_single_fpu(), "should match");
1205       __ fmr_if_needed(to_reg->as_float_reg(), from_reg->as_float_reg());
1206     }
1207   } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) {
1208     if (from_reg->is_double_cpu()) {
1209       __ mr_if_needed(to_reg->as_pointer_register(), from_reg->as_pointer_register());
1210     } else if (to_reg->is_double_cpu()) {
1211       // int to int moves
1212       __ mr_if_needed(to_reg->as_register_lo(), from_reg->as_register());
1213     } else {
1214       // int to int moves
1215       __ mr_if_needed(to_reg->as_register(), from_reg->as_register());
1216     }
1217   } else {
1218     ShouldNotReachHere();
1219   }
1220   if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) {
1221     __ verify_oop(to_reg->as_register());
1222   }
1223 }
1224 
1225 
1226 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type,
1227                             LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack,
1228                             bool wide, bool unaligned) {
1229   assert(type != T_METADATA, "store of metadata ptr not supported");
1230   LIR_Address* addr = dest->as_address_ptr();
1231 
1232   Register src = addr->base()->as_pointer_register();
1233   Register disp_reg = noreg;
1234   int disp_value = addr->disp();
1235   bool needs_patching = (patch_code != lir_patch_none);
1236   bool compress_oop = (type == T_ARRAY || type == T_OBJECT) && UseCompressedOops && !wide &&
1237                       Universe::narrow_oop_mode() != Universe::UnscaledNarrowOop;
1238   bool load_disp = addr->index()->is_illegal() && !Assembler::is_simm16(disp_value);
1239   bool use_R29 = compress_oop && load_disp; // Avoid register conflict, also do null check before killing R29.
1240   // Null check for large offsets in LIRGenerator::do_StoreField.
1241   bool needs_explicit_null_check = !ImplicitNullChecks || use_R29;
1242 
1243   if (info != NULL && needs_explicit_null_check) {
1244     explicit_null_check(src, info);
1245   }
1246 
1247   if (addr->base()->is_oop_register()) {
1248     __ verify_oop(src);
1249   }
1250 
1251   PatchingStub* patch = NULL;
1252   if (needs_patching) {
1253     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1254     assert(!from_reg->is_double_cpu() ||
1255            patch_code == lir_patch_none ||
1256            patch_code == lir_patch_normal, "patching doesn't match register");
1257   }
1258 
1259   if (addr->index()->is_illegal()) {
1260     if (load_disp) {
1261       disp_reg = use_R29 ? R29_TOC : R0;
1262       if (needs_patching) {
1263         __ load_const32(disp_reg, 0); // patchable int
1264       } else {
1265         __ load_const_optimized(disp_reg, disp_value);
1266       }
1267     }
1268   } else {
1269     disp_reg = addr->index()->as_pointer_register();
1270     assert(disp_value == 0, "can't handle 3 operand addresses");
1271   }
1272 
1273   // remember the offset of the store. The patching_epilog must be done
1274   // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get
1275   // entered in increasing order.
1276   int offset;
1277 
1278   if (compress_oop) {
1279     Register co = __ encode_heap_oop(R0, from_reg->as_register());
1280     from_reg = FrameMap::as_opr(co);
1281   }
1282 
1283   if (disp_reg == noreg) {
1284     assert(Assembler::is_simm16(disp_value), "should have set this up");
1285     offset = store(from_reg, src, disp_value, type, wide, unaligned);
1286   } else {
1287     assert(!unaligned, "unexpected");
1288     offset = store(from_reg, src, disp_reg, type, wide);
1289   }
1290 
1291   if (use_R29) {
1292     __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); // reinit
1293   }
1294 
1295   if (patch != NULL) {
1296     patching_epilog(patch, patch_code, src, info);
1297   }
1298 
1299   if (info != NULL && !needs_explicit_null_check) {
1300     add_debug_info_for_null_check(offset, info);
1301   }
1302 }
1303 
1304 
1305 void LIR_Assembler::return_op(LIR_Opr result) {
1306   const Register return_pc        = R31;  // Must survive C-call to enable_stack_reserved_zone().
1307   const Register polling_page     = R12;
1308 
1309   // Pop the stack before the safepoint code.
1310   int frame_size = initial_frame_size_in_bytes();
1311   if (Assembler::is_simm(frame_size, 16)) {
1312     __ addi(R1_SP, R1_SP, frame_size);
1313   } else {
1314     __ pop_frame();
1315   }
1316 
1317   if (LoadPollAddressFromThread) {
1318     // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1319     Unimplemented();
1320   } else {
1321     __ load_const_optimized(polling_page, (long)(address) os::get_polling_page(), R0); // TODO: PPC port: get_standard_polling_page()
1322   }
1323 
1324   // Restore return pc relative to callers' sp.
1325   __ ld(return_pc, _abi(lr), R1_SP);
1326   // Move return pc to LR.
1327   __ mtlr(return_pc);
1328 
1329   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
1330     __ reserved_stack_check(return_pc);
1331   }
1332 
1333   // We need to mark the code position where the load from the safepoint
1334   // polling page was emitted as relocInfo::poll_return_type here.
1335   __ relocate(relocInfo::poll_return_type);
1336   __ load_from_polling_page(polling_page);
1337 
1338   // Return.
1339   __ blr();
1340 }
1341 
1342 
1343 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
1344 
1345   if (LoadPollAddressFromThread) {
1346     const Register poll_addr = tmp->as_register();
1347     // TODO: PPC port __ ld(poll_addr, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1348     Unimplemented();
1349     __ relocate(relocInfo::poll_type); // XXX
1350     guarantee(info != NULL, "Shouldn't be NULL");
1351     int offset = __ offset();
1352     add_debug_info_for_branch(info);
1353     __ load_from_polling_page(poll_addr);
1354     return offset;
1355   }
1356 
1357   __ load_const_optimized(tmp->as_register(), (intptr_t)os::get_polling_page(), R0); // TODO: PPC port: get_standard_polling_page()
1358   if (info != NULL) {
1359     add_debug_info_for_branch(info);
1360   }
1361   int offset = __ offset();
1362   __ relocate(relocInfo::poll_type);
1363   __ load_from_polling_page(tmp->as_register());
1364 
1365   return offset;
1366 }
1367 
1368 
1369 void LIR_Assembler::emit_static_call_stub() {
1370   address call_pc = __ pc();
1371   address stub = __ start_a_stub(static_call_stub_size());
1372   if (stub == NULL) {
1373     bailout("static call stub overflow");
1374     return;
1375   }
1376 
1377   // For java_to_interp stubs we use R11_scratch1 as scratch register
1378   // and in call trampoline stubs we use R12_scratch2. This way we
1379   // can distinguish them (see is_NativeCallTrampolineStub_at()).
1380   const Register reg_scratch = R11_scratch1;
1381 
1382   // Create a static stub relocation which relates this stub
1383   // with the call instruction at insts_call_instruction_offset in the
1384   // instructions code-section.
1385   int start = __ offset();
1386   __ relocate(static_stub_Relocation::spec(call_pc));
1387 
1388   // Now, create the stub's code:
1389   // - load the TOC
1390   // - load the inline cache oop from the constant pool
1391   // - load the call target from the constant pool
1392   // - call
1393   __ calculate_address_from_global_toc(reg_scratch, __ method_toc());
1394   AddressLiteral ic = __ allocate_metadata_address((Metadata *)NULL);
1395   bool success = __ load_const_from_method_toc(R19_inline_cache_reg, ic, reg_scratch, /*fixed_size*/ true);
1396 
1397   if (ReoptimizeCallSequences) {
1398     __ b64_patchable((address)-1, relocInfo::none);
1399   } else {
1400     AddressLiteral a((address)-1);
1401     success = success && __ load_const_from_method_toc(reg_scratch, a, reg_scratch, /*fixed_size*/ true);
1402     __ mtctr(reg_scratch);
1403     __ bctr();
1404   }
1405   if (!success) {
1406     bailout("const section overflow");
1407     return;
1408   }
1409 
1410   assert(__ offset() - start <= static_call_stub_size(), "stub too big");
1411   __ end_a_stub();
1412 }
1413 
1414 
1415 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1416   bool unsigned_comp = (condition == lir_cond_belowEqual || condition == lir_cond_aboveEqual);
1417   if (opr1->is_single_fpu()) {
1418     __ fcmpu(BOOL_RESULT, opr1->as_float_reg(), opr2->as_float_reg());
1419   } else if (opr1->is_double_fpu()) {
1420     __ fcmpu(BOOL_RESULT, opr1->as_double_reg(), opr2->as_double_reg());
1421   } else if (opr1->is_single_cpu()) {
1422     if (opr2->is_constant()) {
1423       switch (opr2->as_constant_ptr()->type()) {
1424         case T_INT:
1425           {
1426             jint con = opr2->as_constant_ptr()->as_jint();
1427             if (unsigned_comp) {
1428               if (Assembler::is_uimm(con, 16)) {
1429                 __ cmplwi(BOOL_RESULT, opr1->as_register(), con);
1430               } else {
1431                 __ load_const_optimized(R0, con);
1432                 __ cmplw(BOOL_RESULT, opr1->as_register(), R0);
1433               }
1434             } else {
1435               if (Assembler::is_simm(con, 16)) {
1436                 __ cmpwi(BOOL_RESULT, opr1->as_register(), con);
1437               } else {
1438                 __ load_const_optimized(R0, con);
1439                 __ cmpw(BOOL_RESULT, opr1->as_register(), R0);
1440               }
1441             }
1442           }
1443           break;
1444 
1445         case T_OBJECT:
1446           // There are only equal/notequal comparisons on objects.
1447           {
1448             assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "oops");
1449             jobject con = opr2->as_constant_ptr()->as_jobject();
1450             if (con == NULL) {
1451               __ cmpdi(BOOL_RESULT, opr1->as_register(), 0);
1452             } else {
1453               jobject2reg(con, R0);
1454               __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1455             }
1456           }
1457           break;
1458 
1459         default:
1460           ShouldNotReachHere();
1461           break;
1462       }
1463     } else {
1464       if (opr2->is_address()) {
1465         DEBUG_ONLY( Unimplemented(); ) // Seems to be unused at the moment.
1466         LIR_Address *addr = opr2->as_address_ptr();
1467         BasicType type = addr->type();
1468         if (type == T_OBJECT) { __ ld(R0, index_or_disp(addr), addr->base()->as_register()); }
1469         else                  { __ lwa(R0, index_or_disp(addr), addr->base()->as_register()); }
1470         __ cmpd(BOOL_RESULT, opr1->as_register(), R0);
1471       } else {
1472         if (unsigned_comp) {
1473           __ cmplw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1474         } else {
1475           __ cmpw(BOOL_RESULT, opr1->as_register(), opr2->as_register());
1476         }
1477       }
1478     }
1479   } else if (opr1->is_double_cpu()) {
1480     if (opr2->is_constant()) {
1481       jlong con = opr2->as_constant_ptr()->as_jlong();
1482       if (unsigned_comp) {
1483         if (Assembler::is_uimm(con, 16)) {
1484           __ cmpldi(BOOL_RESULT, opr1->as_register_lo(), con);
1485         } else {
1486           __ load_const_optimized(R0, con);
1487           __ cmpld(BOOL_RESULT, opr1->as_register_lo(), R0);
1488         }
1489       } else {
1490         if (Assembler::is_simm(con, 16)) {
1491           __ cmpdi(BOOL_RESULT, opr1->as_register_lo(), con);
1492         } else {
1493           __ load_const_optimized(R0, con);
1494           __ cmpd(BOOL_RESULT, opr1->as_register_lo(), R0);
1495         }
1496       }
1497     } else if (opr2->is_register()) {
1498       if (unsigned_comp) {
1499         __ cmpld(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1500       } else {
1501         __ cmpd(BOOL_RESULT, opr1->as_register_lo(), opr2->as_register_lo());
1502       }
1503     } else {
1504       ShouldNotReachHere();
1505     }
1506   } else if (opr1->is_address()) {
1507     DEBUG_ONLY( Unimplemented(); ) // Seems to be unused at the moment.
1508     LIR_Address * addr = opr1->as_address_ptr();
1509     BasicType type = addr->type();
1510     assert (opr2->is_constant(), "Checking");
1511     if (type == T_OBJECT) { __ ld(R0, index_or_disp(addr), addr->base()->as_register()); }
1512     else                  { __ lwa(R0, index_or_disp(addr), addr->base()->as_register()); }
1513     __ cmpdi(BOOL_RESULT, R0, opr2->as_constant_ptr()->as_jint());
1514   } else {
1515     ShouldNotReachHere();
1516   }
1517 }
1518 
1519 
1520 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
1521   const Register Rdst = dst->as_register();
1522   Label done;
1523   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
1524     bool is_unordered_less = (code == lir_ucmp_fd2i);
1525     if (left->is_single_fpu()) {
1526       __ fcmpu(CCR0, left->as_float_reg(), right->as_float_reg());
1527     } else if (left->is_double_fpu()) {
1528       __ fcmpu(CCR0, left->as_double_reg(), right->as_double_reg());
1529     } else {
1530       ShouldNotReachHere();
1531     }
1532     __ li(Rdst, is_unordered_less ? -1 : 1);
1533     __ bso(CCR0, done);
1534   } else if (code == lir_cmp_l2i) {
1535     __ cmpd(CCR0, left->as_register_lo(), right->as_register_lo());
1536   } else {
1537     ShouldNotReachHere();
1538   }
1539   __ mfcr(R0); // set bit 32..33 as follows: <: 0b10, =: 0b00, >: 0b01
1540   __ srwi(Rdst, R0, 30);
1541   __ srawi(R0, R0, 31);
1542   __ orr(Rdst, R0, Rdst); // set result as follows: <: -1, =: 0, >: 1
1543   __ bind(done);
1544 }
1545 
1546 
1547 inline void load_to_reg(LIR_Assembler *lasm, LIR_Opr src, LIR_Opr dst) {
1548   if (src->is_constant()) {
1549     lasm->const2reg(src, dst, lir_patch_none, NULL);
1550   } else if (src->is_register()) {
1551     lasm->reg2reg(src, dst);
1552   } else if (src->is_stack()) {
1553     lasm->stack2reg(src, dst, dst->type());
1554   } else {
1555     ShouldNotReachHere();
1556   }
1557 }
1558 
1559 
1560 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1561   if (opr1->is_equal(opr2) || opr1->is_same_register(opr2)) {
1562     load_to_reg(this, opr1, result); // Condition doesn't matter.
1563     return;
1564   }
1565 
1566   bool positive = false;
1567   Assembler::Condition cond = Assembler::equal;
1568   switch (condition) {
1569     case lir_cond_equal:        positive = true ; cond = Assembler::equal  ; break;
1570     case lir_cond_notEqual:     positive = false; cond = Assembler::equal  ; break;
1571     case lir_cond_less:         positive = true ; cond = Assembler::less   ; break;
1572     case lir_cond_belowEqual:
1573     case lir_cond_lessEqual:    positive = false; cond = Assembler::greater; break;
1574     case lir_cond_greater:      positive = true ; cond = Assembler::greater; break;
1575     case lir_cond_aboveEqual:
1576     case lir_cond_greaterEqual: positive = false; cond = Assembler::less   ; break;
1577     default:                    ShouldNotReachHere();
1578   }
1579 
1580   // Try to use isel on >=Power7.
1581   if (VM_Version::has_isel() && result->is_cpu_register()) {
1582     bool o1_is_reg = opr1->is_cpu_register(), o2_is_reg = opr2->is_cpu_register();
1583     const Register result_reg = result->is_single_cpu() ? result->as_register() : result->as_register_lo();
1584 
1585     // We can use result_reg to load one operand if not already in register.
1586     Register first  = o1_is_reg ? (opr1->is_single_cpu() ? opr1->as_register() : opr1->as_register_lo()) : result_reg,
1587              second = o2_is_reg ? (opr2->is_single_cpu() ? opr2->as_register() : opr2->as_register_lo()) : result_reg;
1588 
1589     if (first != second) {
1590       if (!o1_is_reg) {
1591         load_to_reg(this, opr1, result);
1592       }
1593 
1594       if (!o2_is_reg) {
1595         load_to_reg(this, opr2, result);
1596       }
1597 
1598       __ isel(result_reg, BOOL_RESULT, cond, !positive, first, second);
1599       return;
1600     }
1601   } // isel
1602 
1603   load_to_reg(this, opr1, result);
1604 
1605   Label skip;
1606   int bo = positive ? Assembler::bcondCRbiIs1 : Assembler::bcondCRbiIs0;
1607   int bi = Assembler::bi0(BOOL_RESULT, cond);
1608   __ bc(bo, bi, skip);
1609 
1610   load_to_reg(this, opr2, result);
1611   __ bind(skip);
1612 }
1613 
1614 
1615 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest,
1616                              CodeEmitInfo* info, bool pop_fpu_stack) {
1617   assert(info == NULL, "unused on this code path");
1618   assert(left->is_register(), "wrong items state");
1619   assert(dest->is_register(), "wrong items state");
1620 
1621   if (right->is_register()) {
1622     if (dest->is_float_kind()) {
1623 
1624       FloatRegister lreg, rreg, res;
1625       if (right->is_single_fpu()) {
1626         lreg = left->as_float_reg();
1627         rreg = right->as_float_reg();
1628         res  = dest->as_float_reg();
1629         switch (code) {
1630           case lir_add: __ fadds(res, lreg, rreg); break;
1631           case lir_sub: __ fsubs(res, lreg, rreg); break;
1632           case lir_mul: // fall through
1633           case lir_mul_strictfp: __ fmuls(res, lreg, rreg); break;
1634           case lir_div: // fall through
1635           case lir_div_strictfp: __ fdivs(res, lreg, rreg); break;
1636           default: ShouldNotReachHere();
1637         }
1638       } else {
1639         lreg = left->as_double_reg();
1640         rreg = right->as_double_reg();
1641         res  = dest->as_double_reg();
1642         switch (code) {
1643           case lir_add: __ fadd(res, lreg, rreg); break;
1644           case lir_sub: __ fsub(res, lreg, rreg); break;
1645           case lir_mul: // fall through
1646           case lir_mul_strictfp: __ fmul(res, lreg, rreg); break;
1647           case lir_div: // fall through
1648           case lir_div_strictfp: __ fdiv(res, lreg, rreg); break;
1649           default: ShouldNotReachHere();
1650         }
1651       }
1652 
1653     } else if (dest->is_double_cpu()) {
1654 
1655       Register dst_lo = dest->as_register_lo();
1656       Register op1_lo = left->as_pointer_register();
1657       Register op2_lo = right->as_pointer_register();
1658 
1659       switch (code) {
1660         case lir_add: __ add(dst_lo, op1_lo, op2_lo); break;
1661         case lir_sub: __ sub(dst_lo, op1_lo, op2_lo); break;
1662         case lir_mul: __ mulld(dst_lo, op1_lo, op2_lo); break;
1663         default: ShouldNotReachHere();
1664       }
1665     } else {
1666       assert (right->is_single_cpu(), "Just Checking");
1667 
1668       Register lreg = left->as_register();
1669       Register res  = dest->as_register();
1670       Register rreg = right->as_register();
1671       switch (code) {
1672         case lir_add:  __ add  (res, lreg, rreg); break;
1673         case lir_sub:  __ sub  (res, lreg, rreg); break;
1674         case lir_mul:  __ mullw(res, lreg, rreg); break;
1675         default: ShouldNotReachHere();
1676       }
1677     }
1678   } else {
1679     assert (right->is_constant(), "must be constant");
1680 
1681     if (dest->is_single_cpu()) {
1682       Register lreg = left->as_register();
1683       Register res  = dest->as_register();
1684       int    simm16 = right->as_constant_ptr()->as_jint();
1685 
1686       switch (code) {
1687         case lir_sub:  assert(Assembler::is_simm16(-simm16), "cannot encode"); // see do_ArithmeticOp_Int
1688                        simm16 = -simm16;
1689         case lir_add:  if (res == lreg && simm16 == 0) break;
1690                        __ addi(res, lreg, simm16); break;
1691         case lir_mul:  if (res == lreg && simm16 == 1) break;
1692                        __ mulli(res, lreg, simm16); break;
1693         default: ShouldNotReachHere();
1694       }
1695     } else {
1696       Register lreg = left->as_pointer_register();
1697       Register res  = dest->as_register_lo();
1698       long con = right->as_constant_ptr()->as_jlong();
1699       assert(Assembler::is_simm16(con), "must be simm16");
1700 
1701       switch (code) {
1702         case lir_sub:  assert(Assembler::is_simm16(-con), "cannot encode");  // see do_ArithmeticOp_Long
1703                        con = -con;
1704         case lir_add:  if (res == lreg && con == 0) break;
1705                        __ addi(res, lreg, (int)con); break;
1706         case lir_mul:  if (res == lreg && con == 1) break;
1707                        __ mulli(res, lreg, (int)con); break;
1708         default: ShouldNotReachHere();
1709       }
1710     }
1711   }
1712 }
1713 
1714 
1715 void LIR_Assembler::fpop() {
1716   Unimplemented();
1717   // do nothing
1718 }
1719 
1720 
1721 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) {
1722   switch (code) {
1723     case lir_sqrt: {
1724       __ fsqrt(dest->as_double_reg(), value->as_double_reg());
1725       break;
1726     }
1727     case lir_abs: {
1728       __ fabs(dest->as_double_reg(), value->as_double_reg());
1729       break;
1730     }
1731     default: {
1732       ShouldNotReachHere();
1733       break;
1734     }
1735   }
1736 }
1737 
1738 
1739 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) {
1740   if (right->is_constant()) { // see do_LogicOp
1741     long uimm;
1742     Register d, l;
1743     if (dest->is_single_cpu()) {
1744       uimm = right->as_constant_ptr()->as_jint();
1745       d = dest->as_register();
1746       l = left->as_register();
1747     } else {
1748       uimm = right->as_constant_ptr()->as_jlong();
1749       d = dest->as_register_lo();
1750       l = left->as_register_lo();
1751     }
1752     long uimms  = (unsigned long)uimm >> 16,
1753          uimmss = (unsigned long)uimm >> 32;
1754 
1755     switch (code) {
1756       case lir_logic_and:
1757         if (uimmss != 0 || (uimms != 0 && (uimm & 0xFFFF) != 0) || is_power_of_2_long(uimm)) {
1758           __ andi(d, l, uimm); // special cases
1759         } else if (uimms != 0) { __ andis_(d, l, uimms); }
1760         else { __ andi_(d, l, uimm); }
1761         break;
1762 
1763       case lir_logic_or:
1764         if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ oris(d, l, uimms); }
1765         else { __ ori(d, l, uimm); }
1766         break;
1767 
1768       case lir_logic_xor:
1769         if (uimm == -1) { __ nand(d, l, l); } // special case
1770         else if (uimms != 0) { assert((uimm & 0xFFFF) == 0, "sanity"); __ xoris(d, l, uimms); }
1771         else { __ xori(d, l, uimm); }
1772         break;
1773 
1774       default: ShouldNotReachHere();
1775     }
1776   } else {
1777     assert(right->is_register(), "right should be in register");
1778 
1779     if (dest->is_single_cpu()) {
1780       switch (code) {
1781         case lir_logic_and: __ andr(dest->as_register(), left->as_register(), right->as_register()); break;
1782         case lir_logic_or:  __ orr (dest->as_register(), left->as_register(), right->as_register()); break;
1783         case lir_logic_xor: __ xorr(dest->as_register(), left->as_register(), right->as_register()); break;
1784         default: ShouldNotReachHere();
1785       }
1786     } else {
1787       Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() :
1788                                                                         left->as_register_lo();
1789       Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() :
1790                                                                           right->as_register_lo();
1791 
1792       switch (code) {
1793         case lir_logic_and: __ andr(dest->as_register_lo(), l, r); break;
1794         case lir_logic_or:  __ orr (dest->as_register_lo(), l, r); break;
1795         case lir_logic_xor: __ xorr(dest->as_register_lo(), l, r); break;
1796         default: ShouldNotReachHere();
1797       }
1798     }
1799   }
1800 }
1801 
1802 
1803 int LIR_Assembler::shift_amount(BasicType t) {
1804   int elem_size = type2aelembytes(t);
1805   switch (elem_size) {
1806     case 1 : return 0;
1807     case 2 : return 1;
1808     case 4 : return 2;
1809     case 8 : return 3;
1810   }
1811   ShouldNotReachHere();
1812   return -1;
1813 }
1814 
1815 
1816 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
1817   info->add_register_oop(exceptionOop);
1818 
1819   // Reuse the debug info from the safepoint poll for the throw op itself.
1820   address pc_for_athrow = __ pc();
1821   int pc_for_athrow_offset = __ offset();
1822   //RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow);
1823   //__ relocate(rspec);
1824   //__ load_const(exceptionPC->as_register(), pc_for_athrow, R0);
1825   __ calculate_address_from_global_toc(exceptionPC->as_register(), pc_for_athrow, true, true, /*add_relocation*/ true);
1826   add_call_info(pc_for_athrow_offset, info); // for exception handler
1827 
1828   address stub = Runtime1::entry_for(compilation()->has_fpu_code() ? Runtime1::handle_exception_id
1829                                                                    : Runtime1::handle_exception_nofpu_id);
1830   //__ load_const_optimized(R0, stub);
1831   __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(stub));
1832   __ mtctr(R0);
1833   __ bctr();
1834 }
1835 
1836 
1837 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
1838   // Note: Not used with EnableDebuggingOnDemand.
1839   assert(exceptionOop->as_register() == R3, "should match");
1840   __ b(_unwind_handler_entry);
1841 }
1842 
1843 
1844 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
1845   Register src = op->src()->as_register();
1846   Register dst = op->dst()->as_register();
1847   Register src_pos = op->src_pos()->as_register();
1848   Register dst_pos = op->dst_pos()->as_register();
1849   Register length  = op->length()->as_register();
1850   Register tmp = op->tmp()->as_register();
1851   Register tmp2 = R0;
1852 
1853   int flags = op->flags();
1854   ciArrayKlass* default_type = op->expected_type();
1855   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
1856   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
1857 
1858   // Set up the arraycopy stub information.
1859   ArrayCopyStub* stub = op->stub();
1860   const int frame_resize = frame::abi_reg_args_size - sizeof(frame::jit_abi); // C calls need larger frame.
1861 
1862   // Always do stub if no type information is available. It's ok if
1863   // the known type isn't loaded since the code sanity checks
1864   // in debug mode and the type isn't required when we know the exact type
1865   // also check that the type is an array type.
1866   if (op->expected_type() == NULL) {
1867     assert(src->is_nonvolatile() && src_pos->is_nonvolatile() && dst->is_nonvolatile() && dst_pos->is_nonvolatile() &&
1868            length->is_nonvolatile(), "must preserve");
1869     // 3 parms are int. Convert to long.
1870     __ mr(R3_ARG1, src);
1871     __ extsw(R4_ARG2, src_pos);
1872     __ mr(R5_ARG3, dst);
1873     __ extsw(R6_ARG4, dst_pos);
1874     __ extsw(R7_ARG5, length);
1875     address copyfunc_addr = StubRoutines::generic_arraycopy();
1876 
1877     if (copyfunc_addr == NULL) { // Use C version if stub was not generated.
1878       address entry = CAST_FROM_FN_PTR(address, Runtime1::arraycopy);
1879       __ call_c_with_frame_resize(entry, frame_resize);
1880     } else {
1881 #ifndef PRODUCT
1882       if (PrintC1Statistics) {
1883         address counter = (address)&Runtime1::_generic_arraycopystub_cnt;
1884         int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
1885         __ lwz(R11_scratch1, simm16_offs, tmp);
1886         __ addi(R11_scratch1, R11_scratch1, 1);
1887         __ stw(R11_scratch1, simm16_offs, tmp);
1888       }
1889 #endif
1890       __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
1891 
1892       __ nand(tmp, R3_RET, R3_RET);
1893       __ subf(length, tmp, length);
1894       __ add(src_pos, tmp, src_pos);
1895       __ add(dst_pos, tmp, dst_pos);
1896     }
1897 
1898     __ cmpwi(CCR0, R3_RET, 0);
1899     __ bc_far_optimized(Assembler::bcondCRbiIs1, __ bi0(CCR0, Assembler::less), *stub->entry());
1900     __ bind(*stub->continuation());
1901     return;
1902   }
1903 
1904   assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point");
1905   Label cont, slow, copyfunc;
1906 
1907   bool simple_check_flag_set = flags & (LIR_OpArrayCopy::src_null_check |
1908                                         LIR_OpArrayCopy::dst_null_check |
1909                                         LIR_OpArrayCopy::src_pos_positive_check |
1910                                         LIR_OpArrayCopy::dst_pos_positive_check |
1911                                         LIR_OpArrayCopy::length_positive_check);
1912 
1913   // Use only one conditional branch for simple checks.
1914   if (simple_check_flag_set) {
1915     ConditionRegister combined_check = CCR1, tmp_check = CCR1;
1916 
1917     // Make sure src and dst are non-null.
1918     if (flags & LIR_OpArrayCopy::src_null_check) {
1919       __ cmpdi(combined_check, src, 0);
1920       tmp_check = CCR0;
1921     }
1922 
1923     if (flags & LIR_OpArrayCopy::dst_null_check) {
1924       __ cmpdi(tmp_check, dst, 0);
1925       if (tmp_check != combined_check) {
1926         __ cror(combined_check, Assembler::equal, tmp_check, Assembler::equal);
1927       }
1928       tmp_check = CCR0;
1929     }
1930 
1931     // Clear combined_check.eq if not already used.
1932     if (tmp_check == combined_check) {
1933       __ crandc(combined_check, Assembler::equal, combined_check, Assembler::equal);
1934       tmp_check = CCR0;
1935     }
1936 
1937     if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
1938       // Test src_pos register.
1939       __ cmpwi(tmp_check, src_pos, 0);
1940       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1941     }
1942 
1943     if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
1944       // Test dst_pos register.
1945       __ cmpwi(tmp_check, dst_pos, 0);
1946       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1947     }
1948 
1949     if (flags & LIR_OpArrayCopy::length_positive_check) {
1950       // Make sure length isn't negative.
1951       __ cmpwi(tmp_check, length, 0);
1952       __ cror(combined_check, Assembler::equal, tmp_check, Assembler::less);
1953     }
1954 
1955     __ beq(combined_check, slow);
1956   }
1957 
1958   // If the compiler was not able to prove that exact type of the source or the destination
1959   // of the arraycopy is an array type, check at runtime if the source or the destination is
1960   // an instance type.
1961   if (flags & LIR_OpArrayCopy::type_check) {
1962     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
1963       __ load_klass(tmp, dst);
1964       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1965       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1966       __ bge(CCR0, slow);
1967     }
1968 
1969     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
1970       __ load_klass(tmp, src);
1971       __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
1972       __ cmpwi(CCR0, tmp2, Klass::_lh_neutral_value);
1973       __ bge(CCR0, slow);
1974     }
1975   }
1976 
1977   // Higher 32bits must be null.
1978   __ extsw(length, length);
1979 
1980   __ extsw(src_pos, src_pos);
1981   if (flags & LIR_OpArrayCopy::src_range_check) {
1982     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), src);
1983     __ add(tmp, length, src_pos);
1984     __ cmpld(CCR0, tmp2, tmp);
1985     __ ble(CCR0, slow);
1986   }
1987 
1988   __ extsw(dst_pos, dst_pos);
1989   if (flags & LIR_OpArrayCopy::dst_range_check) {
1990     __ lwz(tmp2, arrayOopDesc::length_offset_in_bytes(), dst);
1991     __ add(tmp, length, dst_pos);
1992     __ cmpld(CCR0, tmp2, tmp);
1993     __ ble(CCR0, slow);
1994   }
1995 
1996   int shift = shift_amount(basic_type);
1997 
1998   if (!(flags & LIR_OpArrayCopy::type_check)) {
1999     __ b(cont);
2000   } else {
2001     // We don't know the array types are compatible.
2002     if (basic_type != T_OBJECT) {
2003       // Simple test for basic type arrays.
2004       if (UseCompressedClassPointers) {
2005         // We don't need decode because we just need to compare.
2006         __ lwz(tmp, oopDesc::klass_offset_in_bytes(), src);
2007         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2008         __ cmpw(CCR0, tmp, tmp2);
2009       } else {
2010         __ ld(tmp, oopDesc::klass_offset_in_bytes(), src);
2011         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2012         __ cmpd(CCR0, tmp, tmp2);
2013       }
2014       __ beq(CCR0, cont);
2015     } else {
2016       // For object arrays, if src is a sub class of dst then we can
2017       // safely do the copy.
2018       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2019 
2020       const Register sub_klass = R5, super_klass = R4; // like CheckCast/InstanceOf
2021       assert_different_registers(tmp, tmp2, sub_klass, super_klass);
2022 
2023       __ load_klass(sub_klass, src);
2024       __ load_klass(super_klass, dst);
2025 
2026       __ check_klass_subtype_fast_path(sub_klass, super_klass, tmp, tmp2,
2027                                        &cont, copyfunc_addr != NULL ? &copyfunc : &slow, NULL);
2028 
2029       address slow_stc = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2030       //__ load_const_optimized(tmp, slow_stc, tmp2);
2031       __ calculate_address_from_global_toc(tmp, slow_stc, true, true, false);
2032       __ mtctr(tmp);
2033       __ bctrl(); // sets CR0
2034       __ beq(CCR0, cont);
2035 
2036       if (copyfunc_addr != NULL) { // Use stub if available.
2037         __ bind(copyfunc);
2038         // Src is not a sub class of dst so we have to do a
2039         // per-element check.
2040         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2041         if ((flags & mask) != mask) {
2042           assert(flags & mask, "one of the two should be known to be an object array");
2043 
2044           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2045             __ load_klass(tmp, src);
2046           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2047             __ load_klass(tmp, dst);
2048           }
2049 
2050           __ lwz(tmp2, in_bytes(Klass::layout_helper_offset()), tmp);
2051 
2052           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2053           __ load_const_optimized(tmp, objArray_lh);
2054           __ cmpw(CCR0, tmp, tmp2);
2055           __ bne(CCR0, slow);
2056         }
2057 
2058         Register src_ptr = R3_ARG1;
2059         Register dst_ptr = R4_ARG2;
2060         Register len     = R5_ARG3;
2061         Register chk_off = R6_ARG4;
2062         Register super_k = R7_ARG5;
2063 
2064         __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2065         __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2066         if (shift == 0) {
2067           __ add(src_ptr, src_pos, src_ptr);
2068           __ add(dst_ptr, dst_pos, dst_ptr);
2069         } else {
2070           __ sldi(tmp, src_pos, shift);
2071           __ sldi(tmp2, dst_pos, shift);
2072           __ add(src_ptr, tmp, src_ptr);
2073           __ add(dst_ptr, tmp2, dst_ptr);
2074         }
2075 
2076         __ load_klass(tmp, dst);
2077         __ mr(len, length);
2078 
2079         int ek_offset = in_bytes(ObjArrayKlass::element_klass_offset());
2080         __ ld(super_k, ek_offset, tmp);
2081 
2082         int sco_offset = in_bytes(Klass::super_check_offset_offset());
2083         __ lwz(chk_off, sco_offset, super_k);
2084 
2085         __ call_c_with_frame_resize(copyfunc_addr, /*stub does not need resized frame*/ 0);
2086 
2087 #ifndef PRODUCT
2088         if (PrintC1Statistics) {
2089           Label failed;
2090           __ cmpwi(CCR0, R3_RET, 0);
2091           __ bne(CCR0, failed);
2092           address counter = (address)&Runtime1::_arraycopy_checkcast_cnt;
2093           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2094           __ lwz(R11_scratch1, simm16_offs, tmp);
2095           __ addi(R11_scratch1, R11_scratch1, 1);
2096           __ stw(R11_scratch1, simm16_offs, tmp);
2097           __ bind(failed);
2098         }
2099 #endif
2100 
2101         __ nand(tmp, R3_RET, R3_RET);
2102         __ cmpwi(CCR0, R3_RET, 0);
2103         __ beq(CCR0, *stub->continuation());
2104 
2105 #ifndef PRODUCT
2106         if (PrintC1Statistics) {
2107           address counter = (address)&Runtime1::_arraycopy_checkcast_attempt_cnt;
2108           int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2109           __ lwz(R11_scratch1, simm16_offs, tmp);
2110           __ addi(R11_scratch1, R11_scratch1, 1);
2111           __ stw(R11_scratch1, simm16_offs, tmp);
2112         }
2113 #endif
2114 
2115         __ subf(length, tmp, length);
2116         __ add(src_pos, tmp, src_pos);
2117         __ add(dst_pos, tmp, dst_pos);
2118       }
2119     }
2120   }
2121   __ bind(slow);
2122   __ b(*stub->entry());
2123   __ bind(cont);
2124 
2125 #ifdef ASSERT
2126   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2127     // Sanity check the known type with the incoming class. For the
2128     // primitive case the types must match exactly with src.klass and
2129     // dst.klass each exactly matching the default type. For the
2130     // object array case, if no type check is needed then either the
2131     // dst type is exactly the expected type and the src type is a
2132     // subtype which we can't check or src is the same array as dst
2133     // but not necessarily exactly of type default_type.
2134     Label known_ok, halt;
2135     metadata2reg(op->expected_type()->constant_encoding(), tmp);
2136     if (UseCompressedClassPointers) {
2137       // Tmp holds the default type. It currently comes uncompressed after the
2138       // load of a constant, so encode it.
2139       __ encode_klass_not_null(tmp);
2140       // Load the raw value of the dst klass, since we will be comparing
2141       // uncompressed values directly.
2142       __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2143       __ cmpw(CCR0, tmp, tmp2);
2144       if (basic_type != T_OBJECT) {
2145         __ bne(CCR0, halt);
2146         // Load the raw value of the src klass.
2147         __ lwz(tmp2, oopDesc::klass_offset_in_bytes(), src);
2148         __ cmpw(CCR0, tmp, tmp2);
2149         __ beq(CCR0, known_ok);
2150       } else {
2151         __ beq(CCR0, known_ok);
2152         __ cmpw(CCR0, src, dst);
2153         __ beq(CCR0, known_ok);
2154       }
2155     } else {
2156       __ ld(tmp2, oopDesc::klass_offset_in_bytes(), dst);
2157       __ cmpd(CCR0, tmp, tmp2);
2158       if (basic_type != T_OBJECT) {
2159         __ bne(CCR0, halt);
2160         // Load the raw value of the src klass.
2161         __ ld(tmp2, oopDesc::klass_offset_in_bytes(), src);
2162         __ cmpd(CCR0, tmp, tmp2);
2163         __ beq(CCR0, known_ok);
2164       } else {
2165         __ beq(CCR0, known_ok);
2166         __ cmpd(CCR0, src, dst);
2167         __ beq(CCR0, known_ok);
2168       }
2169     }
2170     __ bind(halt);
2171     __ stop("incorrect type information in arraycopy");
2172     __ bind(known_ok);
2173   }
2174 #endif
2175 
2176 #ifndef PRODUCT
2177   if (PrintC1Statistics) {
2178     address counter = Runtime1::arraycopy_count_address(basic_type);
2179     int simm16_offs = __ load_const_optimized(tmp, counter, tmp2, true);
2180     __ lwz(R11_scratch1, simm16_offs, tmp);
2181     __ addi(R11_scratch1, R11_scratch1, 1);
2182     __ stw(R11_scratch1, simm16_offs, tmp);
2183   }
2184 #endif
2185 
2186   Register src_ptr = R3_ARG1;
2187   Register dst_ptr = R4_ARG2;
2188   Register len     = R5_ARG3;
2189 
2190   __ addi(src_ptr, src, arrayOopDesc::base_offset_in_bytes(basic_type));
2191   __ addi(dst_ptr, dst, arrayOopDesc::base_offset_in_bytes(basic_type));
2192   if (shift == 0) {
2193     __ add(src_ptr, src_pos, src_ptr);
2194     __ add(dst_ptr, dst_pos, dst_ptr);
2195   } else {
2196     __ sldi(tmp, src_pos, shift);
2197     __ sldi(tmp2, dst_pos, shift);
2198     __ add(src_ptr, tmp, src_ptr);
2199     __ add(dst_ptr, tmp2, dst_ptr);
2200   }
2201 
2202   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2203   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2204   const char *name;
2205   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2206 
2207   // Arraycopy stubs takes a length in number of elements, so don't scale it.
2208   __ mr(len, length);
2209   __ call_c_with_frame_resize(entry, /*stub does not need resized frame*/ 0);
2210 
2211   __ bind(*stub->continuation());
2212 }
2213 
2214 
2215 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2216   if (dest->is_single_cpu()) {
2217     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-5);
2218 #ifdef _LP64
2219     if (left->type() == T_OBJECT) {
2220       switch (code) {
2221         case lir_shl:  __ sld(dest->as_register(), left->as_register(), tmp->as_register()); break;
2222         case lir_shr:  __ srad(dest->as_register(), left->as_register(), tmp->as_register()); break;
2223         case lir_ushr: __ srd(dest->as_register(), left->as_register(), tmp->as_register()); break;
2224         default: ShouldNotReachHere();
2225       }
2226     } else
2227 #endif
2228       switch (code) {
2229         case lir_shl:  __ slw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2230         case lir_shr:  __ sraw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2231         case lir_ushr: __ srw(dest->as_register(), left->as_register(), tmp->as_register()); break;
2232         default: ShouldNotReachHere();
2233       }
2234   } else {
2235     __ rldicl(tmp->as_register(), count->as_register(), 0, 64-6);
2236     switch (code) {
2237       case lir_shl:  __ sld(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2238       case lir_shr:  __ srad(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2239       case lir_ushr: __ srd(dest->as_register_lo(), left->as_register_lo(), tmp->as_register()); break;
2240       default: ShouldNotReachHere();
2241     }
2242   }
2243 }
2244 
2245 
2246 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2247 #ifdef _LP64
2248   if (left->type() == T_OBJECT) {
2249     count = count & 63;  // Shouldn't shift by more than sizeof(intptr_t).
2250     if (count == 0) { __ mr_if_needed(dest->as_register_lo(), left->as_register()); }
2251     else {
2252       switch (code) {
2253         case lir_shl:  __ sldi(dest->as_register_lo(), left->as_register(), count); break;
2254         case lir_shr:  __ sradi(dest->as_register_lo(), left->as_register(), count); break;
2255         case lir_ushr: __ srdi(dest->as_register_lo(), left->as_register(), count); break;
2256         default: ShouldNotReachHere();
2257       }
2258     }
2259     return;
2260   }
2261 #endif
2262 
2263   if (dest->is_single_cpu()) {
2264     count = count & 0x1F; // Java spec
2265     if (count == 0) { __ mr_if_needed(dest->as_register(), left->as_register()); }
2266     else {
2267       switch (code) {
2268         case lir_shl: __ slwi(dest->as_register(), left->as_register(), count); break;
2269         case lir_shr:  __ srawi(dest->as_register(), left->as_register(), count); break;
2270         case lir_ushr: __ srwi(dest->as_register(), left->as_register(), count); break;
2271         default: ShouldNotReachHere();
2272       }
2273     }
2274   } else if (dest->is_double_cpu()) {
2275     count = count & 63; // Java spec
2276     if (count == 0) { __ mr_if_needed(dest->as_pointer_register(), left->as_pointer_register()); }
2277     else {
2278       switch (code) {
2279         case lir_shl:  __ sldi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2280         case lir_shr:  __ sradi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2281         case lir_ushr: __ srdi(dest->as_pointer_register(), left->as_pointer_register(), count); break;
2282         default: ShouldNotReachHere();
2283       }
2284     }
2285   } else {
2286     ShouldNotReachHere();
2287   }
2288 }
2289 
2290 
2291 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
2292   if (op->init_check()) {
2293     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2294       explicit_null_check(op->klass()->as_register(), op->stub()->info());
2295     } else {
2296       add_debug_info_for_null_check_here(op->stub()->info());
2297     }
2298     __ lbz(op->tmp1()->as_register(),
2299            in_bytes(InstanceKlass::init_state_offset()), op->klass()->as_register());
2300     __ cmpwi(CCR0, op->tmp1()->as_register(), InstanceKlass::fully_initialized);
2301     __ bc_far_optimized(Assembler::bcondCRbiIs0, __ bi0(CCR0, Assembler::equal), *op->stub()->entry());
2302   }
2303   __ allocate_object(op->obj()->as_register(),
2304                      op->tmp1()->as_register(),
2305                      op->tmp2()->as_register(),
2306                      op->tmp3()->as_register(),
2307                      op->header_size(),
2308                      op->object_size(),
2309                      op->klass()->as_register(),
2310                      *op->stub()->entry());
2311 
2312   __ bind(*op->stub()->continuation());
2313   __ verify_oop(op->obj()->as_register());
2314 }
2315 
2316 
2317 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
2318   LP64_ONLY( __ extsw(op->len()->as_register(), op->len()->as_register()); )
2319   if (UseSlowPath ||
2320       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
2321       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
2322     __ b(*op->stub()->entry());
2323   } else {
2324     __ allocate_array(op->obj()->as_register(),
2325                       op->len()->as_register(),
2326                       op->tmp1()->as_register(),
2327                       op->tmp2()->as_register(),
2328                       op->tmp3()->as_register(),
2329                       arrayOopDesc::header_size(op->type()),
2330                       type2aelembytes(op->type()),
2331                       op->klass()->as_register(),
2332                       *op->stub()->entry());
2333   }
2334   __ bind(*op->stub()->continuation());
2335 }
2336 
2337 
2338 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias,
2339                                         ciMethodData *md, ciProfileData *data,
2340                                         Register recv, Register tmp1, Label* update_done) {
2341   uint i;
2342   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2343     Label next_test;
2344     // See if the receiver is receiver[n].
2345     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2346     __ verify_klass_ptr(tmp1);
2347     __ cmpd(CCR0, recv, tmp1);
2348     __ bne(CCR0, next_test);
2349 
2350     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2351     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2352     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2353     __ b(*update_done);
2354 
2355     __ bind(next_test);
2356   }
2357 
2358   // Didn't find receiver; find next empty slot and fill it in.
2359   for (i = 0; i < VirtualCallData::row_limit(); i++) {
2360     Label next_test;
2361     __ ld(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2362     __ cmpdi(CCR0, tmp1, 0);
2363     __ bne(CCR0, next_test);
2364     __ li(tmp1, DataLayout::counter_increment);
2365     __ std(recv, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - mdo_offset_bias, mdo);
2366     __ std(tmp1, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2367     __ b(*update_done);
2368 
2369     __ bind(next_test);
2370   }
2371 }
2372 
2373 
2374 void LIR_Assembler::setup_md_access(ciMethod* method, int bci,
2375                                     ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) {
2376   md = method->method_data_or_null();
2377   assert(md != NULL, "Sanity");
2378   data = md->bci_to_data(bci);
2379   assert(data != NULL,       "need data for checkcast");
2380   assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
2381   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) {
2382     // The offset is large so bias the mdo by the base of the slot so
2383     // that the ld can use simm16s to reference the slots of the data.
2384     mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset());
2385   }
2386 }
2387 
2388 
2389 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
2390   Register obj = op->object()->as_register();
2391   Register k_RInfo = op->tmp1()->as_register();
2392   Register klass_RInfo = op->tmp2()->as_register();
2393   Register Rtmp1 = op->tmp3()->as_register();
2394   Register dst = op->result_opr()->as_register();
2395   ciKlass* k = op->klass();
2396   bool should_profile = op->should_profile();
2397   bool move_obj_to_dst = (op->code() == lir_checkcast);
2398   // Attention: do_temp(opTypeCheck->_object) is not used, i.e. obj may be same as one of the temps.
2399   bool reg_conflict = (obj == k_RInfo || obj == klass_RInfo || obj == Rtmp1);
2400   bool restore_obj = move_obj_to_dst && reg_conflict;
2401 
2402   __ cmpdi(CCR0, obj, 0);
2403   if (move_obj_to_dst || reg_conflict) {
2404     __ mr_if_needed(dst, obj);
2405     if (reg_conflict) { obj = dst; }
2406   }
2407 
2408   ciMethodData* md;
2409   ciProfileData* data;
2410   int mdo_offset_bias = 0;
2411   if (should_profile) {
2412     ciMethod* method = op->profiled_method();
2413     assert(method != NULL, "Should have method");
2414     setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2415 
2416     Register mdo      = k_RInfo;
2417     Register data_val = Rtmp1;
2418     Label not_null;
2419     __ bne(CCR0, not_null);
2420     metadata2reg(md->constant_encoding(), mdo);
2421     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2422     __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2423     __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2424     __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2425     __ b(*obj_is_null);
2426     __ bind(not_null);
2427   } else {
2428     __ beq(CCR0, *obj_is_null);
2429   }
2430 
2431   // get object class
2432   __ load_klass(klass_RInfo, obj);
2433 
2434   if (k->is_loaded()) {
2435     metadata2reg(k->constant_encoding(), k_RInfo);
2436   } else {
2437     klass2reg_with_patching(k_RInfo, op->info_for_patch());
2438   }
2439 
2440   Label profile_cast_failure, failure_restore_obj, profile_cast_success;
2441   Label *failure_target = should_profile ? &profile_cast_failure : failure;
2442   Label *success_target = should_profile ? &profile_cast_success : success;
2443 
2444   if (op->fast_check()) {
2445     assert_different_registers(klass_RInfo, k_RInfo);
2446     __ cmpd(CCR0, k_RInfo, klass_RInfo);
2447     if (should_profile) {
2448       __ bne(CCR0, *failure_target);
2449       // Fall through to success case.
2450     } else {
2451       __ beq(CCR0, *success);
2452       // Fall through to failure case.
2453     }
2454   } else {
2455     bool need_slow_path = true;
2456     if (k->is_loaded()) {
2457       if ((int) k->super_check_offset() != in_bytes(Klass::secondary_super_cache_offset())) {
2458         need_slow_path = false;
2459       }
2460       // Perform the fast part of the checking logic.
2461       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, (need_slow_path ? success_target : NULL),
2462                                        failure_target, NULL, RegisterOrConstant(k->super_check_offset()));
2463     } else {
2464       // Perform the fast part of the checking logic.
2465       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, failure_target);
2466     }
2467     if (!need_slow_path) {
2468       if (!should_profile) { __ b(*success); }
2469     } else {
2470       // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2471       address entry = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2472       //__ load_const_optimized(Rtmp1, entry, R0);
2473       __ calculate_address_from_global_toc(Rtmp1, entry, true, true, false);
2474       __ mtctr(Rtmp1);
2475       __ bctrl(); // sets CR0
2476       if (should_profile) {
2477         __ bne(CCR0, *failure_target);
2478         // Fall through to success case.
2479       } else {
2480         __ beq(CCR0, *success);
2481         // Fall through to failure case.
2482       }
2483     }
2484   }
2485 
2486   if (should_profile) {
2487     Register mdo = k_RInfo, recv = klass_RInfo;
2488     assert_different_registers(mdo, recv, Rtmp1);
2489     __ bind(profile_cast_success);
2490     metadata2reg(md->constant_encoding(), mdo);
2491     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2492     type_profile_helper(mdo, mdo_offset_bias, md, data, recv, Rtmp1, success);
2493     __ b(*success);
2494 
2495     // Cast failure case.
2496     __ bind(profile_cast_failure);
2497     metadata2reg(md->constant_encoding(), mdo);
2498     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2499     __ ld(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2500     __ addi(Rtmp1, Rtmp1, -DataLayout::counter_increment);
2501     __ std(Rtmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2502   }
2503 
2504   __ bind(*failure);
2505 
2506   if (restore_obj) {
2507     __ mr(op->object()->as_register(), dst);
2508     // Fall through to failure case.
2509   }
2510 }
2511 
2512 
2513 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
2514   LIR_Code code = op->code();
2515   if (code == lir_store_check) {
2516     Register value = op->object()->as_register();
2517     Register array = op->array()->as_register();
2518     Register k_RInfo = op->tmp1()->as_register();
2519     Register klass_RInfo = op->tmp2()->as_register();
2520     Register Rtmp1 = op->tmp3()->as_register();
2521     bool should_profile = op->should_profile();
2522 
2523     __ verify_oop(value);
2524     CodeStub* stub = op->stub();
2525     // Check if it needs to be profiled.
2526     ciMethodData* md;
2527     ciProfileData* data;
2528     int mdo_offset_bias = 0;
2529     if (should_profile) {
2530       ciMethod* method = op->profiled_method();
2531       assert(method != NULL, "Should have method");
2532       setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias);
2533     }
2534     Label profile_cast_success, failure, done;
2535     Label *success_target = should_profile ? &profile_cast_success : &done;
2536 
2537     __ cmpdi(CCR0, value, 0);
2538     if (should_profile) {
2539       Label not_null;
2540       __ bne(CCR0, not_null);
2541       Register mdo      = k_RInfo;
2542       Register data_val = Rtmp1;
2543       metadata2reg(md->constant_encoding(), mdo);
2544       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2545       __ lbz(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2546       __ ori(data_val, data_val, BitData::null_seen_byte_constant());
2547       __ stb(data_val, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias, mdo);
2548       __ b(done);
2549       __ bind(not_null);
2550     } else {
2551       __ beq(CCR0, done);
2552     }
2553     if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2554       explicit_null_check(array, op->info_for_exception());
2555     } else {
2556       add_debug_info_for_null_check_here(op->info_for_exception());
2557     }
2558     __ load_klass(k_RInfo, array);
2559     __ load_klass(klass_RInfo, value);
2560 
2561     // Get instance klass.
2562     __ ld(k_RInfo, in_bytes(ObjArrayKlass::element_klass_offset()), k_RInfo);
2563     // Perform the fast part of the checking logic.
2564     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, R0, success_target, &failure, NULL);
2565 
2566     // Call out-of-line instance of __ check_klass_subtype_slow_path(...):
2567     const address slow_path = Runtime1::entry_for(Runtime1::slow_subtype_check_id);
2568     //__ load_const_optimized(R0, slow_path);
2569     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(slow_path));
2570     __ mtctr(R0);
2571     __ bctrl(); // sets CR0
2572     if (!should_profile) {
2573       __ beq(CCR0, done);
2574       __ bind(failure);
2575     } else {
2576       __ bne(CCR0, failure);
2577       // Fall through to the success case.
2578 
2579       Register mdo  = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1;
2580       assert_different_registers(value, mdo, recv, tmp1);
2581       __ bind(profile_cast_success);
2582       metadata2reg(md->constant_encoding(), mdo);
2583       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2584       __ load_klass(recv, value);
2585       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done);
2586       __ b(done);
2587 
2588       // Cast failure case.
2589       __ bind(failure);
2590       metadata2reg(md->constant_encoding(), mdo);
2591       __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2592       Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias);
2593       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2594       __ addi(tmp1, tmp1, -DataLayout::counter_increment);
2595       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2596     }
2597     __ b(*stub->entry());
2598     __ bind(done);
2599 
2600   } else if (code == lir_checkcast) {
2601     Label success, failure;
2602     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &success); // Moves obj to dst.
2603     __ b(*op->stub()->entry());
2604     __ align(32, 12);
2605     __ bind(success);
2606   } else if (code == lir_instanceof) {
2607     Register dst = op->result_opr()->as_register();
2608     Label success, failure, done;
2609     emit_typecheck_helper(op, &success, /*fallthru*/&failure, &failure);
2610     __ li(dst, 0);
2611     __ b(done);
2612     __ align(32, 12);
2613     __ bind(success);
2614     __ li(dst, 1);
2615     __ bind(done);
2616   } else {
2617     ShouldNotReachHere();
2618   }
2619 }
2620 
2621 
2622 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
2623   Register addr = op->addr()->as_pointer_register();
2624   Register cmp_value = noreg, new_value = noreg;
2625   bool is_64bit = false;
2626 
2627   if (op->code() == lir_cas_long) {
2628     cmp_value = op->cmp_value()->as_register_lo();
2629     new_value = op->new_value()->as_register_lo();
2630     is_64bit = true;
2631   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) {
2632     cmp_value = op->cmp_value()->as_register();
2633     new_value = op->new_value()->as_register();
2634     if (op->code() == lir_cas_obj) {
2635       if (UseCompressedOops) {
2636         Register t1 = op->tmp1()->as_register();
2637         Register t2 = op->tmp2()->as_register();
2638         cmp_value = __ encode_heap_oop(t1, cmp_value);
2639         new_value = __ encode_heap_oop(t2, new_value);
2640       } else {
2641         is_64bit = true;
2642       }
2643     }
2644   } else {
2645     Unimplemented();
2646   }
2647 
2648   if (is_64bit) {
2649     __ cmpxchgd(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2650                 MacroAssembler::MemBarNone,
2651                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2652                 noreg, NULL, /*check without ldarx first*/true);
2653   } else {
2654     __ cmpxchgw(BOOL_RESULT, /*current_value=*/R0, cmp_value, new_value, addr,
2655                 MacroAssembler::MemBarNone,
2656                 MacroAssembler::cmpxchgx_hint_atomic_update(),
2657                 noreg, /*check without ldarx first*/true);
2658   }
2659 
2660   if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
2661     __ isync();
2662   } else {
2663     __ sync();
2664   }
2665 }
2666 
2667 
2668 void LIR_Assembler::set_24bit_FPU() {
2669   Unimplemented();
2670 }
2671 
2672 void LIR_Assembler::reset_FPU() {
2673   Unimplemented();
2674 }
2675 
2676 
2677 void LIR_Assembler::breakpoint() {
2678   __ illtrap();
2679 }
2680 
2681 
2682 void LIR_Assembler::push(LIR_Opr opr) {
2683   Unimplemented();
2684 }
2685 
2686 void LIR_Assembler::pop(LIR_Opr opr) {
2687   Unimplemented();
2688 }
2689 
2690 
2691 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) {
2692   Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no);
2693   Register dst = dst_opr->as_register();
2694   Register reg = mon_addr.base();
2695   int offset = mon_addr.disp();
2696   // Compute pointer to BasicLock.
2697   __ add_const_optimized(dst, reg, offset);
2698 }
2699 
2700 
2701 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2702   Register obj = op->obj_opr()->as_register();
2703   Register hdr = op->hdr_opr()->as_register();
2704   Register lock = op->lock_opr()->as_register();
2705 
2706   // Obj may not be an oop.
2707   if (op->code() == lir_lock) {
2708     MonitorEnterStub* stub = (MonitorEnterStub*)op->stub();
2709     if (UseFastLocking) {
2710       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2711       // Add debug info for NullPointerException only if one is possible.
2712       if (op->info() != NULL) {
2713         if (!os::zero_page_read_protected() || !ImplicitNullChecks) {
2714           explicit_null_check(obj, op->info());
2715         } else {
2716           add_debug_info_for_null_check_here(op->info());
2717         }
2718       }
2719       __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry());
2720     } else {
2721       // always do slow locking
2722       // note: The slow locking code could be inlined here, however if we use
2723       //       slow locking, speed doesn't matter anyway and this solution is
2724       //       simpler and requires less duplicated code - additionally, the
2725       //       slow locking code is the same in either case which simplifies
2726       //       debugging.
2727       __ b(*op->stub()->entry());
2728     }
2729   } else {
2730     assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock");
2731     if (UseFastLocking) {
2732       assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2733       __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2734     } else {
2735       // always do slow unlocking
2736       // note: The slow unlocking code could be inlined here, however if we use
2737       //       slow unlocking, speed doesn't matter anyway and this solution is
2738       //       simpler and requires less duplicated code - additionally, the
2739       //       slow unlocking code is the same in either case which simplifies
2740       //       debugging.
2741       __ b(*op->stub()->entry());
2742     }
2743   }
2744   __ bind(*op->stub()->continuation());
2745 }
2746 
2747 
2748 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2749   ciMethod* method = op->profiled_method();
2750   int bci          = op->profiled_bci();
2751   ciMethod* callee = op->profiled_callee();
2752 
2753   // Update counter for all call types.
2754   ciMethodData* md = method->method_data_or_null();
2755   assert(md != NULL, "Sanity");
2756   ciProfileData* data = md->bci_to_data(bci);
2757   assert(data->is_CounterData(), "need CounterData for calls");
2758   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2759   Register mdo = op->mdo()->as_register();
2760 #ifdef _LP64
2761   assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated");
2762   Register tmp1 = op->tmp1()->as_register_lo();
2763 #else
2764   assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated");
2765   Register tmp1 = op->tmp1()->as_register();
2766 #endif
2767   metadata2reg(md->constant_encoding(), mdo);
2768   int mdo_offset_bias = 0;
2769   if (!Assembler::is_simm16(md->byte_offset_of_slot(data, CounterData::count_offset()) +
2770                             data->size_in_bytes())) {
2771     // The offset is large so bias the mdo by the base of the slot so
2772     // that the ld can use simm16s to reference the slots of the data.
2773     mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset());
2774     __ add_const_optimized(mdo, mdo, mdo_offset_bias, R0);
2775   }
2776 
2777   Bytecodes::Code bc = method->java_code_at_bci(bci);
2778   const bool callee_is_static = callee->is_loaded() && callee->is_static();
2779   // Perform additional virtual call profiling for invokevirtual and
2780   // invokeinterface bytecodes.
2781   if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) &&
2782       !callee_is_static &&  // Required for optimized MH invokes.
2783       C1ProfileVirtualCalls) {
2784     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2785     Register recv = op->recv()->as_register();
2786     assert_different_registers(mdo, tmp1, recv);
2787     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2788     ciKlass* known_klass = op->known_holder();
2789     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2790       // We know the type that will be seen at this call site; we can
2791       // statically update the MethodData* rather than needing to do
2792       // dynamic tests on the receiver type.
2793 
2794       // NOTE: we should probably put a lock around this search to
2795       // avoid collisions by concurrent compilations.
2796       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2797       uint i;
2798       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2799         ciKlass* receiver = vc_data->receiver(i);
2800         if (known_klass->equals(receiver)) {
2801           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2802           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2803           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2804           return;
2805         }
2806       }
2807 
2808       // Receiver type not found in profile data; select an empty slot.
2809 
2810       // Note that this is less efficient than it should be because it
2811       // always does a write to the receiver part of the
2812       // VirtualCallData rather than just the first time.
2813       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2814         ciKlass* receiver = vc_data->receiver(i);
2815         if (receiver == NULL) {
2816           metadata2reg(known_klass->constant_encoding(), tmp1);
2817           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - mdo_offset_bias, mdo);
2818 
2819           __ ld(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2820           __ addi(tmp1, tmp1, DataLayout::counter_increment);
2821           __ std(tmp1, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - mdo_offset_bias, mdo);
2822           return;
2823         }
2824       }
2825     } else {
2826       __ load_klass(recv, recv);
2827       Label update_done;
2828       type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done);
2829       // Receiver did not match any saved receiver and there is no empty row for it.
2830       // Increment total counter to indicate polymorphic case.
2831       __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2832       __ addi(tmp1, tmp1, DataLayout::counter_increment);
2833       __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2834 
2835       __ bind(update_done);
2836     }
2837   } else {
2838     // Static call
2839     __ ld(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2840     __ addi(tmp1, tmp1, DataLayout::counter_increment);
2841     __ std(tmp1, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias, mdo);
2842   }
2843 }
2844 
2845 
2846 void LIR_Assembler::align_backward_branch_target() {
2847   __ align(32, 12); // Insert up to 3 nops to align with 32 byte boundary.
2848 }
2849 
2850 
2851 void LIR_Assembler::emit_delay(LIR_OpDelay* op) {
2852   Unimplemented();
2853 }
2854 
2855 
2856 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) {
2857   assert(left->is_register(), "can only handle registers");
2858 
2859   if (left->is_single_cpu()) {
2860     __ neg(dest->as_register(), left->as_register());
2861   } else if (left->is_single_fpu()) {
2862     __ fneg(dest->as_float_reg(), left->as_float_reg());
2863   } else if (left->is_double_fpu()) {
2864     __ fneg(dest->as_double_reg(), left->as_double_reg());
2865   } else {
2866     assert (left->is_double_cpu(), "Must be a long");
2867     __ neg(dest->as_register_lo(), left->as_register_lo());
2868   }
2869 }
2870 
2871 
2872 void LIR_Assembler::fxch(int i) {
2873   Unimplemented();
2874 }
2875 
2876 void LIR_Assembler::fld(int i) {
2877   Unimplemented();
2878 }
2879 
2880 void LIR_Assembler::ffree(int i) {
2881   Unimplemented();
2882 }
2883 
2884 
2885 void LIR_Assembler::rt_call(LIR_Opr result, address dest,
2886                             const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2887   // Stubs: Called via rt_call, but dest is a stub address (no function descriptor).
2888   if (dest == Runtime1::entry_for(Runtime1::register_finalizer_id) ||
2889       dest == Runtime1::entry_for(Runtime1::new_multi_array_id   )) {
2890     //__ load_const_optimized(R0, dest);
2891     __ add_const_optimized(R0, R29_TOC, MacroAssembler::offset_to_global_toc(dest));
2892     __ mtctr(R0);
2893     __ bctrl();
2894     assert(info != NULL, "sanity");
2895     add_call_info_here(info);
2896     return;
2897   }
2898 
2899   __ call_c_with_frame_resize(dest, /*no resizing*/ 0);
2900   if (info != NULL) {
2901     add_call_info_here(info);
2902   }
2903 }
2904 
2905 
2906 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2907   ShouldNotReachHere(); // Not needed on _LP64.
2908 }
2909 
2910 void LIR_Assembler::membar() {
2911   __ fence();
2912 }
2913 
2914 void LIR_Assembler::membar_acquire() {
2915   __ acquire();
2916 }
2917 
2918 void LIR_Assembler::membar_release() {
2919   __ release();
2920 }
2921 
2922 void LIR_Assembler::membar_loadload() {
2923   __ membar(Assembler::LoadLoad);
2924 }
2925 
2926 void LIR_Assembler::membar_storestore() {
2927   __ membar(Assembler::StoreStore);
2928 }
2929 
2930 void LIR_Assembler::membar_loadstore() {
2931   __ membar(Assembler::LoadStore);
2932 }
2933 
2934 void LIR_Assembler::membar_storeload() {
2935   __ membar(Assembler::StoreLoad);
2936 }
2937 
2938 void LIR_Assembler::on_spin_wait() {
2939   Unimplemented();
2940 }
2941 
2942 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) {
2943   LIR_Address* addr = addr_opr->as_address_ptr();
2944   assert(addr->scale() == LIR_Address::times_1, "no scaling on this platform");
2945   if (addr->index()->is_illegal()) {
2946     __ add_const_optimized(dest->as_pointer_register(), addr->base()->as_pointer_register(), addr->disp());
2947   } else {
2948     assert(addr->disp() == 0, "can't have both: index and disp");
2949     __ add(dest->as_pointer_register(), addr->index()->as_pointer_register(), addr->base()->as_pointer_register());
2950   }
2951 }
2952 
2953 
2954 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2955   ShouldNotReachHere();
2956 }
2957 
2958 
2959 #ifdef ASSERT
2960 // Emit run-time assertion.
2961 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2962   Unimplemented();
2963 }
2964 #endif
2965 
2966 
2967 void LIR_Assembler::peephole(LIR_List* lir) {
2968   // Optimize instruction pairs before emitting.
2969   LIR_OpList* inst = lir->instructions_list();
2970   for (int i = 1; i < inst->length(); i++) {
2971     LIR_Op* op = inst->at(i);
2972 
2973     // 2 register-register-moves
2974     if (op->code() == lir_move) {
2975       LIR_Opr in2  = ((LIR_Op1*)op)->in_opr(),
2976               res2 = ((LIR_Op1*)op)->result_opr();
2977       if (in2->is_register() && res2->is_register()) {
2978         LIR_Op* prev = inst->at(i - 1);
2979         if (prev && prev->code() == lir_move) {
2980           LIR_Opr in1  = ((LIR_Op1*)prev)->in_opr(),
2981                   res1 = ((LIR_Op1*)prev)->result_opr();
2982           if (in1->is_same_register(res2) && in2->is_same_register(res1)) {
2983             inst->remove_at(i);
2984           }
2985         }
2986       }
2987     }
2988 
2989   }
2990   return;
2991 }
2992 
2993 
2994 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
2995   const Register Rptr = src->as_pointer_register(),
2996                  Rtmp = tmp->as_register();
2997   Register Rco = noreg;
2998   if (UseCompressedOops && data->is_oop()) {
2999     Rco = __ encode_heap_oop(Rtmp, data->as_register());
3000   }
3001 
3002   Label Lretry;
3003   __ bind(Lretry);
3004 
3005   if (data->type() == T_INT) {
3006     const Register Rold = dest->as_register(),
3007                    Rsrc = data->as_register();
3008     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3009     __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3010     if (code == lir_xadd) {
3011       __ add(Rtmp, Rsrc, Rold);
3012       __ stwcx_(Rtmp, Rptr);
3013     } else {
3014       __ stwcx_(Rsrc, Rptr);
3015     }
3016   } else if (data->is_oop()) {
3017     assert(code == lir_xchg, "xadd for oops");
3018     const Register Rold = dest->as_register();
3019     if (UseCompressedOops) {
3020       assert_different_registers(Rptr, Rold, Rco);
3021       __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3022       __ stwcx_(Rco, Rptr);
3023     } else {
3024       const Register Robj = data->as_register();
3025       assert_different_registers(Rptr, Rold, Robj);
3026       __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3027       __ stdcx_(Robj, Rptr);
3028     }
3029   } else if (data->type() == T_LONG) {
3030     const Register Rold = dest->as_register_lo(),
3031                    Rsrc = data->as_register_lo();
3032     assert_different_registers(Rptr, Rtmp, Rold, Rsrc);
3033     __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update());
3034     if (code == lir_xadd) {
3035       __ add(Rtmp, Rsrc, Rold);
3036       __ stdcx_(Rtmp, Rptr);
3037     } else {
3038       __ stdcx_(Rsrc, Rptr);
3039     }
3040   } else {
3041     ShouldNotReachHere();
3042   }
3043 
3044   if (UseStaticBranchPredictionInCompareAndSwapPPC64) {
3045     __ bne_predict_not_taken(CCR0, Lretry);
3046   } else {
3047     __ bne(                  CCR0, Lretry);
3048   }
3049 
3050   if (UseCompressedOops && data->is_oop()) {
3051     __ decode_heap_oop(dest->as_register());
3052   }
3053 }
3054 
3055 
3056 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3057   Register obj = op->obj()->as_register();
3058   Register tmp = op->tmp()->as_pointer_register();
3059   LIR_Address* mdo_addr = op->mdp()->as_address_ptr();
3060   ciKlass* exact_klass = op->exact_klass();
3061   intptr_t current_klass = op->current_klass();
3062   bool not_null = op->not_null();
3063   bool no_conflict = op->no_conflict();
3064 
3065   Label Lupdate, Ldo_update, Ldone;
3066 
3067   bool do_null = !not_null;
3068   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3069   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3070 
3071   assert(do_null || do_update, "why are we here?");
3072   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3073 
3074   __ verify_oop(obj);
3075 
3076   if (do_null) {
3077     if (!TypeEntries::was_null_seen(current_klass)) {
3078       __ cmpdi(CCR0, obj, 0);
3079       __ bne(CCR0, Lupdate);
3080       __ ld(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3081       __ ori(R0, R0, TypeEntries::null_seen);
3082       if (do_update) {
3083         __ b(Ldo_update);
3084       } else {
3085         __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3086       }
3087     } else {
3088       if (do_update) {
3089         __ cmpdi(CCR0, obj, 0);
3090         __ beq(CCR0, Ldone);
3091       }
3092     }
3093 #ifdef ASSERT
3094   } else {
3095     __ cmpdi(CCR0, obj, 0);
3096     __ bne(CCR0, Lupdate);
3097     __ stop("unexpect null obj", 0x9652);
3098 #endif
3099   }
3100 
3101   __ bind(Lupdate);
3102   if (do_update) {
3103     Label Lnext;
3104     const Register klass = R29_TOC; // kill and reload
3105     bool klass_reg_used = false;
3106 #ifdef ASSERT
3107     if (exact_klass != NULL) {
3108       Label ok;
3109       klass_reg_used = true;
3110       __ load_klass(klass, obj);
3111       metadata2reg(exact_klass->constant_encoding(), R0);
3112       __ cmpd(CCR0, klass, R0);
3113       __ beq(CCR0, ok);
3114       __ stop("exact klass and actual klass differ", 0x8564);
3115       __ bind(ok);
3116     }
3117 #endif
3118 
3119     if (!no_conflict) {
3120       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3121         klass_reg_used = true;
3122         if (exact_klass != NULL) {
3123           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3124           metadata2reg(exact_klass->constant_encoding(), klass);
3125         } else {
3126           __ load_klass(klass, obj);
3127           __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register()); // may kill obj
3128         }
3129 
3130         // Like InterpreterMacroAssembler::profile_obj_type
3131         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3132         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3133         __ cmpd(CCR1, R0, klass);
3134         // Klass seen before, nothing to do (regardless of unknown bit).
3135         //beq(CCR1, do_nothing);
3136 
3137         __ andi_(R0, klass, TypeEntries::type_unknown);
3138         // Already unknown. Nothing to do anymore.
3139         //bne(CCR0, do_nothing);
3140         __ crorc(CCR0, Assembler::equal, CCR1, Assembler::equal); // cr0 eq = cr1 eq or cr0 ne
3141         __ beq(CCR0, Lnext);
3142 
3143         if (TypeEntries::is_type_none(current_klass)) {
3144           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3145           __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3146           __ beq(CCR0, Ldo_update); // First time here. Set profile type.
3147         }
3148 
3149       } else {
3150         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3151                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3152 
3153         __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3154         __ andi_(R0, tmp, TypeEntries::type_unknown);
3155         // Already unknown. Nothing to do anymore.
3156         __ bne(CCR0, Lnext);
3157       }
3158 
3159       // Different than before. Cannot keep accurate profile.
3160       __ ori(R0, tmp, TypeEntries::type_unknown);
3161     } else {
3162       // There's a single possible klass at this profile point
3163       assert(exact_klass != NULL, "should be");
3164       __ ld(tmp, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3165 
3166       if (TypeEntries::is_type_none(current_klass)) {
3167         klass_reg_used = true;
3168         metadata2reg(exact_klass->constant_encoding(), klass);
3169 
3170         __ clrrdi(R0, tmp, exact_log2(-TypeEntries::type_klass_mask));
3171         // Basically same as andi(R0, tmp, TypeEntries::type_klass_mask);
3172         __ cmpd(CCR1, R0, klass);
3173         // Klass seen before, nothing to do (regardless of unknown bit).
3174         __ beq(CCR1, Lnext);
3175 #ifdef ASSERT
3176         {
3177           Label ok;
3178           __ clrrdi_(R0, tmp, exact_log2(-TypeEntries::type_mask));
3179           __ beq(CCR0, ok); // First time here.
3180 
3181           __ stop("unexpected profiling mismatch", 0x7865);
3182           __ bind(ok);
3183         }
3184 #endif
3185         // First time here. Set profile type.
3186         __ orr(R0, klass, tmp); // Combine klass and null_seen bit (only used if (tmp & type_mask)==0).
3187       } else {
3188         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3189                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3190 
3191         // Already unknown. Nothing to do anymore.
3192         __ andi_(R0, tmp, TypeEntries::type_unknown);
3193         __ bne(CCR0, Lnext);
3194 
3195         // Different than before. Cannot keep accurate profile.
3196         __ ori(R0, tmp, TypeEntries::type_unknown);
3197       }
3198     }
3199 
3200     __ bind(Ldo_update);
3201     __ std(R0, index_or_disp(mdo_addr), mdo_addr->base()->as_pointer_register());
3202 
3203     __ bind(Lnext);
3204     if (klass_reg_used) { __ load_const_optimized(R29_TOC, MacroAssembler::global_toc(), R0); } // reinit
3205   }
3206   __ bind(Ldone);
3207 }
3208 
3209 
3210 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3211   assert(op->crc()->is_single_cpu(), "crc must be register");
3212   assert(op->val()->is_single_cpu(), "byte value must be register");
3213   assert(op->result_opr()->is_single_cpu(), "result must be register");
3214   Register crc = op->crc()->as_register();
3215   Register val = op->val()->as_register();
3216   Register res = op->result_opr()->as_register();
3217 
3218   assert_different_registers(val, crc, res);
3219 
3220   __ load_const_optimized(res, StubRoutines::crc_table_addr(), R0);
3221   __ kernel_crc32_singleByteReg(crc, val, res, true);
3222   __ mr(res, crc);
3223 }
3224 
3225 #undef __
--- EOF ---