1 //
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   3 // Copyright (c) 2012, 2017 SAP SE. All rights reserved.
   4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5 //
   6 // This code is free software; you can redistribute it and/or modify it
   7 // under the terms of the GNU General Public License version 2 only, as
   8 // published by the Free Software Foundation.
   9 //
  10 // This code is distributed in the hope that it will be useful, but WITHOUT
  11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13 // version 2 for more details (a copy is included in the LICENSE file that
  14 // accompanied this code).
  15 //
  16 // You should have received a copy of the GNU General Public License version
  17 // 2 along with this work; if not, write to the Free Software Foundation,
  18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19 //
  20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21 // or visit www.oracle.com if you need additional information or have any
  22 // questions.
  23 //
  24 //
  25 
  26 //
  27 // PPC64 Architecture Description File
  28 //
  29 
  30 //----------REGISTER DEFINITION BLOCK------------------------------------------
  31 // This information is used by the matcher and the register allocator to
  32 // describe individual registers and classes of registers within the target
  33 // architecture.
  34 register %{
  35 //----------Architecture Description Register Definitions----------------------
  36 // General Registers
  37 // "reg_def"  name (register save type, C convention save type,
  38 //                  ideal register type, encoding);
  39 //
  40 // Register Save Types:
  41 //
  42 //   NS  = No-Save:     The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method, &
  44 //                      that they do not need to be saved at call sites.
  45 //
  46 //   SOC = Save-On-Call: The register allocator assumes that these registers
  47 //                      can be used without saving upon entry to the method,
  48 //                      but that they must be saved at call sites.
  49 //                      These are called "volatiles" on ppc.
  50 //
  51 //   SOE = Save-On-Entry: The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, but they do not need to be saved at call
  54 //                      sites.
  55 //                      These are called "nonvolatiles" on ppc.
  56 //
  57 //   AS  = Always-Save:   The register allocator assumes that these registers
  58 //                      must be saved before using them upon entry to the
  59 //                      method, & that they must be saved at call sites.
  60 //
  61 // Ideal Register Type is used to determine how to save & restore a
  62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
  64 //
  65 // The encoding number is the actual bit-pattern placed into the opcodes.
  66 //
  67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI
  68 // Supplement Version 1.7 as of 2003-10-29.
  69 //
  70 // For each 64-bit register we must define two registers: the register
  71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half',
  72 // e.g. R3_H, which is needed by the allocator, but is not used
  73 // for stores, loads, etc.
  74 
  75 // ----------------------------
  76 // Integer/Long Registers
  77 // ----------------------------
  78 
  79   // PPC64 has 32 64-bit integer registers.
  80 
  81   // types: v = volatile, nv = non-volatile, s = system
  82   reg_def R0   ( SOC, SOC, Op_RegI,  0, R0->as_VMReg()         );  // v   used in prologs
  83   reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() );
  84   reg_def R1   ( NS,  NS,  Op_RegI,  1, R1->as_VMReg()         );  // s   SP
  85   reg_def R1_H ( NS,  NS,  Op_RegI, 99, R1->as_VMReg()->next() );
  86   reg_def R2   ( SOC, SOC, Op_RegI,  2, R2->as_VMReg()         );  // v   TOC
  87   reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() );
  88   reg_def R3   ( SOC, SOC, Op_RegI,  3, R3->as_VMReg()         );  // v   iarg1 & iret
  89   reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() );
  90   reg_def R4   ( SOC, SOC, Op_RegI,  4, R4->as_VMReg()         );  //     iarg2
  91   reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() );
  92   reg_def R5   ( SOC, SOC, Op_RegI,  5, R5->as_VMReg()         );  // v   iarg3
  93   reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() );
  94   reg_def R6   ( SOC, SOC, Op_RegI,  6, R6->as_VMReg()         );  // v   iarg4
  95   reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() );
  96   reg_def R7   ( SOC, SOC, Op_RegI,  7, R7->as_VMReg()         );  // v   iarg5
  97   reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() );
  98   reg_def R8   ( SOC, SOC, Op_RegI,  8, R8->as_VMReg()         );  // v   iarg6
  99   reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() );
 100   reg_def R9   ( SOC, SOC, Op_RegI,  9, R9->as_VMReg()         );  // v   iarg7
 101   reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() );
 102   reg_def R10  ( SOC, SOC, Op_RegI, 10, R10->as_VMReg()        );  // v   iarg8
 103   reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next());
 104   reg_def R11  ( SOC, SOC, Op_RegI, 11, R11->as_VMReg()        );  // v   ENV / scratch
 105   reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next());
 106   reg_def R12  ( SOC, SOC, Op_RegI, 12, R12->as_VMReg()        );  // v   scratch
 107   reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next());
 108   reg_def R13  ( NS,  NS,  Op_RegI, 13, R13->as_VMReg()        );  // s   system thread id
 109   reg_def R13_H( NS,  NS,  Op_RegI, 99, R13->as_VMReg()->next());
 110   reg_def R14  ( SOC, SOE, Op_RegI, 14, R14->as_VMReg()        );  // nv
 111   reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next());
 112   reg_def R15  ( SOC, SOE, Op_RegI, 15, R15->as_VMReg()        );  // nv
 113   reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next());
 114   reg_def R16  ( SOC, SOE, Op_RegI, 16, R16->as_VMReg()        );  // nv
 115   reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next());
 116   reg_def R17  ( SOC, SOE, Op_RegI, 17, R17->as_VMReg()        );  // nv
 117   reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next());
 118   reg_def R18  ( SOC, SOE, Op_RegI, 18, R18->as_VMReg()        );  // nv
 119   reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next());
 120   reg_def R19  ( SOC, SOE, Op_RegI, 19, R19->as_VMReg()        );  // nv
 121   reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next());
 122   reg_def R20  ( SOC, SOE, Op_RegI, 20, R20->as_VMReg()        );  // nv
 123   reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next());
 124   reg_def R21  ( SOC, SOE, Op_RegI, 21, R21->as_VMReg()        );  // nv
 125   reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next());
 126   reg_def R22  ( SOC, SOE, Op_RegI, 22, R22->as_VMReg()        );  // nv
 127   reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next());
 128   reg_def R23  ( SOC, SOE, Op_RegI, 23, R23->as_VMReg()        );  // nv
 129   reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next());
 130   reg_def R24  ( SOC, SOE, Op_RegI, 24, R24->as_VMReg()        );  // nv
 131   reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next());
 132   reg_def R25  ( SOC, SOE, Op_RegI, 25, R25->as_VMReg()        );  // nv
 133   reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next());
 134   reg_def R26  ( SOC, SOE, Op_RegI, 26, R26->as_VMReg()        );  // nv
 135   reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next());
 136   reg_def R27  ( SOC, SOE, Op_RegI, 27, R27->as_VMReg()        );  // nv
 137   reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next());
 138   reg_def R28  ( SOC, SOE, Op_RegI, 28, R28->as_VMReg()        );  // nv
 139   reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next());
 140   reg_def R29  ( SOC, SOE, Op_RegI, 29, R29->as_VMReg()        );  // nv
 141   reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next());
 142   reg_def R30  ( SOC, SOE, Op_RegI, 30, R30->as_VMReg()        );  // nv
 143   reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next());
 144   reg_def R31  ( SOC, SOE, Op_RegI, 31, R31->as_VMReg()        );  // nv
 145   reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next());
 146 
 147 
 148 // ----------------------------
 149 // Float/Double Registers
 150 // ----------------------------
 151 
 152   // Double Registers
 153   // The rules of ADL require that double registers be defined in pairs.
 154   // Each pair must be two 32-bit values, but not necessarily a pair of
 155   // single float registers. In each pair, ADLC-assigned register numbers
 156   // must be adjacent, with the lower number even. Finally, when the
 157   // CPU stores such a register pair to memory, the word associated with
 158   // the lower ADLC-assigned number must be stored to the lower address.
 159 
 160   // PPC64 has 32 64-bit floating-point registers. Each can store a single
 161   // or double precision floating-point value.
 162 
 163   // types: v = volatile, nv = non-volatile, s = system
 164   reg_def F0   ( SOC, SOC, Op_RegF,  0, F0->as_VMReg()         );  // v   scratch
 165   reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() );
 166   reg_def F1   ( SOC, SOC, Op_RegF,  1, F1->as_VMReg()         );  // v   farg1 & fret
 167   reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() );
 168   reg_def F2   ( SOC, SOC, Op_RegF,  2, F2->as_VMReg()         );  // v   farg2
 169   reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() );
 170   reg_def F3   ( SOC, SOC, Op_RegF,  3, F3->as_VMReg()         );  // v   farg3
 171   reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() );
 172   reg_def F4   ( SOC, SOC, Op_RegF,  4, F4->as_VMReg()         );  // v   farg4
 173   reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() );
 174   reg_def F5   ( SOC, SOC, Op_RegF,  5, F5->as_VMReg()         );  // v   farg5
 175   reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() );
 176   reg_def F6   ( SOC, SOC, Op_RegF,  6, F6->as_VMReg()         );  // v   farg6
 177   reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() );
 178   reg_def F7   ( SOC, SOC, Op_RegF,  7, F7->as_VMReg()         );  // v   farg7
 179   reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() );
 180   reg_def F8   ( SOC, SOC, Op_RegF,  8, F8->as_VMReg()         );  // v   farg8
 181   reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() );
 182   reg_def F9   ( SOC, SOC, Op_RegF,  9, F9->as_VMReg()         );  // v   farg9
 183   reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() );
 184   reg_def F10  ( SOC, SOC, Op_RegF, 10, F10->as_VMReg()        );  // v   farg10
 185   reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next());
 186   reg_def F11  ( SOC, SOC, Op_RegF, 11, F11->as_VMReg()        );  // v   farg11
 187   reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next());
 188   reg_def F12  ( SOC, SOC, Op_RegF, 12, F12->as_VMReg()        );  // v   farg12
 189   reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next());
 190   reg_def F13  ( SOC, SOC, Op_RegF, 13, F13->as_VMReg()        );  // v   farg13
 191   reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next());
 192   reg_def F14  ( SOC, SOE, Op_RegF, 14, F14->as_VMReg()        );  // nv
 193   reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next());
 194   reg_def F15  ( SOC, SOE, Op_RegF, 15, F15->as_VMReg()        );  // nv
 195   reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next());
 196   reg_def F16  ( SOC, SOE, Op_RegF, 16, F16->as_VMReg()        );  // nv
 197   reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next());
 198   reg_def F17  ( SOC, SOE, Op_RegF, 17, F17->as_VMReg()        );  // nv
 199   reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next());
 200   reg_def F18  ( SOC, SOE, Op_RegF, 18, F18->as_VMReg()        );  // nv
 201   reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next());
 202   reg_def F19  ( SOC, SOE, Op_RegF, 19, F19->as_VMReg()        );  // nv
 203   reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next());
 204   reg_def F20  ( SOC, SOE, Op_RegF, 20, F20->as_VMReg()        );  // nv
 205   reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next());
 206   reg_def F21  ( SOC, SOE, Op_RegF, 21, F21->as_VMReg()        );  // nv
 207   reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next());
 208   reg_def F22  ( SOC, SOE, Op_RegF, 22, F22->as_VMReg()        );  // nv
 209   reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next());
 210   reg_def F23  ( SOC, SOE, Op_RegF, 23, F23->as_VMReg()        );  // nv
 211   reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next());
 212   reg_def F24  ( SOC, SOE, Op_RegF, 24, F24->as_VMReg()        );  // nv
 213   reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next());
 214   reg_def F25  ( SOC, SOE, Op_RegF, 25, F25->as_VMReg()        );  // nv
 215   reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next());
 216   reg_def F26  ( SOC, SOE, Op_RegF, 26, F26->as_VMReg()        );  // nv
 217   reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next());
 218   reg_def F27  ( SOC, SOE, Op_RegF, 27, F27->as_VMReg()        );  // nv
 219   reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next());
 220   reg_def F28  ( SOC, SOE, Op_RegF, 28, F28->as_VMReg()        );  // nv
 221   reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next());
 222   reg_def F29  ( SOC, SOE, Op_RegF, 29, F29->as_VMReg()        );  // nv
 223   reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next());
 224   reg_def F30  ( SOC, SOE, Op_RegF, 30, F30->as_VMReg()        );  // nv
 225   reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next());
 226   reg_def F31  ( SOC, SOE, Op_RegF, 31, F31->as_VMReg()        );  // nv
 227   reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next());
 228 
 229 // ----------------------------
 230 // Special Registers
 231 // ----------------------------
 232 
 233 // Condition Codes Flag Registers
 234 
 235   // PPC64 has 8 condition code "registers" which are all contained
 236   // in the CR register.
 237 
 238   // types: v = volatile, nv = non-volatile, s = system
 239   reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg());  // v
 240   reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg());  // v
 241   reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg());  // nv
 242   reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg());  // nv
 243   reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg());  // nv
 244   reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg());  // v
 245   reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg());  // v
 246   reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg());  // v
 247 
 248   // Special registers of PPC64
 249 
 250   reg_def SR_XER(    SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg());     // v
 251   reg_def SR_LR(     SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg());      // v
 252   reg_def SR_CTR(    SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg());     // v
 253   reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg());  // v
 254   reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v
 255   reg_def SR_PPR(    SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg());     // v
 256 
 257 
 258 // ----------------------------
 259 // Specify priority of register selection within phases of register
 260 // allocation. Highest priority is first. A useful heuristic is to
 261 // give registers a low priority when they are required by machine
 262 // instructions, like EAX and EDX on I486, and choose no-save registers
 263 // before save-on-call, & save-on-call before save-on-entry. Registers
 264 // which participate in fixed calling sequences should come last.
 265 // Registers which are used as pairs must fall on an even boundary.
 266 
 267 // It's worth about 1% on SPEC geomean to get this right.
 268 
 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g.
 271 // R3_num. Therefore, R3_num may not be (and in reality is not)
 272 // the same as R3->encoding()! Furthermore, we cannot make any
 273 // assumptions on ordering, e.g. R3_num may be less than R2_num.
 274 // Additionally, the function
 275 //   static enum RC rc_class(OptoReg::Name reg )
 276 // maps a given <register>_num value to its chunk type (except for flags)
 277 // and its current implementation relies on chunk0 and chunk1 having a
 278 // size of 64 each.
 279 
 280 // If you change this allocation class, please have a look at the
 281 // default values for the parameters RoundRobinIntegerRegIntervalStart
 282 // and RoundRobinFloatRegIntervalStart
 283 
 284 alloc_class chunk0 (
 285   // Chunk0 contains *all* 64 integer registers halves.
 286 
 287   // "non-volatile" registers
 288   R14, R14_H,
 289   R15, R15_H,
 290   R17, R17_H,
 291   R18, R18_H,
 292   R19, R19_H,
 293   R20, R20_H,
 294   R21, R21_H,
 295   R22, R22_H,
 296   R23, R23_H,
 297   R24, R24_H,
 298   R25, R25_H,
 299   R26, R26_H,
 300   R27, R27_H,
 301   R28, R28_H,
 302   R29, R29_H,
 303   R30, R30_H,
 304   R31, R31_H,
 305 
 306   // scratch/special registers
 307   R11, R11_H,
 308   R12, R12_H,
 309 
 310   // argument registers
 311   R10, R10_H,
 312   R9,  R9_H,
 313   R8,  R8_H,
 314   R7,  R7_H,
 315   R6,  R6_H,
 316   R5,  R5_H,
 317   R4,  R4_H,
 318   R3,  R3_H,
 319 
 320   // special registers, not available for allocation
 321   R16, R16_H,     // R16_thread
 322   R13, R13_H,     // system thread id
 323   R2,  R2_H,      // may be used for TOC
 324   R1,  R1_H,      // SP
 325   R0,  R0_H       // R0 (scratch)
 326 );
 327 
 328 // If you change this allocation class, please have a look at the
 329 // default values for the parameters RoundRobinIntegerRegIntervalStart
 330 // and RoundRobinFloatRegIntervalStart
 331 
 332 alloc_class chunk1 (
 333   // Chunk1 contains *all* 64 floating-point registers halves.
 334 
 335   // scratch register
 336   F0,  F0_H,
 337 
 338   // argument registers
 339   F13, F13_H,
 340   F12, F12_H,
 341   F11, F11_H,
 342   F10, F10_H,
 343   F9,  F9_H,
 344   F8,  F8_H,
 345   F7,  F7_H,
 346   F6,  F6_H,
 347   F5,  F5_H,
 348   F4,  F4_H,
 349   F3,  F3_H,
 350   F2,  F2_H,
 351   F1,  F1_H,
 352 
 353   // non-volatile registers
 354   F14, F14_H,
 355   F15, F15_H,
 356   F16, F16_H,
 357   F17, F17_H,
 358   F18, F18_H,
 359   F19, F19_H,
 360   F20, F20_H,
 361   F21, F21_H,
 362   F22, F22_H,
 363   F23, F23_H,
 364   F24, F24_H,
 365   F25, F25_H,
 366   F26, F26_H,
 367   F27, F27_H,
 368   F28, F28_H,
 369   F29, F29_H,
 370   F30, F30_H,
 371   F31, F31_H
 372 );
 373 
 374 alloc_class chunk2 (
 375   // Chunk2 contains *all* 8 condition code registers.
 376 
 377   CCR0,
 378   CCR1,
 379   CCR2,
 380   CCR3,
 381   CCR4,
 382   CCR5,
 383   CCR6,
 384   CCR7
 385 );
 386 
 387 alloc_class chunk3 (
 388   // special registers
 389   // These registers are not allocated, but used for nodes generated by postalloc expand.
 390   SR_XER,
 391   SR_LR,
 392   SR_CTR,
 393   SR_VRSAVE,
 394   SR_SPEFSCR,
 395   SR_PPR
 396 );
 397 
 398 //-------Architecture Description Register Classes-----------------------
 399 
 400 // Several register classes are automatically defined based upon
 401 // information in this architecture description.
 402 
 403 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 404 // 2) reg_class compiler_method_oop_reg    ( as defined in frame section )
 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 407 //
 408 
 409 // ----------------------------
 410 // 32 Bit Register Classes
 411 // ----------------------------
 412 
 413 // We specify registers twice, once as read/write, and once read-only.
 414 // We use the read-only registers for source operands. With this, we
 415 // can include preset read only registers in this class, as a hard-coded
 416 // '0'-register. (We used to simulate this on ppc.)
 417 
 418 // 32 bit registers that can be read and written i.e. these registers
 419 // can be dest (or src) of normal instructions.
 420 reg_class bits32_reg_rw(
 421 /*R0*/              // R0
 422 /*R1*/              // SP
 423   R2,               // TOC
 424   R3,
 425   R4,
 426   R5,
 427   R6,
 428   R7,
 429   R8,
 430   R9,
 431   R10,
 432   R11,
 433   R12,
 434 /*R13*/             // system thread id
 435   R14,
 436   R15,
 437 /*R16*/             // R16_thread
 438   R17,
 439   R18,
 440   R19,
 441   R20,
 442   R21,
 443   R22,
 444   R23,
 445   R24,
 446   R25,
 447   R26,
 448   R27,
 449   R28,
 450 /*R29,*/             // global TOC
 451   R30,
 452   R31
 453 );
 454 
 455 // 32 bit registers that can only be read i.e. these registers can
 456 // only be src of all instructions.
 457 reg_class bits32_reg_ro(
 458 /*R0*/              // R0
 459 /*R1*/              // SP
 460   R2                // TOC
 461   R3,
 462   R4,
 463   R5,
 464   R6,
 465   R7,
 466   R8,
 467   R9,
 468   R10,
 469   R11,
 470   R12,
 471 /*R13*/             // system thread id
 472   R14,
 473   R15,
 474 /*R16*/             // R16_thread
 475   R17,
 476   R18,
 477   R19,
 478   R20,
 479   R21,
 480   R22,
 481   R23,
 482   R24,
 483   R25,
 484   R26,
 485   R27,
 486   R28,
 487 /*R29,*/
 488   R30,
 489   R31
 490 );
 491 
 492 reg_class rscratch1_bits32_reg(R11);
 493 reg_class rscratch2_bits32_reg(R12);
 494 reg_class rarg1_bits32_reg(R3);
 495 reg_class rarg2_bits32_reg(R4);
 496 reg_class rarg3_bits32_reg(R5);
 497 reg_class rarg4_bits32_reg(R6);
 498 
 499 // ----------------------------
 500 // 64 Bit Register Classes
 501 // ----------------------------
 502 // 64-bit build means 64-bit pointers means hi/lo pairs
 503 
 504 reg_class rscratch1_bits64_reg(R11_H, R11);
 505 reg_class rscratch2_bits64_reg(R12_H, R12);
 506 reg_class rarg1_bits64_reg(R3_H, R3);
 507 reg_class rarg2_bits64_reg(R4_H, R4);
 508 reg_class rarg3_bits64_reg(R5_H, R5);
 509 reg_class rarg4_bits64_reg(R6_H, R6);
 510 // Thread register, 'written' by tlsLoadP, see there.
 511 reg_class thread_bits64_reg(R16_H, R16);
 512 
 513 reg_class r19_bits64_reg(R19_H, R19);
 514 
 515 // 64 bit registers that can be read and written i.e. these registers
 516 // can be dest (or src) of normal instructions.
 517 reg_class bits64_reg_rw(
 518 /*R0_H,  R0*/     // R0
 519 /*R1_H,  R1*/     // SP
 520   R2_H,  R2,      // TOC
 521   R3_H,  R3,
 522   R4_H,  R4,
 523   R5_H,  R5,
 524   R6_H,  R6,
 525   R7_H,  R7,
 526   R8_H,  R8,
 527   R9_H,  R9,
 528   R10_H, R10,
 529   R11_H, R11,
 530   R12_H, R12,
 531 /*R13_H, R13*/   // system thread id
 532   R14_H, R14,
 533   R15_H, R15,
 534 /*R16_H, R16*/   // R16_thread
 535   R17_H, R17,
 536   R18_H, R18,
 537   R19_H, R19,
 538   R20_H, R20,
 539   R21_H, R21,
 540   R22_H, R22,
 541   R23_H, R23,
 542   R24_H, R24,
 543   R25_H, R25,
 544   R26_H, R26,
 545   R27_H, R27,
 546   R28_H, R28,
 547 /*R29_H, R29,*/
 548   R30_H, R30,
 549   R31_H, R31
 550 );
 551 
 552 // 64 bit registers used excluding r2, r11 and r12
 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses
 554 // r2, r11 and r12 internally.
 555 reg_class bits64_reg_leaf_call(
 556 /*R0_H,  R0*/     // R0
 557 /*R1_H,  R1*/     // SP
 558 /*R2_H,  R2*/     // TOC
 559   R3_H,  R3,
 560   R4_H,  R4,
 561   R5_H,  R5,
 562   R6_H,  R6,
 563   R7_H,  R7,
 564   R8_H,  R8,
 565   R9_H,  R9,
 566   R10_H, R10,
 567 /*R11_H, R11*/
 568 /*R12_H, R12*/
 569 /*R13_H, R13*/   // system thread id
 570   R14_H, R14,
 571   R15_H, R15,
 572 /*R16_H, R16*/   // R16_thread
 573   R17_H, R17,
 574   R18_H, R18,
 575   R19_H, R19,
 576   R20_H, R20,
 577   R21_H, R21,
 578   R22_H, R22,
 579   R23_H, R23,
 580   R24_H, R24,
 581   R25_H, R25,
 582   R26_H, R26,
 583   R27_H, R27,
 584   R28_H, R28,
 585 /*R29_H, R29,*/
 586   R30_H, R30,
 587   R31_H, R31
 588 );
 589 
 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall
 591 // which uses r19 as inline cache internally and expanded LeafCall which uses
 592 // r2, r11 and r12 internally.
 593 reg_class bits64_constant_table_base(
 594 /*R0_H,  R0*/     // R0
 595 /*R1_H,  R1*/     // SP
 596 /*R2_H,  R2*/     // TOC
 597   R3_H,  R3,
 598   R4_H,  R4,
 599   R5_H,  R5,
 600   R6_H,  R6,
 601   R7_H,  R7,
 602   R8_H,  R8,
 603   R9_H,  R9,
 604   R10_H, R10,
 605 /*R11_H, R11*/
 606 /*R12_H, R12*/
 607 /*R13_H, R13*/   // system thread id
 608   R14_H, R14,
 609   R15_H, R15,
 610 /*R16_H, R16*/   // R16_thread
 611   R17_H, R17,
 612   R18_H, R18,
 613 /*R19_H, R19*/
 614   R20_H, R20,
 615   R21_H, R21,
 616   R22_H, R22,
 617   R23_H, R23,
 618   R24_H, R24,
 619   R25_H, R25,
 620   R26_H, R26,
 621   R27_H, R27,
 622   R28_H, R28,
 623 /*R29_H, R29,*/
 624   R30_H, R30,
 625   R31_H, R31
 626 );
 627 
 628 // 64 bit registers that can only be read i.e. these registers can
 629 // only be src of all instructions.
 630 reg_class bits64_reg_ro(
 631 /*R0_H,  R0*/     // R0
 632   R1_H,  R1,
 633   R2_H,  R2,       // TOC
 634   R3_H,  R3,
 635   R4_H,  R4,
 636   R5_H,  R5,
 637   R6_H,  R6,
 638   R7_H,  R7,
 639   R8_H,  R8,
 640   R9_H,  R9,
 641   R10_H, R10,
 642   R11_H, R11,
 643   R12_H, R12,
 644 /*R13_H, R13*/   // system thread id
 645   R14_H, R14,
 646   R15_H, R15,
 647   R16_H, R16,    // R16_thread
 648   R17_H, R17,
 649   R18_H, R18,
 650   R19_H, R19,
 651   R20_H, R20,
 652   R21_H, R21,
 653   R22_H, R22,
 654   R23_H, R23,
 655   R24_H, R24,
 656   R25_H, R25,
 657   R26_H, R26,
 658   R27_H, R27,
 659   R28_H, R28,
 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!!
 661   R30_H, R30,
 662   R31_H, R31
 663 );
 664 
 665 
 666 // ----------------------------
 667 // Special Class for Condition Code Flags Register
 668 
 669 reg_class int_flags(
 670 /*CCR0*/             // scratch
 671 /*CCR1*/             // scratch
 672 /*CCR2*/             // nv!
 673 /*CCR3*/             // nv!
 674 /*CCR4*/             // nv!
 675   CCR5,
 676   CCR6,
 677   CCR7
 678 );
 679 
 680 reg_class int_flags_ro(
 681   CCR0,
 682   CCR1,
 683   CCR2,
 684   CCR3,
 685   CCR4,
 686   CCR5,
 687   CCR6,
 688   CCR7
 689 );
 690 
 691 reg_class int_flags_CR0(CCR0);
 692 reg_class int_flags_CR1(CCR1);
 693 reg_class int_flags_CR6(CCR6);
 694 reg_class ctr_reg(SR_CTR);
 695 
 696 // ----------------------------
 697 // Float Register Classes
 698 // ----------------------------
 699 
 700 reg_class flt_reg(
 701   F0,
 702   F1,
 703   F2,
 704   F3,
 705   F4,
 706   F5,
 707   F6,
 708   F7,
 709   F8,
 710   F9,
 711   F10,
 712   F11,
 713   F12,
 714   F13,
 715   F14,              // nv!
 716   F15,              // nv!
 717   F16,              // nv!
 718   F17,              // nv!
 719   F18,              // nv!
 720   F19,              // nv!
 721   F20,              // nv!
 722   F21,              // nv!
 723   F22,              // nv!
 724   F23,              // nv!
 725   F24,              // nv!
 726   F25,              // nv!
 727   F26,              // nv!
 728   F27,              // nv!
 729   F28,              // nv!
 730   F29,              // nv!
 731   F30,              // nv!
 732   F31               // nv!
 733 );
 734 
 735 // Double precision float registers have virtual `high halves' that
 736 // are needed by the allocator.
 737 reg_class dbl_reg(
 738   F0,  F0_H,
 739   F1,  F1_H,
 740   F2,  F2_H,
 741   F3,  F3_H,
 742   F4,  F4_H,
 743   F5,  F5_H,
 744   F6,  F6_H,
 745   F7,  F7_H,
 746   F8,  F8_H,
 747   F9,  F9_H,
 748   F10, F10_H,
 749   F11, F11_H,
 750   F12, F12_H,
 751   F13, F13_H,
 752   F14, F14_H,    // nv!
 753   F15, F15_H,    // nv!
 754   F16, F16_H,    // nv!
 755   F17, F17_H,    // nv!
 756   F18, F18_H,    // nv!
 757   F19, F19_H,    // nv!
 758   F20, F20_H,    // nv!
 759   F21, F21_H,    // nv!
 760   F22, F22_H,    // nv!
 761   F23, F23_H,    // nv!
 762   F24, F24_H,    // nv!
 763   F25, F25_H,    // nv!
 764   F26, F26_H,    // nv!
 765   F27, F27_H,    // nv!
 766   F28, F28_H,    // nv!
 767   F29, F29_H,    // nv!
 768   F30, F30_H,    // nv!
 769   F31, F31_H     // nv!
 770 );
 771 
 772  %}
 773 
 774 //----------DEFINITION BLOCK---------------------------------------------------
 775 // Define name --> value mappings to inform the ADLC of an integer valued name
 776 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 777 // Format:
 778 //        int_def  <name>         ( <int_value>, <expression>);
 779 // Generated Code in ad_<arch>.hpp
 780 //        #define  <name>   (<expression>)
 781 //        // value == <int_value>
 782 // Generated code in ad_<arch>.cpp adlc_verification()
 783 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 784 //
 785 definitions %{
 786   // The default cost (of an ALU instruction).
 787   int_def DEFAULT_COST_LOW        (     30,      30);
 788   int_def DEFAULT_COST            (    100,     100);
 789   int_def HUGE_COST               (1000000, 1000000);
 790 
 791   // Memory refs
 792   int_def MEMORY_REF_COST_LOW     (    200, DEFAULT_COST * 2);
 793   int_def MEMORY_REF_COST         (    300, DEFAULT_COST * 3);
 794 
 795   // Branches are even more expensive.
 796   int_def BRANCH_COST             (    900, DEFAULT_COST * 9);
 797   int_def CALL_COST               (   1300, DEFAULT_COST * 13);
 798 %}
 799 
 800 
 801 //----------SOURCE BLOCK-------------------------------------------------------
 802 // This is a block of C++ code which provides values, functions, and
 803 // definitions necessary in the rest of the architecture description.
 804 source_hpp %{
 805   // Header information of the source block.
 806   // Method declarations/definitions which are used outside
 807   // the ad-scope can conveniently be defined here.
 808   //
 809   // To keep related declarations/definitions/uses close together,
 810   // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 811 
 812   // Returns true if Node n is followed by a MemBar node that
 813   // will do an acquire. If so, this node must not do the acquire
 814   // operation.
 815   bool followed_by_acquire(const Node *n);
 816 %}
 817 
 818 source %{
 819 
 820 // Should the Matcher clone shifts on addressing modes, expecting them
 821 // to be subsumed into complex addressing expressions or compute them
 822 // into registers?
 823 bool Matcher::clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 824   return clone_base_plus_offset_address(m, mstack, address_visited);
 825 }
 826 
 827 void Compile::reshape_address(AddPNode* addp) {
 828 }
 829 
 830 // Optimize load-acquire.
 831 //
 832 // Check if acquire is unnecessary due to following operation that does
 833 // acquire anyways.
 834 // Walk the pattern:
 835 //
 836 //      n: Load.acq
 837 //           |
 838 //      MemBarAcquire
 839 //       |         |
 840 //  Proj(ctrl)  Proj(mem)
 841 //       |         |
 842 //   MemBarRelease/Volatile
 843 //
 844 bool followed_by_acquire(const Node *load) {
 845   assert(load->is_Load(), "So far implemented only for loads.");
 846 
 847   // Find MemBarAcquire.
 848   const Node *mba = NULL;
 849   for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) {
 850     const Node *out = load->fast_out(i);
 851     if (out->Opcode() == Op_MemBarAcquire) {
 852       if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge.
 853       mba = out;
 854       break;
 855     }
 856   }
 857   if (!mba) return false;
 858 
 859   // Find following MemBar node.
 860   //
 861   // The following node must be reachable by control AND memory
 862   // edge to assure no other operations are in between the two nodes.
 863   //
 864   // So first get the Proj node, mem_proj, to use it to iterate forward.
 865   Node *mem_proj = NULL;
 866   for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) {
 867     mem_proj = mba->fast_out(i);      // Throw out-of-bounds if proj not found
 868     assert(mem_proj->is_Proj(), "only projections here");
 869     ProjNode *proj = mem_proj->as_Proj();
 870     if (proj->_con == TypeFunc::Memory &&
 871         !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only
 872       break;
 873   }
 874   assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken");
 875 
 876   // Search MemBar behind Proj. If there are other memory operations
 877   // behind the Proj we lost.
 878   for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) {
 879     Node *x = mem_proj->fast_out(j);
 880     // Proj might have an edge to a store or load node which precedes the membar.
 881     if (x->is_Mem()) return false;
 882 
 883     // On PPC64 release and volatile are implemented by an instruction
 884     // that also has acquire semantics. I.e. there is no need for an
 885     // acquire before these.
 886     int xop = x->Opcode();
 887     if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) {
 888       // Make sure we're not missing Call/Phi/MergeMem by checking
 889       // control edges. The control edge must directly lead back
 890       // to the MemBarAcquire
 891       Node *ctrl_proj = x->in(0);
 892       if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) {
 893         return true;
 894       }
 895     }
 896   }
 897 
 898   return false;
 899 }
 900 
 901 #define __ _masm.
 902 
 903 // Tertiary op of a LoadP or StoreP encoding.
 904 #define REGP_OP true
 905 
 906 // ****************************************************************************
 907 
 908 // REQUIRED FUNCTIONALITY
 909 
 910 // !!!!! Special hack to get all type of calls to specify the byte offset
 911 //       from the start of the call to the point where the return address
 912 //       will point.
 913 
 914 // PPC port: Removed use of lazy constant construct.
 915 
 916 int MachCallStaticJavaNode::ret_addr_offset() {
 917   // It's only a single branch-and-link instruction.
 918   return 4;
 919 }
 920 
 921 int MachCallDynamicJavaNode::ret_addr_offset() {
 922   // Offset is 4 with postalloc expanded calls (bl is one instruction). We use
 923   // postalloc expanded calls if we use inline caches and do not update method data.
 924   if (UseInlineCaches)
 925     return 4;
 926 
 927   int vtable_index = this->_vtable_index;
 928   if (vtable_index < 0) {
 929     // Must be invalid_vtable_index, not nonvirtual_vtable_index.
 930     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 931     return 12;
 932   } else {
 933     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 934     return 24;
 935   }
 936 }
 937 
 938 int MachCallRuntimeNode::ret_addr_offset() {
 939 #if defined(ABI_ELFv2)
 940   return 28;
 941 #else
 942   return 40;
 943 #endif
 944 }
 945 
 946 //=============================================================================
 947 
 948 // condition code conversions
 949 
 950 static int cc_to_boint(int cc) {
 951   return Assembler::bcondCRbiIs0 | (cc & 8);
 952 }
 953 
 954 static int cc_to_inverse_boint(int cc) {
 955   return Assembler::bcondCRbiIs0 | (8-(cc & 8));
 956 }
 957 
 958 static int cc_to_biint(int cc, int flags_reg) {
 959   return (flags_reg << 2) | (cc & 3);
 960 }
 961 
 962 //=============================================================================
 963 
 964 // Compute padding required for nodes which need alignment. The padding
 965 // is the number of bytes (not instructions) which will be inserted before
 966 // the instruction. The padding must match the size of a NOP instruction.
 967 
 968 // Currently not used on this platform.
 969 
 970 //=============================================================================
 971 
 972 // Indicate if the safepoint node needs the polling page as an input.
 973 bool SafePointNode::needs_polling_address_input() {
 974   // The address is loaded from thread by a seperate node.
 975   return true;
 976 }
 977 
 978 //=============================================================================
 979 
 980 // Emit an interrupt that is caught by the debugger (for debugging compiler).
 981 void emit_break(CodeBuffer &cbuf) {
 982   MacroAssembler _masm(&cbuf);
 983   __ illtrap();
 984 }
 985 
 986 #ifndef PRODUCT
 987 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
 988   st->print("BREAKPOINT");
 989 }
 990 #endif
 991 
 992 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 993   emit_break(cbuf);
 994 }
 995 
 996 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 997   return MachNode::size(ra_);
 998 }
 999 
1000 //=============================================================================
1001 
1002 void emit_nop(CodeBuffer &cbuf) {
1003   MacroAssembler _masm(&cbuf);
1004   __ nop();
1005 }
1006 
1007 static inline void emit_long(CodeBuffer &cbuf, int value) {
1008   *((int*)(cbuf.insts_end())) = value;
1009   cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord);
1010 }
1011 
1012 //=============================================================================
1013 
1014 %} // interrupt source
1015 
1016 source_hpp %{ // Header information of the source block.
1017 
1018 //--------------------------------------------------------------
1019 //---<  Used for optimization in Compile::Shorten_branches  >---
1020 //--------------------------------------------------------------
1021 
1022 class CallStubImpl {
1023 
1024  public:
1025 
1026   // Emit call stub, compiled java to interpreter.
1027   static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset);
1028 
1029   // Size of call trampoline stub.
1030   // This doesn't need to be accurate to the byte, but it
1031   // must be larger than or equal to the real size of the stub.
1032   static uint size_call_trampoline() {
1033     return MacroAssembler::trampoline_stub_size;
1034   }
1035 
1036   // number of relocations needed by a call trampoline stub
1037   static uint reloc_call_trampoline() {
1038     return 5;
1039   }
1040 
1041 };
1042 
1043 %} // end source_hpp
1044 
1045 source %{
1046 
1047 // Emit a trampoline stub for a call to a target which is too far away.
1048 //
1049 // code sequences:
1050 //
1051 // call-site:
1052 //   branch-and-link to <destination> or <trampoline stub>
1053 //
1054 // Related trampoline stub for this call-site in the stub section:
1055 //   load the call target from the constant pool
1056 //   branch via CTR (LR/link still points to the call-site above)
1057 
1058 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) {
1059   address stub = __ emit_trampoline_stub(destination_toc_offset, insts_call_instruction_offset);
1060   if (stub == NULL) {
1061     ciEnv::current()->record_out_of_memory_failure();
1062   }
1063 }
1064 
1065 //=============================================================================
1066 
1067 // Emit an inline branch-and-link call and a related trampoline stub.
1068 //
1069 // code sequences:
1070 //
1071 // call-site:
1072 //   branch-and-link to <destination> or <trampoline stub>
1073 //
1074 // Related trampoline stub for this call-site in the stub section:
1075 //   load the call target from the constant pool
1076 //   branch via CTR (LR/link still points to the call-site above)
1077 //
1078 
1079 typedef struct {
1080   int insts_call_instruction_offset;
1081   int ret_addr_offset;
1082 } EmitCallOffsets;
1083 
1084 // Emit a branch-and-link instruction that branches to a trampoline.
1085 // - Remember the offset of the branch-and-link instruction.
1086 // - Add a relocation at the branch-and-link instruction.
1087 // - Emit a branch-and-link.
1088 // - Remember the return pc offset.
1089 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) {
1090   EmitCallOffsets offsets = { -1, -1 };
1091   const int start_offset = __ offset();
1092   offsets.insts_call_instruction_offset = __ offset();
1093 
1094   // No entry point given, use the current pc.
1095   if (entry_point == NULL) entry_point = __ pc();
1096 
1097   // Put the entry point as a constant into the constant pool.
1098   const address entry_point_toc_addr   = __ address_constant(entry_point, RelocationHolder::none);
1099   if (entry_point_toc_addr == NULL) {
1100     ciEnv::current()->record_out_of_memory_failure();
1101     return offsets;
1102   }
1103   const int     entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
1104   
1105   // Emit the trampoline stub which will be related to the branch-and-link below.
1106   CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset);
1107   if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full.
1108   __ relocate(rtype);
1109   
1110   // Note: At this point we do not have the address of the trampoline
1111   // stub, and the entry point might be too far away for bl, so __ pc()
1112   // serves as dummy and the bl will be patched later.
1113   __ bl((address) __ pc());
1114 
1115   offsets.ret_addr_offset = __ offset() - start_offset;
1116 
1117   return offsets;
1118 }
1119 
1120 //=============================================================================
1121 
1122 // Factory for creating loadConL* nodes for large/small constant pool.
1123 
1124 static inline jlong replicate_immF(float con) {
1125   // Replicate float con 2 times and pack into vector.
1126   int val = *((int*)&con);
1127   jlong lval = val;
1128   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
1129   return lval;
1130 }
1131 
1132 //=============================================================================
1133 
1134 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask();
1135 int Compile::ConstantTable::calculate_table_base_offset() const {
1136   return 0;  // absolute addressing, no offset
1137 }
1138 
1139 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; }
1140 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1141   iRegPdstOper *op_dst = new iRegPdstOper();
1142   MachNode *m1 = new loadToc_hiNode();
1143   MachNode *m2 = new loadToc_loNode();
1144 
1145   m1->add_req(NULL);
1146   m2->add_req(NULL, m1);
1147   m1->_opnds[0] = op_dst;
1148   m2->_opnds[0] = op_dst;
1149   m2->_opnds[1] = op_dst;
1150   ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1151   ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
1152   nodes->push(m1);
1153   nodes->push(m2);
1154 }
1155 
1156 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1157   // Is postalloc expanded.
1158   ShouldNotReachHere();
1159 }
1160 
1161 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
1162   return 0;
1163 }
1164 
1165 #ifndef PRODUCT
1166 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1167   st->print("-- \t// MachConstantBaseNode (empty encoding)");
1168 }
1169 #endif
1170 
1171 //=============================================================================
1172 
1173 #ifndef PRODUCT
1174 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1175   Compile* C = ra_->C;
1176   const long framesize = C->frame_slots() << LogBytesPerInt;
1177 
1178   st->print("PROLOG\n\t");
1179   if (C->need_stack_bang(framesize)) {
1180     st->print("stack_overflow_check\n\t");
1181   }
1182 
1183   if (!false /* TODO: PPC port C->is_frameless_method()*/) {
1184     st->print("save return pc\n\t");
1185     st->print("push frame %ld\n\t", -framesize);
1186   }
1187 }
1188 #endif
1189 
1190 // Macro used instead of the common __ to emulate the pipes of PPC.
1191 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the
1192 // micro scheduler to cope with "hand written" assembler like in the prolog. Though
1193 // still no scheduling of this code is possible, the micro scheduler is aware of the
1194 // code and can update its internal data. The following mechanism is used to achieve this:
1195 // The micro scheduler calls size() of each compound node during scheduling. size() does a
1196 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL.
1197 #if 0 // TODO: PPC port
1198 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1199                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \
1200                 _masm.
1201 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling())                    \
1202                   C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none)
1203 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling())                 \
1204                   C->hb_scheduling()->_pdScheduling->advance_offset
1205 #else
1206 #define ___(op) if (UsePower6SchedulerPPC64)                                          \
1207                   Unimplemented();                                                    \
1208                 _masm.
1209 #define ___stop if (UsePower6SchedulerPPC64)                                          \
1210                   Unimplemented()
1211 #define ___advance if (UsePower6SchedulerPPC64)                                       \
1212                   Unimplemented()
1213 #endif
1214 
1215 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1216   Compile* C = ra_->C;
1217   MacroAssembler _masm(&cbuf);
1218 
1219   const long framesize = C->frame_size_in_bytes();
1220   assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment");
1221 
1222   const bool method_is_frameless      = false /* TODO: PPC port C->is_frameless_method()*/;
1223 
1224   const Register return_pc            = R20; // Must match return_addr() in frame section.
1225   const Register callers_sp           = R21;
1226   const Register push_frame_temp      = R22;
1227   const Register toc_temp             = R23;
1228   assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp);
1229 
1230   if (method_is_frameless) {
1231     // Add nop at beginning of all frameless methods to prevent any
1232     // oop instructions from getting overwritten by make_not_entrant
1233     // (patching attempt would fail).
1234     ___(nop) nop();
1235   } else {
1236     // Get return pc.
1237     ___(mflr) mflr(return_pc);
1238   }
1239 
1240   // Calls to C2R adapters often do not accept exceptional returns.
1241   // We require that their callers must bang for them. But be
1242   // careful, because some VM calls (such as call site linkage) can
1243   // use several kilobytes of stack. But the stack safety zone should
1244   // account for that. See bugs 4446381, 4468289, 4497237.
1245 
1246   int bangsize = C->bang_size_in_bytes();
1247   assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect");
1248   if (C->need_stack_bang(bangsize) && UseStackBanging) {
1249     // Unfortunately we cannot use the function provided in
1250     // assembler.cpp as we have to emulate the pipes. So I had to
1251     // insert the code of generate_stack_overflow_check(), see
1252     // assembler.cpp for some illuminative comments.
1253     const int page_size = os::vm_page_size();
1254     int bang_end = JavaThread::stack_shadow_zone_size();
1255 
1256     // This is how far the previous frame's stack banging extended.
1257     const int bang_end_safe = bang_end;
1258 
1259     if (bangsize > page_size) {
1260       bang_end += bangsize;
1261     }
1262 
1263     int bang_offset = bang_end_safe;
1264 
1265     while (bang_offset <= bang_end) {
1266       // Need at least one stack bang at end of shadow zone.
1267 
1268       // Again I had to copy code, this time from assembler_ppc.cpp,
1269       // bang_stack_with_offset - see there for comments.
1270 
1271       // Stack grows down, caller passes positive offset.
1272       assert(bang_offset > 0, "must bang with positive offset");
1273 
1274       long stdoffset = -bang_offset;
1275 
1276       if (Assembler::is_simm(stdoffset, 16)) {
1277         // Signed 16 bit offset, a simple std is ok.
1278         if (UseLoadInstructionsForStackBangingPPC64) {
1279           ___(ld) ld(R0,  (int)(signed short)stdoffset, R1_SP);
1280         } else {
1281           ___(std) std(R0, (int)(signed short)stdoffset, R1_SP);
1282         }
1283       } else if (Assembler::is_simm(stdoffset, 31)) {
1284         // Use largeoffset calculations for addis & ld/std.
1285         const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset);
1286         const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset);
1287 
1288         Register tmp = R11;
1289         ___(addis) addis(tmp, R1_SP, hi);
1290         if (UseLoadInstructionsForStackBangingPPC64) {
1291           ___(ld) ld(R0, lo, tmp);
1292         } else {
1293           ___(std) std(R0, lo, tmp);
1294         }
1295       } else {
1296         ShouldNotReachHere();
1297       }
1298 
1299       bang_offset += page_size;
1300     }
1301     // R11 trashed
1302   } // C->need_stack_bang(framesize) && UseStackBanging
1303 
1304   unsigned int bytes = (unsigned int)framesize;
1305   long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes);
1306   ciMethod *currMethod = C->method();
1307 
1308   // Optimized version for most common case.
1309   if (UsePower6SchedulerPPC64 &&
1310       !method_is_frameless && Assembler::is_simm((int)(-offset), 16) &&
1311       !(false /* ConstantsALot TODO: PPC port*/)) {
1312     ___(or) mr(callers_sp, R1_SP);
1313     ___(std) std(return_pc, _abi(lr), R1_SP);
1314     ___(stdu) stdu(R1_SP, -offset, R1_SP);
1315     return;
1316   }
1317 
1318   if (!method_is_frameless) {
1319     // Get callers sp.
1320     ___(or) mr(callers_sp, R1_SP);
1321 
1322     // Push method's frame, modifies SP.
1323     assert(Assembler::is_uimm(framesize, 32U), "wrong type");
1324     // The ABI is already accounted for in 'framesize' via the
1325     // 'out_preserve' area.
1326     Register tmp = push_frame_temp;
1327     // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp).
1328     if (Assembler::is_simm(-offset, 16)) {
1329       ___(stdu) stdu(R1_SP, -offset, R1_SP);
1330     } else {
1331       long x = -offset;
1332       // Had to insert load_const(tmp, -offset).
1333       ___(addis)  lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16)));
1334       ___(ori)    ori( tmp, tmp, ((x >> 32) & 0x0000ffff));
1335       ___(rldicr) sldi(tmp, tmp, 32);
1336       ___(oris)   oris(tmp, tmp, (x & 0xffff0000) >> 16);
1337       ___(ori)    ori( tmp, tmp, (x & 0x0000ffff));
1338 
1339       ___(stdux) stdux(R1_SP, R1_SP, tmp);
1340     }
1341   }
1342 #if 0 // TODO: PPC port
1343   // For testing large constant pools, emit a lot of constants to constant pool.
1344   // "Randomize" const_size.
1345   if (ConstantsALot) {
1346     const int num_consts = const_size();
1347     for (int i = 0; i < num_consts; i++) {
1348       __ long_constant(0xB0B5B00BBABE);
1349     }
1350   }
1351 #endif
1352   if (!method_is_frameless) {
1353     // Save return pc.
1354     ___(std) std(return_pc, _abi(lr), callers_sp);
1355   }
1356   
1357   C->set_frame_complete(cbuf.insts_size());
1358 }
1359 #undef ___
1360 #undef ___stop
1361 #undef ___advance
1362 
1363 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1364   // Variable size. determine dynamically.
1365   return MachNode::size(ra_);
1366 }
1367 
1368 int MachPrologNode::reloc() const {
1369   // Return number of relocatable values contained in this instruction.
1370   return 1; // 1 reloc entry for load_const(toc).
1371 }
1372 
1373 //=============================================================================
1374 
1375 #ifndef PRODUCT
1376 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1377   Compile* C = ra_->C;
1378 
1379   st->print("EPILOG\n\t");
1380   st->print("restore return pc\n\t");
1381   st->print("pop frame\n\t");
1382 
1383   if (do_polling() && C->is_method_compilation()) {
1384     st->print("touch polling page\n\t");
1385   }
1386 }
1387 #endif
1388 
1389 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1390   Compile* C = ra_->C;
1391   MacroAssembler _masm(&cbuf);
1392 
1393   const long framesize = ((long)C->frame_slots()) << LogBytesPerInt;
1394   assert(framesize >= 0, "negative frame-size?");
1395 
1396   const bool method_needs_polling = do_polling() && C->is_method_compilation();
1397   const bool method_is_frameless  = false /* TODO: PPC port C->is_frameless_method()*/;
1398   const Register return_pc        = R31;  // Must survive C-call to enable_stack_reserved_zone().
1399   const Register polling_page     = R12;
1400 
1401   if (!method_is_frameless) {
1402     // Restore return pc relative to callers' sp.
1403     __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP);
1404   }
1405 
1406   if (method_needs_polling) {
1407     if (LoadPollAddressFromThread) {
1408       // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1409       Unimplemented();
1410     } else {
1411       __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page()
1412     }
1413   }
1414 
1415   if (!method_is_frameless) {
1416     // Move return pc to LR.
1417     __ mtlr(return_pc);
1418     // Pop frame (fixed frame-size).
1419     __ addi(R1_SP, R1_SP, (int)framesize);
1420   }
1421 
1422   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1423     __ reserved_stack_check(return_pc);
1424   }
1425 
1426   if (method_needs_polling) {
1427     // We need to mark the code position where the load from the safepoint
1428     // polling page was emitted as relocInfo::poll_return_type here.
1429     __ relocate(relocInfo::poll_return_type);
1430     __ load_from_polling_page(polling_page);
1431   }
1432 }
1433 
1434 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1435   // Variable size. Determine dynamically.
1436   return MachNode::size(ra_);
1437 }
1438 
1439 int MachEpilogNode::reloc() const {
1440   // Return number of relocatable values contained in this instruction.
1441   return 1; // 1 for load_from_polling_page.
1442 }
1443 
1444 const Pipeline * MachEpilogNode::pipeline() const {
1445   return MachNode::pipeline_class();
1446 }
1447 
1448 // This method seems to be obsolete. It is declared in machnode.hpp
1449 // and defined in all *.ad files, but it is never called. Should we
1450 // get rid of it?
1451 int MachEpilogNode::safepoint_offset() const {
1452   assert(do_polling(), "no return for this epilog node");
1453   return 0;
1454 }
1455 
1456 #if 0 // TODO: PPC port
1457 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1458   MacroAssembler _masm(&cbuf);
1459   if (LoadPollAddressFromThread) {
1460     _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread);
1461   } else {
1462     _masm.nop();
1463   }
1464 }
1465 
1466 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const {
1467   if (LoadPollAddressFromThread) {
1468     return 4;
1469   } else {
1470     return 4;
1471   }
1472 }
1473 
1474 #ifndef PRODUCT
1475 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1476   st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread");
1477 }
1478 #endif
1479 
1480 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const {
1481   return RSCRATCH1_BITS64_REG_mask();
1482 }
1483 #endif // PPC port
1484 
1485 // =============================================================================
1486 
1487 // Figure out which register class each belongs in: rc_int, rc_float or
1488 // rc_stack.
1489 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1490 
1491 static enum RC rc_class(OptoReg::Name reg) {
1492   // Return the register class for the given register. The given register
1493   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
1494   // enumeration in adGlobals_ppc.hpp.
1495 
1496   if (reg == OptoReg::Bad) return rc_bad;
1497 
1498   // We have 64 integer register halves, starting at index 0.
1499   if (reg < 64) return rc_int;
1500 
1501   // We have 64 floating-point register halves, starting at index 64.
1502   if (reg < 64+64) return rc_float;
1503 
1504   // Between float regs & stack are the flags regs.
1505   assert(OptoReg::is_stack(reg), "blow up if spilling flags");
1506 
1507   return rc_stack;
1508 }
1509 
1510 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset,
1511                         bool do_print, Compile* C, outputStream *st) {
1512 
1513   assert(opcode == Assembler::LD_OPCODE   ||
1514          opcode == Assembler::STD_OPCODE  ||
1515          opcode == Assembler::LWZ_OPCODE  ||
1516          opcode == Assembler::STW_OPCODE  ||
1517          opcode == Assembler::LFD_OPCODE  ||
1518          opcode == Assembler::STFD_OPCODE ||
1519          opcode == Assembler::LFS_OPCODE  ||
1520          opcode == Assembler::STFS_OPCODE,
1521          "opcode not supported");
1522 
1523   if (cbuf) {
1524     int d =
1525       (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ?
1526         Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/)
1527       : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build.
1528     emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP));
1529   }
1530 #ifndef PRODUCT
1531   else if (do_print) {
1532     st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy",
1533               op_str,
1534               Matcher::regName[reg],
1535               offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/);
1536   }
1537 #endif
1538   return 4; // size
1539 }
1540 
1541 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const {
1542   Compile* C = ra_->C;
1543 
1544   // Get registers to move.
1545   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
1546   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
1547   OptoReg::Name dst_hi = ra_->get_reg_second(this);
1548   OptoReg::Name dst_lo = ra_->get_reg_first(this);
1549 
1550   enum RC src_hi_rc = rc_class(src_hi);
1551   enum RC src_lo_rc = rc_class(src_lo);
1552   enum RC dst_hi_rc = rc_class(dst_hi);
1553   enum RC dst_lo_rc = rc_class(dst_lo);
1554 
1555   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
1556   if (src_hi != OptoReg::Bad)
1557     assert((src_lo&1)==0 && src_lo+1==src_hi &&
1558            (dst_lo&1)==0 && dst_lo+1==dst_hi,
1559            "expected aligned-adjacent pairs");
1560   // Generate spill code!
1561   int size = 0;
1562 
1563   if (src_lo == dst_lo && src_hi == dst_hi)
1564     return size;            // Self copy, no move.
1565 
1566   // --------------------------------------
1567   // Memory->Memory Spill. Use R0 to hold the value.
1568   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1569     int src_offset = ra_->reg2offset(src_lo);
1570     int dst_offset = ra_->reg2offset(dst_lo);
1571     if (src_hi != OptoReg::Bad) {
1572       assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack,
1573              "expected same type of move for high parts");
1574       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE,  R0_num, src_offset, !do_size, C, st);
1575       if (!cbuf && !do_size) st->print("\n\t");
1576       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st);
1577     } else {
1578       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st);
1579       if (!cbuf && !do_size) st->print("\n\t");
1580       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st);
1581     }
1582     return size;
1583   }
1584 
1585   // --------------------------------------
1586   // Check for float->int copy; requires a trip through memory.
1587   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1588     Unimplemented();
1589   }
1590 
1591   // --------------------------------------
1592   // Check for integer reg-reg copy.
1593   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1594       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1595       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1596       size = (Rsrc != Rdst) ? 4 : 0;
1597 
1598       if (cbuf) {
1599         MacroAssembler _masm(cbuf);
1600         if (size) {
1601           __ mr(Rdst, Rsrc);
1602         }
1603       }
1604 #ifndef PRODUCT
1605       else if (!do_size) {
1606         if (size) {
1607           st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1608         } else {
1609           st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1610         }
1611       }
1612 #endif
1613       return size;
1614   }
1615 
1616   // Check for integer store.
1617   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1618     int dst_offset = ra_->reg2offset(dst_lo);
1619     if (src_hi != OptoReg::Bad) {
1620       assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack,
1621              "expected same type of move for high parts");
1622       size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1623     } else {
1624       size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st);
1625     }
1626     return size;
1627   }
1628 
1629   // Check for integer load.
1630   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1631     int src_offset = ra_->reg2offset(src_lo);
1632     if (src_hi != OptoReg::Bad) {
1633       assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack,
1634              "expected same type of move for high parts");
1635       size += ld_st_helper(cbuf, "LD  ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1636     } else {
1637       size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st);
1638     }
1639     return size;
1640   }
1641 
1642   // Check for float reg-reg copy.
1643   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1644     if (cbuf) {
1645       MacroAssembler _masm(cbuf);
1646       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
1647       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
1648       __ fmr(Rdst, Rsrc);
1649     }
1650 #ifndef PRODUCT
1651     else if (!do_size) {
1652       st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
1653     }
1654 #endif
1655     return 4;
1656   }
1657 
1658   // Check for float store.
1659   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1660     int dst_offset = ra_->reg2offset(dst_lo);
1661     if (src_hi != OptoReg::Bad) {
1662       assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack,
1663              "expected same type of move for high parts");
1664       size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st);
1665     } else {
1666       size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st);
1667     }
1668     return size;
1669   }
1670 
1671   // Check for float load.
1672   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1673     int src_offset = ra_->reg2offset(src_lo);
1674     if (src_hi != OptoReg::Bad) {
1675       assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack,
1676              "expected same type of move for high parts");
1677       size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st);
1678     } else {
1679       size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st);
1680     }
1681     return size;
1682   }
1683 
1684   // --------------------------------------------------------------------
1685   // Check for hi bits still needing moving. Only happens for misaligned
1686   // arguments to native calls.
1687   if (src_hi == dst_hi)
1688     return size;               // Self copy; no move.
1689 
1690   assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
1691   ShouldNotReachHere(); // Unimplemented
1692   return 0;
1693 }
1694 
1695 #ifndef PRODUCT
1696 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1697   if (!ra_)
1698     st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx);
1699   else
1700     implementation(NULL, ra_, false, st);
1701 }
1702 #endif
1703 
1704 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1705   implementation(&cbuf, ra_, false, NULL);
1706 }
1707 
1708 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1709   return implementation(NULL, ra_, true, NULL);
1710 }
1711 
1712 #if 0 // TODO: PPC port
1713 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) {
1714 #ifndef PRODUCT
1715   if (ra_->node_regs_max_index() == 0) return archOpcode_undefined;
1716 #endif
1717   assert(ra_->node_regs_max_index() != 0, "");
1718 
1719   // Get registers to move.
1720   OptoReg::Name src_hi = ra_->get_reg_second(n->in(1));
1721   OptoReg::Name src_lo = ra_->get_reg_first(n->in(1));
1722   OptoReg::Name dst_hi = ra_->get_reg_second(n);
1723   OptoReg::Name dst_lo = ra_->get_reg_first(n);
1724 
1725   enum RC src_lo_rc = rc_class(src_lo);
1726   enum RC dst_lo_rc = rc_class(dst_lo);
1727 
1728   if (src_lo == dst_lo && src_hi == dst_hi)
1729     return ppc64Opcode_none;            // Self copy, no move.
1730 
1731   // --------------------------------------
1732   // Memory->Memory Spill. Use R0 to hold the value.
1733   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
1734     return ppc64Opcode_compound;
1735   }
1736 
1737   // --------------------------------------
1738   // Check for float->int copy; requires a trip through memory.
1739   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
1740     Unimplemented();
1741   }
1742 
1743   // --------------------------------------
1744   // Check for integer reg-reg copy.
1745   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
1746     Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
1747     Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
1748     if (Rsrc == Rdst) {
1749       return ppc64Opcode_none;
1750     } else {
1751       return ppc64Opcode_or;
1752     }
1753   }
1754 
1755   // Check for integer store.
1756   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
1757     if (src_hi != OptoReg::Bad) {
1758       return ppc64Opcode_std;
1759     } else {
1760       return ppc64Opcode_stw;
1761     }
1762   }
1763 
1764   // Check for integer load.
1765   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
1766     if (src_hi != OptoReg::Bad) {
1767       return ppc64Opcode_ld;
1768     } else {
1769       return ppc64Opcode_lwz;
1770     }
1771   }
1772 
1773   // Check for float reg-reg copy.
1774   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
1775     return ppc64Opcode_fmr;
1776   }
1777 
1778   // Check for float store.
1779   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
1780     if (src_hi != OptoReg::Bad) {
1781       return ppc64Opcode_stfd;
1782     } else {
1783       return ppc64Opcode_stfs;
1784     }
1785   }
1786 
1787   // Check for float load.
1788   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
1789     if (src_hi != OptoReg::Bad) {
1790       return ppc64Opcode_lfd;
1791     } else {
1792       return ppc64Opcode_lfs;
1793     }
1794   }
1795 
1796   // --------------------------------------------------------------------
1797   // Check for hi bits still needing moving. Only happens for misaligned
1798   // arguments to native calls.
1799   if (src_hi == dst_hi) {
1800     return ppc64Opcode_none;               // Self copy; no move.
1801   }
1802 
1803   ShouldNotReachHere();
1804   return ppc64Opcode_undefined;
1805 }
1806 #endif // PPC port
1807 
1808 #ifndef PRODUCT
1809 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1810   st->print("NOP \t// %d nops to pad for loops.", _count);
1811 }
1812 #endif
1813 
1814 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1815   MacroAssembler _masm(&cbuf);
1816   // _count contains the number of nops needed for padding.
1817   for (int i = 0; i < _count; i++) {
1818     __ nop();
1819   }
1820 }
1821 
1822 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1823   return _count * 4;
1824 }
1825 
1826 #ifndef PRODUCT
1827 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1828   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1829   char reg_str[128];
1830   ra_->dump_register(this, reg_str);
1831   st->print("ADDI    %s, SP, %d \t// box node", reg_str, offset);
1832 }
1833 #endif
1834 
1835 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1836   MacroAssembler _masm(&cbuf);
1837 
1838   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1839   int reg    = ra_->get_encode(this);
1840 
1841   if (Assembler::is_simm(offset, 16)) {
1842     __ addi(as_Register(reg), R1, offset);
1843   } else {
1844     ShouldNotReachHere();
1845   }
1846 }
1847 
1848 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1849   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_).
1850   return 4;
1851 }
1852 
1853 #ifndef PRODUCT
1854 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
1855   st->print_cr("---- MachUEPNode ----");
1856   st->print_cr("...");
1857 }
1858 #endif
1859 
1860 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1861   // This is the unverified entry point.
1862   MacroAssembler _masm(&cbuf);
1863 
1864   // Inline_cache contains a klass.
1865   Register ic_klass       = as_Register(Matcher::inline_cache_reg_encode());
1866   Register receiver_klass = R12_scratch2;  // tmp
1867 
1868   assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1);
1869   assert(R11_scratch1 == R11, "need prologue scratch register");
1870 
1871   // Check for NULL argument if we don't have implicit null checks.
1872   if (!ImplicitNullChecks || !os::zero_page_read_protected()) {
1873     if (TrapBasedNullChecks) {
1874       __ trap_null_check(R3_ARG1);
1875     } else {
1876       Label valid;
1877       __ cmpdi(CCR0, R3_ARG1, 0);
1878       __ bne_predict_taken(CCR0, valid);
1879       // We have a null argument, branch to ic_miss_stub.
1880       __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1881                            relocInfo::runtime_call_type);
1882       __ bind(valid);
1883     }
1884   }
1885   // Assume argument is not NULL, load klass from receiver.
1886   __ load_klass(receiver_klass, R3_ARG1);
1887 
1888   if (TrapBasedICMissChecks) {
1889     __ trap_ic_miss_check(receiver_klass, ic_klass);
1890   } else {
1891     Label valid;
1892     __ cmpd(CCR0, receiver_klass, ic_klass);
1893     __ beq_predict_taken(CCR0, valid);
1894     // We have an unexpected klass, branch to ic_miss_stub.
1895     __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(),
1896                          relocInfo::runtime_call_type);
1897     __ bind(valid);
1898   }
1899 
1900   // Argument is valid and klass is as expected, continue.
1901 }
1902 
1903 #if 0 // TODO: PPC port
1904 // Optimize UEP code on z (save a load_const() call in main path).
1905 int MachUEPNode::ep_offset() {
1906   return 0;
1907 }
1908 #endif
1909 
1910 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1911   // Variable size. Determine dynamically.
1912   return MachNode::size(ra_);
1913 }
1914 
1915 //=============================================================================
1916 
1917 %} // interrupt source
1918 
1919 source_hpp %{ // Header information of the source block.
1920 
1921 class HandlerImpl {
1922 
1923  public:
1924 
1925   static int emit_exception_handler(CodeBuffer &cbuf);
1926   static int emit_deopt_handler(CodeBuffer& cbuf);
1927 
1928   static uint size_exception_handler() {
1929     // The exception_handler is a b64_patchable.
1930     return MacroAssembler::b64_patchable_size;
1931   }
1932 
1933   static uint size_deopt_handler() {
1934     // The deopt_handler is a bl64_patchable.
1935     return MacroAssembler::bl64_patchable_size;
1936   }
1937 
1938 };
1939 
1940 %} // end source_hpp
1941 
1942 source %{
1943 
1944 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
1945   MacroAssembler _masm(&cbuf);
1946 
1947   address base = __ start_a_stub(size_exception_handler());
1948   if (base == NULL) return 0; // CodeBuffer::expand failed
1949 
1950   int offset = __ offset();
1951   __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(),
1952                        relocInfo::runtime_call_type);
1953   assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size");
1954   __ end_a_stub();
1955 
1956   return offset;
1957 }
1958 
1959 // The deopt_handler is like the exception handler, but it calls to
1960 // the deoptimization blob instead of jumping to the exception blob.
1961 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1962   MacroAssembler _masm(&cbuf);
1963 
1964   address base = __ start_a_stub(size_deopt_handler());
1965   if (base == NULL) return 0; // CodeBuffer::expand failed
1966 
1967   int offset = __ offset();
1968   __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(),
1969                         relocInfo::runtime_call_type);
1970   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
1971   __ end_a_stub();
1972 
1973   return offset;
1974 }
1975 
1976 //=============================================================================
1977 
1978 // Use a frame slots bias for frameless methods if accessing the stack.
1979 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) {
1980   if (as_Register(reg_enc) == R1_SP) {
1981     return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes();
1982   }
1983   return 0;
1984 }
1985 
1986 const bool Matcher::match_rule_supported(int opcode) {
1987   if (!has_match_rule(opcode))
1988     return false;
1989 
1990   switch (opcode) {
1991   case Op_SqrtD:
1992     return VM_Version::has_fsqrt();
1993   case Op_CountLeadingZerosI:
1994   case Op_CountLeadingZerosL:
1995   case Op_CountTrailingZerosI:
1996   case Op_CountTrailingZerosL:
1997     if (!UseCountLeadingZerosInstructionsPPC64)
1998       return false;
1999     break;
2000 
2001   case Op_PopCountI:
2002   case Op_PopCountL:
2003     return (UsePopCountInstruction && VM_Version::has_popcntw());
2004 
2005   case Op_StrComp:
2006     return SpecialStringCompareTo;
2007   case Op_StrEquals:
2008     return SpecialStringEquals;
2009   case Op_StrIndexOf:
2010     return SpecialStringIndexOf;
2011   case Op_StrIndexOfChar:
2012     return SpecialStringIndexOf;
2013   }
2014 
2015   return true;  // Per default match rules are supported.
2016 }
2017 
2018 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
2019 
2020   // TODO
2021   // identify extra cases that we might want to provide match rules for
2022   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
2023   bool ret_value = match_rule_supported(opcode);
2024   // Add rules here.
2025 
2026   return ret_value;  // Per default match rules are supported.
2027 }
2028 
2029 const bool Matcher::has_predicated_vectors(void) {
2030   return false;
2031 }
2032 
2033 const int Matcher::float_pressure(int default_pressure_threshold) {
2034   return default_pressure_threshold;
2035 }
2036 
2037 int Matcher::regnum_to_fpu_offset(int regnum) {
2038   // No user for this method?
2039   Unimplemented();
2040   return 999;
2041 }
2042 
2043 const bool Matcher::convL2FSupported(void) {
2044   // fcfids can do the conversion (>= Power7).
2045   // fcfid + frsp showed rounding problem when result should be 0x3f800001.
2046   return VM_Version::has_fcfids(); // False means that conversion is done by runtime call.
2047 }
2048 
2049 // Vector width in bytes.
2050 const int Matcher::vector_width_in_bytes(BasicType bt) {
2051   assert(MaxVectorSize == 8, "");
2052   return 8;
2053 }
2054 
2055 // Vector ideal reg.
2056 const uint Matcher::vector_ideal_reg(int size) {
2057   assert(MaxVectorSize == 8 && size == 8, "");
2058   return Op_RegL;
2059 }
2060 
2061 const uint Matcher::vector_shift_count_ideal_reg(int size) {
2062   fatal("vector shift is not supported");
2063   return Node::NotAMachineReg;
2064 }
2065 
2066 // Limits on vector size (number of elements) loaded into vector.
2067 const int Matcher::max_vector_size(const BasicType bt) {
2068   assert(is_java_primitive(bt), "only primitive type vectors");
2069   return vector_width_in_bytes(bt)/type2aelembytes(bt);
2070 }
2071 
2072 const int Matcher::min_vector_size(const BasicType bt) {
2073   return max_vector_size(bt); // Same as max.
2074 }
2075 
2076 // PPC doesn't support misaligned vectors store/load.
2077 const bool Matcher::misaligned_vectors_ok() {
2078   return false;
2079 }
2080 
2081 // PPC AES support not yet implemented
2082 const bool Matcher::pass_original_key_for_aes() {
2083   return false;
2084 }
2085 
2086 // RETURNS: whether this branch offset is short enough that a short
2087 // branch can be used.
2088 //
2089 // If the platform does not provide any short branch variants, then
2090 // this method should return `false' for offset 0.
2091 //
2092 // `Compile::Fill_buffer' will decide on basis of this information
2093 // whether to do the pass `Compile::Shorten_branches' at all.
2094 //
2095 // And `Compile::Shorten_branches' will decide on basis of this
2096 // information whether to replace particular branch sites by short
2097 // ones.
2098 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
2099   // Is the offset within the range of a ppc64 pc relative branch?
2100   bool b;
2101 
2102   const int safety_zone = 3 * BytesPerInstWord;
2103   b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2104                          29 - 16 + 1 + 2);
2105   return b;
2106 }
2107 
2108 const bool Matcher::isSimpleConstant64(jlong value) {
2109   // Probably always true, even if a temp register is required.
2110   return true;
2111 }
2112 /* TODO: PPC port
2113 // Make a new machine dependent decode node (with its operands).
2114 MachTypeNode *Matcher::make_decode_node() {
2115   assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2116          "This method is only implemented for unscaled cOops mode so far");
2117   MachTypeNode *decode = new decodeN_unscaledNode();
2118   decode->set_opnd_array(0, new iRegPdstOper());
2119   decode->set_opnd_array(1, new iRegNsrcOper());
2120   return decode;
2121 }
2122 */
2123 
2124 // false => size gets scaled to BytesPerLong, ok.
2125 const bool Matcher::init_array_count_is_in_bytes = false;
2126 
2127 // Use conditional move (CMOVL) on Power7.
2128 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2129 
2130 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2131 // fsel doesn't accept a condition register as input, so this would be slightly different.
2132 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2133 
2134 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2135 const bool Matcher::require_postalloc_expand = true;
2136 
2137 // Do we need to mask the count passed to shift instructions or does
2138 // the cpu only look at the lower 5/6 bits anyway?
2139 // PowerPC requires masked shift counts.
2140 const bool Matcher::need_masked_shift_count = true;
2141 
2142 // This affects two different things:
2143 //  - how Decode nodes are matched
2144 //  - how ImplicitNullCheck opportunities are recognized
2145 // If true, the matcher will try to remove all Decodes and match them
2146 // (as operands) into nodes. NullChecks are not prepared to deal with
2147 // Decodes by final_graph_reshaping().
2148 // If false, final_graph_reshaping() forces the decode behind the Cmp
2149 // for a NullCheck. The matcher matches the Decode node into a register.
2150 // Implicit_null_check optimization moves the Decode along with the
2151 // memory operation back up before the NullCheck.
2152 bool Matcher::narrow_oop_use_complex_address() {
2153   // TODO: PPC port if (MatchDecodeNodes) return true;
2154   return false;
2155 }
2156 
2157 bool Matcher::narrow_klass_use_complex_address() {
2158   NOT_LP64(ShouldNotCallThis());
2159   assert(UseCompressedClassPointers, "only for compressed klass code");
2160   // TODO: PPC port if (MatchDecodeNodes) return true;
2161   return false;
2162 }
2163 
2164 bool Matcher::const_oop_prefer_decode() {
2165   // Prefer ConN+DecodeN over ConP in simple compressed oops mode.
2166   return Universe::narrow_oop_base() == NULL;
2167 }
2168 
2169 bool Matcher::const_klass_prefer_decode() {
2170   // Prefer ConNKlass+DecodeNKlass over ConP in simple compressed klass mode.
2171   return Universe::narrow_klass_base() == NULL;
2172 }
2173 
2174 // Is it better to copy float constants, or load them directly from memory?
2175 // Intel can load a float constant from a direct address, requiring no
2176 // extra registers. Most RISCs will have to materialize an address into a
2177 // register first, so they would do better to copy the constant from stack.
2178 const bool Matcher::rematerialize_float_constants = false;
2179 
2180 // If CPU can load and store mis-aligned doubles directly then no fixup is
2181 // needed. Else we split the double into 2 integer pieces and move it
2182 // piece-by-piece. Only happens when passing doubles into C code as the
2183 // Java calling convention forces doubles to be aligned.
2184 const bool Matcher::misaligned_doubles_ok = true;
2185 
2186 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2187  Unimplemented();
2188 }
2189 
2190 // Advertise here if the CPU requires explicit rounding operations
2191 // to implement the UseStrictFP mode.
2192 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2193 
2194 // Do floats take an entire double register or just half?
2195 //
2196 // A float occupies a ppc64 double register. For the allocator, a
2197 // ppc64 double register appears as a pair of float registers.
2198 bool Matcher::float_in_double() { return true; }
2199 
2200 // Do ints take an entire long register or just half?
2201 // The relevant question is how the int is callee-saved:
2202 // the whole long is written but de-opt'ing will have to extract
2203 // the relevant 32 bits.
2204 const bool Matcher::int_in_long = true;
2205 
2206 // Constants for c2c and c calling conventions.
2207 
2208 const MachRegisterNumbers iarg_reg[8] = {
2209   R3_num, R4_num, R5_num, R6_num,
2210   R7_num, R8_num, R9_num, R10_num
2211 };
2212 
2213 const MachRegisterNumbers farg_reg[13] = {
2214   F1_num, F2_num, F3_num, F4_num,
2215   F5_num, F6_num, F7_num, F8_num,
2216   F9_num, F10_num, F11_num, F12_num,
2217   F13_num
2218 };
2219 
2220 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]);
2221 
2222 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]);
2223 
2224 // Return whether or not this register is ever used as an argument. This
2225 // function is used on startup to build the trampoline stubs in generateOptoStub.
2226 // Registers not mentioned will be killed by the VM call in the trampoline, and
2227 // arguments in those registers not be available to the callee.
2228 bool Matcher::can_be_java_arg(int reg) {
2229   // We return true for all registers contained in iarg_reg[] and
2230   // farg_reg[] and their virtual halves.
2231   // We must include the virtual halves in order to get STDs and LDs
2232   // instead of STWs and LWs in the trampoline stubs.
2233 
2234   if (   reg == R3_num  || reg == R3_H_num
2235       || reg == R4_num  || reg == R4_H_num
2236       || reg == R5_num  || reg == R5_H_num
2237       || reg == R6_num  || reg == R6_H_num
2238       || reg == R7_num  || reg == R7_H_num
2239       || reg == R8_num  || reg == R8_H_num
2240       || reg == R9_num  || reg == R9_H_num
2241       || reg == R10_num || reg == R10_H_num)
2242     return true;
2243 
2244   if (   reg == F1_num  || reg == F1_H_num
2245       || reg == F2_num  || reg == F2_H_num
2246       || reg == F3_num  || reg == F3_H_num
2247       || reg == F4_num  || reg == F4_H_num
2248       || reg == F5_num  || reg == F5_H_num
2249       || reg == F6_num  || reg == F6_H_num
2250       || reg == F7_num  || reg == F7_H_num
2251       || reg == F8_num  || reg == F8_H_num
2252       || reg == F9_num  || reg == F9_H_num
2253       || reg == F10_num || reg == F10_H_num
2254       || reg == F11_num || reg == F11_H_num
2255       || reg == F12_num || reg == F12_H_num
2256       || reg == F13_num || reg == F13_H_num)
2257     return true;
2258 
2259   return false;
2260 }
2261 
2262 bool Matcher::is_spillable_arg(int reg) {
2263   return can_be_java_arg(reg);
2264 }
2265 
2266 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
2267   return false;
2268 }
2269 
2270 // Register for DIVI projection of divmodI.
2271 RegMask Matcher::divI_proj_mask() {
2272   ShouldNotReachHere();
2273   return RegMask();
2274 }
2275 
2276 // Register for MODI projection of divmodI.
2277 RegMask Matcher::modI_proj_mask() {
2278   ShouldNotReachHere();
2279   return RegMask();
2280 }
2281 
2282 // Register for DIVL projection of divmodL.
2283 RegMask Matcher::divL_proj_mask() {
2284   ShouldNotReachHere();
2285   return RegMask();
2286 }
2287 
2288 // Register for MODL projection of divmodL.
2289 RegMask Matcher::modL_proj_mask() {
2290   ShouldNotReachHere();
2291   return RegMask();
2292 }
2293 
2294 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2295   return RegMask();
2296 }
2297 
2298 const bool Matcher::convi2l_type_required = true;
2299 
2300 %}
2301 
2302 //----------ENCODING BLOCK-----------------------------------------------------
2303 // This block specifies the encoding classes used by the compiler to output
2304 // byte streams. Encoding classes are parameterized macros used by
2305 // Machine Instruction Nodes in order to generate the bit encoding of the
2306 // instruction. Operands specify their base encoding interface with the
2307 // interface keyword. There are currently supported four interfaces,
2308 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2309 // operand to generate a function which returns its register number when
2310 // queried. CONST_INTER causes an operand to generate a function which
2311 // returns the value of the constant when queried. MEMORY_INTER causes an
2312 // operand to generate four functions which return the Base Register, the
2313 // Index Register, the Scale Value, and the Offset Value of the operand when
2314 // queried. COND_INTER causes an operand to generate six functions which
2315 // return the encoding code (ie - encoding bits for the instruction)
2316 // associated with each basic boolean condition for a conditional instruction.
2317 //
2318 // Instructions specify two basic values for encoding. Again, a function
2319 // is available to check if the constant displacement is an oop. They use the
2320 // ins_encode keyword to specify their encoding classes (which must be
2321 // a sequence of enc_class names, and their parameters, specified in
2322 // the encoding block), and they use the
2323 // opcode keyword to specify, in order, their primary, secondary, and
2324 // tertiary opcode. Only the opcode sections which a particular instruction
2325 // needs for encoding need to be specified.
2326 encode %{
2327   enc_class enc_unimplemented %{
2328     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2329     MacroAssembler _masm(&cbuf);
2330     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
2331   %}
2332 
2333   enc_class enc_untested %{
2334 #ifdef ASSERT
2335     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2336     MacroAssembler _masm(&cbuf);
2337     __ untested("Untested mach node encoding in AD file.");
2338 #else
2339     // TODO: PPC port $archOpcode(ppc64Opcode_none);
2340 #endif
2341   %}
2342 
2343   enc_class enc_lbz(iRegIdst dst, memory mem) %{
2344     // TODO: PPC port $archOpcode(ppc64Opcode_lbz);
2345     MacroAssembler _masm(&cbuf);
2346     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2347     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2348   %}
2349 
2350   // Load acquire.
2351   enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{
2352     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2353     MacroAssembler _masm(&cbuf);
2354     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2355     __ lbz($dst$$Register, Idisp, $mem$$base$$Register);
2356     __ twi_0($dst$$Register);
2357     __ isync();
2358   %}
2359 
2360   enc_class enc_lhz(iRegIdst dst, memory mem) %{
2361     // TODO: PPC port $archOpcode(ppc64Opcode_lhz);
2362 
2363     MacroAssembler _masm(&cbuf);
2364     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2365     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2366   %}
2367 
2368   // Load acquire.
2369   enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{
2370     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2371 
2372     MacroAssembler _masm(&cbuf);
2373     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2374     __ lhz($dst$$Register, Idisp, $mem$$base$$Register);
2375     __ twi_0($dst$$Register);
2376     __ isync();
2377   %}
2378 
2379   enc_class enc_lwz(iRegIdst dst, memory mem) %{
2380     // TODO: PPC port $archOpcode(ppc64Opcode_lwz);
2381 
2382     MacroAssembler _masm(&cbuf);
2383     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2384     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2385   %}
2386 
2387   // Load acquire.
2388   enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{
2389     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2390 
2391     MacroAssembler _masm(&cbuf);
2392     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2393     __ lwz($dst$$Register, Idisp, $mem$$base$$Register);
2394     __ twi_0($dst$$Register);
2395     __ isync();
2396   %}
2397 
2398   enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{
2399     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2400     MacroAssembler _masm(&cbuf);
2401     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2402     // Operand 'ds' requires 4-alignment.
2403     assert((Idisp & 0x3) == 0, "unaligned offset");
2404     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2405   %}
2406 
2407   // Load acquire.
2408   enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{
2409     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2410     MacroAssembler _masm(&cbuf);
2411     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2412     // Operand 'ds' requires 4-alignment.
2413     assert((Idisp & 0x3) == 0, "unaligned offset");
2414     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
2415     __ twi_0($dst$$Register);
2416     __ isync();
2417   %}
2418 
2419   enc_class enc_lfd(RegF dst, memory mem) %{
2420     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
2421     MacroAssembler _masm(&cbuf);
2422     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2423     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
2424   %}
2425 
2426   enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{
2427     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2428 
2429     MacroAssembler _masm(&cbuf);
2430     int toc_offset = 0;
2431 
2432     address const_toc_addr;
2433     // Create a non-oop constant, no relocation needed.
2434     // If it is an IC, it has a virtual_call_Relocation.
2435     const_toc_addr = __ long_constant((jlong)$src$$constant);
2436     if (const_toc_addr == NULL) {
2437       ciEnv::current()->record_out_of_memory_failure();
2438       return;
2439     }
2440     
2441     // Get the constant's TOC offset.
2442     toc_offset = __ offset_to_method_toc(const_toc_addr);
2443     
2444     // Keep the current instruction offset in mind.
2445     ((loadConLNode*)this)->_cbuf_insts_offset = __ offset();
2446   
2447     __ ld($dst$$Register, toc_offset, $toc$$Register);
2448   %}
2449 
2450   enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{
2451     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2452 
2453     MacroAssembler _masm(&cbuf);
2454 
2455     if (!ra_->C->in_scratch_emit_size()) {
2456       address const_toc_addr;
2457       // Create a non-oop constant, no relocation needed.
2458       // If it is an IC, it has a virtual_call_Relocation.
2459       const_toc_addr = __ long_constant((jlong)$src$$constant);
2460       if (const_toc_addr == NULL) {
2461         ciEnv::current()->record_out_of_memory_failure();
2462         return;
2463       }
2464 
2465       // Get the constant's TOC offset.
2466       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2467       // Store the toc offset of the constant.
2468       ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset;
2469 
2470       // Also keep the current instruction offset in mind.
2471       ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset();
2472     }
2473 
2474     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2475   %}
2476 
2477 %} // encode
2478 
2479 source %{
2480 
2481 typedef struct {
2482   loadConL_hiNode *_large_hi;
2483   loadConL_loNode *_large_lo;
2484   loadConLNode    *_small;
2485   MachNode        *_last;
2486 } loadConLNodesTuple;
2487 
2488 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc,
2489                                              OptoReg::Name reg_second, OptoReg::Name reg_first) {
2490   loadConLNodesTuple nodes;
2491 
2492   const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2493   if (large_constant_pool) {
2494     // Create new nodes.
2495     loadConL_hiNode *m1 = new loadConL_hiNode();
2496     loadConL_loNode *m2 = new loadConL_loNode();
2497 
2498     // inputs for new nodes
2499     m1->add_req(NULL, toc);
2500     m2->add_req(NULL, m1);
2501 
2502     // operands for new nodes
2503     m1->_opnds[0] = new iRegLdstOper(); // dst
2504     m1->_opnds[1] = immSrc;             // src
2505     m1->_opnds[2] = new iRegPdstOper(); // toc
2506     m2->_opnds[0] = new iRegLdstOper(); // dst
2507     m2->_opnds[1] = immSrc;             // src
2508     m2->_opnds[2] = new iRegLdstOper(); // base
2509 
2510     // Initialize ins_attrib TOC fields.
2511     m1->_const_toc_offset = -1;
2512     m2->_const_toc_offset_hi_node = m1;
2513 
2514     // Initialize ins_attrib instruction offset.
2515     m1->_cbuf_insts_offset = -1;
2516 
2517     // register allocation for new nodes
2518     ra_->set_pair(m1->_idx, reg_second, reg_first);
2519     ra_->set_pair(m2->_idx, reg_second, reg_first);
2520 
2521     // Create result.
2522     nodes._large_hi = m1;
2523     nodes._large_lo = m2;
2524     nodes._small = NULL;
2525     nodes._last = nodes._large_lo;
2526     assert(m2->bottom_type()->isa_long(), "must be long");
2527   } else {
2528     loadConLNode *m2 = new loadConLNode();
2529 
2530     // inputs for new nodes
2531     m2->add_req(NULL, toc);
2532 
2533     // operands for new nodes
2534     m2->_opnds[0] = new iRegLdstOper(); // dst
2535     m2->_opnds[1] = immSrc;             // src
2536     m2->_opnds[2] = new iRegPdstOper(); // toc
2537 
2538     // Initialize ins_attrib instruction offset.
2539     m2->_cbuf_insts_offset = -1;
2540 
2541     // register allocation for new nodes
2542     ra_->set_pair(m2->_idx, reg_second, reg_first);
2543 
2544     // Create result.
2545     nodes._large_hi = NULL;
2546     nodes._large_lo = NULL;
2547     nodes._small = m2;
2548     nodes._last = nodes._small;
2549     assert(m2->bottom_type()->isa_long(), "must be long");
2550   }
2551 
2552   return nodes;
2553 }
2554 
2555 %} // source
2556 
2557 encode %{
2558   // Postalloc expand emitter for loading a long constant from the method's TOC.
2559   // Enc_class needed as consttanttablebase is not supported by postalloc
2560   // expand.
2561   enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{
2562     // Create new nodes.
2563     loadConLNodesTuple loadConLNodes =
2564       loadConLNodesTuple_create(ra_, n_toc, op_src,
2565                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
2566 
2567     // Push new nodes.
2568     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
2569     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
2570 
2571     // some asserts
2572     assert(nodes->length() >= 1, "must have created at least 1 node");
2573     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
2574   %}
2575 
2576   enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{
2577     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
2578 
2579     MacroAssembler _masm(&cbuf);
2580     int toc_offset = 0;
2581 
2582     intptr_t val = $src$$constant;
2583     relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2584     address const_toc_addr;
2585     if (constant_reloc == relocInfo::oop_type) {
2586       // Create an oop constant and a corresponding relocation.
2587       AddressLiteral a = __ allocate_oop_address((jobject)val);
2588       const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2589       __ relocate(a.rspec());
2590     } else if (constant_reloc == relocInfo::metadata_type) {
2591       AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2592       const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2593       __ relocate(a.rspec());
2594     } else {
2595       // Create a non-oop constant, no relocation needed.
2596       const_toc_addr = __ long_constant((jlong)$src$$constant);
2597     }
2598 
2599     if (const_toc_addr == NULL) {
2600       ciEnv::current()->record_out_of_memory_failure();
2601       return;
2602     }
2603     // Get the constant's TOC offset.
2604     toc_offset = __ offset_to_method_toc(const_toc_addr);
2605 
2606     __ ld($dst$$Register, toc_offset, $toc$$Register);
2607   %}
2608 
2609   enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{
2610     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
2611 
2612     MacroAssembler _masm(&cbuf);
2613     if (!ra_->C->in_scratch_emit_size()) {
2614       intptr_t val = $src$$constant;
2615       relocInfo::relocType constant_reloc = $src->constant_reloc();  // src
2616       address const_toc_addr;
2617       if (constant_reloc == relocInfo::oop_type) {
2618         // Create an oop constant and a corresponding relocation.
2619         AddressLiteral a = __ allocate_oop_address((jobject)val);
2620         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2621         __ relocate(a.rspec());
2622       } else if (constant_reloc == relocInfo::metadata_type) {
2623         AddressLiteral a = __ constant_metadata_address((Metadata *)val);
2624         const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
2625         __ relocate(a.rspec());
2626       } else {  // non-oop pointers, e.g. card mark base, heap top
2627         // Create a non-oop constant, no relocation needed.
2628         const_toc_addr = __ long_constant((jlong)$src$$constant);
2629       }
2630 
2631       if (const_toc_addr == NULL) {
2632         ciEnv::current()->record_out_of_memory_failure();
2633         return;
2634       }
2635       // Get the constant's TOC offset.
2636       const int toc_offset = __ offset_to_method_toc(const_toc_addr);
2637       // Store the toc offset of the constant.
2638       ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset;
2639     }
2640 
2641     __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset));
2642   %}
2643 
2644   // Postalloc expand emitter for loading a ptr constant from the method's TOC.
2645   // Enc_class needed as consttanttablebase is not supported by postalloc
2646   // expand.
2647   enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{
2648     const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2649     if (large_constant_pool) {
2650       // Create new nodes.
2651       loadConP_hiNode *m1 = new loadConP_hiNode();
2652       loadConP_loNode *m2 = new loadConP_loNode();
2653 
2654       // inputs for new nodes
2655       m1->add_req(NULL, n_toc);
2656       m2->add_req(NULL, m1);
2657 
2658       // operands for new nodes
2659       m1->_opnds[0] = new iRegPdstOper(); // dst
2660       m1->_opnds[1] = op_src;             // src
2661       m1->_opnds[2] = new iRegPdstOper(); // toc
2662       m2->_opnds[0] = new iRegPdstOper(); // dst
2663       m2->_opnds[1] = op_src;             // src
2664       m2->_opnds[2] = new iRegLdstOper(); // base
2665 
2666       // Initialize ins_attrib TOC fields.
2667       m1->_const_toc_offset = -1;
2668       m2->_const_toc_offset_hi_node = m1;
2669 
2670       // Register allocation for new nodes.
2671       ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2672       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2673 
2674       nodes->push(m1);
2675       nodes->push(m2);
2676       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2677     } else {
2678       loadConPNode *m2 = new loadConPNode();
2679 
2680       // inputs for new nodes
2681       m2->add_req(NULL, n_toc);
2682 
2683       // operands for new nodes
2684       m2->_opnds[0] = new iRegPdstOper(); // dst
2685       m2->_opnds[1] = op_src;             // src
2686       m2->_opnds[2] = new iRegPdstOper(); // toc
2687 
2688       // Register allocation for new nodes.
2689       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2690 
2691       nodes->push(m2);
2692       assert(m2->bottom_type()->isa_ptr(), "must be ptr");
2693     }
2694   %}
2695 
2696   // Enc_class needed as consttanttablebase is not supported by postalloc
2697   // expand.
2698   enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{
2699     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2700 
2701     MachNode *m2;
2702     if (large_constant_pool) {
2703       m2 = new loadConFCompNode();
2704     } else {
2705       m2 = new loadConFNode();
2706     }
2707     // inputs for new nodes
2708     m2->add_req(NULL, n_toc);
2709 
2710     // operands for new nodes
2711     m2->_opnds[0] = op_dst;
2712     m2->_opnds[1] = op_src;
2713     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2714 
2715     // register allocation for new nodes
2716     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2717     nodes->push(m2);
2718   %}
2719 
2720   // Enc_class needed as consttanttablebase is not supported by postalloc
2721   // expand.
2722   enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{
2723     bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000;
2724 
2725     MachNode *m2;
2726     if (large_constant_pool) {
2727       m2 = new loadConDCompNode();
2728     } else {
2729       m2 = new loadConDNode();
2730     }
2731     // inputs for new nodes
2732     m2->add_req(NULL, n_toc);
2733 
2734     // operands for new nodes
2735     m2->_opnds[0] = op_dst;
2736     m2->_opnds[1] = op_src;
2737     m2->_opnds[2] = new iRegPdstOper(); // constanttablebase
2738 
2739     // register allocation for new nodes
2740     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2741     nodes->push(m2);
2742   %}
2743 
2744   enc_class enc_stw(iRegIsrc src, memory mem) %{
2745     // TODO: PPC port $archOpcode(ppc64Opcode_stw);
2746     MacroAssembler _masm(&cbuf);
2747     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2748     __ stw($src$$Register, Idisp, $mem$$base$$Register);
2749   %}
2750 
2751   enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{
2752     // TODO: PPC port $archOpcode(ppc64Opcode_std);
2753     MacroAssembler _masm(&cbuf);
2754     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2755     // Operand 'ds' requires 4-alignment.
2756     assert((Idisp & 0x3) == 0, "unaligned offset");
2757     __ std($src$$Register, Idisp, $mem$$base$$Register);
2758   %}
2759 
2760   enc_class enc_stfs(RegF src, memory mem) %{
2761     // TODO: PPC port $archOpcode(ppc64Opcode_stfs);
2762     MacroAssembler _masm(&cbuf);
2763     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2764     __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register);
2765   %}
2766 
2767   enc_class enc_stfd(RegF src, memory mem) %{
2768     // TODO: PPC port $archOpcode(ppc64Opcode_stfd);
2769     MacroAssembler _masm(&cbuf);
2770     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
2771     __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register);
2772   %}
2773 
2774   // Use release_store for card-marking to ensure that previous
2775   // oop-stores are visible before the card-mark change.
2776   enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
2777     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
2778     // FIXME: Implement this as a cmove and use a fixed condition code
2779     // register which is written on every transition to compiled code,
2780     // e.g. in call-stub and when returning from runtime stubs.
2781     //
2782     // Proposed code sequence for the cmove implementation:
2783     //
2784     // Label skip_release;
2785     // __ beq(CCRfixed, skip_release);
2786     // __ release();
2787     // __ bind(skip_release);
2788     // __ stb(card mark);
2789 
2790     MacroAssembler _masm(&cbuf);
2791     Label skip_storestore;
2792 
2793 #if 0 // TODO: PPC port
2794     // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the
2795     // StoreStore barrier conditionally.
2796     __ lwz(R0, 0, $releaseFieldAddr$$Register);
2797     __ cmpwi($crx$$CondRegister, R0, 0);
2798     __ beq_predict_taken($crx$$CondRegister, skip_storestore);
2799 #endif
2800     __ li(R0, 0);
2801     __ membar(Assembler::StoreStore);
2802 #if 0 // TODO: PPC port
2803     __ bind(skip_storestore);
2804 #endif
2805 
2806     // Do the store.
2807     if ($mem$$index == 0) {
2808       __ stb(R0, $mem$$disp, $mem$$base$$Register);
2809     } else {
2810       assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc");
2811       __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register);
2812     }
2813   %}
2814 
2815   enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{
2816 
2817     if (VM_Version::has_isel()) {
2818       // use isel instruction with Power 7
2819       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2820       encodeP_subNode    *n_sub_base = new encodeP_subNode();
2821       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2822       cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode();
2823 
2824       n_compare->add_req(n_region, n_src);
2825       n_compare->_opnds[0] = op_crx;
2826       n_compare->_opnds[1] = op_src;
2827       n_compare->_opnds[2] = new immL16Oper(0);
2828 
2829       n_sub_base->add_req(n_region, n_src);
2830       n_sub_base->_opnds[0] = op_dst;
2831       n_sub_base->_opnds[1] = op_src;
2832       n_sub_base->_bottom_type = _bottom_type;
2833 
2834       n_shift->add_req(n_region, n_sub_base);
2835       n_shift->_opnds[0] = op_dst;
2836       n_shift->_opnds[1] = op_dst;
2837       n_shift->_bottom_type = _bottom_type;
2838 
2839       n_cond_set->add_req(n_region, n_compare, n_shift);
2840       n_cond_set->_opnds[0] = op_dst;
2841       n_cond_set->_opnds[1] = op_crx;
2842       n_cond_set->_opnds[2] = op_dst;
2843       n_cond_set->_bottom_type = _bottom_type;
2844 
2845       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2846       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2847       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2848       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2849 
2850       nodes->push(n_compare);
2851       nodes->push(n_sub_base);
2852       nodes->push(n_shift);
2853       nodes->push(n_cond_set);
2854 
2855     } else {
2856       // before Power 7
2857       moveRegNode        *n_move     = new moveRegNode();
2858       cmpP_reg_imm16Node *n_compare  = new cmpP_reg_imm16Node();
2859       encodeP_shiftNode  *n_shift    = new encodeP_shiftNode();
2860       cond_sub_baseNode  *n_sub_base = new cond_sub_baseNode();
2861 
2862       n_move->add_req(n_region, n_src);
2863       n_move->_opnds[0] = op_dst;
2864       n_move->_opnds[1] = op_src;
2865       ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop.
2866 
2867       n_compare->add_req(n_region, n_src);
2868       n_compare->add_prec(n_move);
2869 
2870       n_compare->_opnds[0] = op_crx;
2871       n_compare->_opnds[1] = op_src;
2872       n_compare->_opnds[2] = new immL16Oper(0);
2873 
2874       n_sub_base->add_req(n_region, n_compare, n_src);
2875       n_sub_base->_opnds[0] = op_dst;
2876       n_sub_base->_opnds[1] = op_crx;
2877       n_sub_base->_opnds[2] = op_src;
2878       n_sub_base->_bottom_type = _bottom_type;
2879 
2880       n_shift->add_req(n_region, n_sub_base);
2881       n_shift->_opnds[0] = op_dst;
2882       n_shift->_opnds[1] = op_dst;
2883       n_shift->_bottom_type = _bottom_type;
2884 
2885       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2886       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2887       ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2888       ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2889 
2890       nodes->push(n_move);
2891       nodes->push(n_compare);
2892       nodes->push(n_sub_base);
2893       nodes->push(n_shift);
2894     }
2895 
2896     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2897   %}
2898 
2899   enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{
2900 
2901     encodeP_subNode *n1 = new encodeP_subNode();
2902     n1->add_req(n_region, n_src);
2903     n1->_opnds[0] = op_dst;
2904     n1->_opnds[1] = op_src;
2905     n1->_bottom_type = _bottom_type;
2906 
2907     encodeP_shiftNode *n2 = new encodeP_shiftNode();
2908     n2->add_req(n_region, n1);
2909     n2->_opnds[0] = op_dst;
2910     n2->_opnds[1] = op_dst;
2911     n2->_bottom_type = _bottom_type;
2912     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2913     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2914 
2915     nodes->push(n1);
2916     nodes->push(n2);
2917     assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed.
2918   %}
2919 
2920   enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
2921     decodeN_shiftNode *n_shift    = new decodeN_shiftNode();
2922     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
2923 
2924     n_compare->add_req(n_region, n_src);
2925     n_compare->_opnds[0] = op_crx;
2926     n_compare->_opnds[1] = op_src;
2927     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
2928 
2929     n_shift->add_req(n_region, n_src);
2930     n_shift->_opnds[0] = op_dst;
2931     n_shift->_opnds[1] = op_src;
2932     n_shift->_bottom_type = _bottom_type;
2933 
2934     if (VM_Version::has_isel()) {
2935       // use isel instruction with Power 7
2936 
2937       decodeN_addNode *n_add_base = new decodeN_addNode();
2938       n_add_base->add_req(n_region, n_shift);
2939       n_add_base->_opnds[0] = op_dst;
2940       n_add_base->_opnds[1] = op_dst;
2941       n_add_base->_bottom_type = _bottom_type;
2942 
2943       cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
2944       n_cond_set->add_req(n_region, n_compare, n_add_base);
2945       n_cond_set->_opnds[0] = op_dst;
2946       n_cond_set->_opnds[1] = op_crx;
2947       n_cond_set->_opnds[2] = op_dst;
2948       n_cond_set->_bottom_type = _bottom_type;
2949 
2950       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2951       ra_->set_oop(n_cond_set, true);
2952 
2953       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2954       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2955       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2956       ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2957 
2958       nodes->push(n_compare);
2959       nodes->push(n_shift);
2960       nodes->push(n_add_base);
2961       nodes->push(n_cond_set);
2962 
2963     } else {
2964       // before Power 7
2965       cond_add_baseNode *n_add_base = new cond_add_baseNode();
2966 
2967       n_add_base->add_req(n_region, n_compare, n_shift);
2968       n_add_base->_opnds[0] = op_dst;
2969       n_add_base->_opnds[1] = op_crx;
2970       n_add_base->_opnds[2] = op_dst;
2971       n_add_base->_bottom_type = _bottom_type;
2972 
2973       assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
2974       ra_->set_oop(n_add_base, true);
2975 
2976       ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2977       ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
2978       ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2979 
2980       nodes->push(n_compare);
2981       nodes->push(n_shift);
2982       nodes->push(n_add_base);
2983     }
2984   %}
2985 
2986   enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{
2987     decodeN_shiftNode *n1 = new decodeN_shiftNode();
2988     n1->add_req(n_region, n_src);
2989     n1->_opnds[0] = op_dst;
2990     n1->_opnds[1] = op_src;
2991     n1->_bottom_type = _bottom_type;
2992 
2993     decodeN_addNode *n2 = new decodeN_addNode();
2994     n2->add_req(n_region, n1);
2995     n2->_opnds[0] = op_dst;
2996     n2->_opnds[1] = op_dst;
2997     n2->_bottom_type = _bottom_type;
2998     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
2999     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
3000 
3001     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
3002     ra_->set_oop(n2, true);
3003 
3004     nodes->push(n1);
3005     nodes->push(n2);
3006   %}
3007 
3008   enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{
3009     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3010 
3011     MacroAssembler _masm(&cbuf);
3012     int cc        = $cmp$$cmpcode;
3013     int flags_reg = $crx$$reg;
3014     Label done;
3015     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3016     // Branch if not (cmp crx).
3017     __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done);
3018     __ mr($dst$$Register, $src$$Register);
3019     // TODO PPC port __ endgroup_if_needed(_size == 12);
3020     __ bind(done);
3021   %}
3022 
3023   enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{
3024     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3025 
3026     MacroAssembler _masm(&cbuf);
3027     Label done;
3028     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3029     // Branch if not (cmp crx).
3030     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
3031     __ li($dst$$Register, $src$$constant);
3032     // TODO PPC port __ endgroup_if_needed(_size == 12);
3033     __ bind(done);
3034   %}
3035 
3036   // This enc_class is needed so that scheduler gets proper
3037   // input mapping for latency computation.
3038   enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
3039     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
3040     MacroAssembler _masm(&cbuf);
3041     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
3042   %}
3043 
3044   enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3045     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3046 
3047     MacroAssembler _masm(&cbuf);
3048 
3049     Label done;
3050     __ cmpwi($crx$$CondRegister, $src$$Register, 0);
3051     __ li($dst$$Register, $zero$$constant);
3052     __ beq($crx$$CondRegister, done);
3053     __ li($dst$$Register, $notzero$$constant);
3054     __ bind(done);
3055   %}
3056 
3057   enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{
3058     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3059 
3060     MacroAssembler _masm(&cbuf);
3061 
3062     Label done;
3063     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3064     __ li($dst$$Register, $zero$$constant);
3065     __ beq($crx$$CondRegister, done);
3066     __ li($dst$$Register, $notzero$$constant);
3067     __ bind(done);
3068   %}
3069 
3070   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3071     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3072 
3073     MacroAssembler _masm(&cbuf);
3074     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3075     Label done;
3076     __ bso($crx$$CondRegister, done);
3077     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3078     // TODO PPC port __ endgroup_if_needed(_size == 12);
3079     __ bind(done);
3080   %}
3081 
3082   enc_class enc_cmove_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
3083     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3084 
3085     MacroAssembler _masm(&cbuf);
3086     Label done;
3087     __ bso($crx$$CondRegister, done);
3088     __ mffprd($dst$$Register, $src$$FloatRegister);
3089     // TODO PPC port __ endgroup_if_needed(_size == 12);
3090     __ bind(done);
3091   %}
3092 
3093   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3094     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3095 
3096     MacroAssembler _masm(&cbuf);
3097     Label d;   // dummy
3098     __ bind(d);
3099     Label* p = ($lbl$$label);
3100     // `p' is `NULL' when this encoding class is used only to
3101     // determine the size of the encoded instruction.
3102     Label& l = (NULL == p)? d : *(p);
3103     int cc = $cmp$$cmpcode;
3104     int flags_reg = $crx$$reg;
3105     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3106     int bhint = Assembler::bhintNoHint;
3107 
3108     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3109       if (_prob <= PROB_NEVER) {
3110         bhint = Assembler::bhintIsNotTaken;
3111       } else if (_prob >= PROB_ALWAYS) {
3112         bhint = Assembler::bhintIsTaken;
3113       }
3114     }
3115 
3116     __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3117           cc_to_biint(cc, flags_reg),
3118           l);
3119   %}
3120 
3121   enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3122     // The scheduler doesn't know about branch shortening, so we set the opcode
3123     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3124     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3125 
3126     MacroAssembler _masm(&cbuf);
3127     Label d;    // dummy
3128     __ bind(d);
3129     Label* p = ($lbl$$label);
3130     // `p' is `NULL' when this encoding class is used only to
3131     // determine the size of the encoded instruction.
3132     Label& l = (NULL == p)? d : *(p);
3133     int cc = $cmp$$cmpcode;
3134     int flags_reg = $crx$$reg;
3135     int bhint = Assembler::bhintNoHint;
3136 
3137     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3138       if (_prob <= PROB_NEVER) {
3139         bhint = Assembler::bhintIsNotTaken;
3140       } else if (_prob >= PROB_ALWAYS) {
3141         bhint = Assembler::bhintIsTaken;
3142       }
3143     }
3144 
3145     // Tell the conditional far branch to optimize itself when being relocated.
3146     __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3147                   cc_to_biint(cc, flags_reg),
3148                   l,
3149                   MacroAssembler::bc_far_optimize_on_relocate);
3150   %}
3151 
3152   // Branch used with Power6 scheduling (can be shortened without changing the node).
3153   enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3154     // The scheduler doesn't know about branch shortening, so we set the opcode
3155     // to ppc64Opcode_bc in order to hide this detail from the scheduler.
3156     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3157 
3158     MacroAssembler _masm(&cbuf);
3159     Label d;   // dummy
3160     __ bind(d);
3161     Label* p = ($lbl$$label);
3162     // `p' is `NULL' when this encoding class is used only to
3163     // determine the size of the encoded instruction.
3164     Label& l = (NULL == p)? d : *(p);
3165     int cc = $cmp$$cmpcode;
3166     int flags_reg = $crx$$reg;
3167     int bhint = Assembler::bhintNoHint;
3168 
3169     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3170       if (_prob <= PROB_NEVER) {
3171         bhint = Assembler::bhintIsNotTaken;
3172       } else if (_prob >= PROB_ALWAYS) {
3173         bhint = Assembler::bhintIsTaken;
3174       }
3175     }
3176 
3177 #if 0 // TODO: PPC port
3178     if (_size == 8) {
3179       // Tell the conditional far branch to optimize itself when being relocated.
3180       __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3181                     cc_to_biint(cc, flags_reg),
3182                     l,
3183                     MacroAssembler::bc_far_optimize_on_relocate);
3184     } else {
3185       __ bc    (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)),
3186                     cc_to_biint(cc, flags_reg),
3187                     l);
3188     }
3189 #endif
3190     Unimplemented();
3191   %}
3192 
3193   // Postalloc expand emitter for loading a replicatef float constant from
3194   // the method's TOC.
3195   // Enc_class needed as consttanttablebase is not supported by postalloc
3196   // expand.
3197   enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{
3198     // Create new nodes.
3199 
3200     // Make an operand with the bit pattern to load as float.
3201     immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF()));
3202 
3203     loadConLNodesTuple loadConLNodes =
3204       loadConLNodesTuple_create(ra_, n_toc, op_repl,
3205                                 ra_->get_reg_second(this), ra_->get_reg_first(this));
3206 
3207     // Push new nodes.
3208     if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi);
3209     if (loadConLNodes._last)     nodes->push(loadConLNodes._last);
3210 
3211     assert(nodes->length() >= 1, "must have created at least 1 node");
3212     assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long");
3213   %}
3214 
3215   // This enc_class is needed so that scheduler gets proper
3216   // input mapping for latency computation.
3217   enc_class enc_poll(immI dst, iRegLdst poll) %{
3218     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
3219     // Fake operand dst needed for PPC scheduler.
3220     assert($dst$$constant == 0x0, "dst must be 0x0");
3221 
3222     MacroAssembler _masm(&cbuf);
3223     // Mark the code position where the load from the safepoint
3224     // polling page was emitted as relocInfo::poll_type.
3225     __ relocate(relocInfo::poll_type);
3226     __ load_from_polling_page($poll$$Register);
3227   %}
3228 
3229   // A Java static call or a runtime call.
3230   //
3231   // Branch-and-link relative to a trampoline.
3232   // The trampoline loads the target address and does a long branch to there.
3233   // In case we call java, the trampoline branches to a interpreter_stub
3234   // which loads the inline cache and the real call target from the constant pool.
3235   //
3236   // This basically looks like this:
3237   //
3238   // >>>> consts      -+  -+
3239   //                   |   |- offset1
3240   // [call target1]    | <-+
3241   // [IC cache]        |- offset2
3242   // [call target2] <--+
3243   //
3244   // <<<< consts
3245   // >>>> insts
3246   //
3247   // bl offset16               -+  -+             ??? // How many bits available?
3248   //                            |   |
3249   // <<<< insts                 |   |
3250   // >>>> stubs                 |   |
3251   //                            |   |- trampoline_stub_Reloc
3252   // trampoline stub:           | <-+
3253   //   r2 = toc                 |
3254   //   r2 = [r2 + offset1]      |       // Load call target1 from const section
3255   //   mtctr r2                 |
3256   //   bctr                     |- static_stub_Reloc
3257   // comp_to_interp_stub:   <---+
3258   //   r1 = toc
3259   //   ICreg = [r1 + IC_offset]         // Load IC from const section
3260   //   r1    = [r1 + offset2]           // Load call target2 from const section
3261   //   mtctr r1
3262   //   bctr
3263   //
3264   // <<<< stubs
3265   //
3266   // The call instruction in the code either
3267   // - Branches directly to a compiled method if the offset is encodable in instruction.
3268   // - Branches to the trampoline stub if the offset to the compiled method is not encodable.
3269   // - Branches to the compiled_to_interp stub if the target is interpreted.
3270   //
3271   // Further there are three relocations from the loads to the constants in
3272   // the constant section.
3273   //
3274   // Usage of r1 and r2 in the stubs allows to distinguish them.
3275   enc_class enc_java_static_call(method meth) %{
3276     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3277 
3278     MacroAssembler _masm(&cbuf);
3279     address entry_point = (address)$meth$$method;
3280 
3281     if (!_method) {
3282       // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap.
3283       emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type);
3284     } else {
3285       // Remember the offset not the address.
3286       const int start_offset = __ offset();
3287 
3288       // The trampoline stub.
3289       // No entry point given, use the current pc.
3290       // Make sure branch fits into
3291       if (entry_point == 0) entry_point = __ pc();
3292 
3293       // Put the entry point as a constant into the constant pool.
3294       const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none);
3295       if (entry_point_toc_addr == NULL) {
3296         ciEnv::current()->record_out_of_memory_failure();
3297         return;
3298       }
3299       const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr);
3300 
3301       // Emit the trampoline stub which will be related to the branch-and-link below.
3302       CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset);
3303       if (ciEnv::current()->failing()) { return; } // Code cache may be full.
3304       int method_index = resolved_method_index(cbuf);
3305       __ relocate(_optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
3306                   : static_call_Relocation::spec(method_index));
3307 
3308       // The real call.
3309       // Note: At this point we do not have the address of the trampoline
3310       // stub, and the entry point might be too far away for bl, so __ pc()
3311       // serves as dummy and the bl will be patched later.
3312       cbuf.set_insts_mark();
3313       __ bl(__ pc());  // Emits a relocation.
3314 
3315       // The stub for call to interpreter.
3316       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
3317       if (stub == NULL) {
3318         ciEnv::current()->record_failure("CodeCache is full");
3319         return;
3320       }
3321     }
3322   %}
3323 
3324   // Second node of expanded dynamic call - the call.
3325   enc_class enc_java_dynamic_call_sched(method meth) %{
3326     // TODO: PPC port $archOpcode(ppc64Opcode_bl);
3327 
3328     MacroAssembler _masm(&cbuf);
3329 
3330     if (!ra_->C->in_scratch_emit_size()) {
3331       // Create a call trampoline stub for the given method.
3332       const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method;
3333       const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none);
3334       if (entry_point_const == NULL) {
3335         ciEnv::current()->record_out_of_memory_failure();
3336         return;
3337       }
3338       const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const);
3339       CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset());
3340       if (ra_->C->env()->failing()) { return; } // Code cache may be full.
3341 
3342       // Build relocation at call site with ic position as data.
3343       assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) ||
3344              (_load_ic_hi_node == NULL && _load_ic_node != NULL),
3345              "must have one, but can't have both");
3346       assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) ||
3347              (_load_ic_node != NULL    && _load_ic_node->_cbuf_insts_offset != -1),
3348              "must contain instruction offset");
3349       const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL
3350         ? _load_ic_hi_node->_cbuf_insts_offset
3351         : _load_ic_node->_cbuf_insts_offset;
3352       const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset);
3353       assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr),
3354              "should be load from TOC");
3355       int method_index = resolved_method_index(cbuf);
3356       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
3357     }
3358 
3359     // At this point I do not have the address of the trampoline stub,
3360     // and the entry point might be too far away for bl. Pc() serves
3361     // as dummy and bl will be patched later.
3362     __ bl((address) __ pc());
3363   %}
3364 
3365   // postalloc expand emitter for virtual calls.
3366   enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{
3367 
3368     // Create the nodes for loading the IC from the TOC.
3369     loadConLNodesTuple loadConLNodes_IC =
3370       loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()),
3371                                 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num));
3372 
3373     // Create the call node.
3374     CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode();
3375     call->_method_handle_invoke = _method_handle_invoke;
3376     call->_vtable_index      = _vtable_index;
3377     call->_method            = _method;
3378     call->_bci               = _bci;
3379     call->_optimized_virtual = _optimized_virtual;
3380     call->_tf                = _tf;
3381     call->_entry_point       = _entry_point;
3382     call->_cnt               = _cnt;
3383     call->_argsize           = _argsize;
3384     call->_oop_map           = _oop_map;
3385     call->_jvms              = _jvms;
3386     call->_jvmadj            = _jvmadj;
3387     call->_in_rms            = _in_rms;
3388     call->_nesting           = _nesting;
3389     call->_override_symbolic_info = _override_symbolic_info;
3390 
3391     // New call needs all inputs of old call.
3392     // Req...
3393     for (uint i = 0; i < req(); ++i) {
3394       // The expanded node does not need toc any more.
3395       // Add the inline cache constant here instead. This expresses the
3396       // register of the inline cache must be live at the call.
3397       // Else we would have to adapt JVMState by -1.
3398       if (i == mach_constant_base_node_input()) {
3399         call->add_req(loadConLNodes_IC._last);
3400       } else {
3401         call->add_req(in(i));
3402       }
3403     }
3404     // ...as well as prec
3405     for (uint i = req(); i < len(); ++i) {
3406       call->add_prec(in(i));
3407     }
3408 
3409     // Remember nodes loading the inline cache into r19.
3410     call->_load_ic_hi_node = loadConLNodes_IC._large_hi;
3411     call->_load_ic_node    = loadConLNodes_IC._small;
3412 
3413     // Operands for new nodes.
3414     call->_opnds[0] = _opnds[0];
3415     call->_opnds[1] = _opnds[1];
3416 
3417     // Only the inline cache is associated with a register.
3418     assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19");
3419 
3420     // Push new nodes.
3421     if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi);
3422     if (loadConLNodes_IC._last)     nodes->push(loadConLNodes_IC._last);
3423     nodes->push(call);
3424   %}
3425 
3426   // Compound version of call dynamic
3427   // Toc is only passed so that it can be used in ins_encode statement.
3428   // In the code we have to use $constanttablebase.
3429   enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{
3430     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3431     MacroAssembler _masm(&cbuf);
3432     int start_offset = __ offset();
3433 
3434     Register Rtoc = (ra_) ? $constanttablebase : R2_TOC;
3435 #if 0
3436     int vtable_index = this->_vtable_index;
3437     if (_vtable_index < 0) {
3438       // Must be invalid_vtable_index, not nonvirtual_vtable_index.
3439       assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value");
3440       Register ic_reg = as_Register(Matcher::inline_cache_reg_encode());
3441 
3442       // Virtual call relocation will point to ic load.
3443       address virtual_call_meta_addr = __ pc();
3444       // Load a clear inline cache.
3445       AddressLiteral empty_ic((address) Universe::non_oop_word());
3446       bool success = __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc, /*fixed_size*/ true);
3447       if (!success) {
3448         ciEnv::current()->record_out_of_memory_failure();
3449         return;
3450       }
3451       // CALL to fixup routine.  Fixup routine uses ScopeDesc info
3452       // to determine who we intended to call.
3453       __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr));
3454       emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none);
3455       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3456              "Fix constant in ret_addr_offset()");
3457     } else {
3458       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
3459       // Go thru the vtable. Get receiver klass. Receiver already
3460       // checked for non-null. If we'll go thru a C2I adapter, the
3461       // interpreter expects method in R19_method.
3462 
3463       __ load_klass(R11_scratch1, R3);
3464 
3465       int entry_offset = in_bytes(Klass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes();
3466       int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
3467       __ li(R19_method, v_off);
3468       __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/);
3469       // NOTE: for vtable dispatches, the vtable entry will never be
3470       // null. However it may very well end up in handle_wrong_method
3471       // if the method is abstract for the particular class.
3472       __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method);
3473       // Call target. Either compiled code or C2I adapter.
3474       __ mtctr(R11_scratch1);
3475       __ bctrl();
3476       if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) {
3477         tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset);
3478       }
3479       assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset,
3480              "Fix constant in ret_addr_offset()");
3481     }
3482 #endif
3483     Unimplemented();  // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!).
3484   %}
3485 
3486   // a runtime call
3487   enc_class enc_java_to_runtime_call (method meth) %{
3488     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
3489 
3490     MacroAssembler _masm(&cbuf);
3491     const address start_pc = __ pc();
3492 
3493 #if defined(ABI_ELFv2)
3494     address entry= !($meth$$method) ? NULL : (address)$meth$$method;
3495     __ call_c(entry, relocInfo::runtime_call_type);
3496 #else
3497     // The function we're going to call.
3498     FunctionDescriptor fdtemp;
3499     const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method;
3500 
3501     Register Rtoc = R12_scratch2;
3502     // Calculate the method's TOC.
3503     __ calculate_address_from_global_toc(Rtoc, __ method_toc());
3504     // Put entry, env, toc into the constant pool, this needs up to 3 constant
3505     // pool entries; call_c_using_toc will optimize the call.
3506     bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc);
3507     if (!success) {
3508       ciEnv::current()->record_out_of_memory_failure();
3509       return;
3510     }
3511 #endif
3512 
3513     // Check the ret_addr_offset.
3514     assert(((MachCallRuntimeNode*)this)->ret_addr_offset() ==  __ last_calls_return_pc() - start_pc,
3515            "Fix constant in ret_addr_offset()");
3516   %}
3517 
3518   // Move to ctr for leaf call.
3519   // This enc_class is needed so that scheduler gets proper
3520   // input mapping for latency computation.
3521   enc_class enc_leaf_call_mtctr(iRegLsrc src) %{
3522     // TODO: PPC port $archOpcode(ppc64Opcode_mtctr);
3523     MacroAssembler _masm(&cbuf);
3524     __ mtctr($src$$Register);
3525   %}
3526 
3527   // Postalloc expand emitter for runtime leaf calls.
3528   enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{
3529     loadConLNodesTuple loadConLNodes_Entry;
3530 #if defined(ABI_ELFv2)
3531     jlong entry_address = (jlong) this->entry_point();
3532     assert(entry_address, "need address here");
3533     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3534                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3535 #else
3536     // Get the struct that describes the function we are about to call.
3537     FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point();
3538     assert(fd, "need fd here");
3539     jlong entry_address = (jlong) fd->entry();
3540     // new nodes
3541     loadConLNodesTuple loadConLNodes_Env;
3542     loadConLNodesTuple loadConLNodes_Toc;
3543 
3544     // Create nodes and operands for loading the entry point.
3545     loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address),
3546                                                     OptoReg::Name(R12_H_num), OptoReg::Name(R12_num));
3547 
3548 
3549     // Create nodes and operands for loading the env pointer.
3550     if (fd->env() != NULL) {
3551       loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()),
3552                                                     OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3553     } else {
3554       loadConLNodes_Env._large_hi = NULL;
3555       loadConLNodes_Env._large_lo = NULL;
3556       loadConLNodes_Env._small    = NULL;
3557       loadConLNodes_Env._last = new loadConL16Node();
3558       loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper();
3559       loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0);
3560       ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num));
3561     }
3562 
3563     // Create nodes and operands for loading the Toc point.
3564     loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()),
3565                                                   OptoReg::Name(R2_H_num), OptoReg::Name(R2_num));
3566 #endif // ABI_ELFv2
3567     // mtctr node
3568     MachNode *mtctr = new CallLeafDirect_mtctrNode();
3569 
3570     assert(loadConLNodes_Entry._last != NULL, "entry must exist");
3571     mtctr->add_req(0, loadConLNodes_Entry._last);
3572 
3573     mtctr->_opnds[0] = new iRegLdstOper();
3574     mtctr->_opnds[1] = new iRegLdstOper();
3575 
3576     // call node
3577     MachCallLeafNode *call = new CallLeafDirectNode();
3578 
3579     call->_opnds[0] = _opnds[0];
3580     call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later.
3581 
3582     // Make the new call node look like the old one.
3583     call->_name        = _name;
3584     call->_tf          = _tf;
3585     call->_entry_point = _entry_point;
3586     call->_cnt         = _cnt;
3587     call->_argsize     = _argsize;
3588     call->_oop_map     = _oop_map;
3589     guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms().");
3590     call->_jvms        = NULL;
3591     call->_jvmadj      = _jvmadj;
3592     call->_in_rms      = _in_rms;
3593     call->_nesting     = _nesting;
3594 
3595 
3596     // New call needs all inputs of old call.
3597     // Req...
3598     for (uint i = 0; i < req(); ++i) {
3599       if (i != mach_constant_base_node_input()) {
3600         call->add_req(in(i));
3601       }
3602     }
3603 
3604     // These must be reqired edges, as the registers are live up to
3605     // the call. Else the constants are handled as kills.
3606     call->add_req(mtctr);
3607 #if !defined(ABI_ELFv2)
3608     call->add_req(loadConLNodes_Env._last);
3609     call->add_req(loadConLNodes_Toc._last);
3610 #endif
3611 
3612     // ...as well as prec
3613     for (uint i = req(); i < len(); ++i) {
3614       call->add_prec(in(i));
3615     }
3616 
3617     // registers
3618     ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num));
3619 
3620     // Insert the new nodes.
3621     if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi);
3622     if (loadConLNodes_Entry._last)     nodes->push(loadConLNodes_Entry._last);
3623 #if !defined(ABI_ELFv2)
3624     if (loadConLNodes_Env._large_hi)   nodes->push(loadConLNodes_Env._large_hi);
3625     if (loadConLNodes_Env._last)       nodes->push(loadConLNodes_Env._last);
3626     if (loadConLNodes_Toc._large_hi)   nodes->push(loadConLNodes_Toc._large_hi);
3627     if (loadConLNodes_Toc._last)       nodes->push(loadConLNodes_Toc._last);
3628 #endif
3629     nodes->push(mtctr);
3630     nodes->push(call);
3631   %}
3632 %}
3633 
3634 //----------FRAME--------------------------------------------------------------
3635 // Definition of frame structure and management information.
3636 
3637 frame %{
3638   // What direction does stack grow in (assumed to be same for native & Java).
3639   stack_direction(TOWARDS_LOW);
3640 
3641   // These two registers define part of the calling convention between
3642   // compiled code and the interpreter.
3643 
3644   // Inline Cache Register or method for I2C.
3645   inline_cache_reg(R19); // R19_method
3646 
3647   // Method Oop Register when calling interpreter.
3648   interpreter_method_oop_reg(R19); // R19_method
3649 
3650   // Optional: name the operand used by cisc-spilling to access
3651   // [stack_pointer + offset].
3652   cisc_spilling_operand_name(indOffset);
3653 
3654   // Number of stack slots consumed by a Monitor enter.
3655   sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size));
3656 
3657   // Compiled code's Frame Pointer.
3658   frame_pointer(R1); // R1_SP
3659 
3660   // Interpreter stores its frame pointer in a register which is
3661   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
3662   // interpreted java to compiled java.
3663   //
3664   // R14_state holds pointer to caller's cInterpreter.
3665   interpreter_frame_pointer(R14); // R14_state
3666 
3667   stack_alignment(frame::alignment_in_bytes);
3668 
3669   in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size));
3670 
3671   // Number of outgoing stack slots killed above the
3672   // out_preserve_stack_slots for calls to C. Supports the var-args
3673   // backing area for register parms.
3674   //
3675   varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size));
3676 
3677   // The after-PROLOG location of the return address. Location of
3678   // return address specifies a type (REG or STACK) and a number
3679   // representing the register number (i.e. - use a register name) or
3680   // stack slot.
3681   //
3682   // A: Link register is stored in stack slot ...
3683   // M:  ... but it's in the caller's frame according to PPC-64 ABI.
3684   // J: Therefore, we make sure that the link register is also in R11_scratch1
3685   //    at the end of the prolog.
3686   // B: We use R20, now.
3687   //return_addr(REG R20);
3688 
3689   // G: After reading the comments made by all the luminaries on their
3690   //    failure to tell the compiler where the return address really is,
3691   //    I hardly dare to try myself.  However, I'm convinced it's in slot
3692   //    4 what apparently works and saves us some spills.
3693   return_addr(STACK 4);
3694 
3695   // This is the body of the function
3696   //
3697   // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs
3698   //                                  uint length,      // length of array
3699   //                                  bool is_outgoing)
3700   //
3701   // The `sig' array is to be updated. sig[j] represents the location
3702   // of the j-th argument, either a register or a stack slot.
3703 
3704   // Comment taken from i486.ad:
3705   // Body of function which returns an integer array locating
3706   // arguments either in registers or in stack slots. Passed an array
3707   // of ideal registers called "sig" and a "length" count. Stack-slot
3708   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3709   // arguments for a CALLEE. Incoming stack arguments are
3710   // automatically biased by the preserve_stack_slots field above.
3711   calling_convention %{
3712     // No difference between ingoing/outgoing. Just pass false.
3713     SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
3714   %}
3715 
3716   // Comment taken from i486.ad:
3717   // Body of function which returns an integer array locating
3718   // arguments either in registers or in stack slots. Passed an array
3719   // of ideal registers called "sig" and a "length" count. Stack-slot
3720   // offsets are based on outgoing arguments, i.e. a CALLER setting up
3721   // arguments for a CALLEE. Incoming stack arguments are
3722   // automatically biased by the preserve_stack_slots field above.
3723   c_calling_convention %{
3724     // This is obviously always outgoing.
3725     // C argument in register AND stack slot.
3726     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3727   %}
3728 
3729   // Location of native (C/C++) and interpreter return values. This
3730   // is specified to be the same as Java. In the 32-bit VM, long
3731   // values are actually returned from native calls in O0:O1 and
3732   // returned to the interpreter in I0:I1. The copying to and from
3733   // the register pairs is done by the appropriate call and epilog
3734   // opcodes. This simplifies the register allocator.
3735   c_return_value %{
3736     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3737             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3738             "only return normal values");
3739     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3740     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3741     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3742     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3743   %}
3744 
3745   // Location of compiled Java return values.  Same as C
3746   return_value %{
3747     assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) ||
3748             (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0),
3749             "only return normal values");
3750     // enum names from opcodes.hpp:    Op_Node Op_Set Op_RegN       Op_RegI       Op_RegP       Op_RegF       Op_RegD       Op_RegL
3751     static int typeToRegLo[Op_RegL+1] = { 0,   0,     R3_num,   R3_num,   R3_num,   F1_num,   F1_num,   R3_num };
3752     static int typeToRegHi[Op_RegL+1] = { 0,   0,     OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num };
3753     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
3754   %}
3755 %}
3756 
3757 
3758 //----------ATTRIBUTES---------------------------------------------------------
3759 
3760 //----------Operand Attributes-------------------------------------------------
3761 op_attrib op_cost(1);          // Required cost attribute.
3762 
3763 //----------Instruction Attributes---------------------------------------------
3764 
3765 // Cost attribute. required.
3766 ins_attrib ins_cost(DEFAULT_COST);
3767 
3768 // Is this instruction a non-matching short branch variant of some
3769 // long branch? Not required.
3770 ins_attrib ins_short_branch(0);
3771 
3772 ins_attrib ins_is_TrapBasedCheckNode(true);
3773 
3774 // Number of constants.
3775 // This instruction uses the given number of constants
3776 // (optional attribute).
3777 // This is needed to determine in time whether the constant pool will
3778 // exceed 4000 entries. Before postalloc_expand the overall number of constants
3779 // is determined. It's also used to compute the constant pool size
3780 // in Output().
3781 ins_attrib ins_num_consts(0);
3782 
3783 // Required alignment attribute (must be a power of 2) specifies the
3784 // alignment that some part of the instruction (not necessarily the
3785 // start) requires. If > 1, a compute_padding() function must be
3786 // provided for the instruction.
3787 ins_attrib ins_alignment(1);
3788 
3789 // Enforce/prohibit rematerializations.
3790 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
3791 //   then rematerialization of that instruction is prohibited and the
3792 //   instruction's value will be spilled if necessary.
3793 //   Causes that MachNode::rematerialize() returns false.
3794 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
3795 //   then rematerialization should be enforced and a copy of the instruction
3796 //   should be inserted if possible; rematerialization is not guaranteed.
3797 //   Note: this may result in rematerializations in front of every use.
3798 //   Causes that MachNode::rematerialize() can return true.
3799 // (optional attribute)
3800 ins_attrib ins_cannot_rematerialize(false);
3801 ins_attrib ins_should_rematerialize(false);
3802 
3803 // Instruction has variable size depending on alignment.
3804 ins_attrib ins_variable_size_depending_on_alignment(false);
3805 
3806 // Instruction is a nop.
3807 ins_attrib ins_is_nop(false);
3808 
3809 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock).
3810 ins_attrib ins_use_mach_if_fast_lock_node(false);
3811 
3812 // Field for the toc offset of a constant.
3813 //
3814 // This is needed if the toc offset is not encodable as an immediate in
3815 // the PPC load instruction. If so, the upper (hi) bits of the offset are
3816 // added to the toc, and from this a load with immediate is performed.
3817 // With postalloc expand, we get two nodes that require the same offset
3818 // but which don't know about each other. The offset is only known
3819 // when the constant is added to the constant pool during emitting.
3820 // It is generated in the 'hi'-node adding the upper bits, and saved
3821 // in this node.  The 'lo'-node has a link to the 'hi'-node and reads
3822 // the offset from there when it gets encoded.
3823 ins_attrib ins_field_const_toc_offset(0);
3824 ins_attrib ins_field_const_toc_offset_hi_node(0);
3825 
3826 // A field that can hold the instructions offset in the code buffer.
3827 // Set in the nodes emitter.
3828 ins_attrib ins_field_cbuf_insts_offset(-1);
3829 
3830 // Fields for referencing a call's load-IC-node.
3831 // If the toc offset can not be encoded as an immediate in a load, we
3832 // use two nodes.
3833 ins_attrib ins_field_load_ic_hi_node(0);
3834 ins_attrib ins_field_load_ic_node(0);
3835 
3836 //----------OPERANDS-----------------------------------------------------------
3837 // Operand definitions must precede instruction definitions for correct
3838 // parsing in the ADLC because operands constitute user defined types
3839 // which are used in instruction definitions.
3840 //
3841 // Formats are generated automatically for constants and base registers.
3842 
3843 //----------Simple Operands----------------------------------------------------
3844 // Immediate Operands
3845 
3846 // Integer Immediate: 32-bit
3847 operand immI() %{
3848   match(ConI);
3849   op_cost(40);
3850   format %{ %}
3851   interface(CONST_INTER);
3852 %}
3853 
3854 operand immI8() %{
3855   predicate(Assembler::is_simm(n->get_int(), 8));
3856   op_cost(0);
3857   match(ConI);
3858   format %{ %}
3859   interface(CONST_INTER);
3860 %}
3861 
3862 // Integer Immediate: 16-bit
3863 operand immI16() %{
3864   predicate(Assembler::is_simm(n->get_int(), 16));
3865   op_cost(0);
3866   match(ConI);
3867   format %{ %}
3868   interface(CONST_INTER);
3869 %}
3870 
3871 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000.
3872 operand immIhi16() %{
3873   predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0));
3874   match(ConI);
3875   op_cost(0);
3876   format %{ %}
3877   interface(CONST_INTER);
3878 %}
3879 
3880 operand immInegpow2() %{
3881   predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int()))));
3882   match(ConI);
3883   op_cost(0);
3884   format %{ %}
3885   interface(CONST_INTER);
3886 %}
3887 
3888 operand immIpow2minus1() %{
3889   predicate(is_power_of_2_long((((jlong) (n->get_int()))+1)));
3890   match(ConI);
3891   op_cost(0);
3892   format %{ %}
3893   interface(CONST_INTER);
3894 %}
3895 
3896 operand immIpowerOf2() %{
3897   predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int())))));
3898   match(ConI);
3899   op_cost(0);
3900   format %{ %}
3901   interface(CONST_INTER);
3902 %}
3903 
3904 // Unsigned Integer Immediate: the values 0-31
3905 operand uimmI5() %{
3906   predicate(Assembler::is_uimm(n->get_int(), 5));
3907   match(ConI);
3908   op_cost(0);
3909   format %{ %}
3910   interface(CONST_INTER);
3911 %}
3912 
3913 // Unsigned Integer Immediate: 6-bit
3914 operand uimmI6() %{
3915   predicate(Assembler::is_uimm(n->get_int(), 6));
3916   match(ConI);
3917   op_cost(0);
3918   format %{ %}
3919   interface(CONST_INTER);
3920 %}
3921 
3922 // Unsigned Integer Immediate:  6-bit int, greater than 32
3923 operand uimmI6_ge32() %{
3924   predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32);
3925   match(ConI);
3926   op_cost(0);
3927   format %{ %}
3928   interface(CONST_INTER);
3929 %}
3930 
3931 // Unsigned Integer Immediate: 15-bit
3932 operand uimmI15() %{
3933   predicate(Assembler::is_uimm(n->get_int(), 15));
3934   match(ConI);
3935   op_cost(0);
3936   format %{ %}
3937   interface(CONST_INTER);
3938 %}
3939 
3940 // Unsigned Integer Immediate: 16-bit
3941 operand uimmI16() %{
3942   predicate(Assembler::is_uimm(n->get_int(), 16));
3943   match(ConI);
3944   op_cost(0);
3945   format %{ %}
3946   interface(CONST_INTER);
3947 %}
3948 
3949 // constant 'int 0'.
3950 operand immI_0() %{
3951   predicate(n->get_int() == 0);
3952   match(ConI);
3953   op_cost(0);
3954   format %{ %}
3955   interface(CONST_INTER);
3956 %}
3957 
3958 // constant 'int 1'.
3959 operand immI_1() %{
3960   predicate(n->get_int() == 1);
3961   match(ConI);
3962   op_cost(0);
3963   format %{ %}
3964   interface(CONST_INTER);
3965 %}
3966 
3967 // constant 'int -1'.
3968 operand immI_minus1() %{
3969   predicate(n->get_int() == -1);
3970   match(ConI);
3971   op_cost(0);
3972   format %{ %}
3973   interface(CONST_INTER);
3974 %}
3975 
3976 // int value 16.
3977 operand immI_16() %{
3978   predicate(n->get_int() == 16);
3979   match(ConI);
3980   op_cost(0);
3981   format %{ %}
3982   interface(CONST_INTER);
3983 %}
3984 
3985 // int value 24.
3986 operand immI_24() %{
3987   predicate(n->get_int() == 24);
3988   match(ConI);
3989   op_cost(0);
3990   format %{ %}
3991   interface(CONST_INTER);
3992 %}
3993 
3994 // Compressed oops constants
3995 // Pointer Immediate
3996 operand immN() %{
3997   match(ConN);
3998 
3999   op_cost(10);
4000   format %{ %}
4001   interface(CONST_INTER);
4002 %}
4003 
4004 // NULL Pointer Immediate
4005 operand immN_0() %{
4006   predicate(n->get_narrowcon() == 0);
4007   match(ConN);
4008 
4009   op_cost(0);
4010   format %{ %}
4011   interface(CONST_INTER);
4012 %}
4013 
4014 // Compressed klass constants
4015 operand immNKlass() %{
4016   match(ConNKlass);
4017 
4018   op_cost(0);
4019   format %{ %}
4020   interface(CONST_INTER);
4021 %}
4022 
4023 // This operand can be used to avoid matching of an instruct
4024 // with chain rule.
4025 operand immNKlass_NM() %{
4026   match(ConNKlass);
4027   predicate(false);
4028   op_cost(0);
4029   format %{ %}
4030   interface(CONST_INTER);
4031 %}
4032 
4033 // Pointer Immediate: 64-bit
4034 operand immP() %{
4035   match(ConP);
4036   op_cost(0);
4037   format %{ %}
4038   interface(CONST_INTER);
4039 %}
4040 
4041 // Operand to avoid match of loadConP.
4042 // This operand can be used to avoid matching of an instruct
4043 // with chain rule.
4044 operand immP_NM() %{
4045   match(ConP);
4046   predicate(false);
4047   op_cost(0);
4048   format %{ %}
4049   interface(CONST_INTER);
4050 %}
4051 
4052 // costant 'pointer 0'.
4053 operand immP_0() %{
4054   predicate(n->get_ptr() == 0);
4055   match(ConP);
4056   op_cost(0);
4057   format %{ %}
4058   interface(CONST_INTER);
4059 %}
4060 
4061 // pointer 0x0 or 0x1
4062 operand immP_0or1() %{
4063   predicate((n->get_ptr() == 0) || (n->get_ptr() == 1));
4064   match(ConP);
4065   op_cost(0);
4066   format %{ %}
4067   interface(CONST_INTER);
4068 %}
4069 
4070 operand immL() %{
4071   match(ConL);
4072   op_cost(40);
4073   format %{ %}
4074   interface(CONST_INTER);
4075 %}
4076 
4077 operand immLmax30() %{
4078   predicate((n->get_long() <= 30));
4079   match(ConL);
4080   op_cost(0);
4081   format %{ %}
4082   interface(CONST_INTER);
4083 %}
4084 
4085 // Long Immediate: 16-bit
4086 operand immL16() %{
4087   predicate(Assembler::is_simm(n->get_long(), 16));
4088   match(ConL);
4089   op_cost(0);
4090   format %{ %}
4091   interface(CONST_INTER);
4092 %}
4093 
4094 // Long Immediate: 16-bit, 4-aligned
4095 operand immL16Alg4() %{
4096   predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0));
4097   match(ConL);
4098   op_cost(0);
4099   format %{ %}
4100   interface(CONST_INTER);
4101 %}
4102 
4103 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000.
4104 operand immL32hi16() %{
4105   predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L));
4106   match(ConL);
4107   op_cost(0);
4108   format %{ %}
4109   interface(CONST_INTER);
4110 %}
4111 
4112 // Long Immediate: 32-bit
4113 operand immL32() %{
4114   predicate(Assembler::is_simm(n->get_long(), 32));
4115   match(ConL);
4116   op_cost(0);
4117   format %{ %}
4118   interface(CONST_INTER);
4119 %}
4120 
4121 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000.
4122 operand immLhighest16() %{
4123   predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L);
4124   match(ConL);
4125   op_cost(0);
4126   format %{ %}
4127   interface(CONST_INTER);
4128 %}
4129 
4130 operand immLnegpow2() %{
4131   predicate(is_power_of_2_long((jlong)-(n->get_long())));
4132   match(ConL);
4133   op_cost(0);
4134   format %{ %}
4135   interface(CONST_INTER);
4136 %}
4137 
4138 operand immLpow2minus1() %{
4139   predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) &&
4140             (n->get_long() != (jlong)0xffffffffffffffffL));
4141   match(ConL);
4142   op_cost(0);
4143   format %{ %}
4144   interface(CONST_INTER);
4145 %}
4146 
4147 // constant 'long 0'.
4148 operand immL_0() %{
4149   predicate(n->get_long() == 0L);
4150   match(ConL);
4151   op_cost(0);
4152   format %{ %}
4153   interface(CONST_INTER);
4154 %}
4155 
4156 // constat ' long -1'.
4157 operand immL_minus1() %{
4158   predicate(n->get_long() == -1L);
4159   match(ConL);
4160   op_cost(0);
4161   format %{ %}
4162   interface(CONST_INTER);
4163 %}
4164 
4165 // Long Immediate: low 32-bit mask
4166 operand immL_32bits() %{
4167   predicate(n->get_long() == 0xFFFFFFFFL);
4168   match(ConL);
4169   op_cost(0);
4170   format %{ %}
4171   interface(CONST_INTER);
4172 %}
4173 
4174 // Unsigned Long Immediate: 16-bit
4175 operand uimmL16() %{
4176   predicate(Assembler::is_uimm(n->get_long(), 16));
4177   match(ConL);
4178   op_cost(0);
4179   format %{ %}
4180   interface(CONST_INTER);
4181 %}
4182 
4183 // Float Immediate
4184 operand immF() %{
4185   match(ConF);
4186   op_cost(40);
4187   format %{ %}
4188   interface(CONST_INTER);
4189 %}
4190 
4191 // Float Immediate: +0.0f.
4192 operand immF_0() %{
4193   predicate(jint_cast(n->getf()) == 0);
4194   match(ConF);
4195 
4196   op_cost(0);
4197   format %{ %}
4198   interface(CONST_INTER);
4199 %}
4200 
4201 // Double Immediate
4202 operand immD() %{
4203   match(ConD);
4204   op_cost(40);
4205   format %{ %}
4206   interface(CONST_INTER);
4207 %}
4208 
4209 // Integer Register Operands
4210 // Integer Destination Register
4211 // See definition of reg_class bits32_reg_rw.
4212 operand iRegIdst() %{
4213   constraint(ALLOC_IN_RC(bits32_reg_rw));
4214   match(RegI);
4215   match(rscratch1RegI);
4216   match(rscratch2RegI);
4217   match(rarg1RegI);
4218   match(rarg2RegI);
4219   match(rarg3RegI);
4220   match(rarg4RegI);
4221   format %{ %}
4222   interface(REG_INTER);
4223 %}
4224 
4225 // Integer Source Register
4226 // See definition of reg_class bits32_reg_ro.
4227 operand iRegIsrc() %{
4228   constraint(ALLOC_IN_RC(bits32_reg_ro));
4229   match(RegI);
4230   match(rscratch1RegI);
4231   match(rscratch2RegI);
4232   match(rarg1RegI);
4233   match(rarg2RegI);
4234   match(rarg3RegI);
4235   match(rarg4RegI);
4236   format %{ %}
4237   interface(REG_INTER);
4238 %}
4239 
4240 operand rscratch1RegI() %{
4241   constraint(ALLOC_IN_RC(rscratch1_bits32_reg));
4242   match(iRegIdst);
4243   format %{ %}
4244   interface(REG_INTER);
4245 %}
4246 
4247 operand rscratch2RegI() %{
4248   constraint(ALLOC_IN_RC(rscratch2_bits32_reg));
4249   match(iRegIdst);
4250   format %{ %}
4251   interface(REG_INTER);
4252 %}
4253 
4254 operand rarg1RegI() %{
4255   constraint(ALLOC_IN_RC(rarg1_bits32_reg));
4256   match(iRegIdst);
4257   format %{ %}
4258   interface(REG_INTER);
4259 %}
4260 
4261 operand rarg2RegI() %{
4262   constraint(ALLOC_IN_RC(rarg2_bits32_reg));
4263   match(iRegIdst);
4264   format %{ %}
4265   interface(REG_INTER);
4266 %}
4267 
4268 operand rarg3RegI() %{
4269   constraint(ALLOC_IN_RC(rarg3_bits32_reg));
4270   match(iRegIdst);
4271   format %{ %}
4272   interface(REG_INTER);
4273 %}
4274 
4275 operand rarg4RegI() %{
4276   constraint(ALLOC_IN_RC(rarg4_bits32_reg));
4277   match(iRegIdst);
4278   format %{ %}
4279   interface(REG_INTER);
4280 %}
4281 
4282 operand rarg1RegL() %{
4283   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4284   match(iRegLdst);
4285   format %{ %}
4286   interface(REG_INTER);
4287 %}
4288 
4289 operand rarg2RegL() %{
4290   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4291   match(iRegLdst);
4292   format %{ %}
4293   interface(REG_INTER);
4294 %}
4295 
4296 operand rarg3RegL() %{
4297   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4298   match(iRegLdst);
4299   format %{ %}
4300   interface(REG_INTER);
4301 %}
4302 
4303 operand rarg4RegL() %{
4304   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4305   match(iRegLdst);
4306   format %{ %}
4307   interface(REG_INTER);
4308 %}
4309 
4310 // Pointer Destination Register
4311 // See definition of reg_class bits64_reg_rw.
4312 operand iRegPdst() %{
4313   constraint(ALLOC_IN_RC(bits64_reg_rw));
4314   match(RegP);
4315   match(rscratch1RegP);
4316   match(rscratch2RegP);
4317   match(rarg1RegP);
4318   match(rarg2RegP);
4319   match(rarg3RegP);
4320   match(rarg4RegP);
4321   format %{ %}
4322   interface(REG_INTER);
4323 %}
4324 
4325 // Pointer Destination Register
4326 // Operand not using r11 and r12 (killed in epilog).
4327 operand iRegPdstNoScratch() %{
4328   constraint(ALLOC_IN_RC(bits64_reg_leaf_call));
4329   match(RegP);
4330   match(rarg1RegP);
4331   match(rarg2RegP);
4332   match(rarg3RegP);
4333   match(rarg4RegP);
4334   format %{ %}
4335   interface(REG_INTER);
4336 %}
4337 
4338 // Pointer Source Register
4339 // See definition of reg_class bits64_reg_ro.
4340 operand iRegPsrc() %{
4341   constraint(ALLOC_IN_RC(bits64_reg_ro));
4342   match(RegP);
4343   match(iRegPdst);
4344   match(rscratch1RegP);
4345   match(rscratch2RegP);
4346   match(rarg1RegP);
4347   match(rarg2RegP);
4348   match(rarg3RegP);
4349   match(rarg4RegP);
4350   match(threadRegP);
4351   format %{ %}
4352   interface(REG_INTER);
4353 %}
4354 
4355 // Thread operand.
4356 operand threadRegP() %{
4357   constraint(ALLOC_IN_RC(thread_bits64_reg));
4358   match(iRegPdst);
4359   format %{ "R16" %}
4360   interface(REG_INTER);
4361 %}
4362 
4363 operand rscratch1RegP() %{
4364   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4365   match(iRegPdst);
4366   format %{ "R11" %}
4367   interface(REG_INTER);
4368 %}
4369 
4370 operand rscratch2RegP() %{
4371   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4372   match(iRegPdst);
4373   format %{ %}
4374   interface(REG_INTER);
4375 %}
4376 
4377 operand rarg1RegP() %{
4378   constraint(ALLOC_IN_RC(rarg1_bits64_reg));
4379   match(iRegPdst);
4380   format %{ %}
4381   interface(REG_INTER);
4382 %}
4383 
4384 operand rarg2RegP() %{
4385   constraint(ALLOC_IN_RC(rarg2_bits64_reg));
4386   match(iRegPdst);
4387   format %{ %}
4388   interface(REG_INTER);
4389 %}
4390 
4391 operand rarg3RegP() %{
4392   constraint(ALLOC_IN_RC(rarg3_bits64_reg));
4393   match(iRegPdst);
4394   format %{ %}
4395   interface(REG_INTER);
4396 %}
4397 
4398 operand rarg4RegP() %{
4399   constraint(ALLOC_IN_RC(rarg4_bits64_reg));
4400   match(iRegPdst);
4401   format %{ %}
4402   interface(REG_INTER);
4403 %}
4404 
4405 operand iRegNsrc() %{
4406   constraint(ALLOC_IN_RC(bits32_reg_ro));
4407   match(RegN);
4408   match(iRegNdst);
4409 
4410   format %{ %}
4411   interface(REG_INTER);
4412 %}
4413 
4414 operand iRegNdst() %{
4415   constraint(ALLOC_IN_RC(bits32_reg_rw));
4416   match(RegN);
4417 
4418   format %{ %}
4419   interface(REG_INTER);
4420 %}
4421 
4422 // Long Destination Register
4423 // See definition of reg_class bits64_reg_rw.
4424 operand iRegLdst() %{
4425   constraint(ALLOC_IN_RC(bits64_reg_rw));
4426   match(RegL);
4427   match(rscratch1RegL);
4428   match(rscratch2RegL);
4429   format %{ %}
4430   interface(REG_INTER);
4431 %}
4432 
4433 // Long Source Register
4434 // See definition of reg_class bits64_reg_ro.
4435 operand iRegLsrc() %{
4436   constraint(ALLOC_IN_RC(bits64_reg_ro));
4437   match(RegL);
4438   match(iRegLdst);
4439   match(rscratch1RegL);
4440   match(rscratch2RegL);
4441   format %{ %}
4442   interface(REG_INTER);
4443 %}
4444 
4445 // Special operand for ConvL2I.
4446 operand iRegL2Isrc(iRegLsrc reg) %{
4447   constraint(ALLOC_IN_RC(bits64_reg_ro));
4448   match(ConvL2I reg);
4449   format %{ "ConvL2I($reg)" %}
4450   interface(REG_INTER)
4451 %}
4452 
4453 operand rscratch1RegL() %{
4454   constraint(ALLOC_IN_RC(rscratch1_bits64_reg));
4455   match(RegL);
4456   format %{ %}
4457   interface(REG_INTER);
4458 %}
4459 
4460 operand rscratch2RegL() %{
4461   constraint(ALLOC_IN_RC(rscratch2_bits64_reg));
4462   match(RegL);
4463   format %{ %}
4464   interface(REG_INTER);
4465 %}
4466 
4467 // Condition Code Flag Registers
4468 operand flagsReg() %{
4469   constraint(ALLOC_IN_RC(int_flags));
4470   match(RegFlags);
4471   format %{ %}
4472   interface(REG_INTER);
4473 %}
4474 
4475 operand flagsRegSrc() %{
4476   constraint(ALLOC_IN_RC(int_flags_ro));
4477   match(RegFlags);
4478   match(flagsReg);
4479   match(flagsRegCR0);
4480   format %{ %}
4481   interface(REG_INTER);
4482 %}
4483 
4484 // Condition Code Flag Register CR0
4485 operand flagsRegCR0() %{
4486   constraint(ALLOC_IN_RC(int_flags_CR0));
4487   match(RegFlags);
4488   format %{ "CR0" %}
4489   interface(REG_INTER);
4490 %}
4491 
4492 operand flagsRegCR1() %{
4493   constraint(ALLOC_IN_RC(int_flags_CR1));
4494   match(RegFlags);
4495   format %{ "CR1" %}
4496   interface(REG_INTER);
4497 %}
4498 
4499 operand flagsRegCR6() %{
4500   constraint(ALLOC_IN_RC(int_flags_CR6));
4501   match(RegFlags);
4502   format %{ "CR6" %}
4503   interface(REG_INTER);
4504 %}
4505 
4506 operand regCTR() %{
4507   constraint(ALLOC_IN_RC(ctr_reg));
4508   // RegFlags should work. Introducing a RegSpecial type would cause a
4509   // lot of changes.
4510   match(RegFlags);
4511   format %{"SR_CTR" %}
4512   interface(REG_INTER);
4513 %}
4514 
4515 operand regD() %{
4516   constraint(ALLOC_IN_RC(dbl_reg));
4517   match(RegD);
4518   format %{ %}
4519   interface(REG_INTER);
4520 %}
4521 
4522 operand regF() %{
4523   constraint(ALLOC_IN_RC(flt_reg));
4524   match(RegF);
4525   format %{ %}
4526   interface(REG_INTER);
4527 %}
4528 
4529 // Special Registers
4530 
4531 // Method Register
4532 operand inline_cache_regP(iRegPdst reg) %{
4533   constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg
4534   match(reg);
4535   format %{ %}
4536   interface(REG_INTER);
4537 %}
4538 
4539 operand compiler_method_oop_regP(iRegPdst reg) %{
4540   constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg
4541   match(reg);
4542   format %{ %}
4543   interface(REG_INTER);
4544 %}
4545 
4546 operand interpreter_method_oop_regP(iRegPdst reg) %{
4547   constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg
4548   match(reg);
4549   format %{ %}
4550   interface(REG_INTER);
4551 %}
4552 
4553 // Operands to remove register moves in unscaled mode.
4554 // Match read/write registers with an EncodeP node if neither shift nor add are required.
4555 operand iRegP2N(iRegPsrc reg) %{
4556   predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0);
4557   constraint(ALLOC_IN_RC(bits64_reg_ro));
4558   match(EncodeP reg);
4559   format %{ "$reg" %}
4560   interface(REG_INTER)
4561 %}
4562 
4563 operand iRegN2P(iRegNsrc reg) %{
4564   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4565   constraint(ALLOC_IN_RC(bits32_reg_ro));
4566   match(DecodeN reg);
4567   format %{ "$reg" %}
4568   interface(REG_INTER)
4569 %}
4570 
4571 operand iRegN2P_klass(iRegNsrc reg) %{
4572   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4573   constraint(ALLOC_IN_RC(bits32_reg_ro));
4574   match(DecodeNKlass reg);
4575   format %{ "$reg" %}
4576   interface(REG_INTER)
4577 %}
4578 
4579 //----------Complex Operands---------------------------------------------------
4580 // Indirect Memory Reference
4581 operand indirect(iRegPsrc reg) %{
4582   constraint(ALLOC_IN_RC(bits64_reg_ro));
4583   match(reg);
4584   op_cost(100);
4585   format %{ "[$reg]" %}
4586   interface(MEMORY_INTER) %{
4587     base($reg);
4588     index(0x0);
4589     scale(0x0);
4590     disp(0x0);
4591   %}
4592 %}
4593 
4594 // Indirect with Offset
4595 operand indOffset16(iRegPsrc reg, immL16 offset) %{
4596   constraint(ALLOC_IN_RC(bits64_reg_ro));
4597   match(AddP reg offset);
4598   op_cost(100);
4599   format %{ "[$reg + $offset]" %}
4600   interface(MEMORY_INTER) %{
4601     base($reg);
4602     index(0x0);
4603     scale(0x0);
4604     disp($offset);
4605   %}
4606 %}
4607 
4608 // Indirect with 4-aligned Offset
4609 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{
4610   constraint(ALLOC_IN_RC(bits64_reg_ro));
4611   match(AddP reg offset);
4612   op_cost(100);
4613   format %{ "[$reg + $offset]" %}
4614   interface(MEMORY_INTER) %{
4615     base($reg);
4616     index(0x0);
4617     scale(0x0);
4618     disp($offset);
4619   %}
4620 %}
4621 
4622 //----------Complex Operands for Compressed OOPs-------------------------------
4623 // Compressed OOPs with narrow_oop_shift == 0.
4624 
4625 // Indirect Memory Reference, compressed OOP
4626 operand indirectNarrow(iRegNsrc reg) %{
4627   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4628   constraint(ALLOC_IN_RC(bits64_reg_ro));
4629   match(DecodeN reg);
4630   op_cost(100);
4631   format %{ "[$reg]" %}
4632   interface(MEMORY_INTER) %{
4633     base($reg);
4634     index(0x0);
4635     scale(0x0);
4636     disp(0x0);
4637   %}
4638 %}
4639 
4640 operand indirectNarrow_klass(iRegNsrc reg) %{
4641   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4642   constraint(ALLOC_IN_RC(bits64_reg_ro));
4643   match(DecodeNKlass reg);
4644   op_cost(100);
4645   format %{ "[$reg]" %}
4646   interface(MEMORY_INTER) %{
4647     base($reg);
4648     index(0x0);
4649     scale(0x0);
4650     disp(0x0);
4651   %}
4652 %}
4653 
4654 // Indirect with Offset, compressed OOP
4655 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{
4656   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4657   constraint(ALLOC_IN_RC(bits64_reg_ro));
4658   match(AddP (DecodeN reg) offset);
4659   op_cost(100);
4660   format %{ "[$reg + $offset]" %}
4661   interface(MEMORY_INTER) %{
4662     base($reg);
4663     index(0x0);
4664     scale(0x0);
4665     disp($offset);
4666   %}
4667 %}
4668 
4669 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{
4670   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4671   constraint(ALLOC_IN_RC(bits64_reg_ro));
4672   match(AddP (DecodeNKlass reg) offset);
4673   op_cost(100);
4674   format %{ "[$reg + $offset]" %}
4675   interface(MEMORY_INTER) %{
4676     base($reg);
4677     index(0x0);
4678     scale(0x0);
4679     disp($offset);
4680   %}
4681 %}
4682 
4683 // Indirect with 4-aligned Offset, compressed OOP
4684 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{
4685   predicate(false /* TODO: PPC port MatchDecodeNodes*/);
4686   constraint(ALLOC_IN_RC(bits64_reg_ro));
4687   match(AddP (DecodeN reg) offset);
4688   op_cost(100);
4689   format %{ "[$reg + $offset]" %}
4690   interface(MEMORY_INTER) %{
4691     base($reg);
4692     index(0x0);
4693     scale(0x0);
4694     disp($offset);
4695   %}
4696 %}
4697 
4698 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{
4699   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0);
4700   constraint(ALLOC_IN_RC(bits64_reg_ro));
4701   match(AddP (DecodeNKlass reg) offset);
4702   op_cost(100);
4703   format %{ "[$reg + $offset]" %}
4704   interface(MEMORY_INTER) %{
4705     base($reg);
4706     index(0x0);
4707     scale(0x0);
4708     disp($offset);
4709   %}
4710 %}
4711 
4712 //----------Special Memory Operands--------------------------------------------
4713 // Stack Slot Operand
4714 //
4715 // This operand is used for loading and storing temporary values on
4716 // the stack where a match requires a value to flow through memory.
4717 operand stackSlotI(sRegI reg) %{
4718   constraint(ALLOC_IN_RC(stack_slots));
4719   op_cost(100);
4720   //match(RegI);
4721   format %{ "[sp+$reg]" %}
4722   interface(MEMORY_INTER) %{
4723     base(0x1);   // R1_SP
4724     index(0x0);
4725     scale(0x0);
4726     disp($reg);  // Stack Offset
4727   %}
4728 %}
4729 
4730 operand stackSlotL(sRegL reg) %{
4731   constraint(ALLOC_IN_RC(stack_slots));
4732   op_cost(100);
4733   //match(RegL);
4734   format %{ "[sp+$reg]" %}
4735   interface(MEMORY_INTER) %{
4736     base(0x1);   // R1_SP
4737     index(0x0);
4738     scale(0x0);
4739     disp($reg);  // Stack Offset
4740   %}
4741 %}
4742 
4743 operand stackSlotP(sRegP reg) %{
4744   constraint(ALLOC_IN_RC(stack_slots));
4745   op_cost(100);
4746   //match(RegP);
4747   format %{ "[sp+$reg]" %}
4748   interface(MEMORY_INTER) %{
4749     base(0x1);   // R1_SP
4750     index(0x0);
4751     scale(0x0);
4752     disp($reg);  // Stack Offset
4753   %}
4754 %}
4755 
4756 operand stackSlotF(sRegF reg) %{
4757   constraint(ALLOC_IN_RC(stack_slots));
4758   op_cost(100);
4759   //match(RegF);
4760   format %{ "[sp+$reg]" %}
4761   interface(MEMORY_INTER) %{
4762     base(0x1);   // R1_SP
4763     index(0x0);
4764     scale(0x0);
4765     disp($reg);  // Stack Offset
4766   %}
4767 %}
4768 
4769 operand stackSlotD(sRegD reg) %{
4770   constraint(ALLOC_IN_RC(stack_slots));
4771   op_cost(100);
4772   //match(RegD);
4773   format %{ "[sp+$reg]" %}
4774   interface(MEMORY_INTER) %{
4775     base(0x1);   // R1_SP
4776     index(0x0);
4777     scale(0x0);
4778     disp($reg);  // Stack Offset
4779   %}
4780 %}
4781 
4782 // Operands for expressing Control Flow
4783 // NOTE: Label is a predefined operand which should not be redefined in
4784 //       the AD file. It is generically handled within the ADLC.
4785 
4786 //----------Conditional Branch Operands----------------------------------------
4787 // Comparison Op
4788 //
4789 // This is the operation of the comparison, and is limited to the
4790 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE
4791 // (!=).
4792 //
4793 // Other attributes of the comparison, such as unsignedness, are specified
4794 // by the comparison instruction that sets a condition code flags register.
4795 // That result is represented by a flags operand whose subtype is appropriate
4796 // to the unsignedness (etc.) of the comparison.
4797 //
4798 // Later, the instruction which matches both the Comparison Op (a Bool) and
4799 // the flags (produced by the Cmp) specifies the coding of the comparison op
4800 // by matching a specific subtype of Bool operand below.
4801 
4802 // When used for floating point comparisons: unordered same as less.
4803 operand cmpOp() %{
4804   match(Bool);
4805   format %{ "" %}
4806   interface(COND_INTER) %{
4807                            // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'.
4808                            //           BO          &  BI
4809     equal(0xA);            // 10 10:   bcondCRbiIs1 & Condition::equal
4810     not_equal(0x2);        // 00 10:   bcondCRbiIs0 & Condition::equal
4811     less(0x8);             // 10 00:   bcondCRbiIs1 & Condition::less
4812     greater_equal(0x0);    // 00 00:   bcondCRbiIs0 & Condition::less
4813     less_equal(0x1);       // 00 01:   bcondCRbiIs0 & Condition::greater
4814     greater(0x9);          // 10 01:   bcondCRbiIs1 & Condition::greater
4815     overflow(0xB);         // 10 11:   bcondCRbiIs1 & Condition::summary_overflow
4816     no_overflow(0x3);      // 00 11:   bcondCRbiIs0 & Condition::summary_overflow
4817   %}
4818 %}
4819 
4820 //----------OPERAND CLASSES----------------------------------------------------
4821 // Operand Classes are groups of operands that are used to simplify
4822 // instruction definitions by not requiring the AD writer to specify
4823 // seperate instructions for every form of operand when the
4824 // instruction accepts multiple operand types with the same basic
4825 // encoding and format. The classic case of this is memory operands.
4826 // Indirect is not included since its use is limited to Compare & Swap.
4827 
4828 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass);
4829 // Memory operand where offsets are 4-aligned. Required for ld, std.
4830 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass);
4831 opclass indirectMemory(indirect, indirectNarrow);
4832 
4833 // Special opclass for I and ConvL2I.
4834 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc);
4835 
4836 // Operand classes to match encode and decode. iRegN_P2N is only used
4837 // for storeN. I have never seen an encode node elsewhere.
4838 opclass iRegN_P2N(iRegNsrc, iRegP2N);
4839 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass);
4840 
4841 //----------PIPELINE-----------------------------------------------------------
4842 
4843 pipeline %{
4844 
4845 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM
4846 // J. Res. & Dev., No. 1, Jan. 2002.
4847 
4848 //----------ATTRIBUTES---------------------------------------------------------
4849 attributes %{
4850 
4851   // Power4 instructions are of fixed length.
4852   fixed_size_instructions;
4853 
4854   // TODO: if `bundle' means number of instructions fetched
4855   // per cycle, this is 8. If `bundle' means Power4 `group', that is
4856   // max instructions issued per cycle, this is 5.
4857   max_instructions_per_bundle = 8;
4858 
4859   // A Power4 instruction is 4 bytes long.
4860   instruction_unit_size = 4;
4861 
4862   // The Power4 processor fetches 64 bytes...
4863   instruction_fetch_unit_size = 64;
4864 
4865   // ...in one line
4866   instruction_fetch_units = 1
4867 
4868   // Unused, list one so that array generated by adlc is not empty.
4869   // Aix compiler chokes if _nop_count = 0.
4870   nops(fxNop);
4871 %}
4872 
4873 //----------RESOURCES----------------------------------------------------------
4874 // Resources are the functional units available to the machine
4875 resources(
4876    PPC_BR,         // branch unit
4877    PPC_CR,         // condition unit
4878    PPC_FX1,        // integer arithmetic unit 1
4879    PPC_FX2,        // integer arithmetic unit 2
4880    PPC_LDST1,      // load/store unit 1
4881    PPC_LDST2,      // load/store unit 2
4882    PPC_FP1,        // float arithmetic unit 1
4883    PPC_FP2,        // float arithmetic unit 2
4884    PPC_LDST = PPC_LDST1 | PPC_LDST2,
4885    PPC_FX = PPC_FX1 | PPC_FX2,
4886    PPC_FP = PPC_FP1 | PPC_FP2
4887  );
4888 
4889 //----------PIPELINE DESCRIPTION-----------------------------------------------
4890 // Pipeline Description specifies the stages in the machine's pipeline
4891 pipe_desc(
4892    // Power4 longest pipeline path
4893    PPC_IF,   // instruction fetch
4894    PPC_IC,
4895    //PPC_BP, // branch prediction
4896    PPC_D0,   // decode
4897    PPC_D1,   // decode
4898    PPC_D2,   // decode
4899    PPC_D3,   // decode
4900    PPC_Xfer1,
4901    PPC_GD,   // group definition
4902    PPC_MP,   // map
4903    PPC_ISS,  // issue
4904    PPC_RF,   // resource fetch
4905    PPC_EX1,  // execute (all units)
4906    PPC_EX2,  // execute (FP, LDST)
4907    PPC_EX3,  // execute (FP, LDST)
4908    PPC_EX4,  // execute (FP)
4909    PPC_EX5,  // execute (FP)
4910    PPC_EX6,  // execute (FP)
4911    PPC_WB,   // write back
4912    PPC_Xfer2,
4913    PPC_CP
4914  );
4915 
4916 //----------PIPELINE CLASSES---------------------------------------------------
4917 // Pipeline Classes describe the stages in which input and output are
4918 // referenced by the hardware pipeline.
4919 
4920 // Simple pipeline classes.
4921 
4922 // Default pipeline class.
4923 pipe_class pipe_class_default() %{
4924   single_instruction;
4925   fixed_latency(2);
4926 %}
4927 
4928 // Pipeline class for empty instructions.
4929 pipe_class pipe_class_empty() %{
4930   single_instruction;
4931   fixed_latency(0);
4932 %}
4933 
4934 // Pipeline class for compares.
4935 pipe_class pipe_class_compare() %{
4936   single_instruction;
4937   fixed_latency(16);
4938 %}
4939 
4940 // Pipeline class for traps.
4941 pipe_class pipe_class_trap() %{
4942   single_instruction;
4943   fixed_latency(100);
4944 %}
4945 
4946 // Pipeline class for memory operations.
4947 pipe_class pipe_class_memory() %{
4948   single_instruction;
4949   fixed_latency(16);
4950 %}
4951 
4952 // Pipeline class for call.
4953 pipe_class pipe_class_call() %{
4954   single_instruction;
4955   fixed_latency(100);
4956 %}
4957 
4958 // Define the class for the Nop node.
4959 define %{
4960    MachNop = pipe_class_default;
4961 %}
4962 
4963 %}
4964 
4965 //----------INSTRUCTIONS-------------------------------------------------------
4966 
4967 // Naming of instructions:
4968 //   opA_operB / opA_operB_operC:
4969 //     Operation 'op' with one or two source operands 'oper'. Result
4970 //     type is A, source operand types are B and C.
4971 //     Iff A == B == C, B and C are left out.
4972 //
4973 // The instructions are ordered according to the following scheme:
4974 //  - loads
4975 //  - load constants
4976 //  - prefetch
4977 //  - store
4978 //  - encode/decode
4979 //  - membar
4980 //  - conditional moves
4981 //  - compare & swap
4982 //  - arithmetic and logic operations
4983 //    * int: Add, Sub, Mul, Div, Mod
4984 //    * int: lShift, arShift, urShift, rot
4985 //    * float: Add, Sub, Mul, Div
4986 //    * and, or, xor ...
4987 //  - register moves: float <-> int, reg <-> stack, repl
4988 //  - cast (high level type cast, XtoP, castPP, castII, not_null etc.
4989 //  - conv (low level type cast requiring bit changes (sign extend etc)
4990 //  - compares, range & zero checks.
4991 //  - branches
4992 //  - complex operations, intrinsics, min, max, replicate
4993 //  - lock
4994 //  - Calls
4995 //
4996 // If there are similar instructions with different types they are sorted:
4997 // int before float
4998 // small before big
4999 // signed before unsigned
5000 // e.g., loadS before loadUS before loadI before loadF.
5001 
5002 
5003 //----------Load/Store Instructions--------------------------------------------
5004 
5005 //----------Load Instructions--------------------------------------------------
5006 
5007 // Converts byte to int.
5008 // As convB2I_reg, but without match rule.  The match rule of convB2I_reg
5009 // reuses the 'amount' operand, but adlc expects that operand specification
5010 // and operands in match rule are equivalent.
5011 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{
5012   effect(DEF dst, USE src);
5013   format %{ "EXTSB   $dst, $src \t// byte->int" %}
5014   size(4);
5015   ins_encode %{
5016     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
5017     __ extsb($dst$$Register, $src$$Register);
5018   %}
5019   ins_pipe(pipe_class_default);
5020 %}
5021 
5022 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{
5023   // match-rule, false predicate
5024   match(Set dst (LoadB mem));
5025   predicate(false);
5026 
5027   format %{ "LBZ     $dst, $mem" %}
5028   size(4);
5029   ins_encode( enc_lbz(dst, mem) );
5030   ins_pipe(pipe_class_memory);
5031 %}
5032 
5033 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{
5034   // match-rule, false predicate
5035   match(Set dst (LoadB mem));
5036   predicate(false);
5037 
5038   format %{ "LBZ     $dst, $mem\n\t"
5039             "TWI     $dst\n\t"
5040             "ISYNC" %}
5041   size(12);
5042   ins_encode( enc_lbz_ac(dst, mem) );
5043   ins_pipe(pipe_class_memory);
5044 %}
5045 
5046 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5047 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{
5048   match(Set dst (LoadB mem));
5049   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5050   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5051   expand %{
5052     iRegIdst tmp;
5053     loadUB_indirect(tmp, mem);
5054     convB2I_reg_2(dst, tmp);
5055   %}
5056 %}
5057 
5058 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{
5059   match(Set dst (LoadB mem));
5060   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5061   expand %{
5062     iRegIdst tmp;
5063     loadUB_indirect_ac(tmp, mem);
5064     convB2I_reg_2(dst, tmp);
5065   %}
5066 %}
5067 
5068 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{
5069   // match-rule, false predicate
5070   match(Set dst (LoadB mem));
5071   predicate(false);
5072 
5073   format %{ "LBZ     $dst, $mem" %}
5074   size(4);
5075   ins_encode( enc_lbz(dst, mem) );
5076   ins_pipe(pipe_class_memory);
5077 %}
5078 
5079 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{
5080   // match-rule, false predicate
5081   match(Set dst (LoadB mem));
5082   predicate(false);
5083 
5084   format %{ "LBZ     $dst, $mem\n\t"
5085             "TWI     $dst\n\t"
5086             "ISYNC" %}
5087   size(12);
5088   ins_encode( enc_lbz_ac(dst, mem) );
5089   ins_pipe(pipe_class_memory);
5090 %}
5091 
5092 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B.
5093 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{
5094   match(Set dst (LoadB mem));
5095   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5096   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5097 
5098   expand %{
5099     iRegIdst tmp;
5100     loadUB_indOffset16(tmp, mem);
5101     convB2I_reg_2(dst, tmp);
5102   %}
5103 %}
5104 
5105 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{
5106   match(Set dst (LoadB mem));
5107   ins_cost(3*MEMORY_REF_COST + DEFAULT_COST);
5108 
5109   expand %{
5110     iRegIdst tmp;
5111     loadUB_indOffset16_ac(tmp, mem);
5112     convB2I_reg_2(dst, tmp);
5113   %}
5114 %}
5115 
5116 // Load Unsigned Byte (8bit UNsigned) into an int reg.
5117 instruct loadUB(iRegIdst dst, memory mem) %{
5118   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5119   match(Set dst (LoadUB mem));
5120   ins_cost(MEMORY_REF_COST);
5121 
5122   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int" %}
5123   size(4);
5124   ins_encode( enc_lbz(dst, mem) );
5125   ins_pipe(pipe_class_memory);
5126 %}
5127 
5128 // Load  Unsigned Byte (8bit UNsigned) acquire.
5129 instruct loadUB_ac(iRegIdst dst, memory mem) %{
5130   match(Set dst (LoadUB mem));
5131   ins_cost(3*MEMORY_REF_COST);
5132 
5133   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to int, acquire\n\t"
5134             "TWI     $dst\n\t"
5135             "ISYNC" %}
5136   size(12);
5137   ins_encode( enc_lbz_ac(dst, mem) );
5138   ins_pipe(pipe_class_memory);
5139 %}
5140 
5141 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
5142 instruct loadUB2L(iRegLdst dst, memory mem) %{
5143   match(Set dst (ConvI2L (LoadUB mem)));
5144   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5145   ins_cost(MEMORY_REF_COST);
5146 
5147   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long" %}
5148   size(4);
5149   ins_encode( enc_lbz(dst, mem) );
5150   ins_pipe(pipe_class_memory);
5151 %}
5152 
5153 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{
5154   match(Set dst (ConvI2L (LoadUB mem)));
5155   ins_cost(3*MEMORY_REF_COST);
5156 
5157   format %{ "LBZ     $dst, $mem \t// byte, zero-extend to long, acquire\n\t"
5158             "TWI     $dst\n\t"
5159             "ISYNC" %}
5160   size(12);
5161   ins_encode( enc_lbz_ac(dst, mem) );
5162   ins_pipe(pipe_class_memory);
5163 %}
5164 
5165 // Load Short (16bit signed)
5166 instruct loadS(iRegIdst dst, memory mem) %{
5167   match(Set dst (LoadS mem));
5168   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5169   ins_cost(MEMORY_REF_COST);
5170 
5171   format %{ "LHA     $dst, $mem" %}
5172   size(4);
5173   ins_encode %{
5174     // TODO: PPC port $archOpcode(ppc64Opcode_lha);
5175     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5176     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5177   %}
5178   ins_pipe(pipe_class_memory);
5179 %}
5180 
5181 // Load Short (16bit signed) acquire.
5182 instruct loadS_ac(iRegIdst dst, memory mem) %{
5183   match(Set dst (LoadS mem));
5184   ins_cost(3*MEMORY_REF_COST);
5185 
5186   format %{ "LHA     $dst, $mem\t acquire\n\t"
5187             "TWI     $dst\n\t"
5188             "ISYNC" %}
5189   size(12);
5190   ins_encode %{
5191     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5192     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5193     __ lha($dst$$Register, Idisp, $mem$$base$$Register);
5194     __ twi_0($dst$$Register);
5195     __ isync();
5196   %}
5197   ins_pipe(pipe_class_memory);
5198 %}
5199 
5200 // Load Char (16bit unsigned)
5201 instruct loadUS(iRegIdst dst, memory mem) %{
5202   match(Set dst (LoadUS mem));
5203   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5204   ins_cost(MEMORY_REF_COST);
5205 
5206   format %{ "LHZ     $dst, $mem" %}
5207   size(4);
5208   ins_encode( enc_lhz(dst, mem) );
5209   ins_pipe(pipe_class_memory);
5210 %}
5211 
5212 // Load Char (16bit unsigned) acquire.
5213 instruct loadUS_ac(iRegIdst dst, memory mem) %{
5214   match(Set dst (LoadUS mem));
5215   ins_cost(3*MEMORY_REF_COST);
5216 
5217   format %{ "LHZ     $dst, $mem \t// acquire\n\t"
5218             "TWI     $dst\n\t"
5219             "ISYNC" %}
5220   size(12);
5221   ins_encode( enc_lhz_ac(dst, mem) );
5222   ins_pipe(pipe_class_memory);
5223 %}
5224 
5225 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
5226 instruct loadUS2L(iRegLdst dst, memory mem) %{
5227   match(Set dst (ConvI2L (LoadUS mem)));
5228   predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf));
5229   ins_cost(MEMORY_REF_COST);
5230 
5231   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long" %}
5232   size(4);
5233   ins_encode( enc_lhz(dst, mem) );
5234   ins_pipe(pipe_class_memory);
5235 %}
5236 
5237 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire.
5238 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{
5239   match(Set dst (ConvI2L (LoadUS mem)));
5240   ins_cost(3*MEMORY_REF_COST);
5241 
5242   format %{ "LHZ     $dst, $mem \t// short, zero-extend to long, acquire\n\t"
5243             "TWI     $dst\n\t"
5244             "ISYNC" %}
5245   size(12);
5246   ins_encode( enc_lhz_ac(dst, mem) );
5247   ins_pipe(pipe_class_memory);
5248 %}
5249 
5250 // Load Integer.
5251 instruct loadI(iRegIdst dst, memory mem) %{
5252   match(Set dst (LoadI mem));
5253   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5254   ins_cost(MEMORY_REF_COST);
5255 
5256   format %{ "LWZ     $dst, $mem" %}
5257   size(4);
5258   ins_encode( enc_lwz(dst, mem) );
5259   ins_pipe(pipe_class_memory);
5260 %}
5261 
5262 // Load Integer acquire.
5263 instruct loadI_ac(iRegIdst dst, memory mem) %{
5264   match(Set dst (LoadI mem));
5265   ins_cost(3*MEMORY_REF_COST);
5266 
5267   format %{ "LWZ     $dst, $mem \t// load acquire\n\t"
5268             "TWI     $dst\n\t"
5269             "ISYNC" %}
5270   size(12);
5271   ins_encode( enc_lwz_ac(dst, mem) );
5272   ins_pipe(pipe_class_memory);
5273 %}
5274 
5275 // Match loading integer and casting it to unsigned int in
5276 // long register.
5277 // LoadI + ConvI2L + AndL 0xffffffff.
5278 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{
5279   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5280   predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered());
5281   ins_cost(MEMORY_REF_COST);
5282 
5283   format %{ "LWZ     $dst, $mem \t// zero-extend to long" %}
5284   size(4);
5285   ins_encode( enc_lwz(dst, mem) );
5286   ins_pipe(pipe_class_memory);
5287 %}
5288 
5289 // Match loading integer and casting it to long.
5290 instruct loadI2L(iRegLdst dst, memoryAlg4 mem) %{
5291   match(Set dst (ConvI2L (LoadI mem)));
5292   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5293   ins_cost(MEMORY_REF_COST);
5294 
5295   format %{ "LWA     $dst, $mem \t// loadI2L" %}
5296   size(4);
5297   ins_encode %{
5298     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5299     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5300     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5301   %}
5302   ins_pipe(pipe_class_memory);
5303 %}
5304 
5305 // Match loading integer and casting it to long - acquire.
5306 instruct loadI2L_ac(iRegLdst dst, memoryAlg4 mem) %{
5307   match(Set dst (ConvI2L (LoadI mem)));
5308   ins_cost(3*MEMORY_REF_COST);
5309 
5310   format %{ "LWA     $dst, $mem \t// loadI2L acquire"
5311             "TWI     $dst\n\t"
5312             "ISYNC" %}
5313   size(12);
5314   ins_encode %{
5315     // TODO: PPC port $archOpcode(ppc64Opcode_lwa);
5316     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5317     __ lwa($dst$$Register, Idisp, $mem$$base$$Register);
5318     __ twi_0($dst$$Register);
5319     __ isync();
5320   %}
5321   ins_pipe(pipe_class_memory);
5322 %}
5323 
5324 // Load Long - aligned
5325 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{
5326   match(Set dst (LoadL mem));
5327   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5328   ins_cost(MEMORY_REF_COST);
5329 
5330   format %{ "LD      $dst, $mem \t// long" %}
5331   size(4);
5332   ins_encode( enc_ld(dst, mem) );
5333   ins_pipe(pipe_class_memory);
5334 %}
5335 
5336 // Load Long - aligned acquire.
5337 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{
5338   match(Set dst (LoadL mem));
5339   ins_cost(3*MEMORY_REF_COST);
5340 
5341   format %{ "LD      $dst, $mem \t// long acquire\n\t"
5342             "TWI     $dst\n\t"
5343             "ISYNC" %}
5344   size(12);
5345   ins_encode( enc_ld_ac(dst, mem) );
5346   ins_pipe(pipe_class_memory);
5347 %}
5348 
5349 // Load Long - UNaligned
5350 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{
5351   match(Set dst (LoadL_unaligned mem));
5352   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5353   ins_cost(MEMORY_REF_COST);
5354 
5355   format %{ "LD      $dst, $mem \t// unaligned long" %}
5356   size(4);
5357   ins_encode( enc_ld(dst, mem) );
5358   ins_pipe(pipe_class_memory);
5359 %}
5360 
5361 // Load nodes for superwords
5362 
5363 // Load Aligned Packed Byte
5364 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{
5365   predicate(n->as_LoadVector()->memory_size() == 8);
5366   match(Set dst (LoadVector mem));
5367   ins_cost(MEMORY_REF_COST);
5368 
5369   format %{ "LD      $dst, $mem \t// load 8-byte Vector" %}
5370   size(4);
5371   ins_encode( enc_ld(dst, mem) );
5372   ins_pipe(pipe_class_memory);
5373 %}
5374 
5375 // Load Range, range = array length (=jint)
5376 instruct loadRange(iRegIdst dst, memory mem) %{
5377   match(Set dst (LoadRange mem));
5378   ins_cost(MEMORY_REF_COST);
5379 
5380   format %{ "LWZ     $dst, $mem \t// range" %}
5381   size(4);
5382   ins_encode( enc_lwz(dst, mem) );
5383   ins_pipe(pipe_class_memory);
5384 %}
5385 
5386 // Load Compressed Pointer
5387 instruct loadN(iRegNdst dst, memory mem) %{
5388   match(Set dst (LoadN mem));
5389   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5390   ins_cost(MEMORY_REF_COST);
5391 
5392   format %{ "LWZ     $dst, $mem \t// load compressed ptr" %}
5393   size(4);
5394   ins_encode( enc_lwz(dst, mem) );
5395   ins_pipe(pipe_class_memory);
5396 %}
5397 
5398 // Load Compressed Pointer acquire.
5399 instruct loadN_ac(iRegNdst dst, memory mem) %{
5400   match(Set dst (LoadN mem));
5401   ins_cost(3*MEMORY_REF_COST);
5402 
5403   format %{ "LWZ     $dst, $mem \t// load acquire compressed ptr\n\t"
5404             "TWI     $dst\n\t"
5405             "ISYNC" %}
5406   size(12);
5407   ins_encode( enc_lwz_ac(dst, mem) );
5408   ins_pipe(pipe_class_memory);
5409 %}
5410 
5411 // Load Compressed Pointer and decode it if narrow_oop_shift == 0.
5412 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{
5413   match(Set dst (DecodeN (LoadN mem)));
5414   predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0);
5415   ins_cost(MEMORY_REF_COST);
5416 
5417   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5418   size(4);
5419   ins_encode( enc_lwz(dst, mem) );
5420   ins_pipe(pipe_class_memory);
5421 %}
5422 
5423 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{
5424   match(Set dst (DecodeNKlass (LoadNKlass mem)));
5425   predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 &&
5426             _kids[0]->_leaf->as_Load()->is_unordered());
5427   ins_cost(MEMORY_REF_COST);
5428 
5429   format %{ "LWZ     $dst, $mem \t// DecodeN (unscaled)" %}
5430   size(4);
5431   ins_encode( enc_lwz(dst, mem) );
5432   ins_pipe(pipe_class_memory);
5433 %}
5434 
5435 // Load Pointer
5436 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{
5437   match(Set dst (LoadP mem));
5438   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5439   ins_cost(MEMORY_REF_COST);
5440 
5441   format %{ "LD      $dst, $mem \t// ptr" %}
5442   size(4);
5443   ins_encode( enc_ld(dst, mem) );
5444   ins_pipe(pipe_class_memory);
5445 %}
5446 
5447 // Load Pointer acquire.
5448 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{
5449   match(Set dst (LoadP mem));
5450   ins_cost(3*MEMORY_REF_COST);
5451 
5452   format %{ "LD      $dst, $mem \t// ptr acquire\n\t"
5453             "TWI     $dst\n\t"
5454             "ISYNC" %}
5455   size(12);
5456   ins_encode( enc_ld_ac(dst, mem) );
5457   ins_pipe(pipe_class_memory);
5458 %}
5459 
5460 // LoadP + CastP2L
5461 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{
5462   match(Set dst (CastP2X (LoadP mem)));
5463   predicate(_kids[0]->_leaf->as_Load()->is_unordered());
5464   ins_cost(MEMORY_REF_COST);
5465 
5466   format %{ "LD      $dst, $mem \t// ptr + p2x" %}
5467   size(4);
5468   ins_encode( enc_ld(dst, mem) );
5469   ins_pipe(pipe_class_memory);
5470 %}
5471 
5472 // Load compressed klass pointer.
5473 instruct loadNKlass(iRegNdst dst, memory mem) %{
5474   match(Set dst (LoadNKlass mem));
5475   ins_cost(MEMORY_REF_COST);
5476 
5477   format %{ "LWZ     $dst, $mem \t// compressed klass ptr" %}
5478   size(4);
5479   ins_encode( enc_lwz(dst, mem) );
5480   ins_pipe(pipe_class_memory);
5481 %}
5482 
5483 // Load Klass Pointer
5484 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{
5485   match(Set dst (LoadKlass mem));
5486   ins_cost(MEMORY_REF_COST);
5487 
5488   format %{ "LD      $dst, $mem \t// klass ptr" %}
5489   size(4);
5490   ins_encode( enc_ld(dst, mem) );
5491   ins_pipe(pipe_class_memory);
5492 %}
5493 
5494 // Load Float
5495 instruct loadF(regF dst, memory mem) %{
5496   match(Set dst (LoadF mem));
5497   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5498   ins_cost(MEMORY_REF_COST);
5499 
5500   format %{ "LFS     $dst, $mem" %}
5501   size(4);
5502   ins_encode %{
5503     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
5504     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5505     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5506   %}
5507   ins_pipe(pipe_class_memory);
5508 %}
5509 
5510 // Load Float acquire.
5511 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{
5512   match(Set dst (LoadF mem));
5513   effect(TEMP cr0);
5514   ins_cost(3*MEMORY_REF_COST);
5515 
5516   format %{ "LFS     $dst, $mem \t// acquire\n\t"
5517             "FCMPU   cr0, $dst, $dst\n\t"
5518             "BNE     cr0, next\n"
5519             "next:\n\t"
5520             "ISYNC" %}
5521   size(16);
5522   ins_encode %{
5523     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5524     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5525     Label next;
5526     __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5527     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5528     __ bne(CCR0, next);
5529     __ bind(next);
5530     __ isync();
5531   %}
5532   ins_pipe(pipe_class_memory);
5533 %}
5534 
5535 // Load Double - aligned
5536 instruct loadD(regD dst, memory mem) %{
5537   match(Set dst (LoadD mem));
5538   predicate(n->as_Load()->is_unordered() || followed_by_acquire(n));
5539   ins_cost(MEMORY_REF_COST);
5540 
5541   format %{ "LFD     $dst, $mem" %}
5542   size(4);
5543   ins_encode( enc_lfd(dst, mem) );
5544   ins_pipe(pipe_class_memory);
5545 %}
5546 
5547 // Load Double - aligned acquire.
5548 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{
5549   match(Set dst (LoadD mem));
5550   effect(TEMP cr0);
5551   ins_cost(3*MEMORY_REF_COST);
5552 
5553   format %{ "LFD     $dst, $mem \t// acquire\n\t"
5554             "FCMPU   cr0, $dst, $dst\n\t"
5555             "BNE     cr0, next\n"
5556             "next:\n\t"
5557             "ISYNC" %}
5558   size(16);
5559   ins_encode %{
5560     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5561     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
5562     Label next;
5563     __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register);
5564     __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister);
5565     __ bne(CCR0, next);
5566     __ bind(next);
5567     __ isync();
5568   %}
5569   ins_pipe(pipe_class_memory);
5570 %}
5571 
5572 // Load Double - UNaligned
5573 instruct loadD_unaligned(regD dst, memory mem) %{
5574   match(Set dst (LoadD_unaligned mem));
5575   // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense).
5576   ins_cost(MEMORY_REF_COST);
5577 
5578   format %{ "LFD     $dst, $mem" %}
5579   size(4);
5580   ins_encode( enc_lfd(dst, mem) );
5581   ins_pipe(pipe_class_memory);
5582 %}
5583 
5584 //----------Constants--------------------------------------------------------
5585 
5586 // Load MachConstantTableBase: add hi offset to global toc.
5587 // TODO: Handle hidden register r29 in bundler!
5588 instruct loadToc_hi(iRegLdst dst) %{
5589   effect(DEF dst);
5590   ins_cost(DEFAULT_COST);
5591 
5592   format %{ "ADDIS   $dst, R29, DISP.hi \t// load TOC hi" %}
5593   size(4);
5594   ins_encode %{
5595     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5596     __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc());
5597   %}
5598   ins_pipe(pipe_class_default);
5599 %}
5600 
5601 // Load MachConstantTableBase: add lo offset to global toc.
5602 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{
5603   effect(DEF dst, USE src);
5604   ins_cost(DEFAULT_COST);
5605 
5606   format %{ "ADDI    $dst, $src, DISP.lo \t// load TOC lo" %}
5607   size(4);
5608   ins_encode %{
5609     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5610     __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc());
5611   %}
5612   ins_pipe(pipe_class_default);
5613 %}
5614 
5615 // Load 16-bit integer constant 0xssss????
5616 instruct loadConI16(iRegIdst dst, immI16 src) %{
5617   match(Set dst src);
5618 
5619   format %{ "LI      $dst, $src" %}
5620   size(4);
5621   ins_encode %{
5622     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5623     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
5624   %}
5625   ins_pipe(pipe_class_default);
5626 %}
5627 
5628 // Load integer constant 0x????0000
5629 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{
5630   match(Set dst src);
5631   ins_cost(DEFAULT_COST);
5632 
5633   format %{ "LIS     $dst, $src.hi" %}
5634   size(4);
5635   ins_encode %{
5636     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5637     // Lis sign extends 16-bit src then shifts it 16 bit to the left.
5638     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5639   %}
5640   ins_pipe(pipe_class_default);
5641 %}
5642 
5643 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted
5644 // and sign extended), this adds the low 16 bits.
5645 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
5646   // no match-rule, false predicate
5647   effect(DEF dst, USE src1, USE src2);
5648   predicate(false);
5649 
5650   format %{ "ORI     $dst, $src1.hi, $src2.lo" %}
5651   size(4);
5652   ins_encode %{
5653     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5654     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5655   %}
5656   ins_pipe(pipe_class_default);
5657 %}
5658 
5659 instruct loadConI_Ex(iRegIdst dst, immI src) %{
5660   match(Set dst src);
5661   ins_cost(DEFAULT_COST*2);
5662 
5663   expand %{
5664     // Would like to use $src$$constant.
5665     immI16 srcLo %{ _opnds[1]->constant() %}
5666     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5667     immIhi16 srcHi %{ _opnds[1]->constant() %}
5668     iRegIdst tmpI;
5669     loadConIhi16(tmpI, srcHi);
5670     loadConI32_lo16(dst, tmpI, srcLo);
5671   %}
5672 %}
5673 
5674 // No constant pool entries required.
5675 instruct loadConL16(iRegLdst dst, immL16 src) %{
5676   match(Set dst src);
5677 
5678   format %{ "LI      $dst, $src \t// long" %}
5679   size(4);
5680   ins_encode %{
5681     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5682     __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF)));
5683   %}
5684   ins_pipe(pipe_class_default);
5685 %}
5686 
5687 // Load long constant 0xssssssss????0000
5688 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{
5689   match(Set dst src);
5690   ins_cost(DEFAULT_COST);
5691 
5692   format %{ "LIS     $dst, $src.hi \t// long" %}
5693   size(4);
5694   ins_encode %{
5695     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5696     __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16)));
5697   %}
5698   ins_pipe(pipe_class_default);
5699 %}
5700 
5701 // To load a 32 bit constant: merge lower 16 bits into already loaded
5702 // high 16 bits.
5703 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
5704   // no match-rule, false predicate
5705   effect(DEF dst, USE src1, USE src2);
5706   predicate(false);
5707 
5708   format %{ "ORI     $dst, $src1, $src2.lo" %}
5709   size(4);
5710   ins_encode %{
5711     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5712     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
5713   %}
5714   ins_pipe(pipe_class_default);
5715 %}
5716 
5717 // Load 32-bit long constant
5718 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{
5719   match(Set dst src);
5720   ins_cost(DEFAULT_COST*2);
5721 
5722   expand %{
5723     // Would like to use $src$$constant.
5724     immL16     srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%}
5725     // srcHi can be 0000 if srcLo sign-extends to a negative number.
5726     immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%}
5727     iRegLdst tmpL;
5728     loadConL32hi16(tmpL, srcHi);
5729     loadConL32_lo16(dst, tmpL, srcLo);
5730   %}
5731 %}
5732 
5733 // Load long constant 0x????000000000000.
5734 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{
5735   match(Set dst src);
5736   ins_cost(DEFAULT_COST);
5737 
5738   expand %{
5739     immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%}
5740     immI shift32 %{ 32 %}
5741     iRegLdst tmpL;
5742     loadConL32hi16(tmpL, srcHi);
5743     lshiftL_regL_immI(dst, tmpL, shift32);
5744   %}
5745 %}
5746 
5747 // Expand node for constant pool load: small offset.
5748 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{
5749   effect(DEF dst, USE src, USE toc);
5750   ins_cost(MEMORY_REF_COST);
5751 
5752   ins_num_consts(1);
5753   // Needed so that CallDynamicJavaDirect can compute the address of this
5754   // instruction for relocation.
5755   ins_field_cbuf_insts_offset(int);
5756 
5757   format %{ "LD      $dst, offset, $toc \t// load long $src from TOC" %}
5758   size(4);
5759   ins_encode( enc_load_long_constL(dst, src, toc) );
5760   ins_pipe(pipe_class_memory);
5761 %}
5762 
5763 // Expand node for constant pool load: large offset.
5764 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{
5765   effect(DEF dst, USE src, USE toc);
5766   predicate(false);
5767 
5768   ins_num_consts(1);
5769   ins_field_const_toc_offset(int);
5770   // Needed so that CallDynamicJavaDirect can compute the address of this
5771   // instruction for relocation.
5772   ins_field_cbuf_insts_offset(int);
5773 
5774   format %{ "ADDIS   $dst, $toc, offset \t// load long $src from TOC (hi)" %}
5775   size(4);
5776   ins_encode( enc_load_long_constL_hi(dst, toc, src) );
5777   ins_pipe(pipe_class_default);
5778 %}
5779 
5780 // Expand node for constant pool load: large offset.
5781 // No constant pool entries required.
5782 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{
5783   effect(DEF dst, USE src, USE base);
5784   predicate(false);
5785 
5786   ins_field_const_toc_offset_hi_node(loadConL_hiNode*);
5787 
5788   format %{ "LD      $dst, offset, $base \t// load long $src from TOC (lo)" %}
5789   size(4);
5790   ins_encode %{
5791     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
5792     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
5793     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
5794   %}
5795   ins_pipe(pipe_class_memory);
5796 %}
5797 
5798 // Load long constant from constant table. Expand in case of
5799 // offset > 16 bit is needed.
5800 // Adlc adds toc node MachConstantTableBase.
5801 instruct loadConL_Ex(iRegLdst dst, immL src) %{
5802   match(Set dst src);
5803   ins_cost(MEMORY_REF_COST);
5804 
5805   format %{ "LD      $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %}
5806   // We can not inline the enc_class for the expand as that does not support constanttablebase.
5807   postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) );
5808 %}
5809 
5810 // Load NULL as compressed oop.
5811 instruct loadConN0(iRegNdst dst, immN_0 src) %{
5812   match(Set dst src);
5813   ins_cost(DEFAULT_COST);
5814 
5815   format %{ "LI      $dst, $src \t// compressed ptr" %}
5816   size(4);
5817   ins_encode %{
5818     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5819     __ li($dst$$Register, 0);
5820   %}
5821   ins_pipe(pipe_class_default);
5822 %}
5823 
5824 // Load hi part of compressed oop constant.
5825 instruct loadConN_hi(iRegNdst dst, immN src) %{
5826   effect(DEF dst, USE src);
5827   ins_cost(DEFAULT_COST);
5828 
5829   format %{ "LIS     $dst, $src \t// narrow oop hi" %}
5830   size(4);
5831   ins_encode %{
5832     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5833     __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff));
5834   %}
5835   ins_pipe(pipe_class_default);
5836 %}
5837 
5838 // Add lo part of compressed oop constant to already loaded hi part.
5839 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{
5840   effect(DEF dst, USE src1, USE src2);
5841   ins_cost(DEFAULT_COST);
5842 
5843   format %{ "ORI     $dst, $src1, $src2 \t// narrow oop lo" %}
5844   size(4);
5845   ins_encode %{
5846     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
5847     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5848     int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant);
5849     RelocationHolder rspec = oop_Relocation::spec(oop_index);
5850     __ relocate(rspec, 1);
5851     __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff);
5852   %}
5853   ins_pipe(pipe_class_default);
5854 %}
5855 
5856 instruct rldicl(iRegLdst dst, iRegLsrc src, immI16 shift, immI16 mask_begin) %{
5857   effect(DEF dst, USE src, USE shift, USE mask_begin);
5858 
5859   size(4);
5860   ins_encode %{
5861     __ rldicl($dst$$Register, $src$$Register, $shift$$constant, $mask_begin$$constant);
5862   %}
5863   ins_pipe(pipe_class_default);
5864 %}
5865 
5866 // Needed to postalloc expand loadConN: ConN is loaded as ConI
5867 // leaving the upper 32 bits with sign-extension bits.
5868 // This clears these bits: dst = src & 0xFFFFFFFF.
5869 // TODO: Eventually call this maskN_regN_FFFFFFFF.
5870 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{
5871   effect(DEF dst, USE src);
5872   predicate(false);
5873 
5874   format %{ "MASK    $dst, $src, 0xFFFFFFFF" %} // mask
5875   size(4);
5876   ins_encode %{
5877     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5878     __ clrldi($dst$$Register, $src$$Register, 0x20);
5879   %}
5880   ins_pipe(pipe_class_default);
5881 %}
5882 
5883 // Optimize DecodeN for disjoint base.
5884 // Load base of compressed oops into a register
5885 instruct loadBase(iRegLdst dst) %{
5886   effect(DEF dst);
5887 
5888   format %{ "LoadConst $dst, heapbase" %}
5889   ins_encode %{
5890     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
5891     __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0);
5892   %}
5893   ins_pipe(pipe_class_default);
5894 %}
5895 
5896 // Loading ConN must be postalloc expanded so that edges between
5897 // the nodes are safe. They may not interfere with a safepoint.
5898 // GL TODO: This needs three instructions: better put this into the constant pool.
5899 instruct loadConN_Ex(iRegNdst dst, immN src) %{
5900   match(Set dst src);
5901   ins_cost(DEFAULT_COST*2);
5902 
5903   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
5904   postalloc_expand %{
5905     MachNode *m1 = new loadConN_hiNode();
5906     MachNode *m2 = new loadConN_loNode();
5907     MachNode *m3 = new clearMs32bNode();
5908     m1->add_req(NULL);
5909     m2->add_req(NULL, m1);
5910     m3->add_req(NULL, m2);
5911     m1->_opnds[0] = op_dst;
5912     m1->_opnds[1] = op_src;
5913     m2->_opnds[0] = op_dst;
5914     m2->_opnds[1] = op_dst;
5915     m2->_opnds[2] = op_src;
5916     m3->_opnds[0] = op_dst;
5917     m3->_opnds[1] = op_dst;
5918     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5919     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5920     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5921     nodes->push(m1);
5922     nodes->push(m2);
5923     nodes->push(m3);
5924   %}
5925 %}
5926 
5927 // We have seen a safepoint between the hi and lo parts, and this node was handled
5928 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is
5929 // not a narrow oop.
5930 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{
5931   match(Set dst src);
5932   effect(DEF dst, USE src);
5933   ins_cost(DEFAULT_COST);
5934 
5935   format %{ "LIS     $dst, $src \t// narrow klass hi" %}
5936   size(4);
5937   ins_encode %{
5938     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
5939     intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant);
5940     __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff));
5941   %}
5942   ins_pipe(pipe_class_default);
5943 %}
5944 
5945 // As loadConNKlass_hi this must be recognized as narrow klass, not oop!
5946 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
5947   match(Set dst src1);
5948   effect(TEMP src2);
5949   ins_cost(DEFAULT_COST);
5950 
5951   format %{ "MASK    $dst, $src2, 0xFFFFFFFF" %} // mask
5952   size(4);
5953   ins_encode %{
5954     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
5955     __ clrldi($dst$$Register, $src2$$Register, 0x20);
5956   %}
5957   ins_pipe(pipe_class_default);
5958 %}
5959 
5960 // This needs a match rule so that build_oop_map knows this is
5961 // not a narrow oop.
5962 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{
5963   match(Set dst src1);
5964   effect(TEMP src2);
5965   ins_cost(DEFAULT_COST);
5966 
5967   format %{ "ORI     $dst, $src1, $src2 \t// narrow klass lo" %}
5968   size(4);
5969   ins_encode %{
5970     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
5971     intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant);
5972     assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder");
5973     int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant);
5974     RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5975 
5976     __ relocate(rspec, 1);
5977     __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff);
5978   %}
5979   ins_pipe(pipe_class_default);
5980 %}
5981 
5982 // Loading ConNKlass must be postalloc expanded so that edges between
5983 // the nodes are safe. They may not interfere with a safepoint.
5984 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{
5985   match(Set dst src);
5986   ins_cost(DEFAULT_COST*2);
5987 
5988   format %{ "LoadN   $dst, $src \t// postalloc expanded" %} // mask
5989   postalloc_expand %{
5990     // Load high bits into register. Sign extended.
5991     MachNode *m1 = new loadConNKlass_hiNode();
5992     m1->add_req(NULL);
5993     m1->_opnds[0] = op_dst;
5994     m1->_opnds[1] = op_src;
5995     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
5996     nodes->push(m1);
5997 
5998     MachNode *m2 = m1;
5999     if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) {
6000       // Value might be 1-extended. Mask out these bits.
6001       m2 = new loadConNKlass_maskNode();
6002       m2->add_req(NULL, m1);
6003       m2->_opnds[0] = op_dst;
6004       m2->_opnds[1] = op_src;
6005       m2->_opnds[2] = op_dst;
6006       ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6007       nodes->push(m2);
6008     }
6009 
6010     MachNode *m3 = new loadConNKlass_loNode();
6011     m3->add_req(NULL, m2);
6012     m3->_opnds[0] = op_dst;
6013     m3->_opnds[1] = op_src;
6014     m3->_opnds[2] = op_dst;
6015     ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6016     nodes->push(m3);
6017   %}
6018 %}
6019 
6020 // 0x1 is used in object initialization (initial object header).
6021 // No constant pool entries required.
6022 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{
6023   match(Set dst src);
6024 
6025   format %{ "LI      $dst, $src \t// ptr" %}
6026   size(4);
6027   ins_encode %{
6028     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
6029     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
6030   %}
6031   ins_pipe(pipe_class_default);
6032 %}
6033 
6034 // Expand node for constant pool load: small offset.
6035 // The match rule is needed to generate the correct bottom_type(),
6036 // however this node should never match. The use of predicate is not
6037 // possible since ADLC forbids predicates for chain rules. The higher
6038 // costs do not prevent matching in this case. For that reason the
6039 // operand immP_NM with predicate(false) is used.
6040 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6041   match(Set dst src);
6042   effect(TEMP toc);
6043 
6044   ins_num_consts(1);
6045 
6046   format %{ "LD      $dst, offset, $toc \t// load ptr $src from TOC" %}
6047   size(4);
6048   ins_encode( enc_load_long_constP(dst, src, toc) );
6049   ins_pipe(pipe_class_memory);
6050 %}
6051 
6052 // Expand node for constant pool load: large offset.
6053 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{
6054   effect(DEF dst, USE src, USE toc);
6055   predicate(false);
6056 
6057   ins_num_consts(1);
6058   ins_field_const_toc_offset(int);
6059 
6060   format %{ "ADDIS   $dst, $toc, offset \t// load ptr $src from TOC (hi)" %}
6061   size(4);
6062   ins_encode( enc_load_long_constP_hi(dst, src, toc) );
6063   ins_pipe(pipe_class_default);
6064 %}
6065 
6066 // Expand node for constant pool load: large offset.
6067 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{
6068   match(Set dst src);
6069   effect(TEMP base);
6070 
6071   ins_field_const_toc_offset_hi_node(loadConP_hiNode*);
6072 
6073   format %{ "LD      $dst, offset, $base \t// load ptr $src from TOC (lo)" %}
6074   size(4);
6075   ins_encode %{
6076     // TODO: PPC port $archOpcode(ppc64Opcode_ld);
6077     int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset;
6078     __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register);
6079   %}
6080   ins_pipe(pipe_class_memory);
6081 %}
6082 
6083 // Load pointer constant from constant table. Expand in case an
6084 // offset > 16 bit is needed.
6085 // Adlc adds toc node MachConstantTableBase.
6086 instruct loadConP_Ex(iRegPdst dst, immP src) %{
6087   match(Set dst src);
6088   ins_cost(MEMORY_REF_COST);
6089 
6090   // This rule does not use "expand" because then
6091   // the result type is not known to be an Oop.  An ADLC
6092   // enhancement will be needed to make that work - not worth it!
6093 
6094   // If this instruction rematerializes, it prolongs the live range
6095   // of the toc node, causing illegal graphs.
6096   // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule().
6097   ins_cannot_rematerialize(true);
6098 
6099   format %{ "LD    $dst, offset, $constanttablebase \t//  load ptr $src from table, postalloc expanded" %}
6100   postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) );
6101 %}
6102 
6103 // Expand node for constant pool load: small offset.
6104 instruct loadConF(regF dst, immF src, iRegLdst toc) %{
6105   effect(DEF dst, USE src, USE toc);
6106   ins_cost(MEMORY_REF_COST);
6107 
6108   ins_num_consts(1);
6109 
6110   format %{ "LFS     $dst, offset, $toc \t// load float $src from TOC" %}
6111   size(4);
6112   ins_encode %{
6113     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
6114     address float_address = __ float_constant($src$$constant);
6115     if (float_address == NULL) {
6116       ciEnv::current()->record_out_of_memory_failure();
6117       return;
6118     }
6119     __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register);
6120   %}
6121   ins_pipe(pipe_class_memory);
6122 %}
6123 
6124 // Expand node for constant pool load: large offset.
6125 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{
6126   effect(DEF dst, USE src, USE toc);
6127   ins_cost(MEMORY_REF_COST);
6128 
6129   ins_num_consts(1);
6130 
6131   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6132             "LFS     $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t"
6133             "ADDIS   $toc, $toc, -offset_hi"%}
6134   size(12);
6135   ins_encode %{
6136     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6137     FloatRegister Rdst    = $dst$$FloatRegister;
6138     Register Rtoc         = $toc$$Register;
6139     address float_address = __ float_constant($src$$constant);
6140     if (float_address == NULL) {
6141       ciEnv::current()->record_out_of_memory_failure();
6142       return;
6143     }
6144     int offset            = __ offset_to_method_toc(float_address);
6145     int hi = (offset + (1<<15))>>16;
6146     int lo = offset - hi * (1<<16);
6147 
6148     __ addis(Rtoc, Rtoc, hi);
6149     __ lfs(Rdst, lo, Rtoc);
6150     __ addis(Rtoc, Rtoc, -hi);
6151   %}
6152   ins_pipe(pipe_class_memory);
6153 %}
6154 
6155 // Adlc adds toc node MachConstantTableBase.
6156 instruct loadConF_Ex(regF dst, immF src) %{
6157   match(Set dst src);
6158   ins_cost(MEMORY_REF_COST);
6159 
6160   // See loadConP.
6161   ins_cannot_rematerialize(true);
6162 
6163   format %{ "LFS     $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6164   postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) );
6165 %}
6166 
6167 // Expand node for constant pool load: small offset.
6168 instruct loadConD(regD dst, immD src, iRegLdst toc) %{
6169   effect(DEF dst, USE src, USE toc);
6170   ins_cost(MEMORY_REF_COST);
6171 
6172   ins_num_consts(1);
6173 
6174   format %{ "LFD     $dst, offset, $toc \t// load double $src from TOC" %}
6175   size(4);
6176   ins_encode %{
6177     // TODO: PPC port $archOpcode(ppc64Opcode_lfd);
6178     address float_address = __ double_constant($src$$constant);
6179     if (float_address == NULL) {
6180       ciEnv::current()->record_out_of_memory_failure();
6181       return;
6182     }
6183     int offset =  __ offset_to_method_toc(float_address);
6184     __ lfd($dst$$FloatRegister, offset, $toc$$Register);
6185   %}
6186   ins_pipe(pipe_class_memory);
6187 %}
6188 
6189 // Expand node for constant pool load: large offset.
6190 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{
6191   effect(DEF dst, USE src, USE toc);
6192   ins_cost(MEMORY_REF_COST);
6193 
6194   ins_num_consts(1);
6195 
6196   format %{ "ADDIS   $toc, $toc, offset_hi\n\t"
6197             "LFD     $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t"
6198             "ADDIS   $toc, $toc, -offset_hi" %}
6199   size(12);
6200   ins_encode %{
6201     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6202     FloatRegister Rdst    = $dst$$FloatRegister;
6203     Register      Rtoc    = $toc$$Register;
6204     address float_address = __ double_constant($src$$constant);
6205     if (float_address == NULL) {
6206       ciEnv::current()->record_out_of_memory_failure();
6207       return;
6208     }
6209     int offset = __ offset_to_method_toc(float_address);
6210     int hi = (offset + (1<<15))>>16;
6211     int lo = offset - hi * (1<<16);
6212 
6213     __ addis(Rtoc, Rtoc, hi);
6214     __ lfd(Rdst, lo, Rtoc);
6215     __ addis(Rtoc, Rtoc, -hi);
6216   %}
6217   ins_pipe(pipe_class_memory);
6218 %}
6219 
6220 // Adlc adds toc node MachConstantTableBase.
6221 instruct loadConD_Ex(regD dst, immD src) %{
6222   match(Set dst src);
6223   ins_cost(MEMORY_REF_COST);
6224 
6225   // See loadConP.
6226   ins_cannot_rematerialize(true);
6227 
6228   format %{ "ConD    $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %}
6229   postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) );
6230 %}
6231 
6232 // Prefetch instructions.
6233 // Must be safe to execute with invalid address (cannot fault).
6234 
6235 // Special prefetch versions which use the dcbz instruction.
6236 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{
6237   match(PrefetchAllocation (AddP mem src));
6238   predicate(AllocatePrefetchStyle == 3);
6239   ins_cost(MEMORY_REF_COST);
6240 
6241   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %}
6242   size(4);
6243   ins_encode %{
6244     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6245     __ dcbz($src$$Register, $mem$$base$$Register);
6246   %}
6247   ins_pipe(pipe_class_memory);
6248 %}
6249 
6250 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{
6251   match(PrefetchAllocation mem);
6252   predicate(AllocatePrefetchStyle == 3);
6253   ins_cost(MEMORY_REF_COST);
6254 
6255   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %}
6256   size(4);
6257   ins_encode %{
6258     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6259     __ dcbz($mem$$base$$Register);
6260   %}
6261   ins_pipe(pipe_class_memory);
6262 %}
6263 
6264 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{
6265   match(PrefetchAllocation (AddP mem src));
6266   predicate(AllocatePrefetchStyle != 3);
6267   ins_cost(MEMORY_REF_COST);
6268 
6269   format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %}
6270   size(4);
6271   ins_encode %{
6272     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6273     __ dcbtst($src$$Register, $mem$$base$$Register);
6274   %}
6275   ins_pipe(pipe_class_memory);
6276 %}
6277 
6278 instruct prefetch_alloc_no_offset(indirectMemory mem) %{
6279   match(PrefetchAllocation mem);
6280   predicate(AllocatePrefetchStyle != 3);
6281   ins_cost(MEMORY_REF_COST);
6282 
6283   format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %}
6284   size(4);
6285   ins_encode %{
6286     // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst);
6287     __ dcbtst($mem$$base$$Register);
6288   %}
6289   ins_pipe(pipe_class_memory);
6290 %}
6291 
6292 //----------Store Instructions-------------------------------------------------
6293 
6294 // Store Byte
6295 instruct storeB(memory mem, iRegIsrc src) %{
6296   match(Set mem (StoreB mem src));
6297   ins_cost(MEMORY_REF_COST);
6298 
6299   format %{ "STB     $src, $mem \t// byte" %}
6300   size(4);
6301   ins_encode %{
6302     // TODO: PPC port $archOpcode(ppc64Opcode_stb);
6303     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6304     __ stb($src$$Register, Idisp, $mem$$base$$Register);
6305   %}
6306   ins_pipe(pipe_class_memory);
6307 %}
6308 
6309 // Store Char/Short
6310 instruct storeC(memory mem, iRegIsrc src) %{
6311   match(Set mem (StoreC mem src));
6312   ins_cost(MEMORY_REF_COST);
6313 
6314   format %{ "STH     $src, $mem \t// short" %}
6315   size(4);
6316   ins_encode %{
6317     // TODO: PPC port $archOpcode(ppc64Opcode_sth);
6318     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
6319     __ sth($src$$Register, Idisp, $mem$$base$$Register);
6320   %}
6321   ins_pipe(pipe_class_memory);
6322 %}
6323 
6324 // Store Integer
6325 instruct storeI(memory mem, iRegIsrc src) %{
6326   match(Set mem (StoreI mem src));
6327   ins_cost(MEMORY_REF_COST);
6328 
6329   format %{ "STW     $src, $mem" %}
6330   size(4);
6331   ins_encode( enc_stw(src, mem) );
6332   ins_pipe(pipe_class_memory);
6333 %}
6334 
6335 // ConvL2I + StoreI.
6336 instruct storeI_convL2I(memory mem, iRegLsrc src) %{
6337   match(Set mem (StoreI mem (ConvL2I src)));
6338   ins_cost(MEMORY_REF_COST);
6339 
6340   format %{ "STW     l2i($src), $mem" %}
6341   size(4);
6342   ins_encode( enc_stw(src, mem) );
6343   ins_pipe(pipe_class_memory);
6344 %}
6345 
6346 // Store Long
6347 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{
6348   match(Set mem (StoreL mem src));
6349   ins_cost(MEMORY_REF_COST);
6350 
6351   format %{ "STD     $src, $mem \t// long" %}
6352   size(4);
6353   ins_encode( enc_std(src, mem) );
6354   ins_pipe(pipe_class_memory);
6355 %}
6356 
6357 // Store super word nodes.
6358 
6359 // Store Aligned Packed Byte long register to memory
6360 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{
6361   predicate(n->as_StoreVector()->memory_size() == 8);
6362   match(Set mem (StoreVector mem src));
6363   ins_cost(MEMORY_REF_COST);
6364 
6365   format %{ "STD     $mem, $src \t// packed8B" %}
6366   size(4);
6367   ins_encode( enc_std(src, mem) );
6368   ins_pipe(pipe_class_memory);
6369 %}
6370 
6371 // Store Compressed Oop
6372 instruct storeN(memory dst, iRegN_P2N src) %{
6373   match(Set dst (StoreN dst src));
6374   ins_cost(MEMORY_REF_COST);
6375 
6376   format %{ "STW     $src, $dst \t// compressed oop" %}
6377   size(4);
6378   ins_encode( enc_stw(src, dst) );
6379   ins_pipe(pipe_class_memory);
6380 %}
6381 
6382 // Store Compressed KLass
6383 instruct storeNKlass(memory dst, iRegN_P2N src) %{
6384   match(Set dst (StoreNKlass dst src));
6385   ins_cost(MEMORY_REF_COST);
6386 
6387   format %{ "STW     $src, $dst \t// compressed klass" %}
6388   size(4);
6389   ins_encode( enc_stw(src, dst) );
6390   ins_pipe(pipe_class_memory);
6391 %}
6392 
6393 // Store Pointer
6394 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{
6395   match(Set dst (StoreP dst src));
6396   ins_cost(MEMORY_REF_COST);
6397 
6398   format %{ "STD     $src, $dst \t// ptr" %}
6399   size(4);
6400   ins_encode( enc_std(src, dst) );
6401   ins_pipe(pipe_class_memory);
6402 %}
6403 
6404 // Store Float
6405 instruct storeF(memory mem, regF src) %{
6406   match(Set mem (StoreF mem src));
6407   ins_cost(MEMORY_REF_COST);
6408 
6409   format %{ "STFS    $src, $mem" %}
6410   size(4);
6411   ins_encode( enc_stfs(src, mem) );
6412   ins_pipe(pipe_class_memory);
6413 %}
6414 
6415 // Store Double
6416 instruct storeD(memory mem, regD src) %{
6417   match(Set mem (StoreD mem src));
6418   ins_cost(MEMORY_REF_COST);
6419 
6420   format %{ "STFD    $src, $mem" %}
6421   size(4);
6422   ins_encode( enc_stfd(src, mem) );
6423   ins_pipe(pipe_class_memory);
6424 %}
6425 
6426 //----------Store Instructions With Zeros--------------------------------------
6427 
6428 // Card-mark for CMS garbage collection.
6429 // This cardmark does an optimization so that it must not always
6430 // do a releasing store. For this, it gets the address of
6431 // CMSCollectorCardTableModRefBSExt::_requires_release as input.
6432 // (Using releaseFieldAddr in the match rule is a hack.)
6433 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{
6434   match(Set mem (StoreCM mem releaseFieldAddr));
6435   effect(TEMP crx);
6436   predicate(false);
6437   ins_cost(MEMORY_REF_COST);
6438 
6439   // See loadConP.
6440   ins_cannot_rematerialize(true);
6441 
6442   format %{ "STB     #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %}
6443   ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) );
6444   ins_pipe(pipe_class_memory);
6445 %}
6446 
6447 // Card-mark for CMS garbage collection.
6448 // This cardmark does an optimization so that it must not always
6449 // do a releasing store. For this, it needs the constant address of
6450 // CMSCollectorCardTableModRefBSExt::_requires_release.
6451 // This constant address is split off here by expand so we can use
6452 // adlc / matcher functionality to load it from the constant section.
6453 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{
6454   match(Set mem (StoreCM mem zero));
6455   predicate(UseConcMarkSweepGC);
6456 
6457   expand %{
6458     immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %}
6459     iRegLdst releaseFieldAddress;
6460     flagsReg crx;
6461     loadConL_Ex(releaseFieldAddress, baseImm);
6462     storeCM_CMS(mem, releaseFieldAddress, crx);
6463   %}
6464 %}
6465 
6466 instruct storeCM_G1(memory mem, immI_0 zero) %{
6467   match(Set mem (StoreCM mem zero));
6468   predicate(UseG1GC);
6469   ins_cost(MEMORY_REF_COST);
6470 
6471   ins_cannot_rematerialize(true);
6472 
6473   format %{ "STB     #0, $mem \t// CMS card-mark byte store (G1)" %}
6474   size(8);
6475   ins_encode %{
6476     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6477     __ li(R0, 0);
6478     //__ release(); // G1: oops are allowed to get visible after dirty marking
6479     guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias");
6480     __ stb(R0, $mem$$disp, $mem$$base$$Register);
6481   %}
6482   ins_pipe(pipe_class_memory);
6483 %}
6484 
6485 // Convert oop pointer into compressed form.
6486 
6487 // Nodes for postalloc expand.
6488 
6489 // Shift node for expand.
6490 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{
6491   // The match rule is needed to make it a 'MachTypeNode'!
6492   match(Set dst (EncodeP src));
6493   predicate(false);
6494 
6495   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6496   size(4);
6497   ins_encode %{
6498     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6499     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6500   %}
6501   ins_pipe(pipe_class_default);
6502 %}
6503 
6504 // Add node for expand.
6505 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{
6506   // The match rule is needed to make it a 'MachTypeNode'!
6507   match(Set dst (EncodeP src));
6508   predicate(false);
6509 
6510   format %{ "SUB     $dst, $src, oop_base \t// encode" %}
6511   ins_encode %{
6512     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6513     __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6514   %}
6515   ins_pipe(pipe_class_default);
6516 %}
6517 
6518 // Conditional sub base.
6519 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6520   // The match rule is needed to make it a 'MachTypeNode'!
6521   match(Set dst (EncodeP (Binary crx src1)));
6522   predicate(false);
6523 
6524   format %{ "BEQ     $crx, done\n\t"
6525             "SUB     $dst, $src1, heapbase \t// encode: subtract base if != NULL\n"
6526             "done:" %}
6527   ins_encode %{
6528     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6529     Label done;
6530     __ beq($crx$$CondRegister, done);
6531     __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0);
6532     __ bind(done);
6533   %}
6534   ins_pipe(pipe_class_default);
6535 %}
6536 
6537 // Power 7 can use isel instruction
6538 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6539   // The match rule is needed to make it a 'MachTypeNode'!
6540   match(Set dst (EncodeP (Binary crx src1)));
6541   predicate(false);
6542 
6543   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %}
6544   size(4);
6545   ins_encode %{
6546     // This is a Power7 instruction for which no machine description exists.
6547     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6548     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6549   %}
6550   ins_pipe(pipe_class_default);
6551 %}
6552 
6553 // Disjoint narrow oop base.
6554 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{
6555   match(Set dst (EncodeP src));
6556   predicate(Universe::narrow_oop_base_disjoint());
6557 
6558   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
6559   size(4);
6560   ins_encode %{
6561     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6562     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32);
6563   %}
6564   ins_pipe(pipe_class_default);
6565 %}
6566 
6567 // shift != 0, base != 0
6568 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{
6569   match(Set dst (EncodeP src));
6570   effect(TEMP crx);
6571   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull &&
6572             Universe::narrow_oop_shift() != 0 &&
6573             Universe::narrow_oop_base_overlaps());
6574 
6575   format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %}
6576   postalloc_expand( postalloc_expand_encode_oop(dst, src, crx));
6577 %}
6578 
6579 // shift != 0, base != 0
6580 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{
6581   match(Set dst (EncodeP src));
6582   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull &&
6583             Universe::narrow_oop_shift() != 0 &&
6584             Universe::narrow_oop_base_overlaps());
6585 
6586   format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %}
6587   postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) );
6588 %}
6589 
6590 // shift != 0, base == 0
6591 // TODO: This is the same as encodeP_shift. Merge!
6592 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{
6593   match(Set dst (EncodeP src));
6594   predicate(Universe::narrow_oop_shift() != 0 &&
6595             Universe::narrow_oop_base() ==0);
6596 
6597   format %{ "SRDI    $dst, $src, #3 \t// encodeP, $src != NULL" %}
6598   size(4);
6599   ins_encode %{
6600     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6601     __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f);
6602   %}
6603   ins_pipe(pipe_class_default);
6604 %}
6605 
6606 // Compressed OOPs with narrow_oop_shift == 0.
6607 // shift == 0, base == 0
6608 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{
6609   match(Set dst (EncodeP src));
6610   predicate(Universe::narrow_oop_shift() == 0);
6611 
6612   format %{ "MR      $dst, $src \t// Ptr->Narrow" %}
6613   // variable size, 0 or 4.
6614   ins_encode %{
6615     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6616     __ mr_if_needed($dst$$Register, $src$$Register);
6617   %}
6618   ins_pipe(pipe_class_default);
6619 %}
6620 
6621 // Decode nodes.
6622 
6623 // Shift node for expand.
6624 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{
6625   // The match rule is needed to make it a 'MachTypeNode'!
6626   match(Set dst (DecodeN src));
6627   predicate(false);
6628 
6629   format %{ "SLDI    $dst, $src, #3 \t// DecodeN" %}
6630   size(4);
6631   ins_encode %{
6632     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6633     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6634   %}
6635   ins_pipe(pipe_class_default);
6636 %}
6637 
6638 // Add node for expand.
6639 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{
6640   // The match rule is needed to make it a 'MachTypeNode'!
6641   match(Set dst (DecodeN src));
6642   predicate(false);
6643 
6644   format %{ "ADD     $dst, $src, heapbase \t// DecodeN, add oop base" %}
6645   ins_encode %{
6646     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6647     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6648   %}
6649   ins_pipe(pipe_class_default);
6650 %}
6651 
6652 // conditianal add base for expand
6653 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{
6654   // The match rule is needed to make it a 'MachTypeNode'!
6655   // NOTICE that the rule is nonsense - we just have to make sure that:
6656   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6657   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6658   match(Set dst (DecodeN (Binary crx src)));
6659   predicate(false);
6660 
6661   format %{ "BEQ     $crx, done\n\t"
6662             "ADD     $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n"
6663             "done:" %}
6664   ins_encode %{
6665     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6666     Label done;
6667     __ beq($crx$$CondRegister, done);
6668     __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0);
6669     __ bind(done);
6670   %}
6671   ins_pipe(pipe_class_default);
6672 %}
6673 
6674 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{
6675   // The match rule is needed to make it a 'MachTypeNode'!
6676   // NOTICE that the rule is nonsense - we just have to make sure that:
6677   //  - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp)
6678   //  - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC.
6679   match(Set dst (DecodeN (Binary crx src1)));
6680   predicate(false);
6681 
6682   format %{ "CMOVE   $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %}
6683   size(4);
6684   ins_encode %{
6685     // This is a Power7 instruction for which no machine description exists.
6686     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
6687     __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register);
6688   %}
6689   ins_pipe(pipe_class_default);
6690 %}
6691 
6692 //  shift != 0, base != 0
6693 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6694   match(Set dst (DecodeN src));
6695   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6696              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6697             Universe::narrow_oop_shift() != 0 &&
6698             Universe::narrow_oop_base() != 0);
6699   ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex.
6700   effect(TEMP crx);
6701 
6702   format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %}
6703   postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) );
6704 %}
6705 
6706 // shift != 0, base == 0
6707 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{
6708   match(Set dst (DecodeN src));
6709   predicate(Universe::narrow_oop_shift() != 0 &&
6710             Universe::narrow_oop_base() == 0);
6711 
6712   format %{ "SLDI    $dst, $src, #3 \t// DecodeN (zerobased)" %}
6713   size(4);
6714   ins_encode %{
6715     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6716     __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift());
6717   %}
6718   ins_pipe(pipe_class_default);
6719 %}
6720 
6721 // Optimize DecodeN for disjoint base.
6722 // Shift narrow oop and or it into register that already contains the heap base.
6723 // Base == dst must hold, and is assured by construction in postaloc_expand.
6724 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{
6725   match(Set dst (DecodeN src));
6726   effect(TEMP base);
6727   predicate(false);
6728 
6729   format %{ "RLDIMI  $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %}
6730   size(4);
6731   ins_encode %{
6732     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
6733     __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift());
6734   %}
6735   ins_pipe(pipe_class_default);
6736 %}
6737 
6738 // Optimize DecodeN for disjoint base.
6739 // This node requires only one cycle on the critical path.
6740 // We must postalloc_expand as we can not express use_def effects where
6741 // the used register is L and the def'ed register P.
6742 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{
6743   match(Set dst (DecodeN src));
6744   effect(TEMP_DEF dst);
6745   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6746              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6747             Universe::narrow_oop_base_disjoint());
6748   ins_cost(DEFAULT_COST);
6749 
6750   format %{ "MOV     $dst, heapbase \t\n"
6751             "RLDIMI  $dst, $src, shift, 32-shift \t// decode with disjoint base" %}
6752   postalloc_expand %{
6753     loadBaseNode *n1 = new loadBaseNode();
6754     n1->add_req(NULL);
6755     n1->_opnds[0] = op_dst;
6756 
6757     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6758     n2->add_req(n_region, n_src, n1);
6759     n2->_opnds[0] = op_dst;
6760     n2->_opnds[1] = op_src;
6761     n2->_opnds[2] = op_dst;
6762     n2->_bottom_type = _bottom_type;
6763 
6764     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6765     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6766 
6767     nodes->push(n1);
6768     nodes->push(n2);
6769   %}
6770 %}
6771 
6772 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{
6773   match(Set dst (DecodeN src));
6774   effect(TEMP_DEF dst, TEMP crx);
6775   predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6776              n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) &&
6777             Universe::narrow_oop_base_disjoint() && VM_Version::has_isel());
6778   ins_cost(3 * DEFAULT_COST);
6779 
6780   format %{ "DecodeN  $dst, $src \t// decode with disjoint base using isel" %}
6781   postalloc_expand %{
6782     loadBaseNode *n1 = new loadBaseNode();
6783     n1->add_req(NULL);
6784     n1->_opnds[0] = op_dst;
6785 
6786     cmpN_reg_imm0Node *n_compare  = new cmpN_reg_imm0Node();
6787     n_compare->add_req(n_region, n_src);
6788     n_compare->_opnds[0] = op_crx;
6789     n_compare->_opnds[1] = op_src;
6790     n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR);
6791 
6792     decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode();
6793     n2->add_req(n_region, n_src, n1);
6794     n2->_opnds[0] = op_dst;
6795     n2->_opnds[1] = op_src;
6796     n2->_opnds[2] = op_dst;
6797     n2->_bottom_type = _bottom_type;
6798 
6799     cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode();
6800     n_cond_set->add_req(n_region, n_compare, n2);
6801     n_cond_set->_opnds[0] = op_dst;
6802     n_cond_set->_opnds[1] = op_crx;
6803     n_cond_set->_opnds[2] = op_dst;
6804     n_cond_set->_bottom_type = _bottom_type;
6805 
6806     assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!");
6807     ra_->set_oop(n_cond_set, true);
6808 
6809     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6810     ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx));
6811     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6812     ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6813 
6814     nodes->push(n1);
6815     nodes->push(n_compare);
6816     nodes->push(n2);
6817     nodes->push(n_cond_set);
6818   %}
6819 %}
6820 
6821 // src != 0, shift != 0, base != 0
6822 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{
6823   match(Set dst (DecodeN src));
6824   predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6825              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
6826             Universe::narrow_oop_shift() != 0 &&
6827             Universe::narrow_oop_base() != 0);
6828   ins_cost(2 * DEFAULT_COST);
6829 
6830   format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %}
6831   postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src));
6832 %}
6833 
6834 // Compressed OOPs with narrow_oop_shift == 0.
6835 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{
6836   match(Set dst (DecodeN src));
6837   predicate(Universe::narrow_oop_shift() == 0);
6838   ins_cost(DEFAULT_COST);
6839 
6840   format %{ "MR      $dst, $src \t// DecodeN (unscaled)" %}
6841   // variable size, 0 or 4.
6842   ins_encode %{
6843     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6844     __ mr_if_needed($dst$$Register, $src$$Register);
6845   %}
6846   ins_pipe(pipe_class_default);
6847 %}
6848 
6849 // Convert compressed oop into int for vectors alignment masking.
6850 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{
6851   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6852   predicate(Universe::narrow_oop_shift() == 0);
6853   ins_cost(DEFAULT_COST);
6854 
6855   format %{ "MR      $dst, $src \t// (int)DecodeN (unscaled)" %}
6856   // variable size, 0 or 4.
6857   ins_encode %{
6858     // TODO: PPC port $archOpcode(ppc64Opcode_or);
6859     __ mr_if_needed($dst$$Register, $src$$Register);
6860   %}
6861   ins_pipe(pipe_class_default);
6862 %}
6863 
6864 // Convert klass pointer into compressed form.
6865 
6866 // Nodes for postalloc expand.
6867 
6868 // Shift node for expand.
6869 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{
6870   // The match rule is needed to make it a 'MachTypeNode'!
6871   match(Set dst (EncodePKlass src));
6872   predicate(false);
6873 
6874   format %{ "SRDI    $dst, $src, 3 \t// encode" %}
6875   size(4);
6876   ins_encode %{
6877     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6878     __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6879   %}
6880   ins_pipe(pipe_class_default);
6881 %}
6882 
6883 // Add node for expand.
6884 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6885   // The match rule is needed to make it a 'MachTypeNode'!
6886   match(Set dst (EncodePKlass (Binary base src)));
6887   predicate(false);
6888 
6889   format %{ "SUB     $dst, $base, $src \t// encode" %}
6890   size(4);
6891   ins_encode %{
6892     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
6893     __ subf($dst$$Register, $base$$Register, $src$$Register);
6894   %}
6895   ins_pipe(pipe_class_default);
6896 %}
6897 
6898 // Disjoint narrow oop base.
6899 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{
6900   match(Set dst (EncodePKlass src));
6901   predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/);
6902 
6903   format %{ "EXTRDI  $dst, $src, #32, #3 \t// encode with disjoint base" %}
6904   size(4);
6905   ins_encode %{
6906     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
6907     __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32);
6908   %}
6909   ins_pipe(pipe_class_default);
6910 %}
6911 
6912 // shift != 0, base != 0
6913 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{
6914   match(Set dst (EncodePKlass (Binary base src)));
6915   predicate(false);
6916 
6917   format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6918   postalloc_expand %{
6919     encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode();
6920     n1->add_req(n_region, n_base, n_src);
6921     n1->_opnds[0] = op_dst;
6922     n1->_opnds[1] = op_base;
6923     n1->_opnds[2] = op_src;
6924     n1->_bottom_type = _bottom_type;
6925 
6926     encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode();
6927     n2->add_req(n_region, n1);
6928     n2->_opnds[0] = op_dst;
6929     n2->_opnds[1] = op_dst;
6930     n2->_bottom_type = _bottom_type;
6931     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6932     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
6933 
6934     nodes->push(n1);
6935     nodes->push(n2);
6936   %}
6937 %}
6938 
6939 // shift != 0, base != 0
6940 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{
6941   match(Set dst (EncodePKlass src));
6942   //predicate(Universe::narrow_klass_shift() != 0 &&
6943   //          true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/);
6944 
6945   //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %}
6946   ins_cost(DEFAULT_COST*2);  // Don't count constant.
6947   expand %{
6948     immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %}
6949     iRegLdst base;
6950     loadConL_Ex(base, baseImm);
6951     encodePKlass_not_null_Ex(dst, base, src);
6952   %}
6953 %}
6954 
6955 // Decode nodes.
6956 
6957 // Shift node for expand.
6958 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{
6959   // The match rule is needed to make it a 'MachTypeNode'!
6960   match(Set dst (DecodeNKlass src));
6961   predicate(false);
6962 
6963   format %{ "SLDI    $dst, $src, #3 \t// DecodeNKlass" %}
6964   size(4);
6965   ins_encode %{
6966     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
6967     __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift());
6968   %}
6969   ins_pipe(pipe_class_default);
6970 %}
6971 
6972 // Add node for expand.
6973 
6974 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{
6975   // The match rule is needed to make it a 'MachTypeNode'!
6976   match(Set dst (DecodeNKlass (Binary base src)));
6977   predicate(false);
6978 
6979   format %{ "ADD     $dst, $base, $src \t// DecodeNKlass, add klass base" %}
6980   size(4);
6981   ins_encode %{
6982     // TODO: PPC port $archOpcode(ppc64Opcode_add);
6983     __ add($dst$$Register, $base$$Register, $src$$Register);
6984   %}
6985   ins_pipe(pipe_class_default);
6986 %}
6987 
6988 // src != 0, shift != 0, base != 0
6989 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{
6990   match(Set dst (DecodeNKlass (Binary base src)));
6991   //effect(kill src); // We need a register for the immediate result after shifting.
6992   predicate(false);
6993 
6994   format %{ "DecodeNKlass $dst =  $base + ($src << 3) \t// $src != NULL, postalloc expanded" %}
6995   postalloc_expand %{
6996     decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode();
6997     n1->add_req(n_region, n_base, n_src);
6998     n1->_opnds[0] = op_dst;
6999     n1->_opnds[1] = op_base;
7000     n1->_opnds[2] = op_src;
7001     n1->_bottom_type = _bottom_type;
7002 
7003     decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode();
7004     n2->add_req(n_region, n1);
7005     n2->_opnds[0] = op_dst;
7006     n2->_opnds[1] = op_dst;
7007     n2->_bottom_type = _bottom_type;
7008 
7009     ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7010     ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this));
7011 
7012     nodes->push(n1);
7013     nodes->push(n2);
7014   %}
7015 %}
7016 
7017 // src != 0, shift != 0, base != 0
7018 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{
7019   match(Set dst (DecodeNKlass src));
7020   // predicate(Universe::narrow_klass_shift() != 0 &&
7021   //           Universe::narrow_klass_base() != 0);
7022 
7023   //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %}
7024 
7025   ins_cost(DEFAULT_COST*2);  // Don't count constant.
7026   expand %{
7027     // We add first, then we shift. Like this, we can get along with one register less.
7028     // But we have to load the base pre-shifted.
7029     immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %}
7030     iRegLdst base;
7031     loadConL_Ex(base, baseImm);
7032     decodeNKlass_notNull_addBase_Ex(dst, base, src);
7033   %}
7034 %}
7035 
7036 //----------MemBar Instructions-----------------------------------------------
7037 // Memory barrier flavors
7038 
7039 instruct membar_acquire() %{
7040   match(LoadFence);
7041   ins_cost(4*MEMORY_REF_COST);
7042 
7043   format %{ "MEMBAR-acquire" %}
7044   size(4);
7045   ins_encode %{
7046     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7047     __ acquire();
7048   %}
7049   ins_pipe(pipe_class_default);
7050 %}
7051 
7052 instruct unnecessary_membar_acquire() %{
7053   match(MemBarAcquire);
7054   ins_cost(0);
7055 
7056   format %{ " -- \t// redundant MEMBAR-acquire - empty" %}
7057   size(0);
7058   ins_encode( /*empty*/ );
7059   ins_pipe(pipe_class_default);
7060 %}
7061 
7062 instruct membar_acquire_lock() %{
7063   match(MemBarAcquireLock);
7064   ins_cost(0);
7065 
7066   format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %}
7067   size(0);
7068   ins_encode( /*empty*/ );
7069   ins_pipe(pipe_class_default);
7070 %}
7071 
7072 instruct membar_release() %{
7073   match(MemBarRelease);
7074   match(StoreFence);
7075   ins_cost(4*MEMORY_REF_COST);
7076 
7077   format %{ "MEMBAR-release" %}
7078   size(4);
7079   ins_encode %{
7080     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7081     __ release();
7082   %}
7083   ins_pipe(pipe_class_default);
7084 %}
7085 
7086 instruct membar_storestore() %{
7087   match(MemBarStoreStore);
7088   ins_cost(4*MEMORY_REF_COST);
7089 
7090   format %{ "MEMBAR-store-store" %}
7091   size(4);
7092   ins_encode %{
7093     // TODO: PPC port $archOpcode(ppc64Opcode_lwsync);
7094     __ membar(Assembler::StoreStore);
7095   %}
7096   ins_pipe(pipe_class_default);
7097 %}
7098 
7099 instruct membar_release_lock() %{
7100   match(MemBarReleaseLock);
7101   ins_cost(0);
7102 
7103   format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %}
7104   size(0);
7105   ins_encode( /*empty*/ );
7106   ins_pipe(pipe_class_default);
7107 %}
7108 
7109 instruct membar_volatile() %{
7110   match(MemBarVolatile);
7111   ins_cost(4*MEMORY_REF_COST);
7112 
7113   format %{ "MEMBAR-volatile" %}
7114   size(4);
7115   ins_encode %{
7116     // TODO: PPC port $archOpcode(ppc64Opcode_sync);
7117     __ fence();
7118   %}
7119   ins_pipe(pipe_class_default);
7120 %}
7121 
7122 // This optimization is wrong on PPC. The following pattern is not supported:
7123 //  MemBarVolatile
7124 //   ^        ^
7125 //   |        |
7126 //  CtrlProj MemProj
7127 //   ^        ^
7128 //   |        |
7129 //   |       Load
7130 //   |
7131 //  MemBarVolatile
7132 //
7133 //  The first MemBarVolatile could get optimized out! According to
7134 //  Vladimir, this pattern can not occur on Oracle platforms.
7135 //  However, it does occur on PPC64 (because of membars in
7136 //  inline_unsafe_load_store).
7137 //
7138 // Add this node again if we found a good solution for inline_unsafe_load_store().
7139 // Don't forget to look at the implementation of post_store_load_barrier again,
7140 // we did other fixes in that method.
7141 //instruct unnecessary_membar_volatile() %{
7142 //  match(MemBarVolatile);
7143 //  predicate(Matcher::post_store_load_barrier(n));
7144 //  ins_cost(0);
7145 //
7146 //  format %{ " -- \t// redundant MEMBAR-volatile - empty" %}
7147 //  size(0);
7148 //  ins_encode( /*empty*/ );
7149 //  ins_pipe(pipe_class_default);
7150 //%}
7151 
7152 instruct membar_CPUOrder() %{
7153   match(MemBarCPUOrder);
7154   ins_cost(0);
7155 
7156   format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %}
7157   size(0);
7158   ins_encode( /*empty*/ );
7159   ins_pipe(pipe_class_default);
7160 %}
7161 
7162 //----------Conditional Move---------------------------------------------------
7163 
7164 // Cmove using isel.
7165 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7166   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7167   predicate(VM_Version::has_isel());
7168   ins_cost(DEFAULT_COST);
7169 
7170   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7171   size(4);
7172   ins_encode %{
7173     // This is a Power7 instruction for which no machine description
7174     // exists. Anyways, the scheduler should be off on Power7.
7175     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7176     int cc        = $cmp$$cmpcode;
7177     __ isel($dst$$Register, $crx$$CondRegister,
7178             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7179   %}
7180   ins_pipe(pipe_class_default);
7181 %}
7182 
7183 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{
7184   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7185   predicate(!VM_Version::has_isel());
7186   ins_cost(DEFAULT_COST+BRANCH_COST);
7187 
7188   ins_variable_size_depending_on_alignment(true);
7189 
7190   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7191   // Worst case is branch + move + stop, no stop without scheduler
7192   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7193   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7194   ins_pipe(pipe_class_default);
7195 %}
7196 
7197 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{
7198   match(Set dst (CMoveI (Binary cmp crx) (Binary dst src)));
7199   ins_cost(DEFAULT_COST+BRANCH_COST);
7200 
7201   ins_variable_size_depending_on_alignment(true);
7202 
7203   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7204   // Worst case is branch + move + stop, no stop without scheduler
7205   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7206   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7207   ins_pipe(pipe_class_default);
7208 %}
7209 
7210 // Cmove using isel.
7211 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7212   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7213   predicate(VM_Version::has_isel());
7214   ins_cost(DEFAULT_COST);
7215 
7216   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7217   size(4);
7218   ins_encode %{
7219     // This is a Power7 instruction for which no machine description
7220     // exists. Anyways, the scheduler should be off on Power7.
7221     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7222     int cc        = $cmp$$cmpcode;
7223     __ isel($dst$$Register, $crx$$CondRegister,
7224             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7225   %}
7226   ins_pipe(pipe_class_default);
7227 %}
7228 
7229 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{
7230   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7231   predicate(!VM_Version::has_isel());
7232   ins_cost(DEFAULT_COST+BRANCH_COST);
7233 
7234   ins_variable_size_depending_on_alignment(true);
7235 
7236   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7237   // Worst case is branch + move + stop, no stop without scheduler.
7238   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7239   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7240   ins_pipe(pipe_class_default);
7241 %}
7242 
7243 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{
7244   match(Set dst (CMoveL (Binary cmp crx) (Binary dst src)));
7245   ins_cost(DEFAULT_COST+BRANCH_COST);
7246 
7247   ins_variable_size_depending_on_alignment(true);
7248 
7249   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7250   // Worst case is branch + move + stop, no stop without scheduler.
7251   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7252   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7253   ins_pipe(pipe_class_default);
7254 %}
7255 
7256 // Cmove using isel.
7257 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7258   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7259   predicate(VM_Version::has_isel());
7260   ins_cost(DEFAULT_COST);
7261 
7262   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7263   size(4);
7264   ins_encode %{
7265     // This is a Power7 instruction for which no machine description
7266     // exists. Anyways, the scheduler should be off on Power7.
7267     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7268     int cc        = $cmp$$cmpcode;
7269     __ isel($dst$$Register, $crx$$CondRegister,
7270             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7271   %}
7272   ins_pipe(pipe_class_default);
7273 %}
7274 
7275 // Conditional move for RegN. Only cmov(reg, reg).
7276 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{
7277   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7278   predicate(!VM_Version::has_isel());
7279   ins_cost(DEFAULT_COST+BRANCH_COST);
7280 
7281   ins_variable_size_depending_on_alignment(true);
7282 
7283   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7284   // Worst case is branch + move + stop, no stop without scheduler.
7285   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7286   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7287   ins_pipe(pipe_class_default);
7288 %}
7289 
7290 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{
7291   match(Set dst (CMoveN (Binary cmp crx) (Binary dst src)));
7292   ins_cost(DEFAULT_COST+BRANCH_COST);
7293 
7294   ins_variable_size_depending_on_alignment(true);
7295 
7296   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7297   // Worst case is branch + move + stop, no stop without scheduler.
7298   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7299   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7300   ins_pipe(pipe_class_default);
7301 %}
7302 
7303 // Cmove using isel.
7304 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{
7305   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7306   predicate(VM_Version::has_isel());
7307   ins_cost(DEFAULT_COST);
7308 
7309   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7310   size(4);
7311   ins_encode %{
7312     // This is a Power7 instruction for which no machine description
7313     // exists. Anyways, the scheduler should be off on Power7.
7314     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7315     int cc        = $cmp$$cmpcode;
7316     __ isel($dst$$Register, $crx$$CondRegister,
7317             (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register);
7318   %}
7319   ins_pipe(pipe_class_default);
7320 %}
7321 
7322 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{
7323   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7324   predicate(!VM_Version::has_isel());
7325   ins_cost(DEFAULT_COST+BRANCH_COST);
7326 
7327   ins_variable_size_depending_on_alignment(true);
7328 
7329   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7330   // Worst case is branch + move + stop, no stop without scheduler.
7331   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7332   ins_encode( enc_cmove_reg(dst, crx, src, cmp) );
7333   ins_pipe(pipe_class_default);
7334 %}
7335 
7336 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{
7337   match(Set dst (CMoveP (Binary cmp crx) (Binary dst src)));
7338   ins_cost(DEFAULT_COST+BRANCH_COST);
7339 
7340   ins_variable_size_depending_on_alignment(true);
7341 
7342   format %{ "CMOVE   $cmp, $crx, $dst, $src\n\t" %}
7343   // Worst case is branch + move + stop, no stop without scheduler.
7344   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
7345   ins_encode( enc_cmove_imm(dst, crx, src, cmp) );
7346   ins_pipe(pipe_class_default);
7347 %}
7348 
7349 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{
7350   match(Set dst (CMoveF (Binary cmp crx) (Binary dst src)));
7351   ins_cost(DEFAULT_COST+BRANCH_COST);
7352 
7353   ins_variable_size_depending_on_alignment(true);
7354 
7355   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7356   // Worst case is branch + move + stop, no stop without scheduler.
7357   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7358   ins_encode %{
7359     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7360     Label done;
7361     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7362     // Branch if not (cmp crx).
7363     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7364     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7365     // TODO PPC port __ endgroup_if_needed(_size == 12);
7366     __ bind(done);
7367   %}
7368   ins_pipe(pipe_class_default);
7369 %}
7370 
7371 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{
7372   match(Set dst (CMoveD (Binary cmp crx) (Binary dst src)));
7373   ins_cost(DEFAULT_COST+BRANCH_COST);
7374 
7375   ins_variable_size_depending_on_alignment(true);
7376 
7377   format %{ "CMOVEF  $cmp, $crx, $dst, $src\n\t" %}
7378   // Worst case is branch + move + stop, no stop without scheduler.
7379   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
7380   ins_encode %{
7381     // TODO: PPC port $archOpcode(ppc64Opcode_cmovef);
7382     Label done;
7383     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
7384     // Branch if not (cmp crx).
7385     __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done);
7386     __ fmr($dst$$FloatRegister, $src$$FloatRegister);
7387     // TODO PPC port __ endgroup_if_needed(_size == 12);
7388     __ bind(done);
7389   %}
7390   ins_pipe(pipe_class_default);
7391 %}
7392 
7393 //----------Conditional_store--------------------------------------------------
7394 // Conditional-store of the updated heap-top.
7395 // Used during allocation of the shared heap.
7396 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7397 
7398 // As compareAndSwapL, but return flag register instead of boolean value in
7399 // int register.
7400 // Used by sun/misc/AtomicLongCSImpl.java.
7401 // Mem_ptr must be a memory operand, else this node does not get
7402 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7403 // can be rematerialized which leads to errors.
7404 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{
7405   match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal)));
7406   effect(TEMP cr0);
7407   format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7408   ins_encode %{
7409     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7410     __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register,
7411                 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(),
7412                 noreg, NULL, true);
7413   %}
7414   ins_pipe(pipe_class_default);
7415 %}
7416 
7417 // As compareAndSwapP, but return flag register instead of boolean value in
7418 // int register.
7419 // This instruction is matched if UseTLAB is off.
7420 // Mem_ptr must be a memory operand, else this node does not get
7421 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node
7422 // can be rematerialized which leads to errors.
7423 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{
7424   match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal)));
7425   ins_cost(2*MEMORY_REF_COST);
7426 
7427   format %{ "STDCX_  if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %}
7428   ins_encode %{
7429     // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_);
7430     __ stdcx_($newVal$$Register, $mem_ptr$$Register);
7431   %}
7432   ins_pipe(pipe_class_memory);
7433 %}
7434 
7435 // Implement LoadPLocked. Must be ordered against changes of the memory location
7436 // by storePConditional.
7437 // Don't know whether this is ever used.
7438 instruct loadPLocked(iRegPdst dst, memory mem) %{
7439   match(Set dst (LoadPLocked mem));
7440   ins_cost(2*MEMORY_REF_COST);
7441 
7442   format %{ "LDARX   $dst, $mem \t// loadPLocked\n\t" %}
7443   size(4);
7444   ins_encode %{
7445     // TODO: PPC port $archOpcode(ppc64Opcode_ldarx);
7446     __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
7447   %}
7448   ins_pipe(pipe_class_memory);
7449 %}
7450 
7451 //----------Compare-And-Swap---------------------------------------------------
7452 
7453 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI
7454 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))"  cannot be
7455 // matched.
7456 
7457 // Strong versions:
7458 
7459 instruct compareAndSwapB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7460   match(Set res (CompareAndSwapB mem_ptr (Binary src1 src2)));
7461   predicate(VM_Version::has_lqarx());
7462   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7463   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7464   ins_encode %{
7465     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7466     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7467     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7468                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7469                 $res$$Register, true);
7470     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7471       __ isync();
7472     } else {
7473       __ sync();
7474     }
7475   %}
7476   ins_pipe(pipe_class_default);
7477 %}
7478 
7479 instruct compareAndSwapB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7480   match(Set res (CompareAndSwapB mem_ptr (Binary src1 src2)));
7481   predicate(!VM_Version::has_lqarx());
7482   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7483   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7484   ins_encode %{
7485     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7486     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7487     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7488                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7489                 $res$$Register, true);
7490     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7491       __ isync();
7492     } else {
7493       __ sync();
7494     }
7495   %}
7496   ins_pipe(pipe_class_default);
7497 %}
7498 
7499 instruct compareAndSwapS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7500   match(Set res (CompareAndSwapS mem_ptr (Binary src1 src2)));
7501   predicate(VM_Version::has_lqarx());
7502   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7503   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7504   ins_encode %{
7505     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7506     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7507     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7508                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7509                 $res$$Register, true);
7510     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7511       __ isync();
7512     } else {
7513       __ sync();
7514     }
7515   %}
7516   ins_pipe(pipe_class_default);
7517 %}
7518 
7519 instruct compareAndSwapS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7520   match(Set res (CompareAndSwapS mem_ptr (Binary src1 src2)));
7521   predicate(!VM_Version::has_lqarx());
7522   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7523   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7524   ins_encode %{
7525     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7526     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7527     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7528                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7529                 $res$$Register, true);
7530     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7531       __ isync();
7532     } else {
7533       __ sync();
7534     }
7535   %}
7536   ins_pipe(pipe_class_default);
7537 %}
7538 
7539 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7540   match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2)));
7541   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7542   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7543   ins_encode %{
7544     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7545     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7546     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7547                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7548                 $res$$Register, true);
7549     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7550       __ isync();
7551     } else {
7552       __ sync();
7553     }
7554   %}
7555   ins_pipe(pipe_class_default);
7556 %}
7557 
7558 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7559   match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2)));
7560   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7561   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7562   ins_encode %{
7563     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7564     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7565     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7566                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7567                 $res$$Register, true);
7568     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7569       __ isync();
7570     } else {
7571       __ sync();
7572     }
7573   %}
7574   ins_pipe(pipe_class_default);
7575 %}
7576 
7577 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7578   match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2)));
7579   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7580   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7581   ins_encode %{
7582     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7583     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7584     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7585                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7586                 $res$$Register, NULL, true);
7587     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7588       __ isync();
7589     } else {
7590       __ sync();
7591     }
7592   %}
7593   ins_pipe(pipe_class_default);
7594 %}
7595 
7596 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7597   match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2)));
7598   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7599   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7600   ins_encode %{
7601     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7602     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7603     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7604                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7605                 $res$$Register, NULL, true);
7606     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7607       __ isync();
7608     } else {
7609       __ sync();
7610     }
7611   %}
7612   ins_pipe(pipe_class_default);
7613 %}
7614 
7615 // Weak versions:
7616 
7617 instruct weakCompareAndSwapB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7618   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7619   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
7620   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7621   format %{ "weak CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7622   ins_encode %{
7623     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7624     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7625     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7626                 MacroAssembler::MemBarNone,
7627                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7628   %}
7629   ins_pipe(pipe_class_default);
7630 %}
7631 
7632 instruct weakCompareAndSwapB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7633   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7634   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
7635   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7636   format %{ "weak CMPXCHGB $res, $mem_ptr, $src1, $src2; as bool" %}
7637   ins_encode %{
7638     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7639     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7640     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7641                 MacroAssembler::MemBarNone,
7642                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7643   %}
7644   ins_pipe(pipe_class_default);
7645 %}
7646 
7647 instruct weakCompareAndSwapB_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7648   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7649   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
7650   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7651   format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
7652   ins_encode %{
7653     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7654     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7655     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7656                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7657                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7658   %}
7659   ins_pipe(pipe_class_default);
7660 %}
7661 
7662 instruct weakCompareAndSwapB4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7663   match(Set res (WeakCompareAndSwapB mem_ptr (Binary src1 src2)));
7664   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
7665   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7666   format %{ "weak CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as bool" %}
7667   ins_encode %{
7668     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7669     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7670     __ cmpxchgb(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7671                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7672                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7673   %}
7674   ins_pipe(pipe_class_default);
7675 %}
7676 
7677 instruct weakCompareAndSwapS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7678   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7679   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
7680   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7681   format %{ "weak CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7682   ins_encode %{
7683     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7684     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7685     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7686                 MacroAssembler::MemBarNone,
7687                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7688   %}
7689   ins_pipe(pipe_class_default);
7690 %}
7691 
7692 instruct weakCompareAndSwapS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7693   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7694   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
7695   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7696   format %{ "weak CMPXCHGH $res, $mem_ptr, $src1, $src2; as bool" %}
7697   ins_encode %{
7698     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7699     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7700     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7701                 MacroAssembler::MemBarNone,
7702                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7703   %}
7704   ins_pipe(pipe_class_default);
7705 %}
7706 
7707 instruct weakCompareAndSwapS_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7708   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7709   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
7710   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7711   format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
7712   ins_encode %{
7713     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7714     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7715     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7716                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7717                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7718   %}
7719   ins_pipe(pipe_class_default);
7720 %}
7721 
7722 instruct weakCompareAndSwapS4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, iRegIdst tmp2, flagsRegCR0 cr0) %{
7723   match(Set res (WeakCompareAndSwapS mem_ptr (Binary src1 src2)));
7724   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
7725   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0); // TEMP_DEF to avoid jump
7726   format %{ "weak CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as bool" %}
7727   ins_encode %{
7728     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7729     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7730     __ cmpxchgh(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, $tmp2$$Register,
7731                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7732                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7733   %}
7734   ins_pipe(pipe_class_default);
7735 %}
7736 
7737 instruct weakCompareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7738   match(Set res (WeakCompareAndSwapI mem_ptr (Binary src1 src2)));
7739   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7740   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7741   format %{ "weak CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7742   ins_encode %{
7743     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7744     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7745     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7746                 MacroAssembler::MemBarNone,
7747                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7748   %}
7749   ins_pipe(pipe_class_default);
7750 %}
7751 
7752 instruct weakCompareAndSwapI_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7753   match(Set res (WeakCompareAndSwapI mem_ptr (Binary src1 src2)));
7754   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7755   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7756   format %{ "weak CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as bool" %}
7757   ins_encode %{
7758     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7759     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7760     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7761     // value is never passed to caller.
7762     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7763                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7764                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7765   %}
7766   ins_pipe(pipe_class_default);
7767 %}
7768 
7769 instruct weakCompareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7770   match(Set res (WeakCompareAndSwapN mem_ptr (Binary src1 src2)));
7771   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7772   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7773   format %{ "weak CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %}
7774   ins_encode %{
7775     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7776     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7777     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7778                 MacroAssembler::MemBarNone,
7779                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7780   %}
7781   ins_pipe(pipe_class_default);
7782 %}
7783 
7784 instruct weakCompareAndSwapN_acq_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
7785   match(Set res (WeakCompareAndSwapN mem_ptr (Binary src1 src2)));
7786   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7787   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7788   format %{ "weak CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as bool" %}
7789   ins_encode %{
7790     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7791     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7792     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7793     // value is never passed to caller.
7794     __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7795                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7796                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, true, /*weak*/ true);
7797   %}
7798   ins_pipe(pipe_class_default);
7799 %}
7800 
7801 instruct weakCompareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7802   match(Set res (WeakCompareAndSwapL mem_ptr (Binary src1 src2)));
7803   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7804   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7805   format %{ "weak CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %}
7806   ins_encode %{
7807     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7808     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7809     // value is never passed to caller.
7810     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7811                 MacroAssembler::MemBarNone,
7812                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
7813   %}
7814   ins_pipe(pipe_class_default);
7815 %}
7816 
7817 instruct weakCompareAndSwapL_acq_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
7818   match(Set res (WeakCompareAndSwapL mem_ptr (Binary src1 src2)));
7819   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7820   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7821   format %{ "weak CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as bool" %}
7822   ins_encode %{
7823     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7824     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7825     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7826     // value is never passed to caller.
7827     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7828                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7829                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
7830   %}
7831   ins_pipe(pipe_class_default);
7832 %}
7833 
7834 instruct weakCompareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7835   match(Set res (WeakCompareAndSwapP mem_ptr (Binary src1 src2)));
7836   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
7837   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7838   format %{ "weak CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7839   ins_encode %{
7840     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7841     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7842     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7843                 MacroAssembler::MemBarNone,
7844                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
7845   %}
7846   ins_pipe(pipe_class_default);
7847 %}
7848 
7849 instruct weakCompareAndSwapP_acq_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
7850   match(Set res (WeakCompareAndSwapP mem_ptr (Binary src1 src2)));
7851   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
7852   effect(TEMP_DEF res, TEMP cr0); // TEMP_DEF to avoid jump
7853   format %{ "weak CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as bool; ptr" %}
7854   ins_encode %{
7855     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7856     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7857     // Acquire only needed in successful case. Weak node is allowed to report unsuccessful in additional rare cases and
7858     // value is never passed to caller.
7859     __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
7860                 support_IRIW_for_not_multiple_copy_atomic_cpu ? MacroAssembler::MemBarAcq : MacroAssembler::MemBarFenceAfter,
7861                 MacroAssembler::cmpxchgx_hint_atomic_update(), $res$$Register, NULL, true, /*weak*/ true);
7862   %}
7863   ins_pipe(pipe_class_default);
7864 %}
7865 
7866 // CompareAndExchange
7867 
7868 instruct compareAndExchangeB_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7869   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7870   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
7871   effect(TEMP_DEF res, TEMP cr0);
7872   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as int" %}
7873   ins_encode %{
7874     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7875     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7876     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7877                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7878                 noreg, true);
7879   %}
7880   ins_pipe(pipe_class_default);
7881 %}
7882 
7883 instruct compareAndExchangeB4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
7884   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7885   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
7886   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
7887   format %{ "CMPXCHGB $res, $mem_ptr, $src1, $src2; as int" %}
7888   ins_encode %{
7889     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7890     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7891     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
7892                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7893                 noreg, true);
7894   %}
7895   ins_pipe(pipe_class_default);
7896 %}
7897 
7898 instruct compareAndExchangeB_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7899   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7900   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
7901   effect(TEMP_DEF res, TEMP cr0);
7902   format %{ "CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as int" %}
7903   ins_encode %{
7904     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7905     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7906     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7907                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7908                 noreg, true);
7909     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7910       __ isync();
7911     } else {
7912       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7913       __ sync();
7914     }
7915   %}
7916   ins_pipe(pipe_class_default);
7917 %}
7918 
7919 instruct compareAndExchangeB4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
7920   match(Set res (CompareAndExchangeB mem_ptr (Binary src1 src2)));
7921   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
7922   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
7923   format %{ "CMPXCHGB acq $res, $mem_ptr, $src1, $src2; as int" %}
7924   ins_encode %{
7925     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7926     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7927     __ cmpxchgb(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
7928                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7929                 noreg, true);
7930     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7931       __ isync();
7932     } else {
7933       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7934       __ sync();
7935     }
7936   %}
7937   ins_pipe(pipe_class_default);
7938 %}
7939 
7940 instruct compareAndExchangeS_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7941   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7942   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && VM_Version::has_lqarx());
7943   effect(TEMP_DEF res, TEMP cr0);
7944   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as int" %}
7945   ins_encode %{
7946     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7947     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7948     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7949                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7950                 noreg, true);
7951   %}
7952   ins_pipe(pipe_class_default);
7953 %}
7954 
7955 instruct compareAndExchangeS4_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
7956   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7957   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst && !VM_Version::has_lqarx());
7958   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
7959   format %{ "CMPXCHGH $res, $mem_ptr, $src1, $src2; as int" %}
7960   ins_encode %{
7961     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7962     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7963     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
7964                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7965                 noreg, true);
7966   %}
7967   ins_pipe(pipe_class_default);
7968 %}
7969 
7970 instruct compareAndExchangeS_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
7971   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7972   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && VM_Version::has_lqarx());
7973   effect(TEMP_DEF res, TEMP cr0);
7974   format %{ "CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as int" %}
7975   ins_encode %{
7976     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7977     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7978     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, noreg, noreg,
7979                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
7980                 noreg, true);
7981     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
7982       __ isync();
7983     } else {
7984       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
7985       __ sync();
7986     }
7987   %}
7988   ins_pipe(pipe_class_default);
7989 %}
7990 
7991 instruct compareAndExchangeS4_acq_regP_regI_regI(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src1, rarg4RegI src2, iRegIdst tmp1, flagsRegCR0 cr0) %{
7992   match(Set res (CompareAndExchangeS mem_ptr (Binary src1 src2)));
7993   predicate((((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst) && !VM_Version::has_lqarx());
7994   effect(TEMP_DEF res, USE_KILL src2, USE_KILL mem_ptr, TEMP tmp1, TEMP cr0);
7995   format %{ "CMPXCHGH acq $res, $mem_ptr, $src1, $src2; as int" %}
7996   ins_encode %{
7997     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
7998     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
7999     __ cmpxchgh(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register, $tmp1$$Register, R0,
8000                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8001                 noreg, true);
8002     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8003       __ isync();
8004     } else {
8005       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8006       __ sync();
8007     }
8008   %}
8009   ins_pipe(pipe_class_default);
8010 %}
8011 
8012 instruct compareAndExchangeI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8013   match(Set res (CompareAndExchangeI mem_ptr (Binary src1 src2)));
8014   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8015   effect(TEMP_DEF res, TEMP cr0);
8016   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as int" %}
8017   ins_encode %{
8018     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8019     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8020     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8021                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8022                 noreg, true);
8023   %}
8024   ins_pipe(pipe_class_default);
8025 %}
8026 
8027 instruct compareAndExchangeI_acq_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
8028   match(Set res (CompareAndExchangeI mem_ptr (Binary src1 src2)));
8029   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8030   effect(TEMP_DEF res, TEMP cr0);
8031   format %{ "CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as int" %}
8032   ins_encode %{
8033     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8034     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8035     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8036                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8037                 noreg, true);
8038     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8039       __ isync();
8040     } else {
8041       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8042       __ sync();
8043     }
8044   %}
8045   ins_pipe(pipe_class_default);
8046 %}
8047 
8048 instruct compareAndExchangeN_regP_regN_regN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8049   match(Set res (CompareAndExchangeN mem_ptr (Binary src1 src2)));
8050   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8051   effect(TEMP_DEF res, TEMP cr0);
8052   format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as narrow oop" %}
8053   ins_encode %{
8054     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8055     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8056     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8057                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8058                 noreg, true);
8059   %}
8060   ins_pipe(pipe_class_default);
8061 %}
8062 
8063 instruct compareAndExchangeN_acq_regP_regN_regN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{
8064   match(Set res (CompareAndExchangeN mem_ptr (Binary src1 src2)));
8065   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8066   effect(TEMP_DEF res, TEMP cr0);
8067   format %{ "CMPXCHGW acq $res, $mem_ptr, $src1, $src2; as narrow oop" %}
8068   ins_encode %{
8069     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8070     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8071     __ cmpxchgw(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8072                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8073                 noreg, true);
8074     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8075       __ isync();
8076     } else {
8077       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8078       __ sync();
8079     }
8080   %}
8081   ins_pipe(pipe_class_default);
8082 %}
8083 
8084 instruct compareAndExchangeL_regP_regL_regL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8085   match(Set res (CompareAndExchangeL mem_ptr (Binary src1 src2)));
8086   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8087   effect(TEMP_DEF res, TEMP cr0);
8088   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as long" %}
8089   ins_encode %{
8090     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8091     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8092     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8093                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8094                 noreg, NULL, true);
8095   %}
8096   ins_pipe(pipe_class_default);
8097 %}
8098 
8099 instruct compareAndExchangeL_acq_regP_regL_regL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{
8100   match(Set res (CompareAndExchangeL mem_ptr (Binary src1 src2)));
8101   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8102   effect(TEMP_DEF res, TEMP cr0);
8103   format %{ "CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as long" %}
8104   ins_encode %{
8105     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8106     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8107     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8108                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8109                 noreg, NULL, true);
8110     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8111       __ isync();
8112     } else {
8113       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8114       __ sync();
8115     }
8116   %}
8117   ins_pipe(pipe_class_default);
8118 %}
8119 
8120 instruct compareAndExchangeP_regP_regP_regP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8121   match(Set res (CompareAndExchangeP mem_ptr (Binary src1 src2)));
8122   predicate(((CompareAndSwapNode*)n)->order() != MemNode::acquire && ((CompareAndSwapNode*)n)->order() != MemNode::seqcst);
8123   effect(TEMP_DEF res, TEMP cr0);
8124   format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as ptr; ptr" %}
8125   ins_encode %{
8126     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8127     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8128     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8129                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8130                 noreg, NULL, true);
8131   %}
8132   ins_pipe(pipe_class_default);
8133 %}
8134 
8135 instruct compareAndExchangeP_acq_regP_regP_regP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{
8136   match(Set res (CompareAndExchangeP mem_ptr (Binary src1 src2)));
8137   predicate(((CompareAndSwapNode*)n)->order() == MemNode::acquire || ((CompareAndSwapNode*)n)->order() == MemNode::seqcst);
8138   effect(TEMP_DEF res, TEMP cr0);
8139   format %{ "CMPXCHGD acq $res, $mem_ptr, $src1, $src2; as ptr; ptr" %}
8140   ins_encode %{
8141     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
8142     // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'.
8143     __ cmpxchgd(CCR0, $res$$Register, $src1$$Register, $src2$$Register, $mem_ptr$$Register,
8144                 MacroAssembler::MemBarNone, MacroAssembler::cmpxchgx_hint_atomic_update(),
8145                 noreg, NULL, true);
8146     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8147       __ isync();
8148     } else {
8149       // isync would be sufficient in case of CompareAndExchangeAcquire, but we currently don't optimize for that.
8150       __ sync();
8151     }
8152   %}
8153   ins_pipe(pipe_class_default);
8154 %}
8155 
8156 // Special RMW
8157 
8158 instruct getAndAddB(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8159   match(Set res (GetAndAddB mem_ptr src));
8160   predicate(VM_Version::has_lqarx());
8161   effect(TEMP_DEF res, TEMP cr0);
8162   format %{ "GetAndAddB $res, $mem_ptr, $src" %}
8163   ins_encode %{
8164     __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
8165                   R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8166     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8167       __ isync();
8168     } else {
8169       __ sync();
8170     }
8171   %}
8172   ins_pipe(pipe_class_default);
8173 %}
8174 
8175 instruct getAndAddB4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8176   match(Set res (GetAndAddB mem_ptr src));
8177   predicate(!VM_Version::has_lqarx());
8178   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8179   format %{ "GetAndAddB $res, $mem_ptr, $src" %}
8180   ins_encode %{
8181     __ getandaddb($res$$Register, $src$$Register, $mem_ptr$$Register,
8182                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8183     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8184       __ isync();
8185     } else {
8186       __ sync();
8187     }
8188   %}
8189   ins_pipe(pipe_class_default);
8190 %}
8191 
8192 instruct getAndAddS(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8193   match(Set res (GetAndAddS mem_ptr src));
8194   predicate(VM_Version::has_lqarx());
8195   effect(TEMP_DEF res, TEMP cr0);
8196   format %{ "GetAndAddS $res, $mem_ptr, $src" %}
8197   ins_encode %{
8198     __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
8199                   R0, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8200     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8201       __ isync();
8202     } else {
8203       __ sync();
8204     }
8205   %}
8206   ins_pipe(pipe_class_default);
8207 %}
8208 
8209 instruct getAndAddS4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8210   match(Set res (GetAndAddS mem_ptr src));
8211   predicate(!VM_Version::has_lqarx());
8212   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8213   format %{ "GetAndAddS $res, $mem_ptr, $src" %}
8214   ins_encode %{
8215     __ getandaddh($res$$Register, $src$$Register, $mem_ptr$$Register,
8216                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8217     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8218       __ isync();
8219     } else {
8220       __ sync();
8221     }
8222   %}
8223   ins_pipe(pipe_class_default);
8224 %}
8225 
8226 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8227   match(Set res (GetAndAddI mem_ptr src));
8228   effect(TEMP_DEF res, TEMP cr0);
8229   format %{ "GetAndAddI $res, $mem_ptr, $src" %}
8230   ins_encode %{
8231     __ getandaddw($res$$Register, $src$$Register, $mem_ptr$$Register,
8232                   R0, MacroAssembler::cmpxchgx_hint_atomic_update());
8233     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8234       __ isync();
8235     } else {
8236       __ sync();
8237     }
8238   %}
8239   ins_pipe(pipe_class_default);
8240 %}
8241 
8242 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
8243   match(Set res (GetAndAddL mem_ptr src));
8244   effect(TEMP_DEF res, TEMP cr0);
8245   format %{ "GetAndAddL $res, $mem_ptr, $src" %}
8246   ins_encode %{
8247     __ getandaddd($res$$Register, $src$$Register, $mem_ptr$$Register,
8248                   R0, MacroAssembler::cmpxchgx_hint_atomic_update());
8249     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8250       __ isync();
8251     } else {
8252       __ sync();
8253     }
8254   %}
8255   ins_pipe(pipe_class_default);
8256 %}
8257 
8258 instruct getAndSetB(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8259   match(Set res (GetAndSetB mem_ptr src));
8260   predicate(VM_Version::has_lqarx());
8261   effect(TEMP_DEF res, TEMP cr0);
8262   format %{ "GetAndSetB $res, $mem_ptr, $src" %}
8263   ins_encode %{
8264     __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
8265                   noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8266     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8267       __ isync();
8268     } else {
8269       __ sync();
8270     }
8271   %}
8272   ins_pipe(pipe_class_default);
8273 %}
8274 
8275 instruct getAndSetB4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8276   match(Set res (GetAndSetB mem_ptr src));
8277   predicate(!VM_Version::has_lqarx());
8278   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8279   format %{ "GetAndSetB $res, $mem_ptr, $src" %}
8280   ins_encode %{
8281     __ getandsetb($res$$Register, $src$$Register, $mem_ptr$$Register,
8282                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8283     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8284       __ isync();
8285     } else {
8286       __ sync();
8287     }
8288   %}
8289   ins_pipe(pipe_class_default);
8290 %}
8291 
8292 instruct getAndSetS(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8293   match(Set res (GetAndSetS mem_ptr src));
8294   predicate(VM_Version::has_lqarx());
8295   effect(TEMP_DEF res, TEMP cr0);
8296   format %{ "GetAndSetS $res, $mem_ptr, $src" %}
8297   ins_encode %{
8298     __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
8299                   noreg, noreg, noreg, MacroAssembler::cmpxchgx_hint_atomic_update());
8300     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8301       __ isync();
8302     } else {
8303       __ sync();
8304     }
8305   %}
8306   ins_pipe(pipe_class_default);
8307 %}
8308 
8309 instruct getAndSetS4(iRegIdst res, rarg3RegP mem_ptr, iRegIsrc src, iRegIsrc tmp1, iRegIsrc tmp2, flagsRegCR0 cr0) %{
8310   match(Set res (GetAndSetS mem_ptr src));
8311   predicate(!VM_Version::has_lqarx());
8312   effect(TEMP_DEF res, USE_KILL mem_ptr, TEMP tmp1, TEMP tmp2, TEMP cr0);
8313   format %{ "GetAndSetS $res, $mem_ptr, $src" %}
8314   ins_encode %{
8315     __ getandseth($res$$Register, $src$$Register, $mem_ptr$$Register,
8316                   R0, $tmp1$$Register, $tmp2$$Register, MacroAssembler::cmpxchgx_hint_atomic_update());
8317     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8318       __ isync();
8319     } else {
8320       __ sync();
8321     }
8322   %}
8323   ins_pipe(pipe_class_default);
8324 %}
8325 
8326 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{
8327   match(Set res (GetAndSetI mem_ptr src));
8328   effect(TEMP_DEF res, TEMP cr0);
8329   format %{ "GetAndSetI $res, $mem_ptr, $src" %}
8330   ins_encode %{
8331     __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
8332                   MacroAssembler::cmpxchgx_hint_atomic_update());
8333     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8334       __ isync();
8335     } else {
8336       __ sync();
8337     }
8338   %}
8339   ins_pipe(pipe_class_default);
8340 %}
8341 
8342 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{
8343   match(Set res (GetAndSetL mem_ptr src));
8344   effect(TEMP_DEF res, TEMP cr0);
8345   format %{ "GetAndSetL $res, $mem_ptr, $src" %}
8346   ins_encode %{
8347     __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
8348                   MacroAssembler::cmpxchgx_hint_atomic_update());
8349     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8350       __ isync();
8351     } else {
8352       __ sync();
8353     }
8354   %}
8355   ins_pipe(pipe_class_default);
8356 %}
8357 
8358 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{
8359   match(Set res (GetAndSetP mem_ptr src));
8360   effect(TEMP_DEF res, TEMP cr0);
8361   format %{ "GetAndSetP $res, $mem_ptr, $src" %}
8362   ins_encode %{
8363     __ getandsetd($res$$Register, $src$$Register, $mem_ptr$$Register,
8364                   MacroAssembler::cmpxchgx_hint_atomic_update());
8365     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8366       __ isync();
8367     } else {
8368       __ sync();
8369     }
8370   %}
8371   ins_pipe(pipe_class_default);
8372 %}
8373 
8374 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{
8375   match(Set res (GetAndSetN mem_ptr src));
8376   effect(TEMP_DEF res, TEMP cr0);
8377   format %{ "GetAndSetN $res, $mem_ptr, $src" %}
8378   ins_encode %{
8379     __ getandsetw($res$$Register, $src$$Register, $mem_ptr$$Register,
8380                   MacroAssembler::cmpxchgx_hint_atomic_update());
8381     if (support_IRIW_for_not_multiple_copy_atomic_cpu) {
8382       __ isync();
8383     } else {
8384       __ sync();
8385     }
8386   %}
8387   ins_pipe(pipe_class_default);
8388 %}
8389 
8390 //----------Arithmetic Instructions--------------------------------------------
8391 // Addition Instructions
8392 
8393 // Register Addition
8394 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{
8395   match(Set dst (AddI src1 src2));
8396   format %{ "ADD     $dst, $src1, $src2" %}
8397   size(4);
8398   ins_encode %{
8399     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8400     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8401   %}
8402   ins_pipe(pipe_class_default);
8403 %}
8404 
8405 // Expand does not work with above instruct. (??)
8406 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8407   // no match-rule
8408   effect(DEF dst, USE src1, USE src2);
8409   format %{ "ADD     $dst, $src1, $src2" %}
8410   size(4);
8411   ins_encode %{
8412     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8413     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8414   %}
8415   ins_pipe(pipe_class_default);
8416 %}
8417 
8418 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
8419   match(Set dst (AddI (AddI (AddI src1 src2) src3) src4));
8420   ins_cost(DEFAULT_COST*3);
8421 
8422   expand %{
8423     // FIXME: we should do this in the ideal world.
8424     iRegIdst tmp1;
8425     iRegIdst tmp2;
8426     addI_reg_reg(tmp1, src1, src2);
8427     addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg.
8428     addI_reg_reg(dst, tmp1, tmp2);
8429   %}
8430 %}
8431 
8432 // Immediate Addition
8433 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8434   match(Set dst (AddI src1 src2));
8435   format %{ "ADDI    $dst, $src1, $src2" %}
8436   size(4);
8437   ins_encode %{
8438     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8439     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
8440   %}
8441   ins_pipe(pipe_class_default);
8442 %}
8443 
8444 // Immediate Addition with 16-bit shifted operand
8445 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{
8446   match(Set dst (AddI src1 src2));
8447   format %{ "ADDIS   $dst, $src1, $src2" %}
8448   size(4);
8449   ins_encode %{
8450     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
8451     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
8452   %}
8453   ins_pipe(pipe_class_default);
8454 %}
8455 
8456 // Long Addition
8457 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8458   match(Set dst (AddL src1 src2));
8459   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
8460   size(4);
8461   ins_encode %{
8462     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8463     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8464   %}
8465   ins_pipe(pipe_class_default);
8466 %}
8467 
8468 // Expand does not work with above instruct. (??)
8469 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8470   // no match-rule
8471   effect(DEF dst, USE src1, USE src2);
8472   format %{ "ADD     $dst, $src1, $src2 \t// long" %}
8473   size(4);
8474   ins_encode %{
8475     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8476     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8477   %}
8478   ins_pipe(pipe_class_default);
8479 %}
8480 
8481 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{
8482   match(Set dst (AddL (AddL (AddL src1 src2) src3) src4));
8483   ins_cost(DEFAULT_COST*3);
8484 
8485   expand %{
8486     // FIXME: we should do this in the ideal world.
8487     iRegLdst tmp1;
8488     iRegLdst tmp2;
8489     addL_reg_reg(tmp1, src1, src2);
8490     addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
8491     addL_reg_reg(dst, tmp1, tmp2);
8492   %}
8493 %}
8494 
8495 // AddL + ConvL2I.
8496 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8497   match(Set dst (ConvL2I (AddL src1 src2)));
8498 
8499   format %{ "ADD     $dst, $src1, $src2 \t// long + l2i" %}
8500   size(4);
8501   ins_encode %{
8502     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8503     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8504   %}
8505   ins_pipe(pipe_class_default);
8506 %}
8507 
8508 // No constant pool entries required.
8509 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8510   match(Set dst (AddL src1 src2));
8511 
8512   format %{ "ADDI    $dst, $src1, $src2" %}
8513   size(4);
8514   ins_encode %{
8515     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8516     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
8517   %}
8518   ins_pipe(pipe_class_default);
8519 %}
8520 
8521 // Long Immediate Addition with 16-bit shifted operand.
8522 // No constant pool entries required.
8523 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{
8524   match(Set dst (AddL src1 src2));
8525 
8526   format %{ "ADDIS   $dst, $src1, $src2" %}
8527   size(4);
8528   ins_encode %{
8529     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
8530     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
8531   %}
8532   ins_pipe(pipe_class_default);
8533 %}
8534 
8535 // Pointer Register Addition
8536 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{
8537   match(Set dst (AddP src1 src2));
8538   format %{ "ADD     $dst, $src1, $src2" %}
8539   size(4);
8540   ins_encode %{
8541     // TODO: PPC port $archOpcode(ppc64Opcode_add);
8542     __ add($dst$$Register, $src1$$Register, $src2$$Register);
8543   %}
8544   ins_pipe(pipe_class_default);
8545 %}
8546 
8547 // Pointer Immediate Addition
8548 // No constant pool entries required.
8549 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{
8550   match(Set dst (AddP src1 src2));
8551 
8552   format %{ "ADDI    $dst, $src1, $src2" %}
8553   size(4);
8554   ins_encode %{
8555     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
8556     __ addi($dst$$Register, $src1$$Register, $src2$$constant);
8557   %}
8558   ins_pipe(pipe_class_default);
8559 %}
8560 
8561 // Pointer Immediate Addition with 16-bit shifted operand.
8562 // No constant pool entries required.
8563 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{
8564   match(Set dst (AddP src1 src2));
8565 
8566   format %{ "ADDIS   $dst, $src1, $src2" %}
8567   size(4);
8568   ins_encode %{
8569     // TODO: PPC port $archOpcode(ppc64Opcode_addis);
8570     __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16);
8571   %}
8572   ins_pipe(pipe_class_default);
8573 %}
8574 
8575 //---------------------
8576 // Subtraction Instructions
8577 
8578 // Register Subtraction
8579 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8580   match(Set dst (SubI src1 src2));
8581   format %{ "SUBF    $dst, $src2, $src1" %}
8582   size(4);
8583   ins_encode %{
8584     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
8585     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
8586   %}
8587   ins_pipe(pipe_class_default);
8588 %}
8589 
8590 // Immediate Subtraction
8591 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal),
8592 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16.
8593 
8594 // SubI from constant (using subfic).
8595 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{
8596   match(Set dst (SubI src1 src2));
8597   format %{ "SUBI    $dst, $src1, $src2" %}
8598 
8599   size(4);
8600   ins_encode %{
8601     // TODO: PPC port $archOpcode(ppc64Opcode_subfic);
8602     __ subfic($dst$$Register, $src2$$Register, $src1$$constant);
8603   %}
8604   ins_pipe(pipe_class_default);
8605 %}
8606 
8607 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for
8608 // positive integers and 0xF...F for negative ones.
8609 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{
8610   // no match-rule, false predicate
8611   effect(DEF dst, USE src);
8612   predicate(false);
8613 
8614   format %{ "SRAWI   $dst, $src, #31" %}
8615   size(4);
8616   ins_encode %{
8617     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
8618     __ srawi($dst$$Register, $src$$Register, 0x1f);
8619   %}
8620   ins_pipe(pipe_class_default);
8621 %}
8622 
8623 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{
8624   match(Set dst (AbsI src));
8625   ins_cost(DEFAULT_COST*3);
8626 
8627   expand %{
8628     iRegIdst tmp1;
8629     iRegIdst tmp2;
8630     signmask32I_regI(tmp1, src);
8631     xorI_reg_reg(tmp2, tmp1, src);
8632     subI_reg_reg(dst, tmp2, tmp1);
8633   %}
8634 %}
8635 
8636 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{
8637   match(Set dst (SubI zero src2));
8638   format %{ "NEG     $dst, $src2" %}
8639   size(4);
8640   ins_encode %{
8641     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8642     __ neg($dst$$Register, $src2$$Register);
8643   %}
8644   ins_pipe(pipe_class_default);
8645 %}
8646 
8647 // Long subtraction
8648 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8649   match(Set dst (SubL src1 src2));
8650   format %{ "SUBF    $dst, $src2, $src1 \t// long" %}
8651   size(4);
8652   ins_encode %{
8653     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
8654     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
8655   %}
8656   ins_pipe(pipe_class_default);
8657 %}
8658 
8659 // SubL + convL2I.
8660 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
8661   match(Set dst (ConvL2I (SubL src1 src2)));
8662 
8663   format %{ "SUBF    $dst, $src2, $src1 \t// long + l2i" %}
8664   size(4);
8665   ins_encode %{
8666     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
8667     __ subf($dst$$Register, $src2$$Register, $src1$$Register);
8668   %}
8669   ins_pipe(pipe_class_default);
8670 %}
8671 
8672 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8673 // positive longs and 0xF...F for negative ones.
8674 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{
8675   // no match-rule, false predicate
8676   effect(DEF dst, USE src);
8677   predicate(false);
8678 
8679   format %{ "SRADI   $dst, $src, #63" %}
8680   size(4);
8681   ins_encode %{
8682     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8683     __ sradi($dst$$Register, $src$$Register, 0x3f);
8684   %}
8685   ins_pipe(pipe_class_default);
8686 %}
8687 
8688 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for
8689 // positive longs and 0xF...F for negative ones.
8690 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{
8691   // no match-rule, false predicate
8692   effect(DEF dst, USE src);
8693   predicate(false);
8694 
8695   format %{ "SRADI   $dst, $src, #63" %}
8696   size(4);
8697   ins_encode %{
8698     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
8699     __ sradi($dst$$Register, $src$$Register, 0x3f);
8700   %}
8701   ins_pipe(pipe_class_default);
8702 %}
8703 
8704 // Long negation
8705 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{
8706   match(Set dst (SubL zero src2));
8707   format %{ "NEG     $dst, $src2 \t// long" %}
8708   size(4);
8709   ins_encode %{
8710     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8711     __ neg($dst$$Register, $src2$$Register);
8712   %}
8713   ins_pipe(pipe_class_default);
8714 %}
8715 
8716 // NegL + ConvL2I.
8717 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{
8718   match(Set dst (ConvL2I (SubL zero src2)));
8719 
8720   format %{ "NEG     $dst, $src2 \t// long + l2i" %}
8721   size(4);
8722   ins_encode %{
8723     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8724     __ neg($dst$$Register, $src2$$Register);
8725   %}
8726   ins_pipe(pipe_class_default);
8727 %}
8728 
8729 // Multiplication Instructions
8730 // Integer Multiplication
8731 
8732 // Register Multiplication
8733 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8734   match(Set dst (MulI src1 src2));
8735   ins_cost(DEFAULT_COST);
8736 
8737   format %{ "MULLW   $dst, $src1, $src2" %}
8738   size(4);
8739   ins_encode %{
8740     // TODO: PPC port $archOpcode(ppc64Opcode_mullw);
8741     __ mullw($dst$$Register, $src1$$Register, $src2$$Register);
8742   %}
8743   ins_pipe(pipe_class_default);
8744 %}
8745 
8746 // Immediate Multiplication
8747 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{
8748   match(Set dst (MulI src1 src2));
8749   ins_cost(DEFAULT_COST);
8750 
8751   format %{ "MULLI   $dst, $src1, $src2" %}
8752   size(4);
8753   ins_encode %{
8754     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8755     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8756   %}
8757   ins_pipe(pipe_class_default);
8758 %}
8759 
8760 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8761   match(Set dst (MulL src1 src2));
8762   ins_cost(DEFAULT_COST);
8763 
8764   format %{ "MULLD   $dst $src1, $src2 \t// long" %}
8765   size(4);
8766   ins_encode %{
8767     // TODO: PPC port $archOpcode(ppc64Opcode_mulld);
8768     __ mulld($dst$$Register, $src1$$Register, $src2$$Register);
8769   %}
8770   ins_pipe(pipe_class_default);
8771 %}
8772 
8773 // Multiply high for optimized long division by constant.
8774 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8775   match(Set dst (MulHiL src1 src2));
8776   ins_cost(DEFAULT_COST);
8777 
8778   format %{ "MULHD   $dst $src1, $src2 \t// long" %}
8779   size(4);
8780   ins_encode %{
8781     // TODO: PPC port $archOpcode(ppc64Opcode_mulhd);
8782     __ mulhd($dst$$Register, $src1$$Register, $src2$$Register);
8783   %}
8784   ins_pipe(pipe_class_default);
8785 %}
8786 
8787 // Immediate Multiplication
8788 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{
8789   match(Set dst (MulL src1 src2));
8790   ins_cost(DEFAULT_COST);
8791 
8792   format %{ "MULLI   $dst, $src1, $src2" %}
8793   size(4);
8794   ins_encode %{
8795     // TODO: PPC port $archOpcode(ppc64Opcode_mulli);
8796     __ mulli($dst$$Register, $src1$$Register, $src2$$constant);
8797   %}
8798   ins_pipe(pipe_class_default);
8799 %}
8800 
8801 // Integer Division with Immediate -1: Negate.
8802 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
8803   match(Set dst (DivI src1 src2));
8804   ins_cost(DEFAULT_COST);
8805 
8806   format %{ "NEG     $dst, $src1 \t// /-1" %}
8807   size(4);
8808   ins_encode %{
8809     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8810     __ neg($dst$$Register, $src1$$Register);
8811   %}
8812   ins_pipe(pipe_class_default);
8813 %}
8814 
8815 // Integer Division with constant, but not -1.
8816 // We should be able to improve this by checking the type of src2.
8817 // It might well be that src2 is known to be positive.
8818 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8819   match(Set dst (DivI src1 src2));
8820   predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1
8821   ins_cost(2*DEFAULT_COST);
8822 
8823   format %{ "DIVW    $dst, $src1, $src2 \t// /not-1" %}
8824   size(4);
8825   ins_encode %{
8826     // TODO: PPC port $archOpcode(ppc64Opcode_divw);
8827     __ divw($dst$$Register, $src1$$Register, $src2$$Register);
8828   %}
8829   ins_pipe(pipe_class_default);
8830 %}
8831 
8832 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{
8833   effect(USE_DEF dst, USE src1, USE crx);
8834   predicate(false);
8835 
8836   ins_variable_size_depending_on_alignment(true);
8837 
8838   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8839   // Worst case is branch + move + stop, no stop without scheduler.
8840   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8841   ins_encode %{
8842     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8843     Label done;
8844     __ bne($crx$$CondRegister, done);
8845     __ neg($dst$$Register, $src1$$Register);
8846     // TODO PPC port __ endgroup_if_needed(_size == 12);
8847     __ bind(done);
8848   %}
8849   ins_pipe(pipe_class_default);
8850 %}
8851 
8852 // Integer Division with Registers not containing constants.
8853 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8854   match(Set dst (DivI src1 src2));
8855   ins_cost(10*DEFAULT_COST);
8856 
8857   expand %{
8858     immI16 imm %{ (int)-1 %}
8859     flagsReg tmp1;
8860     cmpI_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8861     divI_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8862     cmovI_bne_negI_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8863   %}
8864 %}
8865 
8866 // Long Division with Immediate -1: Negate.
8867 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
8868   match(Set dst (DivL src1 src2));
8869   ins_cost(DEFAULT_COST);
8870 
8871   format %{ "NEG     $dst, $src1 \t// /-1, long" %}
8872   size(4);
8873   ins_encode %{
8874     // TODO: PPC port $archOpcode(ppc64Opcode_neg);
8875     __ neg($dst$$Register, $src1$$Register);
8876   %}
8877   ins_pipe(pipe_class_default);
8878 %}
8879 
8880 // Long Division with constant, but not -1.
8881 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8882   match(Set dst (DivL src1 src2));
8883   predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1.
8884   ins_cost(2*DEFAULT_COST);
8885 
8886   format %{ "DIVD    $dst, $src1, $src2 \t// /not-1, long" %}
8887   size(4);
8888   ins_encode %{
8889     // TODO: PPC port $archOpcode(ppc64Opcode_divd);
8890     __ divd($dst$$Register, $src1$$Register, $src2$$Register);
8891   %}
8892   ins_pipe(pipe_class_default);
8893 %}
8894 
8895 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{
8896   effect(USE_DEF dst, USE src1, USE crx);
8897   predicate(false);
8898 
8899   ins_variable_size_depending_on_alignment(true);
8900 
8901   format %{ "CMOVE   $dst, neg($src1), $crx" %}
8902   // Worst case is branch + move + stop, no stop without scheduler.
8903   size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
8904   ins_encode %{
8905     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
8906     Label done;
8907     __ bne($crx$$CondRegister, done);
8908     __ neg($dst$$Register, $src1$$Register);
8909     // TODO PPC port __ endgroup_if_needed(_size == 12);
8910     __ bind(done);
8911   %}
8912   ins_pipe(pipe_class_default);
8913 %}
8914 
8915 // Long Division with Registers not containing constants.
8916 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8917   match(Set dst (DivL src1 src2));
8918   ins_cost(10*DEFAULT_COST);
8919 
8920   expand %{
8921     immL16 imm %{ (int)-1 %}
8922     flagsReg tmp1;
8923     cmpL_reg_imm16(tmp1, src2, imm);          // check src2 == -1
8924     divL_reg_regnotMinus1(dst, src1, src2);   // dst = src1 / src2
8925     cmovL_bne_negL_reg(dst, tmp1, src1);      // cmove dst = neg(src1) if src2 == -1
8926   %}
8927 %}
8928 
8929 // Integer Remainder with registers.
8930 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8931   match(Set dst (ModI src1 src2));
8932   ins_cost(10*DEFAULT_COST);
8933 
8934   expand %{
8935     immI16 imm %{ (int)-1 %}
8936     flagsReg tmp1;
8937     iRegIdst tmp2;
8938     iRegIdst tmp3;
8939     cmpI_reg_imm16(tmp1, src2, imm);           // check src2 == -1
8940     divI_reg_regnotMinus1(tmp2, src1, src2);   // tmp2 = src1 / src2
8941     cmovI_bne_negI_reg(tmp2, tmp1, src1);      // cmove tmp2 = neg(src1) if src2 == -1
8942     mulI_reg_reg(tmp3, src2, tmp2);            // tmp3 = src2 * tmp2
8943     subI_reg_reg(dst, src1, tmp3);             // dst = src1 - tmp3
8944   %}
8945 %}
8946 
8947 // Long Remainder with registers
8948 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
8949   match(Set dst (ModL src1 src2));
8950   ins_cost(10*DEFAULT_COST);
8951 
8952   expand %{
8953     immL16 imm %{ (int)-1 %}
8954     flagsReg tmp1;
8955     iRegLdst tmp2;
8956     iRegLdst tmp3;
8957     cmpL_reg_imm16(tmp1, src2, imm);             // check src2 == -1
8958     divL_reg_regnotMinus1(tmp2, src1, src2);     // tmp2 = src1 / src2
8959     cmovL_bne_negL_reg(tmp2, tmp1, src1);        // cmove tmp2 = neg(src1) if src2 == -1
8960     mulL_reg_reg(tmp3, src2, tmp2);              // tmp3 = src2 * tmp2
8961     subL_reg_reg(dst, src1, tmp3);               // dst = src1 - tmp3
8962   %}
8963 %}
8964 
8965 // Integer Shift Instructions
8966 
8967 // Register Shift Left
8968 
8969 // Clear all but the lowest #mask bits.
8970 // Used to normalize shift amounts in registers.
8971 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{
8972   // no match-rule, false predicate
8973   effect(DEF dst, USE src, USE mask);
8974   predicate(false);
8975 
8976   format %{ "MASK    $dst, $src, $mask \t// clear $mask upper bits" %}
8977   size(4);
8978   ins_encode %{
8979     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
8980     __ clrldi($dst$$Register, $src$$Register, $mask$$constant);
8981   %}
8982   ins_pipe(pipe_class_default);
8983 %}
8984 
8985 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
8986   // no match-rule, false predicate
8987   effect(DEF dst, USE src1, USE src2);
8988   predicate(false);
8989 
8990   format %{ "SLW     $dst, $src1, $src2" %}
8991   size(4);
8992   ins_encode %{
8993     // TODO: PPC port $archOpcode(ppc64Opcode_slw);
8994     __ slw($dst$$Register, $src1$$Register, $src2$$Register);
8995   %}
8996   ins_pipe(pipe_class_default);
8997 %}
8998 
8999 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9000   match(Set dst (LShiftI src1 src2));
9001   ins_cost(DEFAULT_COST*2);
9002   expand %{
9003     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
9004     iRegIdst tmpI;
9005     maskI_reg_imm(tmpI, src2, mask);
9006     lShiftI_reg_reg(dst, src1, tmpI);
9007   %}
9008 %}
9009 
9010 // Register Shift Left Immediate
9011 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9012   match(Set dst (LShiftI src1 src2));
9013 
9014   format %{ "SLWI    $dst, $src1, ($src2 & 0x1f)" %}
9015   size(4);
9016   ins_encode %{
9017     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9018     __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9019   %}
9020   ins_pipe(pipe_class_default);
9021 %}
9022 
9023 // AndI with negpow2-constant + LShiftI
9024 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
9025   match(Set dst (LShiftI (AndI src1 src2) src3));
9026   predicate(UseRotateAndMaskInstructionsPPC64);
9027 
9028   format %{ "RLWINM  $dst, lShiftI(AndI($src1, $src2), $src3)" %}
9029   size(4);
9030   ins_encode %{
9031     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
9032     long src2      = $src2$$constant;
9033     long src3      = $src3$$constant;
9034     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
9035     if (maskbits >= 32) {
9036       __ li($dst$$Register, 0); // addi
9037     } else {
9038       __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f);
9039     }
9040   %}
9041   ins_pipe(pipe_class_default);
9042 %}
9043 
9044 // RShiftI + AndI with negpow2-constant + LShiftI
9045 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{
9046   match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3));
9047   predicate(UseRotateAndMaskInstructionsPPC64);
9048 
9049   format %{ "RLWINM  $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %}
9050   size(4);
9051   ins_encode %{
9052     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi
9053     long src2      = $src2$$constant;
9054     long src3      = $src3$$constant;
9055     long maskbits  = src3 + log2_long((jlong) (julong) (juint) -src2);
9056     if (maskbits >= 32) {
9057       __ li($dst$$Register, 0); // addi
9058     } else {
9059       __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f);
9060     }
9061   %}
9062   ins_pipe(pipe_class_default);
9063 %}
9064 
9065 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9066   // no match-rule, false predicate
9067   effect(DEF dst, USE src1, USE src2);
9068   predicate(false);
9069 
9070   format %{ "SLD     $dst, $src1, $src2" %}
9071   size(4);
9072   ins_encode %{
9073     // TODO: PPC port $archOpcode(ppc64Opcode_sld);
9074     __ sld($dst$$Register, $src1$$Register, $src2$$Register);
9075   %}
9076   ins_pipe(pipe_class_default);
9077 %}
9078 
9079 // Register Shift Left
9080 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9081   match(Set dst (LShiftL src1 src2));
9082   ins_cost(DEFAULT_COST*2);
9083   expand %{
9084     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9085     iRegIdst tmpI;
9086     maskI_reg_imm(tmpI, src2, mask);
9087     lShiftL_regL_regI(dst, src1, tmpI);
9088   %}
9089 %}
9090 
9091 // Register Shift Left Immediate
9092 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9093   match(Set dst (LShiftL src1 src2));
9094   format %{ "SLDI    $dst, $src1, ($src2 & 0x3f)" %}
9095   size(4);
9096   ins_encode %{
9097     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9098     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9099   %}
9100   ins_pipe(pipe_class_default);
9101 %}
9102 
9103 // If we shift more than 32 bits, we need not convert I2L.
9104 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{
9105   match(Set dst (LShiftL (ConvI2L src1) src2));
9106   ins_cost(DEFAULT_COST);
9107 
9108   size(4);
9109   format %{ "SLDI    $dst, i2l($src1), $src2" %}
9110   ins_encode %{
9111     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9112     __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9113   %}
9114   ins_pipe(pipe_class_default);
9115 %}
9116 
9117 // Shift a postivie int to the left.
9118 // Clrlsldi clears the upper 32 bits and shifts.
9119 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{
9120   match(Set dst (LShiftL (ConvI2L src1) src2));
9121   predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int());
9122 
9123   format %{ "SLDI    $dst, i2l(positive_int($src1)), $src2" %}
9124   size(4);
9125   ins_encode %{
9126     // TODO: PPC port $archOpcode(ppc64Opcode_rldic);
9127     __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant);
9128   %}
9129   ins_pipe(pipe_class_default);
9130 %}
9131 
9132 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9133   // no match-rule, false predicate
9134   effect(DEF dst, USE src1, USE src2);
9135   predicate(false);
9136 
9137   format %{ "SRAW    $dst, $src1, $src2" %}
9138   size(4);
9139   ins_encode %{
9140     // TODO: PPC port $archOpcode(ppc64Opcode_sraw);
9141     __ sraw($dst$$Register, $src1$$Register, $src2$$Register);
9142   %}
9143   ins_pipe(pipe_class_default);
9144 %}
9145 
9146 // Register Arithmetic Shift Right
9147 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9148   match(Set dst (RShiftI src1 src2));
9149   ins_cost(DEFAULT_COST*2);
9150   expand %{
9151     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
9152     iRegIdst tmpI;
9153     maskI_reg_imm(tmpI, src2, mask);
9154     arShiftI_reg_reg(dst, src1, tmpI);
9155   %}
9156 %}
9157 
9158 // Register Arithmetic Shift Right Immediate
9159 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9160   match(Set dst (RShiftI src1 src2));
9161 
9162   format %{ "SRAWI   $dst, $src1, ($src2 & 0x1f)" %}
9163   size(4);
9164   ins_encode %{
9165     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
9166     __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9167   %}
9168   ins_pipe(pipe_class_default);
9169 %}
9170 
9171 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9172   // no match-rule, false predicate
9173   effect(DEF dst, USE src1, USE src2);
9174   predicate(false);
9175 
9176   format %{ "SRAD    $dst, $src1, $src2" %}
9177   size(4);
9178   ins_encode %{
9179     // TODO: PPC port $archOpcode(ppc64Opcode_srad);
9180     __ srad($dst$$Register, $src1$$Register, $src2$$Register);
9181   %}
9182   ins_pipe(pipe_class_default);
9183 %}
9184 
9185 // Register Shift Right Arithmetic Long
9186 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9187   match(Set dst (RShiftL src1 src2));
9188   ins_cost(DEFAULT_COST*2);
9189 
9190   expand %{
9191     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9192     iRegIdst tmpI;
9193     maskI_reg_imm(tmpI, src2, mask);
9194     arShiftL_regL_regI(dst, src1, tmpI);
9195   %}
9196 %}
9197 
9198 // Register Shift Right Immediate
9199 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9200   match(Set dst (RShiftL src1 src2));
9201 
9202   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f)" %}
9203   size(4);
9204   ins_encode %{
9205     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
9206     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9207   %}
9208   ins_pipe(pipe_class_default);
9209 %}
9210 
9211 // RShiftL + ConvL2I
9212 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
9213   match(Set dst (ConvL2I (RShiftL src1 src2)));
9214 
9215   format %{ "SRADI   $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
9216   size(4);
9217   ins_encode %{
9218     // TODO: PPC port $archOpcode(ppc64Opcode_sradi);
9219     __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9220   %}
9221   ins_pipe(pipe_class_default);
9222 %}
9223 
9224 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9225   // no match-rule, false predicate
9226   effect(DEF dst, USE src1, USE src2);
9227   predicate(false);
9228 
9229   format %{ "SRW     $dst, $src1, $src2" %}
9230   size(4);
9231   ins_encode %{
9232     // TODO: PPC port $archOpcode(ppc64Opcode_srw);
9233     __ srw($dst$$Register, $src1$$Register, $src2$$Register);
9234   %}
9235   ins_pipe(pipe_class_default);
9236 %}
9237 
9238 // Register Shift Right
9239 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9240   match(Set dst (URShiftI src1 src2));
9241   ins_cost(DEFAULT_COST*2);
9242 
9243   expand %{
9244     uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %}
9245     iRegIdst tmpI;
9246     maskI_reg_imm(tmpI, src2, mask);
9247     urShiftI_reg_reg(dst, src1, tmpI);
9248   %}
9249 %}
9250 
9251 // Register Shift Right Immediate
9252 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{
9253   match(Set dst (URShiftI src1 src2));
9254 
9255   format %{ "SRWI    $dst, $src1, ($src2 & 0x1f)" %}
9256   size(4);
9257   ins_encode %{
9258     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9259     __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f);
9260   %}
9261   ins_pipe(pipe_class_default);
9262 %}
9263 
9264 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9265   // no match-rule, false predicate
9266   effect(DEF dst, USE src1, USE src2);
9267   predicate(false);
9268 
9269   format %{ "SRD     $dst, $src1, $src2" %}
9270   size(4);
9271   ins_encode %{
9272     // TODO: PPC port $archOpcode(ppc64Opcode_srd);
9273     __ srd($dst$$Register, $src1$$Register, $src2$$Register);
9274   %}
9275   ins_pipe(pipe_class_default);
9276 %}
9277 
9278 // Register Shift Right
9279 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{
9280   match(Set dst (URShiftL src1 src2));
9281   ins_cost(DEFAULT_COST*2);
9282 
9283   expand %{
9284     uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %}
9285     iRegIdst tmpI;
9286     maskI_reg_imm(tmpI, src2, mask);
9287     urShiftL_regL_regI(dst, src1, tmpI);
9288   %}
9289 %}
9290 
9291 // Register Shift Right Immediate
9292 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{
9293   match(Set dst (URShiftL src1 src2));
9294 
9295   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f)" %}
9296   size(4);
9297   ins_encode %{
9298     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9299     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9300   %}
9301   ins_pipe(pipe_class_default);
9302 %}
9303 
9304 // URShiftL + ConvL2I.
9305 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{
9306   match(Set dst (ConvL2I (URShiftL src1 src2)));
9307 
9308   format %{ "SRDI    $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %}
9309   size(4);
9310   ins_encode %{
9311     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9312     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9313   %}
9314   ins_pipe(pipe_class_default);
9315 %}
9316 
9317 // Register Shift Right Immediate with a CastP2X
9318 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{
9319   match(Set dst (URShiftL (CastP2X src1) src2));
9320 
9321   format %{ "SRDI    $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %}
9322   size(4);
9323   ins_encode %{
9324     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9325     __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f);
9326   %}
9327   ins_pipe(pipe_class_default);
9328 %}
9329 
9330 // Bitfield Extract: URShiftI + AndI
9331 instruct andI_urShiftI_regI_immI_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immI src2, immIpow2minus1 src3) %{
9332   match(Set dst (AndI (URShiftI src1 src2) src3));
9333 
9334   format %{ "EXTRDI  $dst, $src1, shift=$src2, mask=$src3 \t// int bitfield extract" %}
9335   size(4);
9336   ins_encode %{
9337     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9338     int rshift = ($src2$$constant) & 0x1f;
9339     int length = log2_long(((jlong) $src3$$constant) + 1);
9340     if (rshift + length > 32) {
9341       // if necessary, adjust mask to omit rotated bits.
9342       length = 32 - rshift;
9343     }
9344     __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
9345   %}
9346   ins_pipe(pipe_class_default);
9347 %}
9348 
9349 // Bitfield Extract: URShiftL + AndL
9350 instruct andL_urShiftL_regL_immI_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immI src2, immLpow2minus1 src3) %{
9351   match(Set dst (AndL (URShiftL src1 src2) src3));
9352 
9353   format %{ "EXTRDI  $dst, $src1, shift=$src2, mask=$src3 \t// long bitfield extract" %}
9354   size(4);
9355   ins_encode %{
9356     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9357     int rshift  = ($src2$$constant) & 0x3f;
9358     int length = log2_long(((jlong) $src3$$constant) + 1);
9359     if (rshift + length > 64) {
9360       // if necessary, adjust mask to omit rotated bits.
9361       length = 64 - rshift;
9362     }
9363     __ extrdi($dst$$Register, $src1$$Register, length, 64 - (rshift + length));
9364   %}
9365   ins_pipe(pipe_class_default);
9366 %}
9367 
9368 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{
9369   match(Set dst (ConvL2I (ConvI2L src)));
9370 
9371   format %{ "EXTSW   $dst, $src \t// int->int" %}
9372   size(4);
9373   ins_encode %{
9374     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
9375     __ extsw($dst$$Register, $src$$Register);
9376   %}
9377   ins_pipe(pipe_class_default);
9378 %}
9379 
9380 //----------Rotate Instructions------------------------------------------------
9381 
9382 // Rotate Left by 8-bit immediate
9383 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{
9384   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
9385   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9386 
9387   format %{ "ROTLWI  $dst, $src, $lshift" %}
9388   size(4);
9389   ins_encode %{
9390     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9391     __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant);
9392   %}
9393   ins_pipe(pipe_class_default);
9394 %}
9395 
9396 // Rotate Right by 8-bit immediate
9397 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{
9398   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
9399   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
9400 
9401   format %{ "ROTRWI  $dst, $rshift" %}
9402   size(4);
9403   ins_encode %{
9404     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9405     __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant);
9406   %}
9407   ins_pipe(pipe_class_default);
9408 %}
9409 
9410 //----------Floating Point Arithmetic Instructions-----------------------------
9411 
9412 // Add float single precision
9413 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
9414   match(Set dst (AddF src1 src2));
9415 
9416   format %{ "FADDS   $dst, $src1, $src2" %}
9417   size(4);
9418   ins_encode %{
9419     // TODO: PPC port $archOpcode(ppc64Opcode_fadds);
9420     __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9421   %}
9422   ins_pipe(pipe_class_default);
9423 %}
9424 
9425 // Add float double precision
9426 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
9427   match(Set dst (AddD src1 src2));
9428 
9429   format %{ "FADD    $dst, $src1, $src2" %}
9430   size(4);
9431   ins_encode %{
9432     // TODO: PPC port $archOpcode(ppc64Opcode_fadd);
9433     __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9434   %}
9435   ins_pipe(pipe_class_default);
9436 %}
9437 
9438 // Sub float single precision
9439 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
9440   match(Set dst (SubF src1 src2));
9441 
9442   format %{ "FSUBS   $dst, $src1, $src2" %}
9443   size(4);
9444   ins_encode %{
9445     // TODO: PPC port $archOpcode(ppc64Opcode_fsubs);
9446     __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9447   %}
9448   ins_pipe(pipe_class_default);
9449 %}
9450 
9451 // Sub float double precision
9452 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
9453   match(Set dst (SubD src1 src2));
9454   format %{ "FSUB    $dst, $src1, $src2" %}
9455   size(4);
9456   ins_encode %{
9457     // TODO: PPC port $archOpcode(ppc64Opcode_fsub);
9458     __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9459   %}
9460   ins_pipe(pipe_class_default);
9461 %}
9462 
9463 // Mul float single precision
9464 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
9465   match(Set dst (MulF src1 src2));
9466   format %{ "FMULS   $dst, $src1, $src2" %}
9467   size(4);
9468   ins_encode %{
9469     // TODO: PPC port $archOpcode(ppc64Opcode_fmuls);
9470     __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9471   %}
9472   ins_pipe(pipe_class_default);
9473 %}
9474 
9475 // Mul float double precision
9476 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
9477   match(Set dst (MulD src1 src2));
9478   format %{ "FMUL    $dst, $src1, $src2" %}
9479   size(4);
9480   ins_encode %{
9481     // TODO: PPC port $archOpcode(ppc64Opcode_fmul);
9482     __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9483   %}
9484   ins_pipe(pipe_class_default);
9485 %}
9486 
9487 // Div float single precision
9488 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
9489   match(Set dst (DivF src1 src2));
9490   format %{ "FDIVS   $dst, $src1, $src2" %}
9491   size(4);
9492   ins_encode %{
9493     // TODO: PPC port $archOpcode(ppc64Opcode_fdivs);
9494     __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9495   %}
9496   ins_pipe(pipe_class_default);
9497 %}
9498 
9499 // Div float double precision
9500 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
9501   match(Set dst (DivD src1 src2));
9502   format %{ "FDIV    $dst, $src1, $src2" %}
9503   size(4);
9504   ins_encode %{
9505     // TODO: PPC port $archOpcode(ppc64Opcode_fdiv);
9506     __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
9507   %}
9508   ins_pipe(pipe_class_default);
9509 %}
9510 
9511 // Absolute float single precision
9512 instruct absF_reg(regF dst, regF src) %{
9513   match(Set dst (AbsF src));
9514   format %{ "FABS    $dst, $src \t// float" %}
9515   size(4);
9516   ins_encode %{
9517     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
9518     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
9519   %}
9520   ins_pipe(pipe_class_default);
9521 %}
9522 
9523 // Absolute float double precision
9524 instruct absD_reg(regD dst, regD src) %{
9525   match(Set dst (AbsD src));
9526   format %{ "FABS    $dst, $src \t// double" %}
9527   size(4);
9528   ins_encode %{
9529     // TODO: PPC port $archOpcode(ppc64Opcode_fabs);
9530     __ fabs($dst$$FloatRegister, $src$$FloatRegister);
9531   %}
9532   ins_pipe(pipe_class_default);
9533 %}
9534 
9535 instruct negF_reg(regF dst, regF src) %{
9536   match(Set dst (NegF src));
9537   format %{ "FNEG    $dst, $src \t// float" %}
9538   size(4);
9539   ins_encode %{
9540     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
9541     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
9542   %}
9543   ins_pipe(pipe_class_default);
9544 %}
9545 
9546 instruct negD_reg(regD dst, regD src) %{
9547   match(Set dst (NegD src));
9548   format %{ "FNEG    $dst, $src \t// double" %}
9549   size(4);
9550   ins_encode %{
9551     // TODO: PPC port $archOpcode(ppc64Opcode_fneg);
9552     __ fneg($dst$$FloatRegister, $src$$FloatRegister);
9553   %}
9554   ins_pipe(pipe_class_default);
9555 %}
9556 
9557 // AbsF + NegF.
9558 instruct negF_absF_reg(regF dst, regF src) %{
9559   match(Set dst (NegF (AbsF src)));
9560   format %{ "FNABS   $dst, $src \t// float" %}
9561   size(4);
9562   ins_encode %{
9563     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
9564     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
9565   %}
9566   ins_pipe(pipe_class_default);
9567 %}
9568 
9569 // AbsD + NegD.
9570 instruct negD_absD_reg(regD dst, regD src) %{
9571   match(Set dst (NegD (AbsD src)));
9572   format %{ "FNABS   $dst, $src \t// double" %}
9573   size(4);
9574   ins_encode %{
9575     // TODO: PPC port $archOpcode(ppc64Opcode_fnabs);
9576     __ fnabs($dst$$FloatRegister, $src$$FloatRegister);
9577   %}
9578   ins_pipe(pipe_class_default);
9579 %}
9580 
9581 // VM_Version::has_fsqrt() decides if this node will be used.
9582 // Sqrt float double precision
9583 instruct sqrtD_reg(regD dst, regD src) %{
9584   match(Set dst (SqrtD src));
9585   format %{ "FSQRT   $dst, $src" %}
9586   size(4);
9587   ins_encode %{
9588     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt);
9589     __ fsqrt($dst$$FloatRegister, $src$$FloatRegister);
9590   %}
9591   ins_pipe(pipe_class_default);
9592 %}
9593 
9594 // Single-precision sqrt.
9595 instruct sqrtF_reg(regF dst, regF src) %{
9596   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
9597   predicate(VM_Version::has_fsqrts());
9598   ins_cost(DEFAULT_COST);
9599 
9600   format %{ "FSQRTS  $dst, $src" %}
9601   size(4);
9602   ins_encode %{
9603     // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts);
9604     __ fsqrts($dst$$FloatRegister, $src$$FloatRegister);
9605   %}
9606   ins_pipe(pipe_class_default);
9607 %}
9608 
9609 instruct roundDouble_nop(regD dst) %{
9610   match(Set dst (RoundDouble dst));
9611   ins_cost(0);
9612 
9613   format %{ " -- \t// RoundDouble not needed - empty" %}
9614   size(0);
9615   // PPC results are already "rounded" (i.e., normal-format IEEE).
9616   ins_encode( /*empty*/ );
9617   ins_pipe(pipe_class_default);
9618 %}
9619 
9620 instruct roundFloat_nop(regF dst) %{
9621   match(Set dst (RoundFloat dst));
9622   ins_cost(0);
9623 
9624   format %{ " -- \t// RoundFloat not needed - empty" %}
9625   size(0);
9626   // PPC results are already "rounded" (i.e., normal-format IEEE).
9627   ins_encode( /*empty*/ );
9628   ins_pipe(pipe_class_default);
9629 %}
9630 
9631 
9632 // Multiply-Accumulate
9633 // src1 * src2 + src3
9634 instruct maddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9635   match(Set dst (FmaF src3 (Binary src1 src2)));
9636 
9637   format %{ "FMADDS  $dst, $src1, $src2, $src3" %}
9638   size(4);
9639   ins_encode %{
9640     // TODO: PPC port $archOpcode(ppc64Opcode_fmadds);
9641     __ fmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9642   %}
9643   ins_pipe(pipe_class_default);
9644 %}
9645 
9646 // src1 * src2 + src3
9647 instruct maddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9648   match(Set dst (FmaD src3 (Binary src1 src2)));
9649 
9650   format %{ "FMADD   $dst, $src1, $src2, $src3" %}
9651   size(4);
9652   ins_encode %{
9653     // TODO: PPC port $archOpcode(ppc64Opcode_fmadd);
9654     __ fmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9655   %}
9656   ins_pipe(pipe_class_default);
9657 %}
9658 
9659 // -src1 * src2 + src3 = -(src1*src2-src3)
9660 instruct mnsubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9661   match(Set dst (FmaF src3 (Binary (NegF src1) src2)));
9662   match(Set dst (FmaF src3 (Binary src1 (NegF src2))));
9663 
9664   format %{ "FNMSUBS $dst, $src1, $src2, $src3" %}
9665   size(4);
9666   ins_encode %{
9667     // TODO: PPC port $archOpcode(ppc64Opcode_fnmsubs);
9668     __ fnmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9669   %}
9670   ins_pipe(pipe_class_default);
9671 %}
9672 
9673 // -src1 * src2 + src3 = -(src1*src2-src3)
9674 instruct mnsubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9675   match(Set dst (FmaD src3 (Binary (NegD src1) src2)));
9676   match(Set dst (FmaD src3 (Binary src1 (NegD src2))));
9677 
9678   format %{ "FNMSUB  $dst, $src1, $src2, $src3" %}
9679   size(4);
9680   ins_encode %{
9681     // TODO: PPC port $archOpcode(ppc64Opcode_fnmsub);
9682     __ fnmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9683   %}
9684   ins_pipe(pipe_class_default);
9685 %}
9686 
9687 // -src1 * src2 - src3 = -(src1*src2+src3)
9688 instruct mnaddF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9689   match(Set dst (FmaF (NegF src3) (Binary (NegF src1) src2)));
9690   match(Set dst (FmaF (NegF src3) (Binary src1 (NegF src2))));
9691 
9692   format %{ "FNMADDS $dst, $src1, $src2, $src3" %}
9693   size(4);
9694   ins_encode %{
9695     // TODO: PPC port $archOpcode(ppc64Opcode_fnmadds);
9696     __ fnmadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9697   %}
9698   ins_pipe(pipe_class_default);
9699 %}
9700 
9701 // -src1 * src2 - src3 = -(src1*src2+src3)
9702 instruct mnaddD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9703   match(Set dst (FmaD (NegD src3) (Binary (NegD src1) src2)));
9704   match(Set dst (FmaD (NegD src3) (Binary src1 (NegD src2))));
9705 
9706   format %{ "FNMADD  $dst, $src1, $src2, $src3" %}
9707   size(4);
9708   ins_encode %{
9709     // TODO: PPC port $archOpcode(ppc64Opcode_fnmadd);
9710     __ fnmadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9711   %}
9712   ins_pipe(pipe_class_default);
9713 %}
9714 
9715 // src1 * src2 - src3
9716 instruct msubF_reg_reg(regF dst, regF src1, regF src2, regF src3) %{
9717   match(Set dst (FmaF (NegF src3) (Binary src1 src2)));
9718 
9719   format %{ "FMSUBS  $dst, $src1, $src2, $src3" %}
9720   size(4);
9721   ins_encode %{
9722     // TODO: PPC port $archOpcode(ppc64Opcode_fmsubs);
9723     __ fmsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9724   %}
9725   ins_pipe(pipe_class_default);
9726 %}
9727 
9728 // src1 * src2 - src3
9729 instruct msubD_reg_reg(regD dst, regD src1, regD src2, regD src3) %{
9730   match(Set dst (FmaD (NegD src3) (Binary src1 src2)));
9731 
9732   format %{ "FMSUB   $dst, $src1, $src2, $src3" %}
9733   size(4);
9734   ins_encode %{
9735     // TODO: PPC port $archOpcode(ppc64Opcode_fmsub);
9736     __ fmsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister, $src3$$FloatRegister);
9737   %}
9738   ins_pipe(pipe_class_default);
9739 %}
9740 
9741 
9742 //----------Logical Instructions-----------------------------------------------
9743 
9744 // And Instructions
9745 
9746 // Register And
9747 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9748   match(Set dst (AndI src1 src2));
9749   format %{ "AND     $dst, $src1, $src2" %}
9750   size(4);
9751   ins_encode %{
9752     // TODO: PPC port $archOpcode(ppc64Opcode_and);
9753     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9754   %}
9755   ins_pipe(pipe_class_default);
9756 %}
9757 
9758 // Left shifted Immediate And
9759 instruct andI_reg_immIhi16(iRegIdst dst, iRegIsrc src1, immIhi16  src2, flagsRegCR0 cr0) %{
9760   match(Set dst (AndI src1 src2));
9761   effect(KILL cr0);
9762   format %{ "ANDIS   $dst, $src1, $src2.hi" %}
9763   size(4);
9764   ins_encode %{
9765     // TODO: PPC port $archOpcode(ppc64Opcode_andis_);
9766     __ andis_($dst$$Register, $src1$$Register, (int)((unsigned short)(($src2$$constant & 0xFFFF0000) >> 16)));
9767   %}
9768   ins_pipe(pipe_class_default);
9769 %}
9770 
9771 // Immediate And
9772 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{
9773   match(Set dst (AndI src1 src2));
9774   effect(KILL cr0);
9775 
9776   format %{ "ANDI    $dst, $src1, $src2" %}
9777   size(4);
9778   ins_encode %{
9779     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
9780     // FIXME: avoid andi_ ?
9781     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9782   %}
9783   ins_pipe(pipe_class_default);
9784 %}
9785 
9786 // Immediate And where the immediate is a negative power of 2.
9787 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{
9788   match(Set dst (AndI src1 src2));
9789   format %{ "ANDWI   $dst, $src1, $src2" %}
9790   size(4);
9791   ins_encode %{
9792     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9793     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant)));
9794   %}
9795   ins_pipe(pipe_class_default);
9796 %}
9797 
9798 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{
9799   match(Set dst (AndI src1 src2));
9800   format %{ "ANDWI   $dst, $src1, $src2" %}
9801   size(4);
9802   ins_encode %{
9803     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9804     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9805   %}
9806   ins_pipe(pipe_class_default);
9807 %}
9808 
9809 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{
9810   match(Set dst (AndI src1 src2));
9811   predicate(UseRotateAndMaskInstructionsPPC64);
9812   format %{ "ANDWI   $dst, $src1, $src2" %}
9813   size(4);
9814   ins_encode %{
9815     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
9816     __ rlwinm($dst$$Register, $src1$$Register, 0,
9817               (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f);
9818   %}
9819   ins_pipe(pipe_class_default);
9820 %}
9821 
9822 // Register And Long
9823 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9824   match(Set dst (AndL src1 src2));
9825   ins_cost(DEFAULT_COST);
9826 
9827   format %{ "AND     $dst, $src1, $src2 \t// long" %}
9828   size(4);
9829   ins_encode %{
9830     // TODO: PPC port $archOpcode(ppc64Opcode_and);
9831     __ andr($dst$$Register, $src1$$Register, $src2$$Register);
9832   %}
9833   ins_pipe(pipe_class_default);
9834 %}
9835 
9836 // Immediate And long
9837 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{
9838   match(Set dst (AndL src1 src2));
9839   effect(KILL cr0);
9840 
9841   format %{ "ANDI    $dst, $src1, $src2 \t// long" %}
9842   size(4);
9843   ins_encode %{
9844     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
9845     // FIXME: avoid andi_ ?
9846     __ andi_($dst$$Register, $src1$$Register, $src2$$constant);
9847   %}
9848   ins_pipe(pipe_class_default);
9849 %}
9850 
9851 // Immediate And Long where the immediate is a negative power of 2.
9852 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{
9853   match(Set dst (AndL src1 src2));
9854   format %{ "ANDDI   $dst, $src1, $src2" %}
9855   size(4);
9856   ins_encode %{
9857     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
9858     __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant));
9859   %}
9860   ins_pipe(pipe_class_default);
9861 %}
9862 
9863 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9864   match(Set dst (AndL src1 src2));
9865   format %{ "ANDDI   $dst, $src1, $src2" %}
9866   size(4);
9867   ins_encode %{
9868     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9869     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9870   %}
9871   ins_pipe(pipe_class_default);
9872 %}
9873 
9874 // AndL + ConvL2I.
9875 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{
9876   match(Set dst (ConvL2I (AndL src1 src2)));
9877   ins_cost(DEFAULT_COST);
9878 
9879   format %{ "ANDDI   $dst, $src1, $src2 \t// long + l2i" %}
9880   size(4);
9881   ins_encode %{
9882     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
9883     __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1)));
9884   %}
9885   ins_pipe(pipe_class_default);
9886 %}
9887 
9888 // Or Instructions
9889 
9890 // Register Or
9891 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9892   match(Set dst (OrI src1 src2));
9893   format %{ "OR      $dst, $src1, $src2" %}
9894   size(4);
9895   ins_encode %{
9896     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9897     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9898   %}
9899   ins_pipe(pipe_class_default);
9900 %}
9901 
9902 // Expand does not work with above instruct. (??)
9903 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9904   // no match-rule
9905   effect(DEF dst, USE src1, USE src2);
9906   format %{ "OR      $dst, $src1, $src2" %}
9907   size(4);
9908   ins_encode %{
9909     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9910     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9911   %}
9912   ins_pipe(pipe_class_default);
9913 %}
9914 
9915 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
9916   match(Set dst (OrI (OrI (OrI src1 src2) src3) src4));
9917   ins_cost(DEFAULT_COST*3);
9918 
9919   expand %{
9920     // FIXME: we should do this in the ideal world.
9921     iRegIdst tmp1;
9922     iRegIdst tmp2;
9923     orI_reg_reg(tmp1, src1, src2);
9924     orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg.
9925     orI_reg_reg(dst, tmp1, tmp2);
9926   %}
9927 %}
9928 
9929 // Immediate Or
9930 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
9931   match(Set dst (OrI src1 src2));
9932   format %{ "ORI     $dst, $src1, $src2" %}
9933   size(4);
9934   ins_encode %{
9935     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9936     __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF);
9937   %}
9938   ins_pipe(pipe_class_default);
9939 %}
9940 
9941 // Register Or Long
9942 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
9943   match(Set dst (OrL src1 src2));
9944   ins_cost(DEFAULT_COST);
9945 
9946   size(4);
9947   format %{ "OR      $dst, $src1, $src2 \t// long" %}
9948   ins_encode %{
9949     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9950     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9951   %}
9952   ins_pipe(pipe_class_default);
9953 %}
9954 
9955 // OrL + ConvL2I.
9956 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
9957   match(Set dst (ConvL2I (OrL src1 src2)));
9958   ins_cost(DEFAULT_COST);
9959 
9960   format %{ "OR      $dst, $src1, $src2 \t// long + l2i" %}
9961   size(4);
9962   ins_encode %{
9963     // TODO: PPC port $archOpcode(ppc64Opcode_or);
9964     __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register);
9965   %}
9966   ins_pipe(pipe_class_default);
9967 %}
9968 
9969 // Immediate Or long
9970 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{
9971   match(Set dst (OrL src1 con));
9972   ins_cost(DEFAULT_COST);
9973 
9974   format %{ "ORI     $dst, $src1, $con \t// long" %}
9975   size(4);
9976   ins_encode %{
9977     // TODO: PPC port $archOpcode(ppc64Opcode_ori);
9978     __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF);
9979   %}
9980   ins_pipe(pipe_class_default);
9981 %}
9982 
9983 // Xor Instructions
9984 
9985 // Register Xor
9986 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9987   match(Set dst (XorI src1 src2));
9988   format %{ "XOR     $dst, $src1, $src2" %}
9989   size(4);
9990   ins_encode %{
9991     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
9992     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
9993   %}
9994   ins_pipe(pipe_class_default);
9995 %}
9996 
9997 // Expand does not work with above instruct. (??)
9998 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
9999   // no match-rule
10000   effect(DEF dst, USE src1, USE src2);
10001   format %{ "XOR     $dst, $src1, $src2" %}
10002   size(4);
10003   ins_encode %{
10004     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
10005     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
10006   %}
10007   ins_pipe(pipe_class_default);
10008 %}
10009 
10010 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{
10011   match(Set dst (XorI (XorI (XorI src1 src2) src3) src4));
10012   ins_cost(DEFAULT_COST*3);
10013 
10014   expand %{
10015     // FIXME: we should do this in the ideal world.
10016     iRegIdst tmp1;
10017     iRegIdst tmp2;
10018     xorI_reg_reg(tmp1, src1, src2);
10019     xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg.
10020     xorI_reg_reg(dst, tmp1, tmp2);
10021   %}
10022 %}
10023 
10024 // Immediate Xor
10025 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{
10026   match(Set dst (XorI src1 src2));
10027   format %{ "XORI    $dst, $src1, $src2" %}
10028   size(4);
10029   ins_encode %{
10030     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
10031     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
10032   %}
10033   ins_pipe(pipe_class_default);
10034 %}
10035 
10036 // Register Xor Long
10037 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
10038   match(Set dst (XorL src1 src2));
10039   ins_cost(DEFAULT_COST);
10040 
10041   format %{ "XOR     $dst, $src1, $src2 \t// long" %}
10042   size(4);
10043   ins_encode %{
10044     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
10045     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
10046   %}
10047   ins_pipe(pipe_class_default);
10048 %}
10049 
10050 // XorL + ConvL2I.
10051 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
10052   match(Set dst (ConvL2I (XorL src1 src2)));
10053   ins_cost(DEFAULT_COST);
10054 
10055   format %{ "XOR     $dst, $src1, $src2 \t// long + l2i" %}
10056   size(4);
10057   ins_encode %{
10058     // TODO: PPC port $archOpcode(ppc64Opcode_xor);
10059     __ xorr($dst$$Register, $src1$$Register, $src2$$Register);
10060   %}
10061   ins_pipe(pipe_class_default);
10062 %}
10063 
10064 // Immediate Xor Long
10065 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{
10066   match(Set dst (XorL src1 src2));
10067   ins_cost(DEFAULT_COST);
10068 
10069   format %{ "XORI    $dst, $src1, $src2 \t// long" %}
10070   size(4);
10071   ins_encode %{
10072     // TODO: PPC port $archOpcode(ppc64Opcode_xori);
10073     __ xori($dst$$Register, $src1$$Register, $src2$$constant);
10074   %}
10075   ins_pipe(pipe_class_default);
10076 %}
10077 
10078 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{
10079   match(Set dst (XorI src1 src2));
10080   ins_cost(DEFAULT_COST);
10081 
10082   format %{ "NOT     $dst, $src1 ($src2)" %}
10083   size(4);
10084   ins_encode %{
10085     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
10086     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
10087   %}
10088   ins_pipe(pipe_class_default);
10089 %}
10090 
10091 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{
10092   match(Set dst (XorL src1 src2));
10093   ins_cost(DEFAULT_COST);
10094 
10095   format %{ "NOT     $dst, $src1 ($src2) \t// long" %}
10096   size(4);
10097   ins_encode %{
10098     // TODO: PPC port $archOpcode(ppc64Opcode_nor);
10099     __ nor($dst$$Register, $src1$$Register, $src1$$Register);
10100   %}
10101   ins_pipe(pipe_class_default);
10102 %}
10103 
10104 // And-complement
10105 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{
10106   match(Set dst (AndI (XorI src1 src2) src3));
10107   ins_cost(DEFAULT_COST);
10108 
10109   format %{ "ANDW    $dst, xori($src1, $src2), $src3" %}
10110   size(4);
10111   ins_encode( enc_andc(dst, src3, src1) );
10112   ins_pipe(pipe_class_default);
10113 %}
10114 
10115 // And-complement
10116 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{
10117   // no match-rule, false predicate
10118   effect(DEF dst, USE src1, USE src2);
10119   predicate(false);
10120 
10121   format %{ "ANDC    $dst, $src1, $src2" %}
10122   size(4);
10123   ins_encode %{
10124     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
10125     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
10126   %}
10127   ins_pipe(pipe_class_default);
10128 %}
10129 
10130 //----------Moves between int/long and float/double----------------------------
10131 //
10132 // The following rules move values from int/long registers/stack-locations
10133 // to float/double registers/stack-locations and vice versa, without doing any
10134 // conversions. These rules are used to implement the bit-conversion methods
10135 // of java.lang.Float etc., e.g.
10136 //   int   floatToIntBits(float value)
10137 //   float intBitsToFloat(int bits)
10138 //
10139 // Notes on the implementation on ppc64:
10140 // For Power7 and earlier, the rules are limited to those which move between a
10141 // register and a stack-location, because we always have to go through memory
10142 // when moving between a float register and an integer register.
10143 // This restriction is removed in Power8 with the introduction of the mtfprd
10144 // and mffprd instructions.
10145 
10146 instruct moveL2D_reg(regD dst, iRegLsrc src) %{
10147   match(Set dst (MoveL2D src));
10148   predicate(VM_Version::has_mtfprd());
10149 
10150   format %{ "MTFPRD  $dst, $src" %}
10151   size(4);
10152   ins_encode %{
10153     __ mtfprd($dst$$FloatRegister, $src$$Register);
10154   %}
10155   ins_pipe(pipe_class_default);
10156 %}
10157 
10158 instruct moveI2D_reg(regD dst, iRegIsrc src) %{
10159   // no match-rule, false predicate
10160   effect(DEF dst, USE src);
10161   predicate(false);
10162 
10163   format %{ "MTFPRWA $dst, $src" %}
10164   size(4);
10165   ins_encode %{
10166     __ mtfprwa($dst$$FloatRegister, $src$$Register);
10167   %}
10168   ins_pipe(pipe_class_default);
10169 %}
10170 
10171 //---------- Chain stack slots between similar types --------
10172 
10173 // These are needed so that the rules below can match.
10174 
10175 // Load integer from stack slot
10176 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
10177   match(Set dst src);
10178   ins_cost(MEMORY_REF_COST);
10179 
10180   format %{ "LWZ     $dst, $src" %}
10181   size(4);
10182   ins_encode( enc_lwz(dst, src) );
10183   ins_pipe(pipe_class_memory);
10184 %}
10185 
10186 // Store integer to stack slot
10187 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
10188   match(Set dst src);
10189   ins_cost(MEMORY_REF_COST);
10190 
10191   format %{ "STW     $src, $dst \t// stk" %}
10192   size(4);
10193   ins_encode( enc_stw(src, dst) ); // rs=rt
10194   ins_pipe(pipe_class_memory);
10195 %}
10196 
10197 // Load long from stack slot
10198 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{
10199   match(Set dst src);
10200   ins_cost(MEMORY_REF_COST);
10201 
10202   format %{ "LD      $dst, $src \t// long" %}
10203   size(4);
10204   ins_encode( enc_ld(dst, src) );
10205   ins_pipe(pipe_class_memory);
10206 %}
10207 
10208 // Store long to stack slot
10209 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{
10210   match(Set dst src);
10211   ins_cost(MEMORY_REF_COST);
10212 
10213   format %{ "STD     $src, $dst \t// long" %}
10214   size(4);
10215   ins_encode( enc_std(src, dst) ); // rs=rt
10216   ins_pipe(pipe_class_memory);
10217 %}
10218 
10219 //----------Moves between int and float
10220 
10221 // Move float value from float stack-location to integer register.
10222 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{
10223   match(Set dst (MoveF2I src));
10224   ins_cost(MEMORY_REF_COST);
10225 
10226   format %{ "LWZ     $dst, $src \t// MoveF2I" %}
10227   size(4);
10228   ins_encode( enc_lwz(dst, src) );
10229   ins_pipe(pipe_class_memory);
10230 %}
10231 
10232 // Move float value from float register to integer stack-location.
10233 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{
10234   match(Set dst (MoveF2I src));
10235   ins_cost(MEMORY_REF_COST);
10236 
10237   format %{ "STFS    $src, $dst \t// MoveF2I" %}
10238   size(4);
10239   ins_encode( enc_stfs(src, dst) );
10240   ins_pipe(pipe_class_memory);
10241 %}
10242 
10243 // Move integer value from integer stack-location to float register.
10244 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{
10245   match(Set dst (MoveI2F src));
10246   ins_cost(MEMORY_REF_COST);
10247 
10248   format %{ "LFS     $dst, $src \t// MoveI2F" %}
10249   size(4);
10250   ins_encode %{
10251     // TODO: PPC port $archOpcode(ppc64Opcode_lfs);
10252     int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_);
10253     __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register);
10254   %}
10255   ins_pipe(pipe_class_memory);
10256 %}
10257 
10258 // Move integer value from integer register to float stack-location.
10259 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{
10260   match(Set dst (MoveI2F src));
10261   ins_cost(MEMORY_REF_COST);
10262 
10263   format %{ "STW     $src, $dst \t// MoveI2F" %}
10264   size(4);
10265   ins_encode( enc_stw(src, dst) );
10266   ins_pipe(pipe_class_memory);
10267 %}
10268 
10269 //----------Moves between long and float
10270 
10271 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{
10272   // no match-rule, false predicate
10273   effect(DEF dst, USE src);
10274   predicate(false);
10275 
10276   format %{ "storeD  $src, $dst \t// STACK" %}
10277   size(4);
10278   ins_encode( enc_stfd(src, dst) );
10279   ins_pipe(pipe_class_default);
10280 %}
10281 
10282 //----------Moves between long and double
10283 
10284 // Move double value from double stack-location to long register.
10285 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{
10286   match(Set dst (MoveD2L src));
10287   ins_cost(MEMORY_REF_COST);
10288   size(4);
10289   format %{ "LD      $dst, $src \t// MoveD2L" %}
10290   ins_encode( enc_ld(dst, src) );
10291   ins_pipe(pipe_class_memory);
10292 %}
10293 
10294 // Move double value from double register to long stack-location.
10295 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{
10296   match(Set dst (MoveD2L src));
10297   effect(DEF dst, USE src);
10298   ins_cost(MEMORY_REF_COST);
10299 
10300   format %{ "STFD    $src, $dst \t// MoveD2L" %}
10301   size(4);
10302   ins_encode( enc_stfd(src, dst) );
10303   ins_pipe(pipe_class_memory);
10304 %}
10305 
10306 // Move long value from long stack-location to double register.
10307 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{
10308   match(Set dst (MoveL2D src));
10309   ins_cost(MEMORY_REF_COST);
10310 
10311   format %{ "LFD     $dst, $src \t// MoveL2D" %}
10312   size(4);
10313   ins_encode( enc_lfd(dst, src) );
10314   ins_pipe(pipe_class_memory);
10315 %}
10316 
10317 // Move long value from long register to double stack-location.
10318 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{
10319   match(Set dst (MoveL2D src));
10320   ins_cost(MEMORY_REF_COST);
10321 
10322   format %{ "STD     $src, $dst \t// MoveL2D" %}
10323   size(4);
10324   ins_encode( enc_std(src, dst) );
10325   ins_pipe(pipe_class_memory);
10326 %}
10327 
10328 //----------Register Move Instructions-----------------------------------------
10329 
10330 // Replicate for Superword
10331 
10332 instruct moveReg(iRegLdst dst, iRegIsrc src) %{
10333   predicate(false);
10334   effect(DEF dst, USE src);
10335 
10336   format %{ "MR      $dst, $src \t// replicate " %}
10337   // variable size, 0 or 4.
10338   ins_encode %{
10339     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10340     __ mr_if_needed($dst$$Register, $src$$Register);
10341   %}
10342   ins_pipe(pipe_class_default);
10343 %}
10344 
10345 //----------Cast instructions (Java-level type cast)---------------------------
10346 
10347 // Cast Long to Pointer for unsafe natives.
10348 instruct castX2P(iRegPdst dst, iRegLsrc src) %{
10349   match(Set dst (CastX2P src));
10350 
10351   format %{ "MR      $dst, $src \t// Long->Ptr" %}
10352   // variable size, 0 or 4.
10353   ins_encode %{
10354     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10355     __ mr_if_needed($dst$$Register, $src$$Register);
10356   %}
10357  ins_pipe(pipe_class_default);
10358 %}
10359 
10360 // Cast Pointer to Long for unsafe natives.
10361 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{
10362   match(Set dst (CastP2X src));
10363 
10364   format %{ "MR      $dst, $src \t// Ptr->Long" %}
10365   // variable size, 0 or 4.
10366   ins_encode %{
10367     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10368     __ mr_if_needed($dst$$Register, $src$$Register);
10369   %}
10370   ins_pipe(pipe_class_default);
10371 %}
10372 
10373 instruct castPP(iRegPdst dst) %{
10374   match(Set dst (CastPP dst));
10375   format %{ " -- \t// castPP of $dst" %}
10376   size(0);
10377   ins_encode( /*empty*/ );
10378   ins_pipe(pipe_class_default);
10379 %}
10380 
10381 instruct castII(iRegIdst dst) %{
10382   match(Set dst (CastII dst));
10383   format %{ " -- \t// castII of $dst" %}
10384   size(0);
10385   ins_encode( /*empty*/ );
10386   ins_pipe(pipe_class_default);
10387 %}
10388 
10389 instruct checkCastPP(iRegPdst dst) %{
10390   match(Set dst (CheckCastPP dst));
10391   format %{ " -- \t// checkcastPP of $dst" %}
10392   size(0);
10393   ins_encode( /*empty*/ );
10394   ins_pipe(pipe_class_default);
10395 %}
10396 
10397 //----------Convert instructions-----------------------------------------------
10398 
10399 // Convert to boolean.
10400 
10401 // int_to_bool(src) : { 1   if src != 0
10402 //                    { 0   else
10403 //
10404 // strategy:
10405 // 1) Count leading zeros of 32 bit-value src,
10406 //    this returns 32 (0b10.0000) iff src == 0 and <32 otherwise.
10407 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
10408 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
10409 
10410 // convI2Bool
10411 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{
10412   match(Set dst (Conv2B src));
10413   predicate(UseCountLeadingZerosInstructionsPPC64);
10414   ins_cost(DEFAULT_COST);
10415 
10416   expand %{
10417     immI shiftAmount %{ 0x5 %}
10418     uimmI16 mask %{ 0x1 %}
10419     iRegIdst tmp1;
10420     iRegIdst tmp2;
10421     countLeadingZerosI(tmp1, src);
10422     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
10423     xorI_reg_uimm16(dst, tmp2, mask);
10424   %}
10425 %}
10426 
10427 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{
10428   match(Set dst (Conv2B src));
10429   effect(TEMP crx);
10430   predicate(!UseCountLeadingZerosInstructionsPPC64);
10431   ins_cost(DEFAULT_COST);
10432 
10433   format %{ "CMPWI   $crx, $src, #0 \t// convI2B"
10434             "LI      $dst, #0\n\t"
10435             "BEQ     $crx, done\n\t"
10436             "LI      $dst, #1\n"
10437             "done:" %}
10438   size(16);
10439   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) );
10440   ins_pipe(pipe_class_compare);
10441 %}
10442 
10443 // ConvI2B + XorI
10444 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{
10445   match(Set dst (XorI (Conv2B src) mask));
10446   predicate(UseCountLeadingZerosInstructionsPPC64);
10447   ins_cost(DEFAULT_COST);
10448 
10449   expand %{
10450     immI shiftAmount %{ 0x5 %}
10451     iRegIdst tmp1;
10452     countLeadingZerosI(tmp1, src);
10453     urShiftI_reg_imm(dst, tmp1, shiftAmount);
10454   %}
10455 %}
10456 
10457 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{
10458   match(Set dst (XorI (Conv2B src) mask));
10459   effect(TEMP crx);
10460   predicate(!UseCountLeadingZerosInstructionsPPC64);
10461   ins_cost(DEFAULT_COST);
10462 
10463   format %{ "CMPWI   $crx, $src, #0 \t// Xor(convI2B($src), $mask)"
10464             "LI      $dst, #1\n\t"
10465             "BEQ     $crx, done\n\t"
10466             "LI      $dst, #0\n"
10467             "done:" %}
10468   size(16);
10469   ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) );
10470   ins_pipe(pipe_class_compare);
10471 %}
10472 
10473 // AndI 0b0..010..0 + ConvI2B
10474 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{
10475   match(Set dst (Conv2B (AndI src mask)));
10476   predicate(UseRotateAndMaskInstructionsPPC64);
10477   ins_cost(DEFAULT_COST);
10478 
10479   format %{ "RLWINM  $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %}
10480   size(4);
10481   ins_encode %{
10482     // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm);
10483     __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31);
10484   %}
10485   ins_pipe(pipe_class_default);
10486 %}
10487 
10488 // Convert pointer to boolean.
10489 //
10490 // ptr_to_bool(src) : { 1   if src != 0
10491 //                    { 0   else
10492 //
10493 // strategy:
10494 // 1) Count leading zeros of 64 bit-value src,
10495 //    this returns 64 (0b100.0000) iff src == 0 and <64 otherwise.
10496 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise.
10497 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0.
10498 
10499 // ConvP2B
10500 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{
10501   match(Set dst (Conv2B src));
10502   predicate(UseCountLeadingZerosInstructionsPPC64);
10503   ins_cost(DEFAULT_COST);
10504 
10505   expand %{
10506     immI shiftAmount %{ 0x6 %}
10507     uimmI16 mask %{ 0x1 %}
10508     iRegIdst tmp1;
10509     iRegIdst tmp2;
10510     countLeadingZerosP(tmp1, src);
10511     urShiftI_reg_imm(tmp2, tmp1, shiftAmount);
10512     xorI_reg_uimm16(dst, tmp2, mask);
10513   %}
10514 %}
10515 
10516 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{
10517   match(Set dst (Conv2B src));
10518   effect(TEMP crx);
10519   predicate(!UseCountLeadingZerosInstructionsPPC64);
10520   ins_cost(DEFAULT_COST);
10521 
10522   format %{ "CMPDI   $crx, $src, #0 \t// convP2B"
10523             "LI      $dst, #0\n\t"
10524             "BEQ     $crx, done\n\t"
10525             "LI      $dst, #1\n"
10526             "done:" %}
10527   size(16);
10528   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) );
10529   ins_pipe(pipe_class_compare);
10530 %}
10531 
10532 // ConvP2B + XorI
10533 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{
10534   match(Set dst (XorI (Conv2B src) mask));
10535   predicate(UseCountLeadingZerosInstructionsPPC64);
10536   ins_cost(DEFAULT_COST);
10537 
10538   expand %{
10539     immI shiftAmount %{ 0x6 %}
10540     iRegIdst tmp1;
10541     countLeadingZerosP(tmp1, src);
10542     urShiftI_reg_imm(dst, tmp1, shiftAmount);
10543   %}
10544 %}
10545 
10546 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{
10547   match(Set dst (XorI (Conv2B src) mask));
10548   effect(TEMP crx);
10549   predicate(!UseCountLeadingZerosInstructionsPPC64);
10550   ins_cost(DEFAULT_COST);
10551 
10552   format %{ "CMPDI   $crx, $src, #0 \t// XorI(convP2B($src), $mask)"
10553             "LI      $dst, #1\n\t"
10554             "BEQ     $crx, done\n\t"
10555             "LI      $dst, #0\n"
10556             "done:" %}
10557   size(16);
10558   ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) );
10559   ins_pipe(pipe_class_compare);
10560 %}
10561 
10562 // if src1 < src2, return -1 else return 0
10563 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
10564   match(Set dst (CmpLTMask src1 src2));
10565   ins_cost(DEFAULT_COST*4);
10566 
10567   expand %{
10568     iRegLdst src1s;
10569     iRegLdst src2s;
10570     iRegLdst diff;
10571     convI2L_reg(src1s, src1); // Ensure proper sign extension.
10572     convI2L_reg(src2s, src2); // Ensure proper sign extension.
10573     subL_reg_reg(diff, src1s, src2s);
10574     // Need to consider >=33 bit result, therefore we need signmaskL.
10575     signmask64I_regL(dst, diff);
10576   %}
10577 %}
10578 
10579 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{
10580   match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0
10581   format %{ "SRAWI   $dst, $src1, $src2 \t// CmpLTMask" %}
10582   size(4);
10583   ins_encode %{
10584     // TODO: PPC port $archOpcode(ppc64Opcode_srawi);
10585     __ srawi($dst$$Register, $src1$$Register, 0x1f);
10586   %}
10587   ins_pipe(pipe_class_default);
10588 %}
10589 
10590 //----------Arithmetic Conversion Instructions---------------------------------
10591 
10592 // Convert to Byte  -- nop
10593 // Convert to Short -- nop
10594 
10595 // Convert to Int
10596 
10597 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{
10598   match(Set dst (RShiftI (LShiftI src amount) amount));
10599   format %{ "EXTSB   $dst, $src \t// byte->int" %}
10600   size(4);
10601   ins_encode %{
10602     // TODO: PPC port $archOpcode(ppc64Opcode_extsb);
10603     __ extsb($dst$$Register, $src$$Register);
10604   %}
10605   ins_pipe(pipe_class_default);
10606 %}
10607 
10608 instruct extsh(iRegIdst dst, iRegIsrc src) %{
10609   effect(DEF dst, USE src);
10610 
10611   size(4);
10612   ins_encode %{
10613     __ extsh($dst$$Register, $src$$Register);
10614   %}
10615   ins_pipe(pipe_class_default);
10616 %}
10617 
10618 // LShiftI 16 + RShiftI 16 converts short to int.
10619 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{
10620   match(Set dst (RShiftI (LShiftI src amount) amount));
10621   format %{ "EXTSH   $dst, $src \t// short->int" %}
10622   size(4);
10623   ins_encode %{
10624     // TODO: PPC port $archOpcode(ppc64Opcode_extsh);
10625     __ extsh($dst$$Register, $src$$Register);
10626   %}
10627   ins_pipe(pipe_class_default);
10628 %}
10629 
10630 // ConvL2I + ConvI2L: Sign extend int in long register.
10631 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{
10632   match(Set dst (ConvI2L (ConvL2I src)));
10633 
10634   format %{ "EXTSW   $dst, $src \t// long->long" %}
10635   size(4);
10636   ins_encode %{
10637     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
10638     __ extsw($dst$$Register, $src$$Register);
10639   %}
10640   ins_pipe(pipe_class_default);
10641 %}
10642 
10643 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{
10644   match(Set dst (ConvL2I src));
10645   format %{ "MR      $dst, $src \t// long->int" %}
10646   // variable size, 0 or 4
10647   ins_encode %{
10648     // TODO: PPC port $archOpcode(ppc64Opcode_or);
10649     __ mr_if_needed($dst$$Register, $src$$Register);
10650   %}
10651   ins_pipe(pipe_class_default);
10652 %}
10653 
10654 instruct convD2IRaw_regD(regD dst, regD src) %{
10655   // no match-rule, false predicate
10656   effect(DEF dst, USE src);
10657   predicate(false);
10658 
10659   format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %}
10660   size(4);
10661   ins_encode %{
10662     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
10663     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10664   %}
10665   ins_pipe(pipe_class_default);
10666 %}
10667 
10668 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
10669   // no match-rule, false predicate
10670   effect(DEF dst, USE crx, USE src);
10671   predicate(false);
10672 
10673   ins_variable_size_depending_on_alignment(true);
10674 
10675   format %{ "cmovI   $crx, $dst, $src" %}
10676   // Worst case is branch + move + stop, no stop without scheduler.
10677   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10678   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10679   ins_pipe(pipe_class_default);
10680 %}
10681 
10682 instruct cmovI_bso_reg(iRegIdst dst, flagsRegSrc crx, regD src) %{
10683   // no match-rule, false predicate
10684   effect(DEF dst, USE crx, USE src);
10685   predicate(false);
10686 
10687   ins_variable_size_depending_on_alignment(true);
10688 
10689   format %{ "cmovI   $crx, $dst, $src" %}
10690   // Worst case is branch + move + stop, no stop without scheduler.
10691   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10692   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
10693   ins_pipe(pipe_class_default);
10694 %}
10695 
10696 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
10697   // no match-rule, false predicate
10698   effect(DEF dst, USE crx, USE mem);
10699   predicate(false);
10700 
10701   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
10702   postalloc_expand %{
10703     //
10704     // replaces
10705     //
10706     //   region  dst  crx  mem
10707     //    \       |    |   /
10708     //     dst=cmovI_bso_stackSlotL_conLvalue0
10709     //
10710     // with
10711     //
10712     //   region  dst
10713     //    \       /
10714     //     dst=loadConI16(0)
10715     //      |
10716     //      ^  region  dst  crx  mem
10717     //      |   \       |    |    /
10718     //      dst=cmovI_bso_stackSlotL
10719     //
10720 
10721     // Create new nodes.
10722     MachNode *m1 = new loadConI16Node();
10723     MachNode *m2 = new cmovI_bso_stackSlotLNode();
10724 
10725     // inputs for new nodes
10726     m1->add_req(n_region);
10727     m2->add_req(n_region, n_crx, n_mem);
10728 
10729     // precedences for new nodes
10730     m2->add_prec(m1);
10731 
10732     // operands for new nodes
10733     m1->_opnds[0] = op_dst;
10734     m1->_opnds[1] = new immI16Oper(0);
10735 
10736     m2->_opnds[0] = op_dst;
10737     m2->_opnds[1] = op_crx;
10738     m2->_opnds[2] = op_mem;
10739 
10740     // registers for new nodes
10741     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10742     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10743 
10744     // Insert new nodes.
10745     nodes->push(m1);
10746     nodes->push(m2);
10747   %}
10748 %}
10749 
10750 instruct cmovI_bso_reg_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, regD src) %{
10751   // no match-rule, false predicate
10752   effect(DEF dst, USE crx, USE src);
10753   predicate(false);
10754 
10755   format %{ "CmovI   $dst, $crx, $src \t// postalloc expanded" %}
10756   postalloc_expand %{
10757     //
10758     // replaces
10759     //
10760     //   region  dst  crx  src
10761     //    \       |    |   /
10762     //     dst=cmovI_bso_reg_conLvalue0
10763     //
10764     // with
10765     //
10766     //   region  dst
10767     //    \       /
10768     //     dst=loadConI16(0)
10769     //      |
10770     //      ^  region  dst  crx  src
10771     //      |   \       |    |    /
10772     //      dst=cmovI_bso_reg
10773     //
10774 
10775     // Create new nodes.
10776     MachNode *m1 = new loadConI16Node();
10777     MachNode *m2 = new cmovI_bso_regNode();
10778 
10779     // inputs for new nodes
10780     m1->add_req(n_region);
10781     m2->add_req(n_region, n_crx, n_src);
10782 
10783     // precedences for new nodes
10784     m2->add_prec(m1);
10785 
10786     // operands for new nodes
10787     m1->_opnds[0] = op_dst;
10788     m1->_opnds[1] = new immI16Oper(0);
10789 
10790     m2->_opnds[0] = op_dst;
10791     m2->_opnds[1] = op_crx;
10792     m2->_opnds[2] = op_src;
10793 
10794     // registers for new nodes
10795     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10796     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10797 
10798     // Insert new nodes.
10799     nodes->push(m1);
10800     nodes->push(m2);
10801   %}
10802 %}
10803 
10804 // Double to Int conversion, NaN is mapped to 0.
10805 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
10806   match(Set dst (ConvD2I src));
10807   predicate(!VM_Version::has_mtfprd());
10808   ins_cost(DEFAULT_COST);
10809 
10810   expand %{
10811     regD tmpD;
10812     stackSlotL tmpS;
10813     flagsReg crx;
10814     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10815     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10816     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10817     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10818   %}
10819 %}
10820 
10821 // Double to Int conversion, NaN is mapped to 0. Special version for Power8.
10822 instruct convD2I_reg_mffprd_ExEx(iRegIdst dst, regD src) %{
10823   match(Set dst (ConvD2I src));
10824   predicate(VM_Version::has_mtfprd());
10825   ins_cost(DEFAULT_COST);
10826 
10827   expand %{
10828     regD tmpD;
10829     flagsReg crx;
10830     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10831     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10832     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
10833   %}
10834 %}
10835 
10836 instruct convF2IRaw_regF(regF dst, regF src) %{
10837   // no match-rule, false predicate
10838   effect(DEF dst, USE src);
10839   predicate(false);
10840 
10841   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
10842   size(4);
10843   ins_encode %{
10844     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10845     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10846   %}
10847   ins_pipe(pipe_class_default);
10848 %}
10849 
10850 // Float to Int conversion, NaN is mapped to 0.
10851 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
10852   match(Set dst (ConvF2I src));
10853   predicate(!VM_Version::has_mtfprd());
10854   ins_cost(DEFAULT_COST);
10855 
10856   expand %{
10857     regF tmpF;
10858     stackSlotL tmpS;
10859     flagsReg crx;
10860     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10861     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10862     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10863     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10864   %}
10865 %}
10866 
10867 // Float to Int conversion, NaN is mapped to 0. Special version for Power8.
10868 instruct convF2I_regF_mffprd_ExEx(iRegIdst dst, regF src) %{
10869   match(Set dst (ConvF2I src));
10870   predicate(VM_Version::has_mtfprd());
10871   ins_cost(DEFAULT_COST);
10872 
10873   expand %{
10874     regF tmpF;
10875     flagsReg crx;
10876     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10877     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10878     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
10879   %}
10880 %}
10881 
10882 // Convert to Long
10883 
10884 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
10885   match(Set dst (ConvI2L src));
10886   format %{ "EXTSW   $dst, $src \t// int->long" %}
10887   size(4);
10888   ins_encode %{
10889     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
10890     __ extsw($dst$$Register, $src$$Register);
10891   %}
10892   ins_pipe(pipe_class_default);
10893 %}
10894 
10895 // Zero-extend: convert unsigned int to long (convUI2L).
10896 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
10897   match(Set dst (AndL (ConvI2L src) mask));
10898   ins_cost(DEFAULT_COST);
10899 
10900   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
10901   size(4);
10902   ins_encode %{
10903     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
10904     __ clrldi($dst$$Register, $src$$Register, 32);
10905   %}
10906   ins_pipe(pipe_class_default);
10907 %}
10908 
10909 // Zero-extend: convert unsigned int to long in long register.
10910 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{
10911   match(Set dst (AndL src mask));
10912   ins_cost(DEFAULT_COST);
10913 
10914   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
10915   size(4);
10916   ins_encode %{
10917     // TODO: PPC port $archOpcode(ppc64Opcode_rldicl);
10918     __ clrldi($dst$$Register, $src$$Register, 32);
10919   %}
10920   ins_pipe(pipe_class_default);
10921 %}
10922 
10923 instruct convF2LRaw_regF(regF dst, regF src) %{
10924   // no match-rule, false predicate
10925   effect(DEF dst, USE src);
10926   predicate(false);
10927 
10928   format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %}
10929   size(4);
10930   ins_encode %{
10931     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10932     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10933   %}
10934   ins_pipe(pipe_class_default);
10935 %}
10936 
10937 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
10938   // no match-rule, false predicate
10939   effect(DEF dst, USE crx, USE src);
10940   predicate(false);
10941 
10942   ins_variable_size_depending_on_alignment(true);
10943 
10944   format %{ "cmovL   $crx, $dst, $src" %}
10945   // Worst case is branch + move + stop, no stop without scheduler.
10946   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10947   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10948   ins_pipe(pipe_class_default);
10949 %}
10950 
10951 instruct cmovL_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
10952   // no match-rule, false predicate
10953   effect(DEF dst, USE crx, USE src);
10954   predicate(false);
10955 
10956   ins_variable_size_depending_on_alignment(true);
10957 
10958   format %{ "cmovL   $crx, $dst, $src" %}
10959   // Worst case is branch + move + stop, no stop without scheduler.
10960   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10961   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
10962   ins_pipe(pipe_class_default);
10963 %}
10964 
10965 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
10966   // no match-rule, false predicate
10967   effect(DEF dst, USE crx, USE mem);
10968   predicate(false);
10969 
10970   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
10971   postalloc_expand %{
10972     //
10973     // replaces
10974     //
10975     //   region  dst  crx  mem
10976     //    \       |    |   /
10977     //     dst=cmovL_bso_stackSlotL_conLvalue0
10978     //
10979     // with
10980     //
10981     //   region  dst
10982     //    \       /
10983     //     dst=loadConL16(0)
10984     //      |
10985     //      ^  region  dst  crx  mem
10986     //      |   \       |    |    /
10987     //      dst=cmovL_bso_stackSlotL
10988     //
10989 
10990     // Create new nodes.
10991     MachNode *m1 = new loadConL16Node();
10992     MachNode *m2 = new cmovL_bso_stackSlotLNode();
10993 
10994     // inputs for new nodes
10995     m1->add_req(n_region);
10996     m2->add_req(n_region, n_crx, n_mem);
10997     m2->add_prec(m1);
10998 
10999     // operands for new nodes
11000     m1->_opnds[0] = op_dst;
11001     m1->_opnds[1] = new immL16Oper(0);
11002     m2->_opnds[0] = op_dst;
11003     m2->_opnds[1] = op_crx;
11004     m2->_opnds[2] = op_mem;
11005 
11006     // registers for new nodes
11007     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11008     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11009 
11010     // Insert new nodes.
11011     nodes->push(m1);
11012     nodes->push(m2);
11013   %}
11014 %}
11015 
11016 instruct cmovL_bso_reg_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, regD src) %{
11017   // no match-rule, false predicate
11018   effect(DEF dst, USE crx, USE src);
11019   predicate(false);
11020 
11021   format %{ "CmovL   $dst, $crx, $src \t// postalloc expanded" %}
11022   postalloc_expand %{
11023     //
11024     // replaces
11025     //
11026     //   region  dst  crx  src
11027     //    \       |    |   /
11028     //     dst=cmovL_bso_reg_conLvalue0
11029     //
11030     // with
11031     //
11032     //   region  dst
11033     //    \       /
11034     //     dst=loadConL16(0)
11035     //      |
11036     //      ^  region  dst  crx  src
11037     //      |   \       |    |    /
11038     //      dst=cmovL_bso_reg
11039     //
11040 
11041     // Create new nodes.
11042     MachNode *m1 = new loadConL16Node();
11043     MachNode *m2 = new cmovL_bso_regNode();
11044 
11045     // inputs for new nodes
11046     m1->add_req(n_region);
11047     m2->add_req(n_region, n_crx, n_src);
11048     m2->add_prec(m1);
11049 
11050     // operands for new nodes
11051     m1->_opnds[0] = op_dst;
11052     m1->_opnds[1] = new immL16Oper(0);
11053     m2->_opnds[0] = op_dst;
11054     m2->_opnds[1] = op_crx;
11055     m2->_opnds[2] = op_src;
11056 
11057     // registers for new nodes
11058     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11059     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11060 
11061     // Insert new nodes.
11062     nodes->push(m1);
11063     nodes->push(m2);
11064   %}
11065 %}
11066 
11067 // Float to Long conversion, NaN is mapped to 0.
11068 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
11069   match(Set dst (ConvF2L src));
11070   predicate(!VM_Version::has_mtfprd());
11071   ins_cost(DEFAULT_COST);
11072 
11073   expand %{
11074     regF tmpF;
11075     stackSlotL tmpS;
11076     flagsReg crx;
11077     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11078     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11079     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
11080     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11081   %}
11082 %}
11083 
11084 // Float to Long conversion, NaN is mapped to 0. Special version for Power8.
11085 instruct convF2L_reg_mffprd_ExEx(iRegLdst dst, regF src) %{
11086   match(Set dst (ConvF2L src));
11087   predicate(VM_Version::has_mtfprd());
11088   ins_cost(DEFAULT_COST);
11089 
11090   expand %{
11091     regF tmpF;
11092     flagsReg crx;
11093     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11094     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11095     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
11096   %}
11097 %}
11098 
11099 instruct convD2LRaw_regD(regD dst, regD src) %{
11100   // no match-rule, false predicate
11101   effect(DEF dst, USE src);
11102   predicate(false);
11103 
11104   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
11105   size(4);
11106   ins_encode %{
11107     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
11108     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
11109   %}
11110   ins_pipe(pipe_class_default);
11111 %}
11112 
11113 // Double to Long conversion, NaN is mapped to 0.
11114 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
11115   match(Set dst (ConvD2L src));
11116   predicate(!VM_Version::has_mtfprd());
11117   ins_cost(DEFAULT_COST);
11118 
11119   expand %{
11120     regD tmpD;
11121     stackSlotL tmpS;
11122     flagsReg crx;
11123     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11124     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11125     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
11126     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11127   %}
11128 %}
11129 
11130 // Double to Long conversion, NaN is mapped to 0. Special version for Power8.
11131 instruct convD2L_reg_mffprd_ExEx(iRegLdst dst, regD src) %{
11132   match(Set dst (ConvD2L src));
11133   predicate(VM_Version::has_mtfprd());
11134   ins_cost(DEFAULT_COST);
11135 
11136   expand %{
11137     regD tmpD;
11138     flagsReg crx;
11139     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11140     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11141     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
11142   %}
11143 %}
11144 
11145 // Convert to Float
11146 
11147 // Placed here as needed in expand.
11148 instruct convL2DRaw_regD(regD dst, regD src) %{
11149   // no match-rule, false predicate
11150   effect(DEF dst, USE src);
11151   predicate(false);
11152 
11153   format %{ "FCFID $dst, $src \t// convL2D" %}
11154   size(4);
11155   ins_encode %{
11156     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11157     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
11158   %}
11159   ins_pipe(pipe_class_default);
11160 %}
11161 
11162 // Placed here as needed in expand.
11163 instruct convD2F_reg(regF dst, regD src) %{
11164   match(Set dst (ConvD2F src));
11165   format %{ "FRSP    $dst, $src \t// convD2F" %}
11166   size(4);
11167   ins_encode %{
11168     // TODO: PPC port $archOpcode(ppc64Opcode_frsp);
11169     __ frsp($dst$$FloatRegister, $src$$FloatRegister);
11170   %}
11171   ins_pipe(pipe_class_default);
11172 %}
11173 
11174 // Integer to Float conversion.
11175 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{
11176   match(Set dst (ConvI2F src));
11177   predicate(!VM_Version::has_fcfids());
11178   ins_cost(DEFAULT_COST);
11179 
11180   expand %{
11181     iRegLdst tmpL;
11182     stackSlotL tmpS;
11183     regD tmpD;
11184     regD tmpD2;
11185     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11186     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11187     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11188     convL2DRaw_regD(tmpD2, tmpD);        // Convert to double.
11189     convD2F_reg(dst, tmpD2);             // Convert double to float.
11190   %}
11191 %}
11192 
11193 instruct convL2FRaw_regF(regF dst, regD src) %{
11194   // no match-rule, false predicate
11195   effect(DEF dst, USE src);
11196   predicate(false);
11197 
11198   format %{ "FCFIDS $dst, $src \t// convL2F" %}
11199   size(4);
11200   ins_encode %{
11201     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11202     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
11203   %}
11204   ins_pipe(pipe_class_default);
11205 %}
11206 
11207 // Integer to Float conversion. Special version for Power7.
11208 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
11209   match(Set dst (ConvI2F src));
11210   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11211   ins_cost(DEFAULT_COST);
11212 
11213   expand %{
11214     iRegLdst tmpL;
11215     stackSlotL tmpS;
11216     regD tmpD;
11217     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11218     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11219     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11220     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11221   %}
11222 %}
11223 
11224 // Integer to Float conversion. Special version for Power8.
11225 instruct convI2F_ireg_mtfprd_Ex(regF dst, iRegIsrc src) %{
11226   match(Set dst (ConvI2F src));
11227   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11228   ins_cost(DEFAULT_COST);
11229 
11230   expand %{
11231     regD tmpD;
11232     moveI2D_reg(tmpD, src);
11233     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11234   %}
11235 %}
11236 
11237 // L2F to avoid runtime call.
11238 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
11239   match(Set dst (ConvL2F src));
11240   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11241   ins_cost(DEFAULT_COST);
11242 
11243   expand %{
11244     stackSlotL tmpS;
11245     regD tmpD;
11246     regL_to_stkL(tmpS, src);             // Store long to stack.
11247     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11248     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11249   %}
11250 %}
11251 
11252 // L2F to avoid runtime call.  Special version for Power8.
11253 instruct convL2F_ireg_mtfprd_Ex(regF dst, iRegLsrc src) %{
11254   match(Set dst (ConvL2F src));
11255   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11256   ins_cost(DEFAULT_COST);
11257 
11258   expand %{
11259     regD tmpD;
11260     moveL2D_reg(tmpD, src);
11261     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11262   %}
11263 %}
11264 
11265 // Moved up as used in expand.
11266 //instruct convD2F_reg(regF dst, regD src) %{%}
11267 
11268 // Convert to Double
11269 
11270 // Integer to Double conversion.
11271 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
11272   match(Set dst (ConvI2D src));
11273   predicate(!VM_Version::has_mtfprd());
11274   ins_cost(DEFAULT_COST);
11275 
11276   expand %{
11277     iRegLdst tmpL;
11278     stackSlotL tmpS;
11279     regD tmpD;
11280     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11281     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11282     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11283     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11284   %}
11285 %}
11286 
11287 // Integer to Double conversion. Special version for Power8.
11288 instruct convI2D_reg_mtfprd_Ex(regD dst, iRegIsrc src) %{
11289   match(Set dst (ConvI2D src));
11290   predicate(VM_Version::has_mtfprd());
11291   ins_cost(DEFAULT_COST);
11292 
11293   expand %{
11294     regD tmpD;
11295     moveI2D_reg(tmpD, src);
11296     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11297   %}
11298 %}
11299 
11300 // Long to Double conversion
11301 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
11302   match(Set dst (ConvL2D src));
11303   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
11304 
11305   expand %{
11306     regD tmpD;
11307     moveL2D_stack_reg(tmpD, src);
11308     convL2DRaw_regD(dst, tmpD);
11309   %}
11310 %}
11311 
11312 // Long to Double conversion. Special version for Power8.
11313 instruct convL2D_reg_mtfprd_Ex(regD dst, iRegLsrc src) %{
11314   match(Set dst (ConvL2D src));
11315   predicate(VM_Version::has_mtfprd());
11316   ins_cost(DEFAULT_COST);
11317 
11318   expand %{
11319     regD tmpD;
11320     moveL2D_reg(tmpD, src);
11321     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11322   %}
11323 %}
11324 
11325 instruct convF2D_reg(regD dst, regF src) %{
11326   match(Set dst (ConvF2D src));
11327   format %{ "FMR     $dst, $src \t// float->double" %}
11328   // variable size, 0 or 4
11329   ins_encode %{
11330     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11331     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
11332   %}
11333   ins_pipe(pipe_class_default);
11334 %}
11335 
11336 //----------Control Flow Instructions------------------------------------------
11337 // Compare Instructions
11338 
11339 // Compare Integers
11340 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
11341   match(Set crx (CmpI src1 src2));
11342   size(4);
11343   format %{ "CMPW    $crx, $src1, $src2" %}
11344   ins_encode %{
11345     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
11346     __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register);
11347   %}
11348   ins_pipe(pipe_class_compare);
11349 %}
11350 
11351 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{
11352   match(Set crx (CmpI src1 src2));
11353   format %{ "CMPWI   $crx, $src1, $src2" %}
11354   size(4);
11355   ins_encode %{
11356     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
11357     __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11358   %}
11359   ins_pipe(pipe_class_compare);
11360 %}
11361 
11362 // (src1 & src2) == 0?
11363 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{
11364   match(Set cr0 (CmpI (AndI src1 src2) zero));
11365   // r0 is killed
11366   format %{ "ANDI    R0, $src1, $src2 \t// BTST int" %}
11367   size(4);
11368   ins_encode %{
11369     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
11370     __ andi_(R0, $src1$$Register, $src2$$constant);
11371   %}
11372   ins_pipe(pipe_class_compare);
11373 %}
11374 
11375 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{
11376   match(Set crx (CmpL src1 src2));
11377   format %{ "CMPD    $crx, $src1, $src2" %}
11378   size(4);
11379   ins_encode %{
11380     // TODO: PPC port $archOpcode(ppc64Opcode_cmp);
11381     __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register);
11382   %}
11383   ins_pipe(pipe_class_compare);
11384 %}
11385 
11386 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{
11387   match(Set crx (CmpL src1 src2));
11388   format %{ "CMPDI   $crx, $src1, $src2" %}
11389   size(4);
11390   ins_encode %{
11391     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
11392     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11393   %}
11394   ins_pipe(pipe_class_compare);
11395 %}
11396 
11397 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{
11398   match(Set cr0 (CmpL (AndL src1 src2) zero));
11399   // r0 is killed
11400   format %{ "AND     R0, $src1, $src2 \t// BTST long" %}
11401   size(4);
11402   ins_encode %{
11403     // TODO: PPC port $archOpcode(ppc64Opcode_and_);
11404     __ and_(R0, $src1$$Register, $src2$$Register);
11405   %}
11406   ins_pipe(pipe_class_compare);
11407 %}
11408 
11409 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{
11410   match(Set cr0 (CmpL (AndL src1 src2) zero));
11411   // r0 is killed
11412   format %{ "ANDI    R0, $src1, $src2 \t// BTST long" %}
11413   size(4);
11414   ins_encode %{
11415     // TODO: PPC port $archOpcode(ppc64Opcode_andi_);
11416     __ andi_(R0, $src1$$Register, $src2$$constant);
11417   %}
11418   ins_pipe(pipe_class_compare);
11419 %}
11420 
11421 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{
11422   // no match-rule, false predicate
11423   effect(DEF dst, USE crx);
11424   predicate(false);
11425 
11426   ins_variable_size_depending_on_alignment(true);
11427 
11428   format %{ "cmovI   $crx, $dst, -1, 0, +1" %}
11429   // Worst case is branch + move + branch + move + stop, no stop without scheduler.
11430   size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16);
11431   ins_encode %{
11432     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
11433     Label done;
11434     // li(Rdst, 0);              // equal -> 0
11435     __ beq($crx$$CondRegister, done);
11436     __ li($dst$$Register, 1);    // greater -> +1
11437     __ bgt($crx$$CondRegister, done);
11438     __ li($dst$$Register, -1);   // unordered or less -> -1
11439     // TODO: PPC port__ endgroup_if_needed(_size == 20);
11440     __ bind(done);
11441   %}
11442   ins_pipe(pipe_class_compare);
11443 %}
11444 
11445 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{
11446   // no match-rule, false predicate
11447   effect(DEF dst, USE crx);
11448   predicate(false);
11449 
11450   format %{ "CmovI    $crx, $dst, -1, 0, +1 \t// postalloc expanded" %}
11451   postalloc_expand %{
11452     //
11453     // replaces
11454     //
11455     //   region  crx
11456     //    \       |
11457     //     dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1
11458     //
11459     // with
11460     //
11461     //   region
11462     //    \
11463     //     dst=loadConI16(0)
11464     //      |
11465     //      ^  region  crx
11466     //      |   \       |
11467     //      dst=cmovI_conIvalueMinus1_conIvalue1
11468     //
11469 
11470     // Create new nodes.
11471     MachNode *m1 = new loadConI16Node();
11472     MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node();
11473 
11474     // inputs for new nodes
11475     m1->add_req(n_region);
11476     m2->add_req(n_region, n_crx);
11477     m2->add_prec(m1);
11478 
11479     // operands for new nodes
11480     m1->_opnds[0] = op_dst;
11481     m1->_opnds[1] = new immI16Oper(0);
11482     m2->_opnds[0] = op_dst;
11483     m2->_opnds[1] = op_crx;
11484 
11485     // registers for new nodes
11486     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11487     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11488 
11489     // Insert new nodes.
11490     nodes->push(m1);
11491     nodes->push(m2);
11492   %}
11493 %}
11494 
11495 // Manifest a CmpL3 result in an integer register. Very painful.
11496 // This is the test to avoid.
11497 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0)
11498 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{
11499   match(Set dst (CmpL3 src1 src2));
11500   ins_cost(DEFAULT_COST*5+BRANCH_COST);
11501 
11502   expand %{
11503     flagsReg tmp1;
11504     cmpL_reg_reg(tmp1, src1, src2);
11505     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
11506   %}
11507 %}
11508 
11509 // Implicit range checks.
11510 // A range check in the ideal world has one of the following shapes:
11511 //  - (If le (CmpU length index)), (IfTrue  throw exception)
11512 //  - (If lt (CmpU index length)), (IfFalse throw exception)
11513 //
11514 // Match range check 'If le (CmpU length index)'.
11515 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{
11516   match(If cmp (CmpU src_length index));
11517   effect(USE labl);
11518   predicate(TrapBasedRangeChecks &&
11519             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
11520             PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS &&
11521             (Matcher::branches_to_uncommon_trap(_leaf)));
11522 
11523   ins_is_TrapBasedCheckNode(true);
11524 
11525   format %{ "TWI     $index $cmp $src_length \t// RangeCheck => trap $labl" %}
11526   size(4);
11527   ins_encode %{
11528     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
11529     if ($cmp$$cmpcode == 0x1 /* less_equal */) {
11530       __ trap_range_check_le($src_length$$Register, $index$$constant);
11531     } else {
11532       // Both successors are uncommon traps, probability is 0.
11533       // Node got flipped during fixup flow.
11534       assert($cmp$$cmpcode == 0x9, "must be greater");
11535       __ trap_range_check_g($src_length$$Register, $index$$constant);
11536     }
11537   %}
11538   ins_pipe(pipe_class_trap);
11539 %}
11540 
11541 // Match range check 'If lt (CmpU index length)'.
11542 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{
11543   match(If cmp (CmpU src_index src_length));
11544   effect(USE labl);
11545   predicate(TrapBasedRangeChecks &&
11546             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
11547             _leaf->as_If()->_prob >= PROB_ALWAYS &&
11548             (Matcher::branches_to_uncommon_trap(_leaf)));
11549 
11550   ins_is_TrapBasedCheckNode(true);
11551 
11552   format %{ "TW      $src_index $cmp $src_length \t// RangeCheck => trap $labl" %}
11553   size(4);
11554   ins_encode %{
11555     // TODO: PPC port $archOpcode(ppc64Opcode_tw);
11556     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
11557       __ trap_range_check_ge($src_index$$Register, $src_length$$Register);
11558     } else {
11559       // Both successors are uncommon traps, probability is 0.
11560       // Node got flipped during fixup flow.
11561       assert($cmp$$cmpcode == 0x8, "must be less");
11562       __ trap_range_check_l($src_index$$Register, $src_length$$Register);
11563     }
11564   %}
11565   ins_pipe(pipe_class_trap);
11566 %}
11567 
11568 // Match range check 'If lt (CmpU index length)'.
11569 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{
11570   match(If cmp (CmpU src_index length));
11571   effect(USE labl);
11572   predicate(TrapBasedRangeChecks &&
11573             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
11574             _leaf->as_If()->_prob >= PROB_ALWAYS &&
11575             (Matcher::branches_to_uncommon_trap(_leaf)));
11576 
11577   ins_is_TrapBasedCheckNode(true);
11578 
11579   format %{ "TWI     $src_index $cmp $length \t// RangeCheck => trap $labl" %}
11580   size(4);
11581   ins_encode %{
11582     // TODO: PPC port $archOpcode(ppc64Opcode_twi);
11583     if ($cmp$$cmpcode == 0x0 /* greater_equal */) {
11584       __ trap_range_check_ge($src_index$$Register, $length$$constant);
11585     } else {
11586       // Both successors are uncommon traps, probability is 0.
11587       // Node got flipped during fixup flow.
11588       assert($cmp$$cmpcode == 0x8, "must be less");
11589       __ trap_range_check_l($src_index$$Register, $length$$constant);
11590     }
11591   %}
11592   ins_pipe(pipe_class_trap);
11593 %}
11594 
11595 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
11596   match(Set crx (CmpU src1 src2));
11597   format %{ "CMPLW   $crx, $src1, $src2 \t// unsigned" %}
11598   size(4);
11599   ins_encode %{
11600     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11601     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
11602   %}
11603   ins_pipe(pipe_class_compare);
11604 %}
11605 
11606 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{
11607   match(Set crx (CmpU src1 src2));
11608   size(4);
11609   format %{ "CMPLWI  $crx, $src1, $src2" %}
11610   ins_encode %{
11611     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
11612     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11613   %}
11614   ins_pipe(pipe_class_compare);
11615 %}
11616 
11617 // Implicit zero checks (more implicit null checks).
11618 // No constant pool entries required.
11619 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{
11620   match(If cmp (CmpN value zero));
11621   effect(USE labl);
11622   predicate(TrapBasedNullChecks &&
11623             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
11624             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
11625             Matcher::branches_to_uncommon_trap(_leaf));
11626   ins_cost(1);
11627 
11628   ins_is_TrapBasedCheckNode(true);
11629 
11630   format %{ "TDI     $value $cmp $zero \t// ZeroCheckN => trap $labl" %}
11631   size(4);
11632   ins_encode %{
11633     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11634     if ($cmp$$cmpcode == 0xA) {
11635       __ trap_null_check($value$$Register);
11636     } else {
11637       // Both successors are uncommon traps, probability is 0.
11638       // Node got flipped during fixup flow.
11639       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
11640       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
11641     }
11642   %}
11643   ins_pipe(pipe_class_trap);
11644 %}
11645 
11646 // Compare narrow oops.
11647 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{
11648   match(Set crx (CmpN src1 src2));
11649 
11650   size(4);
11651   ins_cost(2);
11652   format %{ "CMPLW   $crx, $src1, $src2 \t// compressed ptr" %}
11653   ins_encode %{
11654     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11655     __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register);
11656   %}
11657   ins_pipe(pipe_class_compare);
11658 %}
11659 
11660 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{
11661   match(Set crx (CmpN src1 src2));
11662   // Make this more expensive than zeroCheckN_iReg_imm0.
11663   ins_cost(2);
11664 
11665   format %{ "CMPLWI  $crx, $src1, $src2 \t// compressed ptr" %}
11666   size(4);
11667   ins_encode %{
11668     // TODO: PPC port $archOpcode(ppc64Opcode_cmpli);
11669     __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11670   %}
11671   ins_pipe(pipe_class_compare);
11672 %}
11673 
11674 // Implicit zero checks (more implicit null checks).
11675 // No constant pool entries required.
11676 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{
11677   match(If cmp (CmpP value zero));
11678   effect(USE labl);
11679   predicate(TrapBasedNullChecks &&
11680             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
11681             _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) &&
11682             Matcher::branches_to_uncommon_trap(_leaf));
11683   ins_cost(1); // Should not be cheaper than zeroCheckN.
11684 
11685   ins_is_TrapBasedCheckNode(true);
11686 
11687   format %{ "TDI     $value $cmp $zero \t// ZeroCheckP => trap $labl" %}
11688   size(4);
11689   ins_encode %{
11690     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
11691     if ($cmp$$cmpcode == 0xA) {
11692       __ trap_null_check($value$$Register);
11693     } else {
11694       // Both successors are uncommon traps, probability is 0.
11695       // Node got flipped during fixup flow.
11696       assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)");
11697       __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned);
11698     }
11699   %}
11700   ins_pipe(pipe_class_trap);
11701 %}
11702 
11703 // Compare Pointers
11704 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{
11705   match(Set crx (CmpP src1 src2));
11706   format %{ "CMPLD   $crx, $src1, $src2 \t// ptr" %}
11707   size(4);
11708   ins_encode %{
11709     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11710     __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register);
11711   %}
11712   ins_pipe(pipe_class_compare);
11713 %}
11714 
11715 instruct cmpP_reg_null(flagsReg crx, iRegP_N2P src1, immP_0or1 src2) %{
11716   match(Set crx (CmpP src1 src2));
11717   format %{ "CMPLDI   $crx, $src1, $src2 \t// ptr" %}
11718   size(4);
11719   ins_encode %{
11720     // TODO: PPC port $archOpcode(ppc64Opcode_cmpl);
11721     __ cmpldi($crx$$CondRegister, $src1$$Register, (int)((short)($src2$$constant & 0xFFFF)));
11722   %}
11723   ins_pipe(pipe_class_compare);
11724 %}
11725 
11726 // Used in postalloc expand.
11727 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{
11728   // This match rule prevents reordering of node before a safepoint.
11729   // This only makes sense if this instructions is used exclusively
11730   // for the expansion of EncodeP!
11731   match(Set crx (CmpP src1 src2));
11732   predicate(false);
11733 
11734   format %{ "CMPDI   $crx, $src1, $src2" %}
11735   size(4);
11736   ins_encode %{
11737     // TODO: PPC port $archOpcode(ppc64Opcode_cmpi);
11738     __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant);
11739   %}
11740   ins_pipe(pipe_class_compare);
11741 %}
11742 
11743 //----------Float Compares----------------------------------------------------
11744 
11745 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{
11746   // Needs matchrule, see cmpDUnordered.
11747   match(Set crx (CmpF src1 src2));
11748   // no match-rule, false predicate
11749   predicate(false);
11750 
11751   format %{ "cmpFUrd $crx, $src1, $src2" %}
11752   size(4);
11753   ins_encode %{
11754     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
11755     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
11756   %}
11757   ins_pipe(pipe_class_default);
11758 %}
11759 
11760 instruct cmov_bns_less(flagsReg crx) %{
11761   // no match-rule, false predicate
11762   effect(DEF crx);
11763   predicate(false);
11764 
11765   ins_variable_size_depending_on_alignment(true);
11766 
11767   format %{ "cmov    $crx" %}
11768   // Worst case is branch + move + stop, no stop without scheduler.
11769   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12);
11770   ins_encode %{
11771     // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr);
11772     Label done;
11773     __ bns($crx$$CondRegister, done);        // not unordered -> keep crx
11774     __ li(R0, 0);
11775     __ cmpwi($crx$$CondRegister, R0, 1);     // unordered -> set crx to 'less'
11776     // TODO PPC port __ endgroup_if_needed(_size == 16);
11777     __ bind(done);
11778   %}
11779   ins_pipe(pipe_class_default);
11780 %}
11781 
11782 // Compare floating, generate condition code.
11783 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{
11784   // FIXME: should we match 'If cmp (CmpF src1 src2))' ??
11785   //
11786   // The following code sequence occurs a lot in mpegaudio:
11787   //
11788   // block BXX:
11789   // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0):
11790   //    cmpFUrd CCR6, F11, F9
11791   // 4: instruct cmov_bns_less (cmpF_reg_reg-1):
11792   //    cmov CCR6
11793   // 8: instruct branchConSched:
11794   //    B_FARle CCR6, B56  P=0.500000 C=-1.000000
11795   match(Set crx (CmpF src1 src2));
11796   ins_cost(DEFAULT_COST+BRANCH_COST);
11797 
11798   format %{ "CmpF    $crx, $src1, $src2 \t// postalloc expanded" %}
11799   postalloc_expand %{
11800     //
11801     // replaces
11802     //
11803     //   region  src1  src2
11804     //    \       |     |
11805     //     crx=cmpF_reg_reg
11806     //
11807     // with
11808     //
11809     //   region  src1  src2
11810     //    \       |     |
11811     //     crx=cmpFUnordered_reg_reg
11812     //      |
11813     //      ^  region
11814     //      |   \
11815     //      crx=cmov_bns_less
11816     //
11817 
11818     // Create new nodes.
11819     MachNode *m1 = new cmpFUnordered_reg_regNode();
11820     MachNode *m2 = new cmov_bns_lessNode();
11821 
11822     // inputs for new nodes
11823     m1->add_req(n_region, n_src1, n_src2);
11824     m2->add_req(n_region);
11825     m2->add_prec(m1);
11826 
11827     // operands for new nodes
11828     m1->_opnds[0] = op_crx;
11829     m1->_opnds[1] = op_src1;
11830     m1->_opnds[2] = op_src2;
11831     m2->_opnds[0] = op_crx;
11832 
11833     // registers for new nodes
11834     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
11835     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
11836 
11837     // Insert new nodes.
11838     nodes->push(m1);
11839     nodes->push(m2);
11840   %}
11841 %}
11842 
11843 // Compare float, generate -1,0,1
11844 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{
11845   match(Set dst (CmpF3 src1 src2));
11846   ins_cost(DEFAULT_COST*5+BRANCH_COST);
11847 
11848   expand %{
11849     flagsReg tmp1;
11850     cmpFUnordered_reg_reg(tmp1, src1, src2);
11851     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
11852   %}
11853 %}
11854 
11855 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{
11856   // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the
11857   // node right before the conditional move using it.
11858   // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7,
11859   // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle
11860   // crashed in register allocation where the flags Reg between cmpDUnoredered and a
11861   // conditional move was supposed to be spilled.
11862   match(Set crx (CmpD src1 src2));
11863   // False predicate, shall not be matched.
11864   predicate(false);
11865 
11866   format %{ "cmpFUrd $crx, $src1, $src2" %}
11867   size(4);
11868   ins_encode %{
11869     // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu);
11870     __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister);
11871   %}
11872   ins_pipe(pipe_class_default);
11873 %}
11874 
11875 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{
11876   match(Set crx (CmpD src1 src2));
11877   ins_cost(DEFAULT_COST+BRANCH_COST);
11878 
11879   format %{ "CmpD    $crx, $src1, $src2 \t// postalloc expanded" %}
11880   postalloc_expand %{
11881     //
11882     // replaces
11883     //
11884     //   region  src1  src2
11885     //    \       |     |
11886     //     crx=cmpD_reg_reg
11887     //
11888     // with
11889     //
11890     //   region  src1  src2
11891     //    \       |     |
11892     //     crx=cmpDUnordered_reg_reg
11893     //      |
11894     //      ^  region
11895     //      |   \
11896     //      crx=cmov_bns_less
11897     //
11898 
11899     // create new nodes
11900     MachNode *m1 = new cmpDUnordered_reg_regNode();
11901     MachNode *m2 = new cmov_bns_lessNode();
11902 
11903     // inputs for new nodes
11904     m1->add_req(n_region, n_src1, n_src2);
11905     m2->add_req(n_region);
11906     m2->add_prec(m1);
11907 
11908     // operands for new nodes
11909     m1->_opnds[0] = op_crx;
11910     m1->_opnds[1] = op_src1;
11911     m1->_opnds[2] = op_src2;
11912     m2->_opnds[0] = op_crx;
11913 
11914     // registers for new nodes
11915     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
11916     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx
11917 
11918     // Insert new nodes.
11919     nodes->push(m1);
11920     nodes->push(m2);
11921   %}
11922 %}
11923 
11924 // Compare double, generate -1,0,1
11925 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{
11926   match(Set dst (CmpD3 src1 src2));
11927   ins_cost(DEFAULT_COST*5+BRANCH_COST);
11928 
11929   expand %{
11930     flagsReg tmp1;
11931     cmpDUnordered_reg_reg(tmp1, src1, src2);
11932     cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1);
11933   %}
11934 %}
11935 
11936 //----------Branches---------------------------------------------------------
11937 // Jump
11938 
11939 // Direct Branch.
11940 instruct branch(label labl) %{
11941   match(Goto);
11942   effect(USE labl);
11943   ins_cost(BRANCH_COST);
11944 
11945   format %{ "B       $labl" %}
11946   size(4);
11947   ins_encode %{
11948     // TODO: PPC port $archOpcode(ppc64Opcode_b);
11949      Label d;    // dummy
11950      __ bind(d);
11951      Label* p = $labl$$label;
11952      // `p' is `NULL' when this encoding class is used only to
11953      // determine the size of the encoded instruction.
11954      Label& l = (NULL == p)? d : *(p);
11955      __ b(l);
11956   %}
11957   ins_pipe(pipe_class_default);
11958 %}
11959 
11960 // Conditional Near Branch
11961 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{
11962   // Same match rule as `branchConFar'.
11963   match(If cmp crx);
11964   effect(USE lbl);
11965   ins_cost(BRANCH_COST);
11966 
11967   // If set to 1 this indicates that the current instruction is a
11968   // short variant of a long branch. This avoids using this
11969   // instruction in first-pass matching. It will then only be used in
11970   // the `Shorten_branches' pass.
11971   ins_short_branch(1);
11972 
11973   format %{ "B$cmp     $crx, $lbl" %}
11974   size(4);
11975   ins_encode( enc_bc(crx, cmp, lbl) );
11976   ins_pipe(pipe_class_default);
11977 %}
11978 
11979 // This is for cases when the ppc64 `bc' instruction does not
11980 // reach far enough. So we emit a far branch here, which is more
11981 // expensive.
11982 //
11983 // Conditional Far Branch
11984 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{
11985   // Same match rule as `branchCon'.
11986   match(If cmp crx);
11987   effect(USE crx, USE lbl);
11988   predicate(!false /* TODO: PPC port HB_Schedule*/);
11989   // Higher cost than `branchCon'.
11990   ins_cost(5*BRANCH_COST);
11991 
11992   // This is not a short variant of a branch, but the long variant.
11993   ins_short_branch(0);
11994 
11995   format %{ "B_FAR$cmp $crx, $lbl" %}
11996   size(8);
11997   ins_encode( enc_bc_far(crx, cmp, lbl) );
11998   ins_pipe(pipe_class_default);
11999 %}
12000 
12001 // Conditional Branch used with Power6 scheduler (can be far or short).
12002 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{
12003   // Same match rule as `branchCon'.
12004   match(If cmp crx);
12005   effect(USE crx, USE lbl);
12006   predicate(false /* TODO: PPC port HB_Schedule*/);
12007   // Higher cost than `branchCon'.
12008   ins_cost(5*BRANCH_COST);
12009 
12010   // Actually size doesn't depend on alignment but on shortening.
12011   ins_variable_size_depending_on_alignment(true);
12012   // long variant.
12013   ins_short_branch(0);
12014 
12015   format %{ "B_FAR$cmp $crx, $lbl" %}
12016   size(8); // worst case
12017   ins_encode( enc_bc_short_far(crx, cmp, lbl) );
12018   ins_pipe(pipe_class_default);
12019 %}
12020 
12021 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{
12022   match(CountedLoopEnd cmp crx);
12023   effect(USE labl);
12024   ins_cost(BRANCH_COST);
12025 
12026   // short variant.
12027   ins_short_branch(1);
12028 
12029   format %{ "B$cmp     $crx, $labl \t// counted loop end" %}
12030   size(4);
12031   ins_encode( enc_bc(crx, cmp, labl) );
12032   ins_pipe(pipe_class_default);
12033 %}
12034 
12035 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{
12036   match(CountedLoopEnd cmp crx);
12037   effect(USE labl);
12038   predicate(!false /* TODO: PPC port HB_Schedule */);
12039   ins_cost(BRANCH_COST);
12040 
12041   // Long variant.
12042   ins_short_branch(0);
12043 
12044   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
12045   size(8);
12046   ins_encode( enc_bc_far(crx, cmp, labl) );
12047   ins_pipe(pipe_class_default);
12048 %}
12049 
12050 // Conditional Branch used with Power6 scheduler (can be far or short).
12051 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{
12052   match(CountedLoopEnd cmp crx);
12053   effect(USE labl);
12054   predicate(false /* TODO: PPC port HB_Schedule */);
12055   // Higher cost than `branchCon'.
12056   ins_cost(5*BRANCH_COST);
12057 
12058   // Actually size doesn't depend on alignment but on shortening.
12059   ins_variable_size_depending_on_alignment(true);
12060   // Long variant.
12061   ins_short_branch(0);
12062 
12063   format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %}
12064   size(8); // worst case
12065   ins_encode( enc_bc_short_far(crx, cmp, labl) );
12066   ins_pipe(pipe_class_default);
12067 %}
12068 
12069 // ============================================================================
12070 // Java runtime operations, intrinsics and other complex operations.
12071 
12072 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
12073 // array for an instance of the superklass. Set a hidden internal cache on a
12074 // hit (cache is checked with exposed code in gen_subtype_check()). Return
12075 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
12076 //
12077 // GL TODO: Improve this.
12078 // - result should not be a TEMP
12079 // - Add match rule as on sparc avoiding additional Cmp.
12080 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass,
12081                              iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{
12082   match(Set result (PartialSubtypeCheck subklass superklass));
12083   effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr);
12084   ins_cost(DEFAULT_COST*10);
12085 
12086   format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %}
12087   ins_encode %{
12088     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12089     __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register,
12090                                      $tmp_klass$$Register, NULL, $result$$Register);
12091   %}
12092   ins_pipe(pipe_class_default);
12093 %}
12094 
12095 // inlined locking and unlocking
12096 
12097 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{
12098   match(Set crx (FastLock oop box));
12099   effect(TEMP tmp1, TEMP tmp2);
12100   predicate(!Compile::current()->use_rtm());
12101 
12102   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2" %}
12103   ins_encode %{
12104     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12105     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12106                                  $tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0,
12107                                  UseBiasedLocking && !UseOptoBiasInlining);
12108     // If locking was successfull, crx should indicate 'EQ'.
12109     // The compiler generates a branch to the runtime call to
12110     // _complete_monitor_locking_Java for the case where crx is 'NE'.
12111   %}
12112   ins_pipe(pipe_class_compare);
12113 %}
12114 
12115 // Separate version for TM. Use bound register for box to enable USE_KILL.
12116 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12117   match(Set crx (FastLock oop box));
12118   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box);
12119   predicate(Compile::current()->use_rtm());
12120 
12121   format %{ "FASTLOCK  $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %}
12122   ins_encode %{
12123     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12124     __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12125                                  $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12126                                  /*Biased Locking*/ false,
12127                                  _rtm_counters, _stack_rtm_counters,
12128                                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12129                                  /*TM*/ true, ra_->C->profile_rtm());
12130     // If locking was successfull, crx should indicate 'EQ'.
12131     // The compiler generates a branch to the runtime call to
12132     // _complete_monitor_locking_Java for the case where crx is 'NE'.
12133   %}
12134   ins_pipe(pipe_class_compare);
12135 %}
12136 
12137 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12138   match(Set crx (FastUnlock oop box));
12139   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
12140   predicate(!Compile::current()->use_rtm());
12141 
12142   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2" %}
12143   ins_encode %{
12144     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12145     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12146                                    $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12147                                    UseBiasedLocking && !UseOptoBiasInlining,
12148                                    false);
12149     // If unlocking was successfull, crx should indicate 'EQ'.
12150     // The compiler generates a branch to the runtime call to
12151     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
12152   %}
12153   ins_pipe(pipe_class_compare);
12154 %}
12155 
12156 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{
12157   match(Set crx (FastUnlock oop box));
12158   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3);
12159   predicate(Compile::current()->use_rtm());
12160 
12161   format %{ "FASTUNLOCK  $oop, $box, $tmp1, $tmp2 (TM)" %}
12162   ins_encode %{
12163     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12164     __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register,
12165                                    $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12166                                    /*Biased Locking*/ false, /*TM*/ true);
12167     // If unlocking was successfull, crx should indicate 'EQ'.
12168     // The compiler generates a branch to the runtime call to
12169     // _complete_monitor_unlocking_Java for the case where crx is 'NE'.
12170   %}
12171   ins_pipe(pipe_class_compare);
12172 %}
12173 
12174 // Align address.
12175 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{
12176   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
12177 
12178   format %{ "ANDDI   $dst, $src, $mask \t// next aligned address" %}
12179   size(4);
12180   ins_encode %{
12181     // TODO: PPC port $archOpcode(ppc64Opcode_rldicr);
12182     __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant));
12183   %}
12184   ins_pipe(pipe_class_default);
12185 %}
12186 
12187 // Array size computation.
12188 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{
12189   match(Set dst (SubL (CastP2X end) (CastP2X start)));
12190 
12191   format %{ "SUB     $dst, $end, $start \t// array size in bytes" %}
12192   size(4);
12193   ins_encode %{
12194     // TODO: PPC port $archOpcode(ppc64Opcode_subf);
12195     __ subf($dst$$Register, $start$$Register, $end$$Register);
12196   %}
12197   ins_pipe(pipe_class_default);
12198 %}
12199 
12200 // Clear-array with constant short array length. The versions below can use dcbz with cnt > 30.
12201 instruct inlineCallClearArrayShort(immLmax30 cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
12202   match(Set dummy (ClearArray cnt base));
12203   effect(USE_KILL base, KILL ctr);
12204   ins_cost(2 * MEMORY_REF_COST);
12205 
12206   format %{ "ClearArray $cnt, $base" %}
12207   ins_encode %{
12208     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12209     __ clear_memory_constlen($base$$Register, $cnt$$constant, R0); // kills base, R0
12210   %}
12211   ins_pipe(pipe_class_default);
12212 %}
12213 
12214 // Clear-array with constant large array length.
12215 instruct inlineCallClearArrayLarge(immL cnt, rarg2RegP base, Universe dummy, iRegLdst tmp, regCTR ctr) %{
12216   match(Set dummy (ClearArray cnt base));
12217   effect(USE_KILL base, TEMP tmp, KILL ctr);
12218   ins_cost(3 * MEMORY_REF_COST);
12219 
12220   format %{ "ClearArray $cnt, $base \t// KILL $tmp" %}
12221   ins_encode %{
12222     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12223     __ clear_memory_doubleword($base$$Register, $tmp$$Register, R0, $cnt$$constant); // kills base, R0
12224   %}
12225   ins_pipe(pipe_class_default);
12226 %}
12227 
12228 // Clear-array with dynamic array length.
12229 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{
12230   match(Set dummy (ClearArray cnt base));
12231   effect(USE_KILL cnt, USE_KILL base, KILL ctr);
12232   ins_cost(4 * MEMORY_REF_COST);
12233 
12234   format %{ "ClearArray $cnt, $base" %}
12235   ins_encode %{
12236     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12237     __ clear_memory_doubleword($base$$Register, $cnt$$Register, R0); // kills cnt, base, R0
12238   %}
12239   ins_pipe(pipe_class_default);
12240 %}
12241 
12242 instruct string_compareL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12243                          iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12244   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12245   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12246   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12247   ins_cost(300);
12248   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12249   ins_encode %{
12250     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12251     __ string_compare($str1$$Register, $str2$$Register,
12252                       $cnt1$$Register, $cnt2$$Register,
12253                       $tmp$$Register,
12254                       $result$$Register, StrIntrinsicNode::LL);
12255   %}
12256   ins_pipe(pipe_class_default);
12257 %}
12258 
12259 instruct string_compareU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12260                          iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12261   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12262   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12263   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12264   ins_cost(300);
12265   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12266   ins_encode %{
12267     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12268     __ string_compare($str1$$Register, $str2$$Register,
12269                       $cnt1$$Register, $cnt2$$Register,
12270                       $tmp$$Register,
12271                       $result$$Register, StrIntrinsicNode::UU);
12272   %}
12273   ins_pipe(pipe_class_default);
12274 %}
12275 
12276 instruct string_compareLU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12277                           iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12278   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12279   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12280   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12281   ins_cost(300);
12282   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12283   ins_encode %{
12284     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12285     __ string_compare($str1$$Register, $str2$$Register,
12286                       $cnt1$$Register, $cnt2$$Register,
12287                       $tmp$$Register,
12288                       $result$$Register, StrIntrinsicNode::LU);
12289   %}
12290   ins_pipe(pipe_class_default);
12291 %}
12292 
12293 instruct string_compareUL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result,
12294                           iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12295   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12296   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12297   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp);
12298   ins_cost(300);
12299   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %}
12300   ins_encode %{
12301     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12302     __ string_compare($str2$$Register, $str1$$Register,
12303                       $cnt2$$Register, $cnt1$$Register,
12304                       $tmp$$Register,
12305                       $result$$Register, StrIntrinsicNode::UL);
12306   %}
12307   ins_pipe(pipe_class_default);
12308 %}
12309 
12310 instruct string_equalsL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
12311                         iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12312   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
12313   match(Set result (StrEquals (Binary str1 str2) cnt));
12314   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
12315   ins_cost(300);
12316   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
12317   ins_encode %{
12318     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12319     __ array_equals(false, $str1$$Register, $str2$$Register,
12320                     $cnt$$Register, $tmp$$Register,
12321                     $result$$Register, true /* byte */);
12322   %}
12323   ins_pipe(pipe_class_default);
12324 %}
12325 
12326 instruct string_equalsU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result,
12327                         iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{
12328   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
12329   match(Set result (StrEquals (Binary str1 str2) cnt));
12330   effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0);
12331   ins_cost(300);
12332   format %{ "String Equals char[]  $str1,$str2,$cnt -> $result \t// KILL $tmp" %}
12333   ins_encode %{
12334     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12335     __ array_equals(false, $str1$$Register, $str2$$Register,
12336                     $cnt$$Register, $tmp$$Register,
12337                     $result$$Register, false /* byte */);
12338   %}
12339   ins_pipe(pipe_class_default);
12340 %}
12341 
12342 instruct array_equalsB(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
12343                        iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
12344   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12345   match(Set result (AryEq ary1 ary2));
12346   effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
12347   ins_cost(300);
12348   format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
12349   ins_encode %{
12350     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12351     __ array_equals(true, $ary1$$Register, $ary2$$Register,
12352                     $tmp1$$Register, $tmp2$$Register,
12353                     $result$$Register, true /* byte */);
12354   %}
12355   ins_pipe(pipe_class_default);
12356 %}
12357 
12358 instruct array_equalsC(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result,
12359                        iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{
12360   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12361   match(Set result (AryEq ary1 ary2));
12362   effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1);
12363   ins_cost(300);
12364   format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %}
12365   ins_encode %{
12366     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12367     __ array_equals(true, $ary1$$Register, $ary2$$Register,
12368                     $tmp1$$Register, $tmp2$$Register,
12369                     $result$$Register, false /* byte */);
12370   %}
12371   ins_pipe(pipe_class_default);
12372 %}
12373 
12374 instruct indexOf_imm1_char_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12375                              immP needleImm, immL offsetImm, immI_1 needlecntImm,
12376                              iRegIdst tmp1, iRegIdst tmp2,
12377                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12378   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12379   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12380   // Required for EA: check if it is still a type_array.
12381   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
12382   ins_cost(150);
12383 
12384   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12385             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12386 
12387   ins_encode %{
12388     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12389     immPOper *needleOper = (immPOper *)$needleImm;
12390     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12391     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12392     jchar chr;
12393 #ifdef VM_LITTLE_ENDIAN
12394     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
12395            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
12396 #else
12397     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
12398            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
12399 #endif
12400     __ string_indexof_char($result$$Register,
12401                            $haystack$$Register, $haycnt$$Register,
12402                            R0, chr,
12403                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12404   %}
12405   ins_pipe(pipe_class_compare);
12406 %}
12407 
12408 instruct indexOf_imm1_char_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12409                              immP needleImm, immL offsetImm, immI_1 needlecntImm,
12410                              iRegIdst tmp1, iRegIdst tmp2,
12411                              flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12412   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12413   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12414   // Required for EA: check if it is still a type_array.
12415   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
12416   ins_cost(150);
12417 
12418   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12419             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12420 
12421   ins_encode %{
12422     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12423     immPOper *needleOper = (immPOper *)$needleImm;
12424     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12425     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12426     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12427     __ string_indexof_char($result$$Register,
12428                            $haystack$$Register, $haycnt$$Register,
12429                            R0, chr,
12430                            $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
12431   %}
12432   ins_pipe(pipe_class_compare);
12433 %}
12434 
12435 instruct indexOf_imm1_char_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12436                               immP needleImm, immL offsetImm, immI_1 needlecntImm,
12437                               iRegIdst tmp1, iRegIdst tmp2,
12438                               flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12439   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm)));
12440   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12441   // Required for EA: check if it is still a type_array.
12442   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
12443   ins_cost(150);
12444 
12445   format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]"
12446             "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12447 
12448   ins_encode %{
12449     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12450     immPOper *needleOper = (immPOper *)$needleImm;
12451     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
12452     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
12453     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12454     __ string_indexof_char($result$$Register,
12455                            $haystack$$Register, $haycnt$$Register,
12456                            R0, chr,
12457                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12458   %}
12459   ins_pipe(pipe_class_compare);
12460 %}
12461 
12462 instruct indexOf_imm1_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12463                         rscratch2RegP needle, immI_1 needlecntImm,
12464                         iRegIdst tmp1, iRegIdst tmp2,
12465                         flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12466   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12467   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12468   // Required for EA: check if it is still a type_array.
12469   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
12470             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12471             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12472   ins_cost(180);
12473 
12474   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12475             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
12476   ins_encode %{
12477     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12478     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12479     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12480     guarantee(needle_values, "sanity");
12481     jchar chr;
12482 #ifdef VM_LITTLE_ENDIAN
12483     chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) |
12484            ((jchar)(unsigned char)needle_values->element_value(0).as_byte());
12485 #else
12486     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
12487            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
12488 #endif
12489     __ string_indexof_char($result$$Register,
12490                            $haystack$$Register, $haycnt$$Register,
12491                            R0, chr,
12492                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12493   %}
12494   ins_pipe(pipe_class_compare);
12495 %}
12496 
12497 instruct indexOf_imm1_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12498                         rscratch2RegP needle, immI_1 needlecntImm,
12499                         iRegIdst tmp1, iRegIdst tmp2,
12500                         flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12501   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12502   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12503   // Required for EA: check if it is still a type_array.
12504   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
12505             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12506             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12507   ins_cost(180);
12508 
12509   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12510             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
12511   ins_encode %{
12512     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12513     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12514     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12515     guarantee(needle_values, "sanity");
12516     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12517     __ string_indexof_char($result$$Register,
12518                            $haystack$$Register, $haycnt$$Register,
12519                            R0, chr,
12520                            $tmp1$$Register, $tmp2$$Register, true /*is_byte*/);
12521   %}
12522   ins_pipe(pipe_class_compare);
12523 %}
12524 
12525 instruct indexOf_imm1_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12526                          rscratch2RegP needle, immI_1 needlecntImm,
12527                          iRegIdst tmp1, iRegIdst tmp2,
12528                          flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12529   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12530   effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12531   // Required for EA: check if it is still a type_array.
12532   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
12533             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12534             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12535   ins_cost(180);
12536 
12537   format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12538             " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %}
12539   ins_encode %{
12540     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12541     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12542     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12543     guarantee(needle_values, "sanity");
12544     jchar chr = (jchar)needle_values->element_value(0).as_byte();
12545     __ string_indexof_char($result$$Register,
12546                            $haystack$$Register, $haycnt$$Register,
12547                            R0, chr,
12548                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12549   %}
12550   ins_pipe(pipe_class_compare);
12551 %}
12552 
12553 instruct indexOfChar_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt,
12554                        iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2,
12555                        flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{
12556   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
12557   effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr);
12558   ins_cost(180);
12559 
12560   format %{ "String IndexOfChar $haystack[0..$haycnt], $ch"
12561             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %}
12562   ins_encode %{
12563     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12564     __ string_indexof_char($result$$Register,
12565                            $haystack$$Register, $haycnt$$Register,
12566                            $ch$$Register, 0 /* this is not used if the character is already in a register */,
12567                            $tmp1$$Register, $tmp2$$Register, false /*is_byte*/);
12568   %}
12569   ins_pipe(pipe_class_compare);
12570 %}
12571 
12572 instruct indexOf_imm_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
12573                        iRegPsrc needle, uimmI15 needlecntImm,
12574                        iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
12575                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12576   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12577   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
12578          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12579   // Required for EA: check if it is still a type_array.
12580   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU &&
12581             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12582             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12583   ins_cost(250);
12584 
12585   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12586             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
12587   ins_encode %{
12588     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12589     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12590     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12591 
12592     __ string_indexof($result$$Register,
12593                       $haystack$$Register, $haycnt$$Register,
12594                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
12595                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
12596   %}
12597   ins_pipe(pipe_class_compare);
12598 %}
12599 
12600 instruct indexOf_imm_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
12601                        iRegPsrc needle, uimmI15 needlecntImm,
12602                        iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
12603                        flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12604   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12605   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
12606          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12607   // Required for EA: check if it is still a type_array.
12608   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL &&
12609             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12610             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12611   ins_cost(250);
12612 
12613   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12614             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
12615   ins_encode %{
12616     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12617     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12618     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12619 
12620     __ string_indexof($result$$Register,
12621                       $haystack$$Register, $haycnt$$Register,
12622                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
12623                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
12624   %}
12625   ins_pipe(pipe_class_compare);
12626 %}
12627 
12628 instruct indexOf_imm_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt,
12629                         iRegPsrc needle, uimmI15 needlecntImm,
12630                         iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5,
12631                         flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12632   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
12633   effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result,
12634          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12635   // Required for EA: check if it is still a type_array.
12636   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL &&
12637             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() &&
12638             n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array());
12639   ins_cost(250);
12640 
12641   format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]"
12642             " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %}
12643   ins_encode %{
12644     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12645     Node *ndl = in(operand_index($needle));  // The node that defines needle.
12646     ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array();
12647 
12648     __ string_indexof($result$$Register,
12649                       $haystack$$Register, $haycnt$$Register,
12650                       $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant,
12651                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
12652   %}
12653   ins_pipe(pipe_class_compare);
12654 %}
12655 
12656 instruct indexOf_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
12657                    iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
12658                    flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12659   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
12660   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
12661          TEMP_DEF result,
12662          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12663   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU);
12664   ins_cost(300);
12665 
12666   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
12667              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
12668   ins_encode %{
12669     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12670     __ string_indexof($result$$Register,
12671                       $haystack$$Register, $haycnt$$Register,
12672                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
12673                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU);
12674   %}
12675   ins_pipe(pipe_class_compare);
12676 %}
12677 
12678 instruct indexOf_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
12679                    iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
12680                    flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12681   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
12682   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
12683          TEMP_DEF result,
12684          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12685   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
12686   ins_cost(300);
12687 
12688   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
12689              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
12690   ins_encode %{
12691     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12692     __ string_indexof($result$$Register,
12693                       $haystack$$Register, $haycnt$$Register,
12694                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
12695                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL);
12696   %}
12697   ins_pipe(pipe_class_compare);
12698 %}
12699 
12700 instruct indexOf_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt,
12701                     iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4,
12702                     flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{
12703   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
12704   effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/
12705          TEMP_DEF result,
12706          TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr);
12707   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
12708   ins_cost(300);
12709 
12710   format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]"
12711              " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %}
12712   ins_encode %{
12713     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12714     __ string_indexof($result$$Register,
12715                       $haystack$$Register, $haycnt$$Register,
12716                       $needle$$Register, NULL, $needlecnt$$Register, 0,  // needlecnt not constant.
12717                       $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL);
12718   %}
12719   ins_pipe(pipe_class_compare);
12720 %}
12721 
12722 // char[] to byte[] compression
12723 instruct string_compress(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
12724                          iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
12725   match(Set result (StrCompressedCopy src (Binary dst len)));
12726   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
12727          USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
12728   ins_cost(300);
12729   format %{ "String Compress $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
12730   ins_encode %{
12731     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12732     Label Lskip, Ldone;
12733     __ li($result$$Register, 0);
12734     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
12735                           $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Ldone);
12736     __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
12737     __ beq(CCR0, Lskip);
12738     __ string_compress($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register, Ldone);
12739     __ bind(Lskip);
12740     __ mr($result$$Register, $len$$Register);
12741     __ bind(Ldone);
12742   %}
12743   ins_pipe(pipe_class_default);
12744 %}
12745 
12746 // byte[] to char[] inflation
12747 instruct string_inflate(Universe dummy, rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegLdst tmp1,
12748                         iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
12749   match(Set dummy (StrInflatedCopy src (Binary dst len)));
12750   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
12751   ins_cost(300);
12752   format %{ "String Inflate $src,$dst,$len \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
12753   ins_encode %{
12754     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12755     Label Ldone;
12756     __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
12757                          $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register);
12758     __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters.
12759     __ beq(CCR0, Ldone);
12760     __ string_inflate($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register);
12761     __ bind(Ldone);
12762   %}
12763   ins_pipe(pipe_class_default);
12764 %}
12765 
12766 // StringCoding.java intrinsics
12767 instruct has_negatives(rarg1RegP ary1, iRegIsrc len, iRegIdst result, iRegLdst tmp1, iRegLdst tmp2,
12768                        regCTR ctr, flagsRegCR0 cr0)
12769 %{
12770   match(Set result (HasNegatives ary1 len));
12771   effect(TEMP_DEF result, USE_KILL ary1, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0);
12772   ins_cost(300);
12773   format %{ "has negatives byte[] $ary1,$len -> $result \t// KILL $tmp1, $tmp2" %}
12774   ins_encode %{
12775     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12776     __ has_negatives($ary1$$Register, $len$$Register, $result$$Register,
12777                      $tmp1$$Register, $tmp2$$Register);
12778   %}
12779   ins_pipe(pipe_class_default);
12780 %}
12781 
12782 // encode char[] to byte[] in ISO_8859_1
12783 instruct encode_iso_array(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1,
12784                           iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{
12785   match(Set result (EncodeISOArray src (Binary dst len)));
12786   effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5,
12787          USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0);
12788   ins_cost(300);
12789   format %{ "Encode array $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %}
12790   ins_encode %{
12791     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12792     Label Lslow, Lfailure1, Lfailure2, Ldone;
12793     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register,
12794                           $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Lfailure1);
12795     __ rldicl_($result$$Register, $len$$Register, 0, 64-3); // Remaining characters.
12796     __ beq(CCR0, Ldone);
12797     __ bind(Lslow);
12798     __ string_compress($src$$Register, $dst$$Register, $result$$Register, $tmp2$$Register, Lfailure2);
12799     __ li($result$$Register, 0);
12800     __ b(Ldone);
12801 
12802     __ bind(Lfailure1);
12803     __ mr($result$$Register, $len$$Register);
12804     __ mfctr($tmp1$$Register);
12805     __ rldimi_($result$$Register, $tmp1$$Register, 3, 0); // Remaining characters.
12806     __ beq(CCR0, Ldone);
12807     __ b(Lslow);
12808 
12809     __ bind(Lfailure2);
12810     __ mfctr($result$$Register); // Remaining characters.
12811 
12812     __ bind(Ldone);
12813     __ subf($result$$Register, $result$$Register, $len$$Register);
12814   %}
12815   ins_pipe(pipe_class_default);
12816 %}
12817 
12818 
12819 //---------- Min/Max Instructions ---------------------------------------------
12820 
12821 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
12822   match(Set dst (MinI src1 src2));
12823   ins_cost(DEFAULT_COST*6);
12824 
12825   expand %{
12826     iRegLdst src1s;
12827     iRegLdst src2s;
12828     iRegLdst diff;
12829     iRegLdst sm;
12830     iRegLdst doz; // difference or zero
12831     convI2L_reg(src1s, src1); // Ensure proper sign extension.
12832     convI2L_reg(src2s, src2); // Ensure proper sign extension.
12833     subL_reg_reg(diff, src2s, src1s);
12834     // Need to consider >=33 bit result, therefore we need signmaskL.
12835     signmask64L_regL(sm, diff);
12836     andL_reg_reg(doz, diff, sm); // <=0
12837     addI_regL_regL(dst, doz, src1s);
12838   %}
12839 %}
12840 
12841 instruct minI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
12842   match(Set dst (MinI src1 src2));
12843   effect(KILL cr0);
12844   predicate(VM_Version::has_isel());
12845   ins_cost(DEFAULT_COST*2);
12846 
12847   ins_encode %{
12848     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12849     __ cmpw(CCR0, $src1$$Register, $src2$$Register);
12850     __ isel($dst$$Register, CCR0, Assembler::less, /*invert*/false, $src1$$Register, $src2$$Register);
12851   %}
12852   ins_pipe(pipe_class_default);
12853 %}
12854 
12855 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{
12856   match(Set dst (MaxI src1 src2));
12857   ins_cost(DEFAULT_COST*6);
12858 
12859   expand %{
12860     iRegLdst src1s;
12861     iRegLdst src2s;
12862     iRegLdst diff;
12863     iRegLdst sm;
12864     iRegLdst doz; // difference or zero
12865     convI2L_reg(src1s, src1); // Ensure proper sign extension.
12866     convI2L_reg(src2s, src2); // Ensure proper sign extension.
12867     subL_reg_reg(diff, src2s, src1s);
12868     // Need to consider >=33 bit result, therefore we need signmaskL.
12869     signmask64L_regL(sm, diff);
12870     andcL_reg_reg(doz, diff, sm); // >=0
12871     addI_regL_regL(dst, doz, src1s);
12872   %}
12873 %}
12874 
12875 instruct maxI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{
12876   match(Set dst (MaxI src1 src2));
12877   effect(KILL cr0);
12878   predicate(VM_Version::has_isel());
12879   ins_cost(DEFAULT_COST*2);
12880 
12881   ins_encode %{
12882     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
12883     __ cmpw(CCR0, $src1$$Register, $src2$$Register);
12884     __ isel($dst$$Register, CCR0, Assembler::greater, /*invert*/false, $src1$$Register, $src2$$Register);
12885   %}
12886   ins_pipe(pipe_class_default);
12887 %}
12888 
12889 //---------- Population Count Instructions ------------------------------------
12890 
12891 // Popcnt for Power7.
12892 instruct popCountI(iRegIdst dst, iRegIsrc src) %{
12893   match(Set dst (PopCountI src));
12894   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
12895   ins_cost(DEFAULT_COST);
12896 
12897   format %{ "POPCNTW $dst, $src" %}
12898   size(4);
12899   ins_encode %{
12900     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
12901     __ popcntw($dst$$Register, $src$$Register);
12902   %}
12903   ins_pipe(pipe_class_default);
12904 %}
12905 
12906 // Popcnt for Power7.
12907 instruct popCountL(iRegIdst dst, iRegLsrc src) %{
12908   predicate(UsePopCountInstruction && VM_Version::has_popcntw());
12909   match(Set dst (PopCountL src));
12910   ins_cost(DEFAULT_COST);
12911 
12912   format %{ "POPCNTD $dst, $src" %}
12913   size(4);
12914   ins_encode %{
12915     // TODO: PPC port $archOpcode(ppc64Opcode_popcntb);
12916     __ popcntd($dst$$Register, $src$$Register);
12917   %}
12918   ins_pipe(pipe_class_default);
12919 %}
12920 
12921 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{
12922   match(Set dst (CountLeadingZerosI src));
12923   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
12924   ins_cost(DEFAULT_COST);
12925 
12926   format %{ "CNTLZW  $dst, $src" %}
12927   size(4);
12928   ins_encode %{
12929     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw);
12930     __ cntlzw($dst$$Register, $src$$Register);
12931   %}
12932   ins_pipe(pipe_class_default);
12933 %}
12934 
12935 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{
12936   match(Set dst (CountLeadingZerosL src));
12937   predicate(UseCountLeadingZerosInstructionsPPC64);  // See Matcher::match_rule_supported.
12938   ins_cost(DEFAULT_COST);
12939 
12940   format %{ "CNTLZD  $dst, $src" %}
12941   size(4);
12942   ins_encode %{
12943     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
12944     __ cntlzd($dst$$Register, $src$$Register);
12945   %}
12946   ins_pipe(pipe_class_default);
12947 %}
12948 
12949 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{
12950   // no match-rule, false predicate
12951   effect(DEF dst, USE src);
12952   predicate(false);
12953 
12954   format %{ "CNTLZD  $dst, $src" %}
12955   size(4);
12956   ins_encode %{
12957     // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd);
12958     __ cntlzd($dst$$Register, $src$$Register);
12959   %}
12960   ins_pipe(pipe_class_default);
12961 %}
12962 
12963 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{
12964   match(Set dst (CountTrailingZerosI src));
12965   predicate(UseCountLeadingZerosInstructionsPPC64);
12966   ins_cost(DEFAULT_COST);
12967 
12968   expand %{
12969     immI16 imm1 %{ (int)-1 %}
12970     immI16 imm2 %{ (int)32 %}
12971     immI_minus1 m1 %{ -1 %}
12972     iRegIdst tmpI1;
12973     iRegIdst tmpI2;
12974     iRegIdst tmpI3;
12975     addI_reg_imm16(tmpI1, src, imm1);
12976     andcI_reg_reg(tmpI2, src, m1, tmpI1);
12977     countLeadingZerosI(tmpI3, tmpI2);
12978     subI_imm16_reg(dst, imm2, tmpI3);
12979   %}
12980 %}
12981 
12982 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{
12983   match(Set dst (CountTrailingZerosL src));
12984   predicate(UseCountLeadingZerosInstructionsPPC64);
12985   ins_cost(DEFAULT_COST);
12986 
12987   expand %{
12988     immL16 imm1 %{ (long)-1 %}
12989     immI16 imm2 %{ (int)64 %}
12990     iRegLdst tmpL1;
12991     iRegLdst tmpL2;
12992     iRegIdst tmpL3;
12993     addL_reg_imm16(tmpL1, src, imm1);
12994     andcL_reg_reg(tmpL2, tmpL1, src);
12995     countLeadingZerosL(tmpL3, tmpL2);
12996     subI_imm16_reg(dst, imm2, tmpL3);
12997  %}
12998 %}
12999 
13000 // Expand nodes for byte_reverse_int.
13001 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
13002   effect(DEF dst, USE src, USE pos, USE shift);
13003   predicate(false);
13004 
13005   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
13006   size(4);
13007   ins_encode %{
13008     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
13009     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
13010   %}
13011   ins_pipe(pipe_class_default);
13012 %}
13013 
13014 // As insrwi_a, but with USE_DEF.
13015 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{
13016   effect(USE_DEF dst, USE src, USE pos, USE shift);
13017   predicate(false);
13018 
13019   format %{ "INSRWI  $dst, $src, $pos, $shift" %}
13020   size(4);
13021   ins_encode %{
13022     // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi);
13023     __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant);
13024   %}
13025   ins_pipe(pipe_class_default);
13026 %}
13027 
13028 // Just slightly faster than java implementation.
13029 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{
13030   match(Set dst (ReverseBytesI src));
13031   ins_cost(7*DEFAULT_COST);
13032 
13033   expand %{
13034     immI16 imm24 %{ (int) 24 %}
13035     immI16 imm16 %{ (int) 16 %}
13036     immI16  imm8 %{ (int)  8 %}
13037     immI16  imm4 %{ (int)  4 %}
13038     immI16  imm0 %{ (int)  0 %}
13039     iRegLdst tmpI1;
13040     iRegLdst tmpI2;
13041     iRegLdst tmpI3;
13042 
13043     urShiftI_reg_imm(tmpI1, src, imm24);
13044     insrwi_a(dst, tmpI1, imm24, imm8);
13045     urShiftI_reg_imm(tmpI2, src, imm16);
13046     insrwi(dst, tmpI2, imm8, imm16);
13047     urShiftI_reg_imm(tmpI3, src, imm8);
13048     insrwi(dst, tmpI3, imm8, imm8);
13049     insrwi(dst, src, imm0, imm8);
13050   %}
13051 %}
13052 
13053 instruct bytes_reverse_long_Ex(iRegLdst dst, iRegLsrc src) %{
13054   match(Set dst (ReverseBytesL src));
13055   ins_cost(15*DEFAULT_COST);
13056 
13057   expand %{
13058     immI16 imm56 %{ (int) 56 %}
13059     immI16 imm48 %{ (int) 48 %}
13060     immI16 imm40 %{ (int) 40 %}
13061     immI16 imm32 %{ (int) 32 %}
13062     immI16 imm24 %{ (int) 24 %}
13063     immI16 imm16 %{ (int) 16 %}
13064     immI16  imm8 %{ (int)  8 %}
13065     immI16  imm0 %{ (int)  0 %}
13066     iRegLdst tmpL1;
13067     iRegLdst tmpL2;
13068     iRegLdst tmpL3;
13069     iRegLdst tmpL4;
13070     iRegLdst tmpL5;
13071     iRegLdst tmpL6;
13072 
13073                                         // src   : |a|b|c|d|e|f|g|h|
13074     rldicl(tmpL1, src, imm8, imm24);    // tmpL1 : | | | |e|f|g|h|a|
13075     rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |a| | | |e|
13076     rldicl(tmpL3, tmpL2, imm32, imm0);  // tmpL3 : | | | |e| | | |a|
13077     rldicl(tmpL1, src, imm16, imm24);   // tmpL1 : | | | |f|g|h|a|b|
13078     rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |b| | | |f|
13079     rldicl(tmpL4, tmpL2, imm40, imm0);  // tmpL4 : | | |f| | | |b| |
13080     orL_reg_reg(tmpL5, tmpL3, tmpL4);   // tmpL5 : | | |f|e| | |b|a|
13081     rldicl(tmpL1, src, imm24, imm24);   // tmpL1 : | | | |g|h|a|b|c|
13082     rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |c| | | |g|
13083     rldicl(tmpL3, tmpL2, imm48, imm0);  // tmpL3 : | |g| | | |c| | |
13084     rldicl(tmpL1, src, imm32, imm24);   // tmpL1 : | | | |h|a|b|c|d|
13085     rldicl(tmpL2, tmpL1, imm32, imm24); // tmpL2 : | | | |d| | | |h|
13086     rldicl(tmpL4, tmpL2, imm56, imm0);  // tmpL4 : |h| | | |d| | | |
13087     orL_reg_reg(tmpL6, tmpL3, tmpL4);   // tmpL6 : |h|g| | |d|c| | |
13088     orL_reg_reg(dst, tmpL5, tmpL6);     // dst   : |h|g|f|e|d|c|b|a|
13089   %}
13090 %}
13091 
13092 instruct bytes_reverse_ushort_Ex(iRegIdst dst, iRegIsrc src) %{
13093   match(Set dst (ReverseBytesUS src));
13094   ins_cost(2*DEFAULT_COST);
13095 
13096   expand %{
13097     immI16  imm16 %{ (int) 16 %}
13098     immI16   imm8 %{ (int)  8 %}
13099 
13100     urShiftI_reg_imm(dst, src, imm8);
13101     insrwi(dst, src, imm16, imm8);
13102   %}
13103 %}
13104 
13105 instruct bytes_reverse_short_Ex(iRegIdst dst, iRegIsrc src) %{
13106   match(Set dst (ReverseBytesS src));
13107   ins_cost(3*DEFAULT_COST);
13108 
13109   expand %{
13110     immI16  imm16 %{ (int) 16 %}
13111     immI16   imm8 %{ (int)  8 %}
13112     iRegLdst tmpI1;
13113 
13114     urShiftI_reg_imm(tmpI1, src, imm8);
13115     insrwi(tmpI1, src, imm16, imm8);
13116     extsh(dst, tmpI1);
13117   %}
13118 %}
13119 
13120 // Load Integer reversed byte order
13121 instruct loadI_reversed(iRegIdst dst, indirect mem) %{
13122   match(Set dst (ReverseBytesI (LoadI mem)));
13123   ins_cost(MEMORY_REF_COST);
13124 
13125   size(4);
13126   ins_encode %{
13127     __ lwbrx($dst$$Register, $mem$$Register);
13128   %}
13129   ins_pipe(pipe_class_default);
13130 %}
13131 
13132 // Load Long - aligned and reversed
13133 instruct loadL_reversed(iRegLdst dst, indirect mem) %{
13134   match(Set dst (ReverseBytesL (LoadL mem)));
13135   predicate(VM_Version::has_ldbrx());
13136   ins_cost(MEMORY_REF_COST);
13137 
13138   size(4);
13139   ins_encode %{
13140     __ ldbrx($dst$$Register, $mem$$Register);
13141   %}
13142   ins_pipe(pipe_class_default);
13143 %}
13144 
13145 // Load unsigned short / char reversed byte order
13146 instruct loadUS_reversed(iRegIdst dst, indirect mem) %{
13147   match(Set dst (ReverseBytesUS (LoadUS mem)));
13148   ins_cost(MEMORY_REF_COST);
13149 
13150   size(4);
13151   ins_encode %{
13152     __ lhbrx($dst$$Register, $mem$$Register);
13153   %}
13154   ins_pipe(pipe_class_default);
13155 %}
13156 
13157 // Load short reversed byte order
13158 instruct loadS_reversed(iRegIdst dst, indirect mem) %{
13159   match(Set dst (ReverseBytesS (LoadS mem)));
13160   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
13161 
13162   size(8);
13163   ins_encode %{
13164     __ lhbrx($dst$$Register, $mem$$Register);
13165     __ extsh($dst$$Register, $dst$$Register);
13166   %}
13167   ins_pipe(pipe_class_default);
13168 %}
13169 
13170 // Store Integer reversed byte order
13171 instruct storeI_reversed(iRegIsrc src, indirect mem) %{
13172   match(Set mem (StoreI mem (ReverseBytesI src)));
13173   ins_cost(MEMORY_REF_COST);
13174 
13175   size(4);
13176   ins_encode %{
13177     __ stwbrx($src$$Register, $mem$$Register);
13178   %}
13179   ins_pipe(pipe_class_default);
13180 %}
13181 
13182 // Store Long reversed byte order
13183 instruct storeL_reversed(iRegLsrc src, indirect mem) %{
13184   match(Set mem (StoreL mem (ReverseBytesL src)));
13185   predicate(VM_Version::has_stdbrx());
13186   ins_cost(MEMORY_REF_COST);
13187 
13188   size(4);
13189   ins_encode %{
13190     __ stdbrx($src$$Register, $mem$$Register);
13191   %}
13192   ins_pipe(pipe_class_default);
13193 %}
13194 
13195 // Store unsigned short / char reversed byte order
13196 instruct storeUS_reversed(iRegIsrc src, indirect mem) %{
13197   match(Set mem (StoreC mem (ReverseBytesUS src)));
13198   ins_cost(MEMORY_REF_COST);
13199 
13200   size(4);
13201   ins_encode %{
13202     __ sthbrx($src$$Register, $mem$$Register);
13203   %}
13204   ins_pipe(pipe_class_default);
13205 %}
13206 
13207 // Store short reversed byte order
13208 instruct storeS_reversed(iRegIsrc src, indirect mem) %{
13209   match(Set mem (StoreC mem (ReverseBytesS src)));
13210   ins_cost(MEMORY_REF_COST);
13211 
13212   size(4);
13213   ins_encode %{
13214     __ sthbrx($src$$Register, $mem$$Register);
13215   %}
13216   ins_pipe(pipe_class_default);
13217 %}
13218 
13219 //---------- Replicate Vector Instructions ------------------------------------
13220 
13221 // Insrdi does replicate if src == dst.
13222 instruct repl32(iRegLdst dst) %{
13223   predicate(false);
13224   effect(USE_DEF dst);
13225 
13226   format %{ "INSRDI  $dst, #0, $dst, #32 \t// replicate" %}
13227   size(4);
13228   ins_encode %{
13229     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13230     __ insrdi($dst$$Register, $dst$$Register, 32, 0);
13231   %}
13232   ins_pipe(pipe_class_default);
13233 %}
13234 
13235 // Insrdi does replicate if src == dst.
13236 instruct repl48(iRegLdst dst) %{
13237   predicate(false);
13238   effect(USE_DEF dst);
13239 
13240   format %{ "INSRDI  $dst, #0, $dst, #48 \t// replicate" %}
13241   size(4);
13242   ins_encode %{
13243     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13244     __ insrdi($dst$$Register, $dst$$Register, 48, 0);
13245   %}
13246   ins_pipe(pipe_class_default);
13247 %}
13248 
13249 // Insrdi does replicate if src == dst.
13250 instruct repl56(iRegLdst dst) %{
13251   predicate(false);
13252   effect(USE_DEF dst);
13253 
13254   format %{ "INSRDI  $dst, #0, $dst, #56 \t// replicate" %}
13255   size(4);
13256   ins_encode %{
13257     // TODO: PPC port $archOpcode(ppc64Opcode_rldimi);
13258     __ insrdi($dst$$Register, $dst$$Register, 56, 0);
13259   %}
13260   ins_pipe(pipe_class_default);
13261 %}
13262 
13263 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13264   match(Set dst (ReplicateB src));
13265   predicate(n->as_Vector()->length() == 8);
13266   expand %{
13267     moveReg(dst, src);
13268     repl56(dst);
13269     repl48(dst);
13270     repl32(dst);
13271   %}
13272 %}
13273 
13274 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{
13275   match(Set dst (ReplicateB zero));
13276   predicate(n->as_Vector()->length() == 8);
13277   format %{ "LI      $dst, #0 \t// replicate8B" %}
13278   size(4);
13279   ins_encode %{
13280     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13281     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13282   %}
13283   ins_pipe(pipe_class_default);
13284 %}
13285 
13286 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{
13287   match(Set dst (ReplicateB src));
13288   predicate(n->as_Vector()->length() == 8);
13289   format %{ "LI      $dst, #-1 \t// replicate8B" %}
13290   size(4);
13291   ins_encode %{
13292     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13293     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13294   %}
13295   ins_pipe(pipe_class_default);
13296 %}
13297 
13298 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13299   match(Set dst (ReplicateS src));
13300   predicate(n->as_Vector()->length() == 4);
13301   expand %{
13302     moveReg(dst, src);
13303     repl48(dst);
13304     repl32(dst);
13305   %}
13306 %}
13307 
13308 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{
13309   match(Set dst (ReplicateS zero));
13310   predicate(n->as_Vector()->length() == 4);
13311   format %{ "LI      $dst, #0 \t// replicate4C" %}
13312   size(4);
13313   ins_encode %{
13314     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13315     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13316   %}
13317   ins_pipe(pipe_class_default);
13318 %}
13319 
13320 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{
13321   match(Set dst (ReplicateS src));
13322   predicate(n->as_Vector()->length() == 4);
13323   format %{ "LI      $dst, -1 \t// replicate4C" %}
13324   size(4);
13325   ins_encode %{
13326     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13327     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13328   %}
13329   ins_pipe(pipe_class_default);
13330 %}
13331 
13332 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{
13333   match(Set dst (ReplicateI src));
13334   predicate(n->as_Vector()->length() == 2);
13335   ins_cost(2 * DEFAULT_COST);
13336   expand %{
13337     moveReg(dst, src);
13338     repl32(dst);
13339   %}
13340 %}
13341 
13342 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{
13343   match(Set dst (ReplicateI zero));
13344   predicate(n->as_Vector()->length() == 2);
13345   format %{ "LI      $dst, #0 \t// replicate4C" %}
13346   size(4);
13347   ins_encode %{
13348     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13349     __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF)));
13350   %}
13351   ins_pipe(pipe_class_default);
13352 %}
13353 
13354 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{
13355   match(Set dst (ReplicateI src));
13356   predicate(n->as_Vector()->length() == 2);
13357   format %{ "LI      $dst, -1 \t// replicate4C" %}
13358   size(4);
13359   ins_encode %{
13360     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13361     __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF)));
13362   %}
13363   ins_pipe(pipe_class_default);
13364 %}
13365 
13366 // Move float to int register via stack, replicate.
13367 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{
13368   match(Set dst (ReplicateF src));
13369   predicate(n->as_Vector()->length() == 2);
13370   ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST);
13371   expand %{
13372     stackSlotL tmpS;
13373     iRegIdst tmpI;
13374     moveF2I_reg_stack(tmpS, src);   // Move float to stack.
13375     moveF2I_stack_reg(tmpI, tmpS);  // Move stack to int reg.
13376     moveReg(dst, tmpI);             // Move int to long reg.
13377     repl32(dst);                    // Replicate bitpattern.
13378   %}
13379 %}
13380 
13381 // Replicate scalar constant to packed float values in Double register
13382 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{
13383   match(Set dst (ReplicateF src));
13384   predicate(n->as_Vector()->length() == 2);
13385   ins_cost(5 * DEFAULT_COST);
13386 
13387   format %{ "LD      $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %}
13388   postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) );
13389 %}
13390 
13391 // Replicate scalar zero constant to packed float values in Double register
13392 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{
13393   match(Set dst (ReplicateF zero));
13394   predicate(n->as_Vector()->length() == 2);
13395 
13396   format %{ "LI      $dst, #0 \t// replicate2F" %}
13397   ins_encode %{
13398     // TODO: PPC port $archOpcode(ppc64Opcode_addi);
13399     __ li($dst$$Register, 0x0);
13400   %}
13401   ins_pipe(pipe_class_default);
13402 %}
13403 
13404 
13405 //----------Overflow Math Instructions-----------------------------------------
13406 
13407 // Note that we have to make sure that XER.SO is reset before using overflow instructions.
13408 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc).
13409 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.)
13410 
13411 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13412   match(Set cr0 (OverflowAddL op1 op2));
13413 
13414   format %{ "add_    $op1, $op2\t# overflow check long" %}
13415   ins_encode %{
13416     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13417     __ li(R0, 0);
13418     __ mtxer(R0); // clear XER.SO
13419     __ addo_(R0, $op1$$Register, $op2$$Register);
13420   %}
13421   ins_pipe(pipe_class_default);
13422 %}
13423 
13424 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13425   match(Set cr0 (OverflowSubL op1 op2));
13426 
13427   format %{ "subfo_  R0, $op2, $op1\t# overflow check long" %}
13428   ins_encode %{
13429     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13430     __ li(R0, 0);
13431     __ mtxer(R0); // clear XER.SO
13432     __ subfo_(R0, $op2$$Register, $op1$$Register);
13433   %}
13434   ins_pipe(pipe_class_default);
13435 %}
13436 
13437 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{
13438   match(Set cr0 (OverflowSubL zero op2));
13439 
13440   format %{ "nego_   R0, $op2\t# overflow check long" %}
13441   ins_encode %{
13442     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13443     __ li(R0, 0);
13444     __ mtxer(R0); // clear XER.SO
13445     __ nego_(R0, $op2$$Register);
13446   %}
13447   ins_pipe(pipe_class_default);
13448 %}
13449 
13450 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{
13451   match(Set cr0 (OverflowMulL op1 op2));
13452 
13453   format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %}
13454   ins_encode %{
13455     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13456     __ li(R0, 0);
13457     __ mtxer(R0); // clear XER.SO
13458     __ mulldo_(R0, $op1$$Register, $op2$$Register);
13459   %}
13460   ins_pipe(pipe_class_default);
13461 %}
13462 
13463 
13464 // ============================================================================
13465 // Safepoint Instruction
13466 
13467 instruct safePoint_poll(iRegPdst poll) %{
13468   match(SafePoint poll);
13469   predicate(LoadPollAddressFromThread);
13470 
13471   // It caused problems to add the effect that r0 is killed, but this
13472   // effect no longer needs to be mentioned, since r0 is not contained
13473   // in a reg_class.
13474 
13475   format %{ "LD      R0, #0, $poll \t// Safepoint poll for GC" %}
13476   size(4);
13477   ins_encode( enc_poll(0x0, poll) );
13478   ins_pipe(pipe_class_default);
13479 %}
13480 
13481 // Safepoint without per-thread support. Load address of page to poll
13482 // as constant.
13483 // Rscratch2RegP is R12.
13484 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be
13485 // a seperate node so that the oop map is at the right location.
13486 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{
13487   match(SafePoint poll);
13488   predicate(!LoadPollAddressFromThread);
13489 
13490   // It caused problems to add the effect that r0 is killed, but this
13491   // effect no longer needs to be mentioned, since r0 is not contained
13492   // in a reg_class.
13493 
13494   format %{ "LD      R0, #0, R12 \t// Safepoint poll for GC" %}
13495   ins_encode( enc_poll(0x0, poll) );
13496   ins_pipe(pipe_class_default);
13497 %}
13498 
13499 // ============================================================================
13500 // Call Instructions
13501 
13502 // Call Java Static Instruction
13503 
13504 // Schedulable version of call static node.
13505 instruct CallStaticJavaDirect(method meth) %{
13506   match(CallStaticJava);
13507   effect(USE meth);
13508   ins_cost(CALL_COST);
13509 
13510   ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */);
13511 
13512   format %{ "CALL,static $meth \t// ==> " %}
13513   size(4);
13514   ins_encode( enc_java_static_call(meth) );
13515   ins_pipe(pipe_class_call);
13516 %}
13517 
13518 // Call Java Dynamic Instruction
13519 
13520 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call).
13521 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable
13522 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node.
13523 // The call destination must still be placed in the constant pool.
13524 instruct CallDynamicJavaDirectSched(method meth) %{
13525   match(CallDynamicJava); // To get all the data fields we need ...
13526   effect(USE meth);
13527   predicate(false);       // ... but never match.
13528 
13529   ins_field_load_ic_hi_node(loadConL_hiNode*);
13530   ins_field_load_ic_node(loadConLNode*);
13531   ins_num_consts(1 /* 1 patchable constant: call destination */);
13532 
13533   format %{ "BL        \t// dynamic $meth ==> " %}
13534   size(4);
13535   ins_encode( enc_java_dynamic_call_sched(meth) );
13536   ins_pipe(pipe_class_call);
13537 %}
13538 
13539 // Schedulable (i.e. postalloc expanded) version of call dynamic java.
13540 // We use postalloc expanded calls if we use inline caches
13541 // and do not update method data.
13542 //
13543 // This instruction has two constants: inline cache (IC) and call destination.
13544 // Loading the inline cache will be postalloc expanded, thus leaving a call with
13545 // one constant.
13546 instruct CallDynamicJavaDirectSched_Ex(method meth) %{
13547   match(CallDynamicJava);
13548   effect(USE meth);
13549   predicate(UseInlineCaches);
13550   ins_cost(CALL_COST);
13551 
13552   ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */);
13553 
13554   format %{ "CALL,dynamic $meth \t// postalloc expanded" %}
13555   postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) );
13556 %}
13557 
13558 // Compound version of call dynamic java
13559 // We use postalloc expanded calls if we use inline caches
13560 // and do not update method data.
13561 instruct CallDynamicJavaDirect(method meth) %{
13562   match(CallDynamicJava);
13563   effect(USE meth);
13564   predicate(!UseInlineCaches);
13565   ins_cost(CALL_COST);
13566 
13567   // Enc_java_to_runtime_call needs up to 4 constants (method data oop).
13568   ins_num_consts(4);
13569 
13570   format %{ "CALL,dynamic $meth \t// ==> " %}
13571   ins_encode( enc_java_dynamic_call(meth, constanttablebase) );
13572   ins_pipe(pipe_class_call);
13573 %}
13574 
13575 // Call Runtime Instruction
13576 
13577 instruct CallRuntimeDirect(method meth) %{
13578   match(CallRuntime);
13579   effect(USE meth);
13580   ins_cost(CALL_COST);
13581 
13582   // Enc_java_to_runtime_call needs up to 3 constants: call target,
13583   // env for callee, C-toc.
13584   ins_num_consts(3);
13585 
13586   format %{ "CALL,runtime" %}
13587   ins_encode( enc_java_to_runtime_call(meth) );
13588   ins_pipe(pipe_class_call);
13589 %}
13590 
13591 // Call Leaf
13592 
13593 // Used by postalloc expand of CallLeafDirect_Ex (mtctr).
13594 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{
13595   effect(DEF dst, USE src);
13596 
13597   ins_num_consts(1);
13598 
13599   format %{ "MTCTR   $src" %}
13600   size(4);
13601   ins_encode( enc_leaf_call_mtctr(src) );
13602   ins_pipe(pipe_class_default);
13603 %}
13604 
13605 // Used by postalloc expand of CallLeafDirect_Ex (actual call).
13606 instruct CallLeafDirect(method meth) %{
13607   match(CallLeaf);   // To get the data all the data fields we need ...
13608   effect(USE meth);
13609   predicate(false);  // but never match.
13610 
13611   format %{ "BCTRL     \t// leaf call $meth ==> " %}
13612   size(4);
13613   ins_encode %{
13614     // TODO: PPC port $archOpcode(ppc64Opcode_bctrl);
13615     __ bctrl();
13616   %}
13617   ins_pipe(pipe_class_call);
13618 %}
13619 
13620 // postalloc expand of CallLeafDirect.
13621 // Load adress to call from TOC, then bl to it.
13622 instruct CallLeafDirect_Ex(method meth) %{
13623   match(CallLeaf);
13624   effect(USE meth);
13625   ins_cost(CALL_COST);
13626 
13627   // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target,
13628   // env for callee, C-toc.
13629   ins_num_consts(3);
13630 
13631   format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %}
13632   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
13633 %}
13634 
13635 // Call runtime without safepoint - same as CallLeaf.
13636 // postalloc expand of CallLeafNoFPDirect.
13637 // Load adress to call from TOC, then bl to it.
13638 instruct CallLeafNoFPDirect_Ex(method meth) %{
13639   match(CallLeafNoFP);
13640   effect(USE meth);
13641   ins_cost(CALL_COST);
13642 
13643   // Enc_java_to_runtime_call needs up to 3 constants: call target,
13644   // env for callee, C-toc.
13645   ins_num_consts(3);
13646 
13647   format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %}
13648   postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) );
13649 %}
13650 
13651 // Tail Call; Jump from runtime stub to Java code.
13652 // Also known as an 'interprocedural jump'.
13653 // Target of jump will eventually return to caller.
13654 // TailJump below removes the return address.
13655 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{
13656   match(TailCall jump_target method_oop);
13657   ins_cost(CALL_COST);
13658 
13659   format %{ "MTCTR   $jump_target \t// $method_oop holds method oop\n\t"
13660             "BCTR         \t// tail call" %}
13661   size(8);
13662   ins_encode %{
13663     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13664     __ mtctr($jump_target$$Register);
13665     __ bctr();
13666   %}
13667   ins_pipe(pipe_class_call);
13668 %}
13669 
13670 // Return Instruction
13671 instruct Ret() %{
13672   match(Return);
13673   format %{ "BLR      \t// branch to link register" %}
13674   size(4);
13675   ins_encode %{
13676     // TODO: PPC port $archOpcode(ppc64Opcode_blr);
13677     // LR is restored in MachEpilogNode. Just do the RET here.
13678     __ blr();
13679   %}
13680   ins_pipe(pipe_class_default);
13681 %}
13682 
13683 // Tail Jump; remove the return address; jump to target.
13684 // TailCall above leaves the return address around.
13685 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
13686 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
13687 // "restore" before this instruction (in Epilogue), we need to materialize it
13688 // in %i0.
13689 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{
13690   match(TailJump jump_target ex_oop);
13691   ins_cost(CALL_COST);
13692 
13693   format %{ "LD      R4_ARG2 = LR\n\t"
13694             "MTCTR   $jump_target\n\t"
13695             "BCTR     \t// TailJump, exception oop: $ex_oop" %}
13696   size(12);
13697   ins_encode %{
13698     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13699     __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP);
13700     __ mtctr($jump_target$$Register);
13701     __ bctr();
13702   %}
13703   ins_pipe(pipe_class_call);
13704 %}
13705 
13706 // Create exception oop: created by stack-crawling runtime code.
13707 // Created exception is now available to this handler, and is setup
13708 // just prior to jumping to this handler. No code emitted.
13709 instruct CreateException(rarg1RegP ex_oop) %{
13710   match(Set ex_oop (CreateEx));
13711   ins_cost(0);
13712 
13713   format %{ " -- \t// exception oop; no code emitted" %}
13714   size(0);
13715   ins_encode( /*empty*/ );
13716   ins_pipe(pipe_class_default);
13717 %}
13718 
13719 // Rethrow exception: The exception oop will come in the first
13720 // argument position. Then JUMP (not call) to the rethrow stub code.
13721 instruct RethrowException() %{
13722   match(Rethrow);
13723   ins_cost(CALL_COST);
13724 
13725   format %{ "Jmp     rethrow_stub" %}
13726   ins_encode %{
13727     // TODO: PPC port $archOpcode(ppc64Opcode_compound);
13728     cbuf.set_insts_mark();
13729     __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type);
13730   %}
13731   ins_pipe(pipe_class_call);
13732 %}
13733 
13734 // Die now.
13735 instruct ShouldNotReachHere() %{
13736   match(Halt);
13737   ins_cost(CALL_COST);
13738 
13739   format %{ "ShouldNotReachHere" %}
13740   size(4);
13741   ins_encode %{
13742     // TODO: PPC port $archOpcode(ppc64Opcode_tdi);
13743     __ trap_should_not_reach_here();
13744   %}
13745   ins_pipe(pipe_class_default);
13746 %}
13747 
13748 // This name is KNOWN by the ADLC and cannot be changed.  The ADLC
13749 // forces a 'TypeRawPtr::BOTTOM' output type for this guy.
13750 // Get a DEF on threadRegP, no costs, no encoding, use
13751 // 'ins_should_rematerialize(true)' to avoid spilling.
13752 instruct tlsLoadP(threadRegP dst) %{
13753   match(Set dst (ThreadLocal));
13754   ins_cost(0);
13755 
13756   ins_should_rematerialize(true);
13757 
13758   format %{ " -- \t// $dst=Thread::current(), empty" %}
13759   size(0);
13760   ins_encode( /*empty*/ );
13761   ins_pipe(pipe_class_empty);
13762 %}
13763 
13764 //---Some PPC specific nodes---------------------------------------------------
13765 
13766 // Stop a group.
13767 instruct endGroup() %{
13768   ins_cost(0);
13769 
13770   ins_is_nop(true);
13771 
13772   format %{ "End Bundle (ori r1, r1, 0)" %}
13773   size(4);
13774   ins_encode %{
13775     // TODO: PPC port $archOpcode(ppc64Opcode_endgroup);
13776     __ endgroup();
13777   %}
13778   ins_pipe(pipe_class_default);
13779 %}
13780 
13781 // Nop instructions
13782 
13783 instruct fxNop() %{
13784   ins_cost(0);
13785 
13786   ins_is_nop(true);
13787 
13788   format %{ "fxNop" %}
13789   size(4);
13790   ins_encode %{
13791     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
13792     __ nop();
13793   %}
13794   ins_pipe(pipe_class_default);
13795 %}
13796 
13797 instruct fpNop0() %{
13798   ins_cost(0);
13799 
13800   ins_is_nop(true);
13801 
13802   format %{ "fpNop0" %}
13803   size(4);
13804   ins_encode %{
13805     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
13806     __ fpnop0();
13807   %}
13808   ins_pipe(pipe_class_default);
13809 %}
13810 
13811 instruct fpNop1() %{
13812   ins_cost(0);
13813 
13814   ins_is_nop(true);
13815 
13816   format %{ "fpNop1" %}
13817   size(4);
13818   ins_encode %{
13819     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
13820     __ fpnop1();
13821   %}
13822   ins_pipe(pipe_class_default);
13823 %}
13824 
13825 instruct brNop0() %{
13826   ins_cost(0);
13827   size(4);
13828   format %{ "brNop0" %}
13829   ins_encode %{
13830     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
13831     __ brnop0();
13832   %}
13833   ins_is_nop(true);
13834   ins_pipe(pipe_class_default);
13835 %}
13836 
13837 instruct brNop1() %{
13838   ins_cost(0);
13839 
13840   ins_is_nop(true);
13841 
13842   format %{ "brNop1" %}
13843   size(4);
13844   ins_encode %{
13845     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
13846     __ brnop1();
13847   %}
13848   ins_pipe(pipe_class_default);
13849 %}
13850 
13851 instruct brNop2() %{
13852   ins_cost(0);
13853 
13854   ins_is_nop(true);
13855 
13856   format %{ "brNop2" %}
13857   size(4);
13858   ins_encode %{
13859     // TODO: PPC port $archOpcode(ppc64Opcode_mcrf);
13860     __ brnop2();
13861   %}
13862   ins_pipe(pipe_class_default);
13863 %}
13864 
13865 //----------PEEPHOLE RULES-----------------------------------------------------
13866 // These must follow all instruction definitions as they use the names
13867 // defined in the instructions definitions.
13868 //
13869 // peepmatch ( root_instr_name [preceeding_instruction]* );
13870 //
13871 // peepconstraint %{
13872 // (instruction_number.operand_name relational_op instruction_number.operand_name
13873 //  [, ...] );
13874 // // instruction numbers are zero-based using left to right order in peepmatch
13875 //
13876 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13877 // // provide an instruction_number.operand_name for each operand that appears
13878 // // in the replacement instruction's match rule
13879 //
13880 // ---------VM FLAGS---------------------------------------------------------
13881 //
13882 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13883 //
13884 // Each peephole rule is given an identifying number starting with zero and
13885 // increasing by one in the order seen by the parser. An individual peephole
13886 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13887 // on the command-line.
13888 //
13889 // ---------CURRENT LIMITATIONS----------------------------------------------
13890 //
13891 // Only match adjacent instructions in same basic block
13892 // Only equality constraints
13893 // Only constraints between operands, not (0.dest_reg == EAX_enc)
13894 // Only one replacement instruction
13895 //
13896 // ---------EXAMPLE----------------------------------------------------------
13897 //
13898 // // pertinent parts of existing instructions in architecture description
13899 // instruct movI(eRegI dst, eRegI src) %{
13900 //   match(Set dst (CopyI src));
13901 // %}
13902 //
13903 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
13904 //   match(Set dst (AddI dst src));
13905 //   effect(KILL cr);
13906 // %}
13907 //
13908 // // Change (inc mov) to lea
13909 // peephole %{
13910 //   // increment preceeded by register-register move
13911 //   peepmatch ( incI_eReg movI );
13912 //   // require that the destination register of the increment
13913 //   // match the destination register of the move
13914 //   peepconstraint ( 0.dst == 1.dst );
13915 //   // construct a replacement instruction that sets
13916 //   // the destination to ( move's source register + one )
13917 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13918 // %}
13919 //
13920 // Implementation no longer uses movX instructions since
13921 // machine-independent system no longer uses CopyX nodes.
13922 //
13923 // peephole %{
13924 //   peepmatch ( incI_eReg movI );
13925 //   peepconstraint ( 0.dst == 1.dst );
13926 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13927 // %}
13928 //
13929 // peephole %{
13930 //   peepmatch ( decI_eReg movI );
13931 //   peepconstraint ( 0.dst == 1.dst );
13932 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13933 // %}
13934 //
13935 // peephole %{
13936 //   peepmatch ( addI_eReg_imm movI );
13937 //   peepconstraint ( 0.dst == 1.dst );
13938 //   peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) );
13939 // %}
13940 //
13941 // peephole %{
13942 //   peepmatch ( addP_eReg_imm movP );
13943 //   peepconstraint ( 0.dst == 1.dst );
13944 //   peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) );
13945 // %}
13946 
13947 // // Change load of spilled value to only a spill
13948 // instruct storeI(memory mem, eRegI src) %{
13949 //   match(Set mem (StoreI mem src));
13950 // %}
13951 //
13952 // instruct loadI(eRegI dst, memory mem) %{
13953 //   match(Set dst (LoadI mem));
13954 // %}
13955 //
13956 peephole %{
13957   peepmatch ( loadI storeI );
13958   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13959   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
13960 %}
13961 
13962 peephole %{
13963   peepmatch ( loadL storeL );
13964   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
13965   peepreplace ( storeL( 1.mem 1.mem 1.src ) );
13966 %}
13967 
13968 peephole %{
13969   peepmatch ( loadP storeP );
13970   peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem );
13971   peepreplace ( storeP( 1.dst 1.dst 1.src ) );
13972 %}
13973 
13974 //----------SMARTSPILL RULES---------------------------------------------------
13975 // These must follow all instruction definitions as they use the names
13976 // defined in the instructions definitions.