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src/cpu/ppc/vm/ppc.ad

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rev 13142 : 8181809: PPC64: Leverage mtfprd/mffprd on POWER8
Reviewed-by: mdoerr, simonis
Contributed-by: Matthew Brandyberry <mbrandy@linux.vnet.ibm.com>


3062     Label done;
3063     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3064     __ li($dst$$Register, $zero$$constant);
3065     __ beq($crx$$CondRegister, done);
3066     __ li($dst$$Register, $notzero$$constant);
3067     __ bind(done);
3068   %}
3069 
3070   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3071     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3072 
3073     MacroAssembler _masm(&cbuf);
3074     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3075     Label done;
3076     __ bso($crx$$CondRegister, done);
3077     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3078     // TODO PPC port __ endgroup_if_needed(_size == 12);
3079     __ bind(done);
3080   %}
3081 











3082   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3083     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3084 
3085     MacroAssembler _masm(&cbuf);
3086     Label d;   // dummy
3087     __ bind(d);
3088     Label* p = ($lbl$$label);
3089     // `p' is `NULL' when this encoding class is used only to
3090     // determine the size of the encoded instruction.
3091     Label& l = (NULL == p)? d : *(p);
3092     int cc = $cmp$$cmpcode;
3093     int flags_reg = $crx$$reg;
3094     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3095     int bhint = Assembler::bhintNoHint;
3096 
3097     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3098       if (_prob <= PROB_NEVER) {
3099         bhint = Assembler::bhintIsNotTaken;
3100       } else if (_prob >= PROB_ALWAYS) {
3101         bhint = Assembler::bhintIsTaken;


10109 
10110   format %{ "ANDC    $dst, $src1, $src2" %}
10111   size(4);
10112   ins_encode %{
10113     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
10114     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
10115   %}
10116   ins_pipe(pipe_class_default);
10117 %}
10118 
10119 //----------Moves between int/long and float/double----------------------------
10120 //
10121 // The following rules move values from int/long registers/stack-locations
10122 // to float/double registers/stack-locations and vice versa, without doing any
10123 // conversions. These rules are used to implement the bit-conversion methods
10124 // of java.lang.Float etc., e.g.
10125 //   int   floatToIntBits(float value)
10126 //   float intBitsToFloat(int bits)
10127 //
10128 // Notes on the implementation on ppc64:
10129 // We only provide rules which move between a register and a stack-location,
10130 // because we always have to go through memory when moving between a float
10131 // register and an integer register.



























10132 
10133 //---------- Chain stack slots between similar types --------
10134 
10135 // These are needed so that the rules below can match.
10136 
10137 // Load integer from stack slot
10138 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
10139   match(Set dst src);
10140   ins_cost(MEMORY_REF_COST);
10141 
10142   format %{ "LWZ     $dst, $src" %}
10143   size(4);
10144   ins_encode( enc_lwz(dst, src) );
10145   ins_pipe(pipe_class_memory);
10146 %}
10147 
10148 // Store integer to stack slot
10149 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
10150   match(Set dst src);
10151   ins_cost(MEMORY_REF_COST);


10624     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
10625     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10626   %}
10627   ins_pipe(pipe_class_default);
10628 %}
10629 
10630 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
10631   // no match-rule, false predicate
10632   effect(DEF dst, USE crx, USE src);
10633   predicate(false);
10634 
10635   ins_variable_size_depending_on_alignment(true);
10636 
10637   format %{ "cmovI   $crx, $dst, $src" %}
10638   // Worst case is branch + move + stop, no stop without scheduler.
10639   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10640   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10641   ins_pipe(pipe_class_default);
10642 %}
10643 














10644 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
10645   // no match-rule, false predicate
10646   effect(DEF dst, USE crx, USE mem);
10647   predicate(false);
10648 
10649   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
10650   postalloc_expand %{
10651     //
10652     // replaces
10653     //
10654     //   region  dst  crx  mem
10655     //    \       |    |   /
10656     //     dst=cmovI_bso_stackSlotL_conLvalue0
10657     //
10658     // with
10659     //
10660     //   region  dst
10661     //    \       /
10662     //     dst=loadConI16(0)
10663     //      |


10678     m2->add_prec(m1);
10679 
10680     // operands for new nodes
10681     m1->_opnds[0] = op_dst;
10682     m1->_opnds[1] = new immI16Oper(0);
10683 
10684     m2->_opnds[0] = op_dst;
10685     m2->_opnds[1] = op_crx;
10686     m2->_opnds[2] = op_mem;
10687 
10688     // registers for new nodes
10689     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10690     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10691 
10692     // Insert new nodes.
10693     nodes->push(m1);
10694     nodes->push(m2);
10695   %}
10696 %}
10697 






















































10698 // Double to Int conversion, NaN is mapped to 0.
10699 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
10700   match(Set dst (ConvD2I src));

10701   ins_cost(DEFAULT_COST);
10702 
10703   expand %{
10704     regD tmpD;
10705     stackSlotL tmpS;
10706     flagsReg crx;
10707     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10708     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10709     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10710     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10711   %}
10712 %}
10713 















10714 instruct convF2IRaw_regF(regF dst, regF src) %{
10715   // no match-rule, false predicate
10716   effect(DEF dst, USE src);
10717   predicate(false);
10718 
10719   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
10720   size(4);
10721   ins_encode %{
10722     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10723     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10724   %}
10725   ins_pipe(pipe_class_default);
10726 %}
10727 
10728 // Float to Int conversion, NaN is mapped to 0.
10729 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
10730   match(Set dst (ConvF2I src));

10731   ins_cost(DEFAULT_COST);
10732 
10733   expand %{
10734     regF tmpF;
10735     stackSlotL tmpS;
10736     flagsReg crx;
10737     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10738     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10739     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10740     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10741   %}
10742 %}
10743 















10744 // Convert to Long
10745 
10746 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
10747   match(Set dst (ConvI2L src));
10748   format %{ "EXTSW   $dst, $src \t// int->long" %}
10749   size(4);
10750   ins_encode %{
10751     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
10752     __ extsw($dst$$Register, $src$$Register);
10753   %}
10754   ins_pipe(pipe_class_default);
10755 %}
10756 
10757 // Zero-extend: convert unsigned int to long (convUI2L).
10758 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
10759   match(Set dst (AndL (ConvI2L src) mask));
10760   ins_cost(DEFAULT_COST);
10761 
10762   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
10763   size(4);


10793     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10794     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10795   %}
10796   ins_pipe(pipe_class_default);
10797 %}
10798 
10799 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
10800   // no match-rule, false predicate
10801   effect(DEF dst, USE crx, USE src);
10802   predicate(false);
10803 
10804   ins_variable_size_depending_on_alignment(true);
10805 
10806   format %{ "cmovL   $crx, $dst, $src" %}
10807   // Worst case is branch + move + stop, no stop without scheduler.
10808   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10809   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10810   ins_pipe(pipe_class_default);
10811 %}
10812 














10813 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
10814   // no match-rule, false predicate
10815   effect(DEF dst, USE crx, USE mem);
10816   predicate(false);
10817 
10818   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
10819   postalloc_expand %{
10820     //
10821     // replaces
10822     //
10823     //   region  dst  crx  mem
10824     //    \       |    |   /
10825     //     dst=cmovL_bso_stackSlotL_conLvalue0
10826     //
10827     // with
10828     //
10829     //   region  dst
10830     //    \       /
10831     //     dst=loadConL16(0)
10832     //      |


10844     m2->add_req(n_region, n_crx, n_mem);
10845     m2->add_prec(m1);
10846 
10847     // operands for new nodes
10848     m1->_opnds[0] = op_dst;
10849     m1->_opnds[1] = new immL16Oper(0);
10850     m2->_opnds[0] = op_dst;
10851     m2->_opnds[1] = op_crx;
10852     m2->_opnds[2] = op_mem;
10853 
10854     // registers for new nodes
10855     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10856     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10857 
10858     // Insert new nodes.
10859     nodes->push(m1);
10860     nodes->push(m2);
10861   %}
10862 %}
10863 



















































10864 // Float to Long conversion, NaN is mapped to 0.
10865 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
10866   match(Set dst (ConvF2L src));

10867   ins_cost(DEFAULT_COST);
10868 
10869   expand %{
10870     regF tmpF;
10871     stackSlotL tmpS;
10872     flagsReg crx;
10873     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10874     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
10875     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10876     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10877   %}
10878 %}
10879 















10880 instruct convD2LRaw_regD(regD dst, regD src) %{
10881   // no match-rule, false predicate
10882   effect(DEF dst, USE src);
10883   predicate(false);
10884 
10885   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
10886   size(4);
10887   ins_encode %{
10888     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10889     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10890   %}
10891   ins_pipe(pipe_class_default);
10892 %}
10893 
10894 // Double to Long conversion, NaN is mapped to 0.
10895 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
10896   match(Set dst (ConvD2L src));

10897   ins_cost(DEFAULT_COST);
10898 
10899   expand %{
10900     regD tmpD;
10901     stackSlotL tmpS;
10902     flagsReg crx;
10903     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10904     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
10905     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10906     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10907   %}
10908 %}
10909 















10910 // Convert to Float
10911 
10912 // Placed here as needed in expand.
10913 instruct convL2DRaw_regD(regD dst, regD src) %{
10914   // no match-rule, false predicate
10915   effect(DEF dst, USE src);
10916   predicate(false);
10917 
10918   format %{ "FCFID $dst, $src \t// convL2D" %}
10919   size(4);
10920   ins_encode %{
10921     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10922     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
10923   %}
10924   ins_pipe(pipe_class_default);
10925 %}
10926 
10927 // Placed here as needed in expand.
10928 instruct convD2F_reg(regF dst, regD src) %{
10929   match(Set dst (ConvD2F src));


10955   %}
10956 %}
10957 
10958 instruct convL2FRaw_regF(regF dst, regD src) %{
10959   // no match-rule, false predicate
10960   effect(DEF dst, USE src);
10961   predicate(false);
10962 
10963   format %{ "FCFIDS $dst, $src \t// convL2F" %}
10964   size(4);
10965   ins_encode %{
10966     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
10967     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
10968   %}
10969   ins_pipe(pipe_class_default);
10970 %}
10971 
10972 // Integer to Float conversion. Special version for Power7.
10973 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
10974   match(Set dst (ConvI2F src));
10975   predicate(VM_Version::has_fcfids());
10976   ins_cost(DEFAULT_COST);
10977 
10978   expand %{
10979     iRegLdst tmpL;
10980     stackSlotL tmpS;
10981     regD tmpD;
10982     convI2L_reg(tmpL, src);              // Sign-extension int to long.
10983     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
10984     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
10985     convL2FRaw_regF(dst, tmpD);          // Convert to float.
10986   %}
10987 %}
10988 













10989 // L2F to avoid runtime call.
10990 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
10991   match(Set dst (ConvL2F src));
10992   predicate(VM_Version::has_fcfids());
10993   ins_cost(DEFAULT_COST);
10994 
10995   expand %{
10996     stackSlotL tmpS;
10997     regD tmpD;
10998     regL_to_stkL(tmpS, src);             // Store long to stack.
10999     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11000     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11001   %}
11002 %}
11003 













11004 // Moved up as used in expand.
11005 //instruct convD2F_reg(regF dst, regD src) %{%}
11006 
11007 // Convert to Double
11008 
11009 // Integer to Double conversion.
11010 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
11011   match(Set dst (ConvI2D src));

11012   ins_cost(DEFAULT_COST);
11013 
11014   expand %{
11015     iRegLdst tmpL;
11016     stackSlotL tmpS;
11017     regD tmpD;
11018     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11019     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11020     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11021     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11022   %}
11023 %}
11024 













11025 // Long to Double conversion
11026 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
11027   match(Set dst (ConvL2D src));
11028   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
11029 
11030   expand %{
11031     regD tmpD;
11032     moveL2D_stack_reg(tmpD, src);
11033     convL2DRaw_regD(dst, tmpD);













11034   %}
11035 %}
11036 
11037 instruct convF2D_reg(regD dst, regF src) %{
11038   match(Set dst (ConvF2D src));
11039   format %{ "FMR     $dst, $src \t// float->double" %}
11040   // variable size, 0 or 4
11041   ins_encode %{
11042     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11043     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
11044   %}
11045   ins_pipe(pipe_class_default);
11046 %}
11047 
11048 //----------Control Flow Instructions------------------------------------------
11049 // Compare Instructions
11050 
11051 // Compare Integers
11052 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
11053   match(Set crx (CmpI src1 src2));




3062     Label done;
3063     __ cmpdi($crx$$CondRegister, $src$$Register, 0);
3064     __ li($dst$$Register, $zero$$constant);
3065     __ beq($crx$$CondRegister, done);
3066     __ li($dst$$Register, $notzero$$constant);
3067     __ bind(done);
3068   %}
3069 
3070   enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{
3071     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3072 
3073     MacroAssembler _masm(&cbuf);
3074     int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_);
3075     Label done;
3076     __ bso($crx$$CondRegister, done);
3077     __ ld($dst$$Register, Idisp, $mem$$base$$Register);
3078     // TODO PPC port __ endgroup_if_needed(_size == 12);
3079     __ bind(done);
3080   %}
3081 
3082   enc_class enc_cmove_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
3083     // TODO: PPC port $archOpcode(ppc64Opcode_cmove);
3084 
3085     MacroAssembler _masm(&cbuf);
3086     Label done;
3087     __ bso($crx$$CondRegister, done);
3088     __ mffprd($dst$$Register, $src$$FloatRegister);
3089     // TODO PPC port __ endgroup_if_needed(_size == 12);
3090     __ bind(done);
3091   %}
3092 
3093   enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{
3094     // TODO: PPC port $archOpcode(ppc64Opcode_bc);
3095 
3096     MacroAssembler _masm(&cbuf);
3097     Label d;   // dummy
3098     __ bind(d);
3099     Label* p = ($lbl$$label);
3100     // `p' is `NULL' when this encoding class is used only to
3101     // determine the size of the encoded instruction.
3102     Label& l = (NULL == p)? d : *(p);
3103     int cc = $cmp$$cmpcode;
3104     int flags_reg = $crx$$reg;
3105     assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding");
3106     int bhint = Assembler::bhintNoHint;
3107 
3108     if (UseStaticBranchPredictionForUncommonPathsPPC64) {
3109       if (_prob <= PROB_NEVER) {
3110         bhint = Assembler::bhintIsNotTaken;
3111       } else if (_prob >= PROB_ALWAYS) {
3112         bhint = Assembler::bhintIsTaken;


10120 
10121   format %{ "ANDC    $dst, $src1, $src2" %}
10122   size(4);
10123   ins_encode %{
10124     // TODO: PPC port $archOpcode(ppc64Opcode_andc);
10125     __ andc($dst$$Register, $src1$$Register, $src2$$Register);
10126   %}
10127   ins_pipe(pipe_class_default);
10128 %}
10129 
10130 //----------Moves between int/long and float/double----------------------------
10131 //
10132 // The following rules move values from int/long registers/stack-locations
10133 // to float/double registers/stack-locations and vice versa, without doing any
10134 // conversions. These rules are used to implement the bit-conversion methods
10135 // of java.lang.Float etc., e.g.
10136 //   int   floatToIntBits(float value)
10137 //   float intBitsToFloat(int bits)
10138 //
10139 // Notes on the implementation on ppc64:
10140 // For Power7 and earlier, the rules are limited to those which move between a
10141 // register and a stack-location, because we always have to go through memory
10142 // when moving between a float register and an integer register.
10143 // This restriction is removed in Power8 with the introduction of the mtfprd
10144 // and mffprd instructions.
10145 
10146 instruct moveL2D_reg(regD dst, iRegLsrc src) %{
10147   match(Set dst (MoveL2D src));
10148   predicate(VM_Version::has_mtfprd());
10149 
10150   format %{ "MTFPRD  $dst, $src" %}
10151   size(4);
10152   ins_encode %{
10153     __ mtfprd($dst$$FloatRegister, $src$$Register);
10154   %}
10155   ins_pipe(pipe_class_default);
10156 %}
10157 
10158 instruct moveI2D_reg(regD dst, iRegIsrc src) %{
10159   // no match-rule, false predicate
10160   effect(DEF dst, USE src);
10161   predicate(false);
10162 
10163   format %{ "MTFPRWA $dst, $src" %}
10164   size(4);
10165   ins_encode %{
10166     __ mtfprwa($dst$$FloatRegister, $src$$Register);
10167   %}
10168   ins_pipe(pipe_class_default);
10169 %}
10170 
10171 //---------- Chain stack slots between similar types --------
10172 
10173 // These are needed so that the rules below can match.
10174 
10175 // Load integer from stack slot
10176 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{
10177   match(Set dst src);
10178   ins_cost(MEMORY_REF_COST);
10179 
10180   format %{ "LWZ     $dst, $src" %}
10181   size(4);
10182   ins_encode( enc_lwz(dst, src) );
10183   ins_pipe(pipe_class_memory);
10184 %}
10185 
10186 // Store integer to stack slot
10187 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{
10188   match(Set dst src);
10189   ins_cost(MEMORY_REF_COST);


10662     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);;
10663     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10664   %}
10665   ins_pipe(pipe_class_default);
10666 %}
10667 
10668 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{
10669   // no match-rule, false predicate
10670   effect(DEF dst, USE crx, USE src);
10671   predicate(false);
10672 
10673   ins_variable_size_depending_on_alignment(true);
10674 
10675   format %{ "cmovI   $crx, $dst, $src" %}
10676   // Worst case is branch + move + stop, no stop without scheduler.
10677   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10678   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10679   ins_pipe(pipe_class_default);
10680 %}
10681 
10682 instruct cmovI_bso_reg(iRegIdst dst, flagsRegSrc crx, regD src) %{
10683   // no match-rule, false predicate
10684   effect(DEF dst, USE crx, USE src);
10685   predicate(false);
10686 
10687   ins_variable_size_depending_on_alignment(true);
10688 
10689   format %{ "cmovI   $crx, $dst, $src" %}
10690   // Worst case is branch + move + stop, no stop without scheduler.
10691   size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8);
10692   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
10693   ins_pipe(pipe_class_default);
10694 %}
10695 
10696 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{
10697   // no match-rule, false predicate
10698   effect(DEF dst, USE crx, USE mem);
10699   predicate(false);
10700 
10701   format %{ "CmovI   $dst, $crx, $mem \t// postalloc expanded" %}
10702   postalloc_expand %{
10703     //
10704     // replaces
10705     //
10706     //   region  dst  crx  mem
10707     //    \       |    |   /
10708     //     dst=cmovI_bso_stackSlotL_conLvalue0
10709     //
10710     // with
10711     //
10712     //   region  dst
10713     //    \       /
10714     //     dst=loadConI16(0)
10715     //      |


10730     m2->add_prec(m1);
10731 
10732     // operands for new nodes
10733     m1->_opnds[0] = op_dst;
10734     m1->_opnds[1] = new immI16Oper(0);
10735 
10736     m2->_opnds[0] = op_dst;
10737     m2->_opnds[1] = op_crx;
10738     m2->_opnds[2] = op_mem;
10739 
10740     // registers for new nodes
10741     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10742     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10743 
10744     // Insert new nodes.
10745     nodes->push(m1);
10746     nodes->push(m2);
10747   %}
10748 %}
10749 
10750 instruct cmovI_bso_reg_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, regD src) %{
10751   // no match-rule, false predicate
10752   effect(DEF dst, USE crx, USE src);
10753   predicate(false);
10754 
10755   format %{ "CmovI   $dst, $crx, $src \t// postalloc expanded" %}
10756   postalloc_expand %{
10757     //
10758     // replaces
10759     //
10760     //   region  dst  crx  src
10761     //    \       |    |   /
10762     //     dst=cmovI_bso_reg_conLvalue0
10763     //
10764     // with
10765     //
10766     //   region  dst
10767     //    \       /
10768     //     dst=loadConI16(0)
10769     //      |
10770     //      ^  region  dst  crx  src
10771     //      |   \       |    |    /
10772     //      dst=cmovI_bso_reg
10773     //
10774 
10775     // Create new nodes.
10776     MachNode *m1 = new loadConI16Node();
10777     MachNode *m2 = new cmovI_bso_regNode();
10778 
10779     // inputs for new nodes
10780     m1->add_req(n_region);
10781     m2->add_req(n_region, n_crx, n_src);
10782 
10783     // precedences for new nodes
10784     m2->add_prec(m1);
10785 
10786     // operands for new nodes
10787     m1->_opnds[0] = op_dst;
10788     m1->_opnds[1] = new immI16Oper(0);
10789 
10790     m2->_opnds[0] = op_dst;
10791     m2->_opnds[1] = op_crx;
10792     m2->_opnds[2] = op_src;
10793 
10794     // registers for new nodes
10795     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10796     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
10797 
10798     // Insert new nodes.
10799     nodes->push(m1);
10800     nodes->push(m2);
10801   %}
10802 %}
10803 
10804 // Double to Int conversion, NaN is mapped to 0.
10805 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{
10806   match(Set dst (ConvD2I src));
10807   predicate(!VM_Version::has_mtfprd());
10808   ins_cost(DEFAULT_COST);
10809 
10810   expand %{
10811     regD tmpD;
10812     stackSlotL tmpS;
10813     flagsReg crx;
10814     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10815     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10816     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
10817     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10818   %}
10819 %}
10820 
10821 // Double to Int conversion, NaN is mapped to 0. Special version for Power8.
10822 instruct convD2I_reg_mffprd_ExEx(iRegIdst dst, regD src) %{
10823   match(Set dst (ConvD2I src));
10824   predicate(VM_Version::has_mtfprd());
10825   ins_cost(DEFAULT_COST);
10826 
10827   expand %{
10828     regD tmpD;
10829     flagsReg crx;
10830     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10831     convD2IRaw_regD(tmpD, src);                         // Convert float to int (speculated).
10832     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
10833   %}
10834 %}
10835 
10836 instruct convF2IRaw_regF(regF dst, regF src) %{
10837   // no match-rule, false predicate
10838   effect(DEF dst, USE src);
10839   predicate(false);
10840 
10841   format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %}
10842   size(4);
10843   ins_encode %{
10844     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10845     __ fctiwz($dst$$FloatRegister, $src$$FloatRegister);
10846   %}
10847   ins_pipe(pipe_class_default);
10848 %}
10849 
10850 // Float to Int conversion, NaN is mapped to 0.
10851 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{
10852   match(Set dst (ConvF2I src));
10853   predicate(!VM_Version::has_mtfprd());
10854   ins_cost(DEFAULT_COST);
10855 
10856   expand %{
10857     regF tmpF;
10858     stackSlotL tmpS;
10859     flagsReg crx;
10860     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10861     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10862     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
10863     cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
10864   %}
10865 %}
10866 
10867 // Float to Int conversion, NaN is mapped to 0. Special version for Power8.
10868 instruct convF2I_regF_mffprd_ExEx(iRegIdst dst, regF src) %{
10869   match(Set dst (ConvF2I src));
10870   predicate(VM_Version::has_mtfprd());
10871   ins_cost(DEFAULT_COST);
10872 
10873   expand %{
10874     regF tmpF;
10875     flagsReg crx;
10876     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
10877     convF2IRaw_regF(tmpF, src);                         // Convert float to int (speculated).
10878     cmovI_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
10879   %}
10880 %}
10881 
10882 // Convert to Long
10883 
10884 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{
10885   match(Set dst (ConvI2L src));
10886   format %{ "EXTSW   $dst, $src \t// int->long" %}
10887   size(4);
10888   ins_encode %{
10889     // TODO: PPC port $archOpcode(ppc64Opcode_extsw);
10890     __ extsw($dst$$Register, $src$$Register);
10891   %}
10892   ins_pipe(pipe_class_default);
10893 %}
10894 
10895 // Zero-extend: convert unsigned int to long (convUI2L).
10896 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{
10897   match(Set dst (AndL (ConvI2L src) mask));
10898   ins_cost(DEFAULT_COST);
10899 
10900   format %{ "CLRLDI  $dst, $src, #32 \t// zero-extend int to long" %}
10901   size(4);


10931     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
10932     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
10933   %}
10934   ins_pipe(pipe_class_default);
10935 %}
10936 
10937 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{
10938   // no match-rule, false predicate
10939   effect(DEF dst, USE crx, USE src);
10940   predicate(false);
10941 
10942   ins_variable_size_depending_on_alignment(true);
10943 
10944   format %{ "cmovL   $crx, $dst, $src" %}
10945   // Worst case is branch + move + stop, no stop without scheduler.
10946   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10947   ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) );
10948   ins_pipe(pipe_class_default);
10949 %}
10950 
10951 instruct cmovL_bso_reg(iRegLdst dst, flagsRegSrc crx, regD src) %{
10952   // no match-rule, false predicate
10953   effect(DEF dst, USE crx, USE src);
10954   predicate(false);
10955 
10956   ins_variable_size_depending_on_alignment(true);
10957 
10958   format %{ "cmovL   $crx, $dst, $src" %}
10959   // Worst case is branch + move + stop, no stop without scheduler.
10960   size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8);
10961   ins_encode( enc_cmove_bso_reg(dst, crx, src) );
10962   ins_pipe(pipe_class_default);
10963 %}
10964 
10965 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{
10966   // no match-rule, false predicate
10967   effect(DEF dst, USE crx, USE mem);
10968   predicate(false);
10969 
10970   format %{ "CmovL   $dst, $crx, $mem \t// postalloc expanded" %}
10971   postalloc_expand %{
10972     //
10973     // replaces
10974     //
10975     //   region  dst  crx  mem
10976     //    \       |    |   /
10977     //     dst=cmovL_bso_stackSlotL_conLvalue0
10978     //
10979     // with
10980     //
10981     //   region  dst
10982     //    \       /
10983     //     dst=loadConL16(0)
10984     //      |


10996     m2->add_req(n_region, n_crx, n_mem);
10997     m2->add_prec(m1);
10998 
10999     // operands for new nodes
11000     m1->_opnds[0] = op_dst;
11001     m1->_opnds[1] = new immL16Oper(0);
11002     m2->_opnds[0] = op_dst;
11003     m2->_opnds[1] = op_crx;
11004     m2->_opnds[2] = op_mem;
11005 
11006     // registers for new nodes
11007     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11008     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11009 
11010     // Insert new nodes.
11011     nodes->push(m1);
11012     nodes->push(m2);
11013   %}
11014 %}
11015 
11016 instruct cmovL_bso_reg_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, regD src) %{
11017   // no match-rule, false predicate
11018   effect(DEF dst, USE crx, USE src);
11019   predicate(false);
11020 
11021   format %{ "CmovL   $dst, $crx, $src \t// postalloc expanded" %}
11022   postalloc_expand %{
11023     //
11024     // replaces
11025     //
11026     //   region  dst  crx  src
11027     //    \       |    |   /
11028     //     dst=cmovL_bso_reg_conLvalue0
11029     //
11030     // with
11031     //
11032     //   region  dst
11033     //    \       /
11034     //     dst=loadConL16(0)
11035     //      |
11036     //      ^  region  dst  crx  src
11037     //      |   \       |    |    /
11038     //      dst=cmovL_bso_reg
11039     //
11040 
11041     // Create new nodes.
11042     MachNode *m1 = new loadConL16Node();
11043     MachNode *m2 = new cmovL_bso_regNode();
11044 
11045     // inputs for new nodes
11046     m1->add_req(n_region);
11047     m2->add_req(n_region, n_crx, n_src);
11048     m2->add_prec(m1);
11049 
11050     // operands for new nodes
11051     m1->_opnds[0] = op_dst;
11052     m1->_opnds[1] = new immL16Oper(0);
11053     m2->_opnds[0] = op_dst;
11054     m2->_opnds[1] = op_crx;
11055     m2->_opnds[2] = op_src;
11056 
11057     // registers for new nodes
11058     ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11059     ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst
11060 
11061     // Insert new nodes.
11062     nodes->push(m1);
11063     nodes->push(m2);
11064   %}
11065 %}
11066 
11067 // Float to Long conversion, NaN is mapped to 0.
11068 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{
11069   match(Set dst (ConvF2L src));
11070   predicate(!VM_Version::has_mtfprd());
11071   ins_cost(DEFAULT_COST);
11072 
11073   expand %{
11074     regF tmpF;
11075     stackSlotL tmpS;
11076     flagsReg crx;
11077     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11078     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11079     moveF2L_reg_stack(tmpS, tmpF);                      // Store float to stack (speculated).
11080     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11081   %}
11082 %}
11083 
11084 // Float to Long conversion, NaN is mapped to 0. Special version for Power8.
11085 instruct convF2L_reg_mffprd_ExEx(iRegLdst dst, regF src) %{
11086   match(Set dst (ConvF2L src));
11087   predicate(VM_Version::has_mtfprd());
11088   ins_cost(DEFAULT_COST);
11089 
11090   expand %{
11091     regF tmpF;
11092     flagsReg crx;
11093     cmpFUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11094     convF2LRaw_regF(tmpF, src);                         // Convert float to long (speculated).
11095     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpF);        // Cmove based on NaN check.
11096   %}
11097 %}
11098 
11099 instruct convD2LRaw_regD(regD dst, regD src) %{
11100   // no match-rule, false predicate
11101   effect(DEF dst, USE src);
11102   predicate(false);
11103 
11104   format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %}
11105   size(4);
11106   ins_encode %{
11107     // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);
11108     __ fctidz($dst$$FloatRegister, $src$$FloatRegister);
11109   %}
11110   ins_pipe(pipe_class_default);
11111 %}
11112 
11113 // Double to Long conversion, NaN is mapped to 0.
11114 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{
11115   match(Set dst (ConvD2L src));
11116   predicate(!VM_Version::has_mtfprd());
11117   ins_cost(DEFAULT_COST);
11118 
11119   expand %{
11120     regD tmpD;
11121     stackSlotL tmpS;
11122     flagsReg crx;
11123     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11124     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11125     moveD2L_reg_stack(tmpS, tmpD);                      // Store float to stack (speculated).
11126     cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check.
11127   %}
11128 %}
11129 
11130 // Double to Long conversion, NaN is mapped to 0. Special version for Power8.
11131 instruct convD2L_reg_mffprd_ExEx(iRegLdst dst, regD src) %{
11132   match(Set dst (ConvD2L src));
11133   predicate(VM_Version::has_mtfprd());
11134   ins_cost(DEFAULT_COST);
11135 
11136   expand %{
11137     regD tmpD;
11138     flagsReg crx;
11139     cmpDUnordered_reg_reg(crx, src, src);               // Check whether src is NaN.
11140     convD2LRaw_regD(tmpD, src);                         // Convert float to long (speculated).
11141     cmovL_bso_reg_conLvalue0_Ex(dst, crx, tmpD);        // Cmove based on NaN check.
11142   %}
11143 %}
11144 
11145 // Convert to Float
11146 
11147 // Placed here as needed in expand.
11148 instruct convL2DRaw_regD(regD dst, regD src) %{
11149   // no match-rule, false predicate
11150   effect(DEF dst, USE src);
11151   predicate(false);
11152 
11153   format %{ "FCFID $dst, $src \t// convL2D" %}
11154   size(4);
11155   ins_encode %{
11156     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11157     __ fcfid($dst$$FloatRegister, $src$$FloatRegister);
11158   %}
11159   ins_pipe(pipe_class_default);
11160 %}
11161 
11162 // Placed here as needed in expand.
11163 instruct convD2F_reg(regF dst, regD src) %{
11164   match(Set dst (ConvD2F src));


11190   %}
11191 %}
11192 
11193 instruct convL2FRaw_regF(regF dst, regD src) %{
11194   // no match-rule, false predicate
11195   effect(DEF dst, USE src);
11196   predicate(false);
11197 
11198   format %{ "FCFIDS $dst, $src \t// convL2F" %}
11199   size(4);
11200   ins_encode %{
11201     // TODO: PPC port $archOpcode(ppc64Opcode_fcfid);
11202     __ fcfids($dst$$FloatRegister, $src$$FloatRegister);
11203   %}
11204   ins_pipe(pipe_class_default);
11205 %}
11206 
11207 // Integer to Float conversion. Special version for Power7.
11208 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{
11209   match(Set dst (ConvI2F src));
11210   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11211   ins_cost(DEFAULT_COST);
11212 
11213   expand %{
11214     iRegLdst tmpL;
11215     stackSlotL tmpS;
11216     regD tmpD;
11217     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11218     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11219     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11220     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11221   %}
11222 %}
11223 
11224 // Integer to Float conversion. Special version for Power8.
11225 instruct convI2F_ireg_mtfprd_Ex(regF dst, iRegIsrc src) %{
11226   match(Set dst (ConvI2F src));
11227   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11228   ins_cost(DEFAULT_COST);
11229 
11230   expand %{
11231     regD tmpD;
11232     moveI2D_reg(tmpD, src);
11233     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11234   %}
11235 %}
11236 
11237 // L2F to avoid runtime call.
11238 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{
11239   match(Set dst (ConvL2F src));
11240   predicate(VM_Version::has_fcfids() && !VM_Version::has_mtfprd());
11241   ins_cost(DEFAULT_COST);
11242 
11243   expand %{
11244     stackSlotL tmpS;
11245     regD tmpD;
11246     regL_to_stkL(tmpS, src);             // Store long to stack.
11247     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11248     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11249   %}
11250 %}
11251 
11252 // L2F to avoid runtime call.  Special version for Power8.
11253 instruct convL2F_ireg_mtfprd_Ex(regF dst, iRegLsrc src) %{
11254   match(Set dst (ConvL2F src));
11255   predicate(VM_Version::has_fcfids() && VM_Version::has_mtfprd());
11256   ins_cost(DEFAULT_COST);
11257 
11258   expand %{
11259     regD tmpD;
11260     moveL2D_reg(tmpD, src);
11261     convL2FRaw_regF(dst, tmpD);          // Convert to float.
11262   %}
11263 %}
11264 
11265 // Moved up as used in expand.
11266 //instruct convD2F_reg(regF dst, regD src) %{%}
11267 
11268 // Convert to Double
11269 
11270 // Integer to Double conversion.
11271 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{
11272   match(Set dst (ConvI2D src));
11273   predicate(!VM_Version::has_mtfprd());
11274   ins_cost(DEFAULT_COST);
11275 
11276   expand %{
11277     iRegLdst tmpL;
11278     stackSlotL tmpS;
11279     regD tmpD;
11280     convI2L_reg(tmpL, src);              // Sign-extension int to long.
11281     regL_to_stkL(tmpS, tmpL);            // Store long to stack.
11282     moveL2D_stack_reg(tmpD, tmpS);       // Load long into double register.
11283     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11284   %}
11285 %}
11286 
11287 // Integer to Double conversion. Special version for Power8.
11288 instruct convI2D_reg_mtfprd_Ex(regD dst, iRegIsrc src) %{
11289   match(Set dst (ConvI2D src));
11290   predicate(VM_Version::has_mtfprd());
11291   ins_cost(DEFAULT_COST);
11292 
11293   expand %{
11294     regD tmpD;
11295     moveI2D_reg(tmpD, src);
11296     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11297   %}
11298 %}
11299 
11300 // Long to Double conversion
11301 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{
11302   match(Set dst (ConvL2D src));
11303   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
11304 
11305   expand %{
11306     regD tmpD;
11307     moveL2D_stack_reg(tmpD, src);
11308     convL2DRaw_regD(dst, tmpD);
11309   %}
11310 %}
11311 
11312 // Long to Double conversion. Special version for Power8.
11313 instruct convL2D_reg_mtfprd_Ex(regD dst, iRegLsrc src) %{
11314   match(Set dst (ConvL2D src));
11315   predicate(VM_Version::has_mtfprd());
11316   ins_cost(DEFAULT_COST);
11317 
11318   expand %{
11319     regD tmpD;
11320     moveL2D_reg(tmpD, src);
11321     convL2DRaw_regD(dst, tmpD);          // Convert to double.
11322   %}
11323 %}
11324 
11325 instruct convF2D_reg(regD dst, regF src) %{
11326   match(Set dst (ConvF2D src));
11327   format %{ "FMR     $dst, $src \t// float->double" %}
11328   // variable size, 0 or 4
11329   ins_encode %{
11330     // TODO: PPC port $archOpcode(ppc64Opcode_fmr);
11331     __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister);
11332   %}
11333   ins_pipe(pipe_class_default);
11334 %}
11335 
11336 //----------Control Flow Instructions------------------------------------------
11337 // Compare Instructions
11338 
11339 // Compare Integers
11340 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{
11341   match(Set crx (CmpI src1 src2));


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