1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2012, 2017, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/assembler.inline.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "compiler/disassembler.hpp"
  30 #include "memory/resourceArea.hpp"
  31 #include "prims/jvm.h"
  32 #include "runtime/java.hpp"
  33 #include "runtime/os.hpp"
  34 #include "runtime/stubCodeGenerator.hpp"
  35 #include "utilities/align.hpp"
  36 #include "utilities/defaultStream.hpp"
  37 #include "utilities/globalDefinitions.hpp"
  38 #include "vm_version_ppc.hpp"
  39 
  40 # include <sys/sysinfo.h>
  41 
  42 bool VM_Version::_is_determine_features_test_running = false;
  43 uint64_t VM_Version::_dscr_val = 0;
  44 
  45 #define MSG(flag)   \
  46   if (flag && !FLAG_IS_DEFAULT(flag))                                  \
  47       jio_fprintf(defaultStream::error_stream(),                       \
  48                   "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
  49                   "         -XX:+" #flag " will be disabled!\n");
  50 
  51 void VM_Version::initialize() {
  52 
  53   // Test which instructions are supported and measure cache line size.
  54   determine_features();
  55 
  56   // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
  57   if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
  58     if (VM_Version::has_lqarx()) {
  59       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
  60     } else if (VM_Version::has_popcntw()) {
  61       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
  62     } else if (VM_Version::has_cmpb()) {
  63       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
  64     } else if (VM_Version::has_popcntb()) {
  65       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
  66     } else {
  67       FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
  68     }
  69   }
  70 
  71   bool PowerArchitecturePPC64_ok = false;
  72   switch (PowerArchitecturePPC64) {
  73     case 8: if (!VM_Version::has_lqarx()  ) break;
  74     case 7: if (!VM_Version::has_popcntw()) break;
  75     case 6: if (!VM_Version::has_cmpb()   ) break;
  76     case 5: if (!VM_Version::has_popcntb()) break;
  77     case 0: PowerArchitecturePPC64_ok = true; break;
  78     default: break;
  79   }
  80   guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
  81             UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
  82 
  83   // Power 8: Configure Data Stream Control Register.
  84   if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
  85     config_dscr();
  86   }
  87 
  88   if (!UseSIGTRAP) {
  89     MSG(TrapBasedICMissChecks);
  90     MSG(TrapBasedNotEntrantChecks);
  91     MSG(TrapBasedNullChecks);
  92     FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
  93     FLAG_SET_ERGO(bool, TrapBasedNullChecks,       false);
  94     FLAG_SET_ERGO(bool, TrapBasedICMissChecks,     false);
  95   }
  96 
  97 #ifdef COMPILER2
  98   if (!UseSIGTRAP) {
  99     MSG(TrapBasedRangeChecks);
 100     FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
 101   }
 102 
 103   // On Power6 test for section size.
 104   if (PowerArchitecturePPC64 == 6) {
 105     determine_section_size();
 106   // TODO: PPC port } else {
 107   // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
 108   }
 109 
 110   MaxVectorSize = 8;
 111 #endif
 112 
 113   // Create and print feature-string.
 114   char buf[(num_features+1) * 16]; // Max 16 chars per feature.
 115   jio_snprintf(buf, sizeof(buf),
 116                "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
 117                (has_fsqrt()   ? " fsqrt"   : ""),
 118                (has_isel()    ? " isel"    : ""),
 119                (has_lxarxeh() ? " lxarxeh" : ""),
 120                (has_cmpb()    ? " cmpb"    : ""),
 121                //(has_mftgpr()? " mftgpr"  : ""),
 122                (has_popcntb() ? " popcntb" : ""),
 123                (has_popcntw() ? " popcntw" : ""),
 124                (has_fcfids()  ? " fcfids"  : ""),
 125                (has_vand()    ? " vand"    : ""),
 126                (has_lqarx()   ? " lqarx"   : ""),
 127                (has_vcipher() ? " aes"     : ""),
 128                (has_vpmsumb() ? " vpmsumb" : ""),
 129                (has_tcheck()  ? " tcheck"  : ""),
 130                (has_mfdscr()  ? " mfdscr"  : ""),
 131                (has_vsx()     ? " vsx"     : ""),
 132                (has_ldbrx()   ? " ldbrx"   : ""),
 133                (has_stdbrx()  ? " stdbrx"  : "")
 134                // Make sure number of %s matches num_features!
 135               );
 136   _features_string = os::strdup(buf);
 137   if (Verbose) {
 138     print_features();
 139   }
 140 
 141   // PPC64 supports 8-byte compare-exchange operations (see
 142   // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
 143   // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
 144   _supports_cx8 = true;
 145 
 146   // Used by C1.
 147   _supports_atomic_getset4 = true;
 148   _supports_atomic_getadd4 = true;
 149   _supports_atomic_getset8 = true;
 150   _supports_atomic_getadd8 = true;
 151 
 152   UseSSE = 0; // Only on x86 and x64
 153 
 154   intx cache_line_size = L1_data_cache_line_size();
 155 
 156   if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
 157 
 158   if (AllocatePrefetchStyle == 4) {
 159     AllocatePrefetchStepSize = cache_line_size; // Need exact value.
 160     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
 161     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
 162   } else {
 163     if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
 164     if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
 165     if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
 166   }
 167 
 168   assert(AllocatePrefetchLines > 0, "invalid value");
 169   if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
 170     AllocatePrefetchLines = 1; // Conservative value.
 171   }
 172 
 173   if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
 174     AllocatePrefetchStyle = 1; // Fall back if inappropriate.
 175   }
 176 
 177   assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
 178 
 179   // If defined(VM_LITTLE_ENDIAN) and running on Power8 or newer hardware,
 180   // the implementation uses the vector instructions available with Power8.
 181   // In all other cases, the implementation uses only generally available instructions.
 182   if (!UseCRC32Intrinsics) {
 183     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 184       FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
 185     }
 186   }
 187 
 188   // Implementation does not use any of the vector instructions available with Power8.
 189   // Their exploitation is still pending (aka "work in progress").
 190   if (!UseCRC32CIntrinsics) {
 191     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 192       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 193     }
 194   }
 195 
 196   // TODO: Provide implementation.
 197   if (UseAdler32Intrinsics) {
 198     warning("Adler32Intrinsics not available on this CPU.");
 199     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
 200   }
 201 
 202   // The AES intrinsic stubs require AES instruction support.
 203 #if defined(VM_LITTLE_ENDIAN)
 204   if (has_vcipher()) {
 205     if (FLAG_IS_DEFAULT(UseAES)) {
 206       UseAES = true;
 207     }
 208   } else if (UseAES) {
 209     if (!FLAG_IS_DEFAULT(UseAES))
 210       warning("AES instructions are not available on this CPU");
 211     FLAG_SET_DEFAULT(UseAES, false);
 212   }
 213 
 214   if (UseAES && has_vcipher()) {
 215     if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
 216       UseAESIntrinsics = true;
 217     }
 218   } else if (UseAESIntrinsics) {
 219     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 220       warning("AES intrinsics are not available on this CPU");
 221     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 222   }
 223 
 224 #else
 225   if (UseAES) {
 226     warning("AES instructions are not available on this CPU");
 227     FLAG_SET_DEFAULT(UseAES, false);
 228   }
 229   if (UseAESIntrinsics) {
 230     if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
 231       warning("AES intrinsics are not available on this CPU");
 232     FLAG_SET_DEFAULT(UseAESIntrinsics, false);
 233   }
 234 #endif
 235 
 236   if (UseAESCTRIntrinsics) {
 237     warning("AES/CTR intrinsics are not available on this CPU");
 238     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 239   }
 240 
 241   if (UseGHASHIntrinsics) {
 242     warning("GHASH intrinsics are not available on this CPU");
 243     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 244   }
 245 
 246   if (FLAG_IS_DEFAULT(UseFMA)) {
 247     FLAG_SET_DEFAULT(UseFMA, true);
 248   }
 249 
 250   if (UseSHA) {
 251     warning("SHA instructions are not available on this CPU");
 252     FLAG_SET_DEFAULT(UseSHA, false);
 253   }
 254   if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
 255     warning("SHA intrinsics are not available on this CPU");
 256     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 257     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 258     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 259   }
 260 
 261   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 262     UseMultiplyToLenIntrinsic = true;
 263   }
 264   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 265     UseMontgomeryMultiplyIntrinsic = true;
 266   }
 267   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 268     UseMontgomerySquareIntrinsic = true;
 269   }
 270 
 271   if (UseVectorizedMismatchIntrinsic) {
 272     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 273     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 274   }
 275 
 276 
 277   // Adjust RTM (Restricted Transactional Memory) flags.
 278   if (UseRTMLocking) {
 279     // If CPU or OS are too old:
 280     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 281     // setting during arguments processing. See use_biased_locking().
 282     // VM_Version_init() is executed after UseBiasedLocking is used
 283     // in Thread::allocate().
 284     if (!has_tcheck()) {
 285       vm_exit_during_initialization("RTM instructions are not available on this CPU");
 286     }
 287     bool os_too_old = true;
 288 #ifdef AIX
 289     // Actually, this is supported since AIX 7.1.. Unfortunately, this first
 290     // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
 291     // The Java property os.version, which is used in RTM tests to decide
 292     // whether the feature is available, only knows major and minor versions.
 293     // We don't want to change this property, as user code might depend on it.
 294     // So the tests can not check on subversion 3.30, and we only enable RTM
 295     // with AIX 7.2.
 296     if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
 297       os_too_old = false;
 298     }
 299 #endif
 300 #ifdef LINUX
 301     // At least Linux kernel 4.2, as the problematic behavior of syscalls
 302     // being called in the middle of a transaction has been addressed.
 303     // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894
 304     // in Linux kernel source tree: https://goo.gl/Kc5i7A
 305     if (os::Linux::os_version_is_known()) {
 306       if (os::Linux::os_version() >= 0x040200)
 307         os_too_old = false;
 308     } else {
 309       vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown.");
 310     }
 311 #endif
 312     if (os_too_old) {
 313       vm_exit_during_initialization("RTM is not supported on this OS version.");
 314     }
 315   }
 316 
 317   if (UseRTMLocking) {
 318 #if INCLUDE_RTM_OPT
 319     if (!UnlockExperimentalVMOptions) {
 320       vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
 321                                     "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
 322     } else {
 323       warning("UseRTMLocking is only available as experimental option on this platform.");
 324     }
 325     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
 326       // RTM locking should be used only for applications with
 327       // high lock contention. For now we do not use it by default.
 328       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
 329     }
 330 #else
 331     // Only C2 does RTM locking optimization.
 332     // Can't continue because UseRTMLocking affects UseBiasedLocking flag
 333     // setting during arguments processing. See use_biased_locking().
 334     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
 335 #endif
 336   } else { // !UseRTMLocking
 337     if (UseRTMForStackLocks) {
 338       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
 339         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
 340       }
 341       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
 342     }
 343     if (UseRTMDeopt) {
 344       FLAG_SET_DEFAULT(UseRTMDeopt, false);
 345     }
 346     if (PrintPreciseRTMLockingStatistics) {
 347       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
 348     }
 349   }
 350 
 351   // This machine allows unaligned memory accesses
 352   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
 353     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
 354   }
 355 }
 356 
 357 bool VM_Version::use_biased_locking() {
 358 #if INCLUDE_RTM_OPT
 359   // RTM locking is most useful when there is high lock contention and
 360   // low data contention. With high lock contention the lock is usually
 361   // inflated and biased locking is not suitable for that case.
 362   // RTM locking code requires that biased locking is off.
 363   // Note: we can't switch off UseBiasedLocking in get_processor_features()
 364   // because it is used by Thread::allocate() which is called before
 365   // VM_Version::initialize().
 366   if (UseRTMLocking && UseBiasedLocking) {
 367     if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
 368       FLAG_SET_DEFAULT(UseBiasedLocking, false);
 369     } else {
 370       warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
 371       UseBiasedLocking = false;
 372     }
 373   }
 374 #endif
 375   return UseBiasedLocking;
 376 }
 377 
 378 void VM_Version::print_features() {
 379   tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
 380 }
 381 
 382 #ifdef COMPILER2
 383 // Determine section size on power6: If section size is 8 instructions,
 384 // there should be a difference between the two testloops of ~15 %. If
 385 // no difference is detected the section is assumed to be 32 instructions.
 386 void VM_Version::determine_section_size() {
 387 
 388   int unroll = 80;
 389 
 390   const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
 391 
 392   // Allocate space for the code.
 393   ResourceMark rm;
 394   CodeBuffer cb("detect_section_size", code_size, 0);
 395   MacroAssembler* a = new MacroAssembler(&cb);
 396 
 397   uint32_t *code = (uint32_t *)a->pc();
 398   // Emit code.
 399   void (*test1)() = (void(*)())(void *)a->function_entry();
 400 
 401   Label l1;
 402 
 403   a->li(R4, 1);
 404   a->sldi(R4, R4, 28);
 405   a->b(l1);
 406   a->align(CodeEntryAlignment);
 407 
 408   a->bind(l1);
 409 
 410   for (int i = 0; i < unroll; i++) {
 411     // Schleife 1
 412     // ------- sector 0 ------------
 413     // ;; 0
 414     a->nop();                   // 1
 415     a->fpnop0();                // 2
 416     a->fpnop1();                // 3
 417     a->addi(R4,R4, -1); // 4
 418 
 419     // ;;  1
 420     a->nop();                   // 5
 421     a->fmr(F6, F6);             // 6
 422     a->fmr(F7, F7);             // 7
 423     a->endgroup();              // 8
 424     // ------- sector 8 ------------
 425 
 426     // ;;  2
 427     a->nop();                   // 9
 428     a->nop();                   // 10
 429     a->fmr(F8, F8);             // 11
 430     a->fmr(F9, F9);             // 12
 431 
 432     // ;;  3
 433     a->nop();                   // 13
 434     a->fmr(F10, F10);           // 14
 435     a->fmr(F11, F11);           // 15
 436     a->endgroup();              // 16
 437     // -------- sector 16 -------------
 438 
 439     // ;;  4
 440     a->nop();                   // 17
 441     a->nop();                   // 18
 442     a->fmr(F15, F15);           // 19
 443     a->fmr(F16, F16);           // 20
 444 
 445     // ;;  5
 446     a->nop();                   // 21
 447     a->fmr(F17, F17);           // 22
 448     a->fmr(F18, F18);           // 23
 449     a->endgroup();              // 24
 450     // ------- sector 24  ------------
 451 
 452     // ;;  6
 453     a->nop();                   // 25
 454     a->nop();                   // 26
 455     a->fmr(F19, F19);           // 27
 456     a->fmr(F20, F20);           // 28
 457 
 458     // ;;  7
 459     a->nop();                   // 29
 460     a->fmr(F21, F21);           // 30
 461     a->fmr(F22, F22);           // 31
 462     a->brnop0();                // 32
 463 
 464     // ------- sector 32 ------------
 465   }
 466 
 467   // ;; 8
 468   a->cmpdi(CCR0, R4, unroll);   // 33
 469   a->bge(CCR0, l1);             // 34
 470   a->blr();
 471 
 472   // Emit code.
 473   void (*test2)() = (void(*)())(void *)a->function_entry();
 474   // uint32_t *code = (uint32_t *)a->pc();
 475 
 476   Label l2;
 477 
 478   a->li(R4, 1);
 479   a->sldi(R4, R4, 28);
 480   a->b(l2);
 481   a->align(CodeEntryAlignment);
 482 
 483   a->bind(l2);
 484 
 485   for (int i = 0; i < unroll; i++) {
 486     // Schleife 2
 487     // ------- sector 0 ------------
 488     // ;; 0
 489     a->brnop0();                  // 1
 490     a->nop();                     // 2
 491     //a->cmpdi(CCR0, R4, unroll);
 492     a->fpnop0();                  // 3
 493     a->fpnop1();                  // 4
 494     a->addi(R4,R4, -1);           // 5
 495 
 496     // ;; 1
 497 
 498     a->nop();                     // 6
 499     a->fmr(F6, F6);               // 7
 500     a->fmr(F7, F7);               // 8
 501     // ------- sector 8 ---------------
 502 
 503     // ;; 2
 504     a->endgroup();                // 9
 505 
 506     // ;; 3
 507     a->nop();                     // 10
 508     a->nop();                     // 11
 509     a->fmr(F8, F8);               // 12
 510 
 511     // ;; 4
 512     a->fmr(F9, F9);               // 13
 513     a->nop();                     // 14
 514     a->fmr(F10, F10);             // 15
 515 
 516     // ;; 5
 517     a->fmr(F11, F11);             // 16
 518     // -------- sector 16 -------------
 519 
 520     // ;; 6
 521     a->endgroup();                // 17
 522 
 523     // ;; 7
 524     a->nop();                     // 18
 525     a->nop();                     // 19
 526     a->fmr(F15, F15);             // 20
 527 
 528     // ;; 8
 529     a->fmr(F16, F16);             // 21
 530     a->nop();                     // 22
 531     a->fmr(F17, F17);             // 23
 532 
 533     // ;; 9
 534     a->fmr(F18, F18);             // 24
 535     // -------- sector 24 -------------
 536 
 537     // ;; 10
 538     a->endgroup();                // 25
 539 
 540     // ;; 11
 541     a->nop();                     // 26
 542     a->nop();                     // 27
 543     a->fmr(F19, F19);             // 28
 544 
 545     // ;; 12
 546     a->fmr(F20, F20);             // 29
 547     a->nop();                     // 30
 548     a->fmr(F21, F21);             // 31
 549 
 550     // ;; 13
 551     a->fmr(F22, F22);             // 32
 552   }
 553 
 554   // -------- sector 32 -------------
 555   // ;; 14
 556   a->cmpdi(CCR0, R4, unroll); // 33
 557   a->bge(CCR0, l2);           // 34
 558 
 559   a->blr();
 560   uint32_t *code_end = (uint32_t *)a->pc();
 561   a->flush();
 562 
 563   double loop1_seconds,loop2_seconds, rel_diff;
 564   uint64_t start1, stop1;
 565 
 566   start1 = os::current_thread_cpu_time(false);
 567   (*test1)();
 568   stop1 = os::current_thread_cpu_time(false);
 569   loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
 570 
 571 
 572   start1 = os::current_thread_cpu_time(false);
 573   (*test2)();
 574   stop1 = os::current_thread_cpu_time(false);
 575 
 576   loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
 577 
 578   rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
 579 
 580   if (PrintAssembly) {
 581     ttyLocker ttyl;
 582     tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
 583     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 584     tty->print_cr("Time loop1 :%f", loop1_seconds);
 585     tty->print_cr("Time loop2 :%f", loop2_seconds);
 586     tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
 587 
 588     if (rel_diff > 12.0) {
 589       tty->print_cr("Section Size 8 Instructions");
 590     } else{
 591       tty->print_cr("Section Size 32 Instructions or Power5");
 592     }
 593   }
 594 
 595 #if 0 // TODO: PPC port
 596   // Set sector size (if not set explicitly).
 597   if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
 598     if (rel_diff > 12.0) {
 599       PdScheduling::power6SectorSize = 0x20;
 600     } else {
 601       PdScheduling::power6SectorSize = 0x80;
 602     }
 603   } else if (Power6SectorSize128PPC64) {
 604     PdScheduling::power6SectorSize = 0x80;
 605   } else {
 606     PdScheduling::power6SectorSize = 0x20;
 607   }
 608 #endif
 609   if (UsePower6SchedulerPPC64) Unimplemented();
 610 }
 611 #endif // COMPILER2
 612 
 613 void VM_Version::determine_features() {
 614 #if defined(ABI_ELFv2)
 615   // 1 InstWord per call for the blr instruction.
 616   const int code_size = (num_features+1+2*1)*BytesPerInstWord;
 617 #else
 618   // 7 InstWords for each call (function descriptor + blr instruction).
 619   const int code_size = (num_features+1+2*7)*BytesPerInstWord;
 620 #endif
 621   int features = 0;
 622 
 623   // create test area
 624   enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
 625   char test_area[BUFFER_SIZE];
 626   char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
 627 
 628   // Allocate space for the code.
 629   ResourceMark rm;
 630   CodeBuffer cb("detect_cpu_features", code_size, 0);
 631   MacroAssembler* a = new MacroAssembler(&cb);
 632 
 633   // Must be set to true so we can generate the test code.
 634   _features = VM_Version::all_features_m;
 635 
 636   // Emit code.
 637   void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
 638   uint32_t *code = (uint32_t *)a->pc();
 639   // Don't use R0 in ldarx.
 640   // Keep R3_ARG1 unmodified, it contains &field (see below).
 641   // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
 642   a->fsqrt(F3, F4);                            // code[0]  -> fsqrt_m
 643   a->fsqrts(F3, F4);                           // code[1]  -> fsqrts_m
 644   a->isel(R7, R5, R6, 0);                      // code[2]  -> isel_m
 645   a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3]  -> lxarx_m
 646   a->cmpb(R7, R5, R6);                         // code[4]  -> cmpb
 647   a->popcntb(R7, R5);                          // code[5]  -> popcntb
 648   a->popcntw(R7, R5);                          // code[6]  -> popcntw
 649   a->fcfids(F3, F4);                           // code[7]  -> fcfids
 650   a->vand(VR0, VR0, VR0);                      // code[8]  -> vand
 651   // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
 652   a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9]  -> lqarx_m
 653   a->vcipher(VR0, VR1, VR2);                   // code[10] -> vcipher
 654   a->vpmsumb(VR0, VR1, VR2);                   // code[11] -> vpmsumb
 655   a->tcheck(0);                                // code[12] -> tcheck
 656   a->mfdscr(R0);                               // code[13] -> mfdscr
 657   a->lxvd2x(VSR0, R3_ARG1);                    // code[14] -> vsx
 658   a->ldbrx(R7, R3_ARG1, R4_ARG2);              // code[15] -> ldbrx
 659   a->stdbrx(R7, R3_ARG1, R4_ARG2);             // code[16] -> stdbrx
 660   a->blr();
 661 
 662   // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
 663   void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
 664   a->dcbz(R3_ARG1); // R3_ARG1 = addr
 665   a->blr();
 666 
 667   uint32_t *code_end = (uint32_t *)a->pc();
 668   a->flush();
 669   _features = VM_Version::unknown_m;
 670 
 671   // Print the detection code.
 672   if (PrintAssembly) {
 673     ttyLocker ttyl;
 674     tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
 675     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 676   }
 677 
 678   // Measure cache line size.
 679   memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
 680   (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
 681   int count = 0; // count zeroed bytes
 682   for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
 683   guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
 684   _L1_data_cache_line_size = count;
 685 
 686   // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
 687   VM_Version::_is_determine_features_test_running = true;
 688   // We must align the first argument to 16 bytes because of the lqarx check.
 689   (*test)(align_up((address)mid_of_test_area, 16), 0);
 690   VM_Version::_is_determine_features_test_running = false;
 691 
 692   // determine which instructions are legal.
 693   int feature_cntr = 0;
 694   if (code[feature_cntr++]) features |= fsqrt_m;
 695   if (code[feature_cntr++]) features |= fsqrts_m;
 696   if (code[feature_cntr++]) features |= isel_m;
 697   if (code[feature_cntr++]) features |= lxarxeh_m;
 698   if (code[feature_cntr++]) features |= cmpb_m;
 699   if (code[feature_cntr++]) features |= popcntb_m;
 700   if (code[feature_cntr++]) features |= popcntw_m;
 701   if (code[feature_cntr++]) features |= fcfids_m;
 702   if (code[feature_cntr++]) features |= vand_m;
 703   if (code[feature_cntr++]) features |= lqarx_m;
 704   if (code[feature_cntr++]) features |= vcipher_m;
 705   if (code[feature_cntr++]) features |= vpmsumb_m;
 706   if (code[feature_cntr++]) features |= tcheck_m;
 707   if (code[feature_cntr++]) features |= mfdscr_m;
 708   if (code[feature_cntr++]) features |= vsx_m;
 709   if (code[feature_cntr++]) features |= ldbrx_m;
 710   if (code[feature_cntr++]) features |= stdbrx_m;
 711 
 712   // Print the detection code.
 713   if (PrintAssembly) {
 714     ttyLocker ttyl;
 715     tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
 716     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 717   }
 718 
 719   _features = features;
 720 }
 721 
 722 // Power 8: Configure Data Stream Control Register.
 723 void VM_Version::config_dscr() {
 724   // 7 InstWords for each call (function descriptor + blr instruction).
 725   const int code_size = (2+2*7)*BytesPerInstWord;
 726 
 727   // Allocate space for the code.
 728   ResourceMark rm;
 729   CodeBuffer cb("config_dscr", code_size, 0);
 730   MacroAssembler* a = new MacroAssembler(&cb);
 731 
 732   // Emit code.
 733   uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
 734   uint32_t *code = (uint32_t *)a->pc();
 735   a->mfdscr(R3);
 736   a->blr();
 737 
 738   void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
 739   a->mtdscr(R3);
 740   a->blr();
 741 
 742   uint32_t *code_end = (uint32_t *)a->pc();
 743   a->flush();
 744 
 745   // Print the detection code.
 746   if (PrintAssembly) {
 747     ttyLocker ttyl;
 748     tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
 749     Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
 750   }
 751 
 752   // Apply the configuration if needed.
 753   _dscr_val = (*get_dscr)();
 754   if (Verbose) {
 755     tty->print_cr("dscr value was 0x%lx" , _dscr_val);
 756   }
 757   bool change_requested = false;
 758   if (DSCR_PPC64 != (uintx)-1) {
 759     _dscr_val = DSCR_PPC64;
 760     change_requested = true;
 761   }
 762   if (DSCR_DPFD_PPC64 <= 7) {
 763     uint64_t mask = 0x7;
 764     if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
 765       _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
 766       change_requested = true;
 767     }
 768   }
 769   if (DSCR_URG_PPC64 <= 7) {
 770     uint64_t mask = 0x7 << 6;
 771     if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
 772       _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
 773       change_requested = true;
 774     }
 775   }
 776   if (change_requested) {
 777     (*set_dscr)(_dscr_val);
 778     if (Verbose) {
 779       tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
 780     }
 781   }
 782 }
 783 
 784 static uint64_t saved_features = 0;
 785 
 786 void VM_Version::allow_all() {
 787   saved_features = _features;
 788   _features      = all_features_m;
 789 }
 790 
 791 void VM_Version::revert() {
 792   _features = saved_features;
 793 }