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src/cpu/ppc/vm/assembler_ppc.hpp

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rev 13550 : 8185979: PPC64: Implement SHA2 intrinsic
Reviewed-by: mdoerr, goetz
Contributed-by: Bruno Rosa <bruno.rosa@eldorado.org.br>, Gustavo Serra Scalet <gustavo.scalet@eldorado.org.br>, Igor Nunes <igor.nunes@eldorado.org.br>, Martin Doerr <martin.doerr@sap.com>

*** 2172,2182 **** inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); inline void vsbox( VectorRegister d, VectorRegister a); // SHA (introduced with Power 8) ! // Not yet implemented. // Vector Binary Polynomial Multiplication (introduced with Power 8) inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); --- 2172,2183 ---- inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); inline void vsbox( VectorRegister d, VectorRegister a); // SHA (introduced with Power 8) ! inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six); ! inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six); // Vector Binary Polynomial Multiplication (introduced with Power 8) inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b);
*** 2283,2292 **** --- 2284,2297 ---- inline void stvx( VectorRegister d, Register s2); inline void stvxl( VectorRegister d, Register s2); inline void lvsl( VectorRegister d, Register s2); inline void lvsr( VectorRegister d, Register s2); + // Endianess specific concatenation of 2 loaded vectors. + inline void load_perm(VectorRegister perm, Register addr); + inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm); + // RegisterOrConstant versions. // These emitters choose between the versions using two registers and // those with register and immediate, depending on the content of roc. // If the constant is not encodable as immediate, instructions to // load the constant are emitted beforehand. Store instructions need a
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