1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2017, SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "prims/jvm.h"
32 #include "runtime/java.hpp"
33 #include "runtime/os.hpp"
34 #include "runtime/stubCodeGenerator.hpp"
35 #include "utilities/align.hpp"
36 #include "utilities/defaultStream.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "vm_version_ppc.hpp"
39
40 # include <sys/sysinfo.h>
41
42 bool VM_Version::_is_determine_features_test_running = false;
43 uint64_t VM_Version::_dscr_val = 0;
44
45 #define MSG(flag) \
46 if (flag && !FLAG_IS_DEFAULT(flag)) \
47 jio_fprintf(defaultStream::error_stream(), \
48 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
49 " -XX:+" #flag " will be disabled!\n");
50
51 void VM_Version::initialize() {
52
53 // Test which instructions are supported and measure cache line size.
54 determine_features();
55
56 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
57 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
58 if (VM_Version::has_lqarx()) {
59 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
60 } else if (VM_Version::has_popcntw()) {
61 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
62 } else if (VM_Version::has_cmpb()) {
63 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
64 } else if (VM_Version::has_popcntb()) {
65 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
66 } else {
67 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
68 }
69 }
70
71 bool PowerArchitecturePPC64_ok = false;
72 switch (PowerArchitecturePPC64) {
73 case 8: if (!VM_Version::has_lqarx() ) break;
74 case 7: if (!VM_Version::has_popcntw()) break;
75 case 6: if (!VM_Version::has_cmpb() ) break;
76 case 5: if (!VM_Version::has_popcntb()) break;
77 case 0: PowerArchitecturePPC64_ok = true; break;
78 default: break;
79 }
80 guarantee(PowerArchitecturePPC64_ok, "PowerArchitecturePPC64 cannot be set to "
81 UINTX_FORMAT " on this machine", PowerArchitecturePPC64);
82
83 // Power 8: Configure Data Stream Control Register.
84 if (PowerArchitecturePPC64 >= 8 && has_mfdscr()) {
85 config_dscr();
86 }
87
88 if (!UseSIGTRAP) {
89 MSG(TrapBasedICMissChecks);
90 MSG(TrapBasedNotEntrantChecks);
91 MSG(TrapBasedNullChecks);
92 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
93 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
94 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
95 }
96
97 #ifdef COMPILER2
98 if (!UseSIGTRAP) {
99 MSG(TrapBasedRangeChecks);
100 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
101 }
102
103 // On Power6 test for section size.
104 if (PowerArchitecturePPC64 == 6) {
105 determine_section_size();
106 // TODO: PPC port } else {
107 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
108 }
109
110 if (PowerArchitecturePPC64 >= 8) {
111 if (FLAG_IS_DEFAULT(SuperwordUseVSX)) {
112 FLAG_SET_ERGO(bool, SuperwordUseVSX, true);
113 }
114 } else {
115 if (SuperwordUseVSX) {
116 warning("SuperwordUseVSX specified, but needs at least Power8.");
117 FLAG_SET_DEFAULT(SuperwordUseVSX, false);
118 }
119 }
120 MaxVectorSize = SuperwordUseVSX ? 16 : 8;
121 #endif
122
123 // Create and print feature-string.
124 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
125 jio_snprintf(buf, sizeof(buf),
126 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
127 (has_fsqrt() ? " fsqrt" : ""),
128 (has_isel() ? " isel" : ""),
129 (has_lxarxeh() ? " lxarxeh" : ""),
130 (has_cmpb() ? " cmpb" : ""),
131 //(has_mftgpr()? " mftgpr" : ""),
132 (has_popcntb() ? " popcntb" : ""),
133 (has_popcntw() ? " popcntw" : ""),
134 (has_fcfids() ? " fcfids" : ""),
135 (has_vand() ? " vand" : ""),
136 (has_lqarx() ? " lqarx" : ""),
137 (has_vcipher() ? " aes" : ""),
138 (has_vpmsumb() ? " vpmsumb" : ""),
139 (has_tcheck() ? " tcheck" : ""),
140 (has_mfdscr() ? " mfdscr" : ""),
141 (has_vsx() ? " vsx" : ""),
142 (has_ldbrx() ? " ldbrx" : ""),
143 (has_stdbrx() ? " stdbrx" : ""),
144 (has_vshasig() ? " sha" : "")
145 // Make sure number of %s matches num_features!
146 );
147 _features_string = os::strdup(buf);
148 if (Verbose) {
149 print_features();
150 }
151
152 // PPC64 supports 8-byte compare-exchange operations (see
153 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
154 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
155 _supports_cx8 = true;
156
157 // Used by C1.
158 _supports_atomic_getset4 = true;
159 _supports_atomic_getadd4 = true;
160 _supports_atomic_getset8 = true;
161 _supports_atomic_getadd8 = true;
162
163 UseSSE = 0; // Only on x86 and x64
164
165 intx cache_line_size = L1_data_cache_line_size();
166
167 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
168
169 if (AllocatePrefetchStyle == 4) {
170 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
171 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
172 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
173 } else {
174 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
175 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
176 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
177 }
178
179 assert(AllocatePrefetchLines > 0, "invalid value");
180 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
181 AllocatePrefetchLines = 1; // Conservative value.
182 }
183
184 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
185 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
186 }
187
188 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
189
190 // If defined(VM_LITTLE_ENDIAN) and running on Power8 or newer hardware,
191 // the implementation uses the vector instructions available with Power8.
192 // In all other cases, the implementation uses only generally available instructions.
193 if (!UseCRC32Intrinsics) {
194 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
195 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
196 }
197 }
198
199 // Implementation does not use any of the vector instructions available with Power8.
200 // Their exploitation is still pending (aka "work in progress").
201 if (!UseCRC32CIntrinsics) {
202 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
203 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
204 }
205 }
206
207 // TODO: Provide implementation.
208 if (UseAdler32Intrinsics) {
209 warning("Adler32Intrinsics not available on this CPU.");
210 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
211 }
212
213 // The AES intrinsic stubs require AES instruction support.
214 #if defined(VM_LITTLE_ENDIAN)
215 if (has_vcipher()) {
216 if (FLAG_IS_DEFAULT(UseAES)) {
217 UseAES = true;
218 }
219 } else if (UseAES) {
220 if (!FLAG_IS_DEFAULT(UseAES))
221 warning("AES instructions are not available on this CPU");
222 FLAG_SET_DEFAULT(UseAES, false);
223 }
224
225 if (UseAES && has_vcipher()) {
226 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
227 UseAESIntrinsics = true;
228 }
229 } else if (UseAESIntrinsics) {
230 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
231 warning("AES intrinsics are not available on this CPU");
232 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
233 }
234
235 #else
236 if (UseAES) {
237 warning("AES instructions are not available on this CPU");
238 FLAG_SET_DEFAULT(UseAES, false);
239 }
240 if (UseAESIntrinsics) {
241 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
242 warning("AES intrinsics are not available on this CPU");
243 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
244 }
245 #endif
246
247 if (UseAESCTRIntrinsics) {
248 warning("AES/CTR intrinsics are not available on this CPU");
249 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
250 }
251
252 if (UseGHASHIntrinsics) {
253 warning("GHASH intrinsics are not available on this CPU");
254 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
255 }
256
257 if (FLAG_IS_DEFAULT(UseFMA)) {
258 FLAG_SET_DEFAULT(UseFMA, true);
259 }
260
261 if (has_vshasig()) {
262 if (FLAG_IS_DEFAULT(UseSHA)) {
263 UseSHA = true;
264 }
265 } else if (UseSHA) {
266 if (!FLAG_IS_DEFAULT(UseSHA))
267 warning("SHA instructions are not available on this CPU");
268 FLAG_SET_DEFAULT(UseSHA, false);
269 }
270
271 if (UseSHA1Intrinsics) {
272 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
273 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
274 }
275
276 if (UseSHA && has_vshasig()) {
277 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
278 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
279 }
280 } else if (UseSHA256Intrinsics) {
281 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
282 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
283 }
284
285 if (UseSHA && has_vshasig()) {
286 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
287 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
288 }
289 } else if (UseSHA512Intrinsics) {
290 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
291 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
292 }
293
294 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
295 FLAG_SET_DEFAULT(UseSHA, false);
296 }
297
298 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
299 UseSquareToLenIntrinsic = true;
300 }
301 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
302 UseMulAddIntrinsic = true;
303 }
304 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
305 UseMultiplyToLenIntrinsic = true;
306 }
307 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
308 UseMontgomeryMultiplyIntrinsic = true;
309 }
310 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
311 UseMontgomerySquareIntrinsic = true;
312 }
313
314 if (UseVectorizedMismatchIntrinsic) {
315 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
316 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
317 }
318
319
320 // Adjust RTM (Restricted Transactional Memory) flags.
321 if (UseRTMLocking) {
322 // If CPU or OS are too old:
323 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
324 // setting during arguments processing. See use_biased_locking().
325 // VM_Version_init() is executed after UseBiasedLocking is used
326 // in Thread::allocate().
327 if (!has_tcheck()) {
328 vm_exit_during_initialization("RTM instructions are not available on this CPU");
329 }
330 bool os_too_old = true;
331 #ifdef AIX
332 // Actually, this is supported since AIX 7.1.. Unfortunately, this first
333 // contained bugs, so that it can only be enabled after AIX 7.1.3.30.
334 // The Java property os.version, which is used in RTM tests to decide
335 // whether the feature is available, only knows major and minor versions.
336 // We don't want to change this property, as user code might depend on it.
337 // So the tests can not check on subversion 3.30, and we only enable RTM
338 // with AIX 7.2.
339 if (os::Aix::os_version() >= 0x07020000) { // At least AIX 7.2.
340 os_too_old = false;
341 }
342 #endif
343 #ifdef LINUX
344 // At least Linux kernel 4.2, as the problematic behavior of syscalls
345 // being called in the middle of a transaction has been addressed.
346 // Please, refer to commit b4b56f9ecab40f3b4ef53e130c9f6663be491894
347 // in Linux kernel source tree: https://goo.gl/Kc5i7A
348 if (os::Linux::os_version_is_known()) {
349 if (os::Linux::os_version() >= 0x040200)
350 os_too_old = false;
351 } else {
352 vm_exit_during_initialization("RTM can not be enabled: kernel version is unknown.");
353 }
354 #endif
355 if (os_too_old) {
356 vm_exit_during_initialization("RTM is not supported on this OS version.");
357 }
358 }
359
360 if (UseRTMLocking) {
361 #if INCLUDE_RTM_OPT
362 if (!UnlockExperimentalVMOptions) {
363 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
364 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
365 } else {
366 warning("UseRTMLocking is only available as experimental option on this platform.");
367 }
368 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
369 // RTM locking should be used only for applications with
370 // high lock contention. For now we do not use it by default.
371 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
372 }
373 #else
374 // Only C2 does RTM locking optimization.
375 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
376 // setting during arguments processing. See use_biased_locking().
377 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
378 #endif
379 } else { // !UseRTMLocking
380 if (UseRTMForStackLocks) {
381 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
382 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
383 }
384 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
385 }
386 if (UseRTMDeopt) {
387 FLAG_SET_DEFAULT(UseRTMDeopt, false);
388 }
389 if (PrintPreciseRTMLockingStatistics) {
390 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
391 }
392 }
393
394 // This machine allows unaligned memory accesses
395 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
396 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
397 }
398 }
399
400 bool VM_Version::use_biased_locking() {
401 #if INCLUDE_RTM_OPT
402 // RTM locking is most useful when there is high lock contention and
403 // low data contention. With high lock contention the lock is usually
404 // inflated and biased locking is not suitable for that case.
405 // RTM locking code requires that biased locking is off.
406 // Note: we can't switch off UseBiasedLocking in get_processor_features()
407 // because it is used by Thread::allocate() which is called before
408 // VM_Version::initialize().
409 if (UseRTMLocking && UseBiasedLocking) {
410 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
411 FLAG_SET_DEFAULT(UseBiasedLocking, false);
412 } else {
413 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
414 UseBiasedLocking = false;
415 }
416 }
417 #endif
418 return UseBiasedLocking;
419 }
420
421 void VM_Version::print_features() {
422 tty->print_cr("Version: %s L1_data_cache_line_size=%d", features_string(), L1_data_cache_line_size());
423 }
424
425 #ifdef COMPILER2
426 // Determine section size on power6: If section size is 8 instructions,
427 // there should be a difference between the two testloops of ~15 %. If
428 // no difference is detected the section is assumed to be 32 instructions.
429 void VM_Version::determine_section_size() {
430
431 int unroll = 80;
432
433 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
434
435 // Allocate space for the code.
436 ResourceMark rm;
437 CodeBuffer cb("detect_section_size", code_size, 0);
438 MacroAssembler* a = new MacroAssembler(&cb);
439
440 uint32_t *code = (uint32_t *)a->pc();
441 // Emit code.
442 void (*test1)() = (void(*)())(void *)a->function_entry();
443
444 Label l1;
445
446 a->li(R4, 1);
447 a->sldi(R4, R4, 28);
448 a->b(l1);
449 a->align(CodeEntryAlignment);
450
451 a->bind(l1);
452
453 for (int i = 0; i < unroll; i++) {
454 // Schleife 1
455 // ------- sector 0 ------------
456 // ;; 0
457 a->nop(); // 1
458 a->fpnop0(); // 2
459 a->fpnop1(); // 3
460 a->addi(R4,R4, -1); // 4
461
462 // ;; 1
463 a->nop(); // 5
464 a->fmr(F6, F6); // 6
465 a->fmr(F7, F7); // 7
466 a->endgroup(); // 8
467 // ------- sector 8 ------------
468
469 // ;; 2
470 a->nop(); // 9
471 a->nop(); // 10
472 a->fmr(F8, F8); // 11
473 a->fmr(F9, F9); // 12
474
475 // ;; 3
476 a->nop(); // 13
477 a->fmr(F10, F10); // 14
478 a->fmr(F11, F11); // 15
479 a->endgroup(); // 16
480 // -------- sector 16 -------------
481
482 // ;; 4
483 a->nop(); // 17
484 a->nop(); // 18
485 a->fmr(F15, F15); // 19
486 a->fmr(F16, F16); // 20
487
488 // ;; 5
489 a->nop(); // 21
490 a->fmr(F17, F17); // 22
491 a->fmr(F18, F18); // 23
492 a->endgroup(); // 24
493 // ------- sector 24 ------------
494
495 // ;; 6
496 a->nop(); // 25
497 a->nop(); // 26
498 a->fmr(F19, F19); // 27
499 a->fmr(F20, F20); // 28
500
501 // ;; 7
502 a->nop(); // 29
503 a->fmr(F21, F21); // 30
504 a->fmr(F22, F22); // 31
505 a->brnop0(); // 32
506
507 // ------- sector 32 ------------
508 }
509
510 // ;; 8
511 a->cmpdi(CCR0, R4, unroll); // 33
512 a->bge(CCR0, l1); // 34
513 a->blr();
514
515 // Emit code.
516 void (*test2)() = (void(*)())(void *)a->function_entry();
517 // uint32_t *code = (uint32_t *)a->pc();
518
519 Label l2;
520
521 a->li(R4, 1);
522 a->sldi(R4, R4, 28);
523 a->b(l2);
524 a->align(CodeEntryAlignment);
525
526 a->bind(l2);
527
528 for (int i = 0; i < unroll; i++) {
529 // Schleife 2
530 // ------- sector 0 ------------
531 // ;; 0
532 a->brnop0(); // 1
533 a->nop(); // 2
534 //a->cmpdi(CCR0, R4, unroll);
535 a->fpnop0(); // 3
536 a->fpnop1(); // 4
537 a->addi(R4,R4, -1); // 5
538
539 // ;; 1
540
541 a->nop(); // 6
542 a->fmr(F6, F6); // 7
543 a->fmr(F7, F7); // 8
544 // ------- sector 8 ---------------
545
546 // ;; 2
547 a->endgroup(); // 9
548
549 // ;; 3
550 a->nop(); // 10
551 a->nop(); // 11
552 a->fmr(F8, F8); // 12
553
554 // ;; 4
555 a->fmr(F9, F9); // 13
556 a->nop(); // 14
557 a->fmr(F10, F10); // 15
558
559 // ;; 5
560 a->fmr(F11, F11); // 16
561 // -------- sector 16 -------------
562
563 // ;; 6
564 a->endgroup(); // 17
565
566 // ;; 7
567 a->nop(); // 18
568 a->nop(); // 19
569 a->fmr(F15, F15); // 20
570
571 // ;; 8
572 a->fmr(F16, F16); // 21
573 a->nop(); // 22
574 a->fmr(F17, F17); // 23
575
576 // ;; 9
577 a->fmr(F18, F18); // 24
578 // -------- sector 24 -------------
579
580 // ;; 10
581 a->endgroup(); // 25
582
583 // ;; 11
584 a->nop(); // 26
585 a->nop(); // 27
586 a->fmr(F19, F19); // 28
587
588 // ;; 12
589 a->fmr(F20, F20); // 29
590 a->nop(); // 30
591 a->fmr(F21, F21); // 31
592
593 // ;; 13
594 a->fmr(F22, F22); // 32
595 }
596
597 // -------- sector 32 -------------
598 // ;; 14
599 a->cmpdi(CCR0, R4, unroll); // 33
600 a->bge(CCR0, l2); // 34
601
602 a->blr();
603 uint32_t *code_end = (uint32_t *)a->pc();
604 a->flush();
605
606 double loop1_seconds,loop2_seconds, rel_diff;
607 uint64_t start1, stop1;
608
609 start1 = os::current_thread_cpu_time(false);
610 (*test1)();
611 stop1 = os::current_thread_cpu_time(false);
612 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
613
614
615 start1 = os::current_thread_cpu_time(false);
616 (*test2)();
617 stop1 = os::current_thread_cpu_time(false);
618
619 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
620
621 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
622
623 if (PrintAssembly) {
624 ttyLocker ttyl;
625 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
626 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
627 tty->print_cr("Time loop1 :%f", loop1_seconds);
628 tty->print_cr("Time loop2 :%f", loop2_seconds);
629 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
630
631 if (rel_diff > 12.0) {
632 tty->print_cr("Section Size 8 Instructions");
633 } else{
634 tty->print_cr("Section Size 32 Instructions or Power5");
635 }
636 }
637
638 #if 0 // TODO: PPC port
639 // Set sector size (if not set explicitly).
640 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
641 if (rel_diff > 12.0) {
642 PdScheduling::power6SectorSize = 0x20;
643 } else {
644 PdScheduling::power6SectorSize = 0x80;
645 }
646 } else if (Power6SectorSize128PPC64) {
647 PdScheduling::power6SectorSize = 0x80;
648 } else {
649 PdScheduling::power6SectorSize = 0x20;
650 }
651 #endif
652 if (UsePower6SchedulerPPC64) Unimplemented();
653 }
654 #endif // COMPILER2
655
656 void VM_Version::determine_features() {
657 #if defined(ABI_ELFv2)
658 // 1 InstWord per call for the blr instruction.
659 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
660 #else
661 // 7 InstWords for each call (function descriptor + blr instruction).
662 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
663 #endif
664 int features = 0;
665
666 // create test area
667 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
668 char test_area[BUFFER_SIZE];
669 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
670
671 // Allocate space for the code.
672 ResourceMark rm;
673 CodeBuffer cb("detect_cpu_features", code_size, 0);
674 MacroAssembler* a = new MacroAssembler(&cb);
675
676 // Must be set to true so we can generate the test code.
677 _features = VM_Version::all_features_m;
678
679 // Emit code.
680 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
681 uint32_t *code = (uint32_t *)a->pc();
682 // Don't use R0 in ldarx.
683 // Keep R3_ARG1 unmodified, it contains &field (see below).
684 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
685 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
686 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
687 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
688 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
689 a->cmpb(R7, R5, R6); // code[4] -> cmpb
690 a->popcntb(R7, R5); // code[5] -> popcntb
691 a->popcntw(R7, R5); // code[6] -> popcntw
692 a->fcfids(F3, F4); // code[7] -> fcfids
693 a->vand(VR0, VR0, VR0); // code[8] -> vand
694 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
695 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
696 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
697 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
698 a->tcheck(0); // code[12] -> tcheck
699 a->mfdscr(R0); // code[13] -> mfdscr
700 a->lxvd2x(VSR0, R3_ARG1); // code[14] -> vsx
701 a->ldbrx(R7, R3_ARG1, R4_ARG2); // code[15] -> ldbrx
702 a->stdbrx(R7, R3_ARG1, R4_ARG2); // code[16] -> stdbrx
703 a->vshasigmaw(VR0, VR1, 1, 0xF); // code[17] -> vshasig
704 a->blr();
705
706 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
707 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
708 a->dcbz(R3_ARG1); // R3_ARG1 = addr
709 a->blr();
710
711 uint32_t *code_end = (uint32_t *)a->pc();
712 a->flush();
713 _features = VM_Version::unknown_m;
714
715 // Print the detection code.
716 if (PrintAssembly) {
717 ttyLocker ttyl;
718 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
719 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
720 }
721
722 // Measure cache line size.
723 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
724 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
725 int count = 0; // count zeroed bytes
726 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
727 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
728 _L1_data_cache_line_size = count;
729
730 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
731 VM_Version::_is_determine_features_test_running = true;
732 // We must align the first argument to 16 bytes because of the lqarx check.
733 (*test)(align_up((address)mid_of_test_area, 16), 0);
734 VM_Version::_is_determine_features_test_running = false;
735
736 // determine which instructions are legal.
737 int feature_cntr = 0;
738 if (code[feature_cntr++]) features |= fsqrt_m;
739 if (code[feature_cntr++]) features |= fsqrts_m;
740 if (code[feature_cntr++]) features |= isel_m;
741 if (code[feature_cntr++]) features |= lxarxeh_m;
742 if (code[feature_cntr++]) features |= cmpb_m;
743 if (code[feature_cntr++]) features |= popcntb_m;
744 if (code[feature_cntr++]) features |= popcntw_m;
745 if (code[feature_cntr++]) features |= fcfids_m;
746 if (code[feature_cntr++]) features |= vand_m;
747 if (code[feature_cntr++]) features |= lqarx_m;
748 if (code[feature_cntr++]) features |= vcipher_m;
749 if (code[feature_cntr++]) features |= vpmsumb_m;
750 if (code[feature_cntr++]) features |= tcheck_m;
751 if (code[feature_cntr++]) features |= mfdscr_m;
752 if (code[feature_cntr++]) features |= vsx_m;
753 if (code[feature_cntr++]) features |= ldbrx_m;
754 if (code[feature_cntr++]) features |= stdbrx_m;
755 if (code[feature_cntr++]) features |= vshasig_m;
756
757 // Print the detection code.
758 if (PrintAssembly) {
759 ttyLocker ttyl;
760 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
761 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
762 }
763
764 _features = features;
765 }
766
767 // Power 8: Configure Data Stream Control Register.
768 void VM_Version::config_dscr() {
769 // 7 InstWords for each call (function descriptor + blr instruction).
770 const int code_size = (2+2*7)*BytesPerInstWord;
771
772 // Allocate space for the code.
773 ResourceMark rm;
774 CodeBuffer cb("config_dscr", code_size, 0);
775 MacroAssembler* a = new MacroAssembler(&cb);
776
777 // Emit code.
778 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
779 uint32_t *code = (uint32_t *)a->pc();
780 a->mfdscr(R3);
781 a->blr();
782
783 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
784 a->mtdscr(R3);
785 a->blr();
786
787 uint32_t *code_end = (uint32_t *)a->pc();
788 a->flush();
789
790 // Print the detection code.
791 if (PrintAssembly) {
792 ttyLocker ttyl;
793 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
794 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
795 }
796
797 // Apply the configuration if needed.
798 _dscr_val = (*get_dscr)();
799 if (Verbose) {
800 tty->print_cr("dscr value was 0x%lx" , _dscr_val);
801 }
802 bool change_requested = false;
803 if (DSCR_PPC64 != (uintx)-1) {
804 _dscr_val = DSCR_PPC64;
805 change_requested = true;
806 }
807 if (DSCR_DPFD_PPC64 <= 7) {
808 uint64_t mask = 0x7;
809 if ((_dscr_val & mask) != DSCR_DPFD_PPC64) {
810 _dscr_val = (_dscr_val & ~mask) | (DSCR_DPFD_PPC64);
811 change_requested = true;
812 }
813 }
814 if (DSCR_URG_PPC64 <= 7) {
815 uint64_t mask = 0x7 << 6;
816 if ((_dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
817 _dscr_val = (_dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
818 change_requested = true;
819 }
820 }
821 if (change_requested) {
822 (*set_dscr)(_dscr_val);
823 if (Verbose) {
824 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
825 }
826 }
827 }
828
829 static uint64_t saved_features = 0;
830
831 void VM_Version::allow_all() {
832 saved_features = _features;
833 _features = all_features_m;
834 }
835
836 void VM_Version::revert() {
837 _features = saved_features;
838 }